1. A method for managing time constraints in a circuit, the method comprising: creating an initial placement design in a circuit; determining, by one or more processors, whether a first criteria is met, wherein the first criteria comprises a design parameter at a first predefined threshold; in response to determining that a first criteria is met, initiating, by one or more processors, a first checkpoint procedure, wherein the first checkpoint procedure comprises a two-pass flow, in which: a first pass grouping is based on the location of a group of macros and clustering of the group of macros is iteratively performed until a distance parameter exceeds a predetermined threshold; and a second pass grouping is based on a time, wherein pin-list filtering is performed to generate a shortened pin list; determining, by one or more processors, whether a second criteria is met, wherein the second criteria comprises a second predefined threshold; and in response to determining that the second criteria is met, initiating, by one or more processors, a second checkpoint procedure, wherein the second checkpoint procedure comprises: gathering a list of arrival times (ATs) and a list of expected time of arrival (ETA) for the group of macros; performing pin-list filtering; and calculating an average and a standard deviation of the list of ATs and the list of ETA, wherein the second checkpoint procedure is executed after a final placement step when a set of design parameters are within a specific threshold; and wherein after an intermediate placement step, design iterations are performed to reach a final optimized stage, wherein the design iterations include: a detailed routability metrics evaluation, a buffering update, clocking and power related checks, and a fix-up of reliability issues.