1. A computer system comprising a processor that issues requests for data; a first memory chip and a second memory chip coupled to a memory bus, each memory chip having a plurality of banks, wherein a dead cycle is required on the memory bus between a first cycle driven by the first memory chip and a second cycle driven by the second memory chip; a memory controller coupled to the memory bus, the memory controller further comprising a read queue configured to store requests issued by the processor, the memory controller configured to service the requests for data by opening a particular bank, reading the particular bank, and closing the bank, the memory controller configured to control dead cycles on the memory bus as a function of a number of pending requests in the read queue, the memory controller configured to provide more than two memory access modes.