1. An integrated circuit (IC), comprising: a substrate; a logic layer formed on the substrate; a cross-point memory array formed directly above and in contact with the substrate, the cross-point memory array is comprised of a plurality of memory layers and includes X-lines, Y-lines, of which at least one Y-line includes groups of Y-line portions, each Y-line portion being arranged in parallel with other Y-line portions to comprise a group of the Y-line portions, and memory elements (ME's) disposed between a subset of the X-lines and the group of the Y-line portions; and a decoder configured to select a Y-line portion from the group of Y-line portions to access a subset of the ME's.