1. In a programmable logic device in a single integrated circuit package, a reconfigurable memory comprising: an inverter having an input and an output; a PMOS transistor having a gate coupled to the output of the inverter, a drain coupled to the input of the inverter and a source coupled to a power supply potential; an NMOS transistor having a gate coupled to the output of the inverter, a source coupled to a ground potential and a drain; an Erasable Programmable Read Only Memory (EPROM) coupling the PMOS transistor to the NMOS transistor; and a charge circuit for selectively programming the EPROM.