1. A method for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors; a shared memory; a shared communications bus; and a memory controller, said method comprising the following steps: subdividing said shared memory into independent regions and assigning each said region to one of said processors; executing said processors in a single cache coherence domain on said shared communications bus; intercepting and processing all memory access messages to detect if an address is outside of a memory region assigned to a processor in use; and aborting an executed memory access operation and resetting said processor when an address violation of one of said memory region has been detected.