1. A microprocessor comprising: a first addressable memory forming a data cache; a second addressable memory forming an instruction cache, the instruction cache being separate from the data cache; execution means for processing data received from the data cache in response to an instruction from the instruction cache; data interface means, coupled to the data cache and to the execution means, for independently controlling access to the data cache and for communicating data from the data cache to the execution means; and instruction interface means, coupled to the instruction cache and to the execution means, for independently controlling access to the instruction cache and for communicating instructions from the instruction cache to the execution means, the instruction interface means including: a counter for addressing the instruction cache; instruction address loading means, coupled to the counter, for storing a first address in the counter; and cache advance means for repetitively generating a non-address cache advance signal for incrementing the counter after the first address is stored in the counter, the counter being incremented once per cache advance signal, and the cache advance means operating independently of the instruction address loading means.