1. An apparatus, comprising: an extended address register including a plurality of configuration bits indicative of an offset and a size; an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits; a buffer configured to store data, the data including data intended to be stored in the storage area; and a memory control unit coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.