1. A processing system comprising: a plurality of shadow register sets; an interrupt vector generator, for generating an exception vector associating with an interrupt handler, when the processing system receives an interrupt; and shadow set mapping logic, coupled to both said plurality of shadow register sets, and said interrupt vector generator, for selecting one of said plurality of shadow register sets to be used by said interrupt handler; wherein said shadow set mapping logic is programmably provided with a correlation between said exception vector and said selected one of said plurality of shadow register sets.