1. A multi-core processor system, comprising: at least two processor cores, each of said at least two processor cores having a local LEVEL-1 cache including memory for caching data, and a tree communication structure physically interconnecting the multiple LEVEL-1 caches, the tree communication structure having at least two levels, wherein a first level of the two levels comprises the LEVEL-1 caches, and a second level of the two levels comprises at least one higher level cache having a higher level than the LEVEL-1 caches and including memory for caching data, wherein a plurality of memories for storing TAG information are associated to the memories for caching data of the LEVEL-1 caches, the TAG information referencing the data, wherein each of the memories for storing TAG information is physically located in a respective one of the LEVEL-1 caches.