1. A computer-implemented method for race logic analysis on an integrated circuit (IC) design, to aid IC chip designers to detect and correct errors in their circuits and hence produce reliable IC products. The race logic analysis method comprising: (a) detecting the concurrent invocation of HDL-defined system functions/tasks that may cause one or more static or global signals/registers in the IC circuit to be concurrently assigned or concurrently assigned and referenced, and render indeterminate values for those signals/registers; (b) detecting concurrently invocation of “un-related” process blocks in a the IC design that may cause one or more signals/registers to be concurrently assigned with different values, and hence render indeterminate values for those signals/registers; (c) detecting concurrently invocation or “un-related” process blocks in a the IC design that may cause one or more signals/registers to be concurrently assigned and being referenced by different process blocks, and render indeterminate values being read by the driven process blocks; (d) detecting, dynamically via an event-driven logic simulation, circular functions/tasks invocation that may cause the IC design operation to hang (deadlock); (e) detecting user-defined functions/tasks that invoke themselves recursively without termination, and hence render the IC design operation to hang (deadlock).