1. A monolithically integrated dual-dielectric cell (DDC) memory array, comprising: a substrate body of a first conductivity type; a plurality of m.n. DDC field-effect transistors arranged in m columns and n rows, each of said field-effect transistors having a substrate region of a second conductivity type formed in the substrate body, the substrate regions of transistors in a column being connected together and associated with column addresses X.sub.1 to X.sub.m, a drain region formed within each of said substrate regions, said drain regions of transistors in a column being connected together, a source region within each of said substrate regions, said source regions of transistors in a column being connected together as a bit line, and a gate electrode, said gate electrodes of transistors in a row being connected together as word lines and associated with row addresses Y.sub.1 to Y.sub.n ; a load transistor associated with each column for connecting the drain regions of the column to a supply voltage U.sub.3 ; decoding, logic and potential-selecting circuit means, disposed in at least one substrate well of the second conductivity type formed in the substrate body, responsive to binary code signals for assuming one of four operating modes corresponding to bitwise read (R), bitwise erase (E.sub.b), bitwise write (W) and matrix-wise erase (E.sub.m) and for providing an addressed word line with potentials of U.sub.R, U.sub.0, U.sub.3 or U.sub.0 respectively upon assuming the previously mentioned operating modes, for providing an addressed substrate region with potentials of U.sub.0, U.sub.3, U.sub.0 or U.sub.3 respectively upon assuming the previously mentioned operating modes, for providing all non-addressed word lines with potentials of U.sub.0, U.sub.2, U.sub.a or U.sub.0, respectively upon assuming the previously mentioned operating modes, and for providing all non-addressed substrate regions with potentials of U.sub.b, U.sub.1, U.sub.c or U.sub.3 respectively upon assuming the previously mentioned operating modes, wherein U.sub.3 - U.sub.0 approximately equals a gate voltage sufficient for shifting the field-effect threshold voltage of the DDC transistors and wherein EQU U.sub.1 - U.sub.0 approximately equals (U.sub.3 - U.sub.0)/3, EQU u.sub.2 - u.sub.0 approximately equals (2 (U.sub.3 - U.sub.0)/3, EQU u.sub.r - u.sub.0 is no greater than U.sub.1 - U.sub.0, EQU u.sub.a - U.sub.0 is no greater than U.sub.1 - U.sub.0, EQU u.sub.b - U.sub.0 is no greater than U.sub.1 - U.sub.0, and EQU U.sub.c - U.sub.0 is no greater than U.sub.2 - U.sub.0.