1. A processor comprising: a first register to reference a set of page tables, the set of page tables to provide a mapping of guest virtual addresses to guest physical addresses; a second register to reference a set of extended page tables to provide a mapping of guest physical addresses to host physical addresses; access logic to determine whether use of the set of extended page tables is enabled; address translation logic to access the set of page tables and the set of extended page tables to translate a guest virtual address to a guest physical address and to translate the guest physical address to a host physical address in response to a memory access request including the guest virtual address; a translation look-aside buffer (TLB) to cache guest virtual address to guest physical address translations and guest physical address to host physical address translations in corresponding TLB entries; and execution logic, in response to a TLB invalidate instruction, to invalidate a TLB entry associated with a guest physical address to host physical address translation, the TLB invalidate instruction to specify the guest physical address in an operand of the TLB invalidate instruction.