1. An extensible pipelined processor adapted for performing iterative calculations on a plurality of data, said processor having an extension instruction set associated therewith, and comprising: at least one multiply-accumulate stage having at least one accumulator associated therewith; at least one register window; at least one extension instruction provided within said extension instruction set, said at least one extension instruction being adapted to: (i) subtract a value present in said at least one accumulator from a multiple of a first one of said plurality of data; and (ii) preload said at least one accumulator with a second one of said plurality of data; and logic operatively connected to said at least one multiply-accumulate stage and adapted to write back the result of said subtraction to said register window.