1. A processor, comprising: an instruction cache configured to store at least a first instruction read from an external memory and a second instruction, the second instruction being dividable into a plurality of pieces, each piece being a micro instruction; a micro cache configured to store a plurality of third instructions corresponding to the plurality of micro instructions included in the second instruction; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, wherein the core performs the calculation using the first instruction from the instruction cache in a normal mode, and performs the calculation using the plurality of third instructions corresponding to the plurality of micro instructions provided from the micro cache in a micro instruction mode.