1. A sequential logic unit comprising: a data flip-flop having a data input, a clock input, and an output; a first data multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second data multiplexer having a first data input connected to the output of said data flip-flop, a second data input connected to said output of said first multiplexer, a control input, and an output connected to the data input of said data flip-flop; an output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first and second multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.