1. A data demodulation logic unit adaptable to multiple data modulation protocols for decoding data, comprising in combination: an arithmetic logic unit including an input, a plurality of registers and an output controllably operable to convert a base band signal, coupled to said input, to a demodulated data signal representing an estimate of decoded data at said output, a state machine embodied in electronic hardware, coupled to said arithmetic logic unit, said state machine operating in a mode to control said arithmetic logic unit and to select one or more of said plurality of registers for outputting to the output, said mode selectively corresponding to a data modulation protocol and an error correcting circuit coupled to the arithmetic logic unit for receiving the estimate of the decoded data from at least the one or more selected registers.