1. A method for sharing and re-using a voltage parameterized statistical timing model corresponding to a macro during timing analysis of an integrated circuit (IC) chip design provided with at least one voltage domain and at least one instance of the macro, the method comprising: a) using a computer, computing timings of said macro employing said macro's voltage parameterized statistical timing model; b) obtaining information of voltage domain for macro instantiation; c) dynamically updating results of said macro timing computations based on voltage domain conditions of said timing model and said voltage domain information of said macro instantiation; and d) using said updated timing results, performing said timing analysis of said IC chip design as part of design closure prior to manufacture.