1. A method for minimizing noise problems in a chip design, said chip design comprising at least one driver gate driving a victim net and sinks attached to said victim net, the method comprising the steps of: a) identifying noise at the inputs of the at least one driver gate and computing the noise at the output thereof, b) propagating the computed noise at the output to all the sinks attached to said victim net; c) identifying nets coupled to said victim net and signal transitions on said coupled nets, and computing the coupled noise for all the sinks attached to said victim net; d) adding the computed propagation noise to the computed coupled noise; e) iteratively repeating steps a) through d) until a latch is reached; and f) determining if the noise at the latch input overlaps a signal clock, said overlap being indicative of a chip failure.