1. A programmable sequential logic array mechanism for performing logical operations and solving logical equations and comprising: an input random access storage array having addressable plural-bit sotrage locations for storing input control words for testing for different input signals conditions; input circuitry for receiving a plurality of binary input signals and for receiving input control words from the input storage array and producing binary truth signals indicating the states of agreement between the input signal conditions and the test conditions represented by the input control words; a plurality of binary output bistable circuits for providing a plurality of binary output signals; an output random access storage array having addressable plural-bit storage locations for storing output control words for controlling the states of the binary output bistable circuits; address generating circuitry for sequentially generating a series of different storage addresses and for supplying each such address to the address circuitry of both the input and the output storage arrays, for sequentially reading out the desired control words; and control circuitry connecting the input circuitry with binary output bistable circuits and responsive to the truth signals produced by the input circuitry for enabling the binary output bistable circuits to respond to selected output control words.