1. In a digital computing system including a central processing unit (CPU) capable of writing data to and reading data from a random access memory (RAM), which RAM is capable of storing and putting out data as a plurality of digitally addressable words under control of said CPU, and which CPU and RAM are connected by a common data bus for transfer of data words and a common address bus for transfer of address words, an improved data access limitation and protection subsystem for protecting data stored within software selectable boundaries of said RAM from unauthorized access by selective transformation and substitution of data and address words as enabled upon detection of a predetermined transformation control sequence in which a unique operation code word is followed by memory address upper and lower boundary words defining said boundaries, said subsystem comprising: operation code detector means connected to said CPU and to said data bus for detecting said unique operation code word stored in said RAM and fetched by said CPU and for putting out an operation-code-present signal when said unique operation code word is detected; address latch means connected to said operation code detector means and to said data bus for storing an upper boundary address word and a lower boundary address word put out by said CPU when said address latch means is enabled by said operation-code-present signal from said operation code detector means; address comparator means connected to said CPU, to said address bus and to said address latch means for comparing digital addresses subsequently put out by said CPU with said stored boundary addresses and for putting out a transform enable signal upon determination that a said address put out by said CPU lies within a range defined by said boundary addresses as the result of said comparison; address transformation means connected to said address bus between said RAM and said CPU and responsively connected to said address comparator means and enabled by said transform enable signal for transforming said digital addresses lying between said boundary addresses into different digital addresses in accordance with a predetermined address word transform; bi-directional data transformation means connected to said data bus between said RAM and said CPU and responsively connected to said address comparator means and enabled by said transform enable signal for encoding data words as said words are written to said RAM by said CPU and for decoding bytes of data as said words are read from said RAM by said CPU in accordance with a predetermined data word transform; whereby whenever said transform enable signal is put out by said address comparator means a word of data written by said CPU to said RAM is encoded by said data transformation means, and a word of data fetched by said CPU from said RAM is decoded by said data transformation means, and the digital address location to which said word of data is written and from which said word of data is fetched is different than the untransformed digital address generated and put out by said CPU.