1. An m-of-n flash-type threshold gate comprising: a plurality of n input signal lines, each having an asserted state and a NULL state; a FLASH input signal line having a first state and a second state; an output signal line having an asserted state and a NULL state; and a hysteresis circuit switching the output signal line from the NULL state to the asserted state when (i) each and every combination of a number m of input signal lines change from the NULL state to the asserted state, m being less than, and (ii) the FLASH input is in the first state; said hysteresis circuit further holding the output signal line in an asserted state until the FLASH input line changes from the first state to the second state.