1. A data processing apparatus, comprising: a processor core for executing instructions from any of a plurality of instruction sets; a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution; prediction logic for predicting which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within said memory from which a next instruction should be retrieved; the prediction logic further being arranged to predict whether the prefetched instruction will additionally cause a change in instruction set, and if so to cause an instruction set identification signal to be generated for sending to the processor core to indicate the instruction set to which said next instruction belongs.