1. A method for transmitting data to a memory to enable pipelined synchronization of a cache, comprising: storing data from a plurality of write operations in one or more cachelines of said cache; combining said write operations of an identical cacheline address into a combined write operation; flushing said data in said one of more cachelines to said memory based on said combined write operation, said flushing including pushing one or more synchronization events to said memory with a no-block bit set when there are no events in a pending cache FIFO; and concurrently updating said one or more cachelines with additional data during said flushing.