1. A method for operating of NAND-like dual charge retaining transistor NOR flash memory cell comprises: erasing selected NAND-like dual charge retaining transistor NOR flash memory cell to an erased threshold voltage level; selectively programming a first charge retaining transistor of the NAND-like dual charge retaining transistor NOR flash memory cell to a first programmed threshold voltage level; selectively programming the second charge retaining transistor of the NAND-like dual charge retaining transistor NOR flash memory cell to a first programmed threshold voltage level; designating the paired word line page of NAND-like dual charge retaining transistor NOR flash memory cell is to be retaining a first data state, when the first charge retaining transistor is programmed to the first programmed threshold voltage level and a second charge retaining transistor remains at the erase threshold voltage level; designating the paired word line page of NAND-like dual charge retaining transistor NOR flash memory cell is to be retaining a second data state, when the first charge retaining transistors remains at the erase threshold voltage level and the second charge retaining transistor is programmed to the first programmed threshold voltage level; selectively programming the second charge retaining transistor of the NAND-like dual charge retaining transistor NOR flash memory cells to a second programmed threshold voltage level; designating the paired word line page of NAND-like dual charge retaining transistor NOR flash memory cells to be retaining a third data state, if the first charge retaining transistor is programmed to the first programmed threshold voltage level and the second charge retaining transistor is then programmed to the second programmed threshold voltage level; and designating the paired word line page of NAND-like dual charge retaining transistor NOR flash memory cells is to be retaining a fourth data state, if the first charge retaining transistor remains at the erase threshold voltage level and the second charge retaining transistor is programmed to the second programmed threshold voltage level.