1. A method of ordering memory access by an instruction cache of a central processing unit on a global memory device comprising the steps of: extracting a signal list of a link map file in the global memory device; obtaining memory access traces relating to executed tasks from the signal list; identifying memory locations accessed in the global memory device from the access traces; determining a correlation value for each pair of memory locations accessed in the global memory device, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations; reordering accessed memory locations within the global memory device as a function of the determined correlation values; and modifying an executable file accessing the global memory device, the executable file optimizing the memory layout when accessing the global memory device.