1. A method for vector processing in an active memory device that includes memory and a processing element, the method comprising: decoding, in the processing element, an instruction comprising a plurality of sub-instructions to execute in parallel; determining an iteration count to repeat execution of the sub-instructions in parallel; repeating execution of the sub-instructions in parallel for multiple iterations, by the processing element, based on the iteration count; and accessing multiple locations in the memory in parallel based on the execution of the sub-instructions.