1. A data processor architecture comprising: an integrated circuit refreshable memory for storing computer operands in response to a memory refresh signal; an integrated circuit read only memory for storing computer instructions; and execution means for executing the computer instructions stored in said read only memory, said execution means including processing means for processing the computer operands stored in said refreshable memory in response to the execution of at least one of the computer instructions stored in said read only memory and refresh means for generating the memory refresh signal in response to the execution of at least one of the computer instructions stored in said read only memory.