1. A method for designing a system on a target device, comprising: synthesizing a logic representation of a processing channel from a description of the processing channel in hardware description language (HDL) according to a first set of constraints; synthesizing a logic representation of a redundant processing channel, functionally equivalent to the processing channel, from the description of the processing channel in HDL according to a second set of constraints, wherein the first set and the second set of constraints include synthesis constraints; and placing and routing the processing channel and redundant processing channel, wherein the synthesizing is performed by a synthesis unit.