1. A processor, comprising: an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on a plurality of data elements stored in a storage location indicated by a first source operand, the instruction schedule/dispatch unit to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand; a plurality of processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner; and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.