1. An LSI design support device comprising: a computer, wherein the computer is configured to: receive input of a netlist of a circuit including a logic gate and an FET; create a flow-through condition function in the netlist, by obtaining a Boolean expression indicative of function of a circuit of which an output is a source terminal or a drain terminal of a grounded FET; create a flow-through condition determining Boolean expression, by extracting from the netlist a Boolean expression indicative of function of a partial netlist which supplies an input to the flow-through condition function; obtain the flow-through condition function and the flow-through condition determining Boolean expression, by performing logic modeling in which, in the netlist, a power supply terminal is replaced with a logical value 1, a P-type FET is replaced with a logic gate which outputs to a drain a logical value inputted into a source when a logical value 0 is inputted to a gate, and an N-type FET is replaced with a logic gate which outputs to a source a logical value inputted into a drain when a logical value 1 is inputted to a gate; and determine occurrence or non-occurrence of the logic state of the netlist which generates a steady-state flow-through current in a grounded FET included in the netlist, by determining existence of the conditions in which a logical value 1 is outputted from the flow-through condition function, based on the result of having degenerated the flow-through condition determining Boolean expression with the logical equivalence maintained.