1. A circuit operable to perform multiplication, shifting, and rotation, the circuit comprising: a multiplier implemented using hard-logic on a programmable chip, the multiplier including a first multiplier input, a second multiplier input, and a multiplier output, wherein the first multiplier input provides a first operand and the second multiplier input provides a second operand; multiplexer circuitry connected to the multiplier, the multiplexer circuitry including a first multiplexer input, a second multiplexer input, a third multiplexer input, and a multiplexer output, the third multiplexer input a bitwise OR of the first multiplexer input and the second multiplexer input, wherein the first multiplexer input includes the most significant bits associated with the multiplier output and the second multiplexer input includes the least significant bits associated with the multiplier output.