1. An apparatus, comprising: a memory; and arbitration circuitry coupled to or comprised in the memory, the arbitration circuitry comprising: pointer circuitry configured to receive a sequence of memory access requests for the memory and maintain a write pointer that indicates completed write memory access requests of the sequence, wherein the sequence of memory access requests is configured to access locations associated with entries in a data structure stored in the memory; interlock circuitry that is configured, before receiving any memory access requests that are included in the sequence, with interlock information that specifies memory access constraints for write pointer values for the sequence of memory access requests wherein the memory access constraints are pre-determined based on operations to be performed on data stored in the data structure, wherein the constraints indicate ordering dependencies between ones of the requests in the sequence of memory access requests; and hazard circuitry configured to grant the sequence of memory access requests subject to the memory access constraints, including granting ones of the memory access requests in response to write pointer values maintained by the pointer circuitry meeting one or more values specified by the interlock information for corresponding ones of the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.