1. A computer-implemented method of monitoring processor performance by a performance monitor hardware unit, the computer-implemented method comprising actions of: receiving, within the performance monitor hardware unit, a plurality of performance event signals, the plurality of performance event signals indicating a current full event state of the processor at a particular time; counting only a selected subset of the plurality of performance event signals by a plurality of hardware counters included in the performance monitor hardware unit; intercepting, by a hardware event register included in the performance monitor hardware unit, the plurality of performance event signals; outputting, by the hardware event register, the selected subset of the plurality of performance signals to the plurality of hardware counters; storing current values, of the plurality of performance event signals together as a single unit, in the hardware event register as current contents upon each occurrence of a clock cycle, the single unit being a full set of available performance event signals that indicate the current full event state of the processor at the particular time; and overwriting current contents of the hardware event register upon each clock cycle.