1. A networking application processor, comprising: an input socket configured to receive data associated with a processing stage of a data packet, each processing stage of the data packet being associated with one network protocol from a plurality of network protocols in the data packet; a memory for storing instructions; circuitry configured to access data structures associated with the received data and with the corresponding network protocol, the circuitry configured to access data structures and enabling single clock cycle access of an operand from memory during consecutive clock cycles; an arithmetic logic unit (ALU); and circuitry for aligning operands to be processed by the ALU, the circuitry for aligning operands causing the operands to be aligned by a lowest significant bit, wherein the circuitry for aligning the operands supplies an extension to the operands to allow the ALU to process different size operands.