1. A memory array comprising: a substrate; a plurality of access transistors over the substrate, each access transistor comprising a channel region between first and second electrodes, the channel region, first electrode and second electrode being vertically stacked over the substrate, the channel region being in contact with a top surface of the first electrode and completely isolated from the substrate by the first electrode; and a resistance variable material and a first portion of metal-chalcogenide material over and electrically coupled to a plurality of second electrodes of respective access transistors and forming a plurality of resistance variable memory elements, each accessed by the respective access transistor, wherein the channel region comprises a second portion of the metal-chalcogenide material.