1. An apparatus comprising: a polynomial register having a plurality of bits, wherein the polynomial register is configured to store a user-defined polynomial; a first bus; a second bus; a transceiver that is coupled to the first bus, the second bus, and the polynomial register, wherein the transceiver includes: a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial; and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.