1. A pipelined microprocessor, comprising: instruction decode logic; a program counter for indicating a current location in an instruction sequence; instruction fetch logic for fetching an instruction from the current location in the instruction sequence; a virtual program counter; and a virtual instruction expansion store; wherein if the instruction fetch logic determines that the fetched instruction is a virtual instruction, the instruction fetch logic is adapted to: hold the virtual instruction in the instruction fetch logic; maintain the program counter at the address of the virtual instruction; pass one of a plurality of instructions obtained from a virtual instruction expansion store to the instruction decode logic; increment the virtual program counter to select and pass a next instruction from the plurality of instructions to the instruction decode logic until either each of the plurality of instructions has executed or an exception occurs; and after the plurality of instructions have been executed or an exception occurs, advance the program counter.