1. A method for reducing a number of inverting logic gates, and relocating inverting logic gates to a boundary of the network, in a logic network design, comprising the steps of: a) identifying, by a computer system analyzing the network design, a set of nodes in the network having diverging branches defining fan-out cones of the respective nodes; b) identifying, by the computer system, ones of the nodes, from among the set of nodes, wherein the divergent branches of the respective ones of the nodes do not reconverge within the network; and c) selecting, by the computer system, the nodes in the network identified in step b) as candidate nodes for choosing among to select logical phase assignments of network outputs within the respective fan-out cones, wherein the selected logical phase assignments result in removal of inverting gates from the network, and relocation of inverting gates to a boundary of the network, so that at least an interior portion of the network may be implemented in dynamic logic circuitry.