1. A test apparatus that tests a device under test, comprising: a main memory that stores a test instruction stream determining a test sequence for testing the device under test; a sequence cache memory that caches the test instruction stream; a transfer section that reads the test instruction stream stored on the main memory and writes the read stream into the sequence cache memory in accordance with a described sequence; a pattern generating section that sequentially reads and executes instructions from the test instruction stream cached on the sequence cache memory and outputs a test pattern corresponding to the executed instruction; and a test signal output section that generates a test signal according to the test pattern and supplies the generated signal to the device under test, wherein the transfer section overwrites the instruction read from the main memory on a space area on the sequence cache memory or an area on which executed instructions are stored and prohibits overwriting the read instruction on an area on which instructions in a predetermined range is stored, the instructions being located in the predetermined range forward from a final instruction among the executed instructions according to the described sequence.