1. A system including at least a first performance monitoring unit (PMU) and a second performance monitoring unit (PMU) for monitoring performance of events occurring in a multiprocessor system, said multiprocessor system comprising a plurality of processor units, each processor unit for generating signals representing occurrences of events at said processor unit, each processor unit being associated with a single one of a plurality of functional groups, said system comprising: a first plurality of performance counters, each performance counter of the first plurality of performance counters for counting signals representing occurrences of events from one or more processor units associated with only a first one of the functional groups; a first plurality of input devices, each input device of the first plurality of input devices for receiving said event signals from one or more processor units associated with the first functional group, said first plurality of input devices programmable to select event signals for receipt by one or more of said first plurality of performance counters for counting; a second plurality of performance counters, each performance counter of the second plurality of performance counters for counting signals representing occurrences of events from one or more processor units associated with only a second one of the functional groups; and a second plurality of input devices, each input device of the second plurality of input devices for receiving said event signals from one or more processor units associated with the second functional group, said second plurality of input devices programmable to select event signals for receipt by one or more of said second plurality of performance counters for counting; wherein each PMU is shared between multiple processor units.