1. In a data processing system which includes a central processing unit capable of operation in one of a plurality of interrupt level states and having an addressing means providing virtual addresses, and which also includes a memory unit with a plurality of locations each addressable by a real address, the improvement comprising: means responsively coupled to said central processing unit and said memory unit for translating virtual addresses to real addresses for addressing said memory unit having a plurality of internal conversion tables which are loaded by said central processing unit to enable said translating means to translate virtual addresses to real addresses wherein said translating means makes such translation in response to a request from said central processing unit to access said memory unit at a real address corresponding to a virtual address generated by said addressing means; means responsively coupled to said central processing unit and said plurality of internal conversion tables for transferring a binary code representing said permitted interrupt level state to said plurality of internal conversion tables; means responsively coupled to said transferring means and said plurality of internal conversion tables for storing said binary code representing said permitted interrupt level state wherein said storing means stores said binary code whenever said plurality of internal conversion tables are loaded by said central processing unit; means responsively coupled to said storing means for accessing said binary code representing said permitted interrupt level state; means responsively coupled to said accessing means and said central processing unit for determining whether said binary code representing said permitted interrupt level state corresponds with said one of said plurality of interrupt level states of said central processing unit wherein said determining means makes such determination concurrently with the translation by said translating means of said virtual address to said real address; and means responsively coupled to said determining means and said translating means for inhibiting the translation of said virtual address to real address within said means for translating virtual addresses to real addresses if said determining means determines that said binary code representing said permitted interrupt level state does not correspond with said interrupt level state of said central processing unit.