1. A processing device, comprising: a top level router comprising a plurality of high speed communication interfaces to communicate data to other devices external of the processing device; a device controller coupled to the top level router to control operation of the top level router, the device controller comprising a microcontroller and a device controller memory space; and a plurality of clusters of processing engines, each cluster having a cluster controller, a cluster memory and a plurality of processing engines, each cluster memory comprising a memory controller and each processing engine comprising an engine memory and an engine core, wherein the device controller memory space, the cluster memory of all clusters of the processing device and the engine memory of all processing engines form a uniform address space on the processing device; wherein the microcontroller of the device controller, each cluster controller, the memory controller of each cluster memory and each processing engine are configured to address any memory location within the uniform address space using a packet that contains a single destination address in a header of the packet.