1. A digital system comprising: a plurality of processors; a plurality of private level one (L1) caches, each associated with a respective one of the plurality of processors; a shared level two (L2) cache having a plurality of segments per entry connected to transfer a data segment to each private L1 cache; a level three (L3) physical memory connected to provide a plurality of data segments to the shared L2 cache, wherein the shared L2 cache is operable to request transfer of a first plurality of segments in response to a first miss in a first private L1 cache; and wherein the shared L2 cache is operable to stop transferring the first plurality of segments and to start transferring a second plurality of segments in response to a second miss in a second private L1 cache.