1. A method of automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues comprising: identifying a set of target regions and a set of reference regions from a design layout; identifying individual clips in the set of reference regions and the set of target regions; clustering the individual clips by layout pattern similarity to generate a reference baseline of layout patterns from the set of reference regions including determining a first frequency of reference layout patterns in the set of reference regions; clustering the individual clips by layout pattern similarity from the set of target regions to determine a second frequency of target layout patterns in the set of target regions; comparing the second frequency of target layout patterns in the set of target regions to the first frequency of reference layout patterns in the reference baseline; based on the comparison, identifying candidate layout patterns from the set of target regions for further analysis; determining whether any of the candidate clip patterns caused a performance issue in the target region; and upon a positive determination, correcting the candidate layout pattern to correct the performance issue.