1. A pipelined microprocessor configured for long operand instructions, the microprocessor comprising: a memory unit; a load-store unit coupled to the memory unit, the load-store unit including: a data formatter, the data formatter for receiving information from the memory unit and including an operand selector and a shift register portion; and an execution unit coupled to the load-store unit and receiving operand information there from, the execution unit including output latches coupled to a storage location within the execution unit for storing output information from the execution unit; wherein the shift register portion includes a first section, a second section, and a recovery selector, the first section including a first input multiplexer and a first buffer and the second section including a second input multiplexer and a second buffer; wherein an output of the second buffer is coupled to an input of the first input multiplexer and an output of the first buffer is coupled to an input to the recovery selector.