1. A method of generating a length matrix for register transfer level code comprising steps for: receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library; generating a connectivity matrix for the plurality of compile units; generating a priority list of interconnections from the connectivity matrix; generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix; and generating as output at least one of the connectivity matrix and the placement coordinates.