1. A single plane dynamic decoder for applying a logical expression to a plurality of input signals to produce an "on" or "off" state at defined output nodes, the decoder comprising a number of rows wherein a typical row comprises (a) means connected between a first potential and a first node for charging the first node; (b) means connected between a second potential and a second node for discharging the second node; and (c) a plurality of series-connected switches connected between the first node and the second node and defining intermediate nodes at their respective interconnections, each of the switches being connected to receive a corresponding one of the input signals such that the switches are enabled or disabled thereby, the charging means being connected to receive a clock signal such that the charging means is enabled by a first clock phase and is disabled by a second clock phase, the discharging means being connected to receive the clock signal such that the discharging means is enabled by the second clock phase and disabled by the first clock phase, whereby the first node is precharged to the "on" state when the charging means is enabled and the second node is discharged to the "off" state when the discharging means is enabled.