1. A flash memory comprising: a plurality of cells; at least one microcontroller to selectively program a first number of said cells at a time or a second number of cells at a time, said first and second numbers being different; a counter and a verify block coupled to said counter; a combinatorial portion to generate a control flag to select the first or second number of cells; a charge pump; and a register having a second parallelism corresponding to a driving capability value of the charge pump according to the relation: n=Icharge_pump/Icell wherein Icharge_pump is a maximum value of the current which can be supplied by the charge pump, and Icell is a value of the current absorbed by a memory cell during a programming.