1. A combined central processing unit (CPU) and data entering and interrogating device comprising, in combination: a CPU having a plurality of elements comprising at least an arithmetic logic unit (ALU), a register file, a plurality of data buffers, an execution and addressing unit, and instruction and data cache, and a memory controller; a data entering and interrogating device integrally coupled to and located within said CPU comprising: selection means having connections to all of said plurality of elements within said CPU for selectively choosing each of said elements for interrogation of all data contained within each of said elements; data control means connected to said selection means for controlling data flow into and out of each of said elements for selectively supplying data into and receiving data out of each of said elements; and pausing means connected both to said selection means and to said data control means for temporarily stopping operation of said CPU to selectively permit interrogation of each of said elements and data flow into and out of each of said elements without destroying any of said data contained within each of said elements and for allowing said CPU to resume operation once said interrogation of said elements is completed; said data entering and interrogating device being substantially independently dedicated to said CPU.