1. A memory device comprising: a memory array having stored data and a serial output; an address counter that generates a serial address signal that sequentially generates addresses corresponding to stored data in the memory array; an address multiplexer having a first input coupled to an external address bus and a second input coupled to the serial address signal, the address multiplexer selecting either the first or second inputs in response to a state of a select signal; and a data multiplexer coupled to receive stored data from the memory array and an input address from the address multiplexer, the data multiplexer adapted to output either randomly accessed stored data or sequentially accessed stored data in response to the input address and state of the select signal.