1. A system, comprising: a plurality of cryptographic modules to process a plurality of incoming packets, each cryptographic module comprising a systolic array configured to perform cryptographic processing for at least a portion of the incoming packets, wherein the systolic array comprises at least one field-programmable gate array (FPGA), and further wherein each of the plurality of incoming packets is received from one of a plurality of entry ports, each packet includes a key tag to identify at least one key associated with the packet, and each packet further includes an entry port tag to identify its entry port; and at least one programmable input/output interface configured to receive the plurality of incoming packets, and route each packet to one of the cryptographic modules for encryption processing using at least one key selected based on the key tag for the packet, the encryption processing to provide a plurality of encrypted packets for sending to a data storage, and wherein the programmable input/output interface is further configured to, when one of the encrypted packets is retrieved from the data storage, use the respective entry port tag to route the retrieved packet back to its entry port.