1. A data processing circuit, wherein the data processing circuit comprises: an increased iteration enable signal; a first detector circuit, wherein the first detector circuit is operable to receive a data set and performs a data detection on the data set to provide a detected data set; a data decoding circuit, wherein the data decoding circuit is operable to receive a derivative of the detected data set and to perform a decoding process to provide a decoded data set; and wherein the decoded data set is provided to a second detector circuit based at least in part on an assertion level of the increased iteration enable signal.