1. A system that facilitates programming memory utilizing multi-level, multi-bit memory cells, comprising: a translation component that maps an element pair encoded using a first set of levels to a second set of levels so as to reduce the occurrence of potentially discordant element pairs, the number of levels in the second set is greater than the first set, the translation component replaces an unprogrammed element with a high threshold voltage level of the second set; and a program component that programs at least one element of a multi-bit memory cell based upon the mapped element pair.