1. A computer system employing a pipeline operation wherein the pipeline is driven by a high clock frequency higher than a low clock frequency by which a critical path instruction in processing data can be executed correctly, comprising: a high frequency ALU driven by a pipeline clock frequency, a low frequency ALU driven by a low clock frequency lower than the pipeline clock frequency, by which low clock frequency the critical path instruction can be executed correctly, wherein if the high frequency ALU can execute an instruction correctly, the execution result of the high frequency ALU is outputted as an execution result of a pipeline execution stage, if the high frequency ALU can not execute the instruction correctly, the execution result of the low frequency ALU is outputted as an execution result of the pipeline execution stage.