1. A method of programming a programmable logic device (PLD) comprising: (i) invoking an in-system programmable (ISP) mode in the PLD; (ii) determining whether a bit at a current address is an output enable bit; (iii) programming the bit if the bit is other than an output enable bit; (iv) choosing another address; (v) repeating steps (ii) through (iv) until all bits, other than output enable bits, are programmed; and (vi) programming the output enable bits.