1. A microprocessor having a macroinstruction set in its macroarchitecture that includes a macroinstruction that instructs the microprocessor to perform a read/modify/write operation on an operand in memory, the microprocessor comprising: an instruction translator, configured to translate the macroinstruction into exactly three microinstructions to perform the read/modify/write operation on the memory operand, wherein the three microinstructions are first, second, and third microinstructions; wherein the first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location; wherein the second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result; wherein the third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction; a first execution unit, configured to receive the first microinstruction, to responsively load the memory operand into the microprocessor from the memory location; and a second execution unit, configured to also receive the first microinstruction, to responsively calculate the destination address of the memory location, wherein the first and second execution units are distinct execution units within the microprocessor.