1. A content addressable memory, comprising: at least one tag input; at least one random access memory; circuitry to: perform multiple read operations of the at least one random access memory for multiple, different ones of the read operations specifying an address based on different subsets of tag bits; and digital logic circuitry coupled to the at least one random access memory, the circuitry including digital logic gates to determine whether a lookup tag matches a subset of the different subsets of tag bits.