1. A NOR flash memory device comprising: a cell array including banks each composed of sectors, each sector being constructed of memory cells coupled to wordlines and bitlines; a row selector to designate one of the wordlines in each bank in response to a row address; a column selector to designate bitlines in a unit of a predetermined number in each bank in response to a column address; a data input buffer to receive and hold program data bits in the unit of the predetermined number or less; and a program driver to contemporaneously apply a program voltage to the designated bitlines in response to the program data bits held in the data input buffer.