1. A multi-dimensional parallel storage device assembled of a number N of storage elements, comprising a number N of address-computing circuits assigned to respective storage elements, each address-computing circuit including a circuit means A for recursive computation of a storage element for a distinguished array point for isotropic storage function after time point of shifting a memory window, said circuit means A having a plurality of inputs for receiving data pertaining to coordinate changes in a multi-dimensional storing array, and further including a plurality of outputs, a circuit means B for recursive address computation of a distinguished array point for isotropic addressing functions, said circuit means B having a plurality of inputs connected to the inputs of said circuit means A and further including a plurality of outputs; an interpreting circuit C for isotropic storing functions for determining a distance vector of an array point which is independent from the position of window and for which the address computation is made, said interpreting circuit including storage means for storing ascertained distance vectors from the distinguished array point, said interpreting circuit having an input connected to the output of said circuit means A an input for coded data of the considered window and further including a plurality of outputs for delivering values of said distance vectors x.sub.1,. .. , x.sub.n where n is the dimension of the array of points; and a circuit means D for determining an address of an arbitrary storage element pertaining to the address computation circuit, said circuit means having a plurality of inputs connected to the outputs of said interpreting circuit and to the outputs of said circuit means B, and an output for delivering the computed address.