1. A system comprising: a plurality of registers, wherein the plurality of registers comprises: a first set of registers directly accessible by a device; and a second set of registers indirectly accessible by the device solely via the first set of registers, wherein the first set of registers includes a first subset of registers that comprise a third register configured to enable indirect access to the second set of registers by the device based upon stored values in both a first register and a second register of the first subset of registers, wherein the first register, the second register, and the third register are independently accessible by the device separate from one another, wherein the first set of registers includes a second subset of registers different from the first subset; an access logic circuit configured to manage access to the first set of registers and the second set of registers, wherein the access logic circuit is configured to write to the first register, wherein the second register of the first set of registers is automatically set to a predetermined value when the access logic circuit writes to the first register; and a pattern-recognition processor, wherein the second set of registers are configured to store information related to the pattern-recognition processor, wherein the pattern-recognition processor comprises: a row decoder circuit having an input configured to receive a data stream to be searched; and a plurality of feature cells coupled to the row decoder circuit, wherein each of the plurality of feature cells comprises a plurality of memory cells, each memory cell addressable by a conductor coupled to an output of the row decoder circuit.