1. A processing network comprising: a processing circuit having a programmable parser including one or more parsing engines that parse data packets received by the processing circuit; and a parser compiler stored on a non-transitory computer-readable memory and communicatively coupled with each of the parsing engines, wherein the parser compiler is configured to generate values based on a parser configuration file that when programmed into a memory associated with each of the parsing engines enables the parsing engines to identify each of a set of different combinations of packet headers represented by the parser configuration file.