1. A microprocessor system comprising; a first processor, a second processor, means intercoupling the first and second processors including an address bus and a data bus associated with the first processor and an address bus and a data bus associated with the second processor, a first memory associated with the first processor and coupled thereto via the first processor address bus and data bus, a second memory associated with the second processor and coupled thereto via the second processor address bus and data bus, a third memory associated with the first processor and comprising a read-only memory for storing a boot strap control program, power-up reset circuit means including means for generating a reset signal and means coupling the reset signal to the first processor causing first processor instruction operation in accordance with the boot strap control program to load the operating system into the first memory, means responsive to said program after loading of the operating system to terminate operation in accordance with the boot strap control program and commence operation in accordance with the operating system, and control means responsive to a first operating system type code for establishing control of said microprocessor system in said first processor and holding said second processor in an inactive state, and responsive to a second operating system type code for transferring control of said microprocessor system to said second processor.