1. A method comprising: causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time, wherein causing the plurality of shader programs of the common shader program type to be loaded comprises: loading a first shader program of the common shader program type into the on-chip shader program instruction memory; determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory; loading a second shader program of the common shader program type into one of the one or more ranges of available memory space; determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program: determining a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and evicting the least frequently used shader program from the on-chip shader program instruction memory, wherein the on-chip shader program instruction memory comprises an instruction cache from which a shader unit fetches instructions during execution of at least one of the plurality of shader programs.