1. A gate-array chip comprising: a semiconductor bulk; a plurality of groups of basic-cell arrays arranged in parallel on said semiconductor bulk of said gate-array chip, each of said groups of basic-cell arrays including a plurality of basic-cells; a plurality of impurity regions provided for each of said groups of basic-cell arrays, formed on said semiconductor bulk and in regions between each of said groups of basic-cell arrays, first predetermined ones of said impurity regions and first predetermined ones of said groups of basic-cell arrays located on either side of said predetermined ones of said impurity regions connected to form input/output circuits; a first cutting region, formed between second predetermined ones of said basic-cell arrays, for enabling said plurality of groups of basic-cell arrays on said gate-array chip to be cut into smaller plurality of groups of basic cell arrays to form chips smaller than said gate-array chip; and first input/output pad forming regions formed adjacent to said first cutting region.