1. A decompressor having compressed scan inputs that accept compressed scan patterns for generating decompressed scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said decompressor comprising: a) one or more shift registers directly connected to said compressed scan inputs, said one or more shift registers having shift register outputs; and b) a combinational logic network connected to said compressed scan inputs and said shift register outputs for connecting the outputs of said combinational logic network to selected scan inputs of all said scan chains.