1. A high-level synthesis device, which converts a behavior description file describing a function of an integrated circuit using a high-level language without timing description, into a hardware description file describing the integrated circuit including timing description, comprising: a processor; a high-level synthesis unit configured to convert the behavior description file having a functional portion describing the function and a control portion controlling timing, into a first hardware description file; a variable extraction unit configured to extract, from the behavior description file, a function including a latency extended variable in the functional portion; a loop information generation unit configured to extract a description of a loop included in the extracted function, and generate loop information including a loop count of the loop in the function; a static latency extraction unit configured to generate a static latency for each element of the extracted function; a latency calculation circuit generation unit configured to generate a second hardware description file describing a latency calculation circuit which generates the latency information based on the loop count and static latency; and an insertion unit configured to insert the second hardware description file into the first hardware description file to generate a third hardware description file.