1. A non-volatile memory device, said memory device including: a matrix of memory cells, each memory cell being individually programmable to at least one first logic level and individually erasable to a second logic level; a partition circuit for logically subdividing the matrix into a plurality of subspaces, each subspace comprising at least one respective memory cell; a selection circuit for selecting a subspace; an operative circuit for performing an operation on all the memory cells of the selected subspace, the operation including a verify operation, said verify operation being adapted to verify whether all the memory cells of the selected subspace are to a same selected logic value; and a circuit for dynamically modifying the number of memory cells included in each subspace.