1. A method, comprising: generating a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block; generating a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, and a partially flattened netlist; and generating, via a 1×N compiler, a logical representation via the physical design representation.