1. A digital signal processing apparatus for processing a serial stream of digital signal samples of a plurality of “n” number of different signals, said apparatus comprising: a digital signal processor (DSP) configured to perform a digital signal processing algorithm on said digital signal samples of said plurality of signals as said stream of digital signal samples is provided, after a first delay, to a delay input of said DSP; a delay memory comprising “n” number of memory cells each corresponding to one of said “n” number of signals, each said memory cell having sufficient storage to store one of said digital signal samples, wherein said delay memory further comprises a digital signal sample input, a signal-number-in input, a signal-number-out input, and a digital signal sample output connected to said delay input of said DSP, and wherein said delay memory is configured to: store in one of said memory cells identified by a signal identifier at said signal-number-in input one of said digital signal samples at said digital signal sample input, and output at said digital signal sample output one of said digital signal samples stored in one of said memory cells identified by a signal identifier at said signal-number-out input; and a clock connected to said DSP and said delay memory, said clock configured to operate at a rate equal to or greater than a sum of frequencies of each of said “n” number of different signals.