1. A semiconductor integrated circuit design supporting apparatus, comprising: latency adjusting means for calculating, based on a latency value of each module acquired from one of HDL and a synthetic log obtained from a behavioral description describing a circuit behavior through high level synthesis by high level synthesis means, a number of FFs corresponding to a necessary delay that is required to be inserted between modules; input FF stage number acquiring means for extracting, from the one of the HDL and the synthetic log, a pin having an input that receives an FF, and acquiring a number of stages of input FFs of FF reception, which corresponds to an input delay; latency re-adjusting means for obtaining an optimum delay based on the necessary delay from the latency adjusting means and the input delay from the input FF stage number acquiring means; former-stage module analyzing means for detecting, based on the one of the synthetic log and the HDL, each state inside a module having a pin to be subjected to FF insertion and a state having a minimum total number of FFs held in the each state; and FF insertion optimizing synthesis means for subjecting an entire circuit to high level synthesis again by the high level synthesis means based on the optimum delay from the latency re-adjusting means and an FF inserting position obtained based on the state having the minimum total number of FFs from the former-stage module analyzing means, to thereby obtain optimized HDL.