1. An apparatus, comprising: a power estimation circuit coupled to a first processor and a second processor, wherein the power estimation circuit is configured to receive high power instruction information from the first processor and the second processor and generate a power estimate dependent upon the received high power instruction information from the first processor and the second processor; a finite-state machine coupled to the first processor and the second processor, wherein the finite-state machine is configured to operate in one of a plurality of logic states, wherein each logic state of the plurality of logic states corresponds to a throttle level for the first processor and the second processor; a table configured to: store a plurality of pre-determined power threshold values during an initialization; and update at least one of the plurality of pre-determined power threshold values after a time period has elapsed since the initialization; and a comparator configured to compare the power estimate to each one of the plurality of pre-determined power threshold values; wherein the finite-state machine is further configured to transition from a first logic state of the plurality of logic states to a second logic state of the plurality of logic states dependent upon results of the comparison of the power estimate to each one of the plurality of predetermined power threshold values.