1. A computer-implemented method comprising: identifying a plurality of unused slots in a plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on a processor, wherein the processor does not have hardware interrupt capabilities; inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data; executing the inserted conditional branch instructions, wherein a predetermined memory location is checked each time each of the inserted conditional branch instructions is executed; in response to no data being present in the predetermined memory location, the processor takes no action; and in response to data being present in the predetermined memory location, the processor branches to a registered interrupt handler.