1. A parallel adder comprising: a first plurality of computational cells that operate to generate odd sum bits from inputs based on generate and propagate terms recursively computed and a plurality of carry-in bits; a plurality of selection cells that are independent of the first plurality of computational cells and operate to select and output even sum bits from a plurality of candidate sum bits, the selection capable of being made in accordance with predetermined ones of said recursively computed generate and propagate terms; a second plurality of computational cells selectively coupled to the first plurality of computational cells and said plurality of selection cells that operate to recursively compute said generate and propagate terms from initial ones of said generate and propagate terms; and a third plurality of computational cells selectively coupled to said plurality of selection cells that operate to compute said candidate sum bits from initial ones of said generate and propagate terms and a plurality of select inputs, wherein the initial ones of said generate and propagate terms are provided to the second and third pluralities of computational cells by a fourth plurality of computational cells.