1. A description style conversion method of a logic circuit which converts the logic circuit described in a netlist style to a logic circuit described in an RTL style by using a hardware description language, the description style conversion method characterized by including a logic circuit reading step in which the logic circuit described in the netlist style is read; a library reading step in which a lower-level logic circuit described in the RTL style of a library corresponding to an instance in the logic circuit is read; a library hierarchical expansion step in which a process of expanding a hierarchy of the library is performed for the instance in the logic circuit, and the logic circuit is converted to the RTL style; an assignment statement elimination step in which an assignment statement in the logic circuit is replaced and eliminated; and a logic circuit output step in which the logic circuit is output in the RTL style.