1. A configurable logic block (CLB) array for a programmable logic device, the CLB array having a plurality of CLBs arranged in a row-column configuration, wherein each CLB comprises: an array of configurable logic cells having a first column of configurable logic cells and a second column of configurable logic cells; a first carry chain extending through the first column of configurable logic cells; a second carry chain extending through the second column of configurable logic cells; a carry initialization circuit coupled to the first column of configurable logic cells; and a carry output circuit coupled to the second column of configurable logic cells, wherein each of the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells.