1. In a computer system comprising a formal specification of a logic circuit having at least one finite state machine (FSM) and at least one set of functional vectors for simulating the logic circuit, an apparatus for analyzing and verifying said at least one FSM's design and implementation, said apparatus comprising: a) synthesis means for generating a gate level specification of said logic circuit in response to said formal specification of said logic circuit; b) state table generation means comprising: b.1) command script generation means for generating at least one state table extraction command script file for said at least one FSM in response to said formal specification of said logic circuit: and b.2) state table extraction means for generating said at least one state table for said at least one FSM in response to said gate level specification of said logic circuit and said at least one state table extraction command script file; c) simulation means for simulating and generating simulation results of said at least one FSM in response to said gate level specification of said logic circuit, said at least one state table for said at least one FSM, and said at least one set of functional vectors; and d) reporting means for generating analysis reports in response to said simulation results of said at least one FSM and user inputs.