1. A circuit arrangement, comprising: a processing unit including a fixed point execution and a floating point execution unit; branch prediction logic disposed in the processing unit, the branch prediction logic including a branch history table including a plurality of entries, wherein each entry in the branch history table is associated with a branch instruction and includes at least one branch history bit predicting whether the associated branch instruction will be taken, and wherein each entry in the branch history table further includes at least one power usage prediction bit separate from the at least one branch history bit and predicting whether the floating point execution unit is expected to be idle subsequent to execution of the associated branch instruction; tracking logic coupled to the branch prediction logic and configured to notify the branch prediction logic of an idle status of the floating point execution unit, the tracking logic including: a counter configured to track a number of cycles the floating point execution unit has remained idle; and a latch configured to store an address associated with a last branch instruction; and control logic coupled to the branch prediction logic and configured to selectively reduce power consumption of the floating point execution unit in association with execution of a first branch instruction based upon the at least one power usage prediction bit in a first entry in the branch prediction table for the first branch instruction.