1. A memory device comprising: a memory array having a plurality of unit cells with a resistive sense element and a switching device; a row decoder connected to the plurality of unit cells; a column decoder connected to the plurality of unit cells; and a test circuit which establishes a non-operational configuration of the array via the row and column decoders by powering the array off, isolating the unit cells to be tested, and then powering the array on before a first test pattern with a first sensitivity is sent with a quiescent supply current to identify a first type and location of defects in the memory array and in response to the identified first type of defects a second test pattern with a second sensitivity different from the first sensitivity is chosen and sent with the quiescent supply current to identify a second type and location of defects from the same memory array, the first and second sensitivities respectively computed as a ratio of a difference between a faulty current and a nonfaulty current compared to the nonfaulty current.