1. A computer-implemented method for modeling semiconductor device performance, said method comprising: accessing, by a computer, multiple sets of data points for multiple related semiconductor devices, respectively, each set of data points being associated with a corresponding one of said multiple related semiconductor devices and indicating, for said corresponding one of said multiple related semiconductor devices, a corresponding dependence of a performance attribute on a model parameter, said corresponding dependence being different for different ones of said multiple related semiconductor devices due to local layout effects; generating, by said computer, multiple adjusted sets of data points for said multiple related semiconductor devices, respectively, by adjusting said model parameter in each of said multiple sets of data points such that, in each of said multiple adjusted sets of data points, said corresponding dependence of said performance attribute on said model parameter matches a reference dependence of said performance attribute on said model parameter; accessing, by said computer, only a single compact model; and, using, by said computer, said single compact model and said multiple adjusted sets of data points to model performance of all of said multiple related semiconductor devices, said using being performed without adjusting said single compact model.