1. An instruction issuing system for a processor including an execution unit having multiple functional units comprising: an instruction issuing unit receiving instructions from a memory, operating on instructions and forwarding instructions to said execution unit, said instruction issuing unit including means for detecting the existence of concurrencies in said instructions received from said memory; and said instruction issuing unit further including means for issuing multiple instructions and non-sequential instructions to said execution unit within a single processor cycle when a concurrency is detected by said means for detecting the existence of concurrencies in said instructions.