1. A hierarchical instruction scheduler included in a hierarchical microprocessor including a plurality of execution clusters, the hierarchical instruction scheduler comprising: a first-level instruction scheduler configured to: receive instructions for execution; store first operand status information for respective operands of the instructions; and dispatch the instructions to respective execution clusters based on the instructions' respective first operand status information; and a plurality of second-level instruction schedulers each operatively coupled with the first-level instruction scheduler, each second-level instruction scheduler being included in a respective execution cluster, the second-level instruction schedulers each being configured to: receive instructions for execution from the first-level instruction scheduler; store second operand status information for respective operands of the instructions received from the first-level instruction scheduler; and dispatch instructions, for execution, to respective execution units of the execution clusters based on the instructions' respective second operand status information.