1. A field programmable gate array comprising: a plurality of CLBs each having a plurality of lookup table function generators, each such lookup table function generator having a plurality of N input lines for selecting one of 2 N memory cells; a carry chain having a carry input and a carry output and a plurality of serially arrayed carry multiplexers, at least one respective such carry multiplexer being controlled by an output from a corresponding lookup table function generator, each such carry multiplexer having at least two inputs, one such input being provided by a previous carry multiplexer in said carry chain and the other such input being provided by an AND gate the inputs to which comprise a pair of input lines of said corresponding lookup table function generator.