1. An apparatus, comprising: a memory controller with circuitry configured to: initiate a program verify sequence to verify data written to a non-volatile memory (NVM), said program verify sequence having one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified; detect an approximate percentage of memory cells for each program verify level in which data is successfully written; and determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold; and one or more of: the NVM, the NVM being communicatively coupled to the memory controller; a processor communicatively coupled to the memory controller; a network interface communicatively coupled to a processor; a display communicatively coupled to a processor; or a battery coupled to a processor.