1. An integrated circuit chip comprising programmable intelligent search memory for content search wherein said programmable intelligent search memory performs regular expression based search and signature pattern based search, said programmable intelligent search memory using a plurality of regular expressions and a plurality of signature patterns, and said programmable intelligent search memory comprising a plurality of programmable FSA rule search engines to perform search using a plurality of regular expressions and further comprising one or more programmable signature search engines to perform content search using a plurality of signature patterns, said plurality of regular expressions comprising a plurality of symbols or characters, said plurality of regular expressions converted into a plurality of finite state automata representing the functionality of the said plurality of regular expressions for programming in the said programmable FSA rule search engines, said plurality of finite state automata comprising a plurality of states, said plurality of states derived from the said plurality of symbols or characters of said plurality of regular expressions, said content comprising a plurality of input symbols or characters provided as input to the said programmable intelligent search memory, said plurality of programmable FSA rule search engines comprising at least one of each of: a. a symbol memory circuit to store said plurality of symbols; b. a symbol evaluation circuit coupled to the said symbol memory circuit to evaluate match of the said plurality of symbols stored in the said symbol memory circuit with said plurality of input symbols of said content; c. a state dependent vector (SDV) memory circuit to store state transition controls for said plurality of finite state automata; d. a current state vector (CSV) memory circuit to store said plurality of states; and e. a state transition circuit coupled to the said symbol evaluation circuit, current state vector memory circuit and said state dependent vector memory circuit to perform state transition from one or more first states to one or more second states of said plurality of states of said plurality of finite state automata.