1. A computer-implemented method of performing an equivalence check on a mixed-signal circuit, comprising: at a server system, responding to a verification request, including: performing a static analysis on a first netlist and identifying a synthesizable section and a non-synthesizable section of the first netlist; determining functional equivalence between the non-synthesizable section of the first netlist and a corresponding non-synthesizable section of a second netlist; determining logical equivalence between the synthesizable section of the first netlist and a corresponding synthesizable section of a second netlist; and providing an equivalence result based on the determined functional equivalence and the determined logical equivalence.