1. A computer-implemented method for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computer-aided design tool, comprising: converting synchronous logic gates represented by the netlist to asynchronous logic gates; replacing clock circuitry represented by the netlist with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates; inserting a plurality of buffers corresponding to a specific design template into selected ones of the asynchronous pipelines to normalize path lengths through the asynchronous pipelines thereby achieving a level of performance; and removing selected ones of the buffers in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic with substantially no impact on the level of performance.