1. An apparatus comprising: a first chipset configuration (CC) register set in an input/output (I/O) manageability engine (ME) partition to authenticate and control enabling a CC functionality, the I/O ME partition managing I/O resources shared with a processor in a secure manner; and a second CC register set in a processor interface space coupled to the first CC register set to provide the CC functionality, the second CC register set including a global enable register having an enable field securely accessible to the I/O ME partition in a read and write-once accessibility and accessible to the processor via the processor interface space in a read-only accessibility.