1. A processor assembly, comprising a first processor having a first core comprising a program memory, instruction issue logic, and an integer execution unit, the processor assembly further comprising at least a first vector execution unit and a first memory unit arranged to hold data to be operated on, said first core, first vector execution unit and first memory unit being interconnected by a first network, and a second processor having a second core, said program memory being arranged to hold instructions for functional units in the first and the second processor, wherein the first core is arranged to enable the second core to control at least the first vector execution unit, or the first memory unit in the first processor.