1. A message processing circuit arrangement, comprising: a first set of programmable logic of an integrated circuit configured with an implementation of a plurality of thread circuits; and a second set of programmable logic of the integrated circuit configured with an implementation of a broadcast channel coupled to each of the thread circuits; wherein a broadcaster thread circuit of the plurality of thread circuits is configured to start a first thread circuit of the plurality of thread circuits and write messages to the broadcast channel, each message including a plurality of units of data; wherein the broadcast channel is configured to output a message-relative position value of a unit of data within a message available for reading from the broadcast channel; and wherein the first thread circuit is configured to read data from within the message from the broadcast channel responsive to the message-relative position value from the broadcast channel; wherein the broadcaster thread circuit is configured to write n bits of a message to the broadcast channel in parallel in a single cycle, where n is greater than or equal to 1; and wherein the broadcast channel is configured to output 2n bits in parallel in a single cycle.