1. A processor for executing threads through a plurality of logical processors, comprising: an instruction cache to store instructions; and a plurality of processing cores; wherein each processing core, of the plurality of processing cores, is to support simultaneous multithreading, and comprises: an instruction fetch logic to fetch one or more of the stored instructions; an instruction decode logic to decode the one or more of the stored instructions; a first logic that causes the processing core to appear as multiple logical processors, and to identify from the multiple logical processors a first set of the logical processors as operating system visible and a second set of the logical processors as operating system invisible; and a second logic to, when a thread of instructions is scheduled to be executed by the first set of the logical processors, transfer the processing of the entire thread of instructions from the first set of the logical processors to the second set of the logical processors based on a user-level instruction specifying one or more of the first or the second set of the logical processors identified by sequencer identifiers (SIDs), wherein the user-level instruction is to generate a control transfer signal from the first set of the logical processors to be received by one or more of the second set of the logical processors, and wherein the one or more of the second set of the logical processors process the thread of instructions.