1. A virtually parallel multiplier-accumulator (VMAC) responsive to a VMAC clock (VMCK) derived from a master clock (MCK), said VMAC being adapted for performing less than one multiplier-accumulator (MAC) operation within a MCK cycle, said VMAC comprising: a control-wave generator (CWG) adapted for generating a plurality of control signals within a VMCK cycle; and a sequential-computational stage MAC (SCS-MAC) adapted for receiving data from a source register and for receiving said plurality of control signals from said CWG, said SCS-MAC performing an operation on said data upon receipt of each of said plurality of control signals from said CWG.