1. A digital signal processing (DSP) circuit comprising; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, the set of multiplexers controlled by an opcode, the pre-adder circuit comprising a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers, wherein the pre-adder circuit receives a first input from a first multiplexer, the first multiplexer selecting between a first data input and a value in a register.