1. A processor, comprising: a translation lookaside buffer (TLB) storing a plurality of entries, wherein each of the plurality of entries comprises: physical address information associated with a respective virtual address range, and one or more memory attributes for a respective memory range, wherein an entry of the plurality of entries specifies a virtual address range that is a subset of a virtual address range specified by another entry of the plurality of entries, wherein the subset is fully encompassed within, and less than, the virtual address range for the other entry, wherein the TLB is configured to: receive a virtual memory address for a memory operation; and determine that the entry specifying the subset and the other entry are both TLB hits for the received virtual memory address; and a selection circuit configured to: in response to an indication from the TLB of two different entries as TLB hits for the same memory operation, select, based on one or more selection criteria, one of the two different entries; and cause the selected TLB entry including the corresponding physical address information and memory attributes to be provided to a memory interface for the processor.