1. A multi-cycle programmable processor, comprising: a plurality of microprocessor functional units and datapaths interconnecting the microprocessor functional units to form a functional unit electronic circuit to perform instruction execution of a plurality of instruction types; and a programmable controller having a control electronic circuit connected to the functional unit electronic circuit of the microprocessor functional units, the programmable controller selectively altering the datapaths based on a specific instruction type of the plurality of instruction types being executed by the microprocessor functional units, the selective altering of the datapaths limiting clock cycles per instruction (CPI) to a predetermined CPI.