1. A cache tag controller for a cache tag memory coupled to a system bus for receiving multiple cache tag modify operations to update cache tags in said cache tag memory said cache tag controller comprising: memory means for storing cache tags; address register means coupled to said memory means for specifying a cache tag in said memory means, said address register means receiving a first modify operation from said system bus; read register means coupled to said memory means for reading said cache tag according to said address means; first update means coupled to said read register means for modifying said cache tag based on said first modify operation; stage register means coupled to said first update means for storing a once-updated cache tag outputted from said first update means in response to said first modify operation; compare means coupled to said system bus for determining whether a second modify operation, the second modify operation being received subsequent to the first modify operation being received by the address register means from said system bus, is for the same cache tag in said memory means as said first modify operation, if said second modify operation is transmitted from said system bus before said first modify operation completes writing to said memory means; second update means coupled to said stage register means and said compare means for modifying said once-updated cache tag in said stage register means according to said second modify operation if said modify operation is for the same cache tag as said first modify operation; and write register means coupled to said memory means for writing at least one of the once-updated cache tag and a twice-updated cache tag to said memory means as specified by said address from said address register means.