1. In a line support processor for controlling data transfer operations between a host computer and data terminal equipment connected via data communication lines, wherein said line support processor includes a plurality of line adapters, a data link interface unit and a microprocessor means, said microprocessor means having an I/O bus for data transfers and output control registers providing control data to each of said line adapters, a byte oriented line adapter system comprising: (a) a plurality of input/output circuit means connecting said data terminal equipment to a first driver switching means, and wherein said input/output circuit means can execute instructions from said microprocessor to operate synchronously or asynchronously during data transfer operations, each said input/output circuit means including: (a1) a USART receiver-transmitter means controlled by said microprocessor means for receiving serial bit data from said data terminal equipment and converting said serial data to parallel character-byte data for transmission to said microprocessor means, and/or receiving character-byte data from said microprocessor means and converting it to serial bit data for transmission to said data terminal equipment, said USART receiver-transmitter means, being connected to respond to control data from said microprocessor means, for selecting the character-byte data size from five bits-per-byte up to eight bits-per-byte; (a2) timing means, set by the said microprocessor means connected to said input/output circuit means, said timing means including: (a2a) first timing means for generating the baud rate of data transfer in said USART receiver-transmitter means; (a2b) second timing means connected to said microprocessor means for establishing programmed time-out periods and delayed response time for accepting data coming in on said data communication lines to said line adapter; (b) first driver switching means, controlled by said microprocessor means, for transferring data from said microprocessor means to a selected one of said input/output circuit means, or transferring data from said selected input/output circuit means to a multiplexor means; (c) multiplexor means, having an output to said I/O bus of said microprocessor means, for conveying data bytes to a buffer memory means or to said microprocessor means for subsequent transfer to a main host computer, said multiplexor means including: (c1) a group of n multiplexors, each multiplexor connected for conveying data from one bit-line of a data transfer bus means from said first driver switching means, said group of n multiplexors providing for parallel transfer of character bytes of up to eight bits; (c2) said data transfer bus means connecting said first driver switching means to said multiplexor means; (c3) a plurality of input information-data means connected to the input of each of said multiplexors, said information-data means being transferrable to said microprocessor means upon control instructions from said microprocessor means; (c4) input instruction means connected to said multiplexor means from said microprocessor means for selecting which of said information-data means shall be transferred to said microprocessor means; (d) buffer memory means, connected to said I/O bus, for temporarily buffering data being transferred between said microprocessor means and said data terminal equipment, said buffer memory means including: (d1) address input lines connected from said microprocessor means to said memory means to receive addresses from said microprocessor means; and (d2) a memory output bus connected to convey addressed data from said memory means to said microprocessor means.