1. An apparatus comprising: a processing element including a load buffer, the load buffer to hold: a tail load instruction entry; a head load instruction entry, wherein a non-senior portion of entries between the tail load instruction entry and the head load instruction entry are to include non-senior load entries; and a senior head load instruction entry, wherein a senior portion of entries between the head load instruction entry and the senior head load instruction entry are to hold senior load entries, wherein a senior load entry of the senior portion of entries to hold senior load entries comprises a filter field to hold a state of a load tracking field associated with a line of a memory referenced by a load operation associated with the senior load entry; and a scheduler to schedule a post-retire access to the line of the memory referenced by the load operation associated with the senior load entry in response to the state of the load tracking field to be stored in the filter field represents a first state, wherein the post-retire access to the line of the memory is to update the load tracking field to a second state and further wherein the first state is represented by a first logical value, and wherein the second state is represented by a second logical value.