1. An apparatus comprising: a field programmable gate array (FPGA); and a bus through which streaming data is delivered to the FPGA at a bus bandwidth rate; the FPGA having firmware logic deployed thereon, the firmware logic configured to (1) receive the streaming data, (2) perform regular expression pattern matching on the streaming data with respect to a plurality of patterns to detect whether any pattern matches exist within the streaming data, and (3) concurrently build, at the bus bandwidth rate, a plurality of pattern indexes for the streaming data based on detected pattern matches, wherein each pattern index corresponds to a pattern against which regular expression pattern matching was performed and comprises location data for detected pattern matches.