1. A processing network for receiving a source code including a plurality of IF clauses, the network comprising: a plurality of processing elements on a programmable microchip; a plurality of on-chip routers on the microchip for routing the data between the processing elements, wherein each of the on-chip routers is communicatively coupled with one or more of the processing elements; and a compiler stored on a non-transitory computer-readable memory and comprising a parser that based on one or more conditions and one or more assignments of the source code generates a control tree by, for each one of the plurality of IF clauses within the source code, utilizing flags to determine if the IF clause is serial to or nested within one or more preceding IF clauses of the plurality of IF clauses within the source code.