1. An n-bit microprocessor device comprising: an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, comprising at least two 16-bit indirect memory address registers which are accessible by said CPU across all banks; a bank access unit for coupling said CPU with one of said plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein said indirect address registers are operable to access said data memory or program memory and wherein a bit in each of said indirect memory address registers indicates an access to said data memory or to said program memory.