1. A system for conditionally executing branch operations, comprising: a control store including predicate registers, at least one of the predicate registers configured to control Single Instruction Multiple Data (SIMD) lane execution of a plurality of SIMD lanes expressed in an instruction, wherein the at least one of the predicate registers comprises a plurality of bits, each bit being configured to control a corresponding lane of the plurality of SIMD lanes; and a branching circuit configured to receive a conditional branching instruction designating a predicate register and any one bit of the plurality of bits of the designated predicate register and to conditionally perform a branch operation based on a branching condition, wherein the branching condition is satisfied when the designated one bit of the designated predicate register is in a predetermined state.