1. An integrated circuit comprising: a differential input buffer having a first input coupled to a first pad and a second input coupled to a second pad; a first single-ended input buffer having an input coupled to the first pad; a second single-ended input buffer having an input coupled to the second pad; a first single-ended output buffer having an output coupled to the first pad; a second single-ended output buffer having an output coupled to the second pad; a serial-to-parallel converter having an input coupled to an output of the differential input buffer; and a parallel-to-serial converter having an output coupled to an input of the first single-ended output buffer.