1. A selectively configurable decoder having at least a mode selection input, a plurality of address inputs, and a plurality of outputs, said selectively configurable decoder comprising in combination: (a) a plurality of decoding means each having a plurality of decode inputs for decoding selectable combinations of signals applied to said decode inputs, each of said decoding means having an enable input and a plurality of outputs coupled to respective ones of said outputs of said selectively configurable decoder; (b) first means responsive to said address inputs and said mode selection input for producing said selectable combinations of signals; and (c) second means responsive to said mode selection input and said address inputs and coupled to said enable inputs of said plurality of decoding means for enabling a plurality of combinations of said plurality of decoding means in response to a plurality of combinations of binary logic levels applied to said mode selection input.