1. A method for operation of a flash memory controller having soft-decoding error correcting code logic, comprising: reading data from a portion of a flash memory in a plurality of instances using a plurality of different reference voltages, in each instance reading data from the portion of the flash memory using a different reference voltage from all other instances, the plurality of different reference voltages distributed over a voltage range, the voltage range substantially centered on an estimated mid-point between a pair of adjacent target cell voltages; determining a plurality of decision patterns, each decision pattern corresponding to a voltage region bordering one of the reference voltages, each decision pattern representing a combination of flash memory decision values for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell; generating a plurality of numerical values, each numerical value computed in response to the combination of the flash memory decision values represented by each decision pattern; and inputting the plurality of numerical values to the soft-decoding error correcting code logic.