1. A memory controller coupled with a memory, the memory comprising a first memory region and a second memory region, the memory being associated with a memory space and supporting random access to addresses of the memory space, and wherein the first memory region spans a first plurality of addresses of the memory space and the second memory region spans a second plurality of addresses of the memory space, the memory controller comprising: (I) a first pair of registers corresponding to the first memory region, wherein (a) a first register of the first pair stores a base memory address of the first memory region, and (b) a second register of the first pair stores address data corresponding to a current memory address of the first memory region, the current memory address of the first memory region being contiguous with a previously written memory address of the first memory region; (II) a second pair of registers corresponding to the second memory region, wherein (a) a first register of the second pair stores a base memory address of the second memory region, and (b) a second register of the second pair that stores address data corresponding to a current memory address of the second memory region, the current memory address of the second memory region being contiguous with a previously written memory address of the second memory region; (III) control circuitry configured to (i) receive, from a first computing resource, a base memory address of a particular memory region, and first write data to be written in the particular memory region; (ii) search the first register of the first pair and the first register of the second pair, and, when the base memory address of the first memory region stored in the first register of the first pair matches the base memory address of the particular memory region, identify the particular memory region as the first memory region, or when the base memory address of the second memory region stored in the first register of the second pair matches the base memory address of the particular memory region, identify the particular memory region as the second memory region; (iii) write the first write data at the current memory address of the identified memory region based at least on the address data corresponding to the current memory address of the identified memory region; and (iv) update the address data in the second register of the pair corresponding to the identified memory region based on a size of the first write data written at the current memory address of the identified memory region.