1. A packet buffer random access memory (PBRAM) device, comprising: (a) a memory array divided into a plurality of banks; (b) a plurality of input ports to be coupled to a network controller device, the memory array for storing packet data received by the plurality of input ports being shared by the plurality of input ports; (c) a plurality of serial registers each associated with a different one of the plurality of input ports, each of the serial registers configured for receiving packet data from the associated input port at a segment of a serial register concurrent with writing other packet data to the memory array from another segment of the serial register, each of the serial registers further being segmented into a plurality of segments, segments of respective serial registers being associated with corresponding portions of the memory array, segments of different serial registers simultaneously transferring packet data to different portions of the memory array; (d) row and column circuitry at each of the plurality of banks, the row and column circuitry configured to enable said writing other packet data to a respective bank independent of operation at other banks; and (e) a plurality of multiplexers each associated with a different one of the segments of the serial registers, each multiplexer enabling said writing other packet data to the memory array from a respective segment of the serial register.