1. A hardware processor comprising: a storage to store: a plurality of channel data having configuration information including triggering conditions for an aspect of the processor's operation to be monitored, and wherein the channel data includes information regarding an action to be taken responsive to occurrence of a corresponding triggering condition including an asynchronous transfer of control on occurrence of the triggering condition to an instruction address within a software thread; and a header field to store a plurality of in-use bits corresponding to and separate from the plurality of channel data, wherein the in-use bits are to indicate whether the plurality of channel data are to be saved to a plurality of save area segments of a memory coupled to the processor, wherein the processor is to communicate the plurality of channel data to the memory having the plurality of save area segments each to store a corresponding one of the plurality of channel data, wherein channel data stored in each of the plurality of save area segments may be restored to the processor storage independently of other channel data stored in others of the plurality of segments, the save area segments of the memory further including a header area to store an in-use bit vector having a plurality of entries, each entry of the in-use bit vector to indicate whether the channel data stored within a corresponding segment is to be used as the channel data to be stored in the processor, the memory further including logic to detect whether a first segment of the plurality of save area segments is valid and if so, to restore the first segment to the storage of the processor and otherwise to prevent the restore, and to detect an error occurring in a second segment of the plurality of segments and to indicate the error by updating the in-use bit vector entry corresponding to the second segment.