1. Circuitry for synchronously or asynchronously testing the functions of a programmable logic device, said device including a plurality of elements responsive to logic signals and a plurality of input lines, said input lines forming a portion of a data flow path of said device when not in test mode, comprising: a test memory operable to receive, store and output a plurality of test configuration bits; and circuitry responsive to said test configuration bits for forcing said elements of the logic device into pre-determined configurations while test signals are applied to at least one or said plurality of input lines.