1. A method of operating a processor having a first-type pipeline and a second-type pipeline, wherein the first-type pipeline includes a plurality of first-type pipeline stages and the second-type pipeline includes a plurality of second-type pipeline stages, the method comprising: simultaneously issuing a first first-type instruction into a first first-type pipeline stage and a first second-type instruction into a first second-type pipeline stage; generating a first first-type issue tag for the first first-type instruction, wherein the first first-type issue tag is unique relative to other first-type issue tags in the first-type pipeline; and generating a first second-type issue tag for the first second-type instruction, wherein the first second-type issue tag is unique relative to other second-type issue tags in the second-type pipeline.