1. A processor, comprising: a first processing core; and a first cache memory associated the first processing core, the first cache memory including: a plurality of cache lines; and a cache controller to: identify a first cache line as an interrupt reserved cache line; map the first cache line to a host physical memory address; set a coherency state of the first cache line to shared; and emulate a first message signaled interrupt identifying the host physical memory address responsive to detecting an I/O transaction including I/O data from an I/O device assigned to a virtual machine and the I/O transaction including a reference to the host physical memory address, the host physical memory address translated from a guest physical memory address in an address space of the virtual machine.