1. A method of implementing a reduced size register view data structure in a microprocessor, comprising: receiving an incoming instruction sequence using a global front end; grouping instructions of the incoming instruction sequence to form instruction blocks; performing chunking by using a plurality of multiplexers to access ports of a scheduling array comprising entries to store the instruction blocks as a series of chunks, wherein the scheduling array comprises one write port per entry, and is accessed by using a multiplexing structure before allocating to the scheduling array, wherein each multiplexer in the plurality of multiplexers is coupled to multiple entries in the scheduling array via a corresponding write port of each entry.