1. A method for reducing power consumption at a cache, the method comprising: determining a nonuniform architecture for a cache providing an optimum number of cache ways for each of a plurality of cache sets in the cache, the nonuniform architecture allowing the cache sets in the cache to have associativity values that differ from each other, the optimum number of cache ways being determined based on iteratively ordering each block of data in an address space of the cache and identifying an ordering that provides the minimum energy usage; implementing the nonuniform architecture in the cache to reduce power consumption at the cache; disconnecting a power supply to those cache ways of each cache set that are determined to not be a part of the optimum number of cache ways for each cache set in order to further reduce power consumption at the cache.