1. One or more integrated circuits (ICs) comprising: controller circuitry to: receive a command to execute an operation for a plurality of data inputs stored in an external memory or a local memory; and convert the operation into a set of matrix operations, wherein the set of matrix operations are to each operate on respective sub-portions of the plurality of data inputs; and at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include: a plurality of arithmetic logic units (ALUs); a local memory external to the ALUs and accessible by the ALUs; and processing control circuitry to: create a plurality of matrix operands in the local memory from the plurality of data inputs of the operation, wherein each of the plurality of matrix operands respectively comprises one of a scalar, a vector, or a two-dimensional (2D) matrix; and provide a plurality of memory handles to the plurality of ALUs, wherein each of the memory handles corresponds to a respective one of the matrix operands, and the plurality of ALUs are to access the respective matrix operands using the memory handles in association with executing the matrix operations.