1. A method of generating a test bench to verify a processor decoder, the method comprising: receiving an architecture description comprising processor decoder information; parsing the received architecture description into parsed information for verifying the processor decoder; generating the test bench automatically to verify the processor decoder based on the parsed information, wherein the test bench includes a test vector and a reference model of the processor decoder; comparing respective results of inputting the test vector into the reference model and a design under test (DUT) processor decoder; and verifying the processor decoder based on the respective results.