1. A method comprising: modeling a design abstraction of an Interlaken sub-circuit of an integrated circuit as a register transfer level (RTL) code within a data processing device; wherein a first stage of sequential logic in the RTL code is associated with a first stage of combinational logic in the RTL code; implementing, through a processor, a selective bypass or a selective enablement of the first stage of sequential logic; synthesizing, through the processor, a netlist from the RTL code, wherein the first stage of sequential logic is sequentially bypassed or sequentially enabled; and matching, through the processor, a timing of the first stage of combinational logic and a second stage of combinational logic in the RTL code by the selective bypass or the selective enablement of a second stage of sequential logic in the RTL code associated with the second stage of combinatorial logic.