1. A method to control a group of memory cells, the method comprising: erasing the group of memory cells, the group of memory cells including a first stack of NAND memory cells sharing a first body constructed on a substrate, and a second stack of NAND memory cells sharing a second body constructed on the substrate, by: applying an idle voltage to first control gates of the first stack of NAND memory cells and second control gates of the second stack of NAND memory cells; applying an erase voltage to the substrate; and controlling one or more mid-string devices positioned between the substrate and the first and second stacks of NAND memory cells to allow the erase voltage to propagate to the first body and the second body.