1. Hardware-based packet processing circuitry, comprising: header processing circuitry comprising a plurality of first hardware functional blocks configured to perform a plurality of predefined header processing functions, respectively; and payload processing circuitry comprising a plurality of second hardware functional blocks configured to perform a plurality of predefined payload processing functions, respectively; wherein the hardware-based packet processing circuitry is configured to: receive a header portion and a payload portion of an incoming packet in a first packet format; process the header portion in one or more selected first hardware functional blocks among the plurality of first hardware functional blocks according to a specified header processing sequence to form a processed header portion; process the payload portion in one or more selected second hardware functional blocks among the plurality of second hardware functional blocks according to a specified payload processing sequence to form a processed payload portion; and generate an outgoing packet in a second packet format based on the processed header portion and the processed payload portion of the incoming packet.