1. A computing device comprising: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute said primary execution unit instructions from said instruction cache; an auxiliary execution unit configured to receive and execute only said auxiliary execution unit instructions from said instruction cache in a manner independent from and asynchronous to said primary execution unit, wherein both said primary and auxiliary execution unit are configured to allow execution of their respective instructions, including arithmetic instructions, out-of-order with respect to said sequential order; and a central scrutinizer configured to coordinate completion of said primary execution unit instructions by said primary execution unit and said auxiliary execution unit instructions according to said sequential order, the central scrutinizer comprising: confirmation circuitry to evaluate instructions to determine exceptions that the instructions cause, commit circuitry to mark instructions committed to be completed, completion circuitry to coordinate completion of instructions in the auxiliary execution unit with instruction completion in the primary execution unit, and branch mispredict circuitry to track speculative instructions and initiate flushes on instructions newer than mispredicted branches.