1. A method for controlling a pipeline operation of a processor coupled to a memory containing executable computer instructions, including determining a branch instruction to be executed by the processor; providing both an address of a branch target instruction of the branch instruction and an address of a next instruction following the branch instruction in a program sequence; determining a branch decision with respect to the branch instruction; and selecting at least one of the branch target instruction and the next instruction as a proper instruction to be executed by an execution unit of the processor, based on the branch decision and before the branch instruction is executed by the execution unit, such that the pipeline operation is not stalled whether or not a branch is taken with respect to the branch instruction.