1. In a digital processor including means for executing a plurality of instructions stored in a memory and carried from said memory in accordance with a plurality of machine cycles, each of said instructions including an operation code, bit manipulation apparatus comprising: first means for generating a particular bit-mask in response to a particular operational code for an instruction being executed; second means for storing said particular bit-mask, third means for storing a word in which a bit is to be manipulated; logic means for performing a particular logic operation on the output of said second means and the output of said third means; said first means is responsive to the three least significant bits of said particular operational code; and the first means generates a bit-mask in binary digits which is the complement of 2.sup.i which is the number in base 10 represented by the three least significant bits of said particular operational code.