1. A programmable logic integrated circuit device comprising: programmable logic circuitry; and high speed serial interface circuitry including a plurality of functional subcircuits, each of which is at least partly hard-wired to perform a respective function that may be needed to provide a high speed serial interface, and routing circuitry adapted to allow at least one of the functional subcircuits to be selectively bypassed, at least one of the functional subcircuits being selected from the group consisting of pattern detection circuitry, 10 bit to 8 bit decoder circuitry, 8 bit to 10 bit encoder circuitry, and channel alignment circuitry.