1. A processor comprising: an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction; a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plurality of vector data based on the issued vector load instruction from the main memory; a vector register that stores vector data to be used for a vector operation based on the vector load instruction; a determination unit that determines a success or a failure of the branch target prediction after the branch target in the branch instruction is determined; and a vector load management unit that, when the branch target prediction is determined to be a success by the determination unit, acquires all vector data based on the plurality of acquisition requests and then transfers all the vector data to the vector register, and, when the branch target prediction is determined to be a failure, discards the vector data acquired by the acquisition requests issued by the data acquisition unit.