1. A multiple stage branch prediction system comprising: a first stage, the first stage including a branch target address cache (BTAC), the first stage configured to: store a BTAC entry corresponding to a conditional branch instruction; and predict a first direction of the conditional branch instruction based on the BTAC entry; a second stage, the second stage configured to: store an entry associated with the conditional branch instruction; predict a second direction of the conditional branch instruction based on state information corresponding to the entry; and modify state information corresponding to the entry, wherein the state information is modified after the conditional branch instruction is fetched and before the conditional branch instruction is resolved; and a logic circuit configured to: in response to a conflict between the first direction and the second direction before the conditional branch instruction is resolved, modify a position of the BTAC entry before the conditional branch instruction is resolved when the modified state information indicates that a predicted direction of the conditional branch instruction is predicted not taken, wherein the position of the BTAC entry is not modified when the modified state information indicates that the predicted direction of the conditional branch instruction is predicted taken.