1. Apparatus for processing data, said apparatus comprising: a physical set of registers; register renaming circuitry, responsive to register specifiers of an architectural set of register specifiers, configured to map said register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for processing instructions of said instruction set; wherein said register renaming circuitry, responsive to a program instruction specifying an operation requiring more than a predetermined number of register mappings, configured: (i) to divide said more than a predetermined number of register mappings into an initial set of register mappings and a remaining set of register mappings; (ii) to perform said initial set of register mappings to generate register specifiers for physical registers output on a main channel for further processing; and (iii) subsequent to performing said initial set of register mappings, to perform said remaining set of register mappings to generate register specifiers for physical registers output on a background channel separate from said main channel and concurrently with register specifiers for at least some other program instructions being generated by said register renaming circuitry and output on said main channel.