1. A single polysilicon floating gate semiconductor memory cell comprising: a substrate; a floating body region exposed at a surface of said substrate and configured to store volatile memory; a buried layer buried in a bottom portion of said substrate; wherein applying a bias to said buried layer results in at least two stable floating body region charge levels; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating said floating body region from said single polysilicon floating gate; and first and second regions exposed at said surface at locations other than where said floating body region is exposed; wherein said floating gate is configured to receive transfer of data stored by the volatile memory.