1. An integrated circuit, comprising logic circuits connected to a plurality of scan chains and self-test circuits for testing said logic circuits, said self-test circuits comprising: a pseudo random pattern generator for generating at least one flat pseudo random pattern; weighting circuits for providing a selectable weight set to said flat pseudo random patterns; a storage element associated with each of the weighting pattern generators receipt of a random pattern from the associated random pattern generator; and a selection circuit for individually addressing each of the storage elements for providing said weighted pseudo random pattern to said scan chains independently of one another for scanning said weighted pattern to said logic circuits to enable provision of different weights to the storage elements.