1. In a data processing system having a central processing unit, a memory module bank containing a plurality of memory modules, an instruction storage buffer in which instructions retrieved from said memory module bank are stored, and a memory access unit, coupled to said central processing unit and said instruction storage buffer, for controlling the addressing of locations in said memory module bank relative to which instructions and operands associated with said instructions are accessed, the improvement wherein said memory access unit comprises: first means, coupled to said instruction storage buffer, for generating a first memory identification code representative of a selected one of said memory modules in accordance with the contents of the opcode portion of an instruction stored in said instruction storage buffer; and second means, coupled to said first means, for generating a second memory identification code representative of the address location in the memory module from which the next instruction to be executed may be obtained in accordance with said opcode portion of the instruction stored in said instruction storage buffer.