1. A heterogeneous computer system, comprising: at least one performance processor, being configured to load a first part of a heterogeneous hypervisor layer when said at least one performance processor is powered on, wherein said first part of said heterogeneous hypervisor layer loads a performance operating system; a processor supporting logic, supporting said at least one performance processor for executing tasks of software; and a hypervisor processor, consuming less power than said at least one performance processor, loading a boot loader when said hypervisor processor is powered on, wherein said boot loader loads a second part of said heterogeneous hypervisor layer and said second part of said heterogeneous hypervisor layer loads a hypervisor operating system and said heterogeneous hypervisor layer is to provide for simultaneous and seamless communication between the performance and hypervisor operating systems for simultaneous applications, wherein said heterogeneous computer system includes the following modes of executing tasks of said software: said hypervisor processor, supported by said processor supporting logic, executing tasks of said software that said hypervisor processor has sufficient processing power to handle and putting said at least one performance processor to a power-conserving state; said hypervisor processor bringing said at least one performance processor out of said power-conserving state to execute tasks of said software that said hypervisor processor has insufficient processing power to handle; and said at least one performance and hypervisor processors simultaneously executing tasks of said software that require combined processing power of all processors, wherein when said hypervisor processor is powered on before said at least one performance processor is powered on, said at least one performance processor is powered on by said second part of said heterogeneous hypervisor layer, and when said at least one performance processor is powered on before said hypervisor processor is powered on, said hypervisor processor is powered on by said first part of said heterogeneous hypervisor layer.