1. An apparatus, comprising: a pointer detection circuit that, during operation, scans a data cache line fill arriving from a lower level cache and identifies a given memory pointer candidate within the data cache line fill, wherein the lower level cache is at a lower level of a memory hierarchy relative to the data cache; a pointer filter circuit that, during operation, initiates a prefetch request to the lower level cache for the given memory pointer candidate dependent on determining that the given memory pointer candidate satisfies a set of conditions, wherein: the pointer filter circuit comprises a quality factor (QF) table that stores a plurality of counters and is indexed dependent upon a program counter address associated with the given memory pointer candidate and a relative cache line offset of the given memory pointer candidate; the set of conditions includes a determination that a given one of the plurality of counters indexed by the given memory pointer candidate satisfies a QF counter threshold value; in response to initiation of the prefetch request for the given memory pointer candidate, the pointer filter circuit, during operation, updates the given one of the plurality of counters to reflect a prefetch cost; and in response to determining that a subsequent data cache line fill arriving from the lower level cache corresponds to the prefetch request for the given memory pointer candidate, the pointer filter circuit, during operation, updates a particular one of the plurality of counters to reflect a successful prefetch credit.