1. A method for cache management in a processor with a cache, the method comprising: receiving a bulk memory modification instruction; identifying one or more data blocks of the cache associated with the bulk memory modification instruction; updating a cache coherence state of the identified one or more data blocks to a modified zero (MZ) state in a cache to array, wherein: the updated cache coherence state is indicative of a zero value of the identified one or more data blocks, and the cache coherence state of the identified one or more data blocks is updated without modification to a cache data array; in response to receipt of a write instruction to write to a portion of a first data block of the one or more data blocks, modifying the cache data array to write to the portion of the first data block and transitioning a cache coherence state of the first data block from the MZ state to a modified (M) state in the cache tag array to indicate that the first data block potentially has a modified value and is exclusive to the cache; and in response to receipt of an external GetX request that indicates that another cache has requested to write to the first data block, transitioning the cache coherence state of the first data block from the M state to an invalid (I) state.