1. A cache controller of a shared cache memory system comprising a plurality of cache lines, the cache controller comprising a cache allocation circuit comprising: a minimum mapping bitmask for mapping a Quality of Service (QoS) class of a plurality of QoS classes to a minimum partition of the plurality of cache lines; a maximum mapping bitmask for mapping the QoS class of the plurality of QoS classes to a maximum partition of the plurality of cache lines; and the cache allocation circuit configured to: receive a memory access request comprising a QoS identifier (QoSID) corresponding to the QoS class of the plurality of QoS classes; determine whether the memory access request corresponds to a cache line of the plurality of cache lines; and responsive to determining that the memory access request does not correspond to the cache line of the plurality of cache lines: select, as a target partition, one of the minimum partition mapped to the QoS class corresponding to the QoSID by the minimum mapping bitmask and the maximum partition mapped to the QoS class corresponding to the QoSID by the maximum mapping bitmask; and allocate a cache line within the target partition for a cache fill operation.