1. An integrated circuit comprising: a plurality of computing nodes; a memory in at least one of the plurality of computing nodes, the plurality of computing nodes configured to make memory requests for access to the memory; an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests; means for identifying a set of memory requests; means for determining when all of the memory requests in the set of memory requests have been performed, wherein the means for determining when all of the memory requests in the set of memory requests have been performed is a ports counter; and means for initiating execution of a task when all of the memory requests in the set of memory requests have been performed.