1. A processor comprising: one or more cores to execute instructions and process data; one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; one or more epoch counters each programmed with a specified epoch value, wherein the epoch value is selected to be less than the time between occurrences of context switches on the processor; and TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value wherein the epoch value is set between 1 and 100 microseconds.