1. A register file for a pipelined computer architecture the register file comprising: a first instruction register configured to receive an instruction; a first cell array including a first plurality of registers; a first instruction decoder coupled between the first cell array and the first instruction register and being configured to generate a first word line signal in order to select one of the first plurality of registers responsive to the instruction in the first instruction register; a bypass multiplexor configured to receive the content of the selected one of the first plurality of registers; and a first pipestage register coupled between the bypass multiplexor and the first cell array and being configured to latch the content of the selected one of the first plurality of registers.