1. A method of data processing in a multiprocessor data processing system including a plurality of processor cores each having a respective associated one of a plurality of vertical cache hierarchies, each vertical cache hierarchy including a lower latency upper level cache and a high latency lower level cache, said method comprising: in response to a memory access request of a processor core among the plurality of processor cores, said memory access request targeting a target cache line: the lower level cache of a vertical cache hierarchy associated with the processor core supplying a copy of the target cache line to the upper level cache in the vertical cache hierarchy and retaining a copy of the target cache line in a shared coherence state; the upper level cache holding the copy of the target cache line received from the lower level cache in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core; in response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache associating the target cache line with an exclusive ownership coherence state in absence of coherency messaging with any other of the plurality of vertical cache hierarchies.