1. A method for optimizing placement and routing during an integrated circuit design process, comprising: using a design hierarchy tree having a global relationship representing an integrated circuit, wherein the design hierarchy tree includes a set of nodes, wherein each of the nodes has a defined set of inputs and outputs; representing a location of an atom in a design hierarchy of the integrated circuit as a location of one of the nodes in the design hierarchy tree; calculating, using a processor, a gain between two of the nodes; and performing synthesis, clustering, or partitioning of the nodes within the set based on the gain.