1. A system for controlling registers shared among a plurality of processors in a multiprocessor computer system comprising: a plurality of shared registers each being accessed from said processors, said shared registers being present in a number corresponding to that of said processors; and a shared register control portion having a shared register directory providing bit arrays corresponding one-to-one to said processors for each of said shared registers, wherein said shared register control portion manages allocation of said shared registers to said processors and their unoccupied condition according to a setting and a resetting of each bit of the bit arrays of said shared register directory and allocates any arbitrary shared register in response to a request for allocation of an unoccupied register from each of said processors and wherein said shared register control portion further comprises, control means connected to said processors to receive a request for said shared registers and for controlling changing the bits of said shared register directory; shared bit reset means, shared register selector means and shared bit set means connected between said control means and said shared register directory, said shared bit set means setting bits of said bit arrays of said shared register directory, said shared bit reset means resetting a bit of said bit arrays of said shared register directory corresponding to a shared register whose use is to be discontinued by one of said processors, said shared register selector means selecting one of said shared registers corresponding to said bit array, all the bits of which are reset; and access control means, connected between said processors and said shared registers, for allowing access from one of said processors corresponding to one of the set bits of each bit array of said shared register directory to a shared register corresponding to a shared register corresponding to a bit array including said bit.