1. A processing unit for a data processing system including a shared memory system, the processing unit comprising: a condition register; at least one execution unit that executes a memory transaction including: a plurality of transactional store instructions that causes the processing unit of the data processing system to make a corresponding plurality of conditional updates to target memory blocks of the shared memory system conditioned on successful commitment of the memory transaction; a transaction check instruction; and one or more additional instructions; integrated circuit logic configured to, responsive to execution of the transaction check instruction, refrain from committing the plurality of conditional updates caused by execution of the plurality of transactional store instructions to the shared memory system, determine, prior to conclusion of the memory transaction, whether all of the target memory blocks of the shared memory system were unmodified after conditionally updated by execution of the plurality of transactional store instructions, and responsive to determining that at least one of the plurality of target memory blocks was modified after conditionally updated by execution of the plurality of transactional store instructions, set the condition register to indicate a conflict for the memory transaction; wherein: the at least one execution unit executes the one or more additional instructions of the memory transaction following execution of the transaction check instruction; the memory transaction further includes a transactional load instruction that causes the processing unit to conditionally load a value from the shared memory system conditioned on successful commitment of the memory transaction; and the processing unit, responsive to execution of the transaction check instruction, ensures, prior to determining whether all of the target memory blocks of the shared memory system were unmodified after conditionally updated, that the value has been bound to the transactional load instruction.