1. A microprocessor, comprising: a plurality of memories, each configured to hold microcode instructions; wherein at least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions; wherein at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions, wherein M and N are integers greater than zero and N is greater than M; and a decompression unit, configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.