1. A reconfigurable processor, comprising: a status register configured to store a status value; a control register configured to store pending information used to adjust a point in time for initiating a subsequent program by verifying whether an operation according to coarse grained architecture (CGA) logic is terminated; a parallel processing scheduler configured to determine whether to execute very long instruction word (VLIW) logic and the CGA logic in a single execution mode or in a parallel mode based on the stored status value and pending information, and to schedule at least one of the VLIW logic and the CGA logic to be executed based on the determination; a VLIW register configured to store VLIW processed data according to the VLIW logic; and a CGA register configured to store CGA processed data according to the CGA logic.