1. A system for an agnostic runtime architecture, comprising: a close to bare metal JIT conversion layer; a runtime native instruction assembly component included within the conversion layer for receiving instructions from a guest virtual machine; a runtime native instruction sequence formation component included within the conversion layer for receiving instructions from native code; a dynamic sequence block-based instruction mapping component included within the conversion layer for code cache allocation and metadata creation, and is coupled to receive inputs from the runtime native instruction assembly component and the runtime native instruction sequence formation component; wherein the dynamic sequence block-based instruction mapping component receives resulting processed instructions from the runtime native instruction assembly component and the runtime native instruction sequence formation component and allocates the resulting processed instructions to a processor for execution.