1. A dynamically reconfigurable distributed integrated circuit processor comprising: at least one two-layer integrated circuit matrix with a first layer and a second layer; the first layer having a plurality of operative microcomputer modules of computers distributed in one or more computational clusters and linked together by a network of local communications connecting buses; the second layer being a network of global communications connecting buses that are coherent with the first layer through at least one pathway batch controller proximate at least one network node of the global communications connecting buses; each of the operative microcomputer modules having at least three n-bit active operand inputs, one instruction input, two n-bit active operand outputs, one n-bit result output, and one instruction operand output; each of the operative microcomputer modules having basic logic elements; the basic logic elements each having at least two basic n-bit active operand registers, one basic n-bit result register with input and output data-stream routing devices built into the register, a multifunctional controllable combination logic unit with an instruction-assigned operating function, an instruction register, and a set of internal-data and instruction transfer buses; the packet decoder having one control microinstruction address input and a plurality of outputs equal to a plurality of operative microcomputer modules in a computational cluster; the network of local communications connecting buses having a first set of buses linking active operand inputs and outputs and the result operand outputs of each of the operative microcomputer modules with the active operand inputs and outputs and the result operand outputs of the operative microcomputer modules of each computational cluster and corresponding global communications buses; and a second set of buses linking the control microinstruction inputs and outputs of each of the operative microcomputer modules with the control microinstruction inputs and outputs of the operative microcomputer modules of each computational cluster and corresponding global communications buses.