1. A processing core, comprising: functional unit logic circuitry having the following to execute a single instruction: a) a first register to store a read mask; b) a second register to store a first input vector operand; c) read masking circuitry to apply the read mask against the first vector operand to extract a set of elements of the first vector operand for operation; d) logic circuitry to create an output vector having multiple instances of a result of an operation performed on said set of elements; e) a third register to store a write mask different than said read mask; f) write mask circuitry to apply said write mask to said output vector to create a resultant vector.