1. In a multi-way set associative cache memory, an apparatus for updating status bits wherein the status bits depend on a match in at most one way of said cache memory, the apparatus comprising: a first transistor of a first conductivity type, a gate of said first transistor being coupled to a first match signal, a source of said first transistor being coupled to a power supply, a drain of said first transistor being coupled to a first node; a second transistor of said first conductivity type and a third transistor of a second conductivity type, drains of said second and third transistors being coupled together and to said first node, sources of said second and third transistors being coupled together and to a first old status bit, gates of said second and third transistors being coupled to a fifth signal, said fifth signal causing said second and third transistors to turn on only when there is no match in any way of said cache memory; and a fourth transistor of said second conductivity type, a gate of said fourth transistor being coupled to a second match signal, a source of said fourth transistor being coupled to ground, a drain of said fourth transistor being coupled to said first node, said first node providing a first updated status bit.