1. A cache system, comprising: a processor chip configured to receive a processing unit address; a comparing device configured to compare the processing unit address to at least a portion of an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the portion of the address information, a mapping device configured to map the portion of the address information of an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory of the processor chip; and a stacking loop searched in groups of allocated tags, in which each tag in each group of allocated tags is ordered in the stacking loop based at least in part on a most recently used tag in the group of allocated tags when the processing unit address matches the portion of the address information.