1. A method for enforcing memory-reference ordering requirements at an L2 cache, comprising: receiving a load at the L2 cache, wherein the load previously caused a miss at an L1 cache; performing a lookup for the load in reflections of store buffers associated with other L1 caches, wherein the reflections are located at the L2 cache, and wherein each reflection contains addresses for stores in a corresponding store buffer associated with an L1 cache, and possibly data that was overwritten by the stores; and if the lookup generates a hit, which indicates that the load may potentially interfere with a store, causing the load to wait to execute until the store commits.