1. A multi-core processor system comprising: a first processor core comprising a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core, wherein the first processor core further comprises a utilization table configured to receive current and predictive utilization indicators of a second execution resource over a high-speed execution resource bus; a second processor core comprising a second instruction queue and dispatch logic in communication with the second execution resource of the second processor core; and the high-speed execution resource bus coupling the first and second processor cores, wherein the first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.