1. A system on a chip comprising: a memory; a memory bus communicatively coupled to the memory; and a processor communicatively coupled to the memory via the memory bus, the processor including circuitry for providing store exclusive functionality comprising: a store exclusive initialize (STREX_INIT) instruction, the STREX_INIT instruction operable to initiate an exclusive store transaction to a location in the memory; a store exclusive synchronize (STREX_SYNC) instruction, the STREX_SYNC instruction operable to monitor an XWAVAIL indicator, the XWAVAIL indicator operable to indicate that an XWRESULT response to the STREX_INIT primitive is available, the XWRESULT response operable to indicate whether the exclusive store transaction to the location in memory was successful.