1. In a digital electronic computing system having a single machine cycle executable instruction set and including a memory hieracrchy comprising a main memory and a high-speed cache, a Central Processing Unit (CPU) and a bus network interconnecting same, said CPU including an arithmetic and logic unit (ALU) for performing mathematical and logical operations on data supplied thereto, an instruction unit operable in cooperation with a plurality of simultaneously accessible high speed general purpose registers and said ALU for processing primitive instructions to be performed by said system, and condition code generating means for generating a plurality of specified condition bits in accordance with the output of the ALU and the instruction unit, the improvement which comprises, a mechanism including a plurality of concurrently operable means for performing single machine cycle executable Mask and Rotate Instructions in said CPU wherein a subject operand is to be partially merged with an object operand under control of a mask, all of which are specified in one of said instructions, said mechanism comprising: means for generating an N-bit mask word from mask edge addresses specified by mask field in the instruction, access means for obtaining an N-bit subject operand from data specified in said instruction, access means for obtaining one of a plurality of possible N-bit object operands from the system high speed registers from data specified in said instruction, shifter means for rotating said N-bit subject operand which is to be merged with an N-bit object operand by an amount specified in said instruction, combinatorial circuit means for merging said rotated subject operand into said object operand under control of said mask so that data representative of the object operand is retained where said mask has a first binary content and data representative of the rotated subject operand is retained where said mask has the opposite binary content, and means for returning said retained merged N-bit word to a register in the CPU specified by said instructions.