1. A method for processing a computer implemented representation of a circuit design, comprising: representing the sequential circuit design in a machine readable medium, as a data structure defining a netlist as a plurality of nodes, and identifying a first set of nodes that includes word-level datapath nodes in the data structure; segmenting the first set of nodes in the data structure into segmented nodes having segment widths corresponding to uniformly treated segments of the corresponding words; finding reduced safe sizes for the segmented nodes; and generating an updated data structure representing the circuit design, using the reduced safe sizes of the segmented nodes.