1. A parallel bit reversal device comprising: a memory for storing data; a butterfly computation and control unit coupled to the memory via a data bus; and a parallel bit reversal unit configured to bit-reversing butterfly group data used by the butterfly computation and control unit wherein the parallel bit reversal unit comprises: an address reversing logic coupled to the butterfly computation and control unit and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit; an address selector; and a multi-granularity parallel memory coupled to the address selector and the butterfly computation and control unit, and configured to receive an address outputted from the address selector and receive written data and a read/write (R/W) granularity value outputted from the butterfly computation and control unit.