1. A data processor, comprising: internal bus; application accelerator unit (AAU) being integrated in said data processor and coupled to the internal bus, the AAU having storage queue for holding data to be transferred to and from a memory coupled to the internal bus and a boolean unit configured to perform a boolean operation between first data and second data to yield result data, the AAU being configurable to read the first and second data from the memory, perform the boolean operation and write the result data to the memory; and adder logic for performing an addition on third data read from the memory, the adder logic comprising a plurality of adders configured to add first bits of the third data to old carry bits generating new carry bits in a current clock cycle of the internal bus, the old carry bits having been generated by the adders adding second bits of the third data in a prior clock cycle of the internal bus, and a plurality of latches coupled to the adders, each latch for capturing one of the new carry bits and for providing one of the old carry bits.