1. A single event upset (SEU) immune two-input NOR circuit comprising: primary p-channel CMOS transistors, T 1 and T 3, and redundant p-channel CMOS transistors, T 2 and T 4 ; and primary n-channel CMOS transistors, T 6 and T 8, and a redundant n-channel CMOS transistors, T 5 and T 7 ; wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that, a first primary input, A 1, is coupled with the gate of T 1 and the gate of T 8 ; a first redundant input, A 2, is coupled with the gate of T 2 and the gate of T 7 ; a second primary input, B 1, is coupled with the gate of T 3 and the gate of T 6 ; a second redundant input, B 2, is coupled with the gate of T 4 and the gate of T 5 ; the source of T 1 is coupled with a power supply; the drain of T 1 is coupled with the source of T 2 ; the drain of T 2 is coupled with the source of T 3 ; the drain of T 3 is coupled with the source of T 4 ; the drain of T 4 is coupled with an output, Y; the drain of T 5 is coupled with the output, Y; the source of T 5 is coupled with the drain of T 6 ; the source of T 6 is coupled with ground; the drain of T 7 is coupled with the output, Y; the source of T 7 is coupled with the drain of T 8 ; and the source of T 8 is coupled with ground.