1. A discrete cosine transform (DCT) method using a six-stage DCT fast algorithm for parallel processing a sequence of input data of an 8.times.8 data block so as to generate a sequence of transform data, said DCT fast algorithm including first, third and fifth stages, each of which involving a plurality of butterfly operations, second and fourth states, each of which involving a plurality of post-addition multiplication operations, and a sixth stage involving a plurality of intrinsic multiplication operations, said DCT method comprising the steps of: (a) providing an input unit to receive said input data; (b) controlling said input unit to provide said input data to a butterfly operation unit in order to enable said butterfly operation unit to perform said first stage of said DCT fast algorithm; (c) controlling a data register unit to store first-stage output data from said butterfly operation unit therein; (d) controlling said data register unit to provide predetermined ones of said first-stage output data to a multiplication operation unit in order to enable said multiplication operation unit to begin performing said second stage of said DCT fast algorithm when said predetermined ones of said first-stage output data have been stored in said data register unit, while said butterfly operation unit continues to perform said first-stage of said DCT fast algorithm; (e) controlling said data register unit to store second-stage output data from said multiplication operation unit therein; (f) controlling said data register unit to provide said first- and second-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said third stage of said DCT fast algorithm after said butterfly operation unit has finished performing said first stage of said DCT fast algorithm; (g) controlling said data register unit to store third-stage output data from said butterfly operation unit therein; (h) controlling said data register unit to provide predetermined ones of said third-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said fourth stage of said DCT fast algorithm when said predetermined ones of said third-stage output data have been stored in said data register unit while said butterfly operation unit continues to perform said second stage of said DCT fast algorithm; (i) controlling said data register unit to store fourth-stage output data from said multiplication operation unit therein; (j) controlling said data register unit to provide said third- and fourth-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said fifth stage of said DCT fast algorithm after said butterfly operation unit has finished performing said third stage of said DCT fast algorithm; (k) controlling said data register unit to store fifth-stage output data from said butterfly operation unit therein; (l) controlling said data register unit to provide said fifth-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to perform said sixth stage of said DCT fast algorithm; and (m) controlling an output unit to receive sixth-stage output data from said multiplication operation unit.