1. A digital system, comprising a memory interposer module configured to be coupled between a processor module and a memory module, the memory interposer module comprising: a memory controller configured to couple to the memory module; a first memory emulator configured to couple to the processor module, wherein the first memory emulator is configured to emulate the memory module, the first memory emulator being operable to assert a stall signal to stall a memory request from the processor; an arbiter coupled between the memory controller and the memory emulator; and a second memory emulator connected to the arbiter, wherein the second memory emulator is also configured to emulate the memory module and to assert another stall signal to stall a memory request to the second memory emulator.