1. A memory array, comprising: a plurality of memory cells, each memory cell receiving a bit line, a first word line, and a second word line, each memory cell including: a cell selection circuit operably coupled to the first word line and the bit line to select the memory cell in response to activation of at least one of the bit line and the first word line; and a two-terminal switching device having only first and second conductive terminals to access and program the switching device wherein each of the first and second conductive terminals is coupled to a nanotube article, the first terminal operably coupled to the cell selection circuit and the second terminal operably coupled to the second word line; and a memory operation circuit operably coupled to the bit line, the first word line, and the second word line of each cell, said operation circuit including circuitry to activate at least one of the bit line and the first word line to select the memory cell for access or programming and including programming circuitry to apply an electrical stimulus to program a memory state in said nanotube article, said programming circuit to apply a first electrical stimulus to at least one of the bit line, first word line, and second word line, in which said first electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively high resistance and said programming circuit to apply a second electrical stimulus to at least one of the bit line, first word line, and second word line, in which said the second electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively low resistance, wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell.