1. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry programmable to provide products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including: a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product, compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, and circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; said arithmetic circuitry further comprising: floating point circuitry that separately processes sign, exponent and mantissa for carrying out floating point operations, and combined rounding and normalization circuitry for processing said mantissa and said exponent; and special case control circuitry that controls output of said floating point circuitry; wherein: said special case control circuitry comprises: multiplexer circuitry having inputs representative of said processed sign, said processed exponent, said processed mantissa, and output of said rounding and normalization circuitry; and circuitry that examines input sign, exponent and mantissa for special cases and controls said multiplexer to output one of (a) an output of said floating point circuitry and (b) a special case output.