1. A data processing system including a plurality of data handling devices, each connected in common to receive and transfer words including a plurality of bytes over a bus network, said system further including a memory subsystem comprising: a memory for storing said words; input means coupled to said bus for receiving one of said words from any one of said data handling devices for storage in said memory during a memory cycle of operation, each said word including a plurality of bytes and a plurality of parity bit signals each or indicating the validity of a different one of said bytes; encoder means coupled to said input means and to said memory, said encoder means for generating a group of coded check bits derived from said plurality of said bytes and said plurality of parity bit signals, said encoder means forcing a predetermined number of said coded check bits to predetermined states when said plurality of parity bit signals indicate that said bytes are in error; means connected to said encoder means and to said input means for applying said bytes and group of coded check bits to said memory for said storage during said memory cycle of operation; and, decoder means coupled to said memory, said decoder means for generating a plurality of syndrome signals for locating an error in said bytes, the location of said error being established by said bytes and said coded check bits read out from said memory during a subsequent cycle of operation, said plurality of syndrome signals having a first predetermined characteristic for signalling when said plurality of bytes of a word received from any one of said data handling devices have incorrect parity when written into said memory enabling the detection of multibyte parity errors in said words to be deferred until accessed by one of said devices so as to have a minimum effect on system performance.