1. A method, in a data processing system, for assigning memory to on-chip coherence domains, the method comprising: assigning caches on a processing unit chip to a plurality of coherence domains; assigning portions of memory to the plurality of coherence domains; generating a mapping table, wherein the mapping table associates each portion of memory to an identifier of a coherence domain to which it is assigned; responsive to a cache generating a cache miss, looking up an address of the cache miss in the mapping table to identify a coherence domain; and snooping caches within the identified coherence domain.