1. A structure for packing a stream of n-bit data into a stream of m-bit data words (n.ltoreq.m) for both little endian and big endian formats, comprising: a 2m-bit register for holding up to 2m bits of packed data; means for shifting in one direction only each of said n-bit data into position for insertion into said 2m-bit register as said packed data, said shifting means shifting each of said n-bit data, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data in said 2m-bit register before said insertion, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of packed data and n; and means for transferring from said 2m-bit register an m-bit output datum whenever the number of bits of said packed data in said 2m-bit register exceeds m.