1. A non-volatile memory system, comprising: a set of non-volatile storage elements, said set includes a first subset and a second subset of non-volatile storage elements; and managing circuitry in communication with said set of non-volatile storage elements, wherein in response to a request to erase said set, said managing circuitry applies an erase voltage to said set while enabling erasure of each non-volatile storage element of said set, said managing circuitry verifies whether said set is erased after applying said erase voltage by testing conduction through said set while applying a verify voltage to said first subset and applying a different voltage to said second subset, said managing circuitry repeats applying said erase voltage until successfully verifying that said set is erased, said managing circuitry applies said erase voltage to said set while inhibiting erasing of said first subset after successfully verifying that said set is erased.