1. A method comprising: creating a double-summed-to-zero (DSTZ) graph having a plurality of nodes linked by a plurality of directed branches, the DSTZ graph representing a finite state machine (FSM) that generates a sequence for a switching block used in a mismatch-shaping digital-to-analog converter (DAC), each of the plurality of nodes representing a state in the FSM, the DSTZ graph having a total work function and a total potential energy summing to zero for a cycle traversal; and generating a switching sequence starting from a reference node in the plurality of nodes in response to an input sequence, the reference node having a zero potential energy.