1. A system for detecting and correcting errors in a data block, wherein said data block includes a plurality of bits, and wherein said plurality of bits includes data bits and check bits, said system comprising: a transmitter configured to generate said check bits and to transfer said data block; a bus coupled to said transmitter, wherein said bus includes a plurality of data paths for conveying said data block, and wherein paired bits of said data block are conveyed on each of said plurality of data paths; and a receiver coupled to said bus, wherein said receiver is configured to receive said data block and to generate a syndrome vector, wherein said syndrome vector includes a plurality of syndrome bits, and wherein said syndrome vector is used to detect and correct single bit errors and to detect paired double bits errors in said data block.