1. A method of operating a data cache controller comprising: transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency; and transmitting second data to the CPU core with a second latency greater than the first latency; and generating error corrected data by performing an error correction operation on the first data, wherein the first latency is a delay between a read request to the data cache and transmission of the first data according to an execution of a first instruction fetched from an instruction cache, the second latency is a delay between a read request to the data cache and transmission of the second data according to an execution of a second instruction fetched from the instruction cache, and wherein the second data is output based on the error correction operation performed on the first data.