1. A resistive switching integrated circuit memory comprising: a resistive switching memory cell including a correlated electron material (CEM); a write circuit for placing said resistive switching memory cell in a first resistive state or a second resistive state depending on information input into said memory, wherein the resistance of said CEM is higher in said second resistance state than in said first resistance state; and a read circuit for sensing the state of said memory cell and providing an electrical signal corresponding to the sensed state of said memory cell; wherein said memory is capable of being read 10 8 times with less than 50% fatigue.