1. An integrated circuit comprising: A. a TDI/TMS input lead; B. a TCK input lead carrying a TCK clock signal having alternating rising and falling edges; C. a double data rate circuit having a TDI/TMS input coupled to the TDI/TMS input lead, a TCK input coupled to the TCK input lead, and separate TDI and TMS signal output leads, the double data rate circuitry including: i. a TDI circuit path having an input connected to the TDI/TMS input and an output connected to the TDI output lead, ii. a TMS circuit path having an input connected to the TDI/TMS input and an output connected to the TMS output lead, iii. the circuit paths including flip-flops having clock inputs coupled with the TCK input for changing output states on the edges of the TCK clock signal, and the circuit paths receiving alternating TDI and TMS signals on the TDI/TMS input at alternating edges of the TCK clock signal and providing a TDI signal on the TDI signal output lead and a TMS signal on the TMS signal output lead that both change states on the same edge of the TCK clock signal, and iv. each of the flip-flops having a preset input to set the flip-flops in a high state at power up; and D. a TAP domain having separate input leads coupled to the separate TDI and TMS signal output leads, and an input coupled to the TCK input lead.