1. A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions, comprising: a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision floating point instructions and at least one of the plurality of double precision floating point instructions in a fetch group, wherein the decode unit, comprises: a first counter arranged to increment for at least one of the plurality of single precision floating point instructions forwarded; a second counter arranged to increment for at least one of the plurality of double precision floating point instructions forwarded; a first mask register indexed by double precision registers, wherein the first mask register is updated by at least one of the plurality of double precision floating point instructions forwarded; and a second mask register indexed by single precision registers, wherein the second mask register is updated by at least one of the plurality of single precision floating point instructions forwarded.