1. A computer-implementable method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system, said computer-implementable method comprising: providing a load miss queue comprising a physical address field that indicates where load instruction data is stored for said load miss queue, an issue queue position field that indicates an issue queue position of a load-dependent instruction, a valid identifier field that indicates if said load-dependent instruction is valid, a source identifier field that indicates a source of said load-dependent instruction that is dependent on a load instruction, and a data type field that indicates a type of said load instruction data; dispatching said load instruction that misses a first level cache; in response to dispatching said load instruction, setting both of said physical address field and said data type field; identifying said load-dependent instruction, wherein said load-dependent instruction comprises one or more from the group consisting of: an instruction present in one of a plurality of issue queues; and an instruction dispatched from one of a plurality of latches; in response to indentifying said load-dependent instruction, setting each of said issue queue position field, said valid identifier field, and said source identifier field; determining if said issue queue position field refers to a flushed instruction; in response to determining said issue queue position field refers to a flushed instruction, clearing said valid identifier field; recycling said load instruction, in response to recycling said load instruction, determining a value of said valid identifier field; and in response to determining said value of said valid identifier field, selecting said load-dependent instruction for issue on a next processing cycle independent of an age of said load-dependent instruction.