1. A processor comprising: a plurality of packed data registers; a decode unit to decode a data element selection and consolidation instruction, the data element selection and consolidation instruction to have a first source packed data operand that is to have a plurality of data elements, and the data element selection and consolidation instruction to have a second source operand that is to have a plurality of mask elements, wherein each mask element of the second source operand corresponds to a different data element of the first source packed data operand in a same relative position; and an execution unit coupled with the decode unit, the execution unit, in response to the data element selection and consolidation instruction, to store a result packed data operand in a destination storage location that is to be indicated by the data element selection and consolidation instruction, the result packed data operand to include all data elements of the first source packed data operand, which correspond to unmasked mask elements of the second source operand, consolidated together in a portion of the result packed data operand.