1. An apparatus, comprising: a built-in self test (BIST) log to store BIST data representing faulty columns of a memory; redundancy configuration logic to generate one or more select signals based on the BIST data; an input shifter to map input data to one or more redundant columns of the memory, based on the one or more select signals, to avoid storing the input data to the faulty columns; and an output shifter to map output data from the one or more redundant columns of the memory, based on the one or more select signals, by bypassing the faulty columns.