1. A method comprising: receiving an instruction code that is of an instruction format comprising a first field and a second field, the first field to indicate a first multi-bit operand and the second field to indicate a second multi-bit operand; and modifying a first status flag to a first value responsive to determining that a first intermediate result of a bit-wise logical AND operation of the value in each of one or more bit positions of the first operand with the complement of the value in the same respective bit position of the second operand is zero, and modifying the first status flag to a second value responsive to determining that the first intermediate result is non-zero.