1. A multilevel FLASH cell architecture comprising: at least one FLASH cell; a plurality of reference generators; a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators; the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and providing outputs; and translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell.