1. A vector processing system comprising: a main storage for storing vector instructions and vector data; an instruction register for holding an instruction read out of said main storage; a decoder for decoding the vector instruction held in said instruction register; and an execution means operative to implement a vector operation in response to an output of said decoder, including a facility which, when a sort instruction inclusive of a vector starting address, increment switching parameter and operation switching parameter has been set up in said instruction register, implements a sorting process specified by said instruction for vector data stored in said main storage, said facility comprising means in which said operation switching parameter is set and which produces an operation switching signal in compliance with the number of operations and the position of a vector element to be operated, means in which said increment switching parameter is set and which produces an increment switching signal in compliance with the position of the element to be operated, fetch/store address generating means in which said vector starting address and said increment switching parameter are set and which in compliance with said settings generates addresses of vector elements to be sorted for reading out and writing in said main storage successively in an incremental manner and generates said addresses with incremental value thereof being changed in compliance with said increment switching signal, and operation means which implements an operation for sorting vector elements read out of said main storage in complance with said operation switching signal, said facility implementing sorting for all elements of vector data to be sorted when said sort instruction is set up in said instruction register.