1. A controller responsive to a clock synchronization mechanism defining synchronous communication cycles, each communication cycle defining at least one time interval, the controller comprising: a storage medium; and a processing circuit; the storage medium, readable by the processing circuit, storing instructions for execution by the processing circuit for: executing, within a first time interval, a first source task to broadcast a first destination task; communicating, within a second sequential time interval, the first destination task over a channel to a first destination; consuming, within a third sequential time interval, the first destination task; allowing the execution of a second source task to broadcast a second destination task within the first time interval; allowing the communication of the second destination task over the channel to a second destination within the second sequential time interval; and allowing the consumption of the second destination task within the third sequential time interval; wherein the first source task is allowed to be scheduled ahead of the second source task, and the second source task is allowed to be scheduled ahead of the first source task.