1. A non-volatile semiconductor memory device, comprising a plurality of memory cells, each of said plurality of memory cells storing three or more logic states which include at least an i-state and a j-state (j.noteq.i); and a write/verify circuit for detecting whether a predetermined data is sufficiently programmed to the memory cell, wherein when said write/verify circuit detects that a first memory cell of the plurality of memory cells where data "i" should be written does not reach a memory state of data "i", a programming of the first memory cell where "i"-data should be written and a programming of a second memory cell of the plurality of memory cells where "j"-data should be written, and an i-state verify read operation detecting whether "i"-data is stored in the first memory cell and a j-state verify read operation detecting whether "j"-data is stored in the second memory cell are performed, and after said write/verify circuit detects that the first memory cell where data "i" should be written reaches a memory state of data "i", a programming of the second memory cell where "j"-data should be written and a j-state verify read operation detecting whether "j"-data is stored in the second memory cell are performed until the second memory cell where data "j" should be written reaches a memory state of data "j".