1. A system for the management of the physical memory of a processor, incorporating a table of segment descriptive registers connected to the processor and to means for transforming a virtual address supplied by the processor into a physical address in order to permit the performance of a task, on the basis of real pages and segments contained in a physical memory, said virtual address containing at least one virtual page number, the binary value of a checking index of a first descriptive register of a physical segment in the memory corresponding to a task to be performed, and the offset value of the start of the physical segment, with respect to the start of the corresponding real page, wherein it also comprises a base register which is loaded, for each virtual address, by the base address of the first descriptive register corresponding to the task to be performed, said base address being supplied by the processor, the descriptive register table having inputs connected to the outputs of a logic adder, which receives on the one hand the binary value of the base address of the first descriptive register, and on the other hand the binary value of the index corresponding to the first descriptive register corresponding to the task to be performed, the outputs of the adder addressing one of the inputs of the descriptive register table, wherein the segment descriptive registers of the table contain control bits, the processor being enabled by the control bits of the segment to which the processor must have access, to check whether said processor must operate in the local or overall mode, and whether it must process an input - output operation, or an access to the memory.