1. A memory device, comprising: an array of memory cells arranged in rows and columns; and error checking and correcting (ECC) logic coupled to the array of memory cells, the ECC logic configured to generate an error checking and correcting syndrome in the memory device from data written to the array of memory cells, the ECC logic further configured to use the syndrome to check and correct data read from the array of memory cells, the syndrome generated from more data bits than a number of data bus terminals of the memory device but less than the number of memory cells in the row containing the memory cells to which the data is being written.