1. A correlator circuit comprising: tap memory for receiving data values; coefficient memory for receiving coefficients; default processing logic for multiplying the data values and corresponding coefficients in a default correlation manner; alternate processing logic for operating on the data values and coefficients in a non-default correlation manner, the logic including a lookup table in which is stored a second set of data values, the data values received in the tap memory serving as addresses to the lookup table; and a multiplier for multiplying a data value of the second set and a coefficient received from the coefficient memory, the data value of the second set and the coefficient corresponding to a data value from the tap memory addressing the lookup table; and selection logic for selecting between the default processing logic and the alternate processing logic.