1. An electronic system comprising: a first processor; a second processor; a cache memory configured to store some of data stored in a main memory and to be accessible by the first and second processors; and a cache controller configured to differently set a size of a storage space of the cache memory to be managed by each of the first and second processors, based on quality-of-service (QoS) information of each of the first and second processors, wherein: the cache memory comprises a plurality of entries, the plurality of entries is divided into two or more entry groups, and the cache controller limits an entry group to be accessed among the two or more entry groups, based on cache size information corresponding to the QoS information.