1. A computer-implemented method for controlling memory access operations, the method comprising: receiving a stream of graphics commands for execution within a single graphics processing unit (GPU), the stream of commands including a first set of memory access operations, a second set of memory access operations, and a memory barrier command interleaved between the first set of memory access operations and the second set of memory access operations; scheduling the first set of memory access operations, the memory barrier command, and the second set of memory access operations for execution within the single GPU; initiating execution of the first set of memory access operations; initiating execution of the memory barrier command; in response to initiating execution of the memory barrier command, completing the execution of each memory access operation in the first set of memory access operations to a point of coherency, while not initiating execution of the second set of memory access operations; completing the execution of the memory barrier command; and subsequent to completing execution of the memory barrier command, initiating execution of the second set of memory access operations.