1. A microcode patching device coupled to receive a first fetched instruction fetched by a microprocessor including said microcode patching device, the microcode patching device comprising: a first memory for storing microcode instructions, wherein said first memory stores a patch microcode routine; a second memory for storing a plurality of flag bits, wherein different ones of said plurality of flag bits are associated with different ones of said microcode instructions; an address generator coupled to said first memory, wherein said address generator generates, in response to said first fetched instruction, an entry point address of a first microcode instruction within said first memory, said first microcode instruction corresponding to said first fetched instruction, wherein said first memory is configured to provide said first microcode instruction in response to said entry point address, and wherein said second memory is configured to provide a first flag bit of said plurality of flag bits in response to said entry point address; and a controller coupled to said first memory and said second memory, wherein if said first flag bit associated with said first microcode instruction is asserted, said controller: branches to said patch microcode routine; dispatches a second microcode instruction within said patch microcode routine that stores a substitute microcode instruction corresponding to said first fetched instruction in a data register; and dispatches said substitute microcode instruction instead of said first microcode instruction.