1. A ROM coding process with a self-aligned implantation, comprising the steps of: providing a substrate with a plurality of bit-lines formed therein, a gate oxide layer formed on said bit-lines; depositing a conducting layer on the gate oxide layer and an aligning layer on the conducting layer; forming a plurality of word-lines having an aligning layer thereon by patterning the conducting layer and aligning layer, said bit-lines and said word-lines together forming an array of memory cells; coating a photoresist on said gate oxide layer, said aligning layer and sidewalls of said word-lines not covered by said aligning layer; partially etching through portions of said photoresist not covered by a mask pattern to said aligning layer so as to form openings exposing portions of said memory cells that will be programmed to operate in a first state; removing portions of said aligning layer exposed through said openings; and implanting impurities through said openings into said substrate using the photoresist as a mask to program said memory cells that will be programmed to operate in said first state, and leave other non-programmed memory cells operating in a second state.