1. A method of processing instructions in a processor, the method comprising: providing, by an instruction source, a group of instructions to a processor for execution; determining, by the processor, if a particular instruction of the group of instructions is the next instruction to complete execution, thus designating a next to complete instruction; and determining, by the processor, if the next to complete instruction exhibits a stall event during its execution and, in the case of such a stall event during execution, storing in a memory store stall information relating to a cause of the stall event for the next to complete instruction.