1. A direct memory access controller comprising: a data register for transferring a plurality of data in parallel from a source to a destination address, wherein the plurality of data is sequentially loaded into said data register; a pattern register; a data comparator coupled with the data register and the pattern register and for comparing the content of said data register with the content of said pattern register; and a control unit coupled with the data comparator wherein the control unit stops a data transfer if the data comparator detects a match of the data register and the pattern register.