1. A simulation apparatus for performing parallel execution of multiple logical processes obtained by modeling a plurality of components included in a system to be simulated, the simulation apparatus comprising: a condition generating unit configured to generate, on the basis of communication delays between the multiple logical processes: (i) constraint conditions to be satisfied by initial time shifts given to the multiple logical processes, and (ii) look-ahead times, with each look-ahead time corresponding to a time interval to be permitted for look-ahead processing by a message sent from a logical process serving as a communication source to a logical process serving as a communication destination; and a solver unit configured to: (i) solve an optimization problem satisfying the constraint conditions and minimizing overhead in communication of messages between the multiple logical processes, (ii) obtain the initial time shifts of the multiple logical processes and (iii) obtain the look-ahead times between the multiple logical processes.