1. A processor, comprising: a front end including a decoder, the decoder including a first logic to identify an end-of-live-range (EOLR) indicator, the EOLR indicator specifying an architectural register and a location in code for which the architectural register is unused; an allocator including: a second logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator; a third logic to generate a request to disassociate the architectural register from the physical register; and a retirement unit including a fourth logic to disassociate the architectural register from the physical register.