1. A method of modeling asynchronous behavior of a circuit stored as a netlist in a computer system, comprising: identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic; and modifying the stored netlist by inserting additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic, wherein the delayed output from the driving element is delayed with respect to the present driving element output by a number of cycles n which is a minimum of a send clock period of the driving element and a receive clock period of the downstream logic, and wherein the additional logic includes a random value generator having an output, a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the output of the random value generator, the multiplexer further having an output which drives the downstream logic, an XOR gate having at least two inputs, a first input of the XOR gate being connected to the present output from the driving element, and a second input of the XOR gate being connected to the delayed output from the driving element, and an AND gate having at least two inputs, a first input of the AND gate being connected to an output of the XOR gate, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.