1. A logical simulation device executing cycle-based logical simulation using level sort and compile methods, comprising: a first plurality of processors for performing both an evaluation process of executing simulation of logical blocks using logical blocks corresponding to one or more gates as an evaluation unit, and a communication process with a remainder of the first plurality of processors; a small-capacity data storage unit equivalent to cache memory, and wherein each of the first plurality of said processors are divided into processor groups composed of a second plurality of processors, a plurality of the processor groups are connected to each other in a tree-shape hierarchy to constitute one cluster, and said logical simulation device is composed of a plurality of the clusters; and a trace data storage unit for storing trace data of the cycle-based logical simulation and an external input signal pattern according to each processor group belonging to a lower side of the tree-shaped hierarchy.