1. An apparatus comprising: a processor for processing an instruction set, said processor including a first small fast memory; a first address bus coupled to said processor; a data bus coupled to said processor; a second memory, larger and slower than said first small fast memory, coupled to receive an address on said first address bus and to transmit and receive data on said data bus for storing data to be used by said processor; a third memory, larger and slower than said second memory, coupled to said first address bus and said data bus, with said second memory including a plurality of addressable locations each for temporarily storing data from said third memory; control means for controlling accesses to said second and third memories, said control means further comprising: means for determining whether data required by said processor is stored in said second memory; means for providing data to said processor on said data bus from either said second memory or said third memory; and a second address bus comprising at least one bit, coupled between said processor and said third memory, for providing a copy of a portion of said address on said first address bus to said third memory such that said third memory is addressed using address bits from both said first address bus and said second address bus.