1. A microprocessor system comprising: a microprocessor having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines; a demultiplexing register having inputs connected to said second group or multiplexed address/data lines and one of said control lines; a control memory having address inputs connected to the outputs of said demultiplexing register and to at least one line of said first group, having information outputs connected to said second group of lines, and a selection input; a plurality of TTL output gates provided with data inputs, one enabling input and control input connected to another one of said control lines; a decoder having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory and enabling input of said TTL output gates; and a direct connection between the outputs of said demuliplexing register and the data inputs of said TTL output gates.