1. An apparatus comprising: a memory module comprising a plurality of memory blocks; an address decoder module that decodes one or more address lines of the plurality of memory blocks, wherein an address output of the address decoder module corresponds to each memory block of the plurality of memory blocks; a BWE module comprising a block write enable (“BWE”) signal corresponding to each memory block of the plurality of memory blocks, wherein each BWE signal has a block write enable state and a block write disable state; and a MUX module that passes, to a write enable input of each memory block of the plurality of memory blocks, one of a corresponding address output of the address decoder module in response to receiving a block write enable control (“BWEC”) signal in a normal use mode; and a corresponding BWE signal in response to receiving the BWEC signal in a state trace mode.