1. A method of implementing hardware security in an electronic device, comprising: deriving a support vector model to define secure behavior for a first circuit on the electronic device from verification data comprising register-transfer-level (RTL) simulation traces for the first circuit by applying the RTL simulation traces as training data to a support vector machine (SVM) learning engine to generate the support vector model of security-adhering behavior for the first circuit, storing, within a memory of the electronic device, the support vector model; monitoring signals associated with the first circuit with a runtime classifier hardware circuit on the electronic device which compares the signals to the support vector model to detect an outlier signal for the first circuit; and blocking the outlier signal from being input to or output from the first circuit.