1. At a defect metrology computing device, a method for correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location, comprising: receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.