1. An integrated circuit multiprocessor apparatus for processing a plurality of data packets, comprising: a plurality of processors; an interface circuit for receiving and transmitting a plurality of data packets; a memory comprising a plurality of descriptors, each of said plurality of descriptors comprising an ownership indication, a start of packet indication, an end of packet indication, a buffer length value and a buffer address for specifying a location of a buffer in memory for storing at least a portion of a data packet; a packet manager circuit coupled between the interface circuit and the memory to transfer data packets between the interface circuit and memory, wherein the packet manager circuit is configured to transfer a first data packet under control of at least a first descriptor and to transfer a second data packet under control of at least a second descriptor, wherein said packet manager is configured to write back to memory all descriptors associated with a data packet upon completion of the transfer of said data packet and said descriptors are written back in the order in which they are released.