1. A computational circuit comprising: a selector having one input terminal and a plurality of output terminals for selectively connecting an input at said input terminal to one of said output terminals; a plurality of sample/hold circuits each of which is connected to respective output terminals of said selector for holding data output from said selector; a multiplexer, connecting to said plurality of sample/hold circuits, having a plurality of input terminals and at least one output terminal for selectively connecting one of said input terminals thereof to said output terminal thereof; and a computational unit connected to said at least one output terminal of said multiplexer.