1. A system including a first layer element executed in a privileged mode having a first priority of permission to access an entire region of a memory and second and third layer elements executed in an unprivileged mode having a second priority of permission to access a partial region of the memory, the system comprising: the memory; and a processor which determines whether the memory is accessible for each page that is an address space unit based on which mode a layer element currently accessing the memory is executed in between the privileged mode and the unprivileged mode, and which determines whether the memory is accessible based on which one of the first, second and third layer elements corresponds to a domain that is currently being accessed from among a plurality of domains of the memory, wherein each of the first, second, and third layer elements have individual access permissions with respect to the plurality of domains of the memory.