1. A non-volatile memory configuration scheme for volatile configurable circuits in a programmable integrated circuit comprising: an FPGA fabric; a first plurality of configurable circuit elements disposed on the integrated circuit external to the FPGA fabric; a second plurality of configurable circuit elements disposed on the integrated circuit external to the FPGA fabric; a plurality of distributed configuration non-volatile memory cells disposed in the FPGA fabric, each of the plurality of first configurable circuit elements coupled to a different one of the distributed configuration non-volatile memory cells; a non-volatile memory array for storing configuration information for the second configurable circuit elements; and a plurality of register cells disposed within the second plurality of configurable circuit elements and coupleable to the non-volatile memory array, each one of the register cells associated with a different one of the plurality of second configurable circuit elements.