1. In an information processing system including memory means for storing instructions, processor means responsive to the instructions for performing operations, the processor means including instruction queue means for fetching and storing instructions in advance of execution, the instruction queue means fetching instructions over a system data bus from locations in the memory means in response to substantially sequential addresses generated by an instruction pointer register means, the addresses being issued over an address bus to the memory means, and means responsive to certain of the instructions fetched by the instruction queue means for causing execution of an alternate sequence of instructions, prefetch monitor means, comprising: means, coupled to the system data bus, for detecting instructions fetched by the instruction queue means which may result in the execution of an alternate sequence of instructions; means for inhibiting the fetching of a next instruction from the memory means to the processor means, the inhibiting means being coupled to the detecting means and responsive to the operation thereof for inhibiting the fetching of the next instruction when the detecting means detects an instruction which may result in the execution of an alternate sequence of instructions; and means, coupled to the system data bus and to the detecting means and responsive to the instruction queue fetching operation of the processor means, for substituting null instructions upon the system data bus for storage within the instruction queue means, each of the null instructions being a type of instruction the execution of which prevents the instruction pointer register means from incrementing such that at the completion of the execution of the alternate sequence of instructions and also the null instructions stored within the instruction queue means the address within the instruction pointer register means points to the location in the memory means of the next instruction following the instruction which resulted in the execution of the alternate sequence of instructions.