1. A computer-implemented method executed by at least one processor for testing a computer processor device comprising: providing test data comprising a plurality of segments of test data that together make a slice of test data, wherein each segment of the plurality of segments of test data comprise sub-segments of test data with seven words including one single word sub-segment, one double word sub-segment and one quad word sub-segment, and wherein sub-segments in subsequent segments of the test data are arranged in different orders; placing multiple instances of the slice of test data in consecutive locations in a cache memory; and running a test code on the multiple instances of the slice of test data by branching back to rerun the test code on each of the slices of test data.