1. A memory array disposed above a substrate comprising: a first plurality of spaced-apart rail-stacks disposed at a first height in a first direction above the substrate, each rail-stack including a first conductor and a first semiconductor layer extending substantially the entire length of the first conductor; a second plurality of spaced-apart conductors disposed above the first height and in a second direction different than the first direction, and an insulating layer disposed between the first rail-stack and the second conductors which is capable of being selectively breached by passing a current between one of the first and one of the second conductors to program the array.