1. Array of a plurality of digital processing elements, wherein a digital processing element is a hardware structure for processing digital input data and providing digital output data and wherein the array may have one, two or more dimensions, wherein each digital processing element has associated a plurality of registers for holding input data, wherein the input data can be loaded in a load mode from an external data source; and each of the plurality of registers of a digital processing element is connected through switchable connections to at least two of the registers being associated to the two neighboring processing elements in each dimension of the array, wherein the switchable connections can be switched into a shift-register mode of operation, and wherein registers associated to processing elements on the border of the array are connected to registers associated to processing elements on the opposite border of the array.