1. A data processing device with an instruction translator comprising: a processor core; and a memory interface portion arranged between said processor core and an external memory mapped into a predetermined external memory space, said memory interface portion including a fetch circuit for receiving an address value for access to said external memory space from said processor core, and fetching the data at said address in said external memory, said data being an instruction nonnatives to said processor, an instruction native to said processor or data to be processed; a translator for translating the instruction nonnative to said processor core fetched by said fetch circuit from said external memory into the native instruction; and a select circuit for selectively applying the data read from said external memory space and the instruction prepared by translating the instruction read from said external memory space by said translator to said processor core depending on whether the address value for the access from said processor core to said external memory space is in a predetermined region or not.