1. A method of computer processing comprising: supplying source code to a computer having at least one processor having a first instruction set and at least one dynamically reconfigurable logic array; analyzing the source code to identify one or more processor states; binding the one or more processor states to one or more technology types and subtypes; synthesizing logic to reconfigure the at least one dynamically reconfigurable logic array to execute the processor states; reconfiguring the at least one dynamically reconfigurable logic array to a specific set of cell designs and routing options to implement the one or more technology types and subtypes; executing the one or more processor states on the at least one processor and on the at least one reconfigured logic array; wherein the one or more processor states executing on the reconfigured logic array are different than the one or more processor states executing on the at least one processing processor having the first instruction set.