1. A cache coherent memory system for use in a non-homogeneous multiprocessor system, comprising: a first processor; a first cache associated with said first processor; one of a second processor or other device non-homogeneous with said first processor; and multiprocessor bus means connected to said first cache of said first processor and to said one of a second processor or other device non-homogeneous with said first processor for providing cache coherent communications via said bus means.