1. An apparatus comprising: non-volatile memory to include a first region in a Single Level Cell (SLC) mode, a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is to be unexposed as user addressable space; and logic to move a portion of the second region from the multiple level cell mode to the SLC mode, wherein the portion of the second region is capable to enter into the SLC mode based on status of at least one bit, wherein each time one or more new blocks are opened for writing, they are to be opened in SLC mode and once a write idle threshold is met, content from one or more SLC blocks are to be garbage collected to one or more MLC blocks, wherein burst write operations are to be directed at the second region in response to a threshold number of burst write operations directed at the first region.