1. A memory architecture, comprising: a plurality of hierarchical levels, including a lowermost hierarchical level and at least one higher hierarchical level; at least one memory block in each of said hierarchical levels, said memory block in said lowermost hierarchical level including individual memory cells, and each next-higher hierarchical level including memory blocks formed by memory blocks of a respectively next-lower hierarchical level; decoder devices in each of said hierarchical levels for driving, reading, and writing said memory blocks; at least one I/O interface with a plurality of I/O ports being driveable in parallel simultaneously and independently of one another; and an address selection circuit and a port selection buffer circuit in at least one of said hierarchical levels.