1. A computing apparatus, comprising: a coarse-grained array including a plurality of reconfigurable processing elements having connections that are capable of being reconfigured for processing; a host processor comprising one or more processing elements that operate independently from the plurality of reconfigurable processing elements of the coarse-grained array and which are formed outside of the coarse-grained array; a central register file transmitting data between the coarse-grained array and the host processor; and an interrupt supervisor which stalls an operation of the coarse-grained array when an interrupt occurs while a loop is executed in the coarse-grained array, and enables the host processor to process the interrupt, wherein the coarse-grained array and the host processor are tightly coupled together by sharing the central register file.