1. A hardware array processor that implements multi-threaded processing comprising: one or a plurality of thread coordinators; one or a plurality of self-routing switch fabrics; an array of addressable heterogeneous function blocks; said self-routing switch fabric or each of said plurality of self-routing switch fabrics comprising: one or a plurality of input ports; one or a plurality of output ports; one or a plurality of queue memory blocks comprising a plurality of thread queues; said one or plurality of queue memory blocks further comprising one or a plurality of queue memories, wherein a queue memory of said one or plurality of queue memory blocks is selectively partitioned to form one or a plurality of independent thread queues among the plurality of thread queues; and an array of multiplexers that route tokens received on a self-routing switch fabric input port to a selected queue memory, data output from a queue memory forming a self-routing switch fabric output; wherein: an addressable heterogeneous function block of the array of addressable heterogeneous function blocks, comprises at least: one or a plurality of input ports, an output port, an addressable heterogeneous function block input port being connected directly to an output port of a self-routing switch fabric, and the addressable heterogeneous function block output port being connected to a self-routing switch fabric input port; wherein: said one or plurality of queue memory blocks further comprise: queue maintenance and thread synchronisation logic and a queue control block for the plurality of thread queues; the queue maintenance and thread synchronisation logic comprises: a thread queue scheduler and a programmable circuit; and wherein: each of the plurality of thread queues has at least an empty flag output, the empty flag outputs configured into groups of any combination via the programmable circuit to form one or more groups of coupled thread queues; the thread queue scheduler is configured to simultaneously read tokens from selected thread queues and transfer them to a connected addressable heterogeneous function block; and each addressable heterogeneous function block is configured to perform operations upon input data, format resultant data as a token by appending a routing tag to the resultant data, and transfer said token via one or a plurality of the self-routing switch fabrics to a thread coordinator or an addressable heterogeneous function block.