1. A mixed mode parallel processor system comprising: a plurality of processing units, each processing unit executing one MIMD operation and including a plurality of processing elements; and a control processing element (CP) that selects SIMD mode or MIMD mode and broadcasts, upon selection of SIMD mode, an instruction that instructs all processing elements to perform SIMD operation, each processing unit comprising: at least one instruction stream selector in association with the processing elements belonging to the processing unit, said instruction stream selector changing over a control signal and data to be processed by the processing element(s) between SIMD mode and MIMD mode; and at least one control circuit performing, for the plurality of processing elements in each of the processing units, instruction cache control and instruction sequence control, wherein in the MIMD mode operation, a memory included by one processing element among a plurality of processing elements making up said processing unit is made usable as an instruction cache memory; and a mode designation register that registers SIMD mode or MIMD mode designated by said control processing element; wherein in SIMD mode operation, the instruction stream selector in the processing unit selects an instruction from the control processing element, under control by the control circuit, the same instruction being sent to the plurality of the processing elements to perform parallel processing.