1. An apparatus for passing interrupts from one or more devices configured for a specific interrupt architecture to one or more processors not designed for the specific interrupt architecture, comprising: an abstraction layer comprising a first plurality of registers conforming to the specific interrupt architecture; and an implementation dependent layer, disposed in communication between the abstraction layer and the one or more processors, comprising a second plurality of registers which correspond to the first plurality of registers, wherein the implementation dependent layer is configured to receive interrupts and forward received interrupts to the one or more processors and to read and write data to the second plurality of registers in response to interrupts processed through the one or more processors.