1. A method, implemented on a computer, for allowing non-cacheable loads in a hardware transactional memory environment, wherein the computer comprises a processor in communication with a memory, wherein transactional loads or stores by the processor are monitored for transactional execution (TX) conflicts in a cache of the hierarchical cache subsystem, the method comprising: accepting a request, by the processor, to execute a TX transaction; based on execution, by the processor, of a non-cacheable load instruction for loading second memory data of the transaction, loading an address of the second memory data into a non-cache-monitor for monitoring memory conflicts of non-cached lines, the non-cache monitor for monitoring memory conflicts of non-cached lines; and aborting the TX transaction based on the non-cache monitor detecting a memory conflict from another processor, the memory conflict comprising requesting an access, by the other processor, to the address monitored by the non-cache monitor.