1. A processor comprising: a memory; an instruction decoder coupled to the memory for decoding instructions retrieved therefrom; and a plurality of execution units for executing the decoded instructions; wherein one or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, one or more of the operation fields each comprising at least an operation code field and a function field, the operation code field and the function field together specifying a particular operation to be performed by one or more of the execution units.