1. A computer program product comprising a computer readable storage medium having encoded thereon computer program code to describe a processor capable of executing a jump with hazard barrier instruction, the jump with hazard barrier instruction comprising: an opcode field specifying a jump to a target address operation; a first register field, specifying a first register that contains a value used to determine said target address; a second register field, specifying a second register to contain a value used to determine a return address; and a hazard barrier hint field, for designating that instruction hazards are required to be cleared as part of execution of the jump with hazard barrier instruction.