1. A method comprising: identifying, at an instruction pipeline of a processor, a first location of a stack to be accessed by a first stack access instruction and a second location of the stack to be accessed by a second stack access instruction; identifying, based on a first stack offset value stored at a first table, a dependency between the first stack access instruction and the second stack access instruction in response to the first location of the stack matching the second location of the stack; and identifying a dependency between a load instruction and a store instruction based on an identifier of a first memory address stored at a second table different from the first table.