1. A circuit for selecting a field of data from a packet of data in an n-bit data path, comprising: a first selector circuit having m inputs and an output, wherein each of the m inputs receives a respective subset of bits of the data path, the respective subset of bits input to each of the m inputs overlaps with the respective subset of bits of the data path input to another of the m inputs, and the first selector circuit selects one of the subsets of bits for the output; and two or more shift-and-select stages, each shift-and-select stage including a respective second selector circuit having up to m inputs and an output, the inputs of an initial one of the shift-and-select stages coupled to the output of the first selector circuit, and the respective second selector circuit in each other of the two or more shift-and-select stages coupled to the output of the respective second selector circuit in a preceding one of the shift-and-select stages, wherein: one of the inputs of the respective second selector circuit inputs an un-shifted version of the subset of bits, one or more others of the up to m inputs of the respective second selector circuit input different shifted versions of the subset of bits, and the respective second selector circuit outputs a selected one of the un-shifted or shifted versions of the subset of bits; and the respective second selector circuit in a last one of the shift-and-select stages outputs one of the un-shifted or shifted versions of the subset of bits that includes the field of data aligned to the least significant bit.