1. A system for processing memory access requests, comprising: a work queue comprising a plurality of state machines each configured to store one of a plurality of requests for access to logical memory addresses; and a translation look-aside buffer (TLB) that receives requests for access to logical memory addresses and that translates a first subset of the received requests from logical memory addresses to physical memory addresses responsive to comparisons between the received requests and a second collection of page table entries included in the TLB; wherein a first of the plurality of state machines sends a first request stored therein to a cache if another state machine of the work queue is not awaiting translation data relating to the first request; and wherein the TLB sends a second subset of the received requests to the work queue responsive to the comparisons between the received requests and the second collection of page table entries included in the TLB.