1. An apparatus, comprising: a memory controller configured to perform a reading process to read a bit value from a memory cell, the memory controller comprising: comparison logic configured to compare a threshold voltage of the memory cell to at least one pair of fractional reference voltages without using integral reference voltages and to generate comparison results, wherein the comparison logic is configured to compare the threshold voltage of the memory cell with only one pair of fractional reference voltages when the threshold voltage is an unreliable cell voltage; and read logic to determine the bit value of the memory cell based, at least in part, on the comparison results.