1. A data processing apparatus comprising: processing circuitry configured to perform operations; a scalar register bank configured to store scalar operands for access by the processing circuitry; a vector register bank configured to store vector operands for access by the processing circuitry, each vector operand comprising a plurality of operand elements; decoding circuitry configured to decode a sequence of instructions in order to generate control signals for the processing circuitry, such that the operations performed by the processing circuitry are dictated by the sequence of instructions; said sequence of instructions including scalar instructions, each scalar instruction specifying a scalar operation to be performed on one or more scalar operands in said scalar register bank; the decoding circuitry being responsive to a decode modifier instruction within said sequence of instructions, the decode modifier instruction having a type identifier, to alter decoding of a subsequent scalar instruction in said sequence by: mapping at least one scalar operand specified by said subsequent scalar instruction to at least one vector operand in said vector register bank; and determining, in dependence on said scalar operation specified by said subsequent scalar instruction and on said type identifier of the decode modifier instruction, a vector operation to be performed by the processing circuitry upon at least a subset of the operand elements within said at least one vector operand.