1. A data processor system comprising memory and a data processor, the memory comprising a plurality of data word locations each arranged to contain a predetermined number of data bytes and a data string stored in the memory, the data processor comprising: a data register; memory access circuitry for reading one of the data word locations containing at least a portion of the data string and storing the portion of the data string in the data register; end condition detection circuitry connected to the data register generating a multi-bit output word in which certain bits are significant condition bits defining presence of an end condition for a correspondingly positioned byte in the data register; a byte count register storing a value defining a number representing unprocessed bytes in the data string; a first mask circuit connected to the byte count register for generating a byte count mask defining positions of bytes in the data register and belonging to the data string; a first logic circuit connected to the end condition detection circuitry and to the first mask circuit for logically combining the byte count mask and the multi-bit output word of the end condition detection circuit and generating a multi-bit end condition output word defining end conditions of bytes in the data register belonging to the data string; a second mask circuit connected to the first logic circuit for detecting a first significant condition bit in a first position nearer one end of the end condition output word than any other significant bit in the end condition output word and for generating an end condition mask defining only bits of the end condition output word up to and including the first significant condition bit; a second logic circuit connected to the first mask circuit and the second mask circuit for generating a multi-bit output mask having a significant condition bit in a position corresponding to a first byte in the data register representing an end condition and a significant condition bit in each position corresponding to a byte belonging to the data string and positioned between the first byte representing an end condition and one end of the data register corresponding to the one end of the end condition output word; an offset register defining the position of a first byte of the string in a memory location with respect to one end of the memory word stored in the data register; and a shift register connected between the first mask circuit and the first logic circuit and responsive to contents of the offset register to shift the byte count mask generated by the first mask circuit in a direction away from one end of the byte count mask corresponding to the one end of the data register by a number of bit positions defined by the contents of the offset register before the multi-bit mask generated by the first mask circuit is applied to the first logic circuit.