1. A parallel processing apparatus, comprising: a program counter for indicating instructions to be read out from a memory; an instruction register for storing a plurality of consecutive instructions read out from an address of said memory indicated by said program counter; a plurality of integer units for executing integer-arithmetic operations; a floating-point unit for executing floating-point-arithmetic operations; and means for controlling said plurality of integer units and said floating point unit to effect either parallel processing of a plurality of consecutive instructions stored in said instruction register in said plurality of integer units and said floating point unit, or successive processing of instructions stored in said instruction register in response to a processing state alteration instruction.