1. A microprocessor, comprising: (a) a pipelined core unit including an address calculation stage, followed by an execution stage, followed by a writeback stage; (b) a write buffer having a plurality of entries coupled to said execution stage and said writeback stage, each of said plurality of entries containing contents corresponding to a write instruction executed in said execution stage and written from said writeback stage, said contents including a data field, an address field, a data a valid control bit, and a non-cacheable write bit representing whether said write instruction is non-cacheable; (c) a cache memory having a plurality of entries coupled to receive said data and address fields from said write buffer; and, (d) control logic circuitry coupled to said address calculation stage and to said write buffer, to compare an address of a read instruction in said address calculation stage to each of said plurality of address fields in said write buffer, and responsive to an address match, said data valid control bit being set, and said non-cacheable write bit being clear, bypassing said data field in said write buffer to said execution stage in said pipelined core unit.