1. A system comprising: a first processor comprising an interface and a first translation lookaside buffer (TLB) configured to store virtual-to-physical address translations; and a second processor comprising a second TLB different from the first TLB; wherein: in a first mode of operation, the first processor is configured to control the first TLB for the first processor; and in a second mode of operation, external control of the first TLB by a second processor is enabled in which the second processor is able to write virtual-to-physical address translations into the first TLB; wherein in the second mode of operation the second processor is configured to: send a work task to the first processor for processing by the first processor; determine one or more virtual-to-physical address translations the first processor will need in order to process the work task; and convey the determined one or more virtual-to-physical address translations to the first processor via the interface for storage in the first TLB of the first processor.