1. A method for testing enclosure of vias by geometries of a design layout, said vias connecting geometries of a first layer to geometries of a second layer, said method comprising the steps of: representing geometries on the first layer by a w 0 set of objects; for i&equals;1, n: deriving a wide class w i object set; identifying w i connection areas between the first layer and the second layer, each having at least one via located within a w i object of the first layer; performing a w i redundant via test on each identified w i connection area, said w 1 redundant via test performed relative to a base class w 1 object set containing the identified w 1 connection area, said base class w 1 formed by extending virtual edges of w 1 objects inside of w 0 objects; and marking vias that fail the w i redundant via test as a violation.