1. A system, comprising: a first processor; a second processor communicable with the first processor; a first memory for storing first codes to boot the first processor and a start code to boot the second processor, the first memory communicable with the first processor; a second memory designated for the first processor; a third memory designated for the second processor; and a fourth memory shared by the first processor and the second processor, wherein the first processor fetches the start code from the first memory, the start code is transmitted from the first processor to the second processor via a communication channel between the first processor and the second processor to boot the second processor after releasing a reset state of the second processor, and the fourth memory is accessible to one of the first processor and the second processor at a time.