1. A memory comprising: a plurality of arrays including a first array and a second array, the first array including a plurality of blocks; a first global data line associated with the first array; a first delay selection circuitry for providing a delay selection value; wherein each of the plurality of blocks comprises: a plurality of memory cells; a primary sense amplifier having a first input coupled to the plurality of memory cells, a second input that receives a primary sense amp enable signal, and an output coupled to the first global data line; a first delay adjust circuit that receives the delay selection value and a control signal, and generates a delayed control signal by delaying the control signal by an amount determined by the delay selection value; and a first control signal generation circuit which receives the delayed control signal and which provides the primary sense amplifier enable signal to the second input of the primary sense amplifier.