1. A system for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor, the system comprising: a first execution unit to perform instruction execution in a first execution pipeline; a second execution unit to perform instruction execution in a second execution pipeline, wherein the second execution pipeline includes a greater number of stages than the first execution pipeline; an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit; and a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.