1. A processor comprising: a first storage to store a cache ratio indicator indicative of a ratio of a capacity of a second cache to a capacity of a core cache; a processing core including the core cache; the second cache; and a cache controller, including: a core eviction unit to respond to an eviction of a clean and valid cache line from the core cache by performance of an operation selected, based on a value of the cache ratio indicator, from: an inclusive eviction operation comprising: to silently drop the clean and valid cache line from the core cache; and a non-inclusive eviction operation comprising: to update the second cache to include the clean and valid cache line; a state unit to respond to a core cache miss of a targeted line, valid and modified line in the second cache, by performance of an operation selected, based on the value of the cache ratio indicator, from: a first inclusive modified operation comprising: allocation of a core cache line to store the targeted line in an exclusive state and fill the core cache line from the valid and modified line in the second cache; and a first non-inclusive modified operation comprising: allocation of a core cache line to store the targeted line in a modified state, forward the core cache line in the second cache to the core cache, and invalidate the valid and modified line in the second cache.