1. A method for performing register file checkpointing to support speculative execution within a processor, comprising: commencing speculative execution of a program from a point of speculation, at which the outcome of a long latency instruction is speculatively predicted; wherein updating a register with a new value during the speculative execution involves, checkpointing an old value of the register, if the register has not already been checkpointed, and updating the architectural state of the register with the new value; whereby only registers that are updated during the speculative execution are checkpointed, instead of checkpointing all of the architectural registers prior to commencing speculative execution.