1. In a data processor, a method of increasing instruction execution parallelism comprising the steps of: writing an instruction identifier into a first data storage device; writing one or more execution condition data values to a second data storage device when an instruction corresponding to said instruction identifier finishes execution, said second data storage device having one or more storage locations; setting one or more validity bits in said first data storage device; and obtaining said one or more execution condition data values using said instruction identifier and said one or more validity bits.