1. A computer system comprising: a plurality of processors; a shared memory device accessible over a bus by the at least two processors; and a controller operably associated with said plurality of processors for use in connection with performing memory access cycles over said bus from said processors to memory addresses of the shared memory device, the controller operable to perform the operations of: monitoring signals generated during performance of a snoop routine initiated prior to completion of a memory access cycle from a first one of the processors; causing the memory access cycle to be continued in response to a monitored signal received from another processor without awaiting responses from any other of the processors if said received signal indicates that immediate completion of the memory access cycle will not disturb the integrity of the data stored in the system.