1. A system for controlling restarting of instruction fetching using speculative address computations in a processor, the system comprising: a predicted target queue to hold branch prediction logic (BPL) generated target address values; target selection logic including a recycle queue, the target selection logic selecting a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue; and a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, wherein instruction fetching is restarted in response to the wrong target.