1. A processor comprising: a plurality of cache memories, an array of interconnected tiles, each tile comprising a processor core, at least one of the tiles comprising a copy engine to perform a memory-to-memory copy operation based on a source begin address, a source end address, a transaction length, and a stride of transaction and each processor core being associated with one of the cache memories; with the memory-to-memory copy operation copying first segments of data from a source region starting from the begin address, skipping over second segments of data in between the first segments of data, and stopping at the end address, and each of the first segments of data that is copied has a length equal to the transaction length, and each of the second segments of data that is not copied has a length equal to the stride of transaction, and with the source region having the data being copied comprises at least one of a region in a cache memory associated with the tile having the copy engine, a region in a cache memory associated with a tile different from the tile having the copy engine, a region in a cache memory shared by multiple tiles, and a region in a main memory.