1. An apparatus comprising: multiple parallel computing cores, each computing core configured to perform one or more processing operations and generate input data; multiple parallel coprocessors associated with each computing core; multiple communication lines configured to transport the input data from each computing core to a designated one of the coprocessors associated with each of the computing cores, the coprocessors configured to process the input data and generate output data; and multiple reducer circuits, each computing core associated with one of the reducer circuits, each reducer circuit configured to receive the output data from each of the coprocessors of the associated computing core, to apply one or more functions to the output data, and to provide one or more results to the associated computing core.