1. A method for optimizing program instruction execution throughput in a processor apparatus having at least one central processing unit core (CPU), comprising: implementing a simultaneous multithreaded (SMT) operational mode in said CPU wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing a cache memory resource within said CPU; implementing an autothread (AT) operational mode in said CPU; determining as part of said AT operational mode whether there is a resource conflict between said hardware threads that undermines instruction execution throughput; and if said determining detects a resource conflict, adjusting relative instruction execution rates of said hardware threads in said CPU based on relative priorities of said software threads.