1. A data processing apparatus comprising: single instruction multiple data (SIMD) processing circuitry configured to perform a SIMD operation on first and second SIMD operands comprising a plurality of data elements, the SIMD processing circuitry having a plurality of parallel processing lanes for processing corresponding data elements of the first and second SIMD operands; permutation circuitry configured to perform a permutation operation on at least one source operand comprising a plurality of source data elements to generate said first and second SIMD operands, said permutation operation generating at least one of said first and second SIMD operands with at least one of a different data element size and a different data element positioning to said at least one source operand; and an instruction decoder configured to decode SIMD instructions requiring the SIMD operation to be performed by the SIMD processing circuitry; wherein in response to a first SIMD instruction requiring the permutation operation and identifying the at least one source operand, the instruction decoder is configured to control the permutation circuitry to perform the permutation operation on the at least one source operand to generate the first and second SIMD operands, and to control the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands generated by the permutation circuitry; and in response to a second SIMD instruction not requiring the permutation operation and identifying the first and second SIMD operands, the instruction decoder is configured to control the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the second SIMD instruction, without passing the first and second SIMD operands via the permutation circuitry.