1. A data processing apparatus comprising: a vector register bank configured to store vector operands for access by processing circuitry, each vector operand comprising a plurality of vector elements; vector data access circuitry for performing vector access operations in order to move vector operands between the vector register bank and a data store; a reconfigurable buffer accessible to the vector data access circuitry and comprising a storage array for storing up to M vectors of N vector elements, where the values of M and N are reconfigurable; the vector data access circuitry being configured to perform speculative data write operations in order to cause vector elements from selected vector operands in the vector register bank to be stored into said reconfigurable buffer, on occurrence of a commit condition, the vector data access circuitry further being configured to cause the vector elements currently stored in the reconfigurable buffer to be written to the data store; speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements of each selected vector operand stored in the reconfigurable buffer, the speculation width indication being initialised to an initial value, and on detection of an overflow condition within the reconfigurable buffer the speculation width indication being modified to reduce the number of vector elements of each selected vector operand stored in the reconfigurable buffer; and the reconfigurable buffer being responsive to a change in the speculation width indication to reconfigure the storage array to increase the number of vectors M and reduce the number of vector elements N per vector.