1. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: (A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including, (1) instruction prefetch means for prefetching and retaining instructions from said memory means, and (2) instruction alignment means for aligning bit sequences of instructions including at least one operand specifier prefetched from said memory means; (B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including, (1) a first operand specifier decoding means and a second operand specifier decoding means both connected to said instruction alignment means, said second operand specifier decoding means being capable of decoding a next sequential operand specifier received from said instruction alignment means in the same machine cycle as a first operand specifier; and (2) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in the instruction from said instruction alignment means and ascertaining the function of said instruction, said operand operation code decoding means including a simultaneous decode permission means for issuing a signal to permit simultaneous decoding of two operand specifiers within the same machine cycle, said permission signal being provided to said second operand specifier decoding means, said second operand specifier decoding means decoding the next sequential operand specifier to the operand specifier decoded by said first operand specifier decoding means only when said permission signal is provided thereto; and (C) address calculation means connected to said instruction decoding means for calculating an effective address of the operand in accordance with information of an operation code and operand specifiers decoded by said instruction decoding means in the previous machine cycle, whereby said instruction fetch means, said instruction decoding means and said address calculation means carry out their processes in parallel, and said instruction decoding means and said address calculation means carry out their process for each operand specifier.