1. A method of operating a processor, comprising the steps of: executing a sequence of instructions, said instructions being of fixed length; detecting a conditional branch instruction having an opcode and a signed displacement, said conditional branch instruction being in said sequence of instructions and having an address in a sequence of instruction addresses; detecting the sign of said displacement in said conditional branch instruction; fetching a next instruction of said sequence of instructions, said next instruction having an address in sequence with said conditional branch instruction, if said displacement is positive, or, alternatively, fetching a branch target instruction having an address determined by said displacement and not in said sequence of instruction addresses, if said displacement is negative; determining said target branch address by the the steps comprising: shifting the displacement to address a longword boundary; and adding the shifted displacement to contents of a program counter which was undated to address a next instruction following said conditional branch instruction; and, after either said step of fetching a next instruction or said step of fetching a branch target instruction has begun, testing a register defined in said conditional branch instruction to determine a condition specified by said opcode of said conditional branch instruction.