1. A data processing system comprising: a processor means for generating main memory address signals; a main memory having a plurality of memory locations for storing main memory words; a cache control means; first and second cache memories each having a plurality of memory locations for storing main memory addresses and corresponding cache data words in a priority order, and each responsive to main memory address signals which mismatch all of the main memory addresses stored therein to generate and transmit a mismatch signal to said cache control means; said cache control means responsive to concurrent generation of said mismatch signals by said first and second cache memories to generate and transmit a first control signal to said main memory and said first and second cache memories; said main memory responsive to said first control signal and said mismatched main memory address signals to access and transmit a main memory word to said first cache memory; said first cache memory responsive to said first control signal to transmit the lowest priority cache data word and its corresponding stored main memory address to said second cache memory, and to store said transmitted main memory word and said main memory address signals; and said second cache memory responsive to said first control signal to store the transmitted lowest priority cache data word and its corresponding main memory address.