1. A memory having charge trapping memory cells comprising: a substrate; a plurality of conductive word lines; a plurality of memory cells including a plurality of shallow trench isolations, a plurality of source/drain regions bounded by the shallow trench isolations, a plurality of gate electrodes formed by respective parts of the word lines opposing the substrate between adjacent source/drain regions to form a plurality of channel regions, the gate electrodes being isolated from the source/drain regions by a trapping dielectric, and wherein the gate electrodes are arranged in trenches at least partly formed in the substrate.