1. An M out of N code checker circuit apparatus for determining if number M bits, where M.ltoreq.N and where such number M as is received by said circuit as binary-encoded first signals, is equal in number to that number of binary ones as between N binary input second signals, said circuit apparatus comprising: code generator stage means for receiving said N binary input second signals in a plurality of parts, and for producing for each of said plurality of parts binary-encoded third signals representing the number of binary ones contained between the input signals of each respective part; adder stage means for gathering all said binary-encoded third signals as are produced by said code generator means for each respective one of said plurality of parts, from said code generator stage means and for adding said binary-encoded third signals in order to produce as binary-encoded fourth signals that total binary ones bit count as is contained between said N binary input second signals; and comparator stage means for receiving said binary-encoded fourth signals which represent the total binary ones bit count from said adder stage means, and for receiving said binary-encoded first signals which represent the number M, and for producing an error signal if said binary-encoded fourth signals and said binary-encoded first signals are not equal; whereby said error signal results if said total binary ones bit count between said N binary input signals was not equal in number to M; whereby said circuit apparatus thusly checks an M out of N code between said N binary input signals for any number M.ltoreq.N.