1. An apparatus comprising: a semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory includes circuitry associated with operation of the multiple memory cells, and wherein the semiconductor die that includes the 3D memory includes a serializer/deserializer interface configured to enable communication, via a second semiconductor die that is coupled to the serializer/deserializer interface, with a controller of the 3D memory, the controller on a third semiconductor die that is distinct from the second semiconductor die, wherein the second semiconductor die includes periphery circuitry configured to scramble data received from the controller and to communicate the scrambled data to the semiconductor die via the serializer/deserializer interface.