1. In a memory array, a process of forming a phase-change memory cell comprising: forming an isolation structure; forming an N&plus; base below the isolation structure; forming a protective layer over the memory array; selectively removing the protective layer to form a silicided CMOS device peripheral to the memory array; forming a lower electrode in a first recess, wherein the lower electrode touches a self-aligned emitter active area below the first recess; and forming a phase-change memory element.