1. A processor comprising: a plurality of processor elements; and a first processor element to perform a user-level fork instruction of a software thread, the first processor element including: a decoder to decode the user-level fork instruction, wherein the user-level fork instruction is to indicate at least one instruction address; and a user-level thread fork module, in response to the user-level fork instruction being decoded, to configure each of the plurality of processor elements to perform instructions in parallel.