1. A method for mapping state elements for equivalence verification between a first circuit and a second circuit, the method comprising: (a) determining, using a computer, a first sequential depth from primary inputs and primary outputs of the first circuit and the second circuit to each state element of the first and second circuits, wherein the first sequential depth is a minimum count of state elements along any path between two points of a circuit; (b) identifying and mapping first state elements of the first circuit and the second circuit having a unique first sequential depth; (c) determining a second sequential depth from the identified first state elements of the first circuit and the second circuit to the remaining state elements; (d) identifying and mapping second state elements of the first circuit and the second circuit having a unique second sequential depth; and (e) repeating (c) and (d) unless the method is no longer generating new unique mappings of state elements.