1. A mixed mode parallel processor system comprising: a plurality of processing units, each processing unit including a plurality of processing elements, the processing units including: at least one instruction stream selector in association with the processing elements belonging to the processing unit; and at least one control circuit performing, for the plurality of processing elements in each of the processing units, instruction cache control and instruction sequence control; wherein in SIMD mode operation, the instruction stream selector in the processing unit selects an instruction from the control processing element, under control by the control circuit, the same instruction being sent to the plurality of the processing elements to perform parallel processing.