1. A data processing apparatus comprising: a device configured to perform a sequence of operations including execution of instructions having associated instruction addresses and memory operations on data values having associated data addresses, for at least some of the memory operations the data address being determined relative to an architectural state value of an item of architectural state of the device; and trace circuitry configured to receive indications of the sequence of operations being performed by the device, and to generate from said indications a stream of trace elements; when for a memory operation the data address is determined to have been determined relative to an architectural state value of said item of architectural state, the trace circuitry being configured dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation.