1. A partly reprogrammable Finite State Machine including a state register holding the current state and two functions (of and nf) comprising combinational logic to calculate the outputs and the next state, respectively, said combinational functions being representable in a “sum of product terms form”, said Finite State Machine comprising: a) a circuit disabling a predetermined number of product terms associated with said “sum of product terms form”, each product term corresponding to a given state and a given input vector setting, b) a circuit enabling a new product term for a predetermined respective number of new product terms generating for each, a correct output signal corresponding to a given error state and a given error input bit vector, and c) said disabling and/or enabling circuits being provided in a form which allows activation thereof in case a product term was tested to include a bug.