1. A non-volatile memory device comprising: bit lines; word lines; a three dimensional array of memory cells comprising a plurality of memory cell strings, each memory cell string including a vertical stack of memory cells connected to a respective bit line, and memory cells of different memory cell strings connected to a respective word line; a page buffer including first latches and second latches connected to corresponding bit lines, first latches configured to store data; a voltage generator configured to generate a program voltage; a row decoder configured to decode an address and select a word line; a control unit configured to control a programming operation including performing a plurality of program loops, each program loop comprising application of a program pulse to a word line selected by the row decoder and a plurality of sequential verify operations to verify respective program levels of a first row of memory cells connected to the selected word line, wherein the first latches of the page buffer are configured to inhibit or allow a programming operation on respective memory cells of the first row connected to bit lines corresponding to the first latches, and wherein the second latches are configured to select one of a plurality of verify results corresponding to each of the plurality of verify operations of a program loop.