1. An apparatus for identifying memory requests originating on remote I/O devices as non-cacheable in a computer system with multiple processors, comprising: a main memory coupled to a host bridge unit, wherein said host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in a plurality of processor caches in the computer system; a cache coherence directory coupled to said cache coherence controller; an I/O bridge unit coupled to said host bridge unit; and a peripheral bus coupled to said I/O bridge unit, said peripheral bus transmitting requests from a peripheral device coupled to the peripheral bus for data to the I/O bridge unit, wherein said I/O bridge unit transmits the request for data to the host bridge unit and asserts a sideband signal to the host bridge unit if the request is for non-cacheable data.