1. A processor comprising: a decode stage to decode a first instruction for a SIMD SM3 hash round slice, the first instruction specifying a round-slice portion of the hashing algorithm, an intermediate hash value input operand, a source data operand set, and a round constant operand set; and one or more execution units, responsive to the decoded first instruction, to: perform an SM3 hashing round-slice set of round iterations upon the source data operand set, applying the intermediate hash value input operand and the round constant operand set; and store a result of the first instruction in a SIMD destination register.