1. A processor comprising: a memory; one or more functional units coupled to the memory; and a page miss handler interruption module coupled to the memory and the one or more functional units and to: identify a first operation associated with a request for a page miss handler; identify a second operation associated with a current execution of the page miss handler; determine an age of the first operation and an age of the second operation; and interrupt the page miss handler based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.