1. A processor, comprising: an execution unit that executes an instruction by performing an operation indicated by said instruction utilizing at least a first operand and a second operand that each include one or more and at most M bit positions, each of said one or more bit positions having a bit value; and condition code logic that determines less than, greater than, and equal to condition code bits associated with said instruction concurrently with performance of said operation by said execution unit, wherein said condition code logic includes a single computation stage containing M combination elements that each receive as inputs individual bit values of a respective bit position within said first and said second operands, wherein each of said M combination elements of said single computation stage logically combines said individual bit values and outputs each of propagate, generate and kill signals for its respective one of said M bit positions, wherein propagate, generate and kill signals for all of said M bit positions collectively indicate values for said less than, greater than, and equal to condition code bits.