1. In a processor that executes coded instructions, a method for executing instructions comprising memory transactions comprising the steps of: registering the instructions in an instruction scheduling window; issuing the instructions from the instruction scheduling window for execution together with an instruction identification pointing to the instruction in the instruction window; speculatively broadcasting completion of each instruction at a preselected time after issue; and generating a replay signal indicating that a specified one of the instructions for which the completion was speculatively broadcast will not complete correctly; in response to the replay signal, reissuing at least one of the instructions.