1. A computer-readable memory storing a plurality of instructions for causing a processor to perform operations, the plurality of instructions comprising: instructions that cause the processor to detect a first fault raised by an operator of a first continuous execution processing (CEP) query relative to a first event from an event stream; instructions that cause the processor to invoke, in response to detecting the first fault, a first user-registered fault handler that has been registered with a CEP query processor; instructions that cause the processor to determine that the first user-registered fault handler caught and handled the first fault; instructions that cause the processor to cause the CEP query processor, in response to determining that the first user-registered fault handler caught and handled the first fault, to continue to execute the first CEP query without halting execution of the first CEP query; instructions that cause the processor to detect a second fault raised by an operator of a second CEP query relative to a second event from the event stream; instructions that cause the processor to invoke the first user-registered fault handler in response to detecting the second fault; instructions that cause the processor to determine that the first user-registered fault handler caught and handled the second fault; and instructions that cause the processor to cause the CEP query processor, in response to determining that the first user-registered fault handler caught and handled the second fault, to continue to execute the second CEP query without halting execution of the second CEP query, wherein the second CEP query differs from the first CEP query.