1. A multithreaded processor comprising: a plurality of threads, each thread of the plurality of threads capable of executing a corresponding task; a priority encoder configured to provide an indication of a lowest priority thread of the plurality of threads, the lowest priority thread having a lowest priority based on a corresponding priority of each thread of the plurality of threads, wherein the priority encoder is configured to receive the corresponding priority of each thread of the plurality of threads from a corresponding register of a plurality of registers; and an interrupt module configured to receive the indication of the lowest priority thread and to assign an interrupt to the one of the lowest priority thread.