1. A flipping algorithm to architectures of hardware realization for Lifting-based DWT, comprising the steps of: using lifting-based architecture as backbone, which comprising a plurality of basic computing units, and every output of computation node in a basic computing unit connecting to an input of a next basic computing unit; proceeding flipping steps by eliminating multipliers between interconnecting basic computing units to cut off the accumulation effect of timing delay, and the edge of cutset which along through said multipliers multiplying the reciprocal of the said coefficient of multipliers to eliminate said multipliers; and separating the computation node in the basic computing unit into 2 adders, which a first adder functioning with the other said basic computing units while a second adder being routed on said accumulation of timing delay.