1. A memory device comprising: a memory cell array comprising a multitude of memory cells, each memory cell having a selected access characteristic and operable to store information, each memory cell being accessible by an access signal in order to alter the stored information, each of the memory cells assigned to one of a multitude of blocks; a measuring unit coupled to the memory cell array and operable to identify the selected access characteristic of each of the multitude of memory cells in response to the access signal; an assignment unit coupled to the measuring unit and operable to assign a performance parameter to each block; and a performance memory unit coupled to the assignment unit, the performance memory unit adapted to contain the performance parameters assigned to the blocks.