1. An apparatus comprising: a first semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory includes circuitry associated with operation of the multiple memory cells; and a second semiconductor die including: a memory device interface; a memory controller interface; and periphery circuitry associated with the 3D memory; wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface, and wherein the memory controller interface is configured to be coupled to a memory interface of a memory controller die to enable communication of data and control information between the memory controller die and the 3D memory via the memory device interface and the memory controller interface of the second semiconductor die.