1. A memory device with a Low Pin Count (LPC) communication interface, comprising: a memory block, including: a write address decoder; a read address decoder; and a matrix of non-volatile memory cells and associated circuits for reading, modifying and erasing data in the memory block, the matrix divided into functionally independent, simultaneously accessible memory banks independently accessible by the write and read address decoders, each of the banks including a set of reference cells; an address bus; a data bus; and an interface block associated with the LPC communication interface and comprising an address block, a data block and a state machine to control the flow of data to and from the memory block over the address bus and data bus; wherein the data block includes a read data sub-block and a write data sub-block, the read data sub-block and write data sub-block each configured to be selectively enabled by the state machine.