1. A digital signal processing (DSP) circuit comprising: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; a second multiplier circuit; and a second arithmetic logic unit coupled to an output of the second multiplier circuit, wherein an output of the second arithmetic logic unit is coupled to the first arithmetic logic unit.