1. A memory circuit comprising: a first logic element having first and second terminals for providing a conductive path therebetween in response to a charge of a first polarity on a third terminal; a second logic element having first and second terminals for providing a conductive path therebetween in response to the presence of a charge of a second polarity on a third terminal thereof; said third terminals of said first and second logic elements being electrically coupled and further being electrically isolated from any other direct electrical contact; and said first logic element being further coupled to said second logic element through the electrical coupling of said second terminal of said first logic element to the first terminal of said second logic element.