1. A processing system comprising: a memory configured to store data in a plurality of pages, each page including a plurality of lines; a translation lookaside buffer (TLB); a memory cache including a plurality of cache lines, each one of the cache lines configured to store an address of one of the lines of memory, and to store a line of data located at said address; wherein the memory cache is configured to permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address presented to the memory cache; and wherein the memory cache is configured to permit a page attribute of a page located at said matching address to be retrieved from the memory cache without accessing the TLB in order to retrieve the page attribute, by further storing in each one of the cache lines a page attribute of the line of data stored in said cache line.