1. An integrated circuit memory device comprising: a page of memory cells arranged in a plurality of sub-pages of memory cells electrically coupled to a respective plurality of word lines, and a plurality of bit lines; a plurality of sub-page buffers electrically coupled to said plurality of bit lines for storing data read from said memory cells coupled to said plurality of bit lines; an I/O data buffer; each sub-page comprising a plurality of non-adjacent bit lines with memory cells coupled thereto, with said bit lines of each of sub-page interleaving bit lines of another sub-page; and read controller circuit coupled to said plurality of sub-page buffers for initiating a read operation to read data from a first sub-page of memory cells to an associated first sub-page buffer, while simultaneously reading data from a second sub-page buffer to said I/O data buffer.