1. A method of programming a non-volatile field programmable gate array (NV-FPGA), the method comprising: performing a block erase of a plurality of memory cells in the NV-FPGA; verifying that the block erase is successful; programming an upper page of at least one of the plurality of memory cells; verifying that the upper page programming is successful; programming a lower page of at least one of the plurality of memory cells; and verifying that the lower page programming is successful.