1. A circuit implementing a soft logical processing network comprising an interconnection of analog processing elements including soft logic gates, the soft logic gates comprising one or more soft Equals gates, each soft Equals gate comprising: a plurality of circuit parts, each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to convert the accepted voltage representation to a corresponding current signal representation of the soft logical quantity; a signal combination part coupled to the conversion sections of the plurality of circuit parts and configured to form a signal representation of the sum of the soft logical quantities represented in the current signals; an output for providing the signal formed by the signal combination part.