1. A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal, comprising: exponent logic, the exponent logic configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value; exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value, and wherein the exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the exponent output value, the first incremented exponent value, and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value.