1. A microprocessor, comprising: an instruction processing pipeline comprising a hash generator, which performs a concurrent speculative partial execution of a sequence of instructions, and produces a hash associated with execution of the sequence of instructions prior to commitment of execution of the sequence of instructions, for verification of the commitment of execution, configured to delay commitment of a terminal flow control instruction until a signal selectively authorizes commitment of the flow control instruction; an input port configured to receive the sequence of instructions comprising the terminal flow control instruction for execution in the instruction processing pipeline; logic configured to predict a flow control path of the sequence of instructions; prefetch logic configured to prefetch a reference signature associated with the predicted flow control path, corresponding to a verified hash of a verified sequence of instructions corresponding to the sequence of instructions, and to store the prefetched reference signature in a memory; logic configured to determine a correspondence between the hash and the reference signature and to generate the signal if there is a sufficient correspondence, the correspondence being determined insufficient at least if there is present in the sequence of instructions an unexpected flow control instruction between expected consecutive branch points; and logic configured to suspend further execution of the sequence of instructions, and to restore a known stable state or a previous checkpoint state if the signal is withheld.