1. A computer implemented method for throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory, the method comprising: executing, by the processor, instructions of a transaction comprising: determining whether the transaction is in throttling mode; and based on the transaction being in throttling mode, executing memory instructions in-program-order; and based on the transaction not-being in throttling mode, executing memory instructions out-of-program order.