1. In a digital computer capable of executing instructions and of the type having a program address register for holding the address of the next instruction to be executed, said instructions containing a function code portion and an operand address portion and at least one of said instructions being capable of causing a branch to a program address not in succession with the last program address and containing a main memory for storing said instructions, an apparatus for maintaining a history of which of said instructions have been executed by said digital computer, comprising: an instruction register for holding the instruction currently being executed by said digital computer and coupled to said main memory for receiving said instructions from said main memory; decoding means coupled to a portion of said instruction register containing said function code portion for decoding the instruction type and for providing a signal of a first binary significance when the function code portion of said instruction designates a branch instruction and of the opposite binary significance when said function code portion specifies a non-branch instruction; an incrementable program address register coupled to the portion of said instruction register holding said operand address portion for temporarily holding the address of the next instruction to be executed by said digital computer; a set of registers whose data inputs are coupled to the output of said portion of said instruction register containing said operand address portion each of said registers capable of holding the value of the contents of said operand portion of said instructions; an incrementable counter register whose output is coupled to said set of registers for selecting one of said set of registers based upon the value of the contents of said counter registers; and control means coupled to the output of said decoding means and to said set of registers for causing the contents of said operand portion of said instruction register to be stored in the selected one of said set of registers upon the execution of each instruction by said digital computer and for incrementing the value of the contents of said counter register whenever said decoding means produces a signal of said first binary significance; whereby a history is maintained of which of said instructions have been most recently executed.