1. A content addressable memory comprising: a plurality of word memories each for storing digital data in units of words; a plurality of match lines, each of said plurality of match lines associated with a corresponding one of said plurality of word memories; a data retrieval circuit adapted to receive retrieval data and to output match signals to at least one of said plurality of match lines associated with word memories storing one of a bit pattern and a portion of a bit pattern similar to that of the retrieval data; a plurality of weight memory circuits, each of said plurality of weight memory circuits associated with a corresponding one of said plurality of match lines; a weight alteration circuit for selectively altering weights stored in said plurality of weight memory circuits in accordance with a predetermined teacher-signal; and a selection circuit for selecting a match line associated with a weight memory circuit having a maximum weight, if a match signal appears on more than one of said plurality of match lines.