1. An apparatus comprising: a processing core in a multi-processing core system, the processing core being configured to: assemble an atomic program; and store the atomic program in a cache line; wherein the processing core is configured to verify that: each instruction in the atomic program accesses only data that was stored in the cache line before execution of the atomic program; and an atomic program execution unit configured to execute the stored atomic program as a single atomic memory transaction with a guarantee of forward progress.