1. A processor comprising: a first event counter to count events that occur during execution within the processor; event counter checkpoint logic communicably coupled with the first event counter, wherein the event counter checkpoint logic is to store, prior to a transactional execution of the processor, a value of the first event counter; a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted; event count restore logic communicably coupled with the first event counter, wherein the event count restore logic is to restore the first event counter to the stored value after the transactional execution is aborted; and tuning logic communicably coupled with the first event counter and the second event counter, wherein the tuning logic is to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.