1. A logic circuit comprising: a first differential logic unit receiving first and second differential logic signals on first and second pairs of differential input terminals, respectively, the first differential logic unit performing a first logical operation on the first and second logic signals, and in accordance therewith, producing first differential output signals on a first pair of differential output terminals; and a second differential logic unit, receiving the second differential logic signals on a third pair of differential input terminals coupled to the second pair of terminals on the first logic unit, and receiving the first differential logic signals on a fourth pair of differential input terminals coupled to the first pair of terminals on the first logic unit, the second differential logic unit also performing the first logical operation on the first and second logic signals, and in accordance therewith, producing second differential output signals on a second pair of differential output terminals coupled to the first pair of differential output terminals.