1. In a circuit arrangement for executing a first portion microinstruction sequence in data processing equipment wherein during the course of a primary sequence a jump to a subsequence occurs and at the end of the execution of said subsequence, a return jump to the primary sequence occurs for execution of a second portion of said microinstruction sequence, the improvement comprising: microinstruction storage means containing the primary sequence and the subsequence with the first portion of the primary sequence terminating with a jump instruction and an associated address code immediately followed by a second part of a two-part branching instruction and the subsequence terminating with a return jump code which forms the first part of said two-part branching instruction; a microinstruction register having two input terminals connected to said microinstruction storage means for respectively receiving said first and second parts of said branching instruction to indicate the instruction to be executed; central fixed cycle control means for producing first and second sequentially spaced output signals, said central fixed cycle control means being connected to the microinstruction register for effecting a transfer of the microinstruction currently in the microinstruction store to the microinstruction register, said microinstruction storage means and said control means first transferring said first part of said branching instruction to said microinstruction register simultaneous with the occurrence of said first output signal; a decoder responsive to the appearance in said microinstruction register of said first part of said branching instruction and producing first and second signals; said central fixed cycle control means being connected to said decoder and being responsive to said first signal to effect a maintaining of said first part of said two-part branching instruction in said microinstruction register; and return address register means responsive to said second signal from said decoder for effecting a transfer of said second part of said branching instruction to said microinstruction register simultaneous with the occurrence of said second output signal from said control means.