1. A contactless NOR-type memory array, comprising: a semiconductor substrate of a first conductivity type; a plurality of parallel isolation regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein a raised field-oxide film is formed on each of the plurality of parallel isolation regions and a thin tunneling dielectric layer is formed over each of the plurality of active regions; a plurality of word lines being formed alternately on said semiconductor substrate and transversely to the plurality of parallel isolation regions, wherein each of the plurality of word lines comprises an elongated control-gate layer being sandwiched between an interlayer dielectric layer formed on the top and an intergate dielectric layer formed at the bottom, and a plurality of integrated floating-gate layer being formed beneath said intergate dielectric layer; wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer being formed on said thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of each of two nearby raised field-oxide films; a plurality of common-source diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-source lines, wherein each of the plurality of common-source lines is situated in every two of said word lines and between a pair of said word lines; a plurality of common-drain diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-drain lines, wherein each of the plurality of common-drain lines is situated between a pair of said word lines formed between a pair of said common-source lines; a plurality of flat beds being located in the plurality of common-source lines, wherein said raised field-oxide films along each of the plurality of common-source lines are etched and each of the plurality of flat beds is formed alternately by the plurality of common-source diffusion regions and said etched raised field-oxide films; a plurality of first dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of flat beds, and a plurality of second dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films along the plurality of common-drain lines; a plurality of silicided common-source conductive layers being situated on the plurality of common-source lines, wherein each of the plurality of silicided common-source conductive layers is formed over said flat bed between a pair of said first dielectric spacers with a second thick-oxide layer formed on the top; a plurality of silicided common-drain conductive islands being situated on the plurality of common-drain lines, wherein each of the plurality of silicided common-drain conductive islands is formed between a pair of said second dielectric spacers and on a portion of each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films along each of the plurality of common-drain lines; and a plurality of bit lines being formed above the plurality of active regions and transversely to the plurality of word lines, wherein each of the plurality of bit lines is formed over a flat surface formed alternately by said second thick-oxide layer, said interlayer dielectric layer, and said silicided common-drain conductive island having a hard masking layer formed on a metal layer to simultaneously pattern and form said metal layer and said silicided common-drain conductive islands along each of the plurality of bit lines.