1. A network on chip (‘NOC’) comprising: integrated processor (‘IP’) blocks; and computer memory, the computer memory organized in pages and operatively coupled to one or more computer processors of the NOC, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification replacing bits in a cache index for a cache line of a memory page, the replaced bits added to a corresponding cache line tag to preserve the original address of the cache line.