1. An integrated circuit memory system comprising: an array of memory cells divided into a plurality of subarrays; sense amplifier means for sensing the contents of selected cells in said subarrays; compare logic means connected to said sense amplifier means for comparing the contents of said selected cells in said subarrays with compare input data; data output means connected to said sense amplifier means; decode means connected to said sense amplifier means for connecting the output of a selected one of said subarrays to said data output means; a plurality of write data input means each connected to array input data and to at least two of said subarrays; and a plurality of write select means each connected to one of said subarrays, wherein selected portions of said array input data may be simultaneously written into selected of said subarrays and compared with said compare input data.