1. A coprocessor operable to execute instructions in either I/O or memory mapped format presented by a processing system which includes a processor, a data bus, and an address bus, where, for an I/O format instruction, the processor provides the instruction opcode and the instruction operand over the data bus in successive bus cycles, and where, for a memory mapped format instruction, the processor provides the instruction opcode over the address bus and the instruction operand over the data bus in the same bus cycle, the coprocessor comprising: (a) a bus controller coupled to receive from the processor (i) control signals that identify whether an instruction provided by the processor is in I/O or memory mapped format, and (ii) memory mapped format instructions and I/O format instructions over the address and data buses; (b) the bus controller including I/O circuitry and memory map circuitry; and (c) a coprocessor core that executes instructions; (d) responsive to control signals for a memory mapped format instruction, the memory map circuitry generates associated translated control signals for an I/O format instruction; (e) responsive to control signals from the coprocessor for an I/O format instruction, the I/O circuitry provides the corresponding I/O format instruction received by the bus controller to the coprocessor core for execution; and (f) responsive to translated control signals from the memory map circuitry, the I/O circuitry provides the corresponding memory mapped format instruction received by the bus controller to the coprocessor core for execution.