1. A parallel processing array comprising a plurality of processing elements (PEs), each processing element receiving a common instruction and comprising: a multiplexer for receiving said common instruction; an arithmetic logic unit, connected to said multiplexer, for processing the received instruction in association with an accumulator and a flag register; characterized in that one or more of the processing elements in the processing array further comprises a storage element having at least one storage location, the storage element configured to be indirectly addressable by the received instruction, thereby enabling the processing of data dependent operations to be performed.