1. A data processing system comprising a central processor unit having a processor operating time cycle and at least one memory unit having a memory operating time cycle, said system including means for providing a central processor base timing signal; means responsive to said central processor base timing signal for deriving central processor timing control signals for controlling the the processor operating time cycle of said central processor unit; memory timing means including means responsive to said processor base timing signal for providing a memory base timing signal which has a predetermined out-of-phase relationship with said processor base timing signal; and means responsive to said memory base timing signal for deriving memory timing control signals for controlling the operating time cycle of said memory unit; whereby said central processor unit and said memory unit are adapted to operate in controlled timing relationship with each other independently of the duration of the memory operating time cycle of said memory unit.