1. A memory device, comprising: an array of memory cells arranged in a plurality of memory blocks; and control circuitry, wherein the control circuitry is configured to maintain an erase cycle counter value corresponding to each memory block of the plurality of memory blocks of the memory device, store each erase cycle counter value in a memory block of the plurality of memory blocks which is different than its corresponding memory block, adjust a programming voltage in response to a particular erase cycle counter value corresponding to a particular memory block, and perform an erase cycle counter value error detection operation on each erase cycle counter value.