1. In a mechanism for renaming a current set of logical registers associated with a current set of operations to a current set of physical registers of an extended register set, an apparatus for processing size mismatches, said apparatus comprising: array means for renaming said current set of logical registers to said current set of physical registers, wherein said logical registers and said physical registers have partial widths, wherein said logical registers have logical register sizes and said physical registers have physical register sizes; size comparison means, coupled to said array means, for comparing said logical register sizes to said physical register sizes; and partial width stall means, coupled to said size comparison means and said array means, for stalling said array means when a first logical register is of larger size than a corresponding physical register to which said first logical register is renamed.