1. A processor comprising: a register file including a first packed data register and a second packed data register; register renaming circuitry to perform renaming of physical registers within the register file; a decoder to decode an instruction; scheduling circuitry to queue operations corresponding to the instruction for execution; and execution circuitry to execute the operations corresponding to the instruction to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register, each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits.