1. A microprocessor for executing bytecode compiled from an objected oriented programming language in hardware comprising: a RISC processor, the RISC processor configured to be an embedded processor; a first module to execute a set of instructions in bytecode in the RISC processor; a RISC module to execute a set of instructions as microcode in the RISC processor, said RISC module including means for handling interrupts and a flexible hardware interface to control highly specialized peripheral devices; and a datapath in the RISC processor shared by both modules, said datapath including a register file shared by both modules, said register file having a plurality of elements shared by the first module and the RISC module, the first module seeing a first portion of the plurality of elements a circular operand stack and a remaining portion of the plurality of elements as storage registers, the RISC module seeing the plurality of elements as a register file.