1. A circuit, comprising: a memory circuit to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space, wherein the LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, the indicator field is indicative of an attribute of a physical address associated with a logical address; and a controller circuit to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT and receive a physical address that maps to a logical address, compress the physical address, and determine an indicator field of a first level entry corresponding to the logical address based on a size of the compressed physical address.