1. A method of performing cache injection in a processor system, comprising: monitoring, at a cache, addresses on a bus in response to a cache injection instruction, wherein the cache injection instruction causes a cache controller to modify a grab coherency bit of a coherency status field included in a cache directory to indicate that cache injection is to be employed to provide input/output data to a data block of the cache that is associated with the grab coherency bit; and acquiring ownership of input/output data on the bus at the cache when an address on the bus, that is associated with input/output data, corresponds to an address of the data block associated with the cache injection instruction.