1. A system for dynamically adjusting the fetch paths in a multi-level cache based upon application data fetch characteristics or by a prespecified miss threshold comprising: a. a central processing unit (CPU) for fetching data from memory or cache; b. a main memory for storing data for being fetched by the CPU; c. at least one cache, connected via a path between the CPU and the main memory, for storing data for being fetched by the CPU and for reducing the average time to fetch data stored in the main memory; d. a hit/miss rate tracker connected to the at least one cache for tracking the cache misses on the at least one cache; and e. a bypass path to bypass the at least one cache when the miss rate exceeds the prespecified threshold.