1. An apparatus, comprising: a processor coupleable to a shared memory that is shared by one or more other processors, wherein the processor is operating in a virtual machine mode and is configured to execute a section of code that includes a plurality of memory access operations to the shared memory as an atomic transaction relative to the one or more other processors; and wherein the processor is configured to abort the transaction in response to identifying that at least one of the plurality of memory access operations includes a disallowed instruction, the disallowed instruction of a type that is executed in the virtual machine mode and a native computing environment and that has a different operation during execution in the virtual machine mode than during execution of the disallowed instruction in the native computing environment.