1. A computer having a processor programmed to execute processes comprising: a processing unit simulator; at least one hardware component simulator; a system bus simulator in communication with the processing unit simulator and the at least one hardware component simulator; and a bus monitoring unit (BMU) configured to monitor traffic between the processing unit simulator and the at least one hardware component simulator, wherein the BMU is further configured to record bus usage data in a non-transient computer readable storage medium, wherein the bus usage data includes a total transaction time representing how long the at least one hardware component simulator takes to process a plurality of tasks each having an individual transaction time, wherein each of the individual transaction times correspond to one of a high frequency task or a low frequency task, wherein each low frequency task corresponds to time spent performing input/output operations and each high frequency task corresponds to time spent utilizing a component having a scalable frequency, wherein at least one individual transaction time is adjusted by a bias value, and wherein the processor is configured to adjust a frequency of at least one of the processing unit simulator and the at least one hardware component simulator in response to a ratio of the transaction times for one of the high frequency tasks or the low frequency tasks to the total transaction time.