1. A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell in the matrix having up to four immediately adjacent orthogonal nearest neighbor logic cells in the same row or column as that logic cell and up to four immediately adjacent diagonal nearest neighbor logic cells located along either of two diagonals of logic cells including that logic cell, each logic cell having direct cell-to-cell input connections to at least one of its immediately adjacent orthogonal nearest neighbor logic cells and also having direct cell-to-cell input connections to at least one of its immediately adjacent diagonal nearest neighbor logic cells, each logic cell further having direct cell-to-cell output connections to the same set of nearest neighbor logic cells as its direct cell-to-cell input connections, each logic cell having first means for selecting one of said orthogonal direct cell-to-cell input connections and second means for selecting one of said diagonal direct cell-to-cell input connections.