1. A parallel processor, comprising: a Processing Element (PE) array having a plurality of PEs; a local memory directly connected to the PE array; a floating-point accumulator array having a plurality of accumulators connected to the PE array and accelerating a floating-point addition operation; and a control unit for reading an instruction from an external memory, broadcasting the instruction to the PEs of the PE array, and addressing the local memory when a PE communicates with the local memory.