1. A content addressable memory (CAM) device, comprising: a CAM array including a plurality of rows, each row of the plurality of rows including one or more CAM cells coupled to a match line of a plurality of match lines; a multiple match detection circuit coupled to the plurality of match lines configured output to generate a multiple match signal for a first compare operation; a priority encoder; a plurality of multiple match resolution (MMR) circuits configured to store a match result from the first compare operation; a plurality of match latches configured to store a match result from a second compare operation that commenced prior to generation of the multiple match signal for the first compare operation; and an MMR controller configured to generate a stall signal that selectively stalls search operations in the CAM array in response to the multiple match signal indicating that a multiple match condition is detected, wherein the plurality of MMR circuits is further configured to forward the match result from the first compare operation to the priority encoder when the stall signal is in a first state, and the plurality of match latches are configured to forward the match result from the second compare operation to the priority encoder when the stall signal is in a second state.