1. A memory subsystem with fault isolation, comprising: a first data bus routing data groupings in a lower 72 bits to a first memory expander; a second data bus routing data groupings in an upper 72 bits to a second memory expander; a first memory module receiving all of the data groupings in the lower 72 bits of each memory expander; a second memory module receiving all of the data groupings in the upper 72 bits of each memory expander; and wherein a failure in any one or more bytes in an Error Correction Code (ECC) word indicate failures in the computer memory system.