1. A data processing circuit, the circuit comprising: a data detector circuit operative to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output, wherein the detected output includes a number of non-binary symbols; a first symbol constrained arrangement circuit operative to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output, wherein the bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output; and a second symbol constrained arrangement circuit operative to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set, wherein the bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.