1. A data processor having a clustered architecture that comprises an instruction cache and a plurality of clusters, each of said clusters comprising an instruction execution pipeline, each said instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing at least one of a plurality of execution steps associated with instructions being executed by said clusters, said data processor comprising: a power-down controller that monitors each said instruction execution pipeline and said instruction cache to identify power-down conditions associated therewith, and that, in response to an identified power-down condition, at least one of: (i) bypasses performance of at least a portion of subsequent ones of said N processing stages associated with an executing instruction; (ii) powers down said instruction cache; and (iii) powers down said data processor.