1. A method of executing instructions in a processing core of a microprocessor, the method comprising: in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain; synchronizing the input from the second clock domain with the first clock domain; if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction; and otherwise performing the instruction.