1. A computing device comprising a memory and one or more functional units, wherein the computing device is configured to implement a multi-layer control structure comprising: a data structure layer comprising a local high speed memory, wherein the local high speed memory includes one or more Variables; a mentor layer comprising one or more mentor circuits, wherein at least one of the mentor circuits is configured to at least partially control an action associated with at least one of the one or more Variables in the local high speed memory; and instruction interpretation/control layers comprising one or more control circuits configured to interpret one or more instructions or control one or more operations by one or more functional units.