1. A system-on-chip comprising: a central processor; a video processor; an audio processor; a graphic processor; and a coherent memory module configured to handle data communications between the central processor, the video processor, the audio processor, and the graphic processor as accesses to memory, the coherent memory module including: a plurality of first caches, each of the first caches associated with one of the central processor, the video processor, the audio processor, and the graphic processor; a second cache communicatively coupled to each of the plurality of first caches; and a cache controller configured to control the data communications from one or more of the central processor, the video processor, the audio processor, and the graphic processor to other of the central processor, the video processor, the audio processor, and the graphic processor by controlling read and write operations between the plurality of first caches and the second cache.