1. An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads, the apparatus comprising for each thread: a buffer, configured to store fetched instructions of the thread, having an indicator for indicating which of said fetched instructions in said buffer have already been dispatched for execution; an input, for indicating that one or more of said already-dispatched instructions in said buffer have been flushed from execution; and control logic, coupled to said buffer and said input, configured to update said indicator to indicate said flushed instructions are no longer already-dispatched, in response to said input, thereby enabling the processor to re-dispatch said flushed instructions from said buffer to avoid re-fetching said flushed instructions.