1. A computer processor comprising a plurality of functional units, where each functional unit is coupled to a register file for reading and writing operands; an instruction fetch unit coupled to receive instructions from a memory system; an instruction decode and dispatch unit coupled to the instruction fetch unit for receiving instructions therefrom and coupled to the functional units to dispatch commands to the plurality of functional units; a resource status flags register wherein particular functional units may be marked enabled or disabled for use; wherein the instruction fetch and decode unit checks the resource status flags register prior to dispatching commands and dispatches commands only to those functional units marked enabled in the resource status flags register; and wherein the instruction fetch and decode unit is capable of stalling if insufficient resources are available, and of dispatching remaining commands in a following cycle.