1. A method comprising: identifying during non-built-in-self-test (non-BIST) operation of an integrated circuit a first portion of a cache memory for servicing access requests from a random access generator, and identifying a second portion of the cache memory that cannot service access requests from the random access generator, wherein the random access generator is implemented with built-in self-test hardware that includes a random number generator to test memory locations of an integrated circuit during a BIST operation using random numbers, and wherein the non-BIST operation is not related to testing of the cache memory; determining during the non-BIST operation, that a security sensitive operation is to be executed at a processor core that includes the cache memory; and in response to determining that the security sensitive operation is to be executed, using the first portion of the cache memory during non-BIST operation to service access requests generated by the random access generator during execution of the security sensitive operation.