1. A method for testing the timing of an integrated circuit design comprising: on a computer device having a processor configured to implement a simulator to test timing for the design for a plurality of conditions for each net in the design: identifying at least one of RC corners, library files, aggressor net constraints, and aggressor timing windows of each of two or more conditions of the plurality of conditions; comparing the at least one of RC corners, library files, aggressor net constraints, and aggressor timing windows of the two or more conditions; grouping the two or more conditions into a cluster based on the comparison, wherein, for the cluster: loading, into the simulator, (i) RC parameters and (ii) one or more library files for the net; performing, with the simulator, an RC reduction according to one or more restrictions as required by the two or more conditions in the cluster; loading, into the simulator, a plurality of input slews; and calculating, with the simulator, for at least one condition of the two or more conditions in the cluster, a timing delay and an output slew for the net based on the plurality of input slews, wherein a result of at least one calculation is stored in memory and at least one of the timing delay and the output slew of the stored result is used to represent at least one of a timing delay and an output slew of another condition of the two or more conditions in the cluster.