1. A method for operating an instruction decode unit, the method comprising: in an instruction decode unit of a processor: receiving in an instruction buffer a plurality of processor instructions including multiple non-branch processor instructions and multiple branch processor instructions, wherein the plurality of instructions have a relative sequencing defined by a program order; grouping at least first and second non-branch processor instructions and at least first and second branch processor instructions of the plurality of processor instructions into a group of processor instructions, wherein the first branch processor instruction is intermediate the first and second non-branch instructions in program order and wherein the group excludes a third non-branch processor instruction in the instruction buffer that is intermediate the first branch processor instruction and the second non-branch instruction in the program order; and conveying the group of processor instructions to at least one issue queue of the processor.