1. An apparatus for detecting a predetermined bit pattern in data traffic comprising a plurality of data packets, the data packets having a header portion and a payload portion, the apparatus comprising: a processing logic for receiving the data traffic in real-time and for dividing the data packets in the data traffic into bit sequences; and an Internet Protocol (IP) co-processor unit having a bit pattern storage memory array, in which one or more predetermined bit patterns are stored, the IP co-processor unit comprising means for identifying, from within at least the payload portion, each data packet that contains a bit sequence that matches a predetermined bit pattern entry within the memory array.