1. An integral circuit of a type, comprising: a) a first logic block, the first logic block being generated by synthesizing a first code component and including one or more first copies of a static logic circuit, the static logic circuit being independent of an uncertainty, the uncertainty being an unknown first number of one or more clock cycles needed for each of a plurality of input data to travel from an input register to an output register while coding; and b) a second logic block, the second logic block being generated by synthesizing a second code component and including one or more dynamic logic circuits, the dynamic logic circuits being dependent on the uncertainty and changeable by a synthesizer to resolve the uncertainty, and the second logic block being interconnected with the first logic block.