1. An apparatus, comprising: a memory array comprising a plurality of memory planes, wherein each of the plurality of memory planes comprises a plurality of memory cells; and a controller configured to receive a group of memory command and address pairs, wherein each memory command and address pair of the group of memory command and address pairs is associated with a respective memory plane of the plurality of memory planes, the internal controller configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group.