1. An interface between a central processing unit (CPU) and a plurality of coprocessors for transferring data from the CPU to one of the plurality of coprocessors, comprising: a first set of interconnects configured to transfer a first data instruction and a second data instruction from the CPU to the one of the plurality of coprocessors simultaneously; a second set of interconnects configured to tranfer data, associated with said first and said second data instructions, out-of-order; and a third set of interconnects configured to indicate to the one of the plurality of coprocessors a relative data order for execution of said first and said second data instructions.