1. A memory array having a plurality of charge trapping dielectric memory devices, comprising: a substrate having a first bit line and a second bit line formed therein and a body region interposed between the first and the second bit lines; a first dielectric layer disposed on the body region; a dielectric charge trapping layer disposed on the first dielectric layer; and a second dielectric layer disposed on the dielectric charge trapping layer, the first dielectric layer and the dielectric charge trapping layer extending beyond the second dielectric layer in a direction parallel to a top surface of the substrate.