1. A memory device, comprising: an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode; a plurality of word lines each connecting the first signal electrodes of a row of memory cells; and a plurality of bit lines each connecting the second signal electrodes of a column of memory cells, wherein the nano-layer comprises optical nano elements.