1. A method of coordinating execution of instructions in a processor that allows the instructions to execute out-of-order, the method comprising: decoding a particular instruction defined in accordance with an instruction set of the processor; and introducing into a stream of executable operations a corresponding helper sequence of instructions corresponding to the particular instruction, wherein the corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register (1) that is not actually employed as a register source or target for an operation performed by execution of the first artificial dependency instruction and (2) that is used as a register source or target by another instruction, in said corresponding helper sequence, preceding said first artificial dependency instruction wherein said first artificial dependency instruction is positioned in said helper sequence to coordinate execution of said helper sequence.