1. A processor comprising: a plurality of multithreaded cores, wherein one or more of the multithreaded cores are to perform out-of-order instruction execution for a plurality of threads, and wherein the one or more of the multithreaded cores comprise: instruction fetch logic to fetch a plurality of instructions of one or more of the threads, an instruction decode unit to decode the instructions, register renaming logic to rename one or more registers for the instructions within a register file, an instruction cache to cache one or more of the instructions to be executed, a data cache to cache data for the instructions, a level 2 (L2) cache unit to cache one or more of the instructions and data for the instructions, and an execution unit to execute a first instruction among the instructions to test a status of a transactional execution region, wherein, to execute the first instruction to test the status of the transactional execution region, the execution unit is further to determine that the first instruction is within a context of the transactional execution region and, in response, set a flag register to a value indicating that the first instruction is within the context of the transactional execution region.