1. A method for issuing instructions in a processor, comprising: storing a first instruction in a first queue position in an issue queue, the issue queue storing each of a plurality of instructions in a corresponding queue position, the plurality of instructions including at least a second instruction, the first instruction including a target instruction tag and at least a source instruction tag, the source instruction tag specifying a logical register that stores source operand data; storing the target instruction tag associated with the first instruction in a table, wherein the table stores a plurality of target instruction tags, each target instruction tag in the plurality of target instruction tags being associated with a corresponding one of the instructions, each stored target instruction tag specifying a logical register that stores a target operand; and upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with the second instruction, that the first instruction is dependent on the second instruction, associating, with the second instruction, a pointer to the first instruction in the first queue position, wherein the pointer is used to wake up the first instruction upon issue of the second instruction.