1. An instruction processing method for decoding fetched instructions in parallel within a template-type instruction processing system which includes a variable length instruction set, comprising the steps of: defining a set of elementary instructions, each of which embodies a minimum length instruction which can no longer be divided in an instruction set level architecture of a data processing system; defining a set of parallel instructions, each of which embodies a different combination of two or more elementary instructions which can be processed in parallel; fetching, in an instruction fetch mechanism, an instruction string to be executed from an instruction store and transfer means, the fetched instruction string comprising at least one of the elementary instructions or the parallel instructions; comparing the fetched instruction string to the set of parallel instructions in order to determine whether a set of instructions in the fetched instruction string matches any of the parallel instructions in the set of parallel instructions; when a set of instructions in the fetched instruction string matches any one of the parallel instructions in the set of parallel instructions, issuing each of the elementary instructions in the matched set of instructions of the fetched instruction string to a corresponding processing unit, and processing each of the elementary instructions in the matched set of instructions in parallel in the processing units; and when a set of instructions in the fetched instruction string do not match any one of the parallel instructions in the set of parallel instructions, individually executing the elementary instructions in the fetched instruction string in the order in which they are received from the fetch mechanism.