1. A processor node configured to operate within an array of processor nodes in a multiprocessor system, the processor node comprising: a processor configured to execute instructions and including a processor network switch; a first input/output interface configured to process communications with an external device outside the array of processor nodes; a first inter-processor interface configured to process communications with a second processor node within the array of processor nodes; and a selection circuit coupled to the first input/output interface and the first inter-processor interface and further coupled to one of the external device and the second processor node, the selection circuit configured to select between the first input/output interface and the first inter-processor interface, based on whether the selection circuit is further coupled to the external device or to the second processor node, wherein the processor, the first input/output interface, the first inter-processor interface, and the selection circuit are included within the processor node.