1. A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, busses for interconnecting the arithmetic/logic unit and the registers, means for providing instruction words to an instruction register, and control means having a control means output which is connected to said arithmetic/logic unit, said busses, and said registers, said control means for generating commands for controlling operation of the arithmetic/logic unit and accessing the busses and registers in response to said instruction words applied to an input of the control means from the instruction register; and clocking means coupled to said arithmetic/logic unit, said registers, said busses and said control means for defining repetitive mirocode state times, all within the integrated circuit, and wherein the control means includes a read-only-array having an address input and a multi-bit microcode command output connected to said control means output, the control means including means for producing a multi-bit microcode command at said control means output during each microcode state time, and the control means includes addressing means receiving said instruction word from said input and applying sequences of addresses to said address input, one address in each microcode state time, said sequences beng selected by said instruction word whereby each sequence defines an operation which is determined by such instruction word, and each sequence including a plurality of microcode states, said addressing means providing said sequences of addresses in response to said instruction word in the instruction register whereby said addressing means for each said sequences selects the addresses of a first subset of microcode states, which defines the instruction operand mode, from a first set of microcode states which defines a plurality of operand addressing modes, and then selects the addresses of a second subset of microcode states, which defines the arithmetic/logic function of the instruction, from a second set of microcode states defining a plurality of arithmetic/logic functions, a plurality of the addresses of the subsets of the first set sharing a single address which defines a single microcode state, the operand addressing modes providing alternative methods of selecting operands for application to inputs of the arithmetic/logic unit.