1. A system for managing a plurality of threads in a processor having a plurality of processing units, comprising: a) a processor configuration manager that retrieves information descriptive of components of the processor and creates a graph structure including a plurality of nodes, the graph structure representative of at least a portion of the information; and b) a thread scheduler that associates at least one thread of the plurality of threads with at least one processing unit of the plurality of processing units by traversing the graph structure, based on the information.