1. Apparatus for processing data comprising: an instruction processing pipeline having a plurality of pipeline stages; at least one error detector, coupled to a pipeline stage of said instruction processing pipeline and responsive to at least one signal value within said pipeline stage, configured to detect a processing error associated with an erring program instruction within said pipeline stage; error recovery circuitry, coupled to said at least one error detector and responsive to detection of a processing error by said error detector, configured to initiate an error recovery operation, wherein said pipeline stage, includes a first main storage element and a second main storage element, configured to sample a signal for respective program instructions at respective operational sampling points in an alternating sequence, and said error recovery operation includes replacing an incorrect signal value stored in one of said first main storage element and said second main storage element with a correct value subsequent to said operational sampling point while a signal value for a following program instruction remains stored in the other of said first main storage element and said second main storage element; and thread control circuitry, coupled to said instruction processing pipeline and responsive to program instructions from a plurality of different program threads to control supply of an interleaved stream of program instructions from different program threads, configured to store signal values from a first program thread in said first main storage element, and signal values from a second different program thread in said second main storage element, wherein a thread identifying signal accompanies a program instruction passing along said instruction processing pipeline and is coupled to said first main storage element and said second main storage element to gate sampling thereby of said signal at said operational sampling point.