1. An apparatus for parallel processing comprising: a plurality of processing elements (PEs); a control processor merged with one PE of the plurality of PEs to form a merged processor sharing a control function and a PE function of the one PE, the control function for fetching and distributing single instruction multiple data (SIMD) instructions to the control function and the plurality of processing elements (PEs), wherein the merged processor shares execution units between the control function and the PE function and one of the SIMD instructions is a thread start (Tstart) instruction which is received and interpreted by the control function and causes the control function to pause its instruction fetching and enter a hold state; a local PE instruction memory (PE Imem) associated with each PE and containing local PE instructions for execution locally on the associated PE; a local PE very long instruction word (VLIW) memory associated with each PE and containing at addressable locations local PE VLIWs each having a plurality of slot instructions for execution in parallel locally on the associated PE; and a VLIW memory (VIM) controller in each PE that is used to select between the distributed SIMD instructions, the local PE instructions fetched from the local PE Imem, and the local PE VLIWs fetched from the local PE VLIW memory, wherein each PE is initialized to receive the distributed SIMD instructions and wherein each PE receiving the Tstart instruction causes instruction path selection logic to switch from receiving the distributed SIMD instructions to fetching the local PE VLIWs, each VLIW fetched in response to a fetched local PE instruction, wherein a PE hold signal is activated in response to predecoding a thread stop instruction in a predecode pipeline stage prior to decoding and execution pipeline stages used for the local PE instructions and wherein the thread stop instruction is specified to execute one or more PE instructions in the shadow of the thread stop instruction.