1. A memory cell system comprising: (a) feedthru amplifier comprising an input port and an output port; and (b) feedback amplifier comprising an input port, an output port, and a control port; wherein said input port of said feedthru amplifier is electrically connected to said output port of said feedback amplifier; said output port of said feedthru amplifier is electrically connected to said input port of said feedback amplifier; said control port of said feedback amplifier modulates the drive strength of said output port of said feedback amplifier permitting said output port of said feedthru amplifier to be written to a logic state that is the complement of the control port state.