1. A computer system comprising: a memory; and a processor coupled to said memory, said processor comprising: a fused-unfused floating point multiply-add (FMA) module, said fused-unfused FMA module for receiving a first multiply term, a second multiply term, and an addition term, wherein in response to said processor receiving a single unfused multiply-add opcode, said fused-unfused FMA module generates an unfused multiply-add rounding result, and wherein in response to said processor receiving a single fused multiply-add opcode, said fused-unfused FMA module generates a fused multiply-add rounding result.