1. A computer-implemented process performed by a computer including a processing device comprising a plurality of processors, comprising: periodically receiving into a data structure in memory for an interrupt router, from the plurality of processors, data indicating an amount of processing time consumed by the plurality of processors due to executing interrupt handlers; the interrupt router determining a load on the processing device due to interrupt handling by the plurality of processors based on at least the received data; and assigning, by the interrupt router, each interrupt source of a plurality of interrupt sources to a selected respective processor from among the plurality of processors, the plurality of interrupt sources having a corresponding plurality of interrupt handlers based on at least a function of the determined load so as to distribute the load among the processors while maximizing a number of processors that are idle; and repeating determining the load and assigning each interrupt source based on the periodically received data.