1. A method for verification of a retimed integrated circuit logic design using liveness checking as set forth by instructions executed by a computer system, comprising: assigning, by one or more instructions executed by the computer system, a liveness gate to a liveness property for an original netlist; assigning, by one or more instructions executed by the computer system, a fairness gate to a fairness constraint for the original netlist, where the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate; retiming by one or more instructions executed by the computer system, using a retiming engine, the original netlist to provide a retimed netlist, wherein the liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate; performing, by one or more instructions executed by the computer system, verification analysis on the retimed netlist; and returning as an output of the computer system, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist.