1. A processor comprising: instruction fetch circuitry to fetch a memory fence (MFENCE) instruction, a memory load fence (LFENCE) instruction, and a memory store fence (SFENCE) instruction; instruction decoder circuitry to decode the MFENCE instruction, the LFENCE instruction, and the SFENCE instruction; and memory ordering unit circuitry to: prevent load instructions and store instructions and cache line flush instructions that follow the MFENCE instruction in program order from being dispatched until all load instructions and store instructions and cache line flush instructions previous to the MFENCE instruction in the program order have been performed, not prevent cache line flush instructions that follow the LFENCE instruction in the program order from being dispatched until all cache line flush instructions previous to the LFENCE instruction in the program order have been performed, and fence store instructions that follow the SFENCE instruction in the program order relative to store instructions previous to the SFENCE instruction in the program order, but not prevent cache line flush instructions that follow the SFENCE instruction in the program order from being dispatched until all cache line flush instructions previous to the SFENCE instruction in the program order have been performed.