1. A processor, comprising: decode logic coupled to an instruction cache; a micro-sequence vector table coupled to the decode logic, wherein the micro-sequence vector table comprises one entry for each bytecode in an instruction set of the processor, wherein all fields in an entry are unique to a bytecode corresponding to the entry; and a storage unit coupled to the decode logic, wherein the decode logic is configured to: obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache, use the single bytecode to locate the entry corresponding to the single bytecode in the micro-sequence vector table, cause the processor to directly execute the single bytecode using the immediate operand when a first field in the entry indicates that the single bytecode is to be executed, and, when the first field in the entry indicates that a micro-sequence is to be executed instead of the single bytecode and a second field in the entry indicates that the single bytecode requires the immediate operand, obtain the immediate operand from the instruction cache, modify the immediate operand when a third field in the entry indicates that the immediate operand is to be modified, and store the modified immediate operand in the storage unit for use by the micro-sequence.