1. A method for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, comprising: identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test; running statistical timing to calculate a margin to be applied to the paths; updating design specifications for the margin to be applied to the paths; and optimizing chip logic based on the updated design specifications.