1. A system, comprising: a processor, comprising: a prediction component configured for predicting whether a load instruction in the system is associated with an instruction pipeline hazard; and an execution component configured for determining whether a memory address is calculated for the load instruction, for allocating the load instruction to a queue buffer in the system in response to a first determination that the memory address is calculated for the load instruction and a second determination that the prediction component predicts that the load instruction is not associated with the instruction pipeline hazard, and for cancelling execution of the load instruction in response to the second determination that the load instruction is not associated with the instruction pipeline hazard and a third determination that the queue buffer is associated with a memory order violation.