1. An apparatus for providing multi-cycle memory access in a system with a microprocessor having a memory, said apparatus comprising: a test data input for inputting test instructions and data; a test data output for outputting data; a program memory interface circuit for controlling access to said microprocessor memory; a wait-state counter coupled to said program memory interface circuit for counting a number of wait-states elapsed since initiation of a memory access with a counting value loaded into said wait-state counter by said program memory interface circuit; a wait-state counter underflow signal output line from said wait-state counter and selectively coupled to said test data output for outputting completion of said wait-state counter's count, signifying completion of said memory access; and a scan boundary test circuit, said test circuit in turn comprising: an instruction register scan chain coupled to said test data input, said program memory interface circuit and selectively coupled to said test data output, said instruction register scan chain adapted to receive a test instruction and selecting a data register scan chain based on said test instruction; and at least one data register scan chain coupled to said test data input, said program memory interface circuit and selectively coupled to said test data output, said selected data register scan chain adapted to receive test data from said test data input, initiate said memory access, wait for assertion of said wait-state counter underflow signal output line, and output data from said memory access.