1. A method for reducing power dissipation in a clock distribution circuit for a programmable IC, comprising: a) receiving a first clock; b) generating from the first clock a second clock, programmably having either half the frequency of the first clock or the same frequency as the first clock; and c) distributing the second clock but not the first clock to a plurality of flip-flops in the circuit, the flip-flops operating at twice the frequency of the distributed clock in a first programmed state, and operating at the same frequency as the distributed clock in a second programmed state.