1. A processor comprising: a prediction circuit configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution, wherein a PSTLF event occurs for the first load instruction when a plurality of bytes that are to be written to a target of the first load instruction include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation, wherein the prediction circuit comprises a prediction memory and a control circuit coupled to the prediction memory, and wherein the control circuit is coupled to receive an indication from a load/store unit that the PSTLF event has been detected during execution of a first load operation corresponding to the first load instruction, wherein the control circuit is configured to allocate an entry in the prediction memory to correspond to the first load instruction responsive to the indication; and a circuit coupled to the prediction circuit and coupled to receive the first load instruction, wherein the circuit is configured to generate one or more load operations responsive to the first load instruction and further responsive to the prediction from the prediction circuit, wherein the load operations are to be independently executed in the processor to execute the first load instruction, and wherein each load operation accesses a different portion of the plurality of bytes, and wherein a first number of the load operations generated in response to the prediction indicating that the PSTLF event will occur is greater than a second number of the load operations generated in response to the prediction indicating that the PSTLF event will not occur.