1. A data processing system having main storage means comprising addressable locations containing data and instructions, a central processor including an instruction register connected to the main storage means for receiving and storing instructions including a first binary field representing an address displacement value and indentifying a particular addressable main storage location, one or more second binary fields each identifying one of a predetermined number (n) of instruction addressable general purpose registers, and an operation field specifying an operation to be performed, one operation being a load instruction effecting transfer of data to a specified one of said instruction addressable general purpose registers, and transfer means responsive to a central processor generated main storage address for fetching and transferring to the central processor the data and instructions, the improvement allowing access to a larger number (m) of general purpose registers without increasing the size of said second binary fields comprising: a plurality m of hardware registers in the central processor for storing data transferred from the main storage means in the central processor, including access means for effecting read-in or read-out of data in said plurality of hardware registers, said plurality m being greater than the predetermined number of instruction addressable general purpose registers identified by the one or more second binary fields of an instruction, and register renaming means, including means connected and responsive to the first binary field and the second binary fields of a load instruction, and connected to said access means of said plurality m of hardware registers, said register renaming means controlling further access to one of said plurality m hardware registers in response to identification of one of said n instruction addressable general purpose registers.