1. A method of expanding a library of known structured ASIC equivalents of FPGA logic functions comprising: computing an index value for a logic function in an FPGA logic design; using the index value to determine whether the library already contains any structured ASIC equivalents of the logic function; determining an ASIC equivalent of the logic function; and adding the ASIC equivalent from the determining to the library if it is a first equivalent of the logic function or if it is different from and no less efficient than any equivalent of the logic function that is already in the library.