1. A computer implemented method for managing, by a processor, cache line evictions from a cache during transactional execution of a transaction, the method comprising: based on initiating transactional execution of a memory data accessing instruction, by the processor, fetching the memory data from a memory location, at a memory address specified by the instruction, the memory data to be loaded as a new line into a cache entry of the cache; based on determining that a threshold number of cache entries for the transaction in the cache have been marked as read-set cache lines, determining whether a read-set cache line can be replaced, comprising: identifying, in the cache, a cache entry that is a read-set cache line for the transaction, the identified cache entry containing memory data from a memory address within a predetermined non-conflict address range; invalidating the identified cache entry; loading the fetched memory data into the identified cache entry as a cache line; and marking the identified cache entry as a read-set cache line of the transaction.