1. A system comprising: at least one general purpose processor having an instruction set consisting essentially of seven instructions including LOADI, X; LOADACC, Y; STOREACC, Y; ADD, Y; AND, Y; XOR, Y; and INC, Y; embedded in RAM (random access memory) on a single chip; wherein said random access memory is accessible by said at least one general purpose processor, and wherein said at least one general purpose processor comprises at least one local cache associated with at least one dedicated memory addressing register whose least significant address bits are memory addresses to each relative byte of its associated said local cache, and the remaining most significant address bits are operable to initiate a cache load when said remaining most significant address bits are changed during processing when any said at least one dedicated memory addressing register is written.