1. A semiconductor memory, comprising: a plurality of memory cells; and an access section for accessing a memory cell, among the plurality of memory cells, corresponding to a row address and a column address, wherein: the plurality of memory cells comprise a plurality of first memory cells accessible at a first access speed and a plurality of second memory cells accessible at a second access speed which is higher than the first access speed, and for each row address, there exists a plurality of access units in sequence, and at least two of the plurality of access units included in the sequence each comprise at least one of the second memory cells at a leading column address assigned thereto followed by at least one of the first memory cells.