1. A computer for executing a computer program having a first multiplicity of processor-executable instructions comprising: software program encoding means for Huffman-like encoding the operator part of said first multiplicity of processor-executable instructions into an equal first multiplicity of first-type fields, called ENCODED OPERATOR, each partitioned into a first field-part, called REFLEX FIELD 1, and a second field-part, called OPERATOR INDEX, wherein the total bit length of each said first-type fields is not fixed but is variable dependent upon which operator part, and the times of occurrence of such operator part, within the operator parts of all said first multiplicity of processor executable instructions be currently encoded, plus into a first plurality of fixed bit length second-type fields, called OPERATOR REFLEX DESCRIPTORS, each partitioned into a first field-part, called LENGTH 1, and a second field-part, called INSTRUCTION; and for Huffman-like encoding the operand part of said first multiplicity of processor-executable instructions into an equal first multiplicity of first-type fields, called ENCODED OPERAND, each partitioned into a first field-part, called REFLEX FIELD 2, and a second field-part, called OPERAND INDEX, wherein the total bit length of each said first-type fields is not fixed but is variable dependent upon which operand part, and the times of occurrence of such operand part, within the operand parts of all said first multiplicity of processor-executable instructions be currently encoded, plus into a second plurality of fixed bit length second-type fields, called OPERAND REFLEX DESCRIPTORS, each partitioned into a first field-part, called LENGTH 2 and a second field-part, called DATA; first memory means having a multiplicity of fixed bit length addressable locations for storing said first multiplicity of said variable bit length first-type fields as encoded from said operator parts of said processor-executable instructions, in interleaved continuous contiguous association with said first multiplicity of said variable bit length first-type fields as encoded from said operand parts of said processor-executable instructions, which is to say that said variable bit length first-type fields encoded from said operator parts and said operand parts of said processor-executable instructions are stored as a contiguous continuum; second memory means having a first plurality of addressable locations each for storing one of said first plurality of second-type fields, said OPERATOR REFLEX DESCRIPTORS; third memory means having a second plurality of addressable locations each for storing one of said second plurality of second-type fields, said OPERAND REFLEX DESCRIPTORS; processor means for executing said processor-executable instructions; reflex descriptor logic decoding means coupled to said first memory means and said second memory means and said third memory means and said processor means for firstly addressably referencing said first memory means in order to firstly retrieve plural contiguous ones of said variable bit length first-type fields, and for responsively to a first partial field, said REFLEX FIELD 1 field-part, of the first one of said firstly retrieved plural contiguous ones of said first-type fields, secondly addressably referencing said second memory means in order to secondly retrieve an associated one of said second plurality of second-type fields, and for responsively to a first partial field, said LENGTH 1 field-part, of said secondly retrieved one of said second plurality of second-type fields extracting a second partial field, said OPERATOR INDEX field-part, of said first one of said firstly retrieved first-type fields, and for adding a second partial field, said INSTRUCTION field-part, of said secondly retrieved one of said second plurality of second-type fields to said extracted second partial field, said OPERATOR INDEX field-part, of said firstly retrieved first-type fields in order to reconstitute, or decode, therefrom the operator of a processor-executable instruction, and for supplying said reconstituted, or decoded, operator as part of said processor-executable instruction to said processor means for executing, and for responsively to a first partial field, said REFLEX FIELD 2 field-part, of the next consecutive one of said firstly retrieved plural contiguous ones of said first-type fields, thirdly addressably referencing said third memory means in order to thirdly retrieve an associated one of said third plurality of second-type fields, and for responsively to a first partial field, said LENGTH 2 field-part, of said thirdly retrieved one of said third plurality of second-type fields extracting a second partial field, said OPERAND INDEX field-part, of said next consecutive one of said firstly retrieved first-type fields, and for adding a second partial field, said DATA field-part of said thirdly retrieved one of said third plurality of second-type fields to said extracted second partial field, said OPERAND INDEX field-part, of said next consecutive one of retrieved first-type fields in order to reconstitute, or decode, therefrom the operand of a processor-executable instruction, and for supplying said reconstituted, or decoded, operand as part of said processor-executable instruction to said processor means for executing; and instruction address sequencing means, responsive to said processor means executing of said processor-executable instructions, for causing said reflex descriptor logic decoding means to deliver, by operator part and by operand part, such successive entireties of said processor-executable instructions to said processor means as, in sequence and number, comprise said computer program; whereby said computer has executed software to Huffman-type encode a computer program, has stored said Huffman-type encoded computer program, and has referenced and decoded, via said reflex descriptor logic decoding means, said stored encoded computer program in the execution thereof; whereby the action that responsively to said first-type fields, in the first partial field portions thereof, said reflex descriptor logic decoding means does addressably reference said associated one second-type field, and that responsively to said second-type field in the first partial field portion thereof, said reflex descriptor logic decoding means does extract a second partial field of said first-type field is why the word "reflex" is utilized to describe said logic decoding means.