1. A two-dimensional Discrete Cosine Transform (DCT) processor which uses a pair of one-dimensional DCT processors to produce the two-dimensional DCT of an N.times.N matrix of input data by a row-column decomposition method, comprising; a first N.times.1 DCT processor which computes the one-dimensional transform of said input data matrix, one column at a time, to yield a one-dimensional N.times.N intermediate transform matrix, an N.times.N transposition memory for storing said intermediate transform matrix, and a second N.times.1 DCT processor which computes the one-dimensional transform of the transpose of the said intermediate transform matrix stored in said trasposition memory to yield the desired two-dimensional DCT, wherein both of said N.times.1 DCT processors comprise; an input N-stage input register to which a column of said matrix of input data or a row or column of said stored intermediate transform matrix is applied in bit-serial format, an N-stage holding register having its stages connected to the corresponding stages of said input register, and means to transfer the contents to said input register in bit-parallel format to said holding register each time that said input register fills up, means connected to said holding register to concurrently compute N vector inner products, said means comprising circuit means connected to said holding register to implement first stage decimation in frequency to thereby produce a pair of N/2 bit words from the N bit words received from said holding register, N RACs connected to sid circuit means, each said RAC comprising one or more read only memories (ROMs) and an accumulator, and wherein each of said RACs is addressed by one or the other of said N/2 bit words, an N stage output register having each of its stages connected to the corresponding accumulator of each corresponding said RAC, and means to concurrently transfer said N computed vector inner products to said output register.