1. A method for generating a pipelined synchronized circuit representation of a program loop, comprising: generating a dependence graph from the program loop, the dependence graph representing operations and registers and connections therebetween; determining a minimum clock period and initiation interval from the dependence graph, and establishing a current minimum clock period as a function of the minimum clock period and establishing the initiation interval as a current initiation interval; and iteratively attempting to generate a scheduled graph from operations and registers of the dependence graph using the current minimum clock period and the current initiation interval as scheduling constraints, and if an attempt to generate a scheduled graph fails in an iteration, then increasing the current minimum clock period for a next iteration.