1. A processor comprising: a decode stage to decode a first instruction for execution, the first instruction specifying a first operand source data, a second operand source data, a third operand source data, and an operation type; and one or more execution units, responsive to the decoded first instruction, to: perform a first logical operation, according to the specified operation type, between data from the first and second operand sources, and perform a second logical operation between the data from the third operand source and the result of the first logical operation to conditionally set a condition flag.