1. A method for use in connection with a design layout of an electronic circuit, said design layout comprising a plurality of respective features on each of a plurality of layers, said method comprising the steps of: locating a region of overlap between first and second features on respective first and second layers; and for each feature: determining a region of interest, said region of interest containing the region of overlap; ascertaining a set of via enclosure rules applicable within the region of interest and determining whether asymmetric via enclosure rules may be applied for the feature in the region of interest.