1. A processing unit comprising: at least one processor core which carries out program instructions; a cache memory which stores values accessed by said processor core, said cache memory having a store queue and a cache array; scan circuitry which scans cache lines into said store queue; and control circuitry which executes functional clocks to transmit the cache lines from said store queue to said cache array wherein said control circuitry includes a mode bit which indicates that cache entries in said store queue are scanned cache lines, said cache memory includes read/claim dispatch logic which issues store instructions for the cache entries to read/claim machines, and said read/claim machines write the cache lines to said cache array without obtaining write permission after said read/claim machines evaluate said mode bit.