1. A computer system, having a plurality of peripheral devices, and which is reconfigured to perform a plurality of functions including operation with selected combinations of such peripheral devices, comprising: a system bus having a control bus and an address-data bus; an address bus; a microprocessor, connected to said system bus, for outputting an address to said address-data bus and control data to said control bus, for selectively outputting data to said address-data bus, and for selectively receiving input data from said address-data bus; detachable circuit means, having a memory address map, for configuring the computer system to perform at least one of the plurality of functions using at least one of the peripheral devices by latching the address on said address-data bus, by supplying the latched address to said address bus, and by selectively generating an access control signal to select at least one of the peripheral devices in accordance with said latched address and said memory address map whereby the address generated by the computer system is mapped to the address space occupied by said peripheral devices; memory means, responsive to said latched address on said address bus, said control data, and said access control signal, for selectively receiving and storing said output data from said address-data bus, and for selectively supplying said stored output data to said address-data bus; connecting means for connecting said detachable circuit means to said address-data bus and to said control bus by means of a first connecting terminal arrangement; and wherein said detachable circuit means comprises means for latching the address on said address-data bus and means for supplying the latched addres to said memory means via said address bus, and decoding means, responsive to said memory address map, for decoding said latched address and for selectively generating and supplying said access control signal to said memory means.