1. A computer implemented method for performance-based chip-to-chip stacking, the method comprising: selecting a first candidate chip from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit; activating a part of a 3D performance determinant in the first candidate chip; measuring a value of a performance parameter for a set of operating conditions; computing a stacked performance value for the first candidate chip using the value; and stacking a subset of the set of candidate chips in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.