1. A resistive change element memory array, comprising: a plurality of word lines; a plurality of bit lines; a plurality of select lines; a plurality of memory cells, said memory cells comprising: a resistive change element having a first terminal and a second terminal, said first terminal in electrical communication with a select line, wherein said resistive change element is capable of being switched between at least two non-volatile resistance values with a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state; a selection device responsive to a control signal on a word line, said selection device selectively providing a conductive path between a bit line and said second terminal of said resistive change element; a plurality of reference elements, said reference elements comprising: a resistive reference element having a first terminal and a second terminal, said first terminal in electrical communication with a bit line, wherein said resistive reference element has an electrical resistance selected to fall between said first resistance value and said second resistance value; a selection device responsive to a control signal on a word line, said selection device selectively providing a conductive path between a bit line and said second terminal of said resistive reference element; a plurality of sense amplifiers, each of said sense amplifiers responsive to at least one bit line electrically coupled to a resistive change element and at least one bit line electrically coupled to a resistive reference element; wherein said one of said plurality of sense amplifiers is capable of comparing the rate of discharge on a bit line electrically coupled to a resistive change element that has been selected by a word line and the rate of discharge on a bit line electrically coupled to a resistive reference element selected by a word line; and wherein said comparison is used to read the informational state of a selected memory cell.