1. A computer system for performing transactional memory operations in a multi- processor transactional execution (TX) environment, the system comprising: a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising: executing, by the processor, an instruction to cause a transaction be executed in an atomic write-only transaction mode, execution in the atomic write-only transaction mode comprising: monitoring, by the processor, write-set cache lines of the transaction while in atomic write-only transaction mode; and based on detecting, by the processor, a write-set conflict, aborting the transaction; suppressing, by the processor, any transaction abort due to conflicts of a read-set generated while in the atomic write-only transaction mode; and absent any aborting, completing the transaction, by the processor, the completing comprising committing transactional stores to memory and updating architecture states, wherein the read-set is tracked with dirty bits while inside the write-only mode, wherein each dirty bit is associated with a write-only indicator, the write-only indicator indicating that any conflict detected with the read-set should be ignored.