1. A computer implemented method for implementing multi-power domain digital or mixed-signal verification and low power simulation of an electronic circuit design, comprising: using a computer system which comprises at least one processor and is programmed for performing: identifying one or more schematics of the electronic circuit design; automatically generating one or more net or terminal sets, or one or more overriding net or terminal sets for the one or more schematics of the electronic circuit design by referencing a power data file for the electronic circuit design; and performing verification or simulation of the electronic circuit design by using at least the one or more net or terminal sets or one or more overriding net or terminal sets.