1. An analog-to-digital converter which is an integrated circuit charge coupled device having a substrate and a pair of charge packet potential wells comprising a first well and a second well for converting an analog signal to an M-bit binary code, said wells having first and second holding gates respectively; input means to insert charge packets representing analog values of samples of the input analog signal into said first well; transfer means including a transfer gate to transfer charge packets from the first well to the second well and from the second well to the first well; substrate detection means for output of "one" or "zero" values for the M-bits of each sample control means comprising logic, drive, and clock circuits coupled to said holding gates, to said input means, to said transfer gate, and to said detection means, with the clock circuits providing clock signals in repetitive cycles to convert one sample per cycle, each cycle being divided into an input subcycle plus M conversion subcycles of three phases each; the conversion subcycles being designated by the sumbol K, with the first conversion subcycle having K=M, the second K=M-1, and K decreasing by 1 until its value is 1 for the Mth conversion subcycle; the converter being operative during the first conversion subcycle following the input subcycle to place a voltage of (2.sup.m -1) units (the voltage units being of a fixed predetermined value) on both of said holding gates during the first and second clock phases and a voltage of (2.sup.m-1 -1) units during the third clock phase, and to place a voltage of (2.sup.m -1) units on the transfer gate during the second clock phase, so that the full analog charge packet representing the input sample is in the first well during the first clock phase, and any charge in excess of (2.sup.m-1) is transferred to the second well during the second clock phase, then during the third clock phase said detection means is actuated to detect whether the first well has a charge in excess of (2.sup.m-1 -1) to output a "one" or otherwise to output a "zero"; the converter being further operative during subsequent conversion subcycles to place a voltage of (2.sup.k-1 -1) units on both of said holding gates during the first and second clock phases and a voltage of (2.sup.K-1 -1) units during the third clock phase, except that if the bit output in the preceding subcycle was a "one" then the voltage on the holding gate is changed to zero during the first clock phase for that well which produced the output signal to dissipate its charge into the substrate, so that at the end of the first clock phase only one well of said pair contains a charge packet, and any charge in excess of (2.sup.k-1) is transferred to the other well during the second clock phase, then during the third clock phase said detection means is actuated to detect whether said one well has a charge in excess of (2.sup.k-1 -1) to output a "one" or otherwise to output a "zero".