1. In a processor having an instruction unit, a decode/issue unit, a first execution queue configured to provide instructions of a first instruction type to a first execution unit, a second execution queue configured to provide instructions of a second instruction type to a second execution unit, a method comprising: receiving a first instruction of the second instruction type; decoding the first instruction by the decode/issue unit to determine operands of the first instruction; determining that the operands of the first instruction include a dependency on a second instruction of the first instruction type stored in a first entry of the first execution queue; storing the first instruction in a first entry of the second execution queue; in response to the determining that the operands of the first instruction include the dependency on the second instruction: setting a synchronization indicator corresponding to the first instruction in a second entry of the first execution queue, immediately adjacent the first entry of the first execution queue, which indicates that the first instruction is stored in another execution queue; and setting a synchronization pending indicator in the first entry of the second execution queue to indicate that the first instruction has a corresponding synchronization indicator stored in another execution queue.