1. A processor core, comprising: a plurality of dispatch queues for receiving instructions of a corresponding plurality of instruction streams; a plurality of parallel instruction execution slices for executing the plurality of instruction streams in parallel; a dispatch routing network for routing the output of the dispatch queues to the instruction execution slices; a dispatch control logic that dispatches the instructions of the plurality of instruction streams via the dispatch routing network to issue queues of the plurality of parallel instruction execution slices; and a mode control logic, responsive to a mode control signal for reconfiguring a relationship between the plurality of parallel instruction execution slices such that in a first configuration corresponding to a first state of the mode control signal, at least two of the plurality of parallel instruction execution slices are independently operable for executing at least two of the plurality of instruction streams, and wherein in a second configuration corresponding to a second state of the mode control signal the at least two parallel instruction execution slices are linked for executing a single one of the plurality of instruction streams.