1. A method for reducing instruction cache duplication for frequently fetched instructions, a caching system having a first instruction cache and a second instruction cache, the caching system coupled to a computer instruction fetch unit, the method comprising: receiving, by the caching system from the computer instruction fetch unit, an instruction address; based on the received instruction address resulting in a cache miss in both the first instruction cache and the second instruction cache: retrieving, by the caching system, an instruction associated with the received instruction address from a computer memory; storing, by the caching system, the received instruction address and the associated retrieved instruction in the first instruction cache; and initializing, by the caching system, a fetch frequency value for the received instruction address; based on the received instruction address resulting in a cache miss in the second instruction cache and resulting in a cache hit in the first instruction cache: incrementing, by the caching system, the fetch frequency value for the received instruction address; retrieving, by the caching system, the instruction associated with the received instruction address from the first instruction cache; determining, by the caching system, whether an instruction in the second instruction cache matches the instruction retrieved from the first instruction cache; based on no instructions in the second instruction cache matching the instruction retrieved from the first instruction cache and based on the fetch frequency value for the received instruction address exceeding a predetermined threshold: storing, by the caching system, the instruction retrieved from the first instruction cache in the second instruction cache; and storing, by the caching system, an association of the received instruction address to the instruction stored in the second instruction cache; based on an instruction in the second instruction cache matching the instruction retrieved from the first instruction cache: storing, by the caching system, an association of the received instruction address to the instruction stored in the second instruction cache that matches the instruction retrieved from the first instruction cache; based on the received instruction address resulting in a cache hit in the second instruction cache, retrieving, by the caching system, the instruction associated with the received instruction address from the second instruction cache; and returning, by the caching system, the retrieved instruction to the instruction fetch unit.