1. A method of operating a non-volatile logic circuit, the method comprising: a step (a) of preparing the non-volatile logic circuit, wherein: the non-volatile logic circuit comprises a control electrode, a ferroelectric layer, a semiconductor layer, and an electrode group, the control electrode, the ferroelectric layer, the semiconductor layer, and the electrode group are stacked in this order, the semiconductor layer is a p-type semiconductor layer, the electrode group comprises a power electrode, an output electrode, first to eighth input electrodes, and first to fourth logic configuration electrodes, X direction, Y-direction, and Z-direction denote a longitudinal direction of the ferroelectric layer, a direction orthogonal to the longitudinal direction, and a layer stack direction, respectively, the first to eighth input electrodes and the first to fourth logic configuration electrodes are interposed between the power electrode and the output electrode along the X-direction, the first to fourth logic configuration electrodes are disposed along the Y-direction, the first to fourth input electrodes are disposed along the Y-direction, the first to fourth input electrodes are disposed along the Y-direction, the fifth input electrode is interposed between the first logic configuration electrode and the first input electrode along the X-direction, the sixth input electrode is interposed between the second logic configuration electrode and the second input electrode along the X-direction, the seventh input electrode is interposed between the third logic configuration electrode and the third input electrode along the X-direction, and the eighth input electrode is interposed between the fourth logic configuration electrode and the fourth input electrode along the X-direction; a step (b) of configuring one logic in the nonvolatile logic circuit, the one logic being selected from logical multiplication (AND), logical addition (OR), negative logical multiplication (NAND), negative logical addition (NOR), and exclusive logical addition (XOR), wherein: voltages V 1 , VA, VB, VC, and VD are applied to the control electrode, and the first to fourth logic configuration electrodes, respectively, in a case where the logical multiplication (AND) is configured, the voltages which satisfy the following inequality (I) are applied, 
 V1<VA, V1>VB, V1>VC, and V1>VD  (I), in a case where the logical addition (OR) is configured, the voltages which satisfy the following inequality (II) are applied, 
 V1<VA, V1<VB, V1<VC, and V1>VD  (II), in a case where the negative logical multiplication (NAND) is configured, the voltages which satisfy the following inequality (III) are applied, 
 V1>VA, V1<VB, V1<VC, and V1<VD  (III), in a case where the negative logical addition (NOR) is configured, the voltages which satisfy the following inequality (IV) are applied, 
 V1>VA, V1>VB, V1>VC, and V1<VD  (IV), in a case where the exclusive logical addition (XOR) is configured, the voltages which satisfy the following inequality (V) are applied, 
 V1>VA, V1<VB, V1<VC, and V1>VD  (V); a step (c) of writing one state selected from the group consisting of first to fourth states into the non-volatile logic circuit, wherein: voltages Va to Vh are applied to the first to eighth input electrodes, respectively, in a case where the first state is written, voltages which satisfy the following inequality (VI) are applied, 
 V1<Va, V1<Vb, V1>Vc, V1>Vd, V1<Ve, V1>Vf, V1<Vg, and V1>Vh  (VI), in a case where the second state is written, voltages which satisfy the following inequality (VII) are applied, 
 V1>Va, V1>Vb, V1<Vc, V1<Vd, V1<Ve, V1>Vf, V1<Vg, and V1>Vh  (VII), in a case where the third state is written, voltages which satisfy the following inequality (VIII) are applied, 
 V1<Va, V1<Vb, V1>Vc, V1>Vd, V1>Ve, V1<Vf, V1>Vg, and V1<Vh  (VIII), in a case where the fourth state is written, voltages which satisfy the following inequality (IX) are applied, 
 V1>Va, V1>Vb, V1<Vc, V1<Vd, V1>Ve, V1<Vf, V1>Vg, and V1<Vh  (IX); and a step (d) of measuring current generated by applying a potential difference between the power electrode and the output electrode to determine whether the semiconductor layer between the power electrode and the output electrode is a high resistance state or a low resistance state on the basis of the current.