1. A method of forming a trench-gated field effect transistor (FET), comprising: using one mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.