1. An advanced processor, comprising: at least one processor configured to execute multiple threads: and a memory management unit (MMU) coupled to the processor having first, second, and third translation-lookaside buffer (TLB) portions operable in at least two modes, each TLB portion having a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification.