1. A method for performing logical to physical address translations in a NAND memory, the NAND memory including a translation cache containing a subset of a plurality of entries mapping logical block addresses to physical locations of the NAND memory, the method comprising: receiving from a processor a read/write request that includes an address for a logical block and context information regarding the logical block, the context information including at least one of a relationship of the logical block to other logical blocks and a description of future activity associated with the logical block, wherein the context information is part of the read/write request; and pre-fetching a first entry into the translation cache based on the context information to facilitate anticipating a translation request to the translation cache from a future read/write request.