1. A computer implemented method for reducing penalties for cache accessing operations, the method comprising: respectively associating platform registers with cache arrays; loading control information and data of first and second store operations, which are respectively passing through first and second pipe passages and which are to be executed with respect to one or more of the cache arrays, into the one or more of the platform registers respectively associated with the one or more of the cache arrays in an event the first and second store operations are targeting a same wordline of the one or more of the cache arrays, the loading being conducted by way of respective couplings between the first and second pipe passages and the one or more of the platform registers; and based on the one or more of the cache arrays becoming available, committing the data of the first and second store operations from the one or more of the platform registers using the control information from the same platform arrays to the one or more of the cache arrays at a same time.