1. A system comprising: a processor configured to: insert an initialization instruction that is used to facilitate detection of runtime incidental atomicity, wherein the initialization instruction is inserted at a safepoint where an execution state of a central processing unit is known, and wherein the initialization instruction comprises an instruction to speculatively execute a particular number of instructions; initiate speculative execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units that immediately follows the inserted initialization instruction, wherein: at least one of the plurality of instruction units comprises a plurality of machine instructions that emulates one or more virtual instructions; thread execution of each of the plurality of instruction units is guaranteed to be atomic; the plurality of instruction units in the thread is not programmatically specified to be executed atomically together; and the plurality of instruction units includes one or more memory modification operations; in response to detection of an atomicity terminating event triggered by a memory access by another processor during speculative execution of the plurality of instruction units, revert memory modification operations that were speculatively executed during speculative execution; and in response to a determination the event that speculative execution is successful: transition into a commit state; commit memory modification operations that were speculatively executed during speculative execution of the particular number of instructions; and terminate execution of the plurality of instruction units; and a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.