1. A method for analyzing interconnect process variation, the method comprising: generating, by at least one processor, first descriptions of parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC), the first descriptions describing the parasitic RC elements respectively at a typical process corner and a peripheral process corner; generating, by the at least one processor, sensitivity values at the peripheral process corner from the first descriptions, wherein the sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation; combining, by the at least one processor, the sensitivity values into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter; pseudo randomly generating, by the at least one processor, values of the process variation parameter; and repeatedly simulating, by the at least one processor, the second description with the pseudo randomly generated values for the process variation parameter.