1. A static random access memory (SRAM) device comprising: a plurality of memory array layers comprising a first memory array layer and a second memory array layer vertically disposed above the first memory array layer, the first memory array layer comprising a plurality of memory cells, each of which includes a data retention circuitry that allows the memory cell to operate in a reduced power when the data retention circuitry receives a data retention signal; layer decoder circuitry on each memory array layer comprising a first layer decoder circuit on the first memory array layer and a second layer decoder circuit on the second memory array layer, the first layer decoder circuit being configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to the memory cells on the first memory array layer and to send the data retention signal to the data retention circuitry of each of the memory cells on the first memory array layer if the SRAM address does not correspond to the memory cells on the first memory array layer; a plurality of word lines disposed on each memory array layer; a partial SRAM address decoder; a word line driver circuit disposed on each memory array layer, the word line driver circuit of the first memory array layer being configured to operate cooperatively with the partial SRAM address decoder to select and drive one of the plurality of word lines disposed on the first memory array layer, wherein the selected and driven one of the plurality of word lines is connected to a predetermined number of memory cells in the first memory array layer, wherein power is selectively applied to the selected and driven one of the plurality of word lines based on connection to the predetermined number of memory cells selected by the SRAM address only to perform a row read or row write operation, wherein only one word line coupled to the first memory array layer is selected at a time; and a bit line coupled to a single memory cell in the first memory array layer and a single memory cell in the second memory array layer.