1. A computer functioning as a compiler device to optimize a program by changing an order of executing instructions, said compiler device comprising: a movable range analysis unit to analyze an instruction movable range within which the instructions can be moved while obtaining an execution result of the program without increasing a number of times of executing the instructions; a replaceability determination unit to determine whether or not a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together, wherein the replaceability determination unit determines the first and second instructions to be replaceable with the common processing instruction group when the first instruction is an instruction for reading first data from a memory, the second instruction is an instruction for reading, from the memory, second data stored in an address different from that of the first data and the first and the second data can be read by one instruction; a common processing instruction group generation unit to generate a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit to insert the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.