1. A nonvolatile ferroelectric memory device comprising a unit cell array which includes: plurality of bottom word lines; plurality of insulating layers formed on the plurality of bottom word lines, respectively, a floating channel layer comprising a plurality of P-type channel regions located on the plurality of insulating layers and a plurality of N-type drain and source regions which are alternately electrically connected in series to the plurality of P-type channel regions; a plurality of ferroelectric layers formed respectively on the plurality of P-type channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively, wherein the unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of P-type channel regions depending on polarity states of the plurality of ferroelectric layers.