1. A programmable logic structure comprising: an interconnect structure comprising a plurality of interconnect lines; a plurality of logic cells, each logic cell comprising: at least three optional inverters, each of which has an optional inverter input terminal; means for connecting each of said optional inverter input terminals to one of said interconnect lines to receive an input signal from said interconnect structure, each optional inverter providing as an optional inverter output signal one of said input signal and the complement of said input signal; logic gates for generating two functions of said optional inverter output signals, said two functions being the AND function and the sum-of-products function of said optional inverter output signals; and a function selector which causes a selected one of said two functions to be provided as an output signal of said logic cell.