1. A semiconductor memory array comprising a plurality of single polysilicon floating gate semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said single polysilicon floating gate semiconductor memory cell comprising: a substrate; a floating body region exposed at a surface of said substrate and configured to store volatile memory; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating said floating body region from said single polysilicon floating gate; and first and second regions exposed at said surface at locations other than where said floating body region is exposed; wherein said floating gate is configured to receive transfer of data stored by the floating body region.