1. A differential current switch logic circuit comprising: an evaluation tree including a plurality of input terminals and first and second output nodes; an output network having first and second state outputs, the output network establishing both state outputs at a predetermined level during a precharge phase and providing a path to ground for one of the state outputs in response to the evaluation tree output nodes to establish the state outputs at complementary levels during an evaluate phase; first and second evaluation transistors clocked by an evaluation clock signal, in which each state output is cross-coupled to drive the other output during the evaluate phase initiated by the evaluation clock signal; a first isolation transistor coupled between the output network and one of the evaluation tree output nodes, the first isolation transistor having its gate coupled to the second state output; a second isolation transistor coupled between the output network and the other complementary evaluation tree output node, the second isolation transistor having its gate coupled to the first state output; and during the evaluate phase, one of the first or second isolation transistors isolates a non-grounded complementary output node of the evaluation tree from the output network.