1. A system for simultaneous multithreading (SMT), the system comprising: a cache; and a processor core comprising circuitry to execute threads by SMT, each of the threads having its own load queue and store queue, wherein in response to performing a store instruction for a given thread of the threads on the processor core and in response to the processor core having ownership of a cache line in the cache, the processor core is configured to execute the store instruction comprising: placing an entry of the store instruction in a given store queue belonging to the given thread, the entry for the store instruction having a starting memory address and an ending memory address on the cache line; comparing starting memory addresses through ending memory addresses of load queues of the threads on a byte-per-byte basis against the starting memory address through the ending memory address of the store instruction; in response to at least one memory address byte in the starting through ending memory addresses in the load queues of the threads overlapping with a memory address byte in the starting through ending memory address of the store instruction, flushing one or more of the threads having the at least one memory address byte; and in response to no overlap, allowing entries in the load queues of the threads to remain.