1. A multi-threaded processor comprising: a memory; an instruction decoder coupled to the memory for decoding instructions retrieved therefrom; an integer unit coupled to the instruction decoder for processing integer type instructions received from the instruction decoder; a vector unit coupled to the instruction decoder for processing vector type instructions received from the instruction decoder; an accumulator unit associated with the vector unit for storing a first accumulator value; and a reduction unit associated with the vector unit and the accumulator unit and configured to receive parallel data elements processed in the vector unit and to receive the first accumulator value from the accumulator unit, the reduction unit being operable to sum the parallel data elements and the first accumulator value, wherein the sum of the parallel data elements produces the same result as would be obtained if the parallel data elements were summed in series, and to generate a second accumulator value for delivery to the accumulator unit, wherein one or more of the instructions are in a compound instruction format in which a single instruction comprises of multiple operation fields.