1. An interrupt controller, comprising: a fabric slave circuit to connect to a fabric for a computing system, the fabric slave circuit configured to receive an MMIO write request including an MMIO address and MMIO write data, the MMIO write data includes an indication of a task to be done for a MMIO interrupt; a plurality of output interrupt lines; a plurality of interrupt registers, each interrupt register corresponds to at least one output interrupt line of the plurality of output interrupt lines; and a MMIO routing circuit connected to the fabric slave and the plurality of interrupt registers, the MMIO routing circuit configured to route the received MMIO write data to a targeted interrupt register corresponding to a targeted output interrupt line identified by the received MMIO address so that the targeted interrupt register stores the indication of the task to be done for the MMIO interrupt, storing of the indication of the task to be done for the MMIO interrupt in the targeted interrupt register triggers assertion of the targeted output interrupt line.