1. An Arithmetic Logic Unit (ALU) circuit comprising: a bitwise adder adding together a first set, a second set and a third set of input bits to produce a sum set and a carry set of bits; a first multiplexer configured to select the sum set of bits or the carry set of bits; a second multiplexer configured to select the carry set of bits or a set of constant bits; and an adder configured to add the output of the first multiplexer and the output of the second multiplexer to produce a result.