1. In a computer system having a processor, and a memory coupled to the processor via a bus, the memory containing computer readable instructions which when executed by the processor cause the processor to implement a method of verifying a design of a digital system, the method comprising a computer system performing the steps of: modeling a digital system as an extended finite state machine; mapping a plurality of states of the extended finite state machine to a corresponding plurality of strings; mapping sets of the plurality of strings into a corresponding language; representing the corresponding language as an automaton; applying automata operations to the automata to efficiently compute the set of reachable states of the extended finite state machine from an initial state; and determining whether the set of reachable states includes an undesirable state in order to verify a design of the system.