1. An input/output data processing system for controlling input/output operations involving data transfers between a plurality of modules and a plurality of input/output devices, said system comprising: system interface means having a plurality of ports; said plurality of modules connected to a different one of said plurality of ports, said modules including at least one memory module and a plurality of command modules, each of said command modules including: command generating means for generating memory commands, a first type of memory command including an address designating the location in said memory module where data accompanying said memory command is to be stored; and, said one memory module including: a cache store operatively connected to said one of said ports for storing blocks of information words in response to said memory commands; a backing store operatively connected to said one of said ports for storing information words, said backing store including a plurality of word locations, each number of said plurality of word locations defining a block; control circuit means connected to said cache store and to said backing store for controlling the operation of said cache store and backing store, said control circuit means including: input register means connected to said one port for receiving said memory commands from said plurality of command modules; command decode circuit means connected to said input register means for decoding each of said first type of memory commands and generating signals for initiating a memory cycle of operation simultaneously in said backing store and said cache store; input data switching means connected to said one of said interface ports, said switching means including first input means for receiving said data accompanying said first type of memory command, second input means operatively connected to said backing store for receiving words read out during a cycle of operation in response to each said first type of command and output means coupled to said cache store and said backing store, said data switching means applying to said output means the updated data resulting from merging said data accompanying each of said first type command with said words read out from said backing store during said memory cycle of operation; a directory store including a plurality of word locations corresponding in number to the number of blocks in said cache store, each word location for storing a block address designating where a particular block of information is stored in said cache store; comparison means connected to said directory store and to said input register means for comparing said address of said memory command with the block address read out from said directory store in response to said memory command, said comparison means generating an output compare signal indicative of a true address comparison; hit control means connected to said comparison means and said command decode means, said hit control means generating a hit signal in response to said output compare signal for indicating when the block of information words specified by said first type of command is stored in said cache store; and, said command decode circuit means when conditioned by said hit signal being operative in response to said each first type of memory command generating control signals for enabling said cache store to write at the same address said updated data thereby facilitating fast access to valid current information within said cache store.