1. A digital data processor for multiplying row elements of a first input matrix by column elements of a second input matrix to form a product matrix, the processor including: a systolic array of processing cells arranged for bit-level multiplication; data input means for effecting bit-level matrix element input to the array for multiplication of each bit of each first matrix row element by each bit of each of the second matrix elements in a respective column; wherein the data input means is arranged both for matrix input with zeros interspersed between adjacent bits of each matrix element and for producing a cumulative time stagger between input of adjacent rows of the first matrix and adjacent columns of the second matrix, accumulating means for summing array output contributions to each bit of each product matrix element; and clocking means for controlling operation of the processing cells, data input means and accumulating means, the clocking means being arranged to advance both input matrices by one cell through the array on each clock cycle, wherein the processing cells are nearest-neighbour connected and have processing functions to evaluate the product of two input data bits, add the product to an input cumulative sum bit and a carry bit from a next lower order bit computation, output a corresponding result, generate a new carry bit and pass on the input data bits to respective neighbouring cells.