1. A system including embedded non-Flash non-volatile memory, comprising: a silicon semiconductor substrate including circuitry fabricated on the silicon semiconductor substrate, the circuitry including an input/output (I/O) controller and a memory controller in electrical communication with each other; at least one memory plane in direct contact with the silicon semiconductor substrate and fabricated directly above the silicon semiconductor substrate; at least one two-terminal non-volatile cross-point memory array embedded in the at least one memory plane, each memory array including a plurality of first conductive array lines and a plurality of second conductive array lines that are arranged orthogonally to the plurality of first conductive array lines, the first and second conductive array lines are electrically coupled with at least a portion of the circuitry; and a plurality of re-writable two-terminal non-volatile memory elements positioned in each memory array, each memory element is positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of the second conductive array lines, each memory element is electrically in series with its respective first and second conductive array lines, and a write operation to each memory element does not require a prior erase operation to the memory element, and wherein the I/O controller and the memory controller are in electrically communication with the at least one two-terminal non-volatile cross-point memory array, and the memory controller is configured to interface with a command associated with NAND Flash memory, and based on the command, to access the at least one two-terminal non-volatile cross-point memory array for a data operation.