1. A method for generating an Eulerian sequence of test vectors for an integrated circuit, the method comprising the steps of: (a) generating and storing a list of input states for which the circuit is designed to operate; (b) generating and storing a list of transitions between said input states, wherein said states correspond to inputs to said integrated circuit, each of said transitions is a transition between two such states and said transitions conform to some constraint restricting the existence of transitions; (c) defining a graph having vertices that correspond to states in said list of input states and edges that correspond to the transitions in said list of transitions, wherein each such transition is a transition for which a test is desired and wherein each vertex corresponds to an input state to which at least one such transition provides a connection; (d) determining all sub-graphs of said graph; (e) determining if said graph is connected, and if said graph is not connected adding at least one transition that meets said constraint and that connects a vertex in one of said sub-graphs with a vertex in another of said sub-graphs; (f) determine if said graph is connected, and if said graph is still not connected, adding to said graph one or more nodes that correspond to input states having transitions that conform to said constraint condition such that said transitions connect one sub-graph to another sub-graph; (g) determining if said graph is Eulerian, and if said graph is not Eulerian, adding additional edges corresponding to transitions from said input list of transitions and, if necessary, vertexes corresponding to states from said input list of states to cause said graph to be Eulerian, wherein said transitions conform to said constraint; and (h) determining a single path through said graph such that each transition in said list of transitions is used precisely once in traversing said path, said Eulerian sequence of test vectors for said integrated circuit being determined by the sequence of vertices on said path and transferring said Eulerian Sequence of test vectors to a testing unit for testing said integrated circuit, wherein said testing unit is selected from a group consisting of a circuit simulator and a chip tester.