1. An apparatus comprising: a processor running a first thread of execution and a second thread of execution; a plurality of register files having a first portion and a second portion, each register file is operable to hold a plurality of entries and each entry having a plurality of bits, each register file having write and read ports; and a control unit receiving a first instruction from the first thread of execution and a second instruction from the second thread of execution, in response to the control unit receiving the first instruction, the control unit configures the addressability of the plurality of register files to access a first entry stored in the first portion, in response to the control unit receiving the second instruction, the control unit configures the addressability of the plurality of register files to access a second entry which spans across the first and second portions.