1. A method for proving correctness of a bit-serial division circuit design, the method comprising: creating a set of properties to prove correctness of the bit-serial division circuit design, wherein the set of properties can be efficiently proven by using a bit-level solver, wherein the bit-serial division circuit design receives a dividend and a divisor as input, wherein the bit-serial division circuit design outputs a w-bit quotient and a remainder by performing an iterative computation, and wherein in each iteration of the iterative computation, the bit-serial division circuit design determines b bits of the w-bit quotient, wherein b is less than w, and wherein b and w are integers; and performing, by computer, formal verification of the bit-serial division circuit design by attempting to prove the set of properties using the bit-level solver.