1. A method for implementing an inter-virtual processor interrupt, the method comprising: when a source virtual processor needs to trigger an interrupt to one or more target virtual processors, writing register data in a single write operation into a virtual register of a virtual advanced programmable interrupt controller (vAPIC) of the source virtual processor, wherein the virtual register comprises first reserved bits, a second reserved bit, and a plurality of fields including a destination mode field, the register data comprising: information about the one or more target virtual processors written into the first reserved bits, indication data written into at least the destination mode field of the plurality of fields used to indicate that the source virtual processor triggers the interrupt to the one or more target virtual processors wherein when the destination mode field of the indication data is 1, it indicates that the information about the one more target virtual processors identifies a plurality of target virtual processors, and when the destination mode data bit is 0, it indicates that the information about the one or more target virtual processors identifies a single target virtual processor, optimization data written into the second reserved bit of the virtual register of the vAPIC of the source virtual processor, so that when the optimization data written into the second reserved bit is 1, the optimization data instructs a virtual machine monitor to obtain the information about the one or more target virtual processors and the indication data from the virtual register by means of parsing, and the virtual machine monitor obtaining the information about the single target virtual processor or the plurality of target virtual processors contained in the information about the one or more target virtual processors and the indication data from the virtual register by means of parsing when the optimization data is 1, and injecting an inter-virtual processor interrupt corresponding to the interrupt, into the one or more target virtual processors according to the information about the one or more target virtual processors and the indication data.