1. An interconnect for an integrated circuit to pass communication transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, comprising: a centralized Memory Management logic Unit (MMU) for the interconnect and its connected devices, where the centralized MMU is located in the interconnect for virtualization and sharing of integrated circuit resources, which include the one or more target IP cores, the interconnect, and the one or more initiator IP cores; a master translation look aside buffer (TLB), which is part of the centralized MMU, is configured to store virtualization and sharing information in entries of the master TLB; and a set of two or more local translation look aside buffers (TLBs), which are each associated with one or more local initiator IP cores, are configured to store virtualization and sharing information replicated from the master TLB in the centralized MMU, where the master TLB and the set of local TLBs form a distributed system that provides virtualization and sharing services to the IP cores.