1. A microprocessor configured to receive first and second program-adjacent macroinstructions of the instruction set architecture of the microprocessor, wherein the first macroinstruction instructs the microprocessor to move a first operand to a first architectural register of the microprocessor from a second architectural register of the microprocessor, wherein the second macroinstruction instructs the microprocessor to perform an arithmetic/logic operation using the first operand in the second architectural register and a second operand in a third architectural register of the microprocessor to generate a result and to load the result back into the first architectural register, the microprocessor comprising: a hardware execution unit; an instruction translator, configured to simultaneously translate the first and second program-adjacent macroinstructions into a single micro-operation for execution by the hardware execution unit; wherein the single micro-operation instructs the hardware execution unit to perform the arithmetic/logic operation using the first operand in the second architectural register and the second operand in third architectural register to generate the result and to load the result back into the first architectural register; and a retire unit, configured to retire both the first and second macroinstructions in the same clock cycle.