1. A computer-implemented method of allocating registers in a computing system during compilation of program code, comprising: determining a count of hardware registers available for allocating during the compilation; doubling the determined count of hardware registers to reflect independent usage of halves of the hardware registers; invoking a register coloring algorithm to build an interference graph using the doubled count of hardware registers as a number of registers to be allocated, wherein building the interference graph further comprises: programmatically consulting a data structure that specifies, for each of a plurality of operation codes in the program code to be compiled, restrictions on allocating operands of the operation code to hardware registers; responsive to the programmatically consulting determining that a selected operand of a particular operation code must use a full hardware register, causing an allocator to allocate both a high-word half and a low-word half of a hardware register to the selected operand; responsive to the programmatically consulting determining that the selected operand is allocatable to a register half and must use the high-word half of a hardware register, adding an interference to the interference graph between the selected operand and all low-word halves of the hardware registers to force the selected operand to be allocated to a high-word register half; and responsive to the programmatically consulting determining that the selected operand is allocatable to a register half and must use the low-word half of a hardware register, adding an interference to the interference graph between the selected operand and all high-word halves of the hardware registers to force the selected operand to be allocated to a low-word register half; and independently allocating the halves of the hardware registers by the allocator, when generating compiled program code during the compilation, according to results of the register coloring algorithm, thereby causing the compiled program code to specify concurrently storing, in at least one of the hardware registers, a first operand in the high-word half of the hardware register and a second operand in the low-word half of the hardware register, the first and second operands being distinct from and unrelated to one another.