1. A core architecture for a user-programmable gate array integrated circuit, including: an array of logic function modules, each of said modules having at least one input and at least one output; a general interconnect architecture imposed on said array, said general interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each of said horizontal and vertical general interconnect channels including a plurality of interconnect conductors, individual ones of said general interconnect conductors connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements; and a local interconnect architecture imposed on said array, said local interconnect architecture comprising local interconnect channels, each local interconnect channel running between at least two adjacent ones of said logic function modules and including a plurality of local interconnect conductors, first ones of said local interconnect conductors hardwired to the outputs of said adjacent ones of said logic function modules, and second ones of said local interconnect conductors connectable to each other and to the inputs of the logic function modules by user-programmable interconnect elements.