1. A processor, comprising: a front end unit, including: a level 1 branch target buffer (BTB), configured to predict a target address; a BTB index predictor (BIP), configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction; and a level 1 hash perceptron (HP), configured to predict whether a branch instruction is taken or not taken.