1. A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands, the microprocessor comprising: a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result; and forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands; wherein each of the floating-point units comprises: a mux configured to receive the non-ADF results and to select one or more of the non-ADF results for provision as the non-ADF source operands to the floating-point unit.