1. A method for enabling scan test vectors to be generated by an automatic test vector generating software program for a customer designed integrated circuit having an embedded vendor circuit which includes a proprietary circuit and a nonproprietary circuit and which also includes customer supplied circuitry, comprising: creating at least one pseudo input to represent at least a portion of said nonproprietary circuit that is not necessary to be exercised by said automatic test vector generating software program to generate test vectors for said customer designed integrated circuit; identifying an output node of said embedded vendor circuit to which an input of said customer designed circuit is connectable; and creating a test netlist which represents circuitry that produces output states at said output node which would be generated by said embedded vendor circuit thereat; said test netlist including said at least one pseudo input and said output node, without including a full netlist of either said proprietary or nonproprietary circuits; whereby scan test vectors for the customer designed integrated circuit can be generated by said automatic test vector generating software program using said test netlist with said output node connected to an input of a netlist representing said customer supplied circuitry.