1. A method of generating a library of circuit blocks to be floorplanned into a 3D integrated circuit, the steps comprising: assembling, by a computing device, a plurality of circuit blocks comprising 2D circuit implementations and 3D circuit implementations; providing a first additional tier for at least one of the plurality of circuit blocks and generating a first re-implementation of the at least one of the plurality of circuit blocks that includes the first additional tier; evaluating at least one performance objective of the first re-implementation to determine whether the at least one performance objective has improved; and adding the first re-implementation to the library of circuit blocks to be floorplanned into the 3D integrated circuit if a result of the evaluating step is that at least one performance objective has improved, wherein the library of circuit blocks to be floorplanned into the 3D integrated circuit comprises a library of 3D monolithic circuit blocks, wherein at least one 3D monolithic circuit block includes one or more electronic components built sequentially in two or more layers on a single semiconductor wafer.