1. Apparatus for producing a first binary number of "n" bits from a second binary number of "m" bits, the lower order "a" bits of the second binary number being an index number and the higher order "b" bits of the second binary number being a key number, comprising: an associative random access memory having 2.sup.a addressable memory locations, said associative memory adapted to store b+n bits at each addressable memory location; a first independently addressable validity bit array random access memory having 2.sup.a addressable memory locations, said first array adapted to store a validity bit at each addressable memory location; a second independently addressable validity bit array random access memory having a 2.sup.a addressable memory locations, said second array adapted to store a validity bit at each addressable memory location; pointer means for enabling only one of said validity bit arrays to receive address signals of "a" bits at a given time from the binary number m and to produce the validity bit stored at an addressed memory location; circuit means for applying to the associative memory and to the enabled validity bit array the lower "a" bits of the second number as an address, said associative memory in response thereto and to a read enable signal for producing signals representing the (b+n) bits stored at the addressed location of the associative memory, and the enabled validity bit array in response thereto and to a read enable signal producing a signal representing the validity bit stored at the addressed location of the enabled validity bit array; circuit means for comparing the signals representing higher order "b" bits of the second number and the "b" bits stored at the addressed location of the associative memory and for producing a signal that the "n" signals representing a first binary number produced by the associative memory is correct if the signals representing the higher order "b" bits of said second number and the "b" bits of the key number compare and the validity bit produced by the enabled validity bit array is set; means for resetting all the validity bits of all addressable locations stored in the not enabled validity bit array; and means responsive to a CAMP-instruction control signal for causing the pointer to disable the then enabled array and to enable the then disabled array after all validity bits of the not enabled validity bit array have been reset.