1. An apparatus comprising: a storage device configured to store memory pages including a first memory page retrieved from the storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space; an external memory system including a main memory controller coupled to main memory having the physical address space; and a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor at a first access level and at least one guest operating system at a second access level; wherein the processor is configured to: at the second access level, translate from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space using mappings in a first page table accessed by the guest operating system; at the second access level, determine class information for a second memory page mapped by the first page table based on a classification of virtual addresses within the virtual address space, wherein the class information determined at the second access level is independent from: (1) any bits used to indicate virtual addresses, and (2) any bits used to indicate intermediate physical addresses; at the first access level, translate from the intermediate physical addresses to physical addresses in the physical address space of the main memory using mappings in a second page table accessed by the hypervisor; at the first access level, determine class information for the second memory page mapped by the second page table based on a classification of intermediate physical addresses within the intermediate physical address space, wherein the class information determined at the first access level is independent from: (1) any bits used to indicate intermediate physical addresses, and (2) any bits used to indicate physical addresses; and process class information for the second memory page determined at different access levels to determine processed class information for the second memory page using a dynamic processing rule.