1. A computer implemented method of operating a multiplication circuit to compute the product of two operands (A and B), at least one of which is wider than a width associated with the multiplication circuit, where each of the operands comprises one or more contiguous ordered word-wide operand segments (A j and B i ) characterized by specific weights j and i, where j is an integer from 0 to k and where i is an integer from 0 to m, and a word is a specified number of bits (n), and where the multiplication circuit executes a matrix of word-wide operand segment pair multiplication operations, the matrix comprising m+1 rows and k+m+2 columns, each row having a weight x and each column having a weight y, the multiplication circuit having access to a memory, the method comprising: performing multiplication operations on a pair of rows at one time, where for each pair of rows a pair of corresponding B i word-wide operand segments are read from the memory and word-wide operand segment pair multiplication operations (A j *B i ) are iteratively performed for each of k+2 columns, such that for each column in the matrix a maximum of two additional memory read operations and one memory write operation is required.