1. A very long instruction word parallel data processing system comprising: a plurality of processing units; and memory having stored therein sequential multiple-operation instruction words for each of plural threads of computation, each instruction word comprising plural fields, each field identifying an operation for a respective one of the plurality of processing units such that all operations identified by a multiple operations instruction word may be executed simultaneously on respective processing units with processing of a single thread; each processing unit comprising a synchronizer for selecting one of plural threads of computation for execution in that unit, the unit then executing the operation identified in the respective field of a next instruction word for the selected thread of computation, the synchronizer allowing parallel units to simultaneously execute operations from different thread instruction words such that execution of multiple-operation instruction words for plural threads is interleaved across the plural units; each processing unit comprising a processing pipeline which includes the synchronizer as one stage thereof and a read register stage which precedes the synchronizer stage, the read register stage reading operands from a register file and supplying those operands to an operation buffer, the operation buffer storing operations with operand data for each of plural threads of computation prior to execution, the synchronizer stage dynamically selecting an operation for execution after its operands have been stored in the operation buffer.