1. A microprocessor configured to execute a first instruction, wherein an encoded representation of said first instruction includes an opcode field, a first operand field, and a second operand field, said microprocessor comprising: an execution unit coupled to receive a decoded value of said opcode field, a first operand specified by a value of said first operand field, and a second operand specified by a value of said second operand field, wherein said execution unit is configured to perform an extreme value operation on said first operand and said second operand in response to receiving said decoded value of said opcode field; and wherein said execution unit is further configured to convey an output value of said extreme value operation as a result of said first instruction.