1. A method of floorplanning a chip design represented by a netlist of macros to minimize the power dissipated by the chip, the method comprising the steps of: a) subdividing the chip design into a plurality of voltage island partitions, each of said partitions consisting of a plurality of macros, each of said voltage island partitions having a unique voltage; b) grouping the voltage island partitions to minimize the total number of voltage island partitions; and c) iteratively rearranging the voltage island partitions and the macros placed therein to minimize any empty space within the voltage island partition.