1. An apparatus comprising: a layered stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the physical layer logic is to generate a supersequence comprising a repeating sequence comprising an electrical ordered set (EOS) followed by a plurality of training sequences, the plurality of training sequences comprises a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header, the training sequence header is to identify a type of the corresponding training sequence, and the training sequence header is to be DC-balanced over the plurality of training sequences.