1. A multidimensional switch network for a processor array, comprising: multiple switches for routing packets between multiple core circuits of said processor array, wherein said multiple switches are organized into multiple planes; at least one redundant switch organized into at least one redundant plane; and multiple data paths interconnecting said multiple switches and said at least one redundant switch, wherein said multiple data paths include at least one redundant data path interconnecting a pair of non-neighboring switches; wherein at least one switch of said multiple switches is configurable to exchange packets with a non-neighboring switch via a redundant data path to bypass one of said multiple planes when said bypassed plane includes a component failure of said processor array, and allow recovery of said bypassed plane using said at least one redundant plane.