1. A computer system comprising: at least one processor comprising a plurality of processor cores, each of the plurality of processor cores having at least one cache; and an interface that includes an associated cache that is shared by each of the plurality of processor cores, the interface preloading the associated cache with instruction data fetched by the interface from a predetermined address in non-volatile memory as part of a reset sequence so that the instruction data in the associated cache is available to each cache that is associated with a processor core to facilitate reset by the computer system, wherein the instruction data preloaded into the associated cache comprises instructions executable by at the at least one processor for at least one of testing and validating at least one of the at least one cache and at least one processor core of the plurality of processors cores.