1. A processor, comprising: a floating point unit; a logic circuit coupled to the floating point unit, wherein the logic circuit is configured to: receive an operation, a first operand and a second operand, wherein each of the first operand and the second operand include a sign and exponent block, a length block, and one or more mantissa digits; perform the received operation on the first operand and the second operand to generate a first result, wherein the first result includes a sign and exponent block, a length block, and one or more mantissa digits; process each of the first operand and the second operand responsive to a determination that the first operand and the second operand are fixed-length numbers; and perform, responsive to the determination that the first operand and the second operand are fixed-length numbers, the received operation on the processed first operand and the processed second operand to generate a second result, wherein the second result includes a sign and exponent block, and one or more mantissa digits.