1. A method performed by an asynchronous processor comprising a matrix of arithmetic and logic units (ALUs) and a plurality of bundle registers (BRs), each ALU in a respective row of the matrix of ALUs sharing a corresponding BR, the method comprising: receiving, by each corresponding BR, a corresponding bundle of instructions at a first same time, each corresponding BR in the plurality of BRs receiving a different corresponding bundle of instructions at the first same time; and receiving, by each ALU in a respective row of the matrix of ALUs from the corresponding BR, a corresponding instruction in a plurality of instructions in the corresponding bundle of instructions, each ALU in a respective column of the matrix of ALUs accessing resources using gating and passing of a plurality of tokens to process the corresponding instruction in the plurality of instructions, the plurality of tokens being shared with other ALUs in the respective column of the matrix of ALUs, at least one column of the matrix of ALUs accesses different resources than another column of the matrix of ALUs, and each column of ALUs using a different set of token passing rings.