1. Apparatus comprising an arithmetic pipeline (having no central processing unit or software in itself) for image processing for solving an equation of the form ##EQU16## which indicates the summation of K terms having integer values of i from 1 to K inclusive, where, A.sub.i and B.sub.i are each an N-bit implied one floating point number consisting of a sign bit, an exponent of P bits, and a data part of Q bits; m.sub.i and n.sub.i can each take on a value selected from zero, given positive integral powers of two, and 1 divided by given positive integral powers of two; +/- indicates a summing operation which is either an add or a subtract for each value of i, and .times./.div. indicates a product operation which is either a multiply or a divide for each value of i; wherein said apparatus comprises a log section and a separate floating point section; the log section comprises two log-transform units A and B for A and B inputs respectively, a log-sum-or-difference unit having A and B inputs coupled respectively to outputs of the log-transform units A and B, and an antilog-transform unit having an input from the log-sum-or-difference unit and an output to the floating point section; the two log-transform units being identical, each having read-only memory with tables therein, and associated registers, logic and arithmetic circuits, for transforming an input floating point number into a log format in which the exponent becomes a characteristic and the data part becomes a mantissa, a plurality of the registers being coupled in tandem to repeat with delay the (1+P) bits of the sign and exponent to provide the sign and characteristic for output to the log-sum-or-difference unit, the Q bits of the dta part being converted to the mantissa by a piecewise linear approximation based on values stored in said tables, the resulting mantissa being transferred to the log-sum-or-difference unit; the log-sum-or-difference unit having an A shifter to which is supplied an A log value comprising the combination of the characteristic and mantissa from the A log-transform unit, and a separate B shifter to which is supplied a B log value comprising the combination of the characteristic and maintissa from the B log-transform unit, means for controlling the shifters to shift each of said A and B log values an amount depending on the value of m.sub.i for the A shifer and n.sub.i for the B shifter to provide resulting A and B log values in the A and B shifters respectively, arithmetic logic means coupled to the A and B shifters for adding or subtracting the resulting A and B log values depending on whether the product operation is multiply or divide for the value of i to provide a log sum, and number sign means for determining the number sign of said log sum depending on the number signs of the A and B log values; wherein the antilog-transform unit comprises structure like that of the log-transform units, having read-only memory with tables therein, and associated registers, logic and arithmetic circuits, for transforming said log sum from the log-sum-or-difference unit into a floating point number in which the characteristic becomes an exponent and the mantissa becomes a data part, a plurality of the registers being coupled in tandem to repeat with delay the (1+P) bits of the sign and characteristic to provide a sign and exponent for said floating point number, the Q bits of the mantissa being converted to a data part for said floating point number by a piecewise linear approximation based on values stored in said tables of the antilog-transform unit, corresponding to the piecewise approximation used in the log transforms, the resulting floating point number comprising said sign and exponent with said data part being transferred along with said sign and exponent to the floating point section; the floating point section comprises a float-to-fixed unit, a M-bit arithmetic logic unit, and fixed-to-float unit; wherein the float-to-fixed unit comprises means including a shifter, registers, logic and arithmetic circuits, for converting said floating point number from the antilog-transform unit into a fixed point number having a binary number point, and for aligning the binary points of the fixed point numbers for terms with successive values of i, with input from the antilog transform unit and output to the M-bit arithmetic logic unit; wherein the M-bit arithmetic logic unit comprises means to accumulate successive terms to form an accumulated M-bit number, taking account of the number sign of each term, with output of the accumulated M-bit number to the fixed-to-float unit, M being an integer greater than N; and wherein the fixed-to-float unit comprises means for converting the accumulated M-bit number from the M-bit arithmetic logic unit to a floating point format.