1. An apparatus comprising: execution circuitry within a processor to execute a process, the execution unit to execute a single restore instruction to retrieve micro-architectural state and the architectural state upon a resumed execution of the process, wherein the micro-architectural state contains information that is not visible to software including contents of reorder buffers, retirement registers, and performance data resulting from the execution of the process and is used as an intermediate starting point for the resume execution to increase efficiency of the execution; and power management hardware coupled to execution unit, wherein the power management hardware is to monitor execution of the process to collect the performance data.