1. A memory device comprising: a first memory cell array on a first tier; and a second memory cell array on a second tier, the second tier being arranged in an integrated circuit package which encloses both the first and second tiers so the second tier is arranged over the first tier, or vice versa; and a control circuit configured to perform a first read/write operation by writing a first data value to a first group of memory cells on the first tier while concurrently reading a second data value from a second group of memory cells on the second tier.