1. A computer-implemented method, comprising: generating a synchronous netlist from a synchronous circuit design representation, the synchronous netlist including combinational logic gates and state-holding elements; automatically substituting, using a computer, asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core; and converting the synchronous netlist to an asynchronous circuit design representation.