1. A processor comprising: a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level; a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level the first and second cores being in a dynamic multi-core unit; and a virtual-to-physical (V-P) mapping circuit coupled to the first and second physical cores, to map the first physical core to a system firmware interface via a virtual core and to hide the second processor core from the system firmware interface.