1. An apparatus comprising: fetch logic to fetch first instruction information for a first thread and to fetch second instruction information including a store instruction for a second thread, the fetch logic further to mark the second instruction information as speculative; execution logic coupled to the fetch logic to execute the store instruction with the second thread; in response to the second instruction information including the store instruction being marked as speculative, store blocker logic to prevent data associated with a store instruction executed by the second thread from being stored in the memory system; and dependence blocker logic to prevent forwarding of the data associated with the store instruction to the first thread.