1. A data processing system for handling multiple tasks and comprising: at least two processors intended for data processing; a memory unit for storing programs and data; an input/output unit; and a data address and control signal transmission line connected to said processors, said memory unit and said input/output unit; wherein each of said processors comprises: an arithmetic-logic unit performing arithmetic and logic operations in the course of data processing and having a control input and an input/output means; a scratch pad memory storing intermediate results in the course of data processing and having a control input; a processor status register storing the current status word of said processor and having a control input, and output and an input/output means connected to said input/output means of said arithmetic-logic unit; an interface means to ensure interaction between said processor and said memory unit, said input/output unit and each of the processors over said data address and control signal transmission line, and having a control input and an input/output means connected to said data address and control signal transmission line; an address interrupt unit to interrupt the execution of a program by said processor through using means for addressing memory locations of the processor, and having an input/output means connected to said data address and control signal transmission line, an input, a first output and a second output; a control unit to form signals to control said arithmetic-logic unit, said scratch pad memory, said interface means, said processor status register and said address interrupt unit in the course of data processing, and having a first control output connected to said control inputs of said arithmetic-logic unit, said scratch pad memory, said interface means and said processor status register, a first input connected to said output of said processor status register, a second input connected to said second output of said address interrupt unit, and a second control output connected to said input of said address interrupt unit; and a processor data bus to interconnect said arithmetic-logic unit, said scratch pad memory, said processor status register and said interface means, and connected to said first output of said address interrupt unit; wherein said address interrupt unit comprises: a group of interrupt vector registers, each of said interrupt vector registers having an input connected to said input/output means of said address interrupt unit, an output connected to said first output of said address interrupt unit, a first control input and a second control input; a first group of AND gates, each of said AND gates having an output connected to said first control input of a respective register of said group of interrupt vector registers, a first input, and a second input connected to said input of said address interrupt unit; a second group of AND gates, each of said AND gates having an output connected to said second control input of a respective register of said group of interrupt vector registers, a first input, and a second input; a first priority circuit having an output connected to said first input of each of said AND gates of said first group of AND gates, and an input; a second priority circuit having an output connected to said first input of each of said AND gates of said second group of AND gates, and an input; an AND gate having an input and an output; an OR gate having an output connected to said second output of said address interrupt unit, and an input; a status register having a first input connected to said outputs of each of said AND gates of said first group of AND gates, a second input connected to said outputs of each of said AND gates of said second group of AND gates, a first output connected to said input of said first priority circuit, to said input of said AND gate and to said input of said OR gate, and a second output connected to said input of said second priority circuit; a write pulse forming unit having a first input connected to said output of said AND gate, an output connected to said second input of each of said AND gates of said second group of AND gates, an input/output means connected to said input/output means of said address interrupt unit, and a second input; and an address decoder having an output connected to said second input of said write pulse forming unit, and an input connected to said input/output means of said address interrupt unit.