1. A circuit arrangement for counting the number of like binary bits in a binary word of x.gtoreq.8 bits, said arrangement comprising at least first and second combinatorial logic circuits including y.sub.1 &gt;3.ltoreq.x/2 and y.sub.2 .ltoreq.x-y.sub.1 factorial logic elements, respectively, and input means adapted responsive to external signals representative of said binary word to apply to said elements of said first and second circuits y.sub.1 and y.sub.2 bits of said binary word, respectively, said circuit arrangement also including an adder circuit for adding together two N&gt;3 bit words produced by said logic circuits, where N equals the larger of y.sub.1 and y.sub.2, each of said first and second circuits being adapted to apply an N bit word to said adder circuit.