1. In a single-instruction multiple data (SIMD) parallel processor comprising a controller and an array of physical processors controlled in parallel by instructions supplied by said controller, each processor comprising an input, an output, a processing element and an associated memory element coupled to said processing element for storing information from and supplying information to the processing element and comprising at least one memory location, the processing element operating on data provided by its input and said associated memory element, in accordance with instructions provided by said controller, to produce data at its output, a method of simulating the presence of a larger number of processors in the array than the number of said physical processors, thereby to provide a corresponding number of so-called "virtual processors" usable for executing user programs, and of utilizing said virtual processors, comprising the steps of: (a) before executing a user program, subdividing the memory elements asociated with each of a plurality of physical processing elements to form a plurality of m sub-memories associated with each processing element each of v bits in length, where m is a variable number provided before a user program is executed and m may range from 1 to at least tens of thousands; (b) providing an instruction from the controller to a set of the physical processors to cause the processing elements thereof to process data stored at a corresponding location in a first sub-memory associated with each such processing element; and (c) at a subsequent time within a time allowed for the execution of said instruction, providing said instruction from the controller to such set of physical processors to cause the processing elements thereof each to process data stored at a corresponding location in a second sub-memory associated with each such processing element.