1. An apparatus comprising: a core configured to execute memory instructions that access data stored in physical memory based on virtual addresses translated to physical addresses based on a hierarchical page table having multiple levels that each store different intermediate results for determining final mappings between virtual addresses and a physical addresses; and a memory management unit (MMU) coupled to the core, the MMU including a first cache that stores a plurality of the final mappings of the page table, a page table walker that traverses the levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker; wherein the MMU is configured to compare a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address; wherein the comparison is based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache; and wherein the MMU is configured to remove any entries in the second cache that satisfy the match criterion.