1. A method, comprising: generating a synchronous netlist from a synchronous circuit design, the synchronous netlist including combinational logic gates and state-holding elements; converting the synchronous netlist to an asynchronous circuit design, the converting including grouping the combinational logic gates by operations into functions; and generating annotations by an annotation generator to map performance chartacteristics from the asychronous circuit design into the synchronous circuit design to validate timing characteristics of the asynchronous circuit design.