1. A method, executed by one or more processors, for optimizing placement of a logic network, the method comprising: partitioning a logic network comprising a plurality of logic elements into a plurality of logic partitions; launching a plurality of placement optimization threads that correspond to the plurality of logic partitions; allocating memory that is accessible to the plurality of placement optimization threads to provide a globally accessible placement memory; reserving a placement location for at least a portion of the plurality of logic elements via the globally accessible placement memory; and wherein each placement optimization thread of the plurality of placement optimization threads is configured to conduct the operations of: determining a desired location for a logic element of the plurality of logic elements, reserving, via the globally accessible placement memory, a plurality of potential locations for the logic element that are proximate to the desired location, determining a best location from the plurality of potential locations, and placing the logic element at the best location.