1. A cache control apparatus comprising: a coherency controller client configured to include an MESI register that is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache; and a coherency interface connected to the coherency controller, and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.