1. A controller for controlling a data processor having a plurality of SIMD (single instruction multiple data) processor arrays, each of which includes a plurality of processing elements, the controller comprising: a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another; and a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays, wherein the distribution unit is operable to distribute the instruction streams to a plurality of first function controllers operable to control the processing elements in respective processor arrays, and to a plurality of second function controllers operable to control input/output functions of respective arrays of processing elements, the first and second function controllers operating asynchronously.