1. An electronic device comprising a semiconductor memory unit that includes: a plurality of data transfer lines; a plurality of columns respectively corresponding to the plurality of data transfer lines in one-to-one correspondence; one or more redundancy columns; a plurality of first switches, each selectively providing an electrical connection between one of the plurality of data transfer lines and a corresponding one of the plurality of columns; and a plurality of second switches, each selectively providing an electrical connection between one of the plurality of data transfer lines and the one or more redundancy columns.