1. A computer-implemented method comprising: receiving a software interrupt; responsive to receiving the software interrupt, determining whether the software interrupt is latency sensitive; responsive to determining the software interrupt is latency sensitive, determining whether a current processor core is interrupt heavy; responsive to determining the current processor core is interrupt heavy and that the software interrupt is latency sensitive, determining a desired processor core other than the current processor core to run the software interrupt; and responsive to determining the desired processor core other than the current processor core, executing the software interrupt on the desired processor core.