1. A processing device for controlling two hierarchical level data caches, comprising: a memory interface unit which connects said processing device to a main memory; an internal cache included in said processing device and controlled as a first level cache; a cache control unit which controls an external cache as a second level cache; and a processor which executes a prefetch instruction included as one of a plurality of instructions of a program to be executed in said main memory, wherein said prefetch instruction, when executed, causes said processor to perform a prefetch operation by transferring operand data to be used in a subsequent operation from said main memory to said external cache only, not to said internal cache, prior to executing said subsequent operation.