1. An integrated circuit microprocessor comprising: means for providing a pair of 8-bit operands; a parallel binary adder having 8 stages receiving the corresponding order operand bits and corresponding order carry-in bits and providing corresponding order straight binary sum bits and corresponding order straight binary carry-out bits; means for selectively providing a decimal operation command signal; first gating means responsive to said command signal for selectively modifying the 4th and 8th order binary carry-out bits concurrently with the binary addition of the operands by the adder to provide a 4th and an 8th order decimal carry-out bits and for applying the OR-function of the 4th order binary and decimal carry-out bits to the 5th adder stage as a carry-in bit; and second gating means responsive to said command signal for modifying said binary sum bits to provide an 8-bit result corresponding selectively to the binary coded decimal sum or difference of the operands.