1. A microprocessor, comprising: a branch target address cache (BTAC), wherein each entry of the BTAC is configured to store branch prediction information for at most N branch instructions; an execution unit, configured to execute a branch instruction previously fetched from an instruction cache in a fetch quantum; and update logic, coupled to the BTAC and execution unit, configured to: determine whether the BTAC is already storing branch prediction information for N branch instructions within the fetch quantum, wherein N is at least two; update the BTAC with branch information for the branch instruction, if the BTAC is not already storing branch prediction information for N branch instructions within the fetch quantum; determine whether a type of the branch instruction has a higher replacement priority than a type of the N branch instructions already stored in the BTAC, if the BTAC is already storing branch prediction information for N branch instructions within the fetch quantum; and update the BTAC with branch information for the branch instruction, if the type of the branch instruction has a higher replacement priority than the type of the N branch instructions already stored in the BTAC.