1. A two-input logic gate circuit, comprising: a first input; a second input; an Independently-Double-Gated (IDG) field effect transistor (FET) including, a substrate, a bottom gate disposed on the substrate and coupled to the second input, a source, a drain, a channel disposed on the bottom gate and coupled to and disposed between the source and the drain, the channel providing a junction contact to the bottom gate to form a Junction FET (JFET); a gate insulator disposed on the channel, a top gate disposed on the gate insulator to form a MOS FET, wherein the top gate is coupled to the first input; and an output.