1. An apparatus comprising: a processor including: M simultaneous multithreading (SMT) physical threads to support N switch-on-event software threads, wherein N is greater than M, and wherein M is an integer greater than one; a first set of hardware storage structures to maintain M active values for each of a plurality of elements of an architecture state for the processor, the M active values to be associated with M of the N switch-on-event software threads to be currently active; a second set of hardware storage structures coupled to the first set of storage structures in a cross-bar configuration, the second set of hardware storage structures to maintain N-M inactive values for each of the plurality of elements of the architecture state for the processor wherein the cross-bar configuration includes an M:1 multiplexer; and hardware thread switch control logic to perform a timing-critical thread switch, the hardware thread switch control logic to modify a selected one of said N-M inactive values for each of the plurality of elements and a selected one of said M active values for each of the plurality of elements responsive to a thread switch indicator signal being enabled to each of the plurality of elements, wherein the timing-critical thread switch satisfies a critical path timing requirement for accessing of the architectural state for the processor.