1. A system for processing an operation, comprising: a hardware accelerator unit comprising a plurality of types of circuitries; a microengine configured to issue a plurality of command sets to the hardware accelerator unit, wherein each type of circuitry is configured to receive one command set from the microengine and each command set is configured to allow processing of a plurality of different sets of operations by one type of circuitry; a shared memory unit operatively connected to the microengine, the shared memory unit configured to store control information for access by the microengine, wherein the control information is configured to specify at least one set of operations for processing by the one type of circuitry; and a hardware configuration register located within each of the plurality of circuitries, the hardware configuration register configured to receive configuration data from the microengine, wherein the configuration data corresponds to the specified at least one set of operations.