1. A computer system, comprising: a home cluster including a first plurality of processors and a home cache coherence controller, the first plurality of processors and the home cache coherence controller interconnected in a point-to-point architecture; a remote cluster including a second plurality of processors and a remote cache coherence controller, the second plurality of processors and the remote cache coherence controller interconnected in a point-to-point architecture; wherein the remote cluster cache coherence controller is configured to receive a probe request associated with a memory line and send a memory cancel to the home cluster if a probed memory line associated with one of the second plurality of processors is dirty.