1. A semiconductor wafer analysis system comprising: a tester adapted to output test results responsive to a test of presence and type of defects on semiconductor wafers manufactured by at least one manufacturing facility; a wafer map generation module adapted to generate wafer maps based on the test results from the tester; and a wafer analysis module including a data generation module and an operation module, the data generation module adapted to divide each wafer map into a plurality of defect analysis regions and to generate feature vectors having defect values, which representing the semiconductor wafers at least one defect type occurring in each defect analysis region, as a plurality of component values, and the operation module adapted to statistically analyze the feature vectors so as to assist in the determination of a defective one or ore of the manufacturing facilities.