1. In a computer system having at least one central processing unit (CPU), a clock having cycles with at least first and second phases, and a cache arrangement comprising a cache data array and a cache tag array, said computer system having a first bus for conveying virtual addresses for accessing said cache memory and a second bus for conveying other information to said cache memory, the improvement comprising: a first cache tag array coupled to said first bus and to said second bus wherein during said first phase of said clock cycle, said cache tag array is accessed from said first bus and during said second phase of said clock cycle, said first cache tag array is available to receive a snoop address from said second bus; and a second cache tag array coupled to said first bus and to said second bus for being available to receive snoop addresses from said second bus during said first phase of a clock cycle and for accessing by said first bus during said second phase of a clock cycle; whereby addresses from which information is to be retrieved can be processed by said first cache tag array while detected snoop address are processed by said second cache tag array and vice versa.