1. A processor, comprising: instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, wherein each of said plurality of thread groups comprises a subset of said plurality of threads, to issue a first instruction from one of said plurality of threads during one execution cycle, and to issue a second instruction from another one of said plurality of threads during a successive execution cycle; and a plurality of execution units, each configured to execute instructions issued from a respective thread group.