1. In a superscalar microprocessor, a computer circuit for predicting the target location of a branch instruction supplied in a sequence of instructions, said computer circuit comprising: a first and a second pipeline for receiving and processing said sequence of instructions, each pipeline including a decoder including logic to associate said instructions with one of said pipelines, including associating a branch instruction with a non-branch instruction, each of said pipelines also including an execution unit for executing a branch instruction; a branch target buffer, responsive to instructions in the pipeline for supplying a predicted target address to the pipeline, said branch target buffer including a plurality of entries having a tag field for storing a tag indicative of the address of a first instruction pair immediately preceding a second instruction pair that includes a branch instruction. an address field for storing a target address predicted for the branch instruction, and a history field for storing a history of the takenness of the branch; a circuit for supplying a current address of an instruction pair in a preselected stage of the pipeline to the branch target buffer; and a circuit for comparing said current address with the address in the tag field.