1. A multiprocessor system comprising: a first microcomputer having a first central processor unit (CPU), a first read-only memory (ROM), a first random access memory (RAM), and a first I/O port connected to an internal bus; a second microcomputer having a second CPU, a second ROM, a second RAM, a second I/O port and a dual port RAM connected to said internal bus; an external address bus for connecting an internal address bus of said first microcomputer to said second microcomputer; an external data bus for connecting said dual port RAM to an internal data bus of said first microcomputer; and address setting means, provided within the second microcomputer and coupled to said external address bus, the address setting means comprising: logical address value holding means for holding a logical address value supplied from said first CPU; offset value holding means, coupled to the internal address bus of said second microcomputer, for holding an offset value which is set by said second CPU; and address output means for receiving values output from said logical address value holding means and said offset value holding means, calculating a physical address value in said dual port RAM based on these values, and outputting this physical address value to said dual port RAM; wherein said dual port RAM is divided into a first portion having a first area and a second portion having a second area, said first portion storing data to be transferred from said first RAM at an address specified by said first CPU and said second portion storing data required by the first microcomputer to be written by said second CPU and to be read and transferred to said first microcomputer; and wherein a change in said offset value results in a change in an area ratio between said first and second portions of said dual port RAM.