1. Combined adding and rounding circuitry for a programmable logic device, for adding two multi-bit input numbers and rounding a resulting sum to a user-programmable bit position selectable from among a subset of available bit positions, said combined rounding and adding circuitry comprising: multi-bit addition circuitry; and input circuitry for (a) accepting, in each bit position, bits of said two multi-bit input numbers and (b) accepting, for each respective bit position in said subset, an additional input of a rounding bit indicative of whether said respective bit position is said user-programmable bit position, said input circuitry outputting data to said multi-bit addition circuitry in a format common to each bit position regardless of the number of inputs to said input circuitry at said bit position.