1. A non-volatile memory device, comprising: a channel layer vertically extending from a substrate; a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer; and a memory layer interposed between the channel layer and each gate electrode, wherein the memory layer includes a charge storage laver, a tunnel insulation layer interposed between the charge storage layer and the channel layer, and an air gap interposed between the charge storage layer and each gate electrode.