1. Apparatus for processing data comprising: a translation buffer unit to store translation data to translate an input address of a memory access transaction to an output address; and a translation control unit to provide said translation data to said translation buffer unit, wherein said translation buffer unit is responsive to receipt of a memory access transaction for which translation data is unavailable in said translation buffer unit to issue a request to said translation control unit to provide translation data for said memory access transaction; said translation control unit is responsive to a change in enablement of address translation for a given type of memory access transaction to issue an invalidate command to said translation buffer unit to invalidate any translation data for said given type of memory access transaction stored in said translation buffer unit; and said translation control unit is responsive to receipt of a request for translation data from said translation buffer unit for a memory access of said given type for which memory address translation is disabled to return global translation data to be used by said translation buffer unit for all memory access transactions of said given type.