1. A method for generating code for a fixed-width instruction set, comprising: identifying a non-contiguous register specifier; and generating a fixed-width instruction word that includes the non-contiguous register specifier, where an instruction field in the fixed-width instruction word directly specifies a first set of bits in the non-contiguous register and a second set of bits in the non-continuous register specifier is specified using a deep encoding; and generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than m, and the deep encoding involves allocating multiple opcode points or extended opcode points to indicate the fixed-width instruction, wherein each of the opcode points or the extended opcode points further indicates the use of a specific bit string as an extended register specifier.