1. A bridge fused multiply-adder circuit, comprising: a floating-point adder; a floating-point multiplier; an alignment/inversion module, coupled to said floating-point adder, for sharing an input with said floating-point adder; and a bridge module, coupled to said floating-point adder and said floating-point multiplier, for combining a partial product from said floating-point multiplier with an output from said alignment/inversion module to generate an un-rounded output to be fed to said floating-point adder to produce a fused multiply-add result.