1. A computer-readable memory provided with an information refinement detection function including a content-addressable memory (CAM) capable of storing information in each memory address, comprising: (1) an input section for entering first comparison data for being compared in parallel with each data item of the information stored in each memory address and second comparison data for comparing in parallel memory addresses, wherein the first and second comparison data are externally provided; (2) a first determining section for determining and outputting a data match/mismatch result by comparing in parallel the each data item of the information stored in each memory address with the first comparison data; and (3) a second determining section for determining and outputting a memory address match/mismatch result for each memory address by comparing in parallel between the memory addresses the data match/mismatch results of each memory address determined by the first determining section, according to the second comparison data; wherein the second determining section comprises a logic operation section for applying a logic operation between the data match/mismatch results of each memory address, wherein the logic operation of the memory is a logical product (AND) operation, and the memory further comprising: (1) a storing section for storing at least one or more addresses which are determined to have the data match result to become first survivor addresses when the each data item stored in the memory is compared in parallel with the first comparison data in a first information detection; (2) an address transposition section for transposing memory addresses, which are determined to have the data match result when the each data item stored in the memory is compared in parallel with a new set of the first comparison data in subsequent information detections, to obtain transposed addresses by transposing, using a shift register, the memory addresses according to the second comparison data; and (3) a first output section for outputting addresses which are determined to pass the logical product (AND) operation applied on the first survivor addresses and the transposed addresses.