1. A system comprising: a plurality of processors; and a multi-level memory hierarchy; wherein a first processor of the plurality of processors is configured to: detect a miss for a memory request in a first memory; send the memory request to a second processor of the plurality of processors responsive to detecting an indication that the data targeted by the memory request is stored in a second memory; and generate a page fault and send the memory request to a third memory responsive to detecting an indication that the data targeted by the memory request is not stored in the second memory.