1. A processor, for executing instructions of a program stored in compressed form in a program memory, comprising: a program counter which identifies a position in said program memory; an instruction cache, having a plurality of cache blocks, each for storing one or more instructions of said program in decompressed form; a cache loading unit, comprising a decompression section, operable to perform a cache loading operation in which one or more compressed-form instructions are read from said position in the program memory identified by the program counter and are decompressed and stored in one of said cache blocks of the instruction cache; a cache pointer which identifies a position in said instruction cache of an instruction to be fetched for execution; an instruction fetching unit which fetches an instruction to be executed from the position identified by the cache pointer and which, when a cache miss occurs because the instruction to be fetched is not present in the instruction cache, causes the cache loading unit to perform said cache loading operation; and an updating unit which updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that said position identified by said program counter is maintained consistently at the position in said program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.