1. A microprocessor configured for parallel processing of a plurality of threads, wherein each thread includes a sequence of instructions, the microprocessor comprising: an execution module configured to execute instructions for all of the plurality of threads; an instruction buffer including a plurality of storage locations, each storage location being associated with a respective one of the plurality of threads; a fetch circuit configured to select one of the plurality of threads based at least in part on whether the associated storage location in the instruction buffer is available and to fetch a next instruction in the sequence for the selected one of the plurality of threads into the instruction buffer; and a dispatch circuit configured to determine which of the stored instructions in the instruction buffer is ready to execute and to select one of the ready instructions to be issued to the execution module.