1. A method of designing an integrated circuit, comprising: receiving a functional description of said integrated circuit; placing and routing a plurality of synthesized entities to create a physical design implementation for said integrated circuit, wherein each synthesized entity of said plurality of synthesized entities comprises a portion of said functional description of said integrated circuit that has been synthesized into a gate-level implementation; and manipulating said plurality of synthesized entities to facilitate said physical design implementation satisfying a plurality of design constraints, wherein said manipulating comprises using physical design information of said physical design implementation to ensure satisfying said plurality of design constraints.