1. A data processing system comprising: means for providing sequential clock cycles individually corresponding to single system computation cycles; means for storing a plurality of instructions in sequence within an instruction memory; means for selectively dispatching a plurality of instructions following the sequence in which the instructions were stored in the instruction memory during a single clock cycle to selected processors for execution; means for determining for each instruction to be dispatched by the means for dispatching whether that instruction may when executed be dependent upon a bit in a condition register characterizing a previous instruction result; means for monitoring the setting of said bit in said condition register and providing an indication thereof; and control means for selectively delaying the dispatch of one or more instructions during the clock cycle when said means for determining indicates that the instruction is dependent upon the setting of said bit and that said means for monitoring indicates that said bit has not been set.