1. A processor comprising: a plurality of execution units; a plurality of registers; and a control logic to receive an instruction that specifies a subset of registers of the plurality of registers during a transition of the processor from an active state to a low-power mode, the instruction further specifying a pointer to a handler function to be executed after waking from the low-power mode to monitor for work to be performed by the processor, wherein the control logic is to cause the subset of registers to be stored to a persistent storage, and thereafter the processor is to enter the low-power mode, and after waking from the low-power mode, restore the subset of registers, jump to the handler function, and check for work to be performed.