1. A digital data processing apparatus, comprising: at least one processor, each said at least one processor executing at least one respective thread of processor-executable instructions, said at least one processor collectively including: (a) a plurality of parallel pipelines, each pipeline of said plurality of parallel pipelines having the capability to perform a set of pre-defined functions on respective input data; and (b) control logic controlling the routing of data to said plurality of parallel pipelines, wherein said control logic, responsive to detection of a failure of a first pipeline of said plurality of parallel pipelines, causes data intended for processing by said first pipeline to be processed by a second pipeline of said plurality of parallel pipelines.