1. A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising: receiving instructions for detecting one or more critical memory hazards between memory addresses if memory operations are performed in parallel on multiple addresses corresponding to at least a partial vector of addresses, wherein critical memory hazards include memory hazards that lead to different results when the memory addresses are processed in parallel than when the memory addresses are processed sequentially; and executing the instructions for detecting the one or more critical memory hazards.