1. A cache coherent subsystem of a System-on-Chip (SoC), the SoC associated with a system address space representing all memory locations addressable by the SoC, each system address within the system address space consisting of a first number of address bits representing the entire system address space, the cache coherent subsystem associated with a plurality of predefined coherent-capable memory regions distributed within the system address space, each of the coherent-capable memory regions corresponding to a memory, the subsystem comprising: at least one agent that produces a system address within the system address space; at least one address compression unit comprising hardware logic, the address compression unit configured to accept the system address from the at least one agent; and the hardware logic configured to map each system address within the plurality of coherent-capable memory regions into a smaller address space that exclusively represents all addresses of the plurality of coherent-capable memory regions, the address compression unit configured to use the hardware logic to: determine whether the system address is within a memory region of the plurality of coherent-capable memory regions; in response to determining the system address is within a memory region of the plurality of coherent-capable memory regions, produce a compressed address represented by a second number of address bits, the compressed address consisting of fewer bits than an original system address, and using the compressed address to access the memory region of the plurality of coherent-capable memory regions.