1. A channel encoder for encoding received n-bit information words into m-bit, mainly DC-free, code words, where m&gt;n, said channel encoder comprising: a. a precoder having a transfer function (1+D.sup.m-n).sup.-1, where D is a delay operator, said precoder having an input for receiving said n-bit information words in series with (m-n)-bit words and an output for supplying said m-bit code words, said precoder forming said m-bit code words from said n-bit information words and said (m-n)-bit words, so that said m-bit code words are run length limited; b. a counter for determining a digital sum variation (DSV) between two successive m-bit code words, said counter having an input coupled with the output of said precoder for receiving said m-bit code words, and an output at which said digital sum variation is provided; and c. a memory circuit having a first input coupled with the output of the counter for receiving said digital sum variation, a second input for receiving said n-bit information words, and a third input coupled with said precoder for receiving said m-bit code words, said memory circuit forming a digital sum value of said m-bit code words and forming said (m-n)-bit words by logically combining said digital sum value with said digital sum variation and (m-n) bits of received m-bit code words, said memory circuit having an output for supplying said (m-n)-bit words.