1. A pipelined data processor for executing in parallel an instruction of a kind other than a branch instruction and a branch instruction, said data processor comprising: main storage means; operation means for performing an operation in response to an instruction of a kind other than a branch instruction; resource means responsive to a branch instruction for retrieving a branch-to instruction from said main storage means; a pair of instruction registers; set means for retrieving from said main storage means and storing in said pair of instruction registers a first instruction for execution by said data processor during the next cycle of operation thereof and a second instruction for execution by said data processor; detection means for detecting whether the first and second instructions in said pair of instruction registers are an instruction of a kind other than a branch instruction and a branch instruction; and control means responsive to said detection means detecting that one of the first and second instructions is an instruction of a kind other than a branch instruction and the other of the first and second instructions is a branch instruction for controlling the execution of said one of the first and second instructions such that the operation requested by said one of the first and second instructions is executed in a plurality of stages, including a stage executed by said operation means, controlling the execution of said other of the first and second instructions such that the operation requested by said other of the first and second instructions is executed in a plurality of stages, including a stage executed by said resource means, said first and second instructions being executed in parallel, and controlling said set means to cause a third instruction and a fourth instruction to be retrieved from said main storage means and applied to said pair of instruction registers during the execution of said first and second instructions; said control means being responsive to said detection means failing to detect that one of the first and second instructions is an instruction of a kind other than a branch instruction and the other of the first and second instructions is a branch instruction for controlling the execution of said first instruction such that the operation requested by said first instruction is executed in a plurality of stages, including a stage executed by said operation means or said resource means, and controlling said set means to cause said second instruction and a third instruction to be stored in said pair of instruction registers during the execution of said first instruction.