1. An integrated circuit comprising: a network on chip (NOC) comprising: a plurality of compute units (CUs) each comprising a processor having an instruction set and operable to delegate executable instructions intended for a respective CU processor; and a plurality of NOC nodes, interconnected to the plurality of CUs, operative to route data among the plurality of CUs, and each comprising a processor having the same instruction set as the processor in each of the plurality of CUs and operative to execute instructions that are delegated from at least one of the plurality of CUs, using the NOC node processor.