1. A microprocessor arrangement including a semiconductor integrated circuit chip, said chip comprising a first register array adapted to store the hardware context of a current process and a second register array for storing the instantaneous data being processed by said microprocessor during the execution of said current process, said first register array including a first register containing a first bit having first or second values and means responsive to said first or second values for controllably storing the contents of said first and second register arrays or the contents of only said first array, respectively, during a process switch operation.