1. A method for translating instructions for a processor, the method comprising: accessing a plurality of guest instructions that comprise multiple guest branch instructions; assembling the plurality of guest instructions into a guest instruction block; translating the guest instruction block to a corresponding first native conversion block, wherein the guest instruction block comprises instructions of a guest instruction architecture and wherein the corresponding first native conversion block comprises instructions of a native instruction architecture; accumulating translated native instructions in a native conversion buffer during the translating; storing the native conversion block into a native cache; storing a mapping of a guest far branch ending the guest instruction block to a corresponding native instruction in a conversion look aside buffer, wherein the corresponding native instruction is a first instruction in a second native conversion block; responsive to a subsequent request for the guest far branch, indexing the conversion look aside buffer using a target address of the guest far branch to determine whether a hit occurred, wherein the mapping indicates the guest far branch has the corresponding second native conversion block in the native cache; and forwarding the second native conversion block for execution responsive to the hit.