1. A processor comprising: a plurality of processing cores; and a logic engine that is shared by the plurality of processing core, the logic engine including: a translation lookaside buffer to enable the logic engine to directly access a virtual address of a thread executing on one of the plurality of processing cores, and logic to receive a control block from a first thread executed by a first processing core of the plurality of processing cores, the control block including one or more instructions for execution by the logic engine, retrieve a physical address associated with the control block from the translation lookaside buffer by identifying an address space identifier associated with the control block, identifying a page-table register associated with the control block, and retrieving the physical address associated with the control block from the translation lookaside buffer based on the address space identifier and the page-table register; and access a memory using the physical address.