1. An apparatus comprising: a processor including a plurality of cores, each core including at least one transaction register, wherein at least one core of the plurality of cores is to execute an unbounded transactional memory (UTM) transaction in a first user thread, wherein when an event is incurred during execution of the UTM transaction that causes a transition from the first user thread to a kernel mode, the at least one core is to maintain the UTM transaction after the transition to the kernel mode, suspend but not abort the UTM transaction before the transition to the kernel mode, update at least one status field of the at least one transaction register in an exception handler of the kernel mode, and thereafter execute one of a plurality of code paths in the user mode based on execution of the exception handler.