1. A multiple-bus, multiprocessing system comprising: a first bus having at least one processor coupled thereto; a second bus having at least one processor coupled thereto; a multiported memory coupled to said first bus and said second bus, said multiported memory having a pool of memory cells which are configured to transfer bus transactions between said first bus and said second bus, each of said memory cells configured to store a bus code which identifies either said first bus or said second bus as a destination bus, each of said memory cells further configured to store bus transaction information which directs said destination bus to perform a bus transaction; a first bus priority encoder coupled to a plurality of said pool of memory cells and said first bus, said first bus priority encoder configured to evaluate said plurality of memory cells to identify which memory cells designate said first bus; and concurrently with coupling of said first bus priority encoder, a second bus priority encoder coupled to said plurality of said pool of memory cells and said second bus, said second bus priority encoder configured to evaluate said plurality of memory cells to identify which memory cells designate said second bus.