1. An apparatus for decoding of low density parity check encoded data comprising: a message processing circuit in a low density parity check decoder operable to process variable node messages and check node messages in a log domain; and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain, wherein the message processing circuit and the check node calculation circuit are operable to perform iterative layer decoding.