1. A memory, comprising: an array of memory cells, each of the cells configured to store a plurality of memory states; a bit mapping circuit configured to map bits of first data to sub-groups of bits, the sub-groups having fewer bits than a byte of the first data; and a data converter circuit coupled to the bit mapping circuit and further coupled to the array of memory cells, the data converter circuit configured to receive the sub-groups of bits and convert sub-groups of bits into intermediate data corresponding to at least one memory state to be stored by memory cells of the array.