1. A processor comprising: a plurality of cores; a memory controller coupled to the plurality of cores; an interconnect coupled to the plurality of cores; and a logic coupled to the plurality of cores, in response to a first instruction, to: send a message to a second processor of a platform, the platform including the processor and the second processor, to cause the second processor to enter into a wait state; cause a hash of an authenticated code module to be computed, the authenticated code module including code to cause a secure kernel to be loaded; verify a signature of the authenticated code module with the hash of the authenticated code module; in response to verification of the signature of the authenticated code module, cause the second processor to exit the wait state; and execute the authenticated code module on the processor to validate the secure kernel, and in response to validation of the secure kernel, execute the secure kernel on the processor, the secure kernel comprising a secure virtual machine monitor.