1. In a digital signal processing architecture comprising a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array, a method for processing digital data comprises the steps of: encoding a received data input by configuring one of said re-configurable processing elements to emulate a convolution encoding algorithm and applying said received data input to said convolution encoding algorithm to produce an encoded data output; and decoding a received encoded data input by configuring said plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm, wherein said plurality of re-configurable processing elements is configured to accommodate every data state of said convolution encoding algorithm, and applying said received encoded data input to said Viterbi decoding algorithm to produce a decoded data output.