1. A phase locked loop (PLL) circuit using a Schmitt trigger to achieve a very small steady state phase error, said PLL circuit comprising: a phase comparator block for detecting a phase difference between an input reference signal and a feedback signal to produce a phase difference signal indicative of the phase difference; a low-pass filter block for producing a control voltage; a charge pump block, placed between said phase comparator block and said low-pass filter block, for charging or discharging said low-pass filer block according to the phase difference signal; a Schmitt trigger block, connected to said low-pass filter block, consisting of a plurality of Schmitt trigger circuits, each Schmitt trigger circuit having the amount of hysteresis which depends on a damping factor .zeta. of the PLL circuit as well as temperature and voltage coefficients of the control voltage, a hysteresis curve having the midpoint which is set by a current voltage characteristics of said charge pump block, said Schmitt trigger block producing Schmitt output signals which vary in response to the control voltage; a control logic circuit placed between said Schmitt trigger block and said charge pump block, said control logic circuit producing control output signals which vary in response to the Schmitt output signals, the control output signals commanding said charge pump block to turn ON or OFF; a voltage controlled oscillator (VCO), connected to said low-pass filter block, for generating a VCO output signal whose frequency is determined by the control voltage; and a frequency divider, placed between said voltage controlled oscillator and said phase comparator block, for frequency dividing the VCO output signal by a division ratio N, said frequency divider producing a divided signal as the feedback signal which is supplied to said phase comparator block.