1. An arithmetic and control unit that controls a parallel arithmetic operation by a plurality of arithmetic elements of a parallel processor including the plurality of arithmetic elements, and a plurality of memories different in hierarchy which are disposed for the plurality of arithmetic elements, the arithmetic and control unit comprising: an attribute group holding unit that acquires and holds attribute groups designated for respective data blocks of arithmetic subject and arithmetic result, the data blocks of arithmetic subject comprising read blocks in which data to be subjected to the parallel arithmetic operation is transferred to a memory of another hierarchy in the read blocks stored in a memory of a lowest hierarchy among the plurality of memories, and the data blocks of arithmetic result comprising write blocks that include an arithmetic result of the parallel arithmetic operation conducted on the read blocks in the write blocks which are transferred from the memory of the another hierarchy to the memory of the lowest hierarchy after the parallel arithmetic operation; and a scenario determination unit that determines respective transfer systems of the read blocks and the write blocks on a basis of the respective attribute groups held by the attribute group holding unit, and a configuration parameter representing a configuration of the parallel processor, and controls the transfer of the read blocks and the write blocks according to the determined transfer systems, and the parallel arithmetic operation corresponding to the transfer, wherein each of the attribute groups is necessary to determine the transfer systems, and includes one or more attributes not depending on the configuration of the parallel processor, and wherein the attribute groups of the write blocks are set assuming that each of the write blocks has already been located in the memory of the another hierarchy, and is transferred to the memory of the lowest hierarchy.