1. A chipset prefetcher in communication with a memory device having interleaved channels, comprising: a stride detector to detect a stride in a stream; a prefetch injector coupled to the stride detector to insert prefetches from the stream with the stride onto the memory device; a channel mapper coupled to the prefetch injector to map the prefetches to each channel of the memory device; a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner; a throttling heuristic to scale the number of prefetches; and a prefetch data buffer to store prefetch data.