1. A method of selecting memory elements in an integrated circuit for partial scan testing comprising the steps of: deriving a graph from the integrated circuit in which the vertices are memory elements in the integrated circuit and there is a directed edge between vertices if there is a path in the integrated circuit from a memory element corresponding to a source vertex to a memory element corresponding to a sink vertex; associating a Boolean variable with each vertex in the graph; deriving a Boolean function whose satisfying assignments correspond to feedback vertex sets of the graph without explicitly enumerating each cycle in the graph; determining which of the vertex sets is a minimum cost feedback vertex set by finding a minimum cost satisfying assignment for the Boolean function; and selecting memory elements corresponding to the vertices in the minimum cost feedback vertex set for partial scan testing of the integrated circuit.