1. A processor comprising: a plurality of cores on a single semiconductor chip; a shared cache on the single semiconductor chip, the shared cache to be shared by two or more of the plurality of cores on the single semiconductor chip and also to be shared with a plurality of accelerator devices integrated on a line card external to the single semiconductor chip, the plurality of accelerator devices on the external line card having a different instruction processing architecture from the plurality of cores; and an interconnect interface on the single semiconductor chip, the interconnect interface to couple an external cache on the external line card to the shared cache, wherein the interconnect is to operate in a manner that ensures the shared cache and the external cache are kept coherent when in operation.