1. A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, an instruction register, parallel bus means for interconnecting the arithmetic/logic unit and the registers, and control means having an input coupled to the instruction register and generating control signal outputs coupled to the arithmetic/logic unit, to the bus means and to the registers to control operation thereof in response to instruction words, all within the integrated circuit, wherein the control means includes a read-only-array having an address input coupled to said input of the control means and having outputs coupled to said control signal outputs, said control means having addressing means for applying sequences of addresses to said address input to define an operation selected by an instruction word in the instruction register, each sequence including a group dispatch to select an addressing mode using one or more of said addresses and subsequently including a function dispatch to select an arithmetic/logic function using one or more of said addresses, the group and function dispatches being controlled by fields of bits of said instruction word in said instruction register.