1. A cache coherency control circuit that shares a bus with a plurality of processors, wherein each of the processors includes a cache memory, wherein the cache coherency control circuit is exterior to each of said processors, and suspends a request of at least one of the processors during a predetermined period when one processor of said plurality of processors fetches data from a main memory to the cache memory of said one processor of the plurality of processors, wherein the cache coherency control circuit suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory, wherein said cache coherency control circuit comprises: a read administration unit; a cache line address information store unit operatively coupled to the read administration unit; and a pending instruction unit, operatively coupled to the cache line address information unit that outputs spending instruction that includes a cache line address stored in the cache line address information store unit, and wherein, when the read administration unit receives a read request from one of the processors, the read administration unit performs a read operation on a condition that a cache line address corresponding to the read request is not stored in the cache line address information store unit.