1. A programmable rule processor comprising: a general purpose register file; an instruction sequencer to provide instructions; a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer; and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.