1. A controller comprising: a processor configured to output a read command and an address to a memory, responsive to an access command received from outside, the memory including a first memory string unit and a second memory string unit, memory cells in the first memory string unit and memory cells in the second memory string unit being electrically connected to a word line, the address designating at least the first memory string unit, the second memory string unit, and the word line, wherein the controller outputs the read command and the address to read management data from the memory cells of the first and second memory string units at the same time.