1. A processor that implements a conditional move instruction, comprising: an instruction decode unit that receives the conditional move instruction and outputs a first decoded instruction and a second decoded instruction, wherein the first decoded instruction causes the processor to move a first operand to a completion buffer register if a first condition is satisfied, and the second decoded instruction causes the processor to move a second operand to the completion buffer register if the first condition is not satisfied; and an execution unit, coupled to the instruction decode unit, that executes the first decoded instruction and the second decoded instruction.