1. A processor that processes virtual interrupts in a layered virtualization architecture with one or more intervening monitors, comprising: virtual machine entry control hardware to transfer control of the processor from a host to a guest; recognition control hardware to recognize a virtual interrupt request; window control hardware to determine whether an interrupt window is open based on whether an interrupt blocking control bit in the processor is cleared, whether an interrupt blocking instruction is being executed by the processor, and whether the processor is in an activity state that blocks interrupts; evaluation control hardware to determine, based on the determination of the window control hardware, whether to transfer control of the processor from the guest to a lowest intervening monitor of the layered virtualization architecture in response to the virtual interrupt request, wherein the lowest intervening monitor is found by following a chain of child pointers; and virtual machine exit control hardware to transfer control of the processor to the lowest intervening monitor in response to the evaluation control hardware determining to transfer control and that the interrupt window is open.