1. A test circuit for a memory device having a serial input connection, and a serial output connection, comprising: a local comparison circuit for comparing data of at least two memory cells with each other, the local comparison circuit providing local result data corresponding to a fail status if one of the at least two memory cells is defective; and, a compression circuit for logically OR'ing the local result data with a global result data received from the serial input connection, for providing updated global result data to the serial output connection, the updated global result data corresponding to the fail status if at least one of the local result data and the global result data corresponds to the fail status.