1. A logic integrated circuit such as a field programmable gate array having a CPU core: wherein the CPU core is provided with registers, memories and controller for the registers and memories; wherein the CPU core has instructions including microcode; and wherein the controller has control lines for outputting enable signals to the registers and memories, reads in the instruction, and transmits ON/OFF information for each of bits composing microcode included in the instruction to registers and memories allocated to each of the bits, thereby controlling the registers and memories through the directing control lines.