1. A multi-core processor system comprising a plurality of cores; a memory controller including a plurality of ports corresponding to the cores; and shared memory including physical address spaces divided among the ports, wherein a designated core among the cores is configured to: acquire from a database storing for each software, the number of cores to which the software is to be assigned, the number of cores to which software to be executed is to be assigned; determine cores to which the software to be executed is to be assigned, based on the acquired number of cores and a state of use of the cores; set, for each of the determined cores, physical address spaces that correspond to logical address spaces defined by the software to be executed and are among physical address spaces accessible by a designated port that is among the ports and corresponds to the determined cores; notify the designated port of the set physical address spaces and the logical address spaces corresponding to the set physical address spaces; and notify the software to be executed of a start of execution after notification to the designated port has been executed.