1. An apparatus comprising: at least two processing elements having different performance capabilities and power consumption properties, wherein the first one of the at least two processing elements has a first instruction set architecture and the second one of the at least two processing elements has a second instruction set architecture different from the first instruction set architecture; logic to determine whether instructions running on a first one of the at least two processing elements may be run on a second one of the at least two processing elements at or above a minimum level of performance while consuming no greater than a maximum level of power, wherein the instructions are to be transferred from the first to the second one of the at least two processing elements if the instructions may be run at or above the minimum level of performance while consuming no greater than the maximum level of power, and wherein the instructions are to be transferred as instructions of the second instruction set architecture when the instructions running on said first one, need to be translated in order to be run on said second one of the at least two processing elements.