1. A thread-level speculation mechanism for supporting inter-thread synchronization in a transaction memory system, the thread-level speculation mechanism comprising: a content-addressable memory; an address register and a comparator; a control logic circuit for supporting non-transaction memory access instructions; means for recording a memory address and an attribute operand of a non-transaction memory access instruction; means for detecting an access event to the memory address; and means for generating a priority up event in response to detection of the access event when the attribute operand of the non-transaction memory access instruction indicates a thread-execution priority rise.