1. A processor comprising: a plurality of physical registers; a register free list comprising a plurality of entries partitioned into a plurality of banks, wherein each entry is configured to store availability information for a physical register; and a register rename unit configured to assign physical registers to architectural registers, wherein the register rename unit is configured to: receive a returning physical register identifier, wherein the returning physical register identifier corresponds to a physical register identifier that is not indicated as being available by the free list; and assign the returning physical register identifier to a destination architectural register identifier, in response to determining there is an imbalance in a number of available physical register identifiers among the plurality of banks of the free list.