1. A data processing apparatus comprising: processing circuitry for executing a sequence of instructions fetched from memory, the processing circuitry having a plurality of processor states, each processor state having a different instruction set associated therewith; pre-decoding circuitry for receiving the instructions fetched from memory and performing a pre-decoding operation to generate corresponding pre-decoded instructions; a cache for storing the pre-decoded instructions for access by the processing circuitry; the pre-decoding circuitry performing the pre-decoding operation assuming a speculative processor state, and the cache being arranged to store an indication of the speculative processor state in association with the pre-decoded instructions; the processing circuitry configured only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache in association with that corresponding pre-decoded instruction, wherein in response to an access request issued by the processing circuitry, a plurality of instructions are fetched from the cache; and error detection circuitry, responsive to one of the plurality of instructions being a state changing instruction which does not cause a branch to occur, configured to trigger a state error for any subsequent instruction in said plurality of instructions in order to initiate a fetch operation from the memory starting at a memory address immediately after a memory address of the state changing instruction.