1. A neuromorphic computing device, comprising: at least one input; at least one output; a plurality of synapse circuits electrically interconnecting said at least one input to said at least one output; said plurality of synapse circuits being configured in successive layers, each successive layer having at least one synapse circuit; wherein a subsequent said successive layer possesses fewer said synapse circuits than an immediately prior said successive layer; and a plurality of floating voltage adding nodes; wherein each of said plurality of floating voltage adding nodes electrically connects and sums outputs corresponding to at least two of said plurality of synapse circuits of any one said successive layer.