1. A method of processing an instruction fetch from an instruction cache, the method comprising: determining for a next instruction fetch whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, forcing for the next instruction fetch an address match signal for the same cache line, and refraining from the suppressing where there has been an invalidation action against the same cache line, which causes the same cache line to no longer be valid, the invalidation action result in a known-to-hit signal being negated.