1. An operation method for a low density parity check (LDPC) decoder comprising: performing, by a LDPC decoding circuit, an initial update operation to variable nodes by updating a codeword to the variable nodes; performing, by the LDPC decoding circuit, a decoding operation to the codeword based on an original parity check matrix; generating, by a parity check matrix modification circuit, when a number of unsatisfied syndrome checks (USCs) does not decrease below a predetermined number despite reaching a threshold iteration numbers of the decoding operation, a modified parity check matrix by changing data of rows of the original parity check matrix corresponding to check nodes, which are selected among a plurality of check nodes of (2*t)-th level in a (2*t)-level tree structure having one or more root nodes corresponding to the USCs, with dummy data, wherein the variable t is a separation value of a trapping set of the LDPC code when information of the trapping set is known, and has a value of ‘1’ when information of the trapping set is not known; performing, by the LDPC decoding circuit, a node update operation including check node update and variable node update based on the modified parity check matrix; and performing, by the LDPC decoding circuit, a predetermined number of single iterations until the decoding operation is successful, wherein each single iteration includes performing the decoding operation, generating a modified parity check matrix, and performing the node update operation, and wherein the decoding operation is successful when a vector generated as a result of a syndrome check of the decoding operation does not include the USCs thereby decreasing word error rates which enables a semiconductor memory device to be accurately read.