1. A neuron unit for processing a plurality of binary input signals and for outputting a neuron output signal which is indicative of a result of the processing, said neuron unit comprising: a) a plurality of first gate means for carrying out respective synchronous logical operations on a binary input signal using a synchronizing clock signal, the carrying out of the respective synchronous logical operations using weighting coefficients which are each represented by a pulse density which is defined by at least one of first and second values which are arranged at random: i) a number of the first values corresponding to a high binary signal level; and ii) a number of the second values corresponding to a low binary signal level; within a predetermined time; b) a second gate means, coupled to said first gate means, for carrying out a logical operation on an excitatory output signal of each of said first gate means; c) a third gate means, coupled to said first gate means, for carrying out a logic operation on an inhibitory output signal for each of said first gate means; and d) a fourth gate means, coupled to said second and third gate means, for synthesizing output signals of said second and third gate means and for outputting the neuron output signal.