1. An apparatus comprising: a first register to store a stack pointer value; a second register to store a stack pointer base value; a comparator coupled to the first register and the second register to produce an equivalence signal on a determination of equivalence between the stack pointer value and the stack pointer base value during a first instruction cycle, wherein the comparator comprises an exclusive NOR gate; storage coupled to the comparator to store the equivalence signal; instruction storage to store an instruction during a subsequent instruction cycle and to produce an instruction signal when a stack memory retrieval instruction is stored; and combining logic coupled to the storage and to the instruction storage to combine the equivalence signal with the instruction signal and to produce a stack exception signal upon receiving an assertive logic level in both the equivalence signal and the instruction signal.