1. A hardware processor comprising: a register file; cryptographic logic to implement a data encryption algorithm; an execution unit coupled with the register file and the cryptographic logic, the execution unit to execute an instruction to be stored in a secure memory partition of a system memory to include the secure memory partition and an unsecure memory partition; a plurality of caches to cache data from the system memory; logic coupled to the execution unit, wherein the logic is to manage access through virtual addresses and a translation look-aside buffer to the secure memory partition of the system memory; and an address base register, wherein the secure memory partition is defined by the address base register, and wherein the secure memory partition of the system memory has a higher level of security than the unsecure memory partition and is an address range that is to be accessible by a secure kernel having a first security privilege level and that is not to be accessible from a second security privilege level corresponding to application code.