1. A processor, comprising: an input portion which inputs an information word, and a plurality of partial instruction words; and a restoring portion which restores a plurality of instruction words from said information word and said plurality of partial instruction words, wherein said plurality of instruction words are executed in a same cycle, wherein said plurality of instruction words each include a plurality of bit fields, wherein said information word is composed by collecting part by part said plurality of bit fields belonging to each of said plurality of instruction words, wherein said plurality of partial instruction words each comprise each of said plurality of instruction words devoid of the bit fields forming said information word, and wherein when executing said plurality of instruction words, said restoring portion decomposes said information word into said plurality of bit field and adds each of the resultant bit fields to each of said plurality of partial instruction words to thereby restore said plurality of instruction words.