1. A programming method of a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device comprising a memory cell array in which memory cells each having a transistor in which a charge accumulation region is formed between a channel region and a control gate region via insulation film and capable of obtaining three or more memory states including two or more programmed states corresponding to the level of a threshold voltage determined depending on the quantity of charge in the charge accumulation region are arranged in plural quantities each in a row direction and a column direction, while the control gates of the memory cell on the same row are connected to each other so as to form a common word line and the drains of the memory cells on the same column are connected to each other so as to form a common bit line, wherein plural program gate voltages corresponding to each of the two or more programmed states are set up preliminarily and if between a threshold voltage range corresponding to a memory state before programming and a threshold voltage range corresponding to a memory state after programming, there exists at least a threshold voltage range corresponding to other memory state in a programming target memory cell, a first programming step is executed by applying at least a first program gate voltage corresponding to at least one of the other memory states to the word line connected to the programming target memory cell and applying a predetermined program drain voltage to the bit line connected to the programming target memory cell, then a second programming step is executed by applying a second program gate voltage corresponding to a programmed state after the programming to the word line connected to the programming target memory cell and applying a predetermined program drain voltage to the bit line connected to the programming target memory cell, and thereafter a verification step of verifying whether or not a program is made in the programming target memory cell is executed.