1. A semiconductor circuit design supporting apparatus comprising: means for reading Register Transfer Level (RTL) description circuit data; means for generating an equivalent circuit corresponding to the RTL description circuit data and extracting a plurality of arithmetic components included in the generated equivalent circuit; means for clustering some of the extracted arithmetic components as a single arithmetic component, wherein no storage element exists between said some of the extracted arithmetic components; means for reading a timing constraint on the RTL description circuit data; means for tracing an exception path of the RTL description circuit data when the timing constraint includes a timing exception; means for determining whether or not the timing exception is set for input pins of said some of the arithmetic components which are clustered as the single arithmetic component, based on the traced exception path of the RTL description circuit data; and means for separating a arithmetic component for which the timing exception is set, from said some of the arithmetic components which are clustered as the single arithmetic component.