1. A method for implementing logic in an arithmetic/logic unit, comprising: receiving two operands; computing a generate function result that is a logical AND or a logical NAND of the two operands; computing a propagate function result that is a logical OR or a logical NOR of the two operands; transmitting the generate function result to an execution macro of the arithmetic/logic unit that can compute the complement of the generate function result; transmitting the propagate function result to an execution macro of the arithmetic/logic unit that can compute the complement of the propagate function result; transmitting the generate function result and the propagate function result to an execution macro of the arithmetic/logic unit that can compute a logical complement and a logical NAND or a logical AND to produce a logical XOR of the two operands and a logical EQV of the two operands.