1. A microcontroller system comprising: a microcontroller having a plurality of cores, each of the plurality of cores having an interrupt controller, an operating frequency and voltage; and common peripherals electrically coupled to each of the plurality of cores by interrupt lines, the interrupt controller of each of the plurality of cores handling a common interrupt received from one of the common peripherals such that a first task signaled by the common interrupt is handled in parallel with a second task signaled by the common interrupt by having the first task running on a first one of the plurality of cores and the second task running on a second one of the plurality of cores wherein the operating frequency and voltage of the first one of the plurality of cores and the operating frequency and voltage of the second one of the plurality of cores are scaled down to reduce power consumption.