1. A restart and recovery circuit for a decoder that comprises translate (XLAT) programmable logic arrays (PLAs), a field extractor, and a microcode sequencing (MS) unit that includes microcode ROM including assist routines and control circuitry, said restart and recovery circuit comprising: a) an assist routine in the MS unit, said assist routine including microcode that issues assist micro-operations to assist the error-causing macroinstruction to completion; b) circuit means for executing microcode in said assist routine to fetch the error-causing macroinstruction; c) fetch means for fetching the error-causing macroinstruction; d) a field extractor means coupled to receive said error-causing macroinstruction, said field extractor means operable, and to provide macro-alias data from said error-causing instruction; and e) macro-alias registers for storing said macro-alias data.