1. An adder circuit comprising: a propagate and generate circuit stage to provide propagate and generate signals; a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals provided by the propagate and generate circuit stage; a conditional sum generator to provide conditional sums based on the propagate and generate signals, the conditional sum generator including ripple carry gates and logic gates; and a plurality of multiplexers to receive the carry signals and the conditional sums and each to provide an output based on the received signals.