1. A receiver, in a digital transmission system, comprising a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising: a set of co-processors including at least 3 clusters of programmable co-processors for executing the functions of a digital front-end block (DFE), a channel correction block (CHN) and a forward error correction block (FEC), respectively, a general purpose processor (DSP) for managing control, synchronization and configuration of the channel decoder, and a memory (SM) shared between the clusters and the general purpose processor.