1. A system for generating a mask pattern for a vector data processor having a mask register and a vector register in which, the value of the mask register is "1", a calculation is executed for the corresponding element of the vector register, and when the value of the mask register is "0", a calculation is not executed, in accordance with a calculational mask function, said system comprising: designation means for designating sequential "i" elements of "0" or "1" from a beginning element of the mask register and subsequent sequential "j" elements of "1" or "0"; and control means for rendering the "i" elements to be "0" or "1", the "j" elements to be "1" or "0", and the remaining elements to be all "0's" or all "1's", when "i" plus "j" is smaller than a vector length which is the object of the calculation of a vector data operand used in a vector instruction, a desired pattern of "0" or "1" being generted in the mask register.