1. A method in a simultaneous multi-threading (SMT) microprocessor that executes multiple threads concurrently during each clock cycle, said method comprising: assigning a clock cycle priority to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles, said clock cycle priority assignment being temporary and designed to change automatically after said expected number of clock cycles have been executed; assigning said clock cycle priority according to a standard selection definition during said standard selection state by selecting said first thread to be a primary thread and selecting said second thread to be a secondary thread for processing during said standard selection state; determining whether a condition exists that requires overriding said standard selection definition; in response to determining that said condition exists, executing an override state, during which said standard selection definition is overridden by selecting said second thread to be said primary thread and selecting said first thread to be said secondary thread for processing; forcing said override state to be executed for an override period of time; said override period of time equaling said expected number of clock cycles plus a forced number of clock cycles; and granting said forced number of clock cycles to said first thread in response to said first thread again becoming said primary thread.