1. A reconfigurable FIR filter comprising an field-programmable gate array (FPGA) configured with: a data memory to store consecutive samples of input data; a coefficient memory to store a set of filter coefficients; a partial product memory to store partial products from a plurality of data cycles; an output multiplexer configured to select output data from the partial product memory based on a filter order, wherein different outputs from the partial product memory are selected for different filter orders; a first adder to add data from a most delayed data location of the data memory to current input data; a second adder to generate the partial products for storage in the partial product memory; and a multiplier to multiply an output of the first adder with one of the filter coefficients, wherein the second adder is to add an output of the multiplier with a partial product of a previous data cycle to generate a partial product for a current data cycle for storage in a next storage location in the partial product memory, wherein the output multiplexer includes a MUX select input to select an output from the partial product memory based on the filter order, wherein the reconfigurable FIR filter is reconfigured by writing the filter coefficients to the coefficient memory, and wherein the filter order is changed by changing the output selection from the partial product memory.