1. A computing device for performing flexible code acceleration, the computing device comprising: a physical memory having stored therein a plurality of instructions; a processor to execute the plurality of instructions to establish an accelerator virtual device, an accelerator virtual device operating system driver, and a virtual machine, wherein: the virtual machine is to, using the accelerator virtual device operating system driver, (i) initialize the accelerator virtual device to facilitate the acceleration of a software code, (ii) reserve a portion of the physical memory as memory-mapped input/output for accessing the accelerator virtual device, (iii) determine whether to accelerate a software code, (iv) access an accelerator runtime library in response to a determination to accelerate the software code, and (v) allocate an accelerator virtual device context associated with a thread of the software code to be accelerated; and the accelerator virtual device is to (i) access a bytecode from the thread of the software code in response to allocation of the accelerator virtual device context, (ii) determine whether the bytecode of the software code to be accelerated is an operating system-dependent bytecode, wherein an operating system-dependent bytecode requires operating system support to execute, (iii) utilize, by an internal dynamic binary translation module, the reserved portion of the physical memory as a memory fault trap to intercept, read and write calls of bytecode to be accelerated through translation of the bytecode from one or more non-instruction set architecture codes into one or more instruction set architecture codes of the computing device, and (iv) perform hardware acceleration of the bytecode atomically, with no intermediate state associated with the bytecode visible to software executed by the processor, in response to a determination that the bytecode is not an operating system-dependent bytecode, wherein the bytecode does not require operating system support to execute, and in response to interception of the read and write calls with the memory fault trap; wherein the processor is to perform software acceleration of the bytecode in response to a determination that the bytecode is an operating system-dependent bytecode.