1. A computer implemented process for generating a time delay simulator that uses a characteristic of a logic node in an unmapped logic network to a delay time in mapped and optimized logic network in a specified target technology, said mapped and optimized logic network corresponding to said logic node in said unapped logic network, wherein the characteristic is represented by a value, said process comprising the steps of: (a) selecting a target technology having a library of standard gates; (b) selecting a mapping and optimization method; (c) selecting a representative logic function; (d) generating a multiplicity of sample unmapped logic having a selected range of values of said characteristic using said representative logic function; (e) mapping and optimizing each of said sample logic nodes for speed using said library of standard gates with said mapping and optimization method thereby producing a multiplicity of mapped and optimized sample logic networks; (f) determining delay time for each of said multiplicity of mapped and optimized sample logic networks thereby generating data including the delay time in said mapped and optimized sample logic network for each value of said characteristic chosen in step (d); and (g) using said data to generate a means for simulating a delay time associated with the mapped logic network corresponding to said logic node in said unmapped logic network, given the value of said characteristic of said logic node, wherein said means for simulating is the time delay simulator and does not require generation of a mapped and optimized logic network to simulate said delay time.