1. A method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, said chip voltage island including chip power and signal pads, and creating an equivalent circuit model of said chip voltage island; defining a package voltage island, said package voltage island including power and signal package pins, and creating an equivalent circuit model of said package voltage island; analyzing electrical attributes of a combination of said chip voltage island model and said package voltage island model; and modifying said package voltage island until said electrical attributes are acceptable.