1. A scalable, massively parallel computer system comprising: a plurality of processing nodes interconnected by independent networks, each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations, each of said processing nodes including a direct memory access (DMA) element operable for providing a plurality of functions for said processing node; and, a first of said multiple independent networks comprising an n-dimensional torus network including communication links interconnecting said nodes in a manner optimized for providing high-speed, low latency point-to-point and multicast packet communications among said nodes or sub-sets of nodes, said processing node DMA element providing a communications message passing interface enabling communication of messages among said nodes; a second of said multiple independent networks including a scalable collective network comprising nodal interconnections that facilitate simultaneous global operations among nodes or sub-sets of nodes of said network; and, partitioning means for dynamically configuring one or more combinations of independent processing networks according to needs of one or more algorithms, each independent network including a configurable sub-set of processing nodes interconnected by divisible portions of said first and second networks, each of said configured independent processing networks is utilized to enable simultaneous collaborative processing for optimizing algorithm processing performance, and, wherein each said DMA element at said nodes comprises: a processor interface for interfacing with the at least one processor, a DMA controller logic device, a memory interface for interfacing with a memory structure for storing information, a DMA network interface for interfacing with the network, one or more injection and reception byte counters, and injection and reception FIFO metadata associated with a injection FIFO and reception FIFO, respectively, wherein said DMA element supports message-passing operation as controlled from an application via an Injection FIFO Metadata describing multiple Injection FIFOs, where each Injection FIFO may contain an arbitrary number of message descriptors to process messages with a fixed processing overhead irrespective of the number of message descriptors comprising the Injection FIFO, said (DMA) element is operable for Direct Memory Access functions for point-to-point, multicast, and all-to-all communications amongst said nodes.