1. A memory device comprising: a memory cell array including a plurality of memory cells; a counting circuit configured to obtain a counting result by performing a counting operation on data read from the plurality of memory cells; and a control logic configured to perform a data restoring operation based on the counting result without involvement of a memory controller, wherein the control logic is configured to, generate a comparison result by comparing the counting result with a reference value to determine whether errors in the plurality of memory cells are correctable, perform a restoration algorithm for the data restoring operation based on the comparison result, output a ready/busy signal to the memory controller, and maintain the ready/busy signal in a busy state during the data restoring operation.