1. A computer architecture, comprising: a scheduling unit to schedule a group of instructions from a sequential program using inheritance vectors to identify dependencies between instructions; and a plurality of execution units to process the group of instructions, wherein the plurality of execution units access a plurality of register file segments that are physically segmented, but appear as a unified architecture resource with shared architecture state across the plurality of register file segments, wherein the same register numbers are replicated in each of the plurality of register file segments, and wherein each access to an architecture state in a specific register number is resolved to a particular single register file segment utilizing a group number and dynamically assigned hardware thread identifiers obtained from an updated instance of an inheritance vector, wherein the dynamically assigned hardware thread identifiers are assigned in response to a software instruction group and support concurrent execution of different parts of the sequential program.