1. A circuit arrangement, comprising: hardware logic configured to host a multithreaded rendering software pipeline using a plurality of parallel threads of execution, the multithreaded rendering software pipeline including a rasterization backend that generates a raster-based image, the plurality of parallel threads of execution including a plurality of raster threads that execute at least a portion of the rasterization backend, wherein each raster thread is allocated at least one region of an image space for the raster-based image; and control logic configured to dynamically reallocate the regions allocated to the plurality of raster threads based upon performance data collected from the plurality of raster threads.