1. A method of data processing in a data processing system including a processor core having an associated upper level cache having a lower access latency and a lower level victim cache having a higher access latency, said method comprising: filling the lower level victim cache with coherency granules evicted from the upper level cache, wherein at least some coherency granules held in the lower level cache are held simultaneously in the upper level cache; in response to a memory access request of the processor core that missed in the upper level cache and that specifies a non-modifying access to a target coherency granule, determining whether the memory access request hits or misses in a directory of the lower level victim cache; in response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state: the lower level victim cache providing the target coherency granule of the memory access request to the upper level cache; if the memory access request is of a first type, preserving the target coherency granule in the lower level victim cache and associating the target coherency granule in the lower level victim cache with a shared coherence state indicating the target coherency granule is held in both the upper level cache and the lower level victim cache; and invalidating the target coherency granule in the lower level victim cache if the memory access request is of a second type.