1. A method of sharing memory performed in a computer system having multiple processors and memory coupled to the processors, the method comprising: a) obtaining a storage request including a semaphore address at a processing cache, the processing cache having a dedicated arithmetic logic unit (ALU) associated therewith; b) setting a semaphore variable in the processing cache at the semaphore address; c) invoking an operating system trap-call such that i. if the storage request includes a wait-on-semaphore instruction, the dedicated ALU associated with the processing cache will return a result to one of the multiple processors that will require the operating system trap-call to wait on a processing queue, and ii. if the storage request includes a signal-on-semaphore instruction, the dedicated ALU associated with the processing cache will return a result to one of the multiple processors that will require the operating system trap-call to signal on a processing queue.