1. A data processing system comprising: a main memory for storing an address translation table; a central processing unit operatively connected to said main memory; a plurality of channels or sub-system adapters operatively connected to said main memory and said central processing unit, each of said plurality of channels or sub-system adapters including main memory accessing means for accessing said main memory and for providing a physical page address to the respective channel or sub-system adapter by utilizing said main memory and said central processing unit to translate a logical page address to the physical page address, each said main memory accessing means comprising: a register having areas for storing a copy of at least one entry within said address translation table in said main memory and a validity bit indicative of the validity of said copy, said copy including the physical page address; storage register means for storing the logical page address and an address in the page, said storage register means including a counter for indicating respective addresses in the page corresponding to said at least one entry within said address translation table by incrementing said address in the page; first means, operatively connected to said register and said counter, for accessing said main memory in accordance with a physical address comprising said copy, including the physical page address, and one of said respective addresses in the page; and second means, operatively connected to said central processing unit, for altering the state of said storage area containing said validity bit when said central processing unit has issued an instruction for updating said at least one entry within said address translation table or an instruction indicating alteration of said at least one entry, so that said validity bit is indicative of an invalid entry copy.