1. A microprocessor configured to process a repeat load string instruction, wherein the repeat load string instruction specifies a string of data bytes in memory to be loaded into an architectural register of the microprocessor, the microprocessor comprising: a memory subsystem, comprising a cache memory; and microcode, wherein the microprocessor is configured to invoke the microcode in response to encountering the repeat load string instruction, wherein the microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into the cache memory a series of cache lines implicated by the string of data bytes specified by the repeat load string instruction; wherein the memory subsystem is configured to guarantee within architectural limits that the cache line specified by each of the GPREFETCH instructions will be fetched into the cache memory.