1. A central processing unit, comprising: a register file having a plurality of read ports; a first execution unit having a first plurality of input ports; a second execution unit having a second plurality of input ports, wherein a first subset of the plurality of read ports is associated with the first plurality of input ports of the first execution unit and a second subset of the plurality of read ports is associated with the second plurality of input ports of the second execution unit; a first scheduler circuit to schedule instructions for the first execution unit; a second scheduler circuit to schedule instructions for the second execution unit; and multiplexers to selectively couple different arrangements of the plurality of read ports to the first plurality of input ports, wherein the multiplexers are to route at least one of the plurality of read ports in the second subset to one of the first plurality of input ports and the first scheduler circuit is to instruct the second scheduler circuit to delay the instructions scheduled for the second execution unit by inserting a bubble between the instructions scheduled for the second execution unit while the multiplexers are configured to route at least one of the plurality of read ports in the second subset to one of the first plurality of input ports.