1. A computer implemented method comprising computer-readable instructions stored on a non-transitory computer readable storage medium and executed on a computing device comprising a hardware processor and a memory for designing SoC by synchronizing a hierarchy of SMDPs, the method comprises: initializing a chip topology from an SoC specification or a database, wherein the step of initializing comprises extracting details regarding chip, chip skeleton, clock, Input outputs, partitions that are retrieved from the received SoC specification input and a chip database library; creating a plurality of domains and a plurality of subdomains artificial intelligence (AI) setup in form of Markov Decision Process (MDP), Semi Markov Decision Process (SMDP)s, Hierarchical Abstract Machines (HAM)s and MAX-Q to generate chip specific graph library, and wherein the artificial intelligence setup comprises a combination of an AI agent, an AI environment, and a task, wherein the AI setup is created using pre-defined exploration and exploitation algorithms, and reinforcement learning techniques; generating Q values for each domain using AI agent, wherein the AI agent is configured to interact with AI environment through task to extract Q values for each domain; associating the chip topology to a Markov Decision Process (MDP) with HAM constraints; branching the chip topology to a plurality of SMDPs or MDPs; activating the plurality of SMDPs or MDPS, and wherein the plurality of activated SMDPs or MDPs is terminated on achieving a preset Q-value or a preset objective; synchronizing the plurality of SMDPs or MDPs after termination; activating a plurality of subdomains at a same level, and wherein the plurality of activated subdomains is terminated on achieving a preset Q-value or a preset objective; synchronizing the plurality of subdomains after termination; initiating a physical verification of the plurality of SMDPs or MDPs; storing the extracted Q values of each domain and subdomain in a hierarchical SMDP structure in a form of SMDP Q table in a big data database for optimization for planning SoC; and acquiring optimal chip architecture for designing SoC, wherein the optimal chip architecture corresponds to a maximum Q value of a top level in the SMDP Q table.