1. A method performed by a computer for formally verifying the equivalence of an architecture description with an implementation description, the method comprising the steps of: reading, by the computer, an implementation description; reading, by the computer, an architecture description, wherein the architecture description takes a view of the processor in which the processor executes every instruction fully before the processor starts with the next instruction; demonstrating, by the computer, that during execution of a same program with same initial values an architecture sequence of data transfers described by the architecture description is mappable to an implementation sequence of data transfers implemented by the implementation description, such that the mapping is bijective and ensures that the temporal order of the architecture sequence of data transfers corresponds to the temporal order of the implementation sequence of data transfers; and outputting, by the computer, a result of the verification of the equivalence of the architecture description with the implementation description.