1. A processor comprising: a front end unit including an instruction fetch unit and a decode unit; an execution engine coupled to the front end unit; and a memory unit coupled to the execution engine and including a first cache, wherein the processor is to read a first portion of a plurality of portions of a data word from a first portion of the first cache and read a second portion of the plurality of portions from a second memory, wherein bits of the second portion are less critical than bits of the first portion, and the second memory is distinct from the first cache based on at least a physical attribute.