1. An apparatus, comprising: a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to: estimate data under-run at a host dependent upon a histogram of latency of data fetched from the plurality of memory devices; determine a prefetch depth based on the estimated data under-run; fetch data from at least one of the plurality of memory devices dependent upon the determined prefetch depth; send the fetched data to the host; and deactivate prefetching for a given memory device of the plurality of memory devices in response to a determination that the given memory device includes a Double Data Rate (DDR) memory.