1. A method of providing accelerated post-silicon testing for a silicon hardware, comprising: computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint; performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint; manufacturing the silicon hardware using the instrumented logic design; computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.