1. A system, comprising: a bus; a processor circuit coupled to the bus; a memory circuit; a multi-channel memory controller coupled between the bus and the memory circuit; and a first coprocessor coupled to the processor circuit, the first coprocessor further being coupled to the multi-channel memory controller via a first interface that bypasses the processor circuit and the bus, wherein the memory controller comprises an address generator circuit that calculates a series of sequential addresses for the memory circuit in response to data received from the coprocessor specifying a sequential access pattern, and that calculates a series of non-sequential addresses for the memory circuit in response to data received from the coprocessor specifying a non-sequential access pattern.