1. A programmable logic device (PLD), comprising: multiple programmable logic blocks that perform operations on a bit-by-bit basis in a PLD domain, such that the bits are unordered; an engine operable to process data, the engine performing operations on data ordered in vectors; and an interface coupled between a programmable logic block and the engine, the interface operable to convert at least a portion of the unordered bits from the PLD domain to a vector and providing the vector to the engine.