1. A semiconductor memory device, comprising: a main cell array having main memory cells for storing data; a redundant cell array having redundant memory cells for storing data in place of defective main memory cells in the main cell array; a first selection circuit coupled to the main cell array, for selecting the main memory cells in response to external address input; a second selection circuit coupled to the redundant cell array and programmable with at least one redundancy repair address, for selecting the redundant memory cells when the external address input matches the redundancy repair address; a readout circuit coupled to the second selection circuit, for reading the redundancy repair address from the second selection circuit; a spare cell array having spare memory cells for storing the redundancy repair address; a third selection circuit coupled to the spare cell array, for selecting the spare memory cells; and a data output circuit coupled to the main cell array, the redundant cell array, and the spare cell array, for output of the data stored in the selected main memory cells and the selected redundant memory cells, and for output of test data responsive to the redundancy repair address read by the readout circuit and the redundancy repair address stored in the spare cell array.