1. A memory device comprising: a memory array having stored data and a serial output; a cache register, coupled to the memory array, for receiving the stored data; an address counter that generates a serial address signal that sequentially counts through the addresses comprising the stored data; an address multiplexer having a first input coupled to an external address bus and a second input coupled to the serial address signal, the address multiplexer selecting either the first or second inputs in response to a state of a select signal; and a data multiplexer coupled to input data from the cache register and an input address from the address multiplexer, the data multiplexer capable of accepting either randomly accessed stored data or sequentially accessed stored data from the cache register in response to the input address.