1. A method for verifying timing of a circuit using a single tool, the circuit having a first portion with a gate-level description and a second portion with a transistor-level description, comprising: accepting both the gate-level and transistor-level descriptions; and using the single tool to perform timing analysis of the circuit using both the gate-level and transistor-level descriptions, wherein the step of using the single tool includes decomposing circuit structures into transistor-level descriptions to determine timing information associated with the transistor-level descriptions.