1. An apparatus comprising: an integrated circuit comprising: memory cells arranged in a plurality of portions including a first portion and a second portion; volatile memory configured to store defective address data corresponding to the first portion of the memory cells that are deemed defective post-packaging; a decoder configured to select the second portion of the memory cells instead of the first portion of the memory cells when a received address matches the defective address data stored in the volatile memory; non-volatile memory; and a mapping logic circuit, the mapping logic circuit configured to program replacement address data associated with the first portion of the memory cells to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.