1. A method of diagnosing a failure in a circuit in a complex semiconductor device comprising the steps of: selecting a semiconductor device having logic circuits formed of latches: testing the logic circuits in the device and locating a failing logic circuit in said device; testing the logic circuits in the device and locating a failing logic circuit in said device: selecting a functional test procedure; selecting a structural design and test technique; combining said functional test procedure and said structural design and test technique to dynamically create a new test pattern based on the functional located failure; and diagnosing the failing circuit to determine the location of and type of error in said failing circuit.