1. A method for executing a plurality of different voting-logic functions in a data processor, said method comprising: accessing a plurality of program instructions, said plurality of instructions respectively containing specifications of a corresponding plurality of said data operands; accessing said plurality of data operands according to said specifications; entering successive ones of said plurality of data operands into a first a plurality of cascaded registers; thereafter testing for the presence of a fixed value in the operand in said first register; if said tested operand has a predetermined fixed value, pushing said successive operands from each successive register into the next succeeding register in said plurality of cascaded registers; accessing a further program instruction, said further instruction containing a specification of a selectable one of said plurality of registers; and gating to a common output the contents of said selectable one register, so that said output contains one of a plurality of different voting-logic functions of said operands, depending upon which of said plurality of registers is gated thereto in response to said further instruction.