1. An apparatus comprising: a cache memory; a processor coupled with the cache memory, the processor comprising: logic to cause the processor to enter a first mode in response to a first instruction, wherein the first mode is to be indicated by a first mode bit, and wherein the first mode corresponds to a different security level than a normal mode of the processor, and wherein in the first mode a first program is to control access to a secure portion of the cache memory using a translation look-aside buffer; a flash interface to communicate with a flash memory; a wireless interface to communicate with a wireless device; a universal serial bus (USB) interface to communicate with a USB device; and a keypad interface to communicate with a keypad.