1. A network processor having a multithreaded pipeline, comprising: an upper pipeline, having an input coupled to receive a signal indicative of an instruction queue depth corresponding to a plurality of threads, the upper pipeline determining an instruction fetch sequence for the plurality of threads based on the instruction queue depth signal; and a lower pipeline, comprising a first input to receive decoded instructions and a second input to receive a thread conditions signal, the lower pipeline determining a thread execution sequence based on the thread conditions signal, the thread conditions signal indicative of an execution stall corresponding to the plurality of threads.