1. A microprocessor core, comprising: a plurality of inputs, configured to indicate whether a corresponding plurality of independently occurring events has occurred, wherein said plurality of inputs are non-memory address inputs; and a yield instruction, included in an instruction set of an architecture of the microprocessor core, comprising an output operand and an input operand, said input operand for specifying one or more of said plurality of independently occurring events; wherein said yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a thread until at least one of said independently occurring events specified by said input operand has occurred, wherein said thread contains said yield instruction; wherein said yield instruction further instructs the microprocessor core to return a first value in said output operand indicating which of said independently occurring events occurred to cause the microprocessor core to resume issuing said instructions of said thread.