1. An information processing apparatus comprising: an instruction supplying section that supplies a plurality of instructions as a single instruction group; an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel; an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency; and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.