1. A processor for compressing an instruction sequence, wherein the instruction sequence includes a plurality of instructions, each instruction comprising a first number of bits in respective bit positions, the processor operating in accordance with: commands to perform at least one identification process on the instruction sequence in order to identify relationships between the bits in said bit positions among the instructions of the instruction sequence, wherein the identification process identifies pairs of bit positions in the instructions of the instruction sequence which contain opposite bit values from each other; and commands to generate a compressed instruction sequence comprising one compressed instruction corresponding to each instruction of the instruction sequence based on the identification process.