1. A method for on-chip loopback in multicore processors, the method comprising: identifying one or more processes on a multicore processor, wherein the processes are adapted to communicate with each other via an off-chip network; and generating a simulated network loopback at a processor hardware layer to deliver messages between the one or more processes without using the off-chip network, wherein generating the simulated loopback comprises: generating a core-process-to-IP-address map; identifying a destination core for a message based on the core-process-to-IP-address map; identifying data associated with the message to be delivered to the identified destination core; and processing the identified data back into one or more on-chip flits to be delivered to the identified destination core.