1. A processor comprising a hardware-based thread context unit configured to forward instructions of a thread for execution by the processor, the thread context unit comprising: a load reference counter configured to maintain a counter value of a difference between a number of data requests of one or more previous instructions of the thread and a number of data returns in response to the data requests of the previous instructions of the thread; and a context controller configured to evaluate the load reference counter when a current instruction of the thread includes a data dependency indicator indicating the current instruction requires data returned by one of the previous instructions of the thread and further configured to refrain from submitting the current instruction of the thread for execution by the processor when the counter value is nonzero.