1. A microprocessor configured to execute programs in a pipeline architecture, comprising: a plurality of units configured to execute tasks; a task register of a plurality of task registers, the task register configured to hold register information that is used while the plurality of units executes the tasks; a task identification information register configured to hold task identification information, which identifies the task executed by each of the units, in a data format that is used to identify a corresponding unit; a task identification information specifying device configured to specify the task identification information that is held in the task identification information register for the units, if an access request to the register information is received from the units; a register table configured to hold a register information identifier and the task identification information, wherein the register information identifier is used to identify the register information held in the task register; and a controller configured to: control access to the register information that is held in the task register, based on the task identification information specified by the task identification information specifying device; prohibit the units corresponding to task identification information other than previously set task identification information from having access to the task register, according to the register information held in the task register; and prohibit the task register that holds register information from accessing other register information, which is identified by the register information identifier corresponding to the task identification information in the register table.