1. In an embedded-DRAM (dynamic random access memory) processor incorporating wide data paths to memory, a method of intelligent caching comprising the steps of: segmenting the architecture into first and second portions; executing instructions by said first portion which manipulate only register operands; and executing instructions by said second portion which perform row-oriented load/store operations as well as individual register-to-register move operations; wherein: said first portion of said architecture sees a subset of the total available registers as its set of architectural registers; said first portion of said architecture comprises one or more functional units which execute a first program comprising instructions using register operands; and said second portion of said architecture executes a second program tightly coupled to said first program, said second program comprising parallel row-oriented load/store/mask commands, register-to-register move commands, and architectural register set switch commands to insure that data accessed by said first program is available when it is needed.