1. A method of updating an existing netlist to reflect a design change, the method comprising: providing a register transfer level (RTL) design incorporating the design change to a synthesis tool; providing the existing netlist to the synthesis tool; setting the existing netlist to a read-only condition to prevent a change to the existing netlist; synthesizing the design and the read-only existing netlist with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space, the optimization being constrained by the read-only existing netlist; and generating by the synthesis tool the existing read-only netlist and a portion of a new netlist reflecting the design change.