1. A signal processor for discriminating recording data comprising: a magnetic recording medium; a magnetic head for reading a signal from said medium; an equalizer for processing said read signal; a detector circuit for detecting zero-cross points of the equalized waveform of said read signal; a phase locked loop means (PLL) utilizing said zero-cross timing as an input for generating a clock signal at a rate twice the baud rate of said read signal; a frequency divider for dividing an output frequency of said PLL means by two to generate two baud rate clock signals having different phases from each other; and a circuit for selecting one of said clock signals by using the waveform of the received signal and for connecting said selected clock signal to discriminator and decoder circuits, wherein said discriminator circuit discriminates digital data from the equalized waveform of said read signal utilizing said selected clock signal as a discriminating clock signal.