1. A computer comprising: a general purpose register file comprising at least two general purpose registers; a condition code register file distinct from said general purpose register file, having a plurality of addressable condition code registers, each condition code register for representing a condition code value as a small number of bits summarizing the execution or result of a previously-executed instruction; a processor element configured to execute instructions, including condition-setting instructions that each produce a condition code value for storage in one of said condition code registers; a branch execution unit configured to execute conditional branch instructions that each determine a target instruction for execution based on analysis of a condition code value from one of said condition code registers; and a condition code access unit configured to act in response to condition-selecting instructions, at least one of said condition-selecting instructions being one of either said condition-setting instructions or said conditional branch instructions, said condition-selecting instructions for selecting from said condition code register file a condition code register for at least one of: storing into said selected condition code register a condition code value produced by one of said condition-setting instructions, and fetching from said selected condition code register a condition code value for analysis by one of said conditional branch instructions; said selecting being by direct addressing on a condition code address field of the condition-selecting instruction.