1. A microprocessor providing an extendable instruction set architecture, the microprocessor comprising: a memory for storing at least one virtual instruction that includes an index and at least one parameter; a virtual instruction expansion store including at least one instruction template and at least one parameter selector; and substitution logic that forms a sequence of at least one expanded instruction, wherein bits of an opcode of the at least one expanded instruction are formed from the at least one parameter in a manner specified by the at least one parameter selector.