1. An N-bit processor where the number N is a natural number, comprising: (a) an interpretation unit which interprets instructions intended for said N-bit processor, and instructions intended for n Mn-bit processors satisfying N=M1+. .. +Mn where the numbers M1 to Mn are natural numbers and the number n is a natural number equal to or greater than 2; (b) an instruction control unit for said N-bit processor; when an instruction, interpreted by said interpretation unit, is intended for said N-bit processor, said N-bit instruction control unit controlling said N-bit processor to decode and execute said N-bit processor instruction; and (c) n instruction control units for said n Mn-bit processors; when n instructions, interpreted by said interpretation unit, are intended for said n Mn-bit processors, said N-bit processor being divided into n Mn-bit processors and said n Mn-bit instruction control units controlling said n Mn-bit processors to decode and execute in parallel said n Mn-bit processor instructions, wherein: said N-bit processor includes a memory which stores instructions intended for said N-bit processor, instructions intended for said n Mn-bit processors, and specific instructions; and said interpretation unit receives said three types of instructions from said memory and decodes a specific instruction included in said received instructions to determine whether instructions following said specific instruction are intended for said N-bit processor or for said n Mn-bit processors.