1. A processor device comprising: physical layer logic to: enter a loopback state of a state machine; generate, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS); transmit the loopback pattern to another processor device over a physical connection, wherein an instance of the loopback pattern is to also be generated by the other processor device, and the loopback pattern is transmitted according to a first setting of transmitter parameters of the processor device; adjust the first setting of transmitter parameters of the processor device based on metrics generated based on a comparison by the other processor device of the loopback pattern received by the other processor and the instance of the loopback pattern generated by the other processor device, wherein adjusting the first setting of transmitter parameters results in a second setting of transmitter parameters of the processor device; transmit another instance of the loopback pattern to the other processor device according to the second setting of transmitter parameters of the processor device.