1. Data processing apparatus comprising: a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception type; in which: the exception cache is configured to cache information only in respect of instances in which the exception instruction is a branch instruction; the cached information comprises an address dependent upon a branch target of that branch instruction; the instruction fetching unit is configured to initiate fetching of an instruction at the branch target address in response to receipt of the cached information from the exception cache; and the exception cache is configured, in an instance in which the exception cache has provided a cached branch target address to the processor, to inhibit an operation of the processor in response to a branch instruction to delete any instructions currently being fetched by the pipelined instruction fetching unit.