1. An apparatus comprising a delay unit, the delay unit comprising: a plurality of delay elements, wherein each delay element of the plurality of delay elements comprises: a pair of NAND gates; and an And-Or-Invert (AOI) gate coupled to the pair of NAND gates; and a register comprising a plurality of cells, wherein each of the plurality of cells has an output coupled to an input of a corresponding delay element of the plurality of delay elements.