1. A system comprising: one or more simultaneous multithreading (SMT) cores, one or more of the SMT cores perform out-of-order instruction execution for a plurality of threads; a memory hierarchy comprising a system memory and a plurality of cache levels communicatively coupled to one or more of the SMT cores; and an accelerator communicatively coupled to one or more of the cores and the memory subsystem, the accelerator comprising: a memory management circuit to attempt a virtual-to-physical address translation by querying a translation lookaside buffer (TLB) containing a mapping of virtual-to-physical addresses, the memory management circuit to access a page table from the memory subsystem to perform the translation if the query to the TLB fails to locate a translation for a particular virtual address; a memory interface circuit to interconnect the accelerator to the memory subsystem, the memory interface circuit to access the memory subsystem using the address translation provided by the memory management unit; and execution circuitry to execute instructions and process data retrieved from the memory subsystem.