1. A semiconductor memory device in which electrical rewriting of data is possible, comprising: a plurality of memory cells arranged in row and column directions; a word line provided corresponding to each row of memory cells; a complementary bit line pair provided corresponding to each column of memory cells; a sense amplifier including a complementary input node pair for amplifying potential difference between the input node pair; a transfer gate provided between said bit line pair and said input node pair of said sense amplifier; sensing means for sensing that a complementary output of said sense amplifier has been established; and a tristate buffer controlled by an output of said sensing means for outputting an output of said sense amplifier to a data bus.