1. An array processor system comprising: (a) a control processor; (b) an array processor having a plurality of elemental processors configured in an M.times.N array of M elements by N elements, with the operation of said array processor being directed by said control processor; and (c) a replicated data transfer plane operatively associated with said control processor and said array processor for respectively exchanging data thereinbetween or between said elemental processors within said array processor, said replicated data transfer plane including: (i) a plurality of pseudo-modules corresponding to the M.times.N array of elemental processors, said pseudo-modules having means for transferring data to and from said elemental processors; and (ii) pseudo-module control logic having means for transferring data to and from said control processor, means for transferring data to and from all of said pseudo-modules, and means for allowing said control processor to select and direct all transfers of data through said replicated data transfer plane.