1. POR circuit (POR 3, POR 4 ) comprising means (POR 1 ) for delivering a first reset signal (RSTH) when the supply voltage (Vcc) of the POR circuit is between a first low threshold and a first high threshold (V 2 H), characterized in that it comprises, in addition: means (POR 2 ) for delivering a second reset signal (RSTL) when the supply voltage is between a second low threshold and a second high threshold (V 2 L) which is lower than the first high threshold (V 2 H), at least one electrically erasable and programmable non-volatile memory cell (CELL 1, CELL 2, CELL 3, CELL A, CELL B ) that can be put into an erased state or into a programmed state, and means (SCT, MUX, A 4, INV 5 ) for delivering the first (RSTH) or the second (RSTL) reset signal to the output of the POR circuit, depending on whether the memory cell is in the erased state or in the programmed state.