1. A fused multiply-adder comprising: a Booth encoder for encoding a first operand; a fraction multiplier for multiplying said encoded first operand by a second operand to produce partial products, and for reducing said partial products to a set of sum and carry vectors; a carry corrector for generating a carry correction factor for correcting a carry bit stemmed from a Booth encoding of said first operand that is less than full-precision of said fused multiply-adder; and an adder circuit for adding said sum and carry vectors and said carry correction factors to a third operand to produce a final result.