1. An error detection circuit implemented on a logic device, comprising: a multiplexer that takes as input an expected value and configuration data stored on the logic device; and check circuitry coupled to an output of the multiplexer that includes: an XOR tree to implement a polynomial checksum computation, a signature register coupled to the XOR tree, and a logic gate coupled to the signature register, wherein the logic gate takes, as a bit-wise input, content of the signature register.