1. An apparatus comprising: a processing pipeline to process instructions, comprising fetch circuitry to fetch instructions from a plurality of threads for processing by the processing pipeline, and execution circuitry to execute the fetched instructions; execution hint instruction handling circuitry, responsive to the fetch circuitry fetching an execution hint instruction for a first thread in said plurality, to treat the execution hint instruction, at least in a presence of a suspension condition, as a predicted branch instruction with a predicted behaviour, and to cause the fetch circuitry to suspend fetching of instructions for the first thread; the execution circuitry being arranged to execute the predicted branch instruction with a behaviour different to said predicted behaviour in order to trigger a misprediction condition, and the fetch circuitry being responsive to the misprediction condition to resume fetching of instructions for the first thread.