1. A memory controller circuit comprising: a first component of the memory controller circuit in configurable logic, the first component providing functionality associated with a first memory type; and a second component of the memory controller circuit implemented in hard logic, the second component providing functionality associated with a plurality of memory types including the first memory type, wherein the second component includes a transaction buffer pool configured to store transactions received from a memory based on the first memory type, and the second component provides capacity information associated with the transaction buffer pool to the first component to manage transactions between the first component implemented in the configurable logic and the second component implemented in the hard logic.