1. A method for interrupt processing comprising: detecting an exceptional condition resulting from a failed execution of an instruction in one or more stages of an instruction pipeline in a processor; checking an instruction cache for the presence of an instruction at a starting address of an interrupt handler in response to the detected exceptional condition and prior to the processor accepting an interrupt in which the instruction at the starting address of the interrupt handler is fetched in response to the detected exceptional condition; and prefetching the instruction at the starting address of the interrupt handler from storage other than the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.