1. A digital signal processor comprising: a control block configured to issue flow instructions and flow data based on a stored program; and a compute array including plurality of serially connected compute engines configured such that (i) each of the issued flow instructions executes in a first compute engine and flows, in a single direction, to be executed in each successive compute engine of the plurality of serially connected compute engines at successive times, and (ii) the flow data recirculates from a last compute engine in the plurality of serially connected compute engines directly back to the first compute engine.