1. A multi-port burst dynamic random access memory (DRAM) system comprising: a memory array; a plurality of write ports for writing data to said memory array; a plurality of read ports for reading data from said memory array; and a plurality of first-in-first-out (FIFO) output buffers coupled to respective ones of said plurality of read ports, wherein said FIFO output buffers are disposed between said memory array and said read ports to temporarily store data read from said memory array, and each of said read ports is de-coupled by its respective FIFO output buffer from said memory array and/or a plurality of first-in-first-out (FIFO) input buffers coupled to respective ones of said write ports, wherein said FIFO input buffers are disposed between said memory array and said write ports to temporarily store data prior to writing to said memory array, and each of said write ports is de-coupled by its respective FIFO input buffer from said memory array.