1. The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having two capacitor states, the process including the steps of applying to at least one selected cell of said memory array a first potential (a) having a polarity to drive a portion of the substrate of said cell into depletion, (b) having a sufficient magnitude to effect avalanche breakdown in said depletion portion of the substrate of said cell, and (c) having sufficient magnitude and duration to change the state of said cell and simultaneously applying to unselected cells of said memory array at least a second potential having a magnitude and duration insufficient to change a state of said unselected cells.