1. A method, comprising: processing a plurality of logical partitions on a shared processor for the duration of a respective dispatch cycle; issuing, by a hypervisor, at a predefined time prior to completion of each dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a respective cache line address buffer location in a virtual processor; responsive to each lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by each logical partition to the respective cache line address buffer location in the virtual processor; determining an average amount of time required to write the sets of cache line addresses; and setting the average amount of time as the predefined time to issue the lightweight HDEC during subsequent processing of each logical partition.