1. A weakly-ordered processing system, comprising: a plurality of memory devices; a plurality of processors, each of the processors configured to generate memory access requests to one or more of the memory devices, each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request; and a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.