1. A memory device comprising: a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack, the system element including: a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.