1. A flash interface error injector for end-of-life testing of a flash-based array, the error injector comprising: a bit flip probability logic, implemented by one or more bit flip probability processors, configured to identify one or more bits to be flipped; and a plurality of error injection logic blocks, implemented by one or more error injection processors, configured to inject errors in the one or more bits identified by the bit flip probability logic, each of the plurality of error injection logic blocks corresponding with a respective flash channel of the flash-based array.