1. An integrated circuit comprising: a memory having a plurality of memory blocks, wherein each memory block has a set of bits, and wherein each bit has a value; a secure memory controller that inverts and reverts the value of each bit of each memory block of the memory such that the amount of time each bit of the memory contains a digital logic one value is substantially equal to the amount of time the bit contains a digital logic zero value, wherein the secure memory controller uses an inversion flag bit to track whether a memory block contains bits with inverted values, and wherein the inversion flag bit is a bit of the memory block; and a tamper detect circuit that causes the memory to be erased if a tamper detect condition is detected.