1. A level shifter latch circuit comprising: a latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals; a latch storage element coupled to said latch input stage; said latch storage element including a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply; said latch storage element including a level shifting device providing level shifting from the first supply level to the second voltage supply level; said latch storage element including feedback devices receiving the predefined clock signals to gate feedback to said latch input stage responsive to data being written to said latch input stage.