1. A signal conditioning circuit having terminals to receive clock generated control signals, comprising: an amplifier having an input terminal and an output terminal; an input impedor having a non-zero reactance, a first terminal coupled to the amplifier input terminal, and a second terminal; an input circuit coupled to the input impedor second terminal and having first means responsive to a first clock generated control signal for switching the input impedor second terminal between first and second signal source input terminals; a high impedance detection circuit including a detection impedor having a first terminal coupled to the input impedor second terminal and a second terminal; and a feedback circuit including a feedback impedor having a first terminal and a second terminal coupled across the amplifier input and output terminals, respectively.