1. A solid state memory component, comprising: a plurality of bit lines; a source line; a plurality of non-functional memory pillars, each non-functional memory pillar being electrically isolated from one or both of the plurality of bit lines and the source line; a plurality of functional memory pillars, each functional memory pillar being electrically coupled to one of the plurality of bit lines and one of the source lines; wherein memory cells are adjacent to each of the functional memory pillars and the non-functional memory pillars; wherein each memory cell comprises: a tunnel dielectric adjacent to the functional or non-functional memory pillar; a charge storage structure adjacent to the tunnel dielectric; a blocking dielectric adjacent to the charge-storage structure; and a control gate adjacent to the blocking dielectric; and wherein the plurality of functional memory pillars is located in a memory array portion of the memory component and at least some of the plurality of non-functional memory pillars are located in a periphery portion of the solid state memory component.