1. A computing device comprising: an instruction cache comprising primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute said primary execution unit instructions from said instruction cache; an auxiliary execution unit configured to receive and execute only said auxiliary execution unit instructions from said instruction cache in a manner independent from and asynchronous to said primary execution unit; and completion circuitry configured to coordinate completion of said primary execution unit instructions by said primary execution unit and said auxiliary execution unit instructions according to said sequential order.