1. A processing core, comprising: a first source register including a plurality of first operands; a plurality of second operands; a bitwise inverter coupled to at least one of the first plurality of operands and the second plurality of operands; a destination register including a plurality of results; a plurality of arithmetic processors respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.