1. A method of modeling yield for semiconductor products, the method comprising: determining expected faults for each of a plurality of library elements by running a critical area analysis on each of said library elements; assessing, from said critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products, and thereafter updating said expected number of faults for each library element in response to observed yield; establishing a database, said database including the die size and expected faults for each of said library elements; estimating integrated circuit product die size; selecting library elements to be used to create the integrated circuit die; obtaining fault and size data for each of the selected library elements; summing the adjusted estimated faults for each of said library elements; and calculating estimated yield.