1. A processing system comprising: a plurality of processor cores; a plurality of private caches, each private cache associated with a corresponding processor core of the plurality of processor cores and comprising a corresponding set of cachelines, the plurality of private caches configured to store coherency states for the cachelines of the corresponding sets of cachelines in accordance with a first set of coherency states; and a shared cache shared by the plurality of processor cores, the shared cache comprising: a second set of cachelines; and a shadow tag memory comprising a plurality of entries, each entry storing state and address information for a corresponding cacheline of the set of cachelines of one of the private caches, the shadow tag memory configured to store coherency states for the cachelines of the sets of cachelines of the plurality of private caches in accordance with a second set of coherency states, the second set of coherency states comprising a superset of the first set of coherency states, wherein the state information comprises coherency states for at least a subset of the cachelines of the plurality of private caches in accordance with the second set of coherency states.