1. A method for determining capacitance gradients of a Very Large Integrated Circuit (VLSI) chip layout, comprising: i. decomposing one or more layout shapes into elementary patterns; ii. translating physical parameter variations into variations on parameters of elementary patterns into which the layout shapes are decomposed; iii. computing said capacitance gradients of said elementary patterns; iv. combining said capacitance gradients into capacitance gradients of said one or more layout shapes of said chip layout; and v. transferring capacitance gradient values to a netlist providing electrical-level descriptions of said chip layout.