1. A semiconductor memory device comprising: a memory cell array comprising memory cells in a matrix arrangement; a data inverter configured to invert data in the memory cells and to write the inverted data in the memory cells; an address counter configured to increment or decrement an internal address when the data inverter writes the inverted data; a decoder configured to select a first memory cell comprising data to be inverted by the data inverter based on the internal address designated by the address counter; and an address comparator configured to determine whether the data from a memory cell of an external address is inverted and written based on a first result of comparison of an external address and the internal address in a readout cycle, and to determine whether the data written into a memory cell of the external address is inverted based on a second result of comparison of the external address and the internal address in a writing cycle.