1. A method of configuring a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby; the method comprising the steps of: a) programming the host processor with instructions in a high level programming language; b) instantiating elements from a library of elements compatible with the high level programming language; c) providing a compiler for the high level programming language to the host processor for generating executable code in response to the programmed instructions and the instantiated library elements, the executable code including compiled placement and routing information; and d) configuring the FPGA from the host processor in response to the executable code.