1. A method for prefetching data in a microprocessor having a cache hierarchy, the cache hierarchy comprising a cache reload buffer (CRB), an L1 cache, and an L2 cache, the method comprising the steps of: prefetching a stream of data into the L2 cache by using an asynchronous form of a data cache block touch (DCBT) instruction; prefetching the data from the L2 cache directly to the CRB without storing the data in the L1 cache by using a synchronous form of a DCBT instruction; and retrieving the data from the CRB for processing.