1. A method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising: receiving a 3D-IC die description which describes the 3D-IC die, wherein the 3D-IC die comprises two or more vertically stacked 2D-IC dies which are coupled through at least one through-silicon via (TSV); transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description and wherein the set of 2D-IC die descriptions includes a modified TSV; for each 2D-IC die description in the set of 2D-IC die descriptions, performing, by computer, an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.