1. A dynamic random access memory (DRAM) cell, comprising: a pair of bit lines; a storage capacitor; an n-type field-effect transistor (NFET) access transistor selected by a first word line that couples the storage capacitor to one of the pair of bit lines; and a p-type field-effect transistor (PFET) access transistor selected by a second word line that couples the storage capacitor to another of the pair of bit lines; wherein only one bit line from the pair of bit lines is used to perform a read operation on data in the storage capacitor and both of the bit lines from the pair of bit lines are used to perform a data-dependent write-back operation to the storage capacitor.