1. A processing unit, comprising: a processor core; an input/output (I/O) communication adapter coupled to said processor core; and a cache system coupled to said processor core and to said I/O communication adapter, said cache system including a cache array, a cache directory and a cache controller, wherein said cache controller snoops I/O communication by said I/O communication adapter and, responsive to snooping said I/O communication adapter performing an I/O data write of outgoing data in an exclusive state, invalidates corresponding data stored within said cache array.