1. A processor, comprising: a pipeline comprising multiple pipeline stages including an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, including a first processor thread and a second processor thread; a set of registers corresponding to each of the plurality of processor threads, including the first processor thread and the second processor thread, the registers being located before and after each pipeline stage in the multiple pipeline stages of the pipeline of the processor; wherein each pipeline stage includes a first selector in communication with input registers for that pipeline stage, and a second selector in communication with output registers for that pipeline stage, the input registers and the output registers being from the set of registers; and a programmable controller operable to perform a context switch among the plurality of processor threads, including storing a state of a currently executing processor thread in a corresponding set of registers and loading a state of another processor thread from a corresponding set of registers to allow for processing of the another processor thread, by controlling switching of the first and second selectors such that data associated with the first processor thread pass through the corresponding first set of registers, and the multiple pipeline stages, during a time that the first processor thread is being processed, and data associated with the second processor thread pass through the corresponding second set of registers, and the multiple pipeline stages, during a time that the second processor thread is being processed, wherein the controller includes a plurality of hardware thread allocation counters corresponding to the plurality of processor threads to effect the context switch by the programmable controller within the processor, each thread allocation counter containing a first value representing a respective processor time allocation that controls a period of processor time that is to be dedicated to a respective processor thread, wherein the respective processor time allocation is fixed for and determined prior to the period of processor time, wherein the respective processor thread fully and exclusively uses the respective processor time allocation, wherein the programmable controller is configured to dynamically change subsequent processor time allocations to the plurality of processor threads by changing one or more of the first values of the thread allocation counters to one or more second values based on a received input, the received input defining one or more portions of processor time to be allocated to each of the plurality of processor threads.