1. An apparatus, comprising: an array of programmable resistance memory cells, said memory cells being programmable by application of a current; and feedback control circuitry configured to control the current supplied to a memory cell of said array, said feedback control circuitry including circuitry configured to (i) control a first peak current supplied to said memory cell; (ii) rapidly increase the current supplied to said memory cell up to a second peak current and then rapidly decrease current supplied to said memory cell to program said memory cell to a high resistance state; (iii) rapidly increase the current supplied to said memory cell up to a third peak current and then gradually decrease the current supplied to said memory cell to program said memory cell to a low resistance state; (iv) rapidly increase the current supplied to said memory cell up to a fourth peak current and then decrease the current supplied to said memory cell at an intermediate rate to program said memory cell to an intermediate resistance state; and (v) quench the current supplied to said memory cell when a predetermined level is reached.