1. A logic array block for a programmable logic device comprising: a first dedicated input; a first programmable function block in a first level to implement logic functions; a second programmable function block in a second level to implement logic functions, said second programmable function block programmably coupled to said dedicated input and said first programmable function block; and a local interconnect region programmably coupling an output of said first programmable function block or an output of said second programmable function block to a selected output of said logic array block, without passing through a global interconnect region of said programmable logic device.