1. A cache controller, comprising: a first port being configured to receive an address of a content from a processor, a type of the content being one of instruction and data; a second port being configured to receive an information bit corresponding to the content from the processor, the information bit indicating the type of the content; and at least one unified cache, comprising a plurality of cache lines, each of the cache lines comprising a content field and corresponding to an information field, and the content and the information bit being respectively stored in the content field of one of the cache lines and the corresponding information field according to the information bit and the address.