1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising: a metric generator that is operable to: receive first I, Q (In-phase, Quadrature) values corresponding to a first symbol of the LDPC coded signal and is operable to generate a first plurality of bit metrics there from; receive second I, Q values corresponding to a second symbol of the LDPC coded signal and is operable to generate a second plurality of bit metrics there from; a metric memory that is operable to: store the first plurality of bit metrics and the second plurality of bit metrics; support dual port memory management thereby outputting the first plurality of bit metrics while receiving the second plurality of bit metrics from the metric generator; support dual port memory management thereby outputting the second plurality of bit metrics while receiving a third plurality of bit metrics from the metric generator; a plurality of bit/check processors that is operable to: successively receive the first plurality of bit metrics, the second plurality of bit metrics, and the third plurality of bit metrics; perform both bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes and check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes; a message passing memory that is operable to: store the plurality of edge messages with respect to the plurality of bit nodes after undergoing bit node processing within the plurality of bit/check processors; store the plurality of edge messages with respect to the plurality of check nodes after undergoing check node processing within the plurality of bit/check processors; a barrel shifter that is operable to: shift the plurality of edge messages with respect to the plurality of bit nodes that is accessed from the memory passing memory; provide the shifted plurality of edge messages with respect to the plurality of bit nodes to the plurality of bit/check processors for subsequent check node processing; shift the plurality of edge messages with respect to the plurality of check nodes that is accessed from the memory passing memory; and provide the shifted plurality of edge messages with respect to the plurality of check nodes to the plurality of bit/check processors for subsequent bit node processing.