1. An apparatus for loading a very long instruction word (VLIW) in a processor, the apparatus comprising: a VLIW memory (VIM) configured with addressable VLIW locations, each VLIW location comprising N slots; and a VLIW control unit configured to receive a load VLIW (LV) instruction and a first set of N instructions that make up a VLIW from a program memory, the LV instruction having a count value N and VLIW address infoiination, and the VLIW control unit configured to load each instruction of the first set of N instructions in an instruction specified slot at a VIM address according to the received VLIW address information to create the VLIW comprising the N instructions.