1. A memory access controlling system for reducing access competition among a plurality of processors to a main memory and a cache memory, the memory access controlling system comprising: the plurality of processors for processing a task including a data read-ahead thread for performing a data read-ahead process and a task including parallel execution thread for performing an execution process in parallel with the data read-ahead process; the cache memory, a number of the cache memory is one, the cache memory being commonly-accessed by the plurality of processors; and a data read-ahead controller for controlling, when each processor accesses the cache memory, an interval between data read-ahead processes in the data read-ahead thread adapted to a data flow which varies corresponding to an input value of a parallel process in the parallel execution thread.