1. A method of performing clock network synthesis upon receipt of a non-transitory computer readable circuit design, the method comprising: by using a computing device, building a graph representation for a clock network; determining an optimal clock network balancing solution for the clock network by applying linear programming to the graph, the applying linear programming comprising generating a set of constraints for the graph and determining a proper insertion delay for each edge of the graph by solving for a minimal skew based on the set of constraints, the set of constraints comprising a plurality of Edge Relation, Endpoint Constraint, Skew Limit, Maximum Latency Constraint and Maximum Skew Constraint; and implementing the optimal clock network balancing solution, wherein the implemented optimal clock network balancing solution is used to create an integrated circuit.