1. In a computer system capable of processing data signals, said system including process or means for processing said data, memory means for storing at least instructions for use by said processor means, memory input bus means for conducting memory input signals from said processor means to said memory means, memory output bus means for conducting memory output signals from said memory means to said processor means, and I/O means connected to said processor means for communicating system input signals into said processor means from outside of said system and for communicating system output signals to outside of said system from said processor means, said memory means comprising: memory input means for receiving said memory input signals from said input bus means; a plurality of memory modules, each module of said plurality of memory modules connected from said memory input means and capable of performing memory related operations concurrently with and independently of performance by all other modules of said memory related operations, and said each module of said plurality of memory modules capable of completing each of said memory related operations within a uniform predetermined time interval; memory control means connected from said input means and deriving control signals from first certain said memory input signals for providing memory control signals to said memory modules, said memory control means providing certain said memory control signals to said modules for selecting single said modules from said plurality of memory modules and for initiating said memory related operations of said selected single modules in the same sequence as said memory input signals initiating each of said memory related operations appear on said memory input bus means; and output multiplexor means for selectively transferring output signals from said plurality of memory modules to said output bus means, said output multiplexor means responsive to said memory related operations of said modules for transferring said output signals from said plurality of memory modules resulting from said memory related operations to said output bus means in said same sequence as said memory input signals initiating each of said memory related operations appear on said memory input bus means, so that each of said output signals appears on said memory output bus means a said uniform predetermined time interval after a corresponding one of said memory input signals appears n said input bus means.