1. In a single instruction stream/multiple data stream processor having a control processor for exercising control of said single instruction stream/multiple data stream processor in accordance with said single instruction stream, having a plurality of arithmetic units for performing arithmetic operations upon a plurality of data streams, and having a corresponding like plurality of local memories for buffering said plurality of data streams to and from said plurality of arithmetic units, an apparatus for transferring said plurality of data streams to said like plurality of local memories neither under centralized control arising from any centralized resource controller, nor under distributed control arising from said plurality of arithmetic units, but rather under distributed control autonomous of, and non-conflicting with, the function of said plurality of arithmetic units, said apparatus for the distributed control of data transfers within said single instruction stream/multiple data stream processor comprising: a main bus means for according the transfer of data thereon; a plurality of arithmetic unit means each for processing data each connected to, and reading and writing data contained in, an associated one of a plurality of local memory means; a plurality of said local memory means each for storing data of use, at a time, to an associated one of said plurality of arithmetic unit means, each responsively coupled for reading and writing of said data to said associated one of said plurality of arithmetic unit means, and each responsively coupled also for reading and writing of said data to an associated one of a plurality of bus interface units means; and a plurality of bus interface unit means each coupled to said main bus for transferring data thereon, and also coupled to an associated one of said plurality of local memory means for the reading and writing of data, and for each controlling and effectuating the transferring, through said each one of said pluralty of bus interface unit means and via said main bus means and through another one of said plurality of bus interference unit means, of data read and written of the one of said plurality of local memory means associated with said each one of said plurality of bus interface unit means, and of data written and read of the another one of said plurality of local memory means associated with said another one of said plurality of bus interface unit means WHEREIN said controlling and effectuating transferring, via said main bus means and through said each open and said another one of said plurality of bus interface unit means, is autonomously controlled in said each one of said plurality of bus interface unit means which commands said another one of said plurality of bus interface unit means to participate in said controlling and effectuating transferring wherein autonomously controlled does not mean devoid of any outside initiation but does mean that the conduct of said controlling and effectuating transferring without the involvement of any agency outside said each one of said plurality of bus interface unit means; a main memory means for storing data of use, at times, to plural one of said plurality of arithmetic unit means; and a further one bus interface unit means; identical to each of said plurality of bus interface unit means, associated with said main memory means and responsively coupled to said main bus means for transferring data thereon, and responsively coupled to said associated main memory means for the reading and writing of data stored therein said main memory means IN ORDER THAT said further one bus interface unit means will transfer, through said further one bus interface unit means and via said main bus means and through another one of said plurality of bus interface unit means, data between said memory means and one of said plurality of local memory means; wherein a first difference between said main memory means and each of said plurality of local memory means is that said memory means is storing data of use, at times, to plural ones of said plurality of arithmetic unit means whereas each said local memory means is storing data of use, at at a time, to one of said plurality of arithmetic unit means; wherein a second difference between said main memory means and each of said plurality of local memory mean is that said memory means is not responsively coupled to any one of said plurality of arithmetic unit means; wherein said transfer of said data, of use at times to plural ones of said plurality of arithmetic unit means, between said main memory means and said ones of said plurality of local memory means, which said ones of said plurality of local memory means are responsively coupled for reading and writing to associated ones of said plurality of arithmetic unit means, is thusly a way that said data at times of use to plural said ones of said plurality of arithmetic unit means should be emplaced in locations, mainly said ones of said plurality of local memory means, wherein it may be read and written for said use, wherein that said each one of said plurality of bus interface unit means is controlling and effectuating said transferring autonomously thusly requires that said transferring is without the involvement or control of any of said plurality of arithmetic unit means, or of said control processor, or of any other agency without said bus interface unit means whatsoever; wherein because said controlling and effectuating said transferring of data resides in each of said plurality of bus interface unit means, then data transfer control within said apparatus may be said to be distributed.