1. A method of converting a field-programmable gate array (FPGA) implementation of a digital logic design, into a mask-programmable logic cell (MPLC) implementation of said digital logic design, the method comprising the steps of: (a) selecting a FPGA device and a FPGA library for use in achieving said FPGA implementation, said FPGA device including a package containing a substrate carrying a plurality of a programmable input and output interface blocks (IOBs) each having input and output ports operably associated with a plurality of pins on said package and programmable logic circuitry contained therein, a plurality of programmable configurable logic blocks(CLBs) each having input and output ports and programmable logic circuitry contained therein, a plurality of programmable interconnect switches for selectively interconnecting the input and output ports of said CLBs and the input and output ports of said IOBs so to form a first signal network for routing signals within said FPGA device with first set of signal delays, (b) generating a FPGA netlist for said FPGA implementation, said hierarchical FPGA netlist containing a CLB description for each said CLB utilized in said FPGA implementation, an IOB description for each said IOB utilized in said FPGA implementation, and port connectivity specifications specifying the interconnections to be established between the input and output ports of said utilized CLBs and said utilized IOBs, effectuated by said plurality of programmable interconnect switches, in order to form said first signal network within said FPGA device; (c) selecting a MPLC device and a MPLC library for use in achieving said MPLC implementation, said MPLC device including a package containing a substrate having at least one interconnect level and an array of a logic cells which can be selectively configured at said at least one interconnect level to form a plurality of Soft-CLBs and a plurality of Soft-IOBs on said MPLC substrate, wherein each said Soft-CLB and each said Soft-IOB has input and output ports interconnectable at said at least one interconnect level by applying a metalization layer of computable geometry to said MPGA substrate, in order to form a second signal network for routing signals within said MPLC device with a second set of signal delays said second signal network physically corresponding to said first signal network; (d) generating a MPLC netlist for said MPLC implementation, said MPLC netlist containing hierarchical information regarding said MPLC implementation including a Soft-CLB description for each said Soft-CLB to be formed on said MPLC substrate, a Soft-CLB connectivity description specifying the connectivity of the input and output ports of said Soft-CLBs specified in said MPLC netlist, a Soft-IOB description for each said Soft-IOB to be formed on said MPLC substrate, and a Soft-IOB connectivity description specifying the connectivity of the input and output ports of said Soft-IOBs specified in said MPLC netlist; (e) using said modified MPLC netlist and said MPLC library to generate a geometrical database containing geometrical information specifying the physical placement of each said Soft-CLB and each said Soft-IOB on said MPLC substrate, and geometrical information specifying the signal paths on said MPLC substrate interconnecting the input and output ports of said CLBs and IOBs in accordance with said Soft-CLB connectivity description and said Soft-IOB connectivity description, such that the relative signal delays presented during said FPGA implementation are substantially maintained in said MPLC implementation, thereby assuring functional equivalence between said FPGA and MPLC implementations.