1. A method for designing an integrated circuit (IC) chip, comprising: receiving data from a pre-layout design process for the IC chip; routing a plurality of interconnecting wires to connect various devices of the IC chip; extracting various circuit parameters; and simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip, wherein the extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations; wherein establishing the statistical ITP file further includes: measuring metal layer interconnection parasitic parameters and single layer coupling capacitances of a plurality of prefabricated measuring structures; obtaining N number of correlated single layer coupling capacitance variables based on the single coupling capacitances, where N is an integer greater than 2; and converting the N number of correlated single layer coupling capacitance variables into M number of independent and uncorrelated variables, where M is an integer less than N, using a Principal Component Analysis (PCA) method.