1. An electronic device comprising: a parallel processing device comprising: a plurality of processing elements each configured to execute instructions; a memory subsystem comprising a plurality of memory slices including a first memory slice associated with one of the plurality of processing elements, wherein the first memory slice comprises a plurality of random access memory (RAM) tiles each having individual read and write ports; and an interconnect system configured to couple the plurality of processing elements and the memory subsystem, wherein the interconnect system includes: a local interconnect configured to couple the first memory slice and the one of the plurality of processing elements, and a global interconnect configured to couple the first memory slice and the remaining of the plurality of processing elements; a processor, in communication with the parallel processing device, configured to run a module stored in memory that is configured to: receive a flow graph associated with a data processing process, wherein the flow graph comprises a plurality of nodes and a plurality of edges connecting two or more of the plurality of nodes, wherein each node identifies an operation and each edge identifies a relationship between the connected nodes; and assign a first node of the plurality of nodes to a first processing element of the parallel processing device and a second node of the plurality of nodes to a second processing element of the parallel processing device, thereby parallelizing operations associated with the first node and the second node.