1. A processor comprising: a plurality of cores to execute a plurality of threads; an integrated graphics unit; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores, wherein the plurality of counters comprises a first counter to express an average number of physical active cores, a second counter to express an average time that any physical core was active, a third counter to express an average time that the integrated graphics unit was active, and a fourth counter to express an average time that any one of the physical cores was active in parallel with the integrated graphics unit; dependency analysis logic circuit to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and control logic circuit to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.