1. A hard/soft cooperative verifying simulator for performing cooperative verification of hardware and software, comprising: a plurality of time keepers provided for every plurality of threads, the threads constituting simulation models corresponding to the hardware and software, each of the time keepers provided with a first variable for holding a simulation time, a second variable for holding a summation time, a break request queue for storing break requests which each consist of a pair of a break time and a break method corresponding thereto, and a processing function, and each of the time keepers controlling a simulation time of each of the threads to which said time keepers respectively correspond, responsive to the simulation time, the summation time, the break time, the break method and the processing function; and a simulator body which advances each managed system time by a given required time in response to a request issued from each of the time keepers and controls context switching between the threads being operated in parallel on a computer processor.