1. A hierarchical memory device, comprising: at least one input port; and a plurality of output ports, the hierarchical memory device being configured to be simultaneously connectable in both a daisy-chain hierarchy and a hierarchical tree structure with other hierarchical memory devices, the hierarchical memory device being configured to switch traffic between the at least one input port and one of the plurality of output ports to reduce a round-trip latency to a lowest layer of the hierarchical tree structure.