1. A method of executing a plurality of threads within a single programmable processor, the method comprising: receiving an instruction stream for each one of the plurality of threads at an execution unit; executing instructions from each instruction stream received at the execution unit in a multistage pipeline within the execution unit such that, at any given time, the multistage pipeline includes instructions from different ones of the instruction streams in different stages of the multistage pipeline, the instructions including a single instruction that operates on a plurality of data elements in partitioned fields of at least one register to produce a catenated result, the at least one register having a register width and each of the data elements having an elemental width smaller than the register width.