1. A system for testing an integrated circuit comprising: at least one central processing unit; at least one volatile memory area and at least one non-volatile memory area; an interface; and a test device coupled with the integrated circuit, the central processing unit accessing the non-volatile memory area in a normal operation mode, and wherein in a test operation mode the test device is configured to stop program execution, write data in the volatile memory area via the interface, and start program execution, the central processing unit accessing the volatile memory area in the test operation mode.