1. A processor comprising: a plurality of processor cores; a plurality of design blocks coupled to the plurality of processor cores, each design block including a set of registers coupled to gated power, the set of registers to store active context of the design block; and logic circuitry coupled to the plurality of cores and the plurality of design blocks, to monitor access to the set of registers of each design block to detect a change in the active context, and to store an indication of one or more of the design blocks that includes the change in the active context.