1. A multiple defect diagnosis method, comprising: receiving a gate-level netlist, a plurality of test patterns and a plurality of test failures of a chip; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test failures and the plurality of test patterns; utilizing a processor to calculate similarities between the plurality of seed nets, to merge the plurality of seed nets accordingly to generate a single seed-net tree; and determining at least one suspected seed net from the plurality of seed nets according to the single seed-net tree, so as to narrow down a defect region of the chip to the at least one determined suspected seed net.