1. A logic circuit comprising: first n-input LUT circuitry; second n-input LUT circuitry; and a plurality of muxes interposed between an x and an x+1 mux level of the first and second n-input LUT circuits, each mux of the plurality of interposed muxes including: a first input coupled to an output of an x+1 level mux of the first n-input LUT circuitry; a second input coupled to an output of an x+1 level mux of the second n-input LUT circuitry; and an output coupled to an input of an x level mux of the first or second n-input LUT circuitry.