1. A parallel computer system comprising: a plurality of information processing devices, each of the plurality of information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the plurality of information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.