1. An apparatus in a pipeline microprocessor for providing a speculative address operand associated with a result of an arithmetic operation, the arithmetic operation being prescribed by a preceding micro instruction, the apparatus comprising: speculative operand calculation logic, configured to perform the arithmetic operation to generate the speculative address operand prior to when execute logic executes the preceding micro instruction to generate the result; and an update forwarding cache, coupled to said speculative operand calculation logic, configured to temporarily store the speculative address operand, wherein an address-dependent micro instruction can retrieve the speculative address operand, thereby permitting said address-dependent micro instruction to proceed without incurring delay.