1. Apparatus for processing data comprising: processing circuitry configured to perform data processing operations in response to program instructions; instruction decoder circuitry coupled to said processing circuitry and responsive to said program instructions to generate control signals for controlling said processing circuitry to perform said data processing operations; wherein said instruction decoder is responsive to a preload instruction, said preload instruction specifying a memory address location to be subject to a preload operation for preparing for a subsequent memory access to said memory address, to compare said memory address with a null value and: (i) if said memory address does not match said null value then to generate control signals for controlling said processing circuitry to perform said preload operation; and (ii) if said memory address does match said null value then not to generate said control signals for controlling said processing circuitry to perform said preload operation.