1. A method for sharing and re-using a single voltage parameterized statistical timing model corresponding to a macro during timing analysis of an integrated circuit (IC) chip design provided with at least one voltage domain and at least one instance of the macro, the method comprising: a) using a computer, computing timings of said macro employing said macro single voltage parameterized statistical timing model; b) obtaining information of voltage domain for macro instantiation; c) comparing said voltage domain information of said macro instantiation with a voltage domain information of said single voltage parameterized statistical timing model to detect a voltage domain information mismatch; d) generating a self-correction transformation upon discovery of said voltage domain information mismatch that dynamically updates said single voltage parameterized statistical timing model to correspond to said voltage domain of said macro instantiation; e) dynamically updating results of said macro's said computed timings based on said dynamically updated statistical timing model; and f) using said updated timing results, performing said timing analysis of said IC chip design.