1. Apparatus for testing a complex integrated circuit device having a very substantially greater number of internally interconnected logic elements than the number of input and output terminals of said device, thus rendering the internal elements inaccessible for discrete testing theoeof, comprising; (a) a plurality of pseudo-random pattern generators, one for each input terminal, each of said generators being operative to produce a uniquely different sequence of pseudo-random bit patterns, (b) means for applying the succession of bits from each of said generators to a different one of said input terminals in parallel as test input stimuli thereto. (c) signature register means operative responsive to all of the signals produced on said output terminals responsive to a succession of input stimuli to derive a signature which is a predetermined function of all of said output responses, and (d) and comparing means for comparing the thus-derived test signature with a signature of a known good device subjected to the same test stimuli.