1. An array of vertically stacked tiers of non-volatile cross point memory cells, comprising: a plurality of horizontally oriented word lines within individual tiers of memory cells; a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells; individual of the memory cells comprising multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones of the horizontally oriented word lines and local vertical bit line extensions comprising opposing conductive electrodes of individual memory cells where such cross; and a plurality of bit line select circuits individually electrically and physically connected to individual of the local vertical bit line extensions and configured to supply a voltage potential to an individual of the global horizontal bit lines.