1. A processor, comprising: a cache having a plurality of cache levels including a level 1 (L1) cache; a plurality of address generation units (AGUs); a plurality of arithmetic logic units (ALUs); a plurality of floating point (FP) units; instruction fetch logic to fetch one or more instructions; instruction decode logic to decode the one or more instructions; out-of-order logic to perform out-of-order execution of the one or more instructions; a register file including a set of 128-bit packed data registers to store packed single-precision floating point (SPFP) data elements and packed integer data elements; register renaming logic to rename logical registers to physical storage locations within the register file; and a plurality of execution units to execute: a first compare instruction to compare a first plurality of packed unsigned integer data elements stored in a first packed data register with a second plurality of packed unsigned integer data elements stored in a second packed data register, and to store a plurality of first result data elements in a third packed data register, wherein the plurality of first result data elements are expanded mask data elements, each of a first multi-bit size, to represent results of the comparison between the first packed unsigned integer data elements and the second packed unsigned integer data elements, each of the plurality of first result data elements to indicate whether the corresponding first packed unsigned integer data elements and the second packed unsigned integer data elements are equal, a second compare instruction to compare a first plurality of packed signed integer data elements stored in a fourth packed data register with a second plurality of packed signed integer data elements stored in a fifth packed data register, and to store a plurality of second result data elements in a sixth packed data register, wherein the plurality of second result data elements are expanded mask data elements, each of a second multi-bit size, to represent results of the comparison between the first packed signed integer data elements and the second packed signed integer data elements, and a third compare instruction to compare a first plurality of packed single precision floating point (SPFP) data elements stored in a seventh packed data register with a second plurality of packed SPFP data elements stored in an eighth packed data register, and to store a plurality of third result data elements in a ninth packed data register to represent results of the comparison between the first packed SPFP data elements and the second packed SPFP data elements, each of the third result data elements stored in the ninth packed data register to indicate whether the corresponding first packed SPFP data elements and the second packed SPFP data elements are equal.