1. A processor, comprising: an instruction fetch unit to provide an instruction address; an instruction cache to produce an instruction tag and instruction cache content corresponding to the instruction address; a boundary byte predictor to receive the instruction tag and generate a prediction vector including a bit corresponding to each byte in a group of instruction cache content bytes; and an instruction decoder including boundary byte logic to determine an instruction boundary in the instruction cache content, wherein the boundary byte logic forms an initial prediction of a boundary byte based on the prediction vector.