1. A processor comprising: a plurality of logical processors; a first logical processor of the plurality, the first logical processor to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory, wherein the memory access synchronization instruction is selected from a read-modify-write instruction, a compare-and-swap instruction, a test-and-set instruction, and a store-conditional instruction of a load-link/store-conditional pair of instructions; and memory access synchronization relaxation logic to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode, wherein the memory access synchronization relaxation logic comprises logic to convert the memory access synchronization instruction to an instruction selected from a store and a write.