1. A process of designing a base integrated circuit platform having ASIC and FPGA modules to perform memory programmable functions and non-memory programmable functions, comprising steps of: a) preparing a verified hardware description of a circuit to be embodied in the platform; b) grouping the memory programmable functions for assignment to FPGA modules; c) selecting a base platform design containing ASIC and FPGA modules adequate to execute the plurality of functions; d) synthesizing the non-memory programmable functions to ASIC modules and the memory programmable functions to FPGA modules; and e) defining placement, signal routing and boundary timing closure.