1. A method of data processing in a data processing system capable of concurrently executing multiple hardware threads of execution, said method comprising: an intermediate address translation unit in a processing unit translating an effective address for a memory access into an intermediate address; accessing cache memory utilizing the intermediate address; in response to a miss in cache memory, translating the intermediate address into a real address with a real address translation unit that performs address translation for multiple hardware threads of execution; and accessing a system memory with the real address.