1. A semiconductor integrated circuit comprising a PLA operable on a periodic cycle, the PLA having an input register connected to a source of first data, an AND plane connected to the input register for receiving the first data from the input register, an OR plane connected to the AND plane for receiving second data from the AND plane, and output register, a multistage logic network connected to the OR plane and to another part of the circuit for receiving third data both from the OR plane and from the other part of the circuit, for producing fourth data and for delivering the fourth data to the output register, means for feeding back at least some of fourth data from the output register to the input register in time for being received by the AND plane during the next succeeding cycle, the OR plane and the logic network being connected to a single control timing means which simultaneously precharges the OR plane and the logic network during a predetermined portion of each said cycle.