1. An apparatus, comprising: multiple rows of binary operators, each of said binary operators having two message inputs, with said multiple rows of binary operators interconnected according to a parity check matrix; and a control circuit configured for sequential scheduling of message passing and combining to update check-nodes and variable-nodes when decoding codeword data blocks received by said apparatus; said control circuit adapted for performing said message passing and combining according to said sequential scheduling in a zigzag pattern over said multiple rows of binary operators in which said messages for variable-nodes are processed in a first direction for even iterations, and said variable-nodes are processed in a second direction for odd iterations.