1. An integrated circuit device comprising: a memory array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region and separated therefrom by a gate dielectric; and wherein the memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the gate; and operating characteristics adjustment circuitry, coupled to the memory cell array, to responsively adjust one or more operating or response characteristics of one or more predetermined memory cells and thereby enhance the uniformity of operation or response of the predetermined memory cells of the memory array relative to the plurality of memory cells of the memory array.