1. An apparatus for providing an instruction to a processor core in a multi-core microprocessor, the apparatus comprising: a match register storing an opcode that identifies an instruction to be replaced; an instruction fetch logic device receiving an incoming instruction to be run by the processor core, identifying an opcode of the incoming instruction, and storing the identified opcode of the incoming instruction in an instruction register; a swap register storing in a first field a first instruction and in a second field a second instruction, wherein one of the first instruction and the second instruction replaces the identified instruction; a comparator determining whether the opcode stored in the instruction register and the opcode stored in the match register are same; and a multiplexer replacing the incoming instruction with one of the first and second instructions stored in the swap register in response to determining that the opcode stored in the instruction register and the opcode stored in the match register are same; wherein in order to replace the incoming instruction with one of the first and second instructions stored in the swap register, the comparator sets predecode bits in the incoming instruction in response to determining that the opcode stored in the instruction register and the opcode stored in the match register are same, wherein the predecode bits are set in a first pattern when the first instruction stored in the swap register is to replace the incoming instruction, wherein the predecode bits are set in a second pattern, different from the first pattern, when the second instruction stored in the swap register is to replace the incoming instruction, wherein the multiplexer chooses the first instruction stored in the swap register if the predecode bits are set to the first pattern, wherein the multiplexer chooses the second instruction stored in the swap register if the predecode bits are set to the second pattern, and wherein the multiplexer provides the chosen one of the first and second instructions to a further processing device in the processor core.