1. An integrated structure layout of functional blocks and interconnections for an integrated circuit chip, comprising: a. data dependency comparator blocks arranged in rows and columns, said arrangement defining layout regions between adjacent ones of said data dependency comparator blocks in said rows, wherein each data dependency comparator block has i. a first set of input lines for receiving source operand address signals for multiple instructions, and ii. a second set of input lines for receiving destination operand address signals for said multiple instructions and wherein said data dependency comparator blocks locate data dependencies between the multiple instructions and output dependency information; b. tag assignment logic blocks coupled to said data dependency comparator blocks to receive said dependency information, wherein said tag assignment logic blocks are positioned in one or more of said layout regions so as to be integrated with said data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of said rows, wherein each of said tag assignment logic blocks has i. a first set of input lines for receiving source operand address signals from a corresponding one of said multiple instruction, ii. a second set of input lines for receiving destination operand address signals associated with said corresponding one of said multiple instructions, and iii. output lines located in said orthogonal channel for forwarding tag information out of said layout regions, said tag information is generated by said tag assignment logic blocks to address the source and destination operands and execution results during execution of the multiple instructions; and c. register file port multiplexer blocks coupled to said tag assignment logic block output lines adjacent to said orthogonal channel to receive said tag information and to pass said tag information to address ports of a register file.