1. A method to process an instruction to assign a thread to a particular core in a multi-core processor, wherein the multi-core processor includes a first core, a second core, a first memory controller, and a second memory controller, the method comprising: determining first miss data that relates to a first number of times the first memory controller fetches from a memory in response to cache misses experienced by the first core; determining second miss data that relates to a second number of times the first memory controller fetches from the memory in response to cache misses experienced by the second core; determining third miss data that relates to a third number of times the second memory controller fetches from the memory in response to cache misses experienced by the first core; determining fourth miss data that relates to a fourth number of times the second memory controller fetches from the memory in response to cache misses experienced by the second core; and processing the instruction to assign the thread to the first core, wherein the instruction to assign the thread is based on the first, second, third, and fourth miss data.