1. An apparatus for receiving data from a synchronous random access memory, comprising: a data input for receiving a stream of data from the synchronous random access memory; a data clock input for receiving a data clock signal from the synchronous random access memory for clocking the stream of data; a first memory register, that is clocked by the data clock signal, for receiving data from the stream of data; a second memory register, that is clocked by the data clock signal, for receiving data from the stream of data; a first system register for receiving data from the first memory register, the first system register being clocked by a system clock signal, which is slower than the data clock signal; a second system register, that is clocked by the system clock signal, for receiving data from the second memory register; and a controller for coordinating actions of the first and second memory registers as well as the first and second system registers so that data is loaded into the second memory register by the data clock signal while data is being loaded into the first system register by the system clock signal and, during alternate cycles, so that data is loaded into the first memory register by the data clock signal while data is being loaded into the second system register by the system clock signal.