1. A pulse domain 1 to 2N demultiplexer comprising: i. a pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of said counters being responsive to leading edges of the pulses in said incoming pulse train and the other one of said counters being responsive to trailing edges of the pulses in said incoming pulse train; ii. control logic responsive to the states through which said pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of said pulse domain 1 to 2N demultiplexer.