1. A processor, comprising: a plurality of processor cores to execute multiple threads, each of the plurality of processor cores having an instruction cache and data cache; a memory bridge to couple the plurality of processor cores to a memory external to the plurality of processor cores; a packet distribution engine (PDE) to receive a plurality of packets from an input and to provide the plurality of packets to respective threads of the multiple threads; a first ring-based interconnect to couple the PDE to the instruction caches of the plurality of processor cores and to provide a first data pathway from a respective processor core to each of the other processor cores via their corresponding instruction caches without going through the memory, wherein the PDE is external to the plurality of processor cores; and a second ring-based interconnect to provide a second data pathway from the respective processor core to each of the other processor cores via their corresponding data caches without going through the memory.