1. A modified single-instruction multiple-data processor comprising: a first multiply-accumulator unit and, associated therewith, a first data memory and a first coefficient memory; a second multiply-accumulator unit and, associated therewith, a second data memory and a second coefficient memory; and a program memory providing a base address; wherein each multiply-accumulator unit receives as an input at least one coefficient stored in the associated coefficient memory at a memory address corresponding to the sum of the base address and a data sample stored in the associated data memory.