1. A memory repair system, comprising: an integrated circuit configured to receive at least a test mode select signal, a test clock signal, and a programming signal, comprising: a memory array including redundant memory; redundant circuit elements coupled to programmable elements and configured to enable programming of the programmable elements responsive to the programming signal being asserted; and a test access port controller configured to generate at least one internal repair command responsive to the test mode select signal and the test clock signal, the at least one internal repair command causing programming of programmable elements to re-route an address for at least one memory address to redundant memory.