1. A data processor comprising: a central processing unit which executes an instruction; a plurality of circuit modules used by the central processing unit; a first controller which sends a request for interruption to the central processing unit in response to a generated event signal; a second controller which outputs a start control signal to each said circuit module in response to the generated event signal; a plurality of signal wires for transferring the event signal and the start control signal; a first bus connected to the central processing unit; and a second bus connected to the first controller, wherein the circuit modules are connected to the first bus or the second bus, wherein the second controller is connected to the circuit modules via the signal wires different from the first bus and second bus, and wherein the second controller generates the start control signal according to a correspondence between the event signal and the start control signal rewritably defined in a memory circuit.