1. A processor, comprising: instruction fetch circuitry to fetch an MFENCE instruction; instruction decoder circuitry to decode the MFENCE instruction; memory ordering unit circuitry to: prevent load instructions and store instructions that follow the MFENCE instruction in program order from being dispatched until load instructions and store instructions previous to the MFENCE instruction in program order have been performed, and, for multiple memory types, prevent load instructions that follow the MFENCE instruction in program order from being dispatched until store instructions previous to the MFENCE instruction in program order have been performed.