1. A processor comprising: a plurality of processing cores; a ring interconnect coupled to the plurality of processing cores; and a first logic, in one of the plurality of processing cores, to assign a processing core of the plurality of processing cores as a boot strap processor (BSP), wherein the assignment is to be formatted into a packet and transmitted on the ring interconnect and the BSP is a positionally last processing core of the plurality of processing cores on the ring interconnect that is active and detected by the first logic.