1. A back-side trap non-volatile memory cell, comprising: a first and second source/drain regions coupled by a channel region; a top gate-stack, containing an access gate insulator layer formed over the channel region and an access gate formed over the access gate insulator layer; and a bottom gate-stack, the bottom gate-stack comprising, a back-side gate, a charge blocking layer formed over the back-side gate, a trapping layer formed over the charge blocking layer, and an asymmetric band-gap tunnel insulator layer containing one or more sub-layers formed over the trapping layer and beneath the channel region, wherein the one or more sub-layers comprise layers of increasing conduction band offset.