1. A binary encoding circuit ( 1, 2 ) for converting a plurality of binary input signals, including at least a first (R 0 ) and a second (R 1 ) input signal, into an output code made up of a plurality of output signals, including at least one first (Digit- 0 ) and one second (Digit- 1 ) binary output signal, said circuit being provided with at least two terminals to render available a signal of a high logic level (Vdd) and a signal of a low logic level (GR), characterized in that it also comprises: at least one first selection circuit (SC- 1 ) comprising a first (L- 1 ) and a second (L- 2 ) output line, each capable of being selectively connected to said terminals (Vdd, GR) on the basis of the logic level of the first input signal (R 0 ) to receive the high or low level logic signal, at least one second selection circuit (SC- 2 ) comprising a third (L- 3 ) and a fourth (L- 4 ) output line, said second circuit permitting said third (L- 3 ) and fourth (L- 4 ) output line to be selectively connected to at least one of said first (L- 1 ) and second (L- 2 ) output line on the basis of the logic level of the second binary signal (R 1 ) to receive said high or low level signal, said first (Digit- 0 ) and second (Digit- 1 ) binary output signal being obtainable by means of signals available on the third (L- 3 ) and fourth (L- 4 ) output line.