1. A pipeline accelerator, comprising: a communication bus; a plurality of clock signal lines operable to carrv at least a first clock signal and a second clock signal, the first and second clock signals being unsynchronized with one another; and a plurality of pipeline units each coupled to the communication bus and each comprising a respective hardwired-pipeline circuit, including a first hardwired-pipeline circuit that is coupled to receive and is operable synchronously with the first clock signal and at least one other hardwired-pipeline circuit that is coupled to receive and is operable synchronously with the second clock signal.