1. A processor having a set of machine language instructions for executing a sequence of processor instructions without interruption comprising: a plurality of general-purpose registers; an arithmetic logic unit; switching means for interconnecting said general-purpose registers and said arithmetic logic unit; a lock register; and a control unit for activating said switching means to coordinate execution of said machine language instructions, said control unit being in an interrupt-disable condition which does not service interrupts when said lock register contains a locked value, and in an interrupt-enable condition which does service interrupts when said lock register contains an unlocked value, and wherein each of said machine language instructions belongs to one of three sets, a first set of instructions setting the lock register to a locked value interrupt-disable condition to ensure indivisible execution of a second subset of instructions and of a third subset of instructions, said first subset generating a trap if said lock register contained a locked value when execution of said first set began, whereby an error condition is detected for attempting to set tile interrupt-disable condition when it had already been set, said second set of instructions limiting the duration of said interrupt-disable condition by changing the lock register in a predetermined way when it contains a locked value, and leaving the lock register unchanged when it contains an unlocked value, and said third set of instructions terminating said interrupt-disable condition by setting the lock register to an unlocked value, and wherein a subset of the third set of instructions is used only during the interrupt-disable condition to generate a trap if said lock register did not contain a locked value when said third set began, whereby an early loss of said interrupt-enable condition may be detected.