1. A microcomputer system including an improved program execution system comprising: a higher layer program memory having a plurality of addressable storage locations for storing a plurality of instructions for specifying the functions of a program to be executed by the microcomputer and said higher layer program memory having an output for providing data stored in an accessed storage location, with each instruction including only an ID word stored in a single storage location and optionally one or more parameters, stored in storage locations immediately following said single storage location, for use in address or numerical calculations; an upside layer program memory, having a plurality of storage locations, each accessed by one of said ID words stored in said higher layer program memory, and said upside layer program memory having an output for providing data stored in an accessed storage location, each storage location for storing upside layer data, including a function specifying portion, and an ID' word, and with a first ID' word stored at a first storage location accessed by the ID word included in the corresponding instruction; a downside layer program memory, having a plurality of addressable storage locations, each accessed by an ID' word, and said downside layer program memory having an output for providing data stored at an accessed storage location, with each storage location for storing downside layer data, including a function code portion, and an ID' word, with a first storage location accessed by the first ID' word; ID decoding means, coupled to said upside layer program memory and to the output of said higher layer program memory to receive an ID word accessed from said higher layer memory, for accessing an addressable storage location in said upside layer program memory specified by said accessed ID word; ID' decoding means, coupled to said downside layer program memory and to the output of said upside and downside layer program memories to receive an ID' word accessed from said upside or downside layer program memories, for accessing said first addressable storage location is said downside layer program memory when said first ID' word is received and for accessing a second addressable storage location in said downside layer program memory when an ID' word stored in said first addressable storage location in said downside program memory is received; an execution unit for performing a function specified by said instruction and for calculating effective addresses of data to be processed in performing said function in response to received control signals; and command decoding means, coupled to the output of said higher layer and upside and downside layer program memories to receive said parameters, and said upside and downside layer data, for generating control signals to control said execution unit to calculate effective addresses in response to downside layer function code portions accessed from said downside layer program memory, and, responsive to a received function code portion of downside layer data, using said upside layer function code portion to form a command to control said execution unit to perform a function specified in said program if said received downside function code portion is a specific code and using said downside layer function specifying portion to form a command if said received function code portion is not the specific code so that the same storage locations in the downside layer can be utilized for a particular addressing mode if the function to be performed by the instruction in the program is different.