1. In a multi-processor computer system having a memory, a plurality of processors, a plurality of caches, and cache consistency logic, a cache control system comprising: means for establishing which processors of the plurality of processors are allowed to cache a specific portion of the memory; means for receiving a memory access request, said memory access request having addressing information and cache control information, said addressing information identifying a data item in said memory, said cache control information associating said data item with processors of said plurality of processors that are allowed to cache said data item; means for determining which processors of said plurality of processors are allowed to cache said data item based upon said cache control information; and means for activating said cache consistency logic only if at least one processor other than said processor originating said memory access request are allowed to cache said data item, said at least one other processor is allowed to cache said data item being denoted at least one first processor, wherein said cache consistency logic includes means for determining which of said at least one first processors cache a data item identified by said addressing information.