1. A method for verifying a digital circuit design by mapping the design as well as its testbench onto a reconfigurable hardware platform, said method comprising the steps of: synthesizing the design into a structural model; transforming a behavioral model of the testbench into a structural model maintaining exact simulation semantics, said structural model comprising a plurality of finite state machines (FSMs) corresponding to each timed and untimed parallel block of code in said behavioral model; mapping and executing said FSMs onto the reconfigurable hardware platform, generating a global scheduler for synchronized execution of said FSMs; automatically partitioning portions of said testbench for execution on a sequential computation platform; and automatically synthesizing an interface for interaction between the reconfigurable hardware platform and the sequential computation platform to enable execution of said portions partitioned by the computation platform.