1. A test circuit comprising: a first node for coupling to a digital multilevel memory system; a first switch coupled to the first node to selectively couple an input node to the first node in response to a first signal indicative of a write mode of the digital multilevel memory system; a transistor including first and second terminals spaced apart with a channel between the first and the second terminals and including a gate controlling current in said channel, said first terminal being coupled to a voltage node, the second terminal being coupled to an output node; a second switch selectively coupling the first node to the gate of the transistor in response to a second signal indicative of a read mode of the digital multilevel memory system.