1. A semiconductor memory element comprising: a first power-supply terminal and a second power-supply terminal; a MIS (Metal Insulator Semiconductor) transistor including a gate; a two-terminal variable resistor element connected between the gate of the MIS transistor and the first power-supply terminal, the variable resistor element having a resistance that changes in accordance with a current flowing in the variable resistor element or the direction in which the current flows but remains unchanged due to cutoff of the current; and a fixed resistor element connected between the gate of the MIS transistor and the second power-supply terminal.