1. A random access memory in an integrated circuit, comprising: an array of memory cells; read circuitry for sensing contents of selected memory cells in the array in a read operation; write circuitry for writing contents of selected memory cells in the array in a write operation; and power supply switch circuitry for applying a first power supply voltage to the array responsive to a control signal indicating that the memory is to operate in a read/write mode, and for applying a second power supply voltage to the array responsive to a control signal indicating that the memory is to operate in a read-only mode, wherein the second power supply voltage is lower than the first power supply voltage.