1. A switch core system for communicating with a plurality of separate sources of cell data, each of the separate sources including a slave arbitration subsystem, said switch core system comprising; a bus subsystem for coupling the switch core system to the plurality of separate sources, said bus subsystem comprising a control bus, a processor bus, and multiple cell buses for coupling cell data between the switch core system and said plurality of separate sources of cell data; an arbitration subsystem comprising: means for assigning each of the separate sources to a respective one of the cell buses; and bus arbitration controller means for selectively allocating access to the cell buses for communication of cell data between the switch core system and the sources; a processor subsystem comprising: a processor; initialization means for initializing operation of all coupled slave arbitration subsystems; and a shared memory subsystem comprising: addressable means for selectively storing cell data from specific ones of the sources and outputting stored cell data to specified ones of the sources via the multiple cell buses responsive to the arbitration subsystem.