1. A computer processor comprising: a multiplexer having a first input, a second input, a third input, and an output; a scheduler coupled to said multiplexer third input; an execution unit coupled to said multiplexer output; and a replay system having an input coupled to said multiplexer output, said replay system comprising: a first checker coupled to said replay system input and said first multiplexer input; and a second checker coupled to said first checker and said second multiplexer input.