1. A jump with hazard barrier instruction executing on a multi-stage pipelined microprocessor comprising: an opcode field specifying a jump to a target address operation; a first register field, specifying a first register that contains a value used to determine said target address; a second register field, specifying a second register to contain a value used to determine a return address; and a hazard barrier hint field, for designating that instruction hazards are to be cleared as part of execution of the jump instruction.