1. A hardware circuit architecture for returning scalar single precision denormal results to double precision normal results in architected format with limited latency impact on performance, the hardware circuit comprising: a first hardware circuit component configured to perform a first normalization on a first unrounded single precision denormal result of a floating-point operation, wherein the first normalization includes performing fraction leading zero removal and exponent adjustment up to a minimum exponent threshold on the first unrounded single precision denormal result to yield a second unrounded single precision denormal result, wherein the first hardware circuit component is a floating-point unit normalizer circuit; the first hardware circuit component configured to count leading zeros of the second unrounded single precision denormal result; a second hardware circuit component configured to perform fraction rounding of the second unrounded single precision denormal result to yield a rounded single precision denormal result, wherein the second hardware circuit is a floating-point unit rounder circuit; a third hardware circuit component configured to pre-compute a first exponent and a second exponent for the second unrounded single precision denormal result in parallel with a second normalization of the rounded single precision denormal result, wherein the third hardware circuit component is a floating-point unit subtractor circuit; and a fourth hardware circuit component configured to output a final fraction result by performing the second normalization of the rounded single precision denormal result back to architected format, wherein the fourth hardware circuit component is a floating-point unit normalizer circuit; wherein the architected format includes the final fraction result and one of the first exponent and the second exponent.