1. A processor, comprising: a resource scheduler including a first logic to assign alias resources to instructions within an atomic region of instructions, the atomic region including a plurality of reordered instructions; a dispatcher including a second logic to dispatch the atomic region of instructions for execution; a memory execution unit including: a third logic to identify an executed, unretired store operation from the atomic region in a memory ordered buffer; a fourth logic to determine that the store operation is speculative; a fifth logic to determine whether a cache line in a data cache is non-speculative, the cache line associated with the store operation; and a sixth logic to determine whether to block a write of a store operation result to the data cache based upon the determination that the store operation is speculative and a determination that the cache line is non-speculative.