1. A processor, comprising: an instruction decoder to decode an instruction having a first operand, a second operand, and a third operand; and an execution unit coupled to the instruction decoder to execute the decoded instruction, the execution unit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, to generate a final result, and to store the final result in a storage location indicated by the first operand.