1. An arithmetic operating apparatus that selects one operation from among a single data stream operation that processes a single data stream and a multiple data stream operation that processes a plurality of data streams in response to a single arithmetic instruction and performs the selected operation, the apparatus comprising: a register group including a first register region and a second register region each including a same number of a plurality of registers storing operands that are to be subject to arithmetic operation in response to the single arithmetic instruction; and a processor that generates a first instruction for a first arithmetic operator and a second instruction for a second arithmetic operator according to the single arithmetic instruction, the first arithmetic operator performing an arithmetic operation on operands read from one or more of the plurality of registers included in one of the first register region and the second register region in obedience to the first instruction, the second arithmetic operator performing an arithmetic operation on operands read from one or more of the plurality of registers included in one of the first register region and the second register region in obedience to the second instruction, each of the first and second arithmetic operators being a multi-input single-output multiply-add operator capable of switching a kind of arithmetic operation according to an instruction kind code included in the single arithmetic instruction, the instruction kind code indicating a kind of instruction of the single arithmetic instruction, wherein the processor: when the single data stream operation is selected, generates the first instruction according to all bits in each of a plurality of register number specifying fields included in the single arithmetic instruction so as to cause the first arithmetic operator to perform an arithmetic operation on operands read from one or more of the plurality of registers included in one of the first register region and the second register region, the register number specifying fields specifying operands in the register group that are to be output from the register group to the first and second arithmetic operators, when the multiple data stream operation is selected and a most significant bit of each of the register number specifying fields is unused, generates the first instruction according to the instruction kind code and remaining bits in each of the register number specifying fields except for the most significant bit, so as to cause the first arithmetic operator to perform an arithmetic operation on operands read from one or more of the plurality of registers included in the first register region, the remaining bits specifying operands in the first register region or the second register region that are to be output from the first register region or the second register region to the first and second arithmetic operators, and generates the second instruction according to the instruction kind code and the remaining bits, so as to cause the second arithmetic operator to perform an arithmetic operation on operands read from one or more of the plurality of registers included in the second register region, and when the multiple data stream operation is selected and first particular instruction information is set in the most significant bit of at least one of the register number specifying fields, generates the first instruction so as to cause the first arithmetic operator to perform an arithmetic operation on operands read from one or more of the plurality of registers included in the second register region, or generates the second instruction so as to cause the second arithmetic operator to perform an arithmetic operation on operands read from one or more of the plurality of registers included in the first register region.