1. A switchless network topology system for parallel computation, comprising: a plurality of nodes, each node being one of a computing block on chip, a memory controller, a single core on chip, a processor, a storage hard drive, a computer, a group of internally optimized group of computers, and a computational center: wherein each node being configured to create a routing table by: calculating a shortest path of transmission paths between a starting node and a destination node of the nodes, wherein the shortest path has no relay node or has at least one relay node between the starting node and the destination node; removing the transmission path between the starting node and a first relay node of the shortest path, identifying another shortest path between the starting node and the destination node, and repeating the step of removing and identifying for the another shortest path to identify other shortest paths between the starting node and the destination node; and creating the routing table based on every shortest path between any starting node and any destination node of the nodes.