1. A processor comprising: a Confidence/Sampling Read-After-Write Resynchronization Predictor (CSRRP) configured to receive an address of an instruction to be executed, store a CSRRP entry comprising the address of the instruction and a confidence score that indicates whether executing the instruction as a resynchronization predicted store (RPS) will avoid a Read-After-Write (RAW) resynchronization exception (RRE) penalty, and determine whether to execute the instruction as the RPS based on the confidence score.