1. A memory buffering system comprising: a transfer bus; a unified memory controller (UMC) comprising a unified host buffer and a request queue; and a plurality of clients coupled together in a chain architecture, each of the plurality of clients comprising a respective memory element and a corresponding buffer, the plurality of clients being configured to communicate with the unified host buffer in a series bus configuration; wherein the UMC is configured to selectively arbitrate bus ownership of the transfer bus for the plurality of clients according to a time division multiple access (TDMA) scheme and a priority based scheme based on a number of requests pending from one or more of the plurality of clients; and wherein the UMC is further configured to allocate available buffer space of the corresponding buffer of each of the plurality of clients situated upstream from a memory element of a client being accessed from among the plurality of clients.