1. A computer-implemented method for legalizing a portion of a circuit layout, the method comprising: receiving a set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes, wherein the set of technology constraints include design rules; receiving a set of design constraints, wherein the set of design constraints specify object placements and/or configurations that must be preserved during legalization, wherein a design constraint in the set of design constraints requires that symmetry between a first polygon and a second polygon with respect to an axis of symmetry be preserved during legalization, wherein the axis of symmetry is located between the first polygon and the second polygon; and modifying, by computer, a portion of the circuit layout to obtain a modified portion of the circuit layout, wherein said modifying involves modifying the size and/or shape of a first polygon to satisfy at least one technology constraint, and modifying the size and/or shape of a second polygon to preserve symmetry between the first polygon and the second polygon with respect to the axis of symmetry.