1. A computing system operable in multiple security modes, comprising: a plurality of register bits that indicate whether said computing system is in one of a secure or non-secure mode depending upon a state of said bits; an instruction bus; a memory for secure and non-secure instructions coupled to said instruction bus; a monitoring device coupled to said register bits and to said instruction bus, said monitoring device operable to block execution of a non-secure instruction if said non-secure instruction is fetched on said instruction bus while said register bits indicate said system is in said secure mode.