1. A memory interface device operable to provide an interface between a data processor and a memory system, the device comprising: an address generator operable to generate first and second memory addresses, the first memory address being less than or equal to a fractional address, the second memory address being greater than or equal to the fractional address and the fractional address having a fractional part; a memory access unit coupled to the address generator and operable to retrieve a first data value from the memory system at the first memory address and a second data value from the memory system at the second memory address; and a data access unit coupled to the memory access unit and address generator and operable to interpolate between the first and second data values in accordance with the fractional part of the fractional address and further operable to pass the interpolated value to the data processor.