1. In a computer system having a processor and a programmable non-volatile memory device, a memory paging system comprising: a page selector, coupled to said processor, for selecting one selected page of a plurality of pages in said programmable non-volatile memory device; a page decoder, coupled to said page selector and said processor, for receiving address signals from said processor directed to said programmable non-volatile memory device and for modifying said address signals to access said selected page; and swapping logic, operably disposed in said selected page and executed by said processor, said swapping logic enabling said page selector to allow access to said selected page by said processor, said swapping logic further including logic for controlling access within said selected page by said processor.