1. A method for performing a group-multiply-add instruction in a programmable processor, the method comprising: partitioning a first register, a second register, and a third register into a plurality of floating-point operands; multiplying, in parallel, the plurality of floating-point operands from the first register by the plurality of floating-point operands from the second register and adding the plurality of floating-point operands from the third register, producing a plurality of floating-point numbers; and providing the plurality of floating-point numbers to a plurality of partitioned fields of a result.