1. A processor comprising: a plurality of vector registers comprising at least a first vector register and a second vector register; and an execution unit, operatively coupled to the plurality of vector registers, the execution unit comprising a logic circuit to execute a load instruction to load, into the first vector register and the second vector register, at least a first data item and a second data item, respectively, which are located at consecutive position numbers within a data structure stored in a memory, wherein the consecutive position numbers comprise a first position number and a second position number.