1. A method of data processing in a processor having a multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency, each of the first and second level register files including a plurality of physical registers, said method comprising: placing a first register value of a logical register obtained as an execution result of a first instruction in a first physical register of the first level register file, recording a first mapping between the logical register and the first physical register in a mapping data structure, and marking the first register value as non-speculative; in response to processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, moving the first register value to the second level register file, placing the second register value in a second physical register of the first level register file, marking the second register value as speculative, and replacing the first mapping in the mapping data structure with a second mapping between the logical register and the second physical register; in response to unsuccessful termination of the transactional code section, designating the second register value in the first level register file as invalid, such that the first register value in the second level register file becomes a working value of the logical register; and in response to successful termination of the transactional code section, designating the second register value in the first level register file as non-speculative.