1. A hardware forwarding element comprising a plurality of match-action stages, each match-action stage comprising a set of match-action tables, the hardware forwarding element comprising: a plurality of unit memories that are organized into a plurality of rows; a plurality of logical units (LUs) to implement at least a subset of the match action tables, each LU allocated a set of the unit memories, each LU aligned with a row of the unit memories; and a routing structure for providing each LU with access to a set of unit memories allocated to the LU, the routing structure comprising: a first vertical bus for providing each LU with a row above the LU's associated row access to at least one allocated unit memory in the above row; and a second vertical bus for providing each LU with a row below the LU's associated row access to at least one allocated unit memory in the row below, the second vertical bus being a separate, different bus from the first vertical bus, each of the first and second vertical buses comprising a read path and a write path.