1. Switching circuitry for transferring data from a specified input channel occupying a selected one of a plurality of time slots of an input time-division multiplex system to a specified output channel occupying a selected one of a plurality of time slots of an output time-division multiplex system comprising transfer memory means including a plurality of buffer memories each connected to receive a respective input time-division multiplex system and having a plurality of memory positions and being responsive to a position signal for writing incoming data from an input channel of an input time-division multiplex system into a selected buffer memory in a selected memory position thereof designated by said position signal and for transferring the data from said selected memory position to an output channel of a single output time-division multiplex system; input time slot generator means including a plurality of input time slot generators and output time slot generator means including a single output time slot generator for generating respective sets of time slot signals corresponding to the time slots of the input and output time-division multiplex systems, respectively; control circuit means including a write control circuit connected to said input time slot generator means and a read control circuit connected to said output time slot generator means and responsive to a position signal and a pair of signals designating the specified input and output channels for applying said position signal to said transfer memory means to write data from said input multiplex system into a memory position designated by said position signal to said output multiplex system in coincidence with generation of the time slot signal corresponding to said specified output channel, said write control circuit including a plurality of write memories each connected to a respective buffer memory for storing the address of said selected memory position in the associated buffer memory of said transfer memory means in a time slot occupied by said specified input channel of an input multiplex system and said read control circuit including a single read memory for storing the address of said selected memory position in said transfer memory means in a time slot occupied by said specified output channel in an output multiplex system; and distribution means for sequentially connecting said single read memory to said transfer memory means in control of said plural buffer memories.