1. In a matrix array processor, a segregratable elemental processor comprising: (a) a plurality of modules, each including means for performing at least one of a number of generalized logic functions on data; (b) a data bus operatively associated with each of said modules for the tranfer of data thereinbetween, said data bus including a data bus line, each of said mddules including means for transferring data to and from said data bus line at given points along said data bus line; (c) a pseudo-module operatively associated with said data bus at a given segregation point along said data bus line, said pseudo-module including means for effectively severing said data bus line at said given segregation point so as to block the transfer of data between any of said modules associated with respective portions of said data bus line on either side of said given segregation point.