1. A circuit, comprising: a reference clock configured to provide a reference clock signal operating at a reference frequency; and a poly-phase frequency multiplier coupled to the reference clock to receive the reference clock signal, the poly-phase frequency multiplier configured to provide an output signal with an output frequency that is a multiple of the reference frequency, the poly-phase frequency multiplier having: a poly-phase filter stage comprising resistor-capacitor (RC) delay stages configured to generate individual phases of a plurality of phases at the reference clock signal frequency, the plurality of phases separated by equal phase differences, an input bias stage to bias the poly-phase filter stage, and a logic stage configured to receive the plurality of phases from the poly-phase filter stage to generate the output signal having the output frequency therefrom.