1 ) A system 100 for emulation of multiple electronic designs in a single testbench on FPGA or Emulation system, said system 100 comprising: stimulus generation logics 101 and 103 ; a bus 102 coupled with said stimulus generation logics 101 and 103 ; a selection unit 104 connected to the bus 102 ; and another selection unit 105 ; wherein, a wrapper design 100 is created to run multiple instance(s) of a design or different design (s) on FPGA or Emulation system to optimally utilize the area, the wrapper design generates a stimulus using the stimulus generation logics 101 and 103 which acts as an input to the selection unit 104 through the bus 102 ; the selection unit 104 passes multiple inputs received from the stimulus generation logic(s) 101 and 103 in parallel; and the output of said instance(s) of design or different design(s) are connected to another selection unit 105 which selects one output of a design at a time.