1. A data transfer system with overlapped read and write operations and scalable address pipelining, comprising: a data bus including an address bus, a read bus, and a write bus; at least one master device coupled to separate address, read data and write data buses; at least one slave device attached to the local bus through shared, but decoupled address, read and write data buses; an arbiter apparatus coupled to the local bus, the arbiter allowing masters to compete for bus ownership; and scalable logic which programs address pipelining up to “N” deep master requests where “N” is any positive non-zero integer.