1. A processor comprising: a core to execute instructions, the instructions comprising memory operations, the core comprising: a register file having a plurality of registers to store data for use in execution of the instructions; a software translator executed within the core to: determine a relative order of memory operations, detect when a first memory operation has been reordered prior to a second memory operation with respect to an original order of memory operations, identify a reordering problem of the first memory operation with respect to the second memory operation, communicate the relative order of memory operations to the core; and an alias hardware module to verify that the memory operations were executed to distinct addresses.