1. A computer-implemented method for building in computer memory a subset of hierarehical circuit design data representing a physical design of a very large scale integrated (VLSI) circuit comprising the steps of: storing in the computer memory a VLSI design component identifying a leaf design entity in the hierarehical circuit design data; storing in the computer memory a set of placements in the hierarehical circuit design where the VLSI design component appears, the set of placements forming a subset of instances of the leaf design entity; associating with the VLSI design component and the placements a set of links, the links connecting various ones of the placements to one another to further denote placement of the VLSI design component within the hierarehical circuit design data; storing the set of links in the computer memory; storing in the computer memory a subset list in the form of a pruned graph appended to the VLSI design component, the subset list denoting the subset and including placements where the VLSI design component is identified in the hierarehical circuit design data, the pruned graph including leaf nodes and internal nodes, the leaf nodes and the internal nodes having associated instance counts, each instance count including first and second numbers, the second number being indicative of a total quantity of instances of a leaf design entity that could be represented at a node associated with the instance count; computing an instance count denoting a number of instances of the VLSI design component represented in the subset list; and appending the instance count to the subset list in the computer memory.