1. A memory system comprising: a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and one or more transmission buffers, wherein M is an integer equal to or more than 2; a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices; and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full.