1. A method for managing and controlling associativity of a microprocessor cache memory to a logical partition comprising: receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, wherein said unique partition identifiers are each associated with a logical processing partition executing on at least one core of said multi-core processor; responsive to translation of an memory cycle address resulting in a shared cache memory miss, identifying a position in a cache directory for data associated with said address, wherein said shared cache memory is multi-way set associative; responsive to said identifying of a position, associating a new cache line entry with said data and one of said registered unique logical processing partition identifiers; responsive to said associating of a new cache line entry, modifying said cache directory to reflect said association; and responsive to said modifying said cache directory, caching said data at said new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.