1. A method operational in a processing circuit including cache memory, comprising: loading at least portions of an executable code sequence in the cache memory; performing instruction fetches of the executable code sequence from the cache memory; detecting one or more instruction fetch cache misses in response to the instruction fetches, where an individual instruction fetch cache miss represents a fetched instruction absent from the cache memory for a corresponding instruction fetch of the executable code sequence; and monitoring the instruction fetches relative to the one or more instruction fetch cache misses in order to dynamically detect anomalous instruction fetch cache miss activity.