1. A co-processor system comprising: a plurality of configurable logic blocks (CLBs), each of the CLBs to reconfigure to perform a plurality of different logical functions, and each CLB including a plurality of lookup tables (LUTs), a first plurality of multiplexers to receive outputs of the LUTs, a first plurality of adders to receive outputs of the first plurality of multiplexers, a second plurality of multiplexers to receive outputs of the first plurality of adders, a second plurality of adders to receive outputs of the second plurality of multiplexers, a third plurality of multiplexers to receive outputs of the second plurality of adders, and a third plurality of adders to receive outputs of the third plurality of multiplexers.