1. A load/store unit comprising: a first buffer comprising a first plurality of entries, each of said first plurality of entries being configured to store a store address and a corresponding store data of a respective store memory operation; a first control logic coupled to said first buffer, said first control logic configured to detect a first load memory operation having a first load address which hits a first store address within a first entry of said first plurality of entries and for which a first corresponding store data is not stored within said first entry; a second control logic coupled to receive a signal from said first control logic indicative of detecting said first load memory operation, said second control logic configured to allocate a second entry of a second plurality of entries in a second buffer to said first load memory operation in response to said signal; and said second buffer coupled to said second control logic, wherein said second entry is configured to store a first load identifier identifying said first load memory operation and a first store data identifier identifying a source of said first corresponding store data in response to said second control logic allocating said second entry.