1. In a processor having an instruction pipeline and an AGEN Bypass bus, a verification method, comprising: a simulation monitor propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object; in response to a computation of an expected AGEN result in the simulated instruction object, a simulation driver selecting a second set of general purpose register values: updating the first set of general purpose register values with the second set of general purpose register values; and the simulation driver placing the second set of general purpose register values on a bus.