1. A transistor comprising: a substrate; a source region and a drain region within the substrate wherein the source region is separated from the drain region by a channel region; a floating gate overlying the channel region, the floating gate having a bottom surface for controlling a conductivity of the channel region and a sidewall surface; and N control gates laterally adjacent the sidewall surface of the floating gate wherein N is a positive integer greater than zero, each of the N control gates selectively altering the conductivity of the channel region by capacitive coupling, to the sidewall of the floating gate, voltages applied to each of the N control gates through the floating gate wherein each voltage provided by each of the N control gates is independent from all other voltages provided by other of the N control gates.