1. A computer-implemented formal verification method, comprising: by a computing device, receiving a specification of an n×n-bit multiplier circuit; performing a direct model checking operation for a M×n-bit multiplier circuit, where M<n; performing a series of model checking operations for multiplier circuits that are incrementally larger than the M×n-bit multiplier circuit; and outputting a verification result of the n×n-bit multiplier circuit specification based on the direct modeling checking operation and the series of model checking operations.