1. A test circuit for facilitating the testing of a memory device having at least one memory array containing a plurality of memory cells arranged in rows and columns, a sense amplifier having a pair of sense amplifier inputs and at least one output coupled to an externally accessible data terminal of the memory device, and a pair of complimentary digit lines for each column of the memory array, the test circuit comprising a switching circuit selectively coupled between the inputs of the sense amplifier and a plurality of pairs of digit lines, the switching circuit being structured to selectively operate in a normal mode to couple the pair of digit lines for a first column to the pair of sense amplifier inputs and being structured to selectively operate in a test mode to couple one of the digit lines of the pair of digit lines for a second column to one of the sense amplifier inputs and one of the digit lines of the pair of digit lines for a third column to the other of the sense amplifier inputs.