1. A processing system comprising a first processing domain and a second processing domain; each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core; the processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred, wherein following a reset of the thread under the execution of which the detected mismatch of internal state signals occurred, the processing system is arranged to perform a self-test and the supervisor component is arranged to determine which of a hard fault and a soft fault was responsible for the detected mismatch between compared internal state signals, and if it is determined that a soft fault was responsible for the detected mismatch, the supervisor component is arranged to reconfigure the reset thread for continued execution.