1. A computer system which includes an apparatus for monitoring the performance of a multithreaded processor, said apparatus comprising: a processor adapted to execute a plurality of threads simultaneously, each thread including a series of instructions; a plurality of programmable event counters to count two or more independent events generated by one or more threads of said plurality, said two or more events selected from a predetermined list of events resulting from the normal operation of said processor; one or more registers to control the operation of said event counters, each register also selecting the events to be counted from said list of events; and an access location to allow access to said event counters to determine a current count of said events.