1. A microprocessor coupled to a system memory by a bus, the microprocessor comprising: an instruction decode unit, for decoding an instruction, said instruction specifying a data stream in the system memory and a stream prefetch priority; a load/store unit, coupled to said instruction decode unit, for generating load/store requests to transfer data between the system memory and the microprocessor; a stream prefetch unit, coupled to said instruction decode unit, for generating a plurality of prefetch requests to prefetch said data stream from the system memory into the microprocessor, wherein said prefetch requests specify said stream prefetch priority; and a bus interface unit (BIU), coupled to said stream prefetch unit and said load/store unit, for generating transaction requests on the bus to transfer data between the system memory and the microprocessor in response to said load/store requests and said prefetch requests, wherein said BIU prioritizes said bus transaction requests for said prefetch requests relative to said bus transaction requests for said load/store requests based on said stream prefetch priority.