1. A hardware emulator comprising: a processor in a first discrete cluster of processors, the processor having a plurality of input ports, wherein one of the input ports is a shared input port; and selector logic, coupled to the shared input port, for receiving a first amount of input data from a first discrete data array within the first discrete cluster of processors and a second amount of input data from a second discrete data array within a second discrete cluster of processors, where the selector logic is coupled to a selector register for controlling an output of the selector logic and the output of the selector logic is supplied to the shared input port.