1. A method for generating a design of a multiplier, comprising the steps of: (A) generating a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of said multiplier, said first circuit being configured to multiply a plurality of polynomials; (B) generating a second circuit comprising a plurality of polynomial evaluators based on said parameters, said second circuit being (i) connected to said first circuit and (ii) configured to evaluate a polynomial modulo operation; and (C) generating said design of said multiplier in combinational logic by optimizing a depth of a plurality of logic gates through said first circuit and said second circuit, wherein a product of said polynomials resides in a finite field.