1. An apparatus for providing an instruction to a processor core in a multi-core microprocessor, the apparatus comprising: a match register storing an opcode that identifies an instruction to be replaced; an instruction fetch logic device receiving an incoming instruction to be run by the processor core, identifying an opcode of the incoming instruction, and storing the identified opcode of the incoming instruction in an instruction register; a swap register storing an instruction that replaces the identified instruction; a comparator determining whether the opcode stored in the instruction register and the opcode stored in the match register are same; and a multiplexer replacing the incoming instruction with the instruction stored in the swap register in response to determining that the opcode stored in the instruction register and the opcode stored in the match register are same.