1. In a software development system having a processor, a matcher arrangement comprising: processor bus means for transmitting dynamically changeable predetermined digital values under control of said processor; sample bus means for transmitting dynamically changeable digital values; said processor being operated to provide match control signals on corresponding match control leads; means for storing connected to said sample bus means and to said processor via said processor bus means, said means for storing being operated in response to said digital values of said processor to retain said dynamically changeable pluralities of predetermined digital values; said means for storing being further operated to produce one plurality of said predetermined digital values of said processor in response to a comparison of said dynamically changeable digital values transmitted on said sample bus means with said digital values stored in said means for storing by said processor; programmable logic array means connected to said processor via match control lead and to said means for storing, said programmable logic array means being operated in response to first values of said match control signals of said processor and to one plurality of said predetermined digital values to produce a range match signal for said digital value of said sample bus means being within a range of said predetermined digital values, said range match signal being transmitted to said processor; and said programmable logic array means being operated in response to second values of said match control signals of said processor and to said one predetermined digital value to produce at least one of a set of exact match signals for said digital values of said sample bus means being equal to at least one of said stored predetermined digital values, said exact match signals being transmitted to said processor.