1. A circuit, comprising: a source of N reference clock frequencies, where N is an integer greater than one; N frequency extender circuits receiving the N reference clock frequencies and generating N frequency extended output clock signals therefrom; a plurality of N seed slewers producing N seed update values; a plurality of N seed registers each one receiving one of the N seed update values and producing N seed masks therefrom; and a plurality of N logic circuits each receiving one of the N seed masks and one of the N frequency extended output clock signals; each of the N logic circuits producing a pseudorandom sequence from the seed mask and the frequency extended output clock signal: