1. A multicore processor, comprising: a plurality of cache memories; a plurality of processor cores, each associated with one of the plurality of cache memories; one or more memory interfaces providing memory access paths from the plurality of cache memories to a main memory; and one or more input/output modules configured to couple data between an input/output interface and at least one of a memory interface of the one or more memory interfaces and a cache memory of the plurality of cache memories; with at least some of the plurality of cache memories assigned as respective home locations for caching a corresponding portion of the main memory, and configured to maintain the cached corresponding portion of the main memory based on whether a processor core or an input/output module is requesting access to the cached corresponding portion of the main memory.