1. A method for timing optimization of an integrated circuit design using a timing optimization system, the method comprising: loading an original delay value and an original gate configuration net-list for an original gate from a results database; identifying a near optimum gate configuration using near optimum gate configuration information stored in a delay characterization database for the original gate; loading a near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration; and producing a timing optimized gate configuration from running an incremental static timing analysis of the near optimum gate configuration.