1. A computer system for issuing and executing multiple instructions using a minimal instruction set, the computer system comprising: a memory means for storing instructions and data, the memory means having an address input, a bi-directional data port, a control input, and a data output; an instruction buffer for storing multiple instructions for execution in parallel, the instruction buffer having an address input, a data output and a control input, the address input of the instruction buffer coupled to the data output of the memory means; a plurality of register files for storing data, each of the register files having a a bi-directional port, a data input, a first data output and a second data output; a plurality of functional units for performing logical and arithmetic operations, each of the function units having a first data input, a second data input, a control input and an output, each of the functional units corresponding to a respective register file, and the first data input of each functional unit coupled to the first data output of its respective register file, the second data input of each functional unit coupled to the second data output of its respective register file, the output of each functional unit coupled to the data input of its respective register file; a data routing circuit for selectively transferring data between the memory means and the plurality of register files or between one of the plurality of register files and another register file of the plurality of register files, in response to a routing control signal, the data routing circuit having a control input, a first bi-directional port coupled to the bi-directional data port of the memory means, a plurality of second bi-directional data ports, each of the second bi-directional data ports coupled to the bi-directional port of a respective register file; and a control unit for controlling the memory means, the instruction buffer, the functional units and the register files, the control unit determining largest sequential number of instructions within the plurality of instructions received that can be issued in parallel and asserting control signals to execute the instructions in parallel, the control unit having: an input coupled to the data output of the instruction buffer for receiving a plurality of instructions to be executed in parallel, a memory control output coupled to the control input of the memory means, a memory address output coupled to the address input of the memory means, an instruction buffer control output coupled to the control input of the instruction buffer, a plurality of function control outputs each of the function control outputs connected to a respective control input of a functional unit, and a routing control output coupled to the control input of the data routing circuit to provide the routing control signal.