1. A process of selecting different 1149.1 TAP domain arrangements within an integrated circuit comprising the steps of: performing an 1149.1 instruction shift operation through a first 1149.1 TAP domain arrangement, performing an 1149.1 instruction update operation at the end of said 1149. 1 instruction shift operation, and; in response to said 1149.1 instruction update operation, selecting a second 1149.1 TAP domain arrangement which differs from the first 1149.1 TAP domain arrangement.