1. A Signal Processing Engine (SPE), comprising: a process input; a forward delay chain operably coupled between a forward data input and a forward data output and configured for generating a selectable forward tap; a reverse delay chain operably coupled between a reverse data input and a reverse data output and configured for generating a selectable reverse tap; a coefficient buffer configured for circulating coefficients within the coefficient buffer and generating a coefficient output; an add/subtract unit configured for adding or subtracting the selectable forward tap and the selectable reverse tap to generate an intermediate output; a multiply unit configured to multiply the intermediate output and the coefficient output to generate a multiply result and further configured to bypass, add, or subtract the multiply result with the process input to generate a process output; and an output delay chain comprising a plurality of serially connected shift registers operably coupled between the process output and a clock delayed process output, the output delay chain including a programmable length.