1. An integrated circuit (IC) for pattern detection comprising; a digital signal processing unit configured to produce a digital signal processing unit output; a selected mask of a plurality of masks selected by a first multiplexer, the first multiplexer coupled to the comparison circuit; a selected pattern of a plurality of patterns selected by a second multiplexer, the second multiplexer coupled to the comparison circuit; a comparison circuit comprising: a first equality circuit for comparing the digital signal processing unit output with the selected pattern and producing a first comparison output; a second equality circuit for comparing the digital signal processing unit output with an inverted selected pattern and producing a second comparison output; a masking circuit coupled to the first and second comparison outputs for generating a first and second plurality of comparison bits; and one or more trees of AND functions for combining the first and second plurality of comparison bits into a first comparison signal and a second comparison signal; a first set of registers coupled in series for storing the first comparison signal and a previous first comparison signal associated with a prior clock cycle; and a second set of registers coupled in series for storing the second comparison signal and a previous second comparison signal associated with the prior clock cycle.