1. A memory architecture comprising: a plurality of local input and output circuitries (LIOCs), each LIOC coupled to at least one memory bank; and a global input and output circuitry (GIOC) coupled to the plurality of LIOCs, the GIOC comprising a plurality of global sub-write circuitries, wherein one global sub-write circuitry out of the plurality of global sub-write circuitries is enabled to provide a write-data to a selected LIOC from the plurality of LIOCs.