1. A semiconductor associative memory including a memory array comprising: unit storage circuits each having k bits arranged in R rows and W columns (R, W, k are natural numbers); unit comparison circuits arranged in R rows and W columns for comparing input data of W×k bits in terms of word length and reference data stored in said unit storage circuit at every unit of k bit; weighted word comparators for weighting each bit of output data from each row of said unit comparison circuits; row decoders of R rows; and column decoders of W×k columns.