1. A system, comprising: an interconnect to couple to one or more processor cores; and an atomic processing engine (APE) coupled to the interconnect, the APE: receiving a plurality of commands from the one or more processor cores through the interconnect; comparing memory locations to be accessed during operations for two or more of the plurality of commands to determine whether at least one same memory location is to be accessed during the operations for the two or more of the plurality of commands; upon determining that at least one same memory location is to be accessed during the operations for the two or more of the plurality of commands, performing the operations for the two or more of the plurality of commands serially; and upon determining that no same memory location is to be accessed during the operations for the two or more of the plurality of commands, performing the operations for the two or more of the plurality of commands in parallel.