1. A method for increasing the usable memory capacity of a logic simulation hardware emulator, the method comprising the steps of: transforming an original logical array within a logic model into a transformed logical array during a logic synthesis operation, wherein a row within the transformed logical array comprises a plurality of merged rows from the original logical array; and modifying read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time.