1. A cache memory control device which controls a pipeline processing on a command to access a cache memory, comprising: a cache access determination device to determine whether an externally received command is a command to access the cache memory during execution of the command or a command not to access the cache memory during execution of the command; and a path switch device to switch a path of a command in order to put the command to access the cache memory during execution of the command in the pipeline processing, and output the command not to access the cache memory during execution of the command to an external unit without putting the command in the pipeline processing.