1. In a system for computing a fast Fourier transform having a data memory for storing data values and a coefficient memory for storing coefficient values, a circuit for addressing the data memory comprising: a multiplexer having an output for addressing the data memory, a first input of the multiplexer defining a data memory read address and a second input of the multiplexer defining a data memory write address; and a write FIFO disposed in communication with the second input of the multiplexer, the write FIFO having an input that is connected to the first input of the multiplexer.