1. A method for testing at least one memory with a plurality of charge storing cells coupled to a plurality of bit-lines and one or more cell plates for biasing the cells and one or more bit-line plates for biasing the bit-lines, the method comprising: putting the memory in a test mode; applying a test pattern to the memory; providing a first voltage higher than one half of a positive supply voltage (Vdd) to the cell plate when writing a ‘1’ to a predetermined cell; and providing a second voltage lower than one half of the Vdd to the cell plate when writing a ‘0’ to a predetermined cell, wherein the first and second voltages are applied to emulate weak charge storage in the memory cell.