1. An array-type processor, comprising: a state transition control section including a state transition table memory for storing a state transition table in which transition rules between a plurality of operation states are written, and a sequencer section for controlling, using the state transition table memory, transitions between the operation states and for determining the operation states at a particular point of time; and a data path section independent of said state transition control section, including a plurality of processor elements for executing processing of operations according to the operation states determined by said state transition control section, and a plurality of programmable switch elements for connecting the processor elements to each other according to the operation states determined by said state transition control section, said processor elements and said programmable switch elements being electrically connected in a two-dimensional array shape, wherein: each said processor element includes an instruction code memory for storing a plurality of instruction codes, an instruction decoder for decoding an instruction code read from said instruction code memory, and an operating section for executing processing of operation according to the instruction code decoded by said instruction decoder; and each said programmable switch element includes a connection layout information memory for storing a plurality of sets of connection layout information, the information indicating a connection layout between said processor elements and said programmable switch elements and/or between said programmable switch elements.