1. A semiconductor integrated circuit device, comprising: a central processing unit (CPU); a bus; and an aligner arranged between the CPU and the bus, wherein the CPU obtains an instruction code from a memory via the bus and performs an operation according to the instruction code, and obtains data necessary for performing the operation according to the instruction code, the instruction code is stored in the memory by any determined one endian of little endian or big endian, and the data includes vector address information represented by N bits (N=8×k: k is a positive integer that is two or more) providing an address of an instruction code to be fetched by the CPU, and a determination is arbitrarily made whether the data is stored in the memory by the little endian or the big endian, when a data access is carried out by an N-bit length, the aligner supplies the data to the CPU in a byte order stored in the memory regardless whether the data is stored by the little endian or the big endian, when the CPU accesses the vector address information, the aligner supplies the vector address to the CPU in a byte order stored in the memory regardless whether the vector address information is stored by the little endian or the big endian, and when a data access is carried out by a bit length different from the N bit, the aligner changes the byte order stored in the memory so as to supply the data to the CPU according to whether the data is stored by the little endian or the big endian, and regardless of whether or not a size of the data is the same as a size related to the vector address.