1. A high performance graphics applications controller comprising: a core processor; a co-processor sharing a common instruction set with said core processor; said core processor executing at least one instruction from said common instruction set when at least one other instruction from said common instruction set is received by said co-processor; said co-processor executing said at least one other instruction using hardware dedicated to the execution thereof; said co-processor executing said at least one other instruction independently of said core processor; said co-processor executing said at least one other instruction using a hardware data path, said hardware data path functions including a barrel shifter operation in which said barrel shifter circularly shifts data in order to align the data to correspond to the edge of a video display; a first color register to determine the background color when an external color monitor is used, a second color register to determine an alternate background color, a color expand function which selectively applies the color specified by said first color register or the color specified by said second color register when an external color monitor is used; an edge mask register further consisting of a left edge mask and a right edge mask which determines the boundaries of the video data being manipulated; a raster operation function which selectively performs a logical operation on the video data; and a destination multiplexer which selectively determines which internal source of data is output on a bit by bit basis.