1. A processor comprising: a register file having a first portion implementing a first width corresponding to a first operand size and a first data type and a second portion implementing a second width corresponding to a second operand size and the first data type; and a map unit coupled to receive an instruction operation and configured to assign a register in the register file to the result of the instruction, wherein the map unit is configured to select the register from the first portion responsive to the instruction operation having the first operand size, and wherein the map unit is configured to select the register from the second portion responsive to the instruction operation having the second operand size.