1. An apparatus for adapting a scalar data processor having a cache memory connected between main memory and a central processing unit, for efficient vector processing including: means for defining separate scalar and vector data areas in said cache memory, vector mode selection means for selectively enabling access to either said vector or scalar data areas of said cache memory, cache memory addressing means including separate vector and a scalar addressing means responsive to said vector mode selection means and said central processing unit for accessing either said vector or scalar data areas of said cache memory, wherein said central processing unit includes: a pair of operand registers, and a result register, coupling means for providing a data path from said operand registers to an ALU and a further data path from an ALU to said result register, second coupling means for providing a data path from said cache memory to one of said operand registers and to said result register; an output buffer; third coupling means providing a data path from either of said operand registers to said second coupling means and to said output buffer; fourth coupling means providing a data path from said second coupling means or said output buffer to said cache memory; and fifth coupling means providing a data path from said result register to either of said operand registers.