1. An integrated in-system programmable logic device, operable during a normal device operating state to receive logical input signals and provide output signals in dependence on predetermined logic functions implemented by selective connection of input lines to product term lines, comprising: a first set of device input terminals dedicated to receiving input logical data; a second set of device terminals dedicated to the function of receiving input logical data or providing output logical data; a programmable array, said array including a plurality of input lines, a plurality of product term lines and a plurality of output lines, said input lines being coupled to respective ones of said device input terminals; said programmable array comprising an array of nonvolatile memory cells arranged in rows and columns, each cell associated with predetermined ones of said input lines and said product term lines and arranged to selectively connect said input line to said product term line in dependence on the cell state, each cell comprising a cell selection element and an electrically erasable and reprogrammable nonvolatile memory element which retains a selected cell state upon interruption of device power; a first device utility terminal dedicated for device utility functions; data receiving means for receiving cell selection data and row programming data through said first device utility terminal during a device utility state; means for programming the cells of said array to predetermined conditions in dependence on said cell selection and programming data during said utility state; and means for isolating said first set of device input terminals from said array and from said programming means during said utility state; whereby said device may be programmed to a desired configuration during said utility state while installed in a user's system without the necessity for voltage and timing requirements on said input terminals.