1. A method of performing timing analysis on a circuit design, the method comprising: by using a computing device, receiving a signal path that traverses a plurality of gates; for each of the plurality of gates, receiving a gate distribution that represents delay at the gate using a number of statistical moments that comprises a standard deviation and at least one moment that has a higher order than the standard deviation; computing statistical moments for a path distribution representing delay on the signal path by propagating gate distributions; and reconstructing a distribution function based on the computed statistical moments for the path distribution.