1. An apparatus with a delta sigma (ΔΣ) modulator, comprising: a quantizer configured to quantize an analog signal and provide multiple data bits in a sequential order, wherein the quantizer comprises a successive approximation analog-to-digital converter (ADC); a dynamic matching element (DEM) unit coupled to the quantizer and configured to receive the multiple data bits, to generate intermediate bits based on at least one earlier data bit from the quantizer, and to generate multiple control signals based on the intermediate bits and a latest data bit from the quantizer; and multiple digital-to-analog converters (DACs) coupled to the DEM unit and configured to receive the multiple control signals, each DAC being controlled by a respective control signal.