1. A sequential computing system consisting of at least one sequential computer which comprises: an adder for information processing having a first, a second and a third input, and a first and a second output; a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh and a twelfth gate, each of which has a control input, said control inputs being connected together; at least one accumulator register having an input, a direct output and an inverse output, said input of said accumulator register being connected via said fourth gate to said first output of said adder and via said fifth gate to its own direct output, said direct output of said accumulator register being connected via said sixth gate to said second input of said adder, and said inverse output of said accumulator register being connected via said seventh gate to said second input of said adder; series connected registers which are the main memory of the computer, each of said memory registers having a direct output and an input, said direct output of a last in order of said series connected memory registers being connected via said first gate to said first input of said adder, said input of at least one register of said series connected memory registers being connected via said second gate to said output of the preceding register of said series connected memory registers and via said third gate to said first output of said adder, said input of the first register of said series connected memory registers being connected via said tenth gate to said direct output of the last in order register of said series connected memory registers, via said eleventh gate to said direct output of said accumulator register, and via said twelfth gate to said output of at least one more of said series connected memory registers; at least one single digit Link register for carry storage having an input, a direct output and an inverse output, said input of said Link register being connected via said eighth gate to its own direct output and via said ninth gate to said second output of said adder; a program matrix having inputs and outputs; a device for commutation of input signals of said program matrix having inputs and outputs, said inputs of said program matrix being connected to said outputs of said device for commutation of input signals of said program matrix; a device for commutation of output signals of said program matrix having inputs, a first set, a second set, a third set and a fourth set of outputs, and an output, said outputs of said program matrix being connected to said inputs of said device for commutation of output signals of said program matrix; a synchroprogram matrix having inputs and outputs; an output decoder of said synchroprogram matrix having a first and a second set of inputs and outputs, said outputs of said synchroprogram matrix being connected to said first set of inputs of said output decoder; a device for commutation of input signals of said synchroprogram matrix having a first set and a second set of inputs and outputs, said inputs of said synchroprogram matrix being connected to said outputs of said device for commutation of input signals of said synchroprogram matrix, said first set of inputs of said device for commutation of input signals of said synchroprogram matrix being connected to said third set of outputs of said device for commutation of output signals of said program matrix; a microinstruction matrix to control said gates having inputs and outputs, said outputs being connected to said control inputs of each of said gates; a device for commutation of input signals of said microinstruction matrix having inputs and outputs, said inputs of said device for commutation of input signals of said microinstruction matrix being connected to said outputs of said output decoder, said outputs of said device for commutation of input signals of said microinstruction matrix being connected to said inputs of said microinstruction matrix; a controlled synchronizer for double periodic synchronization having at least three series connected counters to initiate time separated clock signals, said first counter having an input, a set of outputs, a first and a second output, said second counter having an input, a set of outputs, a first and a second output, said third counter having an input, a first and a second set of outputs, and a first and a second output, said input of said first counter being connected to a synchronization input of said computer, said first set of outputs and said second output of said third counter being connected to synchronization outputs of said computer, said input of said second counter being connected to said second output of said first counter, said input of said third counter being connected to said second output of said second counter, and at least one control signal forming unit having inputs and outputs, said inputs of said control signal forming unit being connected to said second set of outputs of said third counter, the second set of inputs of said device for commutation of input signals of said synchroprogram matrix being connected to said set of outputs of said second counter, said second set of inputs of said output decoder being electrically coupled to said outputs of said control signal forming unit to provide for a sequence of microinstructions; an address counter having a first, a second, and a third set of inputs, and outputs, said outputs of said address counter being connected to said inputs of said device for commutation of input signals of said program matrix, said first set of inputs of said address counter being connected to said first set of outputs of said device for commutation of output signals of said program matrix; an address counter control unit having a first, a second and a third input, a set of inputs, a set of outputs, and a first and a second output, said second set of inputs of said address counter being connected to said set of outputs of said address counter control unit, said set of inputs of said address counter control unit being connected to said second set of outputs of said device for commutation of output signals of said program matrix, the second input of said address counter control unit being connected to said first output of said third counter, said first input of said address counter control unit being connected to said direct output of said single digit Link register.