1. A processor comprising: a decoder to decode an SM4 instruction, the SM4 instruction to specify a first source data operand set of elements and a second source data operand set of elements; and one or more execution units, responsive to the decode of the SM4 instruction, to store a result of the SM4 instruction, which is to have been generated during performance of the SM4 instruction, in a single destination register, the result to include: a first result of one or more SM4-round exchange that are to have been performed using a first portion of the first source data operand set of elements and one or more corresponding keys from the second source data operand set of elements; and a second result of one or more SM4 key generation that are to have been performed using a second portion of the first source data operand set of elements and one or more corresponding constants from the second source data operand set of elements.