1. An overlay optimization system for registering field patterns on wafers comprising: a first field stepper for registering a first field pattern; a second field stepper for registering a second field pattern overlaying said first field pattern; an overlay measuring instrument for measuring pattern misregistration data of said first and second field patterns; means for generating an overlay coefficient associated with an assignable source of overlay error from said pattern misregistration data; means for calculating the overlay error associated with said assignable source using said overlay coefficient; and means for adjusting said first and second field steppers for reducing said overlay error.