1. A processor comprising: a plurality of packed data registers; a decode unit to decode an instruction, wherein the instruction is to indicate a source packed data operand that is to include a plurality of Morton coordinates, is to indicate a dimensionality of a multi-dimensional space that is to have points that the Morton coordinates are to be mapped to, is to indicate a given dimension of the multi-dimensional space, and is to indicate a destination storage location; and an execution unit coupled with the packed data registers and coupled with the decode unit, the execution unit, in response to the decode of the instruction, to store a result packed data operand in the destination storage location, wherein the result packed data operand is to include a plurality of Morton coordinates that are each to correspond to a different one of the Morton coordinates of the source packed data operand, wherein the Morton coordinates of the result packed data operand are to be mapped to points in the multi-dimensional space that are to differ from the points that the corresponding Morton coordinates of the source packed data operand are to be mapped to by a fixed change in the given dimension that is to be indicated by the instruction.