1. A method for verification of soft error resilience of devices from design data for a logic design, comprising: selecting a statistically relevant set of Soft Error Rate (SER) sensitive logic devices deemed critical to a SER robustness for a test process of logic design by using a SER categorization tool to generate a SER sensitive device test set; and inducing a logic state fault in successive ones of said devices in said test process of functional design verification which provides a sufficient delay after injection for the logic design to detect a logic fault for those devices in said test process; and wherein the SER sensitive Device Test Data set is used to make a correction of a logic state fault found for a device during the test process which is determined to need to be corrected according to the logic design.