1. A reconfigurable Viterbi decoder comprising: a reconfigurable data path comprising a plurality of reconfigurable functional blocks, the plurality of reconfigurable functional blocks including: i) a reconfigurable branch metric calculation block; and ii) a reconfigurable add-compare-select and path metric calculation block; and a programmable finite state machine for controlling the reconfigurable data path, wherein the programmable finite state machine executes a plurality of context-related instructions associated with the reconfigurable Viterbi decoder, wherein the reconfigurable Viterbi decoder is implemented using a plurality of context-based operation reconfigurable instruction set processor (CRISP) devices that shut down independently of each other.