1. A cache memory for a data processing system including an interconnect fabric and at least first and second coherency domains each containing at least one processing unit, said cache memory comprising: a data array; a cache directory of contents of said data array; and a cache controller including a prefetch predictor that determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address, wherein said cache controller issues said first prefetch operation on the interconnect fabric with said predicted scope.