1. A controller comprising a multi-core processor comprising a plurality of cores with independent instruction cache memories to execute a sequential program with a size exceeding a capacity of the instruction cache memory, the controller comprising: a memory in which the sequential program is stored; a program profile information generating section that analyzes an arrangement of the sequential program on the memory to generate and store program profile information in the memory; a program execution information generating section that, based on the program profile information, divides the sequential program into a plurality of programs each with a size fitted into the instruction cache memory and stores program execution information on the divided programs in the memory; a first rewrite inhibiting section that, in accordance with the program execution information, stores the divided programs in the instruction cache memories of the respective cores and inhibits rewriting of the cache memories with the programs stored therein; a second rewrite inhibiting section that, after execution of the stored program is started, based on the program execution information, stores the divided program to be executed next in the instruction cache memory of another core and inhibits rewriting of the cache memory with the program stored therein; and rewrite inhibition canceling section that, when the program in execution ends, starts executing the program to be executed next and cancels the inhibition of rewriting of the cache memory of the core having executed the program.