1. An apparatus, comprising: an instruction-grouping unit configured to organize a plurality of instructions for a computer processor into groups of instructions prior to execution; a plurality of execution units configured to execute the groups of instructions based upon cycles of a clock signal; and a delay-identification unit including: a delay counter configured to count the cycles occurring in a time period between when one of the groups of instructions is ready to be dispatched for execution by one or more execution units of the plurality of execution units, and when the one group of instructions is completely executed by the one or more execution units, a threshold register configured to store a threshold number of cycles that represents an undesired amount of delay in a time period between when any of the groups of instructions is ready to be dispatched for execution by the one or more execution units, and when the any of the groups of instructions is completely executed by the one or more execution units, a delay register configured to store at least one effective address of one of the instructions in one of the groups of instructions that is being executed, and a delay detector configured to detect when the one group of instructions is delayed in a time period between when the one group of instructions is ready to be dispatched for execution by the one or more execution units, and when the one group of instructions is completely executed by the one or more execution units, the delay detector being further configured to: start the delay counter in response to detecting that the one group of instructions is delayed, stop the delay counter in response to detecting that the one group of instructions is no longer delayed, compare the number of cycles counted by the delay counter with the threshold number of cycles in the threshold register, and store at least one effective address of one of the instructions of the one group of instructions when the number of cycles counted by the delay counter is greater than the threshold number of cycles stored in the threshold register.