1. A multiple stage branch prediction system comprising: a first stage, the first stage including a branch target address cache (BTAC), the first stage configured to store a BTAC entry corresponding to a branch instruction; a second stage, the second stage configured to: store an entry associated with the branch instruction; and modify state information corresponding to the entry, wherein the state information is modified after the branch instruction is fetched and before the branch instruction is resolved; and a logic circuit configured to manage the BTAC entry based on the modified state information.