1. An apparatus for processing a series of instruction groups containing a sequence of compiled instructions for parallel execution, comprising: buffer means for receiving a series of instruction groups, each group containing a sequence of compiled instructions; categorization means responsive to the sequence of compiled instructions of each instruction group for: determining whether at least two adjacent instructions of the sequence of compiled instructions belong to predetermined categories of instructions; and providing first signals conditioned to indicate to which predetermined categories the at least two adjacent instructions of the sequence of compiled instructions belong; interlock means responsive to the sequence of compiled instructions for providing second signals conditioned to indicate whether interlocks exist between the at least two adjacent instructions of the sequence of compiled instructions; compounding signal means connected to the categorization and interlock means and responsive to the first and second signals for providing a compounding signal to indicate whether the at least two adjacent instructions of the sequence of compiled instructions belong to instruction categories compatible for execution in parallel and are interlock-free prior to an instruction fetch and decode cycle for instruction execution of said each instruction group during which cycle timing and selection of instructions for execution is determined; and storage means connected to the compounding signal means for receiving a plurality of compounding signals for the sequence of instructions and for storing instructions which are grouped for concurrent execution.