1. An automated method, implemented as design verification software running on a computer system, for formally verifying a set of properties expressing intended logic behavior of an integrated circuit, the method comprising: receiving, by a data storage accessible to a processor, a description of at least a portion of an integrated circuit design to be formally verified, a set of properties of the design to be verified and a corresponding set of constraints for the properties, wherein each property defines a sequence of states from a given initial state to a specific state, the sequence to occur under conditions specified by the corresponding constraints and further subject to a cycle requirement; and analyzing the description by the processor with respect to each property determining reachability of the specific state from the given initial state under the conditions specified by the corresponding constraints, comprising: starting a sub-design from the received description in the given initial state, the sub-design being a portion of the integrated circuit for which the given initial state and the specific state are defined; determining whether the sub-design can reach the specific state from the given initial state via the sequence of states under the specified conditions in a number of cycles that violates the cycle requirement; a) if the specific state is so reachable in a number of cycles that violates the cycle requirement, reporting a failure of that property for the sub-design and the given initial state, and b) otherwise, reporting a pass of that property for the sub-design and the given initial state; if a spurious failure of the analysis is reported, identifying invariant signals from the set of conditions leading to the spurious failure; adding a constraint corresponding to the identified invariant signals; and re-analyzing with the added constraint until reachability is determined.