1. A computer implemented method for critical area computation of defects in VLSI circuit manufacturing comprising the steps of: a) retrieving a design layer containing a plurality of design shapes; b) retrieving a list of defect sizes ordered in increasing size; c) determining seed critical regions for said design layer; d) listing said determined seed critical regions in an ordered list in order of increasing critical radius; e) identifying all seed critical regions having a critical radius less than a minimum defect size and removing each said identified seed critical region from said ordered list; and f) generating an actual critical region for each said identified seed critical region.