1. An integrated circuit comprising: a packet buffer memory that stores an amount of packet data, wherein the packet data stored in the packet buffer memory is a plurality of bytes of packet data; a packet portion request bus system; a packet portion data bus; and a plurality of processors, wherein each processor comprises: a decode stage; a register file read stage comprising an intelligent packet data register file, wherein the intelligent packet data register file cannot store all of the amount of packet data that is stored in the packet buffer memory; and an execute stage, wherein the intelligent packet data register file initiates a prefetching of a packet portion from the packet buffer memory by causing a packet portion request to be sent across the packet portion request bus system to the packet buffer memory such that in response packet data is communicated from the packet buffer memory via the packet portion data bus and is loaded into the intelligent packet data register file, wherein the sending of the packet portion request occurs at a time that precedes an execution by the processor of an instruction that requires the packet portion data to be supplied by the intelligent packet data register file to the execute stage, and wherein there is only one packet buffer memory that is shared by the plurality of processors.