1. A computer-implemented method for constructing a spanning tree in an integrated circuit design comprising: receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design, wherein the plurality of nodes are configured to be intercoupled by one or more combinations of edges; receiving a user-specified floating parameter at a graphical user interface; generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-specified floating parameter and the position of each of the plurality of nodes; generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph; and applying the spanning tree in the electronic design of an integrated circuit to be fabricated.