1. A method of generating a circuit layout of an integrated circuit, the method performed by a hardware controller, the method comprising: generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit, wherein the predetermined portion of the integrated circuit comprises at least a multi-finger transistor; generating a consolidated netlist by combining the original netlist and the layout geometry parameters; replacing a description for modeling the multi-finger transistor with a description for modeling a plurality of single-finger transistors; and generating the circuit layout based on the consolidated netlist.