1. A vector processing device in combination with a main memory for storing vectors as stored vectors, said vector processing device comprising: a plurality of vector registers each for holding a vector, a plurality of vector operation means for carrying out a vector operation based on operand vectors to produce a result vector, input selecting means for selecting one of said vector registers as a destination register and for selecting one of said stored vectors or said result vector as a load vector to load said destination register with said load vector wherein said selected stored vector or said selected result vector is loaded into said selected vector register, output selecting means for selecting one of the vectors held in said vector registers as a store vector for storage in said main memory, means for fixedly coupling said vector registers to inputs of said plurality of vector operation means so that one of said vector operation means is coupled to receive outputs only from a first plurality of said vector registers and a second one of said vector operation means is coupled to receive outputs only from a second plurality of said vector registers which is different from said first plurality of vector registers wherein said operand vectors specify at least an operation code and the destination register without specifying source registers for said plurality of vector operation means, and wherein said vector processing device further comprises selecting means for selecting one of said vector registers as a source register, a plurality of vector memories, memory selecting means for selecting one of said vector memories as a selected memory, and vector moving means for moving the vector held in said source register to said selected memory for storage therein as a retained vector.