1. A processor comprising: a core configured to execute a data cache block write instruction; and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate; wherein the core is configured to transmit a request to the interface unit in response to the data cache block write instruction, and wherein the interface unit is configured to issue a first transaction on the interconnect responsive to the request being speculative, and wherein the interface unit is configured to issue a second transaction on the interconnect responsive to the request being non-speculative, and wherein the second transaction is different from the first transaction.