1. A multicore processor having an interconnect system, the system comprising: a plurality of resources having data for supporting the execution of multiple code sequences; a plurality of partitionable engines for implementing the execution of the multiple code sequences; a plurality of resource consumers within each of the plurality of partitionable engines; a global interconnect structure for coupling the plurality of resource consumers with the plurality of resources to access the data and execute the multiple code sequences, wherein the resource consumers access the resources through a cycle by cycle utilization of the global interconnect structure, wherein the global interconnect structure comprises a routing matrix of transmission lines that allows the plurality of resource consumers to access data from any storage location within the plurality of resources, wherein the system further includes a plurality of local interconnect structures that enable adjacent partitionable engines to directly access data from adjacent resources; and a plurality of schedulers operable to schedule a resource for transfer through the global interconnect structure to a resource consumer.