1. A computer implemented method for throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory, the method comprising: executing, by the processor, instructions of a transaction comprising: executing non-memory instructions without engaging speculation throttling, wherein speculation throttling reduces the number of speculative transactional executions; identifying a first set of memory instructions within the transaction, wherein the memory instructions must be executed in a particular order; based on identifying a first set of memory instructions within the transaction, engaging speculation throttling; identifying a second set of memory instructions within the transaction, wherein the memory instructions must be executed out-of-program order; and based on identifying a second set of memory instructions within the transaction, executing the second set of memory instructions without engaging speculation throttling.