1. An instruction supplier for supplying instructions in sequence to a microprocessor comprising: an instruction memory unit for storing instructions corresponding to instruction addresses; an instruction register for temporarily storing therein an instruction read out from said instruction memory unit in accordance with an inputted instruction address; an error causing instruction memory means for storing therein at least one error causing instruction for causing a functional error operation to occur in said microprocessor if the error causing instruction is executed at this point in the sequence of instructions; at least one comparison means for detecting whether or not at least one error causing instruction stored in said error causing instruction memory means agrees with the instruction stored in said instruction register, respectively, by comparing at least portions of said two stored instructions, and for outputting an agreement detection signal, said agreement detection signal being at a first level when said comparison means has detected that at least one error causing instruction stored in said error causing instruction memory means agrees with the instruction stored in said instruction register and said agreement detection signal being at a second level which is different from said first level when said comparison means has detected that at least one error causing instruction stored in said error causing instruction memory means fails to agree with the instruction stored in said instruction register; an instruction generation means for generating at least one specific instruction in accordance with the agreement detection signal outputted from said comparison means being at said first level; and an instruction selection means for selecting and outputting the instruction stored in said instruction register to said microprocessor in response to the agreement detection signal being at said second level, and for selecting and outputting the specific instruction generated by said instruction generation means to said microprocessor in response to the agreement detection signal being at said first level, thereby preventing any functional error operation from taking place in said microprocessor.