1. A reconfigurable processor comprising: a plurality of processing elements (PEs); a memory configured to store instructions, wherein when executed by a processor, said instructions implement: a designation unit configured to designate at least one of the PEs as a vector lane, based on vector lane configuration information, and an allocation unit configured to allocate a vector operation to the designated vector lane; wherein the vector lane configuration information includes: a number of vector lanes, a number of PEs included in each of the vector lanes, a number of PEs included in each of the vector lanes and that also include a particular function unit, a number of PEs included in each of the vector lanes and that also include a load/store unit, and a connection status between the PEs in a vector lane.