1. An apparatus, comprising: a multicore processor including a plurality of processing cores, a plurality of memory management units, and a plurality of peripheral access management units, each of the processing cores operating exclusively with only one of the memory management units and each of the processing cores operating with one or more of the peripheral access management units; at least one cache shared by the plurality of processing cores; and a separation kernel executing within each of the plurality of processing cores, the separation kernel configured to enforce the static virtual address mappings forming isolated memory domains within a shared system memory, wherein the apparatus is configured to isolate at least two domains within shared data storage including the shared system memory based on the static virtual address mappings, to operate at least a first of the processing cores with one of the two domains, and to separately operate at least a second of the processing cores with the other of the two domains.