1. A processor comprising: instruction hardware to receive a plurality of instructions, including an instruction to enter a virtual machine; control logic to determine, in response to a first exception occurring within the virtual machine operating according to a first configuration of a virtual machine control structure, to cause an exit from the virtual machine to a virtual machine monitor outside the virtual machine, and to determine, in response to the first exception occuring within the virtual machine operating according to a second configuration of the virtual machine control structure, to generate a second exception instead of an exit from the virtual machine; and execution hardware to generate the second exception in response to the control logic determining to generate the second exception and to respond to the second exception with a transfer of execution control within the virtual machine.