1. An apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function, comprising: a processor configured to implement: a compiler, providing native software transactional memory (STM) support, to identify demarcations of atomic blocks of the software and to generate, based on the atomic blocks, assembly code annotated with STM functions; and a shim layer to implement the STM functions using corresponding hardware transactional memory instructions and any necessary additional code to make the HTM instructions compatible with the STM functions, wherein the STM functions include transaction boundary demarcation and memory barriers.