1. A processor comprising: first logic to maintain a history table comprising a plurality of entries, each entry in the history table associated with an instruction executed by an execution unit of said processor and including history data indicating prior hits and/or misses to a cache level of a cache memory and/or a translation lookaside buffer (TLB) for said instruction, the history table is indexed by an instruction pointer address associated with each instruction executed by said processor, wherein maintaining the history table comprises updating the history table with data from instructions in a reorder buffer (ROB) and/or from one or more miss status holding registers (MSHRs) of said processor; and thread selection logic to select a particular thread for execution at a particular processor pipeline stage based on the history data.