1. A processing unit comprising: a plurality of element processors capable of communicating with an external memory via a single memory port, each element processor having a logic unit, an arithmetic unit, and a register file for storing parameter data, and each processor performing an operation on data from the external memory and the parameter data in accordance with an instruction that is common to all element processors; and a control processor for broadcasting the common instruction and addresses for each element processor to access the parameter data to the plurality of element processors to operate the plurality of element processors; wherein at least two of the plurality of element processors pre-receive the parameter data to be used for the operation, wherein the parameter data in one element processor differs from the parameter data in another element processor; store the parameter data in the register files in the respective element processors; upon receiving the common instruction that has been broadcast for the operation by the control processor, read the data from the external memory via the memory port, wherein the data from the external memory is common to all element processors; and perform at least one of logic computation and arithmetic computation in accordance with the common instruction, with respect to the common data and the parameter data that differs among element processors and is stored in respective register files, wherein the plurality of element processors are grouped into groups, each including at least two element processors and having a shared memory, and wherein a mode for reading from the shared memories to the external memory includes a random access mode and a reading mode that involves reduction across multiple groups, a mode for writing from the external memory into the shared memories includes a mode for broadcasting to a plurality of element processors and a mode for randomly accessing and transferring to an individual element processor, and a mode for writing from the external memory into the register files includes a first broadcast mode for broadcasting to all element processors in a group and a second broadcast mode for broadcasting to element processors in multiple groups.