1. An apparatus comprising: a central processing unit for executing instructions; memory for storing data; a system bus for transmitting data between the memory and the central processing unit, the system bus having a first ordering policy for the transmission of data thereon; a processor bus coupled to the processor for transferring data, the processor bus having a second ordering policy for the transmission of data thereon; a cache, coupled between the processor bus and the system bus, for receiving and transmitting data between the processor and memory according to the first and second ordering policies, the cache comprising: a plurality of units each one being assigned to a class of operations; an intraclass ordering means for maintaining the order of operations within a class; and an intraclass ordering means for maintaining the order of operations in one class with respect to another different class.