1. A method for implementing an indirect addressing mode to access memory of a graphics processing unit (GPU), comprising method operations of: receiving a first signal through a first pin of the GPU, the first signal indicating selection of the GPU; receiving a second signal through a second pin of the GPU, the second signal indicating a memory access request for a memory region of the GPU; and toggling a third signal communicated through a third pin between a first state and a second state, the first state representing address information being sent for the memory access and the second state representing data being sent for the memory access.