1. A method for performing an add-compare-select butterfly operation for implementing a Viterbi decoder in a processor having an XY memory and extension arithmetic logic unit (ALU) associated therewith, comprising: disposing old path metrics in said XY memory; providing a single operand add-compare-select (ACS) instruction within the instruction set of said processor, said instruction having at least one short immediate (shimm) data field; providing said old path metrics as inputs to said extension ALU; controlling at least a portion of the operation of said extension ALU using said at least one shimm field; and providing at least one addressing mode for said XY memory that allows new path metrics to be written back to XY memory subsequent to execution of said ACS instruction.