1. A circuit that detects and handles fetch-exceptions for a microprocessor without slowing down the normal operation of said microprocessor, comprising: an exception circuit that monitors fetch-addresses generated by an execution unit of said microprocessor, and that performs fetch-exception checks on said fetch-addresses before said fetch-addresses are used by said microprocessor to fetch instructions from a memory, said exception circuit generating one or more fetch-exception status bits for each instruction byte of said instructions; an instruction buffer that receives and stores said instructions fetched by said microprocessor, and that receives and stores said fetch-exception status bits corresponding to said instruction bytes of said instructions, said instruction bytes and said corresponding fetch-exception status bits being held by said instruction buffer until said instructions are executed; and an instruction control unit that receives said instruction bytes and said corresponding fetch-exception status bits, and that generates micro-instructions based on said instruction bytes and said corresponding status bits, said micro-instructions causing exceptions to be taken by said microprocessor when said fetch-exception status bits indicate a fetch-exception condition.