1. An array-type computer processor including a data-path unit and a state control unit, said data-path unit including a plurality of processor elements and a plurality of switch elements, which are arranged in a matrix, said processor element performing each of data processes according to an instruction code which describes the data in a computer program for each of a plurality of operation states which are sequentially transferred, said switch element switching and controlling each of connections between a plurality of said processor elements according to said instruction code, and said state control unit sequentially transferring a context of said instruction code for each of said operation states of said data-path unit, for each of said operation states according to said instruction code and a properly inputted event data, wherein said array-type computer processor further comprises code-obtaining means for obtaining data of a predetermined number of cooperative partial instruction codes of said operation states along with cooperative partial instruction codes of said contexts, from an external program memory which stores data of said computer program, said state control unit operates with temporarily holding only a predetermined number of instruction codes of said operation states whose data are obtained, and said data-path unit operates with temporarily holding only a predetermined number of instruction codes of said contexts whose data are obtained, and every time said state control unit and said data-path unit complete their operations with said temporarily-held instruction codes, said code-obtaining means obtains data of said instruction codes of subsequent said operation states and said contexts.