1. An integrated circuit (IC) supporting non-electrically-programmable three-dimensional memory (NEP-3DM)-based self-test (NEP-3DMST), comprising a substrate circuit, said substrate circuit further comprising a circuit-under-test (CUT) and a peripheral circuit; and, at least an NEP-3DM level stacked on said substrate circuit, at least a portion of said NEP-3DM level storing at least a portion of test data and/or test-data seeds for said CUT and being connected with said peripheral circuit through a plurality of inter-level connecting vias.