1. A computer-implemented method for design analysis comprising: identifying a cell and multiple instances of the cell from a semiconductor design including a plurality of cells and a plurality of virtual hierarchical levels; loading virtual hierarchical layer (VHL) data based on the cell; obtaining a virtual cell model, representative of the cell; determining interactions, between data within the cell and the VHL data, and selecting relevant portions of shapes based on the determining; and reducing an amount of data within the virtual cell model based on the interactions which were determined.