1. A multi-core processing unit disposed on an integrated circuit device, the multi-core processing unit comprising: first and second processing cores disposed adjacent to one another in the multi-core processing unit; a first floating point execution unit disposed in the first processing core; a first non-pipelined execution sequencer disposed in the first floating point execution unit, the first non-pipelined execution sequencer configured to execute at least one non-pipelined instruction selected from the group consisting of a multiply instruction, a divide instruction and a square root instruction; a second floating point execution unit disposed in the second processing core; a second non-pipelined execution sequencer disposed in the second floating point execution unit, the second non-pipelined execution sequencer configured to execute at least one non-pipelined instruction selected from the group consisting of a multiply instruction, a divide instruction and a square root instruction; first control logic disposed in the first floating point execution unit and configured to selectively issue a non-pipelined instruction to the second non-pipelined execution sequencer in the second floating point execution unit in response to determining that the first non-pipelined execution sequencer is busy and determining that the second non-pipelined execution sequencer is idle; and second control logic disposed in the second floating point execution unit and configured to selectively issue a non-pipelined instruction to the first non-pipelined execution sequencer in the first floating point execution unit in response to determining that the second non-pipelined execution sequencer is busy and determining that the first non-pipelined execution sequencer is idle.