1. An apparatus, comprising: a decoder to decode an instruction; execution circuitry to execute the decoded instruction using a plurality of compare-and-exchange circuits coupled to network circuitry to implement a vector sorting tree, each of said compare-and-exchange circuits having a respective comparison circuit that compares a pair of inputs, each of said compare-and-exchange circuits having a first output for presenting a higher of the two inputs and a second output for presenting a lower of the two inputs, said comparison circuit to also support said functional unit's execution of a prefix min and/or prefix add instruction.