1. A computer implemented method for optimized mapping of an integrated circuit package design, the method comprising: using at least one processor to perform a process, the process comprising: forming a preliminary assignment of nets based at least in part on a priority order, in which the preliminary assignment assigns a first circuit component from a source set of a net to a second circuit component of a destination set of the net; altering the preliminary assignment through introducing randomness in assigning the source set to the destination set of the net to refine the preliminary assignment; committing a final assignment from the action of refining as a final net assignment; and displaying the final net assignment on a display apparatus or storing the final net assignment on a non-transitory computer readable medium.