1. A memory device comprising: an array of memory cells; and control circuitry, coupled to the array of memory cells, wherein the control circuitry is adapted to operate in a plurality of read modes each mode selectable by a received read mode control command, the read modes comprising: a page read mode; and a page segment read mode, wherein the page segment read mode reads a segment of memory cells comprising a subset of memory cells read during the page read mode; wherein the control circuitry comprises a plurality of sense amplifiers, arranged into segments and coupled to a plurality of latch circuits such that a segment of memory read during the page segment read mode can be associated with any one segment of the plurality of sense amplifiers.