1. A method of processing instructions in a processor core, the method comprising: examining, by predecode logic, instructions in an instruction stream of a processor to determine properties of the instructions; in response to an instruction in the instruction stream being a boundary instruction that is a last instruction before a cache boundary, determining, using the predecode logic, a last property of the last instruction; in response to another instruction in the instruction stream being a boundary instruction that is a first instruction after the cache boundary, determining, using the predecode logic, a first property of the first instruction; and indicating, using the predecode logic, the last property of the last instruction and the first property of the first instruction to facilitate decode-time instruction optimization grouping of the last instruction and the first instruction in a single decode-time instruction optimization group.