1. In a memory subsystem having a plurality of buffer chips with different access latencies associated with retrieving memory data from memory components associated with the buffer chips, a memory controller comprising: logic for retrieving a return time vector for a received data request from a table of return time information; and logic for deterministically selecting a next request to schedule to begin executing at a next scheduling cycle based on a data return time vector for that next request compared with a history vector of currently executing requests, wherein said next request is a request that does not provide a data bus conflict with the currently executing requests and which results in maximum usage of data bus bandwidth between the buffer chips and the memory controller.