1. A system for accessing common registers in a register domain in a multi-core processor, comprising: core logic provided at each of a plurality of processing cores in a core domain, the core logic streaming at least one transaction from the core domain to the register domain, wherein both the core domain and the register domain are different clock domains in the same multi-core processor; and bus interface logic in the register domain, the bus interface logic reassembling the at least one streamed transaction for data access operations at the common registers.