1. A method comprising: decoding a single instruction with a hardware decoder of a hardware processor; and executing the single instruction with a hardware execution unit of the hardware processor by: receiving a vector element multiplicand and vector element multiplier expressed in a first base system; converting said vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying said converted vector element multiplicand and said converted vector element multiplier to form a multiplication result; accumulating in a register a portion of said multiplication result with a portion of a result of a prior multiplication of operands expressed in said second lower base system; and converting contents of said register into said first base system.