1. A method for fabricating a multi-level memory array comprising, for each of at least two adjacent levels, the steps of: depositing at least one metal layer; forming at least one layer of a first conductivity type organic polymer for both even-numbered levels and odd-numbered levels; masking and etching the polymer and metal layers to define a plurality of parallel, spaced-apart rail-stacks running in a first direction for even-numbered levels and running in a second direction for odd-numbered levels; filling the space between the rail-stacks with a dielectric material; planarizing the polymer layer and the dielectric material to form a planarized surface, and forming a polymer layer having a variable resistance on the planarized surface.