1. A microprocessor architecture comprising: a microprocessor including a plurality of registers that are internal to the microprocessor, the microprocessor arranged to execute a plurality of instructions that each use a respective first operand of a first operand class, and a respective second operand of a second operand class, each instruction of the plurality of instructions having a respective opcode that comprises: a first field that indicates whether a first register address where its first operand is stored is to be determined using absolute addressing or using relative addressing with respect to an address of a previously accessed register of the first operand class; and a second field that indicates whether a second register address where its second operand is stored is to be determined using absolute addressing or using relative addressing with respect to an address of a previously accessed register of the second operand class.