1. A method comprising: receiving a plurality of instructions, wherein said plurality of instructions comprises a first vector instruction and a second vector instruction, and execution of said second vector instruction depends on an execution result of said first vector instruction, executing said first vector instruction utilizing a processor functional unit, wherein said processor functional unit comprises a pipelined execution unit; determining a forwarding order of a first portion of said execution result and a second portion of said execution result in dependence on a parity of a clock signal applied to said processor functional unit at the time said first vector instruction was received, wherein said determining comprises determining said forwarding order utilizing a single-bit binary counter to identify said parity of said clock signal upon receipt of said first vector instruction; and forwarding said first portion of said execution result and said second portion of said execution result from an output coupled to said pipelined execution unit to an input coupled to said pipelined execution unit according to said forwarding order, wherein said forwarding comprises: forwarding said first portion of said execution result prior to forwarding said second portion of said execution result in response to a determination that said parity of said clock signal upon said receipt of said first vector instruction is even, and forwarding said second portion of said execution result prior to forwarding said first portion of said execution result in response to a determination that said parity of said clock signal upon receipt of said first vector instruction is odd.