1. A programmable logic device (PLD) comprising: a plurality of logic elements coupled together by an interconnect network, each one of said plurality of logic elements including a plurality of memory cells for storing configuration data, said plurality of memory cells forming a serial chain coupled together via access transistors; a configuration data line coupled to said serial chain of memory cells, data being transferred from memory cell to memory cell in said chain via said access transistors; a plurality of partial reconfiguration (PR) data lines corresponding to said plurality of memory cells; and a plurality of data injection transistors respectively coupling said plurality of memory cells to said corresponding plurality of PR data lines.