1. A memory hub, comprising: a memory access device interface structured to interface with a memory access device; and a plurality of memory interfaces coupled to the memory access device interface, the memory interfaces each structured to interface with respective memory devices, each of the memory interfaces comprising: a memory controller; a cache memory; and a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and, without receiving external command and address signals, to cause the memory controller in the respective memory interface to output signals indicative of a memory read operation from the predicted address.