1. A hardware-reconfigurable digital filter having multiple filtering modes, comprising: logic circuitry adapted to process data corresponding to input data, the logic circuitry including an X-by-Y array of registers for supporting at least one first filtering mode using the registers arranged linearly and for supporting at least one second filtering mode using the registers arranged nonlinearly, wherein each of X and Y is at least 2; computational circuitry adapted to perform computations responsive to the logic circuitry and including at least Y multiplication logic circuits and at least Y addition logic circuits; and mode selection circuitry adapted to switch the digital filter between the multiple filtering modes.