1. A testcase checker system, comprising: a processor; and a computer readable medium, the computer readable medium comprising instructions to be executed by the processor, the instructions include: an instruction set simulator configured to simulate execution of each instruction of a sequence of instructions of a testcase on a microprocessor, wherein simulating the execution of each instruction includes using a reference model associated with an architecture of the microprocessor, and to generate logging data associated with each instruction of the sequence of instructions based on the simulated execution of that instruction; and a checker module comprising a set of rules, wherein each rule is associated with a boundedly undefined condition and the checker module is configured to receive the logging data associated with each instruction from the instruction set simulator and to process the logging data associated with each instruction based on each rule to determine if each rule is violated.