1. A driving waveform circuit including a crossbar array having input columns and output rows wherein the crossbar array is configured to store data in the form of high or low resistance states; delay timing circuitry electrically connected to the input columns of the crossbar array and configured to provide a relative delay timing between input signals of each input column; and summation circuitry electrically connected to the output rows of the crossbar array for generating one or more output signals based on the stored resistance state data and the input signals.