1. An apparatus comprising: a plurality of vector registers; and execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to: receive a first vector instruction to update a liner feedback shift register (LFSR) for stream cipher operations, wherein the first vector instruction specifies two or more of the plurality of vector registers as operands; receive a second vector instruction to update a state of a finite state machine (FSM), wherein the FSM receives inputs from re-ordered bits of the LFSR, and wherein the second vector instruction specifies two or more of the plurality of vector registers as operands; and execute the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.