1. A single built-in self-test device for testing a plurality of memories, at least two of which have different characteristics and require different test patterns, comprising; logic to generate test data in pre-selected test patterns specific to each type of memory and anticipated output compare data corresponding to said test data, logic to convey said test data to at least two of said memories simultaneously, logic to supply the address of the locations of said memory to be tested with said test data; logic to receive output data from said memory location and compare said output data with said anticipated output compare data to provide a comparison; control logic including; write enable logic to selectively cause a write function of said test data on each said memory at each addressable location thereon to be tested; and logic to selectively load the results of said comparison at each addressable location thereon to be tested.