1. A method of testing memory designs comprising: identifying potential defects in a memory cell; defining a circuit for the memory cell, the circuit including resistance values indicative of the identified potential defects; providing an assist circuit, the assist circuit reducing voltage for detecting resistive-open or resistive-bridging defects in the memory cell, the assist circuit introducing a resistive value into the circuit for reducing voltage at predetermined points in a testing phase; and activating the assist circuit during a test cycle for detecting a resistive value corresponding to a defect.