1. A method for verifying equivalent logic circuits respectively having different clocking configurations, different types of storage elements, and different descriptive languages, the method comprising: a) comparing with a computer a first logic circuit having a first clocking configuration and a first descriptive language against a second logic circuit having a second clocking configuration and a second descriptive language, the first and second logic circuit each having different descriptive languages from each other, and the first and second logic circuit each having different clocking configurations from each other; b) based on results of said comparison, creating first and second wrappers respective to said first and second logic circuits, matching said first clocking configuration to said second clocking configuration; and c) equalizing said first and second wrappers of said first and second logic circuits, said equalization being performed without affecting the respective storage elements.