1. A semiconductor device comprising: a first memory that stores a plurality of instructions; a second memory that stores a plurality of data items; a first bus and a second bus; a microprocessor that fetches, through the first bus, an instruction at a specified address among the plurality of instructions stored in the first memory, executes the instruction, and accesses the second memory through the second bus based on a result of the execution; and a trace information output unit that acquires, when a branch instruction is generated in the microprocessor, address information of the first memory specified before branching, and outputs the address information as trace information, wherein the trace information output from the trace information output unit is written into the second memory through the second bus in a period in which the microprocessor does not access the second memory during execution of the branch instruction.