1. A processor, comprising: a processor core including circuitry to execute a translated instruction, the translated instruction translated from an instruction stored in a memory location; a translation lookaside buffer (TLB) including circuitry to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and a translation indicator agent (XTBA) including circuitry to determine whether the TLB indicates whether the memory location has been modified subsequent to translation of the instruction.