1. An integrated circuit (IC) having a digital signal processing (DSP) circuit, the DSP circuit comprising: a plurality of multiplexers receiving a first set, second set; and third set of input data bits, the plurality of multiplexers coupled to a first opcode register; a first bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, the second adder coupled to a second opcode register.