1. A resistive memory device fabricating method, comprising: providing a substrate which has an active region, a front end circuit being formed in the active region, and the front end circuit having a plurality of conductive channels arranged as an array; forming a plurality of bottom electrodes in the active region, each of the bottom electrodes being disposed to correspond to each of the conductive channels; forming a patterned sacrificial layer on the substrate, the patterned sacrificial layer covering the bottom electrodes and having a plurality of openings, each of the openings being disposed to correspond to each of the bottom electrodes and exposing a part of each of the bottom electrodes; sequentially forming a resistance switching material layer and a top electrode layer on the patterned sacrificial layer, wherein the resistance switching material layer and the top electrode layer fill the openings; removing the top electrode, the resistance switching material layer, and the patterned sacrificial layer outside the active region; forming a conductive layer on the substrate; patterning the conductive layer, the top electrode, and the resistance switching material layer, so as to form a plurality of patterned interconnections by the conductive layer, and to expose a part of the patterned sacrificial layer; and providing a reactant to react with the patterned sacrificial layer and remove the patterned sacrificial layer, so as to form an air dielectric layer disposed at an original position of the patterned sacrificial layer.