1. An integrated circuit comprising: A. a TDI/TMS input lead; B. a TCK input lead; C. a TDO output lead; D. double data rate circuitry having an input coupled to the TDI/TMS input lead, an input coupled to the TCK input lead, and separate TDI and TMS output leads; E. addressable TAP interface circuitry having: i. a TDI input coupled to the TDI output lead; ii. a TMS input coupled to the TMS output lead; iii. a TCK input coupled to the TCK input lead; iv. a TDO output coupled to the TDO output lead; v. a TDI output; vi. a TMS output; vii. a TCK output; and viii. a TDO input; and F. a TAP domain having: i. a TDI input coupled to the TDI output of the TAP interface circuitry; ii. a TMS input coupled to the TMS output of the TAP interface circuitry; iii. a TCK input coupled to the TCK output of the TAP interface circuitry; iv. a TDO output coupled to the TDO input of the TAP interface circuitry.