1. A programmable logic circuit comprising a plurality of logic elements, a plurality of interconnect means, and static configuration memory means for storing the configuration of the logic elements and interconnect means, wherein said static configuration memory means is formed and arranged to store a multiplicity of different configurations for each said logic element, the static configuration memory means and interconnect means further comprising decoders, programmable logic further comprising means for converting a system clock signal to be applied to the programmable logic circuit into a modified clock signal comprising a predetermined number of sub-cycles for each system clock cycle.