1. A memory architecture comprising: a plurality of transistors arranged to form a bit cell, said bit cell comprising a first transistor, a second transistor, a third transistor and a fourth transistor configured to store a bit of data; a fifth transistor having a gate coupled to a Data Bar (DB) signal, said fifth transistor having a drain coupled to a drain of said first transistor and a Source coupled to an XW signal; a sixth transistor having a gate coupled to a Data (D) signal, a drain coupled to a drain of said third transistor and a source coupled to a source of said fifth transistor; a seventh transistor having a gate coupled to said drain of said sixth transistor, a source coupled to an XR signal and a drain coupled to an Read Bit Line (RBL) signal; and wherein said RBL line is precharged high and to perform a read of data from said bit cell said XR line goes low.