1. A heterogenous, high-performance, scalable processor comprising: at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value; at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W; Shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor; and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges bytes in transit to or from memory to accommodate execution of applications allowing for fast operations.