1. A prefetch circuit for fetching prefetch commands from a memory which includes registers arranged in pages having page frame numbers, said prefetech circuit comprising: real address storage means for storing the real address of a first register which is located in said memory, said real address containing a page frame number; virtual address storage means for storing the virtual address of said first register which is located in said memory, said virtual address containing a virtual page number; adder means having an input and an output, said adder means for adding an offset to an address on its input; virtual address bus means connected between said virtual address storage means and the input of said adder means, said virtual address bus means for transmitting said virtual address to the input of said adder means to obtain a new virtual address having a new virtual page number contained therein; comparator means connected to said real address storage means and the output of said adder means, said comparator means including an output having a first state when a least significant portion of the page frame number contained in said real address is the same as a least significant portion of the new virtual page number contained in said new virtual address, and a second state when the least significant portion of the page frame number contained in said real address is not the same as the least significant portion of the new virtual page number contained in said new virtual address; real address bus means connected between said real address storage means and the input of said adder means, said real address bus means for transmitting said real address to said adder means to obtain a prefetch real address when the output of said comparator means is in its first state; and fetch means connected between the output of said adder means and the memory for fetching a prefetch command from a second register in the memory at the location indicated by said prefetch real address.