1. An instruction execution method to simultaneously execute multiple instructions using a microprocessor, the method comprising: prefetching from a memory sets of instructions containing multiple instructions, the prefetching starting during a first processor cycle; storing at least one of the sets of instructions in a prefetch buffer; transferring the sets of instructions stored in the prefetch buffer to a multistage buffer when there is an extra space, the multistage buffer adapted to store multiple sets of instructions and in which the set of instructions is regarded as a unit; simultaneously decoding, during a processor cycle following the first processor cycle, the multiple instructions contained in a set of instructions stored at a predetermined position of the multistage buffer; checking, during a processor cycle after decoding, dependencies among the decoded multiple instructions based upon at least a condition of conflicting use of a register and, if it is determined that there is no restriction to execution based on dependencies, allocating the multiple instructions to one or more functional units, including at least one instruction to execute out of order; if there is extra space in the prefetch buffer due to transfers to the multistage buffer, continuing prefetching sets of instructions to the prefetch buffer regardless of post decoding processing; and during a processor cycle after executing the multiple instructions, advancing another set of instructions stored in the multistage buffer to the predetermined position for decoding.