1. A method for multi-domain timing analysis of a circuit design for an electronic circuit, the circuit design having a plurality of interconnected cells and a plurality of power domains therefor, the power domains establishing respective non-ground voltages provided by different power supplies, the method comprising: establishing a netlist defining the cells of the circuit design, a plurality of timing paths each being defined to traverse at least one of the cells of the circuit design; executing a processor to selectively determine at least one of the timing paths to be an inter-power domain (IPD) timing path according to predetermined IPD criteria, the IPD criteria including traversal by a timing path through at least one multi-supply element, each multi-supply element including one or more cells energized by multiple power domains; and, executing a processor to selectively actuate at least one multi-domain timing analysis based on an IPD netlist collectively designating each said IPD timing path, wherein the circuit design is altered to correct at least one timing violation detected by the multi-domain timing analysis, and wherein the electronic circuit is manufactured based on the altered circuit design.