1. A system for performing atomic counter operations in a memory storage device provided in a computer processing system including a processor device that issues physical memory addresses for accessing a memory location in a memory storage device, said system comprising: means for receiving said physical memory address from an issuing processor, said physical memory address including embedded instruction bits, said embedded instruction bits representing an operational code for specifying an atomic counter operation to be performed at a memory location; and, means for removing said instruction bits from said received memory address to form a further memory address used in selecting said memory address location in said memory storage device, wherein an atomic counter operation is to be performed at said further memory address according to said instruction bits, wherein said physical memory address from an issuing processor further includes one or more bits to further designate contiguous sets of counters in said memory storage device, each counter allocated for performing said atomic counter operations.