1. A programmable logic cell comprising: a plurality of circuit sections each having a threshold alterable transistor; a plurality of bit lines, at least one such bit line respectively connected to each said circuit section for altering the programming threshold of said transistor; a plurality of input lines connected to said cell for receiving input logic signals; at least one output line connected to said cell for transferring an output logic signal from said cell; and a plurality of driver transistors including at least one driver transistor associated with each threshold alterable transistor, each such driver transistor providing the output signals to said output line and being connected for buffering said threshold alterable transistor thereby reducing the current handling requirement of said threshold alterable transistor; the respective programming thresholds of said alterable transistors determining the Boolean logic function of said logic cell, the logic state of said output logic signal being dependent on said cell Boolean logic function and the logic states of said input logic signals, the logic cell having all possible Boolean logic functions for the number of said input signals.