1. A computer program product for determining, by a processor having a cache, whether data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment, the computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: executing, by the processor, a TM transaction, the execution comprising: reading a prefix instruction that indicates a cache line into which storage operands are loaded by a next sequential instruction following the prefix instruction is not marked as read-set cache lines of the TM transaction, wherein as a result of the prefix instruction not being marked as read-set cache lines of the TM transaction, the cache line is not monitored for cache coherency conflicts or considered in aborting the TM transaction by the processor, wherein the prefix instruction modifies a functionality of one or more subsequent instructions, and wherein the modification of the functionality of the one or more subsequent instructions depends upon an architecture of the prefix instruction; executing the next sequential instruction following the prefix instruction, wherein the next sequential instruction following the prefix instruction is a memory data access instruction that loads a storage operand into the cache line of the cache of the processor, the storage operand is associated with an operand tag comprising an indicator bit embedded in the cache that indicates the storage operand is not marked for monitoring; and based on the prefix instruction, not marking the cache line into which the storage operand is loaded as read-set cache line of the TM transaction.