1. A configurable arithmetic block in a device having programmable resources for implementing arithmetic functions, the configurable arithmetic block comprising: a plurality of input registers coupled to receive multiple bit words, wherein the plurality of input registers comprises a plurality of lookup tables; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled to the output selection circuit.