1. A processor having an interface portion and an internal environment, the interface: portion comprising at least one port and the internal environment comprising: an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal; wherein the at least one port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with the external environment, the thread scheduler being configured to schedule one or more associated threads for execution in dependence on the ready signal.