1. A low density parity check (LDPC) decoder, comprising: a memory configured to store a log-likelihood ratio (LLR) value of bits output from a demapper, and an LLR message exchanged between a variable node and an inspection node; and a node processor configured to select a decoding algorithm from a first algorithm and a second algorithm based on a code rate of an LDPC code, and decode the LLR message based on the selected decoding algorithm.