1. A computer-implemented method for performing compiler straight-line post-increment (SLPI) optimization for memory access instructions of a computer program, comprising: performing SLPI preparation on candidate memory access instructions to obtain an intermediate stream of code containing pseudo-memory instructions, each of said candidate memory access instructions representing a non-loop memory access instruction and employing an address that is computed based on the same base register shared by another instruction of said candidate memory access instructions; and performing SLPI synthesis on said intermediate stream of code to obtain architected memory instructions conforming to a base register auto-incrementing addressing mode.