1. An apparatus, comprising: a first register; a storage element; first logic coupled to the first register and the storage element, the first logic to store first data from an upper part of the first register into the storage element, responsive to detecting that a second instruction is executed next after a first instruction, wherein a lower part of the register is accessible to both the first and second instructions, and the upper part of the register is accessible to the first instruction but not to the second instruction; and said first logic to disable said storing the first data from the upper part of the first register into the storage element responsive to executing a third instruction.