1. A programmable logic device including a plurality of logic blocks and routing resources for transmitting signals between the blocks, a logic block comprising: a plurality of product term circuits each operable in logic mode to provide a product term at an output terminal and operable in memory mode to provide a data bit at the output terminal, each product term circuit including a first stage of configuration cells each operable in logic mode to store a configuration bit and operable in memory mode to store the data bit and a second stage of logic gates operable to combine signals passed from the first stage; and a mode select circuit operable in logic mode to select a source of input signals for the configuration cells and in memory mode to select a source of address signals for the configuration cells.