1. A comparator for determining the fidelity of a response vector output by a memory under test, comprising: a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of said response vector; a second logic gate configured to output a second value that is the logical NAND of said proper subset of bits; and a first multiplexer configured to select between said first and second values based on the value of a first bit of a check vector corresponding to said response vector.