1. A data processing apparatus comprising: processing circuitry configured to process a plurality of threads of processing in parallel; a shared instruction decoder configured to decode program instructions to generate micro-operations to be processed by the processing circuitry, the program instructions comprising at least one complex program instruction corresponding to a plurality of micro-operations; and a plurality of fetch units configured to fetch, for processing by the processing circuitry, the micro-operations generated by the shared instruction decoder, each fetch unit associated with at least one of the plurality of threads; wherein the shared instruction decoder is configured to generate each micro-operation in response to a decode request triggered by one of the plurality of fetch units; and the shared instruction decoder is configured to generate the plurality of micro-operations of a complex program instruction individually in response to separate decode requests each identifying which micro-operation of the complex program instruction is to be generated by the shared instruction decoder in response to the decode request.