1. A host device comprising: one or more processors; a command queue interface for execution by the one or more processors, wherein the command queue interface is configured to place a plurality of commands into a command queue in response to receiving one or more enqueue instructions from a process executing on the host device, the plurality of commands including a first command instructing the host device to transfer data between a first memory space associated with the host device and a second memory space associated with a graphics processing unit (GPU), the plurality of commands further including a second command instructing the host device to initiate execution of a task on the GPU; a message passing interface for execution by the one or more processors, wherein the message passing interface is configured to pass one or more messages between the process executing on the host device and the task executing on the GPU while the task is executing on the GPU and in response to receiving one or more message passing instructions from the process executing on the host device; and a memory buffer interface for execution by the one or more processors, wherein the memory buffer interface is configured to disable, via at least one register associated with a shared memory, caching services associated with the shared memory or a cache coherency mode associated with the shared memory to enable sharing of data between the process executing on the host device and the task executing on the GPU while the task is executing on the GPU, wherein the shared memory is accessible by the GPU and the host device.