1. Addressability definition control for a data processor for executing an address key register (AKR) load instruction for loading address keys into an address key register (AKR) from a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability definition control including a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key ingates separately connected to inputs of each of the key sections in the AKR, a multiple key ingate connected to inputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key ingates, and all of the single key signal lines also connected to the multiple key ingate, a control store decoder having as outputs single and multiple key ingate control lines for connecting control signals activated by microcode received from a control store to the respective ingates, the decoder activating one of the control lines selected by the instruction, means for outputting address signals from the instruction for selecting a general register or a main memory location containing required address key signals, means for connecting the selected general register or memory location to a processor data path, and any ingate control line activated by the decoder in response to the instruction to select any single key section or all key sections for transferring one or multiple address key signals into the AKR from the processor data path, which is currently connected to a selected general register or memory location to load the processor with one or plural addressabilities.