1. In a data processing system including a processor, a bulk memory for storing data or instructions and an accelerator memory for storing selected portions of said data or instructions for use by said processor, the improvement comprising: memory means for storing transformation coordinate signals indicative of the corresponding locations in said accelerator memory of said portions of said data or instructions; a current access register connected to receive and store the currently requested one of said transformation coordinate signals; a prior access register connected to said current access register for storing therein the previously requested one of said coordinate signals; a first and second multiplexer connected for concurrent cyclic selection of data inputs; a first and second link memory respectively receiving the output of said first multiplexer at the data input of said first link memory and at the address inputs of said second link memory and the output of said second multiplexer at the data input of said second memory and the address input of said first memory; a first and second output register respectively connected to receive output signals from said first and second link memory; and connecting means respectively feeding back the output signals from said first and second output registers and said current and prior access registers to said data inputs of said first and second multiplexer.