1. An integrated circuit that processes communication packets, the integrated circuit comprising: a core processor configured to create a plurality of external buffers that are external to the integrated circuit and configured to store the communication packets where each external buffers is associated with a pointer that corresponds to the external buffer; a pointer cache configured to store the pointers that correspond to the external buffers; control logic configured to allocate the external buffers as the corresponding pointers are read from the pointer cache and de-allocate the external buffers as the corresponding pointers are written back to the pointer cache wherein the control logic is configured to transfer an exhaustion signal if a number of the pointers to the de-allocated buffers reaches a minimum threshold; and the core processor configured to create additional external buffers and their corresponding pointers in response to the exhaustion signal.