1. In a computer design system for generating physical design descriptions for VLSI semiconductor circuit devices of the type including a matrix array of dual-row cell locations within a grid of first and second conductive lines extending in first and second orthogonal directions, a method for generating a circuit macro physical design description having a selected storage capacity, said circuit macro including at least one control block and at least one storage block and said control and storage blocks being variably configured in accordance with the selected storage capacity, said method comprising the steps of: identifying a selected number of words and a selected number of bits per word for the circuit macro; selecting one of a plurality of predetermined stored bit decoders for use in the circuit macro; identifying a required number of storage blocks for said selected number of bits per word responsive to said selected bit decoder; identifying a required number of columns for said selected number of words responsive to said selected bit decoder; identifying a required number of rows for said control block responsive to said identified number of columns; sequentially generating a first row of said control block including a first column of a space cell, next successive columns of word selector cells, and a last column of said selected bit decoder; sequentially generating a second row of said control block including said first column of an empty cell, said next successive columns of word address personalization cells, and said last column of an INPUT/OUTPUT cell; sequentially generating subsequent rows of said control block responsive to said identified number of rows including said first column of an empty cell, said next successive columns of word address personalization cells, and said last column of an empty cell; sequentially generating a row for each of said identified number of storage blocks including a first column of a space cell, next successive columns of memory array cells and a last column of an INPUT/OUTPUT cell.