1. A central processing unit for a pipelined computer, comprising: an instruction unit for receiving macroinstructions and decoding a first portion of a variable-bit macroinstruction containing a variable-length operand and for passing information determined from said decoding said first portion to an instruction queue, and for continued decoding of said variable-bit macroinstruction and subsequent ones of said macroinstructions after said passing of said information; means for loading said instruction queue with said information determined from said macroinstruction and for loading a field queue with information identifying said macroinstruction as including said variable-length operand and information of whether the variable-length operand is a register reference or a memory reference; an execution unit for beginning a sequence of microinstruction steps of execution of said macroinstruction based on said information in said instruction queue prior to or simultaneous with said continuing decode of said macroinstruction; and means operative at a decision point within said sequence of microinstruction steps of execution, for checking said information in said field queue to determine whether to execute a first sequence of steps to fetch said variable-length operand from a register or a second sequence of steps to fetch said variable-length operand from memory.