1. A computer processor configured to generate code simulating testing on an integrated circuit device, the processor being in communication with a user interface and a memory, the processor configured to execute: an environment builder that displays a graphical environment model on the user interface, the graphical environment model displaying a device under test graphic, a verification graphic, and at least one connection graphic connecting the device under test graphic and the verification graphic, the device under test graphic associated with source code that simulates an integrated circuit device, the verification graphic associated with source code that simulates a verification module, and the at least one connection graphic being associated with source code that simulates connection signals between the verification module and the integrated circuit device; a code generator that generates test simulation code that simulates operation of the integrated circuit device upon execution; and a navigation program that controls the display of source code associated with graphical environment model on the user interface, wherein the navigation program controls the level of detail of the graphical environment model displayed via the user interface in response to receiving a detail control input signal via the user interface, wherein the code generator is configured to generate a test simulation code in response to receiving an interface input signal, the test simulation code based at least in part on the source code associated with the verification graphic, the source code associated with the device under test graphic, and the source code associated with the at least one connection graphic, and wherein the test simulation code is generated in a format for execution on a simulator to simulate testing on the integrated circuit device.