1. A method, comprising: assigning paths of a routed circuit design to groups based upon clock domain; determining, using a processor, a baseline delay for a path of the routed circuit design, wherein the path belongs to a selected group; comparing using the processor, the baseline delay of the path with a timing constraint of the path; and generating a modified version of the circuit design that is functionally equivalent to the circuit design by selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using the processor; wherein the structural netlist optimization comprises modifying a configuration of at least one combinatorial circuit element in the path to perform a different operation; and wherein the circuit design is adapted to be implemented within an integrated circuit and the paths are processed in an order determined based upon the groups.