1. A method for executing instructions on a processor core implemented with a source operand collector cache coupled to at least one input of a data path residing within the processor core, the method comprising: decoding an instruction to determine a plurality of operands specified by the instruction; for each operand in the plurality of operands, determining that the operand is not stored in the source operand collector cache, loading the operand into the source operand collector cache from a local register file; and configuring the processor core to execute the instruction across the operands stored in the source operand collector cache.