1. A stacked memory device comprising: a memory stack including one or more memory die layers; and a system element coupled with the memory stack, the system element including: a memory controller for the memory stack, a built-in self-test (BIST) circuit to test the memory stack, and a generic data scrambler to scramble data for the testing of the memory stack, the scrambling of the data being performed according to a data scrambling algorithm for the memory stack, the data scrambling algorithm to provide mapping between logical locations and physical locations for data storage in the memory stack, the operation of the data scrambling algorithm being based at least in part on values of addresses for data, wherein the generic data scrambler includes: a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, the programmable lookup table to generate a set of data factors based on addresses of the data for testing of the memory stack, and a determination logic to combine the data for the testing of the memory stack with the data factors generated by the programmable lookup table to generate scrambled data; wherein the BIST circuit and generic data scrambler are operable to implement multiple different data scrambling algorithms to support mappings between logical addresses and physical addresses for different memory types.