1. A microprocessor, comprising: an array of re-configurable gate logic circuits; an array of re-configurable register logic circuits; a programmable switch network having operational connections to the elements of both the array of re-configurable gate logic circuits and the array of re-configurable register logic circuits; a memory circuit block comprising a plurality of cache memory circuits and a plurality of non-volatile memory circuits; a binary code decoder circuit block that performs, at run time, decoding, re-ordering, and parsing of sequences of binary encoded Complex Instruction Set Computer (CISC) type or Reduced Instruction Set Computer (RISC) type machine code instructions into newly generated sequences of binary code; a binary code converter circuit block that converts, at run time, the newly generated sequences of binary code into newly generated configuration bit map codes; and a constructer circuit block that configures, at run time, the array of re-configurable gate logic circuits and the array of re-configurable register logic circuits into at least one finite state machine through the use of the newly generated configuration bit map codes.