1. A data processing unit for a computer comprising: a register file; a register access and permute unit capable of accessing at least one data operand in said register file based on a single data access instruction, said register access and permute unit comprising permute circuitry operable to selectively permute said accessed data operand based on a permute opcode portion of said single data access instruction; and a data execution unit arranged in series with said register access and permute unit, said data execution unit being operable to perform an operation on said selectively permuted data operand based on an execution opcode portion of said single data access instruction.