1. A method for executing instructions using a plurality of virtual cores for a processor, comprising: receiving an incoming instruction sequence using a global front end scheduler; partitioning the incoming instruction sequence into a plurality of code blocks of instructions; generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks; allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines; and executing the code blocks by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.