1. The method of checking integrated circuit chips having data processing logic and error-checking circuitry on each chip, each chip having off-chip outputs connected in parallel with the off-chip outputs of one or more other chips, comprising: inputting data from substantially identical sources to the data processing logic on each chip; outputting data from said logic on each chip to its error-checking circuit and to its off-chip output; inhibiting the off-chip output of one of said chips so that said data does not reach said off-chip output; and connecting said off-chip output of each chip to its own error-checking circuit, so that data generated internally on said one chip may be checked with respect to data generated externally from the other chip.