1. A method of providing fault tolerance in a combinational circuit, the method comprising: identifying a plurality of sensitive gates of the combinational circuit that require protection from at least one of a first type of fault and a second type of fault; computing by circuitry, for each first type of transistor included in a sensitive gate, a first failure probability corresponding to the first type of fault, and for each second type of transistor included in the sensitive gate, a second failure probability corresponding to the second type of fault; calculating by circuitry, a first parameter corresponding to a number of the first type of transistors for which the computed first failure probabilities exceed a first predetermined threshold and a second parameter corresponding to a number of second type of transistors for which the computed second failure probabilities exceed a second predetermined threshold; determining, based on an area overhead of the combinational circuit and the calculated first parameter and second parameter, a protection type to be assigned to the sensitive gate of the combinational circuit; evaluating, based on the computing, the calculating, and the determining, a reliability factor of the combinational circuit; updating the combinational circuit based on the assigned protection type and area overhead to generate an updated combinational circuit having a different amount of transistors, the updated combinational circuit having enhanced fault tolerance.