1. A multiprocessor system having plural processor units including: a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units operate in page level granularity and a second mode in which at least one of said plural processor units operates in a lower granularity then that of first mode; and a setting circuit for classifying said plural processor units in the first mode into plural groups, each group containing at least one processor unit, to successively set said plural groups to the first mode in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the second mode in turn when said reception circuit receives a setting demand requesting the second mode, wherein said setting circuit determines the total granularity demand of said plural processor units when said reception circuit receives the setting demand requesting one of the first mode or the second mode and collectively sets the plural processor units to the normal state or the low granularity-demand state in accordance with the requested mode.