1. An apparatus comprising: processor cores; a smaller non-volatile memory; a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores; volatile memory to act as system memory for the processor cores; and power management logic to control at least some aspects of power management; wherein, in response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory.