1. A processor that includes one or more cores, at least one core of the one or more cores comprising: an instruction cache; and a pre-decode unit comprising logic that is executable by the processor to perform operations comprising: reading the first byte from the instruction cache using a logical instruction pointer that points to a first byte in the instruction cache; detecting whether the first byte includes a length of an instruction; and in response to detecting that the first byte includes the length of the instruction, reading the instruction from the instruction cache based on the length of the instruction.