1. A circuit comprising an intermediate stage comprising: a storage section comprising a first plurality of storage units and coupled to receive ciphertext blocks at an input, a calculation section coupled in parallel with said storage section comprising a second plurality of storage units, and a plurality of calculation units coupled in series, wherein each storage unit of said second plurality of storage units corresponds to a calculation unit of said plurality of calculation units, and wherein each calculation unit of said plurality of calculation units is configured to perform a portion of a decryption operation on a different ciphertext block of said plurality of ciphertext blocks; and an output stage coupled to said storage section and said calculation section, wherein a ciphertext block of said plurality of ciphertext blocks stored in a storage unit of said first plurality of storage units and an output of said calculation section are received by said output stage.