1. A multichannel memory architecture comprising: at least two independent memory clusters, each of said clusters having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses; and at least two multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least one of said clusters, each logic unit being capable of controlling a memory transaction, each channel being adapted to carry address and control information and data information for conducting said memory transaction between said at least one of said logic units and said at least one of said clusters, said at least two multi-line channels providing a plurality of distinct operating modes for said memory transaction, and at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line.