1. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: an integrated circuit device comprising: a cascaded delayed execution pipeline unit having two or more execution pipelines that begin execution of instructions in a common issue group in a delayed manner relative to each other; circuitry configured to: receive an issue group of instructions; determine whether the issue group includes a load instruction; and upon determining that the issue group includes a load instruction, schedule the load instruction to be executed in a first pipeline of the two or more execution pipelines, and schedule each remaining instruction in the issue group to be executed in remaining pipelines of the two or more pipelines, wherein execution of the load instruction in the first pipeline begins prior to beginning execution of the remaining instructions in the remaining pipelines.