1. Apparatus for reducing latency of inter-reference ordering between memory reference operations of a shared memory multiprocessor system having a consistency model, the system having a plurality of processors, each processor capable of issuing a memory reference operation to the system, the apparatus comprising: a commit-signal structure generated by control logic of the multiprocessor system in response to each issued memory reference operation, the commit-signal generated substantially sooner than completion of the memory reference operation, the commit-signal indicating apparent completion of the memory reference operation rather than actual completion of the operation; wherein each processor employs the commit signal to impose inter-reference ordering.