1. In a latching circuit array of logic gates wherein a latch comprising some of said gates and responsive to a logic signal is drivably connected to an output logic circuit comprising at least one other of said gates, said latch having an output gate having at least two inputs, said output gate and said one other of said gates being of the same kind, means for connecting each of the inputs of said output gate of said latch to respective ones of inputs of said one other of said gates, and means for applying at least one additional signal to at least one additional input of said one other of said gates but not to any of said gates of said latch.