1. A memory system, comprising: a memory bit cell comprising: a storage circuit configured to store data; and one or more P-type Field-effect Transistor (PFET) access transistors configured to pass the stored data from the storage circuit to a respective bit line among one or more bit lines in response to a read operation; and a sense amplifier comprising one or more PFET sense transistors each configured to sense the data on a respective bit line among the one or more bit lines in response to the read operation.