1. A soft cache system performing the operations of: comparing tag bits of a virtual address with tag bits programmed in a plurality of register entries, each entry associated with an index to a cache line of programmable cache line size in virtual cache space, the virtual cache space location programmed by a block address portion of the virtual address; when the tag bits of the virtual address match the tag bits of one of the programmable register entries, selecting the index corresponding to said entry for generating a physical address; and generating the physical address using the selected index as an offset to the cache line and the block address from the virtual memory as an address to the virtual cache space.