1. A method of creating logic chains in a Boolean network representing a logic circuit and mapping the logic circuit to an electronic circuit, the method comprising: creating a plurality of generic logic chains in the logic circuit with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations; and mapping the plurality of logic chains in the logic circuit to an electronic circuit; wherein each of the logic chains being a subnetwork of adjacent nodes with equal routing depth and increasing logic depth.