1. A microprocessor, comprising: a register set, defined by an instruction set architecture of the microprocessor; a cache memory; a superscalar pipelined architecture including a plurality of execution units; and a load unit, coupled to the cache memory, wherein the load unit is distinct from the other execution units of the microprocessor and includes an arithmetic/logic unit (ALU) in which the load unit and the ALU are not separated by a register; wherein the load unit is configured to receive an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored; wherein the load unit is configured to read the source operand from the cache memory and to provide the source operand only to the ALU without registering the source operand before being provided to the ALU; wherein the ALU is configured to perform the operation on the source operand to generate the result; and wherein the load unit is further configured to output the result for subsequent retirement to the destination register.