1. A memory, comprising: an array of memory cells divided into a plurality of memory planes; a plurality of programming circuits coupled to the plurality of memory planes, each programming circuit associated with a respective memory plane and operable to program data to the respective memory plane in response to programming signals and when the programming circuit is enabled; and control logic coupled to the plurality of programming circuits, the control logic operable to generate programming signals for the plurality of programming circuits in response to the memory receiving program commands and further operable to generate programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes at least two of the plurality of programming circuits concurrently enabled to overlap a portion of the programming of data for the respective memory planes.