1. A semiconductor memory structure, comprising: a substrate having electrical devices formed therein, and further having at least one dielectric layer and at least one interconnect layer disposed above the substrate; and a first stackable add-on layer, the first stackable add-on layer including a plurality of vertically oriented semiconductor memory cells disposed within the first stackable add-on layer, the plurality of vertically oriented semiconductor memory cells separated from each other by dielectric material; wherein the stackable add-on layer is bonded to a layer of the substrate that is the greatest distance from the substrate; and wherein the memory cell is a DRAM having at least one transistor.