1. An arithmetic-logic circuit for receiving a plurality of input codes and for determining an output code, each code having a respective magnitude and being conveyed in parallel by a plurality of respective code signals, the circuit comprising: a. for each respective plurality of input code signals, a respective product term generator, each product term generator for providing a respective plurality of product term signals, each product term signal indicative of an AND combination of respective input code signals; b. a summary term generator for providing a plurality of summary term signals in parallel, each summary term signal indicative of an OR combination of a corresponding product term signal from each product term generator; and c. a selection circuit for providing the plurality of output code signals according to an extreme of the respective magnitudes of the input codes, an output code signal being indicative of an AND combination of a multiplicity of summary term signals of the plurality of summary term signals.