1. An integrated circuit data processing system comprising: a shared internal bus for transferring both data and instructions; a shared bus interface unit connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory are transferrable to the shared internal bus via the shared bus interface unit; a general purpose (GP) central processing unit (CPU) connected to the shared internal bus for retrieving GP instructions, the GP CPU including means for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus; and a digital signal processor (DSP) module connected to the shared internal bus, the DSP module including circuitry accessible to the GP CPU via the shared internal bus and that holds a vector "Z", and signal processing means for processing an externally-provided signal received by the DSP module by executing DSP command-list code instructions, the signal processing means including lattice means for executing a first of said command-list code instructions to update propagating values of the vector "Z" responsive to the externally-provided signal, wherein execution of said first of said command-list code instructions requires only a single instruction fetch/decode cycle of the DSP module to update the propagating values of the vector "Z".