1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells and a plurality of redundant memory cells; a decoder for selecting one of the plurality of memory cells in accordance with an external address; a failure address register for storing an address of a failed memory cell; a redundant address register for storing an address of a redundant memory cell; a comparator for comparing the external address with the address of the failed memory cell and generating a decision signal when the external address coincides with the address of the failed memory cell; and a switch for converting the external address supplied to the decoder with the address of the redundant memory cell in response to the decision signal.