1. A processor comprising: a semiconductor die including: at least one core; a cache memory; an interconnect that couples the at least one core and the cache memory, the interconnect to operate at an interconnect frequency; and a power management unit (PMU) including first logic to determine whether to adjust the interconnect frequency responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor, the Bayesian prediction value to indicate whether the workload is scalable with respect to the interconnect frequency, wherein the Bayesian prediction value is determined based on one or more activity measures associated with the processor.