1. A controller interface between a processor and a coprocessor, comprising: controller circuitry including: a decoder block; pipeline monitor and control logic coupled to the decoder block, wherein the pipeline monitor and control logic is coupled to an execution stage of the processor for monitoring a pipeline portion of the processor; the monitoring of the pipeline portion of the processor including receiving execute signals from the execution stage of the processor; the pipeline portion of the processor being internal to the processor and having the execution stage of the processor; and buffer and synchronization circuitry coupled to the pipeline monitor and control logic; the controller circuitry coupled to the processor to provide a processor interface for operating at a first frequency, the first frequency being that of the processor; the controller circuitry coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, the second frequency being that of the coprocessor; the first frequency being greater than the second frequency; the controller circuitry configured to operate at both the first frequency and the second frequency such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor; wherein the processor is coupled to receive an instruction for the coprocessor; wherein the instruction is passed from the pipeline of the processor to the controller for passing along to the coprocessor; and wherein the processor does not have to be slowed down for execution of the instruction by the coprocessor.