1. A microprogrammable control unit for an interface circuit adapted to control two systems acting simultaneously according to two stored independent sequences of micro-instructions, a store for storing said sequences or micro-instructions, said microinstructions comprising code words divided in several control fields to direct the operation of said control unit, said control unit having an instruction input bus line and an address bus output line to connect to said store, a data bus line, control inputs, test input and timing input, said control unit comprising: an addressing unit having an instruction input, control inputs, test input, timing input coupled to said timing input of said control unit, address output connected to said address bus output line, and a multiple data output, said addressing unit being adapted to deliver to said store, at a fixed clock rate determined by timing signals applied to said timing input of said addressing unit, instruction addresses corresponding alternately to microinstructions in one and the other sequence; instruction register each having multiple inputs connected to said instruction input bus line, and multiple output coupled to said control inputs of said addressing unit; sources including two input registers, two output registers and two up and down counters, said input registers having control inputs, state outputs, multiple data inputs connected to said data bus line and multiple outputs connected to said instruction bus line, said output registers having control inputs, multiple data inputs connected to said multiple data output of said addressing unit, and said counters having state outputs, multiple data input also connected to said multiple data output of said addressing unit and control outputs, each of said sources having timing inputs coupled to outputs of a logic circuit having an input coupled to said timing input, said logic circuit selectively activating said sources responsive to said timing input for the coordination of data and instruction flow; a multiplexer having inputs coupled to said state outputs and an input connected to said test input of said control unit and having control inputs coupled to outputs of an instruction register, said multiplexer having an output coupled to said test input of said addressing unit.