1. An apparatus comprising: a multithreaded memory management unit (MMU) configured to receive two or more address translation requests from one or more upstream devices, wherein the multithreaded MMU is further configured to process at least two of the two or more address translation requests in parallel, to obtain corresponding translated addresses of a system memory, wherein the multithreaded MMU comprises a primary scheduler, a translation cache, and a secondary scheduler, wherein the primary scheduler is configured to receive the two or more address translation requests and issue the two or more address translation requests for translation in the translation cache, wherein if there are misses in the translation cache for one or more missing address translation requests issued by the primary scheduler, the translation cache is configured to forward the one or more missing address translation requests to the secondary scheduler, and wherein the secondary scheduler is configured to receive the one or more missing address translation requests and schedule the one or more missing address translation requests for translation to addresses of the system memory in one or more translation table walkers (TTWs); and wherein the multithreaded MMU further comprises at least one of: a pre-filtering block configured to receive the one or more missing address translation requests and if two or more missing address translation requests of the one or more missing address translation requests are similar missing address translation requests, forward only one of the two or more similar missing address translation requests to the one or more TTWs and suppress the remaining ones of the two or more similar missing address translation requests; or a translation table access filter configured to determine if two or more of the one or more missing address translation requests involve redundant accesses of the system memory, and allow only unique accesses of the system memory to be performed.