1. A control flow prediction unit comprising: a global history shift register (GSR); update logic, wherein in response to determining: a branch instruction has more than two targets, is indirect, and unconditional, the update logic is configured to derive a value for storage in the GSR based on one or more bits of a branch target address of the branch instruction, wherein said value replaces selected bits of the GSR without performing a shift operation; and the branch instruction is direct, conditional, or has fewer than three targets, said value comprises a taken/not-taken prediction bit to be shifted into the GSR for the branch instruction.