1. A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic, the configurable arithmetic block comprising: a first plurality of registers; a first plurality of multiplexers, wherein each multiplexer of the first plurality of multiplexers is coupled to select a bit of a first serial data stream or a bit of a first multi-bit input word and has an output coupled to a register of the first plurality of registers; a second plurality of registers; an arithmetic function circuit having a plurality of arithmetic function elements, each arithmetic function element coupled to at least one other arithmetic function element of the plurality of arithmetic function elements and coupled to receive outputs of at least one of the first plurality of registers or the second plurality of registers; and an output coupled to the arithmetic function circuit.