1. A computer-implemented method of designing a clock network for a plurality of latches in one or more clock domains of an integrated circuit, comprising: receiving an input layout of the latches by executing first program instructions in a computer system; logically assigning clusters of the latches to respective clock distribution structures by executing second program instructions in the computer system; placing clock pins at pin locations by executing third program instructions in the computer system; placing the clock distribution structures underneath the clock pins such that at least a portion of a given clock distribution structure overlaps with a corresponding clock pin by executing fourth program instructions in the computer system; and connecting each clock distribution structure to a corresponding cluster of the latches by executing fifth program instructions in the computer system.