1. A computing apparatus, comprising: a conversion circuit, receiving a first instruction sequence in which each instruction in the first instruction sequence belongs to an instruction set, and combining, in a power saving mode, a second instruction sequence having the same function as the first instruction sequence with at least one specific instruction used for supporting normally-off computing function to reduce power consumption to obtain and output a third instruction sequence, wherein the at least one specific instruction does not belong to the instruction set; a data storage unit, comprising a volatile part and a non-volatile part; an instruction processing circuit, coupled to the conversion circuit and the data storage unit, wherein the instruction processing circuit process the third instruction sequence, and manages a storage state of the volatile part and the non-volatile part of the data storage unit according to the at least one specific instruction; a power management unit (PMU), coupled to the conversion circuit and the instruction processing circuit, wherein the instruction processing circuit executes a corresponding instruction sequence for operating an operating system (OS), and the OS preserves a state of a process that is interrupted by an interrupt event, an interrupt service routine that serving the interrupt event triggers the PMU to output a mode switching signal with a value indicating that the computing apparatus is in the power saving mode to the conversion circuit, and wherein the conversion circuit inserts the at least one specific instruction into the second instruction sequence to obtain the third instruction sequence, after receiving the mode switching signal with the value indicating that the computing apparatus is in the power saving mode.