1. An integrated circuit device ECL test access port (TAP) having a plurality of test data registers including a boundary scan register for performing boundary scan testing, a bypass register for providing a minimum path, and optional design specific test data registers and a TAP controller comprising an n state finite machine of a plurality of flip flops whose outputs determine the state of the TAP controller, said TAP controller having a test logic reset state in which the test access port is inactive and a plurality of test mode states when the test access port is active, said registers and TAP controller of the ECL test access port comprising ECL gates with respective ECL current sinks, the improvement comprising: said TAP controller comprising a switch control signal (SCS) logic circuit incorporated in the TAP controller for generating a current sink switch control signal (SCS) according to the state of the TAP controller, said TAP controller being constructed so that the outputs of the flip flops comprising the TAP controller n state finite machine are at specified logic potential levels during the test logic reset state of the TAP controller, said SCS logic circuit for generating the current sink switch control signal SCS comprising a first logic gate having inputs coupled to the outputs of the TAP controller n state finite machine flip flops; a current sink switch circuit coupled to respective current sinks of ECL gates incorporated in the boundary scan register and design specific TAP data registers, said current sink switch circuit having an input coupled to the SCS logic circuit to receive the current sink switch control signal SCS and being constructed to turn off said respective current sinks in response to a first SCS signal to reduce power dissipation when the TAP controller is in the inactive test logic reset state.