1. A method of executing instructions in a processor in which a first part of an instruction causes execution of a second part of an instruction, and wherein the second part comprises a plurality of elements, the method comprising the steps of: fetching a first part of the instruction; identifying from first information encoded in the first part of the instruction which elements constitute the second part of the instruction; identifying from second information encoded in the first part of the instruction which of the identified elements correspond to no-operation, NOP instructions; and fetching the elements that form the second part of the instruction, excluding the elements which correspond to no-operation, NOP, instructions.