1. A design conversion method, comprising: a field programmable gate array (FPGA) device and a metal programmable gate array (MPGA) device, wherein each of the devices comprises an exact transistor layout of a logic block. array; and a bit stream to configure the FPGA, wherein a first portion of the bits determine functionality of one or more of said logic blocks in the FPGA; and a conductive pattern to configure the MPGA, wherein the result of said first portion of bits in the FPGA is replicated in a first portion of the conductive pattern to provide identical functionality of said one or more logic blocks in the MPGA.