1. An input output control device connected to a memory, a processor and an input output device for controlling an interface among the memory, the processor and the input output device, the processor and the input output device sharing the memory via the interface provided by the input output control device, the input output control device comprising: a direct memory access controller for controlling direct memory access to the memory by the input output device; an arbiter connected to said direct memory access controller and the processor for arbitrating the access to the memory by the processor and said direct memory access controller; an memory controller connected to the memory for controlling an interface with the memory; and a debug controller connected to said arbiter and said memory controller for issuing said memory controller a memory write request for access address information for debugging in response to a direct memory access request from said direct memory access controller.