1. A method of forming a memory array comprising the steps of: providing a substrate; depositing a first set of spaced apart, substantially parallel address lines on said substrate; insulating a plurality of spaced cross-over regions on said first set of address lines; depositing a second set of spaced apart, substantially parallel address lines on said substrate at an angle to said first set of address lines so as to lie atop said insulated cross-over regions of said first set; depositing a plurality of spaced apart electrical isolation elements in electrical communication with a first one of said first and second sets of address lines, said isolation elements disposed between the cross-over regions thereof; and depositing a plurality of settable, substantially planar memory elements having a length dimension substantially greater than the thickness dimension thereof, said memory elements operatively disposed so as to establish series electrical communication through the length dimension thereof between a corresponding isolation element and the second one of said first and second sets of address lines; said memory elements made of a material capable of having the electrical conductivity thereof set from one conductivity state to another conductivity state by the application of programming energy.