1. A single instruction multiple data processor comprising: a plurality of processing elements, interconnected in a Cube Connected Cycle Network design and using interprocessor communication links which carry one bit at a time in both directions simultaneously; controller means for controlling each of said plurality of processor elements which feeds each of said processor elements identical local memory addresses, identical switching control bits, identical Boolean function selection codes, and distinct activation control bits, depending on each of said processor's position in said Cube Connected Cycles Network in a prescribed fashion; and a plurality of input/output devices connected to said network by a plurality of switching devices wherein, each of said plurality of processing elements comprises: two single-bit accumulator registors (A, B); two Boolean function generator units, each of which computes any one of 2.sup.8 possible Boolean functions of three Boolean variables as specified by Boolean function codes sent 2 at a time by said controller to each of said processing elements; switching circuit means controlled by said controller which select the three inputs to the logic function generators and to which switching circuitry provides that the output of one of said generators is fed to a first one of said registers (B) and the output of the other generator is fed to a second one of said registers (A) and an addressed memory cell of a local memory wherein said local memory consists of at least k bits and at most p bits where p is chosen to be appropriate to VLSI technology so that the space on a VLSI chip required by an entire processing element is at least one-half devoted to the processing elements's memory.