1. A computer-executed method for retargeting a circuit design layout including a pattern of features for a multiple patterning lithography process, the method comprising: decomposing a circuit design layout file to produce decomposed layout files in a computer, wherein each decomposed layout file includes a feature having an initial width, and wherein each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process; retargeting at least one decomposed layout file based on photolithography limitations of the at least one decomposed layout file to produce at least one retargeted layout file with a retargeted feature having a retargeted width greater than the initial width; determining in the computer that a combination of layout files includes a spacing conflict; and resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict to have a modified feature with a modified width less than the retargeted width, wherein the at least one retargeted layout file in the circuit design layout is used for fabricating semiconductor devices.