1. A method for optimizing a digital circuit design, the method comprising steps of: translating a first representation of the digital circuit design to a second representation of the digital circuit design, the second representation comprising a plurality of syntactic expressions that admit a representation of a higher-order function of base Boolean values; syntactically manipulating the plurality of syntactic expressions to form a third representation of the digital circuit design, wherein the manipulating step comprises reducing a number of nodes within the plurality of syntactic expressions.