1. A processor comprising: a plurality of packed data registers; a decode unit to decode a data element selection and consolidation instruction, the data element selection and consolidation instruction to indicate a first source packed data operand that is to have a plurality of data elements, and the data element selection and consolidation instruction to indicate a second source operand that is to have a plurality of mask elements, wherein each mask element of the second source operand corresponds to a different data element of the first source packed data operand in a same relative position, and the data element selection and consolidation instruction to indicate a general-purpose register; and an execution unit coupled with the decode unit, the execution unit, in response to the data element selection and consolidation instruction, to store a result packed data operand in a destination storage location that is to be indicated by the data element selection and consolidation instruction, the result packed data operand to include all data elements of the first source packed data operand, which correspond to unmasked mask elements of the second source operand, consolidated together in a least significant portion of the result packed data operand, wherein to use the least significant portion to store said all data elements is to be fixed for an opcode of the data element selection and consolidation instruction, and the execution unit, in response to the data element selection and consolidation instruction, to store a value indicative of a number of said all data elements of the first source packed data operand that are said consolidated together in the general-purpose register.