1. A detector comprising: a path generator adapted to produce a plurality of candidate sequences of bits and decisions regarding logic states of detected bits in a signal based on reliability information for the logic states; a state reducer adapted to: compare the plurality of candidate sequences of bits and the decisions to identify unlikely error events; and discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths; and a branch metric calculator adapted to calculate metrics for the set of remaining paths.