1. A method for timing analysis using a processor, comprising: generating a model that is representative of a coupling between at least two through substrate vias (“TSVs”); determining an impedance profile between the at least two TSVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determining an effective capacitance value corresponding to each respective impedance value; populating at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and conducting an RC extraction of a design layout of a TSV circuit using the populated table and based on each determined effective capacitance value to generate an RC network.