1. An apparatus for improving performance of a parallel computing system, the apparatus comprising: a plurality of processors, each processor having a local cache memory device and each processor running program code of a software program region having no data dependency, a local cache memory device of each processor associated with a hardware local cache controller that updates a cache line in the local cache memory device; and a first hardware local cache controller associated with a first local cache memory device of a first processor for detecting an occurrence of a false sharing of a first cache line by a second processor running the program code and allowing the false sharing of the first cache line by the second processor, the false sharing of the first cache line occurring upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.