1. A computer system comprising: a first memory storing first computer instructions and first computer operands; a second memory storing second computer instructions and second computer operands; a shared address generator circuit generating a shared memory address; a first memory selection detector coupled to the shared address generator circuit and generating a first memory selection detector signal in response to the shared memory address; a second memory selection detector coupled to the shared address generator circuit and generating a second memory selection detector signal in response to the shared memory address; a first memory accessing circuit coupled to the first memory, to the shared address generator circuit, and to the first memory selection detector and accessing first computer instructions and first computer operands stored by the first memory in response to the shared memory address and in response to the first memory selection detector signal; a second memory accessing circuit coupled to the second memory, to the shared address generator circuit, and to the second memory selection detector and accessing second computer instructions and second computer operands stored by the second memory in response to the shared memory address and in response to the second memory selection detector signal; and a stored program computer coupled to the first memory accessing circuit and to the second memory accessing circuit and processing the accessed first computer operands and the accessed second computer operands in response to the accessed first computer instructions and in response to the accessed second computer instructions.