1. An interface for controlling the exchange of data between a memory unit and at least one processing unit of a computer wherein the operations performed by the processing unit on the memory unit are performed over a time varying period and include the initiation of a memory cycle determined by a memory cycle request signal (DC) and a cycle acknowledge signal (AC), the execution of a write operation determined by a write initiate signal (TE) and a write finish signal (AE) and the execution of a read operation determined by a data ready signal (TL) and a reading finished signal (AL) comprising: a delay device (66, 67) having a plurality of delay outputs and having an input connected to receive the memory cycle request signal (DC) emitted by the processing unit and being operable to transmit said signal (DC) after a first delay (Ri) to the processing unit, said delayed cycle request signal establishing the cycle acknowledge signal (AC) for indicating that a memory cycle has been initiated. a first storage means (70) in the memory unit, a second storage means (69) in the processing unit, said second storage means adapted to store information indicating that either the write or the read operation, or both, are to be performed, means connecting the output of the second storage means to the input of the first storage means to transfer the information to the first storage means, said transfer being effected during an interval of time defined by the cycle request signal (DC) and the cycle acknowledge signal (AC). first means for linking the memory cycle request initiated by the processing unit with a read operation in the memory unit requested by said processing unit in response to the data ready signal TL and the reading finished signal (AL), said data ready signal being obtained from an output of said delay device (66,67) after an adjustable delay (R2) determined by said delay device (66,67) and transmitted to said processing unit for execution of the read operation, the reading finished signal (AL) being outputted by the processing unit after receipt of the data ready signal (TL) and an adjustable delay (R3) determined by the processing unit, and second means for linking the memory cycle request initiated by the processing unit with a write operation in the memory unit requested by said processing unit in response to the write initiate signal (TE) and the write finish signal (AE), said write initiate signal being initiated by the processing unit and transmitted to the memory unit after an adjustable delay (R4) by said delay device (66,67), said write finish signal (AE) being obtained from an output of delay device (66,67) after an adjustable delay (R7) determined by said delay device whereby the exchange of data may be controlled between processing units and memory units having different timing for the signals exchanged.