1. A processor comprising: a first level of cache memory; a first set of instructions configured to implement a first cache coherency protocol; a second set of instructions configured to implement a second cache coherency protocol; a cache coherency protocol selector having at least two choice-states, the cache coherency protocol selector comprising one or more bits in a configuration register; and a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency protocol with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector, the first cache coherency protocol being implemented by the cache coherency implementer when a first value appears in the one or more bits in the configuration register, and the second cache coherency protocol being implemented by the cache coherency implementer when a second value appears in the one or more bits in the configuration register.