1. A basic non-volatile memory group comprising: (i) a plurality of individual memory cells each having a source electrode, a drain electrode and at least one side gate, the memory cells being stacked on a planar substrate along a direction out of the plane of the substrate (“vertically”) and being electrically connected in parallel by sharing the source electrodes and the drain electrodes, respectively; (ii) a piece of semiconductor fin vertically oriented out of the planar substrate providing a plurality of conduction channels for the memory cells with the direction of electrical current flow being approximately parallel to the planar substrate; (iii) the shared source and the shared drain electrodes being connected to respective opposite sides of the semiconductor fin; (iv) the side gates being vertically stacked and located on the other respective opposite sides of the semiconductor fin; and (v) a charge trap structure between the gate electrodes and the conduction channel for trapping electrons as a storage medium for memory cells.