1. A non-volatile storage apparatus, comprising: a plurality of non-volatile memory cells including a data memory cell and a dummy memory cell, wherein the data memory cell and the dummy memory cell are part of a common NAND string; a select gate, wherein the select gate is part of the common NAND string and the dummy memory cell is located on the common NAND string between the data memory cell and the select gate; and one or more control circuits in communication with the plurality of non-volatile memory cells, the one or more control circuits configured to perform a memory operation on the data memory cell, the one or more control circuits configured to apply a gate voltage based on temperature to the dummy memory cell as part of the memory operation, wherein: the memory operation is an erase operation; and the one or more control circuits are configured to apply the gate voltage based on temperature to the dummy memory cell as part of the memory operation to cause the dummy memory cell to experience a shallow erase in response to a higher temperature and to cause the dummy memory cell to experience a deeper erase in response to a lower temperature.