1. A non-volatile content addressable memory (NVCAM), comprising: a NAND-type match line non-volatile memory array having a plurality of NVCAM cells organized in rows and columns in a plurality of NAND strings, each NVCAM cell comprising a switching transistor; a plurality of match lines, each match line being formed by series-connected switching transistors in a corresponding NAND string; a plurality of bit line pairs, each bit line pair being connected to the NVCAM cells in a corresponding column; and a common source line extending vertically for connecting the same-side terminals of the plurality of match lines to a predetermined voltage terminal.