1. A method of processing instructions by a processor, said method comprising the steps: operating said processor by cycling a plurality of instructions through a single pipeline, said single pipeline having a plurality of sequential stages including stages for instruction processing and execution; stalling all of said stages of the pipeline in response to a detected processing fault without stalling as a result solely of a predicted fault; servicing the detected fault while the pipeline is stalled; preloading all of said stages of the pipeline invalidated by said processing fault, while maintaining those stages which are not invalid, so as to fill the pipeline while the pipeline is stalled; and running the pipeline upon completion of preloading, wherein the pipeline includes a stage for executing an instruction, in which for an execution type processing fault the execution stage is invalidated and in which said preloading comprises preloading the execution stage.