1. A method for generating a post-silicon validation test for a physical system on chip (SOC), the method comprising, by operating a test generator comprising a computer processor: obtaining a selection of scenarios from a set of valid scenarios, each valid scenario comprising a plurality of actions that were selected from a set of available actions to be carried out on the physical SOC and defined relations among the selected actions, said each valid scenario originally constructed for generating simulation tests in which the actions of that scenario are conducted on a model of the SOC and validated to determine that the physical SOC is expected to perform the actions flawlessly; combining the selected scenarios into a combined scenario in which the selected scenarios are executed in parallel in repeated loops, a run time of one of the selected scenarios being different from a run time of another of the selected scenarios; if a scenario of the selected scenarios includes an action that addresses concurrently with an action of another scenario of the selected scenarios a single electronic device of the physical SOC in a manner that is beyond a limitation of that electronic device, excluding the scenario from the combined scenario; solving the combined scenario to determine a validity of the combined scenario; and if the solving of the combined scenario validates the combined scenario, generating a post-silicon test code corresponding to the combined scenario for carrying out on the physical SOC.