1. A three dimensional neural network accelerator comprising: a first neural network accelerator chip comprising a first array of tiles that includes a first neural network accelerator tile comprising a first transmission coil; and a second neural network accelerator chip comprising a second array of tiles that includes a second neural network accelerator tile comprising a second transmission coil, wherein each tile of the first array of tiles and the second array of tiles is a self-contained component that can independently execute computations for the three dimensional neural network accelerator and includes a processing element and a memory, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, wherein the first transmission coil is configured to establish wireless communication with the second transmission coil via inductive coupling, wherein the first array of tiles and the second array of tiles are configured to accelerate a computation of a neural network by forming, through wireless communication established between the first transmission coil of the first tile and the second transmission coil of the second tile, a static interconnect system that includes a communication scheme providing for an uninterruptible flow of data and organized as a linear sequence of processing through the first array of tiles and the second array of tiles, and wherein the linear sequence of processing starts and ends in an un-core controller, the un-core controller comprising one or more functional blocks configured to handle one or more of: (i) input/output (I/O) to a host computer, (ii) interface to off-chips memory, (iii) connecting to I/O devices, or (iv) performing synchronization, coordination, and buffer functions.