1. A tally circuit comprising in combination: a first and second switching means having respectively a first and second state, said first and second switching means each having an input, a control terminal and an output, said output of each of said first and second switching means being connected to form a single output, said first and second switching means respectively connected to a two rail selector bus, said first and second switching means connected to each other in a mutually exclusive manner wherein when said first switching means is in the on state said second switching means is in the off state, said two rail selector bus connected to said control terminal to provide control signals to said first and second switching means to maintain the mutually exclusive operation thereof, said first and second switching means receiving a logical signal comprising logical ones and zero at their respective inputs and providing a ones signal output in response to the number of logical ones in the input logical signal, said first and second switching means forming a tally cell, a plurality of said tally cells being arranged in a descending order parallel-series tally cell circuit for counting the number of logical ones in an input signal, said tally cells respectively having a pair of inputs, said plurality of parallel inputs, said descending order occurring from the input of said tally cell circuit to the output thereof, the number of input ones in said plurality of parallel inputs are expressed as a binary code at the output of said tally cell circuit, said first and second switching means respectively comprising in combination: a first and second field effect transistor having their respective sources and drains connected in parallel with each other, a third and fourth field effect transistor having their respective sources and drains connected in parallel with each other, said drains of said first, second, third and fourth field effect transistors are respectively connected to each other to form the signal output, said first and third field effect transistors having their respective gates connected to one rail of said two rail selector bus, said second and fourth field effect transistors having their respective gates connected to the other rail of said two rail selector bus, said logical signal being applied respectively to the common source of said first and second field transistors and, said third and fourth field effect transistor, said first, second, third and fourth field effect transistors each comprise a CMOS transistor which is formed on a silicon-on-sapphire substrate.