1. A hardware system for providing interrupt forwarding registers comprising: a sequence processor (SP); at least one processing element (PE); a compute register file (CRF); a plurality of functional units; and a condition generation unit (CGU); wherein when an interrupt occurs and is acknowledged, all instructions in the decode phase are allowed to proceed through execute; one-cycle instructions are allowed to complete and update their target registers and flags; and any two-cycle instructions are allowed to complete, but their output which may include output data, output register addresses and flag information is saved in a set of special purpose interrupt forwarding registers and no update is made to the CRF or status registers.