1. A dynamic reconfigurable heterogeneous processor architecture with load balancing, comprising: a plurality of microprocessors; at least one dynamic reconfigurable heterogeneous processor coupled to said microprocessors and assisting said microprocessors in executing operations; and a work control logic unit coupled to said microprocessors and said dynamic reconfigurable heterogeneous processor, analyzing work proportion of each said microprocessor, dynamically allocating said dynamic reconfigurable heterogeneous processor to support said microprocessors to execute said operations, and balancing workload of each said microprocessor; wherein a method of designing a circuit of said dynamic reconfigurable heterogeneous processor further comprising steps of: performing a plurality of hardware requirement analyses using operation requirement trees for basic operations of said microprocessors, wherein each said operation requirement tree comprises a plurality of operation nodes showing an operation required; choosing common said operation nodes of said operation requirement trees to establish a plurality of block-selection trees; choosing sharable said operation nodes of said block-selection trees and adding a multiplexer operation node at each sharable said operation node, respectively; and searching all said block-selection trees and choosing said operation nodes and associated said multiplexer operation nodes of said block-selection trees that fulfill all necessary reconfiguration requirements of said dynamic reconfigurable heterogeneous processor.