1. An electronic device, comprising: a communication interface; processing circuitry; and a memory coupled to the processing circuitry, the memory includes a first logic that, when executed by the processing circuitry, organizes (i) a first plurality of indicators of compromise (IOCs) received from a first source via the communication interface, where each of the first plurality of IOCs being caused by a known origin of a malicious attack, and (ii) one or more IOCs received from a second source via the communication interface, the second source being different from the first source where an origin of the one or more IOCs is unknown, and a second logic that, when executed by the processing circuitry, (i) conducts an analysis that evaluates whether the one or more IOCs have at least a degree of correlation with the first plurality of IOCs, and (ii) determine a threat level signifying a degree of confidence that the one or more IOCs received from the second source are caused by the known origin of the first plurality of IOCs.