1. A processor having one or more processing cores, each of said one or more processing cores comprising: front end logic circuitry to fetch respective instructions of threads and decode said instructions into respective micro-code and input operand and resultant addresses of said instructions; a plurality of processing units, each of said processing units to be assigned at least one of said threads, each processing unit coupled to said front end unit and having a respective buffer to receive and store microcode of its assigned at least one of said threads, each of said plurality of processing units comprising: i) at least one set of functional units corresponding to a complete instruction set offered by said processor, said at least one set of functional units to execute its respective processing unit's received microcode; ii) registers coupled to said at least one set of functional units to store operands and resultants of said received microcode; iii) data fetch circuitry to fetch input operands for said at least one functional units' execution of said received microcode.