1. An integrated circuit storage logic array comprising: at least one data column having first and second data column conductors; a plurality of rows disposed substantially orthogonal to said column, each row comprising a row conductor; clock means for generating a plurality of phase-displaced clock signals; a storage cell operatively associated with said data column, said storage cell having a memory element, output means responsive to said clock means for transferring data from said memory element to said first and second data column conductors, and input means coupled for transferring data from said first and second data column conductors to said memory element; and a plurality of functionally distinct logic cells connected between selected column and row conductors and adapted to be actuated by said clock means to manipulate data among said selected column and row conductors.