1. A processor comprising: a decode unit to decode an exception handler return instruction; and an exception handler return execution unit coupled with the decode unit, the exception handler return execution unit, responsive to the exception handler return instruction, to: not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler; and configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler.