1. An advanced encryption standard (AES) architecture which provides high throughput and low latency, comprising: a maximum parallel encryption module arranged to receive a plurality of data bytes to be encrypted and to implement one round of the AES algorithm in one clock cycle, a maximum parallel key scheduling module arranged to generate sub-keys in one clock cycle in parallel with said encryption module, said sub-keys provided to said encryption module, and a controller arranged to control the operation of said maximum parallel encryption and key scheduling modules such that said architecture performs one round of the AES algorithm in one clock cycle.