1. A hardware simulation accelerator having as input a simulation model of a logic design to be simulated in the hardware simulation accelerator, comprising: at least one simulator chip having at least one logic evaluation unit having a plurality of programmable hardware resources; at least one instruction memory associated with each of the at least one logic evaluation unit in the at least one simulator chip, the instruction memory having a plurality of encoded instructions to simulate the simulation model using the hardware resources, the simulation model defining a first combination of selected ones of the plurality of hardware resources that need not be programmed by one or the plurality of encoded instructions, and one or more second combinations of fewer than all of the plurality of hardware resources to be programmed by one or more of the encoded instructions, each encoded instruction having an opcode indicating the one or more second combinations of hardware resources to be programmed, and a data portion consisting of input data or output data to/from those plurality of hardware resources of the one or more second combinations; the logic evaluation unit connected to receive the plurality of encoded instructions from its associated at least one instruction memory; an instruction decode logic connected to the at least one instruction memory and its associated logic evaluation unit to decode each of the plurality of the instructions into its opcode indicating how those hardware resources of the one or more second combinations are programmed according to the respective data portion of the instruction.