1. A microprocessor for performing non-blocking load comprising: an instruction issue unit for issuing a load instruction; and a load unit for executing data retrieval from a memory to a load destination register according to a load instruction that is issued from the instruction issue unit, the load unit comprising: a first input register for storing a value stored in the load destination register before being loaded; and a saved register capable of storing data retained in the first input register, wherein if a load instruction issued from the instruction issue unit is an unaligned load instruction for storing data, that is created by merging data read from the memory with the value before being loaded, in the load destination register, the first input register is made available to subsequent load instructions issued from the instruction issue unit by storing the data stored in the first input register in the saved register.