1. A computer system comprising: a memory system where at least some of the memory is designated as shared memory; a transaction-based bus mechanism coupled to the memory system wherein the bus mechanism includes a cache coherency transaction defined within its transaction set; a processor having a cache memory, the processor coupled to the memory system through the transaction based bus mechanism; a system component coupled to the bus mechanism, the system component including logic for specifying cache coherency policy; logic within the system component for initiating a cache transaction according to the specified cache policy on the bus mechanism; and logic within the processor responsive to the initiated cache transaction for executing a cache operation specified by the cache transaction.