1. A memory apparatus, comprising: a plurality of bit cells, wherein individual bit cells of the plurality of bits cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ), the switch device to produce a switching output according to a stochastic switching probability of the switch device; a bit line coupled to the switch device at a first layer of the MTJ; and a source line coupled to the switch device at a second layer of the MTJ, wherein at least one of the bit line or the source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output, and wherein the switching output enables a determination of whether the respective weight value is to be updated.