1. A digital data processing system, comprising: at least one processor; a plurality of memory modules embodying a main memory; a communications medium for communicating data between said at least one processor and said main memory; and memory access control logic controlling access by said at least one processor to said main memory, said memory access control logic supporting a plurality of different configurations of said memory modules embodying said main memory, said memory access control logic decoding a memory address to a plurality of physical parameter selections representing physical parameters, wherein, for a plurality of said physical parameter selections, a number of such selections to which said memory address is decoded by said memory access control logic is variable depending on the memory module configuration of said plurality of configurations of memory modules; wherein said memory access control logic decodes a first subset of said physical parameter selections from consistent bit positions of said memory address, said first subset comprising at least two physical parameter selections of said plurality of physical parameter selections for which a number of such selections to which said memory address is decoded by said memory access control logic is variable depending of the memory module configuration.