1. A method for testing an integrated SRAM circuit having at least on bit cell coupled to a first bit line and a complement bit line, comprising the steps of: applying power supply voltage and return to the at least one bit cell; enabling a first test switch coupling a first external contact pad to the first bit line and enabling a second test switch coupling a second external contact pad to the complement bit line; coupling one of externally sourced power supply voltage and externally sourced power supply return to each of said first external contact pad and said second external contact pad; and measuring the current into said first external contact pad and into said second external contact pad whereby an anomalous current may be detected.