1. A block-based computer processor, comprising: a cache memory; an unordered store queue comprising a plurality of store queue entries; and a merging logic circuit communicatively coupled to the unordered store queue and the cache memory, comprising a merged data buffer for storing a plurality of merged data bytes; the merging logic circuit configured to: select a first committed store queue entry of the plurality of store queue entries of the unordered store queue; read a memory address, a first age indicator, and a first data value from the first committed store queue entry; store the first age indicator and the first data value in one or more merged data bytes of the plurality of merged data bytes of the merged data buffer; for each remaining committed store queue entry of the plurality of store queue entries of the unordered store queue having an identical memory address as the first committed store queue entry: read a second age indicator and a second data value from the remaining committed store queue entry; and merge the second data value into the one or more merged data bytes of the plurality of merged data bytes of the merged data buffer, based on the second age indicator and one or more age indicators of the one or more merged data bytes; and output the plurality of merged data bytes of the merged data buffer to the cache memory.