1. A data processing system comprising: a main memory for storing therein data and microinstructions; a central processing chip having a data terminal and an instruction terminal; processor memory bus means connected between said main memory and said central processing chip data terminal for the transmission of data address bits and data therebetween; instruction bus means connected between said central processing chip instruction terminal and said main memory for the transmission of instructions address bits and instructions therebetween; instruction address means connected between said processor memory bus means, said instruction bus means and said processor memory bus means, said instruction address means for receiving from said central processing chip, said data address bits as a first portion of a fetching address and said instruction address bits as a second portion of said fetching address, and responsive to said fetching address, fetching from said main memory, said addressed microinstruction stored therein; and transmitting means for transmitting said fetched addressed microinstruction over said instruction bus means to said central processing chip for direct execution by said central processing chip.