1. An electrical fuse (eFuse) memory array comprising: a plurality of eFuse bit cells, each eFuse bit cell of the plurality of eFuse bit cells having a program transistor, a read transistor, and an eFuse, one end of the eFuse is connected to the program transistor and the read transistor, and another end of the eFuse is connected to a program bit line and the read transistor is connected to a read bit line, wherein a total area of the program transistor is greater than a total area of the read transistor, wherein a first eFuse bit cell and a second eFuse bit cell share a first program bit line, wherein the first program bit line is coupled to an eFuse of the first eFuse bit cell and also coupled to an eFuse of the second eFuse bit cell.