1. A data processing system comprising: one or more processors each configured to execute a plurality of tasks; one or more watchdog status registers each comprising a plurality of bits, wherein each watchdog status register is associated with one of the processors, and each bit of the plurality of bits of one watchdog status register is associated with one task of the plurality of tasks of one processor that is associated with the one watchdog status register; a centralized watchdog task configured to determine whether every bit of the plurality of bits of a respective watchdog status register stores a first state value, and write a trigger data pattern to the respective watchdog status register, in response to a determination that every bit of the plurality of bits of the respective watchdog status register stores the first state value, wherein the trigger data pattern comprises the first state value for each of the plurality of bits of the respective watchdog status register; and one or more hardware logic circuits each associated with a particular processor that is associated with a particular watchdog status register, each hardware logic circuit configured to identify a set of active tasks of the particular processor that are presently in an active task state, in response to a detection that the trigger data pattern is written to the particular watchdog status register.