1. In a floating-point processor, an addition pipeline, adapted for application thereto of first and second operand signals, each of which represents the sign, exponent, and mantissa of a respective floating-point input operand, for performing an effective addition or subtraction on the input operands and generating an output signal representing the result, the addition pipeline comprising: A) a main mantissa adder adapted for application thereto of first and second processed mantissa signals and representing respective mantissa values, the main mantissa adder being selectively operable to perform addition and subtraction on the mantissa values and generate a mantissa-adder output, representative thereof, from which the addition pipeline generates the addition-pipeline output; B) a pair of processing trains for generating from respective ones of the input operands' mantissas and applying to the main mantissa adder respective processed mantissa signals, each processing train, for at least some values of input operands whose exponent difference is zero or one, performing a normalization shift, when the addition pipeline is performing effective subtraction, by a number of bit positions represented by a normalization-shift signal applied thereto; and C) a normalization-shift-determination circuit that determines a required normalization shift by generating a possible-shift-point-vector signal comprising a plurality of bit signals representing respective bits of a possible-shift-point vector, each bit in the possible-shift-point vector corresponding to a different bit position in the input operands' mantissas, the value of each bit signal in the possible-shift-point vector being determined only from at most three, consecutive bits of the each input operand's mantissa, and applying to the processing trains a normalization-shift signal representing the position of the most-significant one bit in the possible-shift-point vector.