1. A computing device, comprising: a primary processing resource located in a system on a chip; a dispatch controller located in the system on a chip, the dispatch controller in communication with the primary processing resource; a plurality of secondary processing resources located in the system on a chip in communication with the dispatch controller, the plurality of secondary processing resources arranged to communicate indirectly with the primary processing resource via the dispatch controller, the dispatch controller arranged to synchronously manage a request from the primary processing resource for a first of the plurality of the secondary processing resources to execute a thread, the request from the primary processing resource identifying the first secondary processing resource; a shared memory space electrically coupled and accessible to the primary processing resource and the plurality of secondary processing resources, wherein the primary processing resource and the plurality of secondary processing resources are arranged to generate signals to and respond to signals from a signal/wait interface; and a global coordinator coupled to the primary processing resource and arranged to receive the request and asynchronously generate a dispatch command to the dispatch controller that defines a specific execution unit of the first secondary processing resource in response to a task offload condition.