1. A data processing architecture, comprising: an input device for receiving an incoming stream of data packets of unpredictable size; and a plurality of processing elements which are operable to process the received data packets; wherein the input device is operable to distribute a data packet of unpredictable size across one or more processing elements, the number of which is dynamically determined based at least in part on the size of the data packet; wherein the data processing architecture is operable to process at least one data packet at a time; and wherein the processing elements are arranged in a single instruction multiple data (SIMD) array and are operable to process different respective packet protocols at once while executing a single common instruction stream.