1. A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N, comprising: N functional units, each of the N functional units comprising logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation; and, masking circuitry to enable presentation of output results from selected ones of said N functional units.