1. In a data processing having a memory for storing instructions and an instruction execution means, a memory address controlling device comprising: (a) means for accepting a plurality of addresses and other signals, and means for accepting having a plurality of control inputs, (b) means responsive to said control inputs for selecting one of said plurality of addresses, (c) first storage means coupled to said means for selecting for storing said selected address from said means for selecting, (d) second storage means coupled to said means for selecting and capable of selectively storing an address from said first storage means or said other signals representing an initial count from said means for selecting, (e) means for loading said selected address into said first storage means, (f) means for loading said count into said second storage means, (g) means for addressing said memory at said selected address in said first storage means, (h) means for modifying said count in said second storage means and means for repeatedly addressing said memory at the address contained in said first storage means and modifying said count in said second storage means until the count in said second storage means reaches a predetermined value, (i) whereby a new address from said means for selecting is loaded into said first storage means to address a new location in said memory.