1. An integrated circuit device comprising: a first processor core; a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core; a second processor core communicatively coupled to the first processor core; and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core; wherein the integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.