1. A processor comprising: a fetch unit to fetch instructions; a decode unit to decode the fetched instructions; a plurality of execution units; a plurality of registers; and a control circuit to receive an instruction that specifies a subset of registers of the plurality of registers and a pointer to a handler function to be executed after the processor is awoken from a low-power mode to monitor for work to be performed by the processor, wherein the control circuit is to cause the subset of registers to be stored to a persistent storage prior to entry into the low-power mode, and after the processor is awoken from the low-power mode, to restore the subset of registers, jump to the handler function, and check for work to be performed.