1. A method of extracting capacitance information from an integrated circuit layout, comprising: creating a hierarchical layout database that defines a plurality of cells of elements to be created in the circuit; computing capacitance information for elements in at least one cell, wherein said capacitance information can be re-used at each placement of a cell; determining if an element of the cell for which capacitance information is computed interacts with one or more elements of another cell, combining any interacting elements of the cell in the same hierarchy level as the interacting element(s) of the other cell; and adjusting the capacitance computed to compensate for the interaction.