1. A microprocessor, having a macroarchitecture with a macroinstruction set and a microarchitecture with a microinstruction set, the microprocessor comprising: an instruction translator, configured to translate a store macroinstruction into exactly one fused store microinstruction, wherein the store macroinstruction is an instruction in the macroinstruction set that instructs the microprocessor to store data from a general purpose register of the microprocessor to a memory location, wherein the fused store microinstruction is an instruction in the microinstruction set; a reorder buffer (ROB), having a plurality of entries, configured to receive from the instruction translator the fused store microinstruction into exactly one of the plurality of entries; and an instruction dispatcher, configured to dispatch for execution a store address microinstruction and a store data microinstruction to different respective execution units of the microprocessor, in response to receiving the fused store microinstruction, wherein neither the store address microinstruction nor the store data microinstruction occupy any of the plurality of ROB entries; wherein the ROB is further configured to retire the fused store microinstruction after being notified that both the store address microinstruction and the store data microinstruction have been executed.