1. A branch predictor for use in a processor, comprising: a Level 1 branch predictor configured to generate a Level 1 branch prediction, wherein the Level 1 branch predictor includes: a bias weight array; a first predictor, including a first hash generator and a bimodal counter array; a bimodal chooser; and a multiplexer connected to the bias weight array, the first predictor, and the bimodal chooser; a Level 2 branch predictor configured to generate a Level 2 branch prediction; a match determining circuit configured to determine whether the Level 1 branch prediction matches the Level 2 branch prediction; and an override determining circuit configured to determine whether to override the Level 1 branch prediction with the Level 2 branch prediction.