1. Circuitry for producing a plurality of check symbols comprising: input circuitry configured to receive a data vector comprising a plurality of data symbols, each data symbol having a bit-depth m; a plurality of adder banks comprising: a first adder bank configured to process the data vector to produce a transformed data vector by appending a plurality of parameters to the data vector; a plurality of m additional adder banks, each configured to process a respective bit-slice of the transformed data vector to produce an output based on a respective reverse-mapped generator matrix; and a reducer bank configured to process the outputs of each of the plurality of m additional adder banks to produce the plurality of check symbols.