1. A microprocessor apparatus, for specifying a floating point format to be employed during execution of an associated floating point operation, the microprocessor apparatus comprising: translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for specifying the floating point format; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for executing the associated floating point operation according to the floating point format specified by said extended prefix.