1. A digital processor capable of simultaneously processing individual instructions from a plurality of separate instruction sequences in a time-interlaced manner comprising: A. means to furnish data to be processed; B. means to store separately each of said separate instruction sequences; C. a single arithmetic logic unit to perform arithmetic logic manipulations of data for said separate instruction sequences; D. means to provide the address to said data furnishing means of the data to be manipulated by said arithmetic logic unit in response to individual instructions automatically selected alternately from said plurality of instruction sequences; E. means to cause said arithmetic logic unit to execute selectively the instructions of said separate instruction sequences in a time-interlaced manner; F. means to deliver individual instructions to said arithmetic logic unit automatically selected alternately from said plurality of separate instruction sequences; G. means to automatically select simultaneously with the execution by said single arithmetic logic unit of an instruction selected from one of said instruction sequences the next individual instruction of another one of said instruction sequences to be executed by said single arithmetic unit; and H. means to store separately the results of manipulations made by said single arithmetic logic unit in response to individual instructions from each of said separate instruction sequences for later recall for further manipulation by said arithmetic logic unit in response to a subsequent instruction from one of said instruction sequences.