1. A system for accessing cached data comprising: an address generator, the address generator to provide first and second portions of a linear address for the cached data on first and second phases, respectively, of a clock cycle; a first translation lookaside buffer (TLB) coupled to the address generator, the first TLB including a plurality of address translation entries to determine a tentative physical address for the cached data according to the provided linear address; and a second TLB coupled to the address generator and the first TLB, the second TLB including a plurality of address translation entries each having associated validity data to determine a validated physical address for the cached data, the second TLB to provide the validated physical address to the first TLB to confirm the tentative physical address.