1. A memory to be accommodated among macrocells of a microcontroller so as to reduce needed circuit area, said memory comprising: a matrix of memory cells organized into rows and columns, the number of columns defining the matrix height and the height being variable determined according to a number of memory address bits intended for selecting the row and column of the matrix, the width of the matrix being dependent on an overall desired capacity of the memory; a column decoder and a row decoder; wherein the selection of a memory column location is derived from a predetermined number of least significant bits of the memory address, while the selection of a row is derived from the remaining most significant bits of the same memory address with a predetermined number of memory addresses defining residuaries having no corresponding locations in the memory and are used as additional rows; and a pre-decode circuit acting on the memory addresses to check whether the codes of said predetermined number of bits relate to memory locations which belong to the residuaries.