1. A trace and debug method for a processor, the processor having a processor core, a cache and a timer, the processor core having a normal mode, a debug mode and a program counter (PC) to record a subsequent instruction address, the cache being coupled to the processor core through an address bus and a data bus, the timer being connected to the processor core to offer a timer function to an operating system for performing a context switch, the method comprising the steps: (A) monitoring the program counter (PC); (B) determining whether the processor core executes a non-successive instruction in accordance with an address data of the PC, and if the processor core executes a non-successive instruction, executing steps (C)˜(E); (C) generating a trace break event to set the processor core from the normal mode to the debug mode; (D) fetching a value of the program counter and a state of the processor core; and (E) sending the value and the state to a host to accordingly form a trace and debug message with respect to the processor core.