1. A logic circuit generation device that receives an input of a program in which an operation description, as a flow of a series of processes of hardware for a circuit design, is written, the program including a top-level function of a logic circuit generation target, and generates a logic circuit description, the logic circuit generation device comprising: a control flow graph generation unit that generates a control flow graph from the top-level function including no loop processing part and no function call instruction; a control flow degenerate conversion unit that removes all condition branch edge instructions from the control flow graph that includes, for each variable, a single assignment instruction to the variable, and thereby generates a control flow degenerate program as a program in which a control flow is degenerated; a data flow graph generation unit that generates a data flow graph from the control flow degenerate program, by using each instruction in the control flow degenerate program as a node, and adding a directed edge from an assignment instruction to each variable to an instruction that refers to the variable; and a logic circuit description output unit that generates a logic circuit description expressing a sequential circuit in which the directed edge of the data flow graph corresponds to wiring of a logic circuit, and the node of the data flow graph corresponds to a computing element of the logic circuit, wherein a state variable expressing a state of the sequential circuit is represented in the program as a local variable or a static variable of a high-order hierarchy function calling the top-level function, and a value of the state variable before an assignment instruction to the state variable is executed expresses a current state of the sequential circuit, and a value of the state variable after the assignment instruction to the state variable is executed expresses a next state of the sequential circuit.