1. A computer implemented method for Fast Fourier Transform (FFT) operations in a fixed point processor, the computer implemented method comprising: accessing input data for at least one set of add operations using a plurality of vector register files and a scratch state memory; calculating the at least one set of add operations within at least one FFT butterfly using the input data controlled by a mode register, wherein the at least one FFT butterfly comprises a plurality of FFT stages; and performing dynamic range sensing by determining a data range on an FFT stage of the plurality of FFT stages for a next FFT stage; and selecting scaling of data on the next FFT stage based on the data range.