1. A microprocessor apparatus, for selectively controlling write back of condition codes, comprising: translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for disabling write back of the condition codes, the condition codes corresponding to a result of a prescribed operation; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for generating said result, and for disabling write back of the condition codes.