1. A computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process, the method comprising: decomposing a circuit design layout file to produce decomposed layout files in a computer, wherein each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process; retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files; determining in the computer that a combination of layout files includes a spacing conflict; and resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.