1. A method of managing a flash memory array comprising: at a first time, mapping a plurality of memory states of a memory cell to a first voltage threshold window, wherein individual ones of the plurality of memory states are mapped to voltage sub-ranges of the first voltage threshold window; and at a second time, mapping the plurality of memory states of the memory cell to a second voltage threshold window, wherein individual ones of the plurality of memory states are mapped to voltage sub-ranges of the second voltage threshold window, the second voltage threshold window being wider than the first voltage threshold window so that at least one memory state is mapped into different sub-ranges in the first and second voltage threshold windows.