1. A method of controlling a computer, the computer comprising: a multicore processor having a function of hardware-assisted virtualization; a memory; a first processor core group of processor cores of the multicore processor where the hardware-assisted virtualization is disabled; a second processor core group of processor cores of the multicore processor where the hardware-assisted virtualization is enabled; a first memory group comprising a partial area of the memory; and a second memory group comprising a remaining area of the memory, the method comprising: a first step of allocating the first processor core group and the first memory group to a first OS, and booting the first OS; a second step of allocating the second processor core group and the second memory group to a virtualization module, which runs a virtual machine, and booting the virtualization module; a third step of allocating, by the virtualization module, a given area of the memory and given processor cores of the second processor core group to the virtual machine, and booting a second OS; a fourth step of registering, by the virtualization module, interrupt handlers for resetting the second processor core group; a fifth step of obtaining and keeping, by the first OS, identifiers of the processor cores that belong to the second processor core group when the virtualization module is booted; a sixth step of monitoring, by the first OS, an operation state of the virtualization module and determining whether or not the virtualization module is to be rebooted, based on given conditions; a seventh step of issuing, by the first OS, when the virtualization module is to be rebooted, resetting interrupt to the processor cores belonging to the second processor core group that are associated with the kept identifiers; an eighth step of receiving, by the second processor core group that is allocated to the virtualization module, the resetting interrupt and executing the interrupt handlers to reset the processor cores of the second processor core group; and a ninth step of issuing, by the first OS, startup interrupt to the second processor core group.