1. A device for decoding data using a low-density parity check (LDPC) decoder, the LDPC decoder utilizing a code structure that supports 2N check nodes processed in parallel, the device comprising: an edge memory configured to have a first bank of memory partitions to store extrinsic information for edges corresponding to a first set of N check nodes, the first set of N check nodes corresponding to odd-numbered check nodes of the 2N check nodes, and to have a second bank of memory partitions to store extrinsic information for edges corresponding to a second set of N check nodes, the second set of N check nodes corresponding to even-numbered check nodes of the 2N check nodes, the first and second banks of the edge memory being independent from each other; a first processing module configured to process the first set of N check nodes; and a second processing module configured to process the second set of N check nodes, the first and second sets of N check nodes being processed in parallel by concurrently accessing extrinsic information from the first and second banks of the edge memory in connection with the first and second sets of N check nodes, respectively.