1. A processor comprising: a plurality of multithreaded cores; one or more of the plurality of multithreaded cores to perform out-of-order instruction execution of instructions for a plurality of threads, one or more of the plurality of multithreaded cores comprising: instruction fetch logic to fetch instructions of one or more of the plurality of threads, an instruction decode unit to decode the instructions, register renaming logic to rename one or more registers within a register file, an instruction cache to cache instructions to be executed, a data cache to cache data, a level 2 (L2) cache unit to cache instructions and data, and an execution unit to execute a transactional execution region of instructions, the execution unit having a first instruction, the first instruction to test status related to the transactional execution region.