1. A memory system comprising: a static random access memory array, the static random access memory array organized in rows and columns, wherein a column comprises a first plurality of memory cells coupled to a first bit line and a row comprises a second plurality of memory cells; a non-volatile memory array separate from the static random access memory array, the non-volatile memory array having a plurality of non-volatile memory cells organized in rows and columns, wherein a column of non-volatile memory cells comprises a third plurality of non-volatile memory cells coupled to a second bit line different than the first bit line and a row comprises a fourth plurality of non-volatile memory cells, and wherein the fourth plurality of non-volatile memory cells is an integer multiple of the second plurality of memory cells, wherein the integer multiple is greater than one; and column logic coupled between the columns of to the static random access memory array and the columns of to the non-volatile memory array, the column logic for controlling read and write accesses to either one of only the static random access memory or to only the non-volatile memory array, and for controlling read and write data transfers directly between the static random access memory array and the non-volatile memory array.