1. A data processing unit coupled to a memory and including general registers within a scratchpad memory for storing operands, an instruction buffer for storing a number of program instructions fetched from said memory and an instruction fetch and execution apparatus for executing instruction fetch and instruction execusion operations under microprogram control during minor and major clock pulse cycles wherein each program instruction requires execution of a predetermined number of microinstructions during a corresponding number of minor clock pulse cycles which comprise a major clock pulse cycle, said apparatus comprising: an addressable control memory having a plurality of locations for storing a plurality of microinstructions, a first one of said microinstructions being coded to specify a number of microoperations, one required to terminate the execution of a first one of said program instructions and another microoperation for beginning the processing of next one of said program instructions and a last one of said microinstructions being coded to specify a number of microoperations, one microoperation required for execution of said first one of said program instructions and another microoperation for initiating the processing of a next instruction; first means coupled to said control memory and operative in response to said last one of said microinstruction read out during a last minor clock pulse cycle of said first instruction to execute said one microoperation for completing the major cycle of operation of said first one of said program instructions; second means coupled to said control memory and operative in response to said last one of said microinstructions during said last minor clock pulse cycle to execute said another microoperation for initiating the processing of said next instruction in parallel with the execution of microoperations of said first one of said program instructions; third means coupled to said control memory and operative in response to said first one of said microinstructions during a first minor clock pulse cycle of beginning of a major clock pulse cycle of said next one of said program instructions to execute said another microoperation for completing an operation required in the execution of said second one of said program instructions; and, fourth means coupled to said control memory and operative in response to said first one of said microinstruction during said first minor clock pulse cycle to execute said one microoperation for terminating the execution of said first one of said program instructions in parallel with the execution of said next one of said program instructions.