1. A machine implemented method comprising: analyzing a set of shader execution threads from the shader unit of a graphics pipeline to find a subset of threads that include logic operations on the same output register; merging the subset of threads that include logic operations that write to a common output register; combining shader unit instructions from multiple threads in a set of threads into a combined shader unit thread; dispatching the set of shader execution threads to an array of graphics engine shader cores; and executing the instructions in the set of threads using one or more graphics engine shader cores.