1. A system, comprising: a central processing unit including a primary address decode logic module and a plurality of diagnostic registers, wherein the primary address decode logic module includes inputs from an address bus, inputs from register select lines, and an enable input port; a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an error interrupt signal line, an output coupled to the enable input port of the primary address decode logic module, and a clock input; and an address decode logic module having an input receiving a memory address and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input of the data flip-flop.