1. Apparatus for creating, during execution of a computer program having a first and a second sequence of instructions, each instruction in said first and second sequences having an instruction address and at least some of said instruction addresses of said second sequence being the same as some of said instruction addresses of said first sequence, an entry point into a set of stored parallel subsequences of instructions created from said first sequence of instructions, said parallel subsequences each having a beginning and being executable asynchronously all in parallel on separate processing elements, said first sequence defining a monotonically increasing sequence number associated with each said instruction in said first sequence, said sequence numbers being associated with said instructions in said parallel subsequences of instructions, said entry point allowing said set of parallel subsequences to be entered and executed asynchronously in parallel in place of a corresponding portion of said second sequence starting at a point other than at said beginning of said each parallel subsequence, comprising: means for storing a subset of said instruction addresses of said first sequence and said sequence numbers associated with said stored instruction addresses; comparison means for detecting, during execution of said second sequence of instructions, a coincidence of an instruction address of said second sequence of instructions with an instruction address in said stored subset of instruction addresses; and means responsive to said comparison means for creating an entry point into said set of parallel subsequences which corresponds to said detected coinciding instruction address.