1. An apparatus, comprising: a memory module, wherein the memory module is a reconfigurable hard macro and a first portion of the memory module comprises: a data input multiplexer coupled to select between cascaded data and direct/bused data; a memory coupled to receive output from the data input multiplexer for storage therein; a register input multiplexer coupled to select between read data from the memory and the cascaded data; a register coupled to receive output from the register input multiplexer; a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register; and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.