1. A multithreaded processor comprising: a plurality of hardware thread units; an instruction decoder coupled to the thread units for decoding instructions received therefrom; and a plurality of execution units for executing the decoded instructions; wherein the multithreaded processor is configured for controlling an instruction issuance sequence for a plurality of threads associated with respective ones of the hardware thread units; wherein on a given processor clock cycle only a designated one of the threads is permitted to issue one or more instructions, the designated thread that is permitted to issue instructions varying over a plurality of clock cycles in accordance with the instruction issuance sequence; and wherein the instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.