1. A cache coherent data processing system, comprising: at least first and second coherency domains each including at least one processing unit, wherein said first coherency domain includes a first cache memory and said second coherency domain includes a coherent second cache memory; wherein said first cache memory within said first coherency domain of said data processing system holds a memory block in a storage location associated with an address tag and a coherency state field; and wherein said coherency state field is set to a state that indicates that said address tag is valid, that said storage location does not contain valid data, and that said memory block is possibly cached outside of said first coherency domain.