1. A multi-core processor system, comprising: a first processor core configured to process computer instructions at a first rate; a cache memory corresponding to the first processor core; a second processor core configured to process the computer instructions at a second rate that is different than the first rate; a first shared memory accessible by the first processor core and the second processor core; a core-switch manager configured to switch execution of the computer instructions from the first processor core to the second processor core while the computer instructions are being executed by the first processor core, the switching comprising: causing the first processor core to activate a processor core timer event; causing the second processor core to read a context state of the first processor core from the first shared memory; and responsive to receiving a signal from the second processor core to clear the processor core timer event, initiate flushing of the cache memory corresponding to the first processor core and begin execution of the computer instructions on the second core; or responsive to the processor core timer event lapsing without receiving the signal from the second processor core to clear the processor core timer event, causing the first processor core to resume execution of the computer instructions; and a core profiler configured to generate system profile data to determine when the core-switch manager initiates the switching of the execution of the computer instructions from the first processor core to the second processor core.