1. A method of manufacturing an on-chip bypass capacitor on a chip with at least one cell capacitor, the on-chip bypass capacitor including a plurality of capacitor arrays and each capacitor array including a plurality of capacitors, said method comprising: forming a first layer common to the at least one cell capacitor and each of the plurality of capacitor arrays, the first layer connecting each of the plurality of capacitors of each capacitor array in parallel; and forming a second layer common to the at least one cell capacitor and each of the plurality of capacitor arrays, the second layer connecting the plurality of capacitor arrays in series.