1. A method of enabling the generation of reset signals in an integrated circuit, the method comprising: receiving, in a design tool, information related to reset ports for a plurality of intellectual property cores; providing an intellectual property core comprising a reset circuit adapted to generate a plurality of reset signals for the plurality of intellectual property cores; and generating, by the design tool, configuration data enabling programmable interconnects to couple a first reset signal of the plurality of reset signals to a first intellectual property core of the plurality of intellectual property cores and a second reset signal of the plurality of reset signals to a second intellectual property core of the plurality of intellectual property cores.