1. A method for triangulating multiple failed processing elements, the method comprising: simultaneously scanning multiple processing elements of a chip circuit in a parallel scan mode and a delayed scan mode; and triangulating one or more failed processing elements of the chip circuit by: comparing a first parity value representing a parity of a first set of scan outputs scanned out from all processing elements in the parallel scan mode against a first expected value; and comparing a second parity value representing a parity of a second set of scan outputs scanned out from all processing elements in the delayed scan mode against a second expected value; wherein, in the parallel scan mode, the multiple processing elements are scanned simultaneously and in parallel; and wherein, in the delayed scan mode, at least one processing element of the multiple processing elements is scanned after one or more clock delays has elapsed.