1. A unified microprocessor pick queue comprising: control circuitry; and an array configured to dynamically allocate an entry of a plurality of entries for an instruction, wherein each entry of said entries includes a picked field and a trigger field, wherein the picked field indicates a corresponding instruction is eligible to be picked for issue, and the trigger field indicates a result of the instruction will be available in M clock cycles; wherein for a first instruction dependent upon a second instruction whose results are not yet available, in response to detecting the second instruction has asserted picked and trigger fields prior to said results being scheduled to be available, the circuitry is configured to: determine the first instruction is eligible to be picked for issue responsive to detecting: the first instruction corresponds to a first class of instructions comprising instructions with a same source and destination type, the first class of instructions being floating point instructions; the second instruction is a floating point instruction executable by a floating point unit; and the first instruction has a first latency from the second instruction associated with the first class; and determine the first instruction is eligible for stalling prior to being picked for issue responsive to detecting: the first instruction corresponds to the first class of instructions; the second instruction is a floating point instruction executable by an integer execution unit; and the first instruction does not have the first latency from the second instruction.