1. A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in said set of test patterns determining if a single stuck-at fault could cause said failing test pattern and determining a node on which a defect causing said single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of said selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from said first set of sets of nodes.