1. An arrangement of controlling instruction issue timing in a vector processor which includes a memory means which is physically divided into N memory units (N is a positive integer) and logically divided into a plurality of memory blocks which are shared by said N memory units, a vector being written into or read out of one of said plurality of memory blocks using one of consecutive N time slots which are cyclically generated, said arrangement comprising: first means for decoding an instruction applied thereto and determining whether said instruction is a memory write instruction or a memory read instruction, said first means further receiving one of said plurality of memory blocks which is designated by said instruction; second means coupled to said first means and informed therefrom that said instruction has been determined to be said memory write instruction, said second means generating a first control signal which enables said memory write instruction to be applied to said memory means, said first control signal further indicating one of said plurality of memory blocks which is designated by said memory write instruction; third means coupled to said first means and informed therefrom that said instruction has been determined to be said memory read instruction for controlling memory read operations; fourth means for generating sequentially said N time slots and selecting available time slots among said N time slots and applying respectively one of the selected available time slots to said second and third means; fifth means coupled to said second means for receiving and storing a selected time slot applied to said second means; and sixth means coupled to said third, fourth and fifth means and being responsive to said first control signal for counting a predetermined time duration when said memory read instruction indicates a read operation from one of said memory blocks which is also indicated as a memory block of a write operation of a preceding memory write instruction, said sixth means being responsive to count-up said predetermined time duration for applying a second control signal to said third means when said selected time slot matches one of said N time slots generated by said fourth means, wherein said third means, responsive to said second control signal, generates a third control signal enabling execution of said memory read instruction using one of said N time slots other than said selected time slot.