1. An apparatus, comprising: a first memory comprising a context buffer; a processor core to execute threads based on context information stored in registers of the processor core; and a memory controller circuit to selectively move a portion of a first context for a first thread between the context buffer and the registers based on a latency of the first thread, wherein the portion includes less than all of the first context for the first thread, and wherein the portion of the first context is predicted based on portions of contexts previously used by one or more other threads.