1. A system comprising: a processor having a vector processing mode and a multithreading mode, the processor being a vector processor and being configured to operate on one thread per cycle in the multithreading mode, and the processor comprising: one or more program counter registers together comprising a plurality of program counters, each program counter register of the one or more program counter registers being vectorized into a corresponding subset of the plurality of program counters, and each program counter in the plurality of program counters of one or more program counter registers representing a distinct corresponding thread of a plurality of threads; wherein the number of threads in the plurality of threads is limited by the number of program counters in the plurality of program counters of the one or more program counter registers; the processor configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle; an instruction buffer comprising a plurality of instructions; wherein a first program counter in the plurality of program counters references a first instruction in the instruction buffer for execution by the processor in a first thread of the plurality of threads; wherein a second program counter in the plurality of program counters references a second instruction in the instruction buffer for execution by the processor in a second thread of the plurality of threads, the first instruction being different from the second instruction; wherein the processor is configured to skip, in the round robin cycle, a program counter lacking readiness based on a ready bit setting and determine a validity of each data element to be used in an operation for an active thread of the plurality of threads, said validity indicative of data being fetched from memory to be loaded into a data element, wherein responsive to a determination of an invalid operation, proceed to a next operation without incrementing the second program counter, and responsive to no invalid operation, process one or more output vectors and output a result.