1. A method comprising steps of: (a) receiving as input an integrated circuit design comprising a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; (f) re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.