1. An apparatus, comprising: an array of memory cells; and sensing circuitry coupled to the array through a shift circuitry intermediate in the pair of complementary sense lines, and comprising: a sense amplifier directly coupled to a pair of complementary sense lines via a first input node and a second input node; and a compute component coupled to the sense amplifier and comprising a dynamic latch, wherein the sensing circuitry is configured to: perform a logical operation; and initially store a result of the logical operation in the sense amplifier, and wherein the shift circuitry is configured as a multiplexor capable of selecting from among at least 3 inputs to the sensing circuitry.