1. A method for designing a system to be implemented on a target device, the method comprising: performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system; performing a second synthesis run on the entire design of the system with a second setting where the second synthesis is performed in parallel with the first synthesis to generate a second cell netlist for the entire design of the system; and generating a merged cell netlist that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist, wherein at least one of the performings and generating is conducted using a processor.