1. An apparatus for controlling memory access, comprising: at least one processor, wherein the processor further comprises: at least the ability to issue commands; and at least an ability to embed at least a flag into the commands associated with an assigned tag number; a plurality of communication ports, wherein a plurality of commands are input by the at least one processor through at least a first communication channel of a plurality of communication channels; a tag queue, wherein the tag queue assigns the assigned tag number to each command of the plurality of commands to generate a plurality of tagged commands; and a command queue for storing the plurality of tagged commands, wherein the command queue further comprises an ability to sort the commands.