1. An apparatus for timing recovery, applied to a communication system, comprising: a modulo processing circuit for receiving an input signal for performing a modulo operation; a slicer for rounding an output signal of the modulo processing circuit into an integer signal; a de-modulo processing circuit coupled to the slicer for performing a de-modulo operation on the output signal of the slicer to generate a de-modulo output signal; wherein the de-modulo operation indicates an inverse function of the modulo operation; wherein a value of the output signal of the modulo processing circuit is .+−.2*M*k; M is a modulo of the modulo processing circuit; and k is a non-negative integer; and circuitry configured to use the value in a timing recovery operation.