1. A method of executing instructions in a processor of the type including an auxiliary execution unit, the method comprising: receiving first and second instructions from an instruction stream, wherein the first and second instructions are members of an instruction set architecture defined for the processor, and wherein each instruction in the instruction set architecture includes a primary opcode portion and an operand portion; in response to receiving the first and second instructions: decoding the first and second instructions by determining primary opcodes for each of the first and second instructions from the respective primary opcode portions thereof and determining at least one operand for each of the first and second instructions from the respective operand portions thereof; storing a primary opcode in a primary opcode register in response to decoding the first instruction; and storing a count in a count register in response to decoding the second instruction; and after receiving the first and second instructions, receiving a plurality of auxiliary instructions from the instruction stream, wherein a number of auxiliary instructions in the plurality of auxiliary instructions is equal to the count stored in the count register by the second instruction; and for each auxiliary instruction among the plurality of auxiliary instructions: determining that the count register stores a non-zero value; decoding a primary opcode for such auxiliary instruction based upon the primary opcode stored in the primary opcode register; decoding a secondary opcode for such auxiliary instruction from a secondary opcode portion of such auxiliary instruction, wherein the secondary opcode portion is different from the primary opcode portion; decoding a plurality of operands for such auxiliary instruction by concatenating at least one most significant bit for each operand encoded in the primary opcode portion of such auxiliary instruction with a plurality of least significant bits for each operand encoded in the operand portion of such auxiliary instruction; executing such auxiliary instruction in the auxiliary execution unit using the primary opcode, secondary opcode and plurality of operands decoded from such auxiliary instruction; and decrementing the count register.