1. A processor system, comprising: an image processing unit including a plurality of arithmetic units capable of performing arithmetic processings in parallel; a storage which stores data that said plurality of arithmetic units use for arithmetic processings; a plurality of DMA controllers which perform data transfer between said plurality of arithmetic units, and between said plurality of arithmetic units and said storage in parallel with processings of a host processor; a first DMA control circuit which controls start-up of said plurality of arithmetic units and said plurality of DMA controllers in parallel with processings of said host processor; and a second DMA control circuit which communicates with said host processor, controls said first DMA control circuit, and performs data processing with the image processing units wherein the first DMA control circuit further comprises, a DMA register which stores setting information of the plurality of DMA controllers, a sync register which stores an operational status of the plurality of DMA controllers and the plurality of arithmetic units, a sync register controller which controls the sync register, and a DMA issuance unit which sends start-up signals to the plurality of DMA controllers, wherein the second DMA control circuit checks the sync register to detect whether the host processor is ready to perform a DMA transfer, and then controls a storing operation of the setting information of the DMA controllers into the DMA register, and then instructs the DMA issuance unit to set information stored in the DMA register to the plurality of DMA controllers.