1. An apparatus comprising: a multi-level memory cell; a plurality of latches coupled with the multi-level memory cell, the plurality of latches including a most significant bit (MSB) latch, a least significant bit (LSB) latch, and an auxiliary latch; and a controller coupled to the multi-level memory cell and the plurality of latches and configured to transfer one or more values between the auxiliary latch and the MSB latch and between the auxiliary latch and the LSB latch while programming the multi-level memory cell; wherein the controller is configured to load an LSB of a logic value to be associated with the multi-level memory cell to the LSB latch from the MSB latch while programming the multi-level memory cell.