1. A processor, operable to execute instructions on a predicated basis, comprising: a series of predicate registers, each switchable between at least respective first and second states and each assignable to one or more predicated-execution instructions; a control information holding unit which holds items of control information corresponding respectively to said predicate registers of said series; and a plurality of operating units, corresponding respectively to said predicate registers, each having a first control input connected to said control information holding unit for receiving the control-information item corresponding to the operating unit's own corresponding predicate register and also having a second control input connected for receiving the control-information item corresponding to a further one of said predicate registers, and operable to perform a state determining operation in which said state of its said own predicate register is determined in dependence upon the received control-information items, said operating units of the plurality being operable in parallel with one another to perform respective such state determining operations.