1. A method of generating simulation code of a circuit description having at least a first plurality of modules described with a first hardware descriptive language (HDL) and at least a second plurality of modules described with a second HDL different from the first HDL, the method comprising: performing, on at least one programmed processor, operations including: generating a simulation dataflow graph of the circuit description; and generating simulation code from the dataflow graph, the simulation code modeling execution of modules in a data-driven manner according to the simulation dataflow graph, the generating of the simulation code including: for a signal that is propagated from a first module of the first plurality of modules to a second module of the second plurality of modules and propagated from the second module to a third module of the first plurality of modules, wherein the second module is a sub-module of the first module, and the third module is a sub-module of the second module in a hierarchy of modules: creating a first HDL signal representation and storing the first HDL signal representation in a first memory location and having a format compatible with the first HDL; creating a second HDL signal representation and storing the second HDL signal representation in a second memory location and having a format compatible with the second HDL for the signal; and for instances of the first, second, and third modules of the circuit description in the simulation dataflow graph: mapping ports of instances of the first and third modules to the first HDL signal representation stored in the first memory location; and mapping a port of an instance of the second module to the second HDL signal representation stored in the second memory location.