1. An apparatus comprising: a processor; an associative cache configured to store a plurality of instructions in a plurality of selectively powered ways; and an instruction fetch unit configured to fetch, for execution by said processor, a current instruction from said associative cache in accordance with an instruction pointer; wherein said processor is configured to identify a way of said associative cache in which a future instruction that is a predetermined plurality of instructions ahead of said current fetched instruction is located, using way information for the future instruction that is associated with said current fetched instruction and retrieved together with said current fetched instruction, and said identified way of said associative cache is selectively powered at a time corresponding to when that said future instruction needs to be fetched by said instruction fetch unit.