1. A computer implemented circuit synthesis system, comprising: memory configured to provide a database and operative to store a netlist including nets of an integrated circuit under design; an automatic test pattern generation (ATPG) algorithm operative to design and test an integrated circuit design; and processing circuitry configured to reduce layout area used during scan insertion and operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port.