1. A dual port register file comprising: a clock signal; a memory array comprising: a group of rows of memory array registers; wherein each memory array register in the memory array comprises: a multiplexer, the multiplexer having first and second data inputs, a select input and a data output; a memory cell, the memory cell having a data input connected to the output of the multiplexer, a data output connected to the second data input of the multiplexer and an input connected to the clock signal; synchronous write address decode logic having inputs and outputs, wherein the synchronous write address decode logic outputs select which row from the group of rows of memory array registers data is written; a write port, the write port comprising: pipelined synchronous data registers having inputs and outputs wherein the outputs of the pipelined synchronous data registers are connected to the first data inputs of the memory array registers; pipelined synchronous bit-write registers having inputs and outputs wherein outputs of the pipelined synchronous bit-write registers select which data inputs of the multiplexers are written to the inputs of the memory cells; pipelined synchronous write address registers having inputs and outputs wherein the outputs are electrically connected to the inputs of the write address decode logic, wherein the pipelined synchronous write address registers store a write address; a pipelined synchronous write-enable register, wherein the pipelined synchronous write-enable register selects when the data from the pipelined synchronous data registers is written to the memory array; a read port, the read port comprising an asynchronous read address; asynchronous read address decode logic having inputs and outputs wherein the outputs from the asynchronous read address decode logic select which row of memory array registers is read from the memory array, wherein an asynchronous read address is electrically connected to the inputs of the asynchronous read address decode logic.