1. An advanced processor, comprising: a plurality of processor cores each having a data cache; a data switch interconnect coupled with the data cache of each of the plurality of processor cores, in which the data switch interconnect passes memory related information among the plurality of processor cores; and a level 2 cache coupled to the data switch interconnect which allows sharing of dirty cache lines across the plurality of processor cores, wherein the data switch interconnect includes a ring arrangement with a plurality of ring elements coupled to a respective data cache of the plurality of processor cores and a respective portion of the level 2 cache.