1. An apparatus, comprising: a power estimation circuit coupled to a first processor and a second processor, wherein the power estimation circuit is configured to receive high power instruction information from the first processor and the second processor and generate a power estimate dependent upon the received high power instruction information from the first processor and the second processor; a table configured to store one or more pre-determined power threshold values; a comparator configured to compare the power estimate to the at least one of the stored pre-determined power threshold values and generate a comparison result signal dependent upon the comparison; and a finite-state machine coupled to the first processor and the second processor, wherein the finite-state machine is configured adjust a throttle level of the first processor and the second processor dependent upon the comparison result signal.