1. A disk subsystem, comprising: a first cache board which comprises a first memory controller connected to a first volatile memory and a first non-volatile memory respectively, a first processor which is connected to the first memory controller, and a first battery which temporarily supplies power when power is shut off; a second cache board which comprises a second memory controller connected to a second volatile memory and a second non-volatile memory respectively, a second processor which is connected to the second memory controller, and a second battery which temporarily supplies power when power is shut off; and a transmission channel which communicably connects the first cache board and the second cache board, wherein, if power which is supplied to the first cache board is shut off, the first processor saves data which is stored in the first volatile memory to the first non-volatile memory and saves first management information for managing data which is stored in the first volatile memory and the second volatile memory to the first non-volatile memory, by way of co-operation with the first memory controller while power is being supplied from the first battery, wherein, if power which is supplied to the first cache board is restored, the first processor restores first data among data which has been saved to the first non-volatile memory and second data which has been transferred via the transmission channel, to the first volatile memory, on the basis of the first management information and transfers the first data to the second cache board via the transmission channel, by way of co-operation with the first memory controller, wherein, if power which is supplied to the second cache board is shut off, the second processor saves data which is stored in the second volatile memory to the second non-volatile memory and saves second management information for managing data which is stored in the first volatile memory and the second volatile memory to the second non-volatile memory, by way of co-operation with the second memory controller while power is being supplied from the second battery, and wherein, if power which is supplied to the second cache board is restored, the second processor restores the second data among data which has been saved to the second non-volatile memory and the first data which has been transferred via the transmission channel, to the second volatile memory, on the basis of the second management information and transfers the second data to the first cache board via the transmission channel, by way of co-operation with the second memory controller.