1. A semiconductor device, comprising: a semiconductor substrate; isolation features to separate different regions on the substrate; a p-type field-effect transistor (pFET) core region having a first gate stack on the substrate, the first gate stack including an interfacial layer, a capping layer of a first material on the interfacial layer, and a high k (HK) dielectric layer on the capping layer of the first material; an input/output pFET (pFET IO) region having a second gate stack on the substrate, the second gate stack including a dielectric layer, an interfacial layer on the dielectric layer, a capping layer of the first material on the interfacial layer, and a HK dielectric layer on the capping layer of the first material; an n-type field-effect transistor (nFET) core region having a third gate stack on the substrate, the third gate stack including an interfacial layer, a capping layer of a second material on the interfacial layer, and a HK dielectric layer on the capping layer of the second material; an input/output nFET (nFET IO) region having a fourth gate stack on the substrate, the fourth gate stack including a dielectric layer, an interfacial layer on the dielectric layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer on the capping layer of the second material; and a high-resistor region having a fifth gate stack on the substrate, the fifth gate stack including an interfacial layer, a capping layer of the second material on the interfacial layer, and a HK dielectric layer on the capping layer of the second material.