1. A memory system connectable to a host device, the memory system comprising: a host interface configured to receive a read command and a write command; a first non-volatile memory configured to read data in response to the read command and to store data in response to the write command; a debug unit configured to collect debugging information; and a processor configured to execute firmware to control the memory system, the firmware having a function of receiving a debug command and a function of setting a buffer address to the debug unit, the buffer address indicating a buffer area allocated on a memory in the host device, wherein the debug unit is capable of outputting the debugging information to the buffer area through the host interface when the processor executes the firmware.