1. A multiprocessor computer system comprising: a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines, the state information comprising data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state; a plurality of processors, at least one cache memory associated with each one of the plurality of processors; a system memory shared by the plurality of processors; and at least one bus interconnecting the system memory with the plurality of cache memories and the plurality of processors.