1. A method of testing memory cells of a Flash memory device having a built-in self test circuit, the method comprising: providing a BIST circuit having a BIST interface adapted to adjust a test condition; providing the memory cells of the Flash memory device; providing the BIST circuit adapted to test the flash memory; communicating to the BIST interface one or more global variables associated with the test condition; adjusting or establishing the test condition used by the BIST circuit based on the values represented by the global variables; performing one or more test operations on the flash memory in accordance with the adjusted or established test condition; and reporting the results of the memory test operations performed.