1. A resistive random access memory cell formed in an integrated circuit comprising: a first resistive random access memory device including an anode and a cathode; a second resistive random access memory device including an anode and a cathode, the anode of the second resistive random access memory device connected to the anode of the first resistive random access memory device; a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node; and at least one switch transistor having a gate connected to the anodes of the first and second resistive random access memory devices.