1. An electronic design automation method, comprising: creating a functional coverage model; running random simulations from at least one seed; merging, through a computer system, coverage logs of the functional coverage model generated by verification of a hardware description language circuit design, as the coverage logs are generated, without waiting for all coverage logs of pending verification; and responsive to said merging, the computer system analyzing the merged coverage logs, refining the functional coverage model, and deleting at least part of previous coverage logs.