1. A computer-implemented method for generating a layout of a circuit, the method comprising: invoking the computer to receive a parameterized cell layout having a plurality of attributes; receiving data associated with an attribute of the parameterized cell layout via the computer; converting the parameterized cell layout, via the computer, to an associated symbolic cell layout in accordance with the received data, said symbolic cell layout being an abstract view of the parameterized cell layout; displaying the symbolic cell layout; and generating a second layout of the parameterized cell from the symbolic cell layout, said layout to be manufactured.