1. A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, said method comprising: concurrently holding a value corresponding to at least one program instruction in an upper level instruction cache and a lower level cache of the processing unit; receiving, at the lower level cache, an operation requiring invalidation of the value; and in response to said receiving step, sending an invalidation transaction identifying the value from the lower level cache to the upper level instruction cache.