1. A method of providing linear and dual address spaces within a memory, comprising: providing a digital signal processor (DSP) engine, an arithmetic logic unit (ALU) and a memory; providing separate X and Y address generation units for generating addresses to the memory; the X address generation unit being configured to generate addresses to all of the memory space when processing a non-digital signal processor (DSP) engine instruction and to a first portion of the memory when processing a DSP engine instruction; the Y address generation unit being configured to generate addresses to a second portion of the memory space when processing a DSP engine instruction and to none of the memory space when processing a non-digital signal processor (DSP) engine instruction; and providing an instruction decoder for decoding instructions, the instruction decoder activating the X address generation unit for ALU instructions and the instruction decoder activating the X and Y address generation units for DSP engine instructions.