1. A cryptography accelerator, the accelerator comprising: a first hash core operable to perform a plurality of rounds of hash computations on input data to derive processed data; a persistent memory containing a plurality of instruction sets, the plurality of instruction sets providing information for the first hash core on operations to perform on input data and intermediate data during the plurality of rounds of hash computations; and a temporary memory coupled to the first hash core, the temporary memory operable to hold input data and intermediate data.