1. A method comprising: communicating a request for handling of a fault or exception occurring in an accelerator to a first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer; and handling the fault or exception in the first instruction sequencer responsive to the request to obtain an address translation according to a memory paging mechanism of the first instruction sequencer and translating the address translation according to a memory paging mechanism of the accelerator.