1. A method of performing statistical timing analysis of a logic design, including effects of signal coupling, the method comprising the steps of: performing a deterministic analysis using a processor to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design exhibiting coupling, assuming worst case aggressor conditions; performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair; using the statistical effective capacitance to determine timing data used in the statistical timing analysis; and conducting an update process of the timing data and the statistical timing analysis due to the effect of the coupling capacitance on a particular net to reduce pessimism.