1. A method for re-downloading data to a Field Programmable Gate Array (FPGA), characterized by use of Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit to determine if the CPLDs use the set of connectors to download data according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, wherein a write-to-NVRAM operation for data is determined when the detection state is a first logic level and data is written from the NVRAM to the FPGA when the detection state is a second logic level.