1. A systolic array in an integrated circuit, comprising: boundary cells oriented along a main diagonal of the systolic array; internal cells disposed in a corner, wherein the systolic array is a triangular matrix; the boundary cells and the internal cells configurable for any of a plurality of modes including a triangularization mode, a back-substitution mode, and a multiplication mode; the boundary cells having first multipliers; the internal cells having second multipliers; and the first multipliers and the second multipliers for multiplication of a first matrix and a second matrix responsive to the multiplication mode being invoked.