1. A processor for performing a QR decomposition (QRD) according to a modified Gram-Schmidt (MGS) QRD in a single field programmable gate array (FPGA) comprising: a converter configured to convert a complex fixed point input to a complex floating point input; a dual port memory coupled to said converter and configured to hold complex entries of an input matrix, the input matrix having a pre-determined size; a normalizer programmable logic module (PLM) configured to compute a normalization of an input matrix column vector; a second PLM configured to perform a complex multiplication operation on two input matrix columns to compute an element of an output matrix R and to further compute an intermediate column of an output matrix Q; a scheduler coupled to said normalizer PLM and said second PLM and configured to divert control of the QRD processing to one of the normalizer PLM and the second PLM; a top level state machine in communication with said scheduler and configured to monitor processing in the normalizer PLM and the second PLM and communicate completion of a given operation to the scheduler; a complex divider coupled to said memory and said normalizer PLM and configured to receive the computed normalization of the input matrix column vector and the intermediate column of the output matrix Q and compute a final column for output matrix Q; a multiplexer coupled to said complex divider and to said normalizer PLM and configured to output a computed complex value as an element of one of output matrix Q and output matrix R.