1. A carry look-ahead circuit that generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits, the carry look-ahead circuit comprising: a first circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and a second 2-input circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output, and wherein the second 2-input circuit is a 2-input NAND gate, and a number of gate stages of a combination of the first circuit and the 2-input NAND gate is 4 when the first operand and the second operand respectively have 4 bits.