1. A processor comprising: an execution core configured to execute a vector instruction comprising: a first vector predicate operand that specifies active elements of a result vector of the vector instruction; a second vector predicate operand that represents true/false results of a conditional expression; and a source operand that specifies which combinations of true/false results in the second vector predicate are indicative of dependencies in one or more vector operations, wherein the execution core is configured to generate the result vector identifying which active vector elements are dependent on which other active vector elements in response to the true/false results and the source operand, wherein dependencies are detected only between active vector elements.