1. An integrated circuit comprising: at least two cascade-connected multiplexers (Mux 1, Mux 2, Mux 4 ) each having: a plurality of data inputs (ar, arq; a 0, a 0 q; a 1,a 1 q); a data output (z, zq), wherein each data input and each data output has two terminals for the application of a dual-rail signal; and a control input (sr, s 0, s 1 ), wherein a signal (shj<2:0>, j&equals;1, 2, 4) present at the control input defines which of the data inputs is connected to the data output; and at least one precharge unit (VE), which is driven with a precharge unit control signal (PrShQ), is connected to the data output or at least one of the data inputs of one of the multiplexers (Mux 1, Mux 2, Mux 4 ) to thereby bring the data outputs (z, zq) and/or data inputs (a 0, a 0 q) of the multiplexers (Mux 1, Mux 2, Mux 4 ) into a precharge state before execution of a computation operation, wherein the data output (z, zq) of a multiplexer of the at least two cascade-connected multiplexers is connected to one of the data inputs (a 0, a 0 q) of the multiplexer connected downstream, as a result of which a data path leading through the cascade is formed.