1. A read activity detector circuit for use in a random access memory array, the circuit comprising: a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals each having a frequency that is substantially the same as a frequency of a core reference clock and having different phases relative to one another, each of the synchronizer circuits, in response to a first control signal presented thereto, generating an output signal having one of a rising edge and a falling edge which is substantially aligned to one of a rising edge and a falling edge of the reference clock signal corresponding thereto; and a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array.