1. In a pipelined digital processor employing macro-instructions utilizing interpretation by micro-instructions, each of said macro-instructions being identifiable by an assoicated address and each of said micro-instructions being identifiable by an associated addresss, a lookahead fetch system for transmitting predicted brach addresses to a prefetch section prior to decoding of respective brach instructions, comprising: branch cache means coupled to said prefetch section, said branch cache means receiving prefetch information from said prefetch section, and said branch cache means transmitting to said prefetch section predicted branch address information, said branch cache means including a plurality of indexed memory loations for storing an indexed table of branch target addresses, each of said branch target addresses corresponding to an addresss of a previously fetched instruction that resulted from a succeeding execution of said instruction, hashing means for simultaniously receiving and combining a predetermined number of bits representative of the address of a macro-instruction being fetched with a predetermined number of bits representative of the address of a micro-instruction invoked by said macro-instruction, and index means, in communication with said hashing means and said branch cache means, for applying an address, generated by combinations of bits produced by said hashing means, to said branch cache means, to read out a branch target address; whereby a branch target address that is predictive of a branch of a micro-instruction interpreting a macro-instruction is read out of the branch cache means.