1. A circuit for converting a single-ended input signal to a differential output signal, comprising: a voltage supply; a reference potential; a first stage, having an input INP and a bias input IBIAS, first and second output nodes N 1 and N 2, said first stage providing a differential output signal at said nodes N 1 and N 2, said first stage having a first and a second MOS transistor of a first conductivity-type forming a differential amplifier, the gate of said first MOS transistor connected to said input INP via capacitive means C I, and where a capacitive means C D connected across said gate and a source of said first MOS transistor compensates for a parasitic drain to reference potential capacitance C B of a tail current source; and a second stage connected to said nodes N 1 and N 2, said second stage having a third and a fourth MOS transistor of said first conductivity-type forming a differential amplifier, said second stage having outputs OUTA and OUTB, said outputs OUTA and OUTB providing fully differential, wide-band signals ranging in frequency from 100 kHz to 1 GHz (1 GHz&equals;109 Hertz), with a magnitude and phase error at said frequency of 1 GHz, when referenced to a signal at said input INP, of no more than 0.015 dB (10 dB&equals;1 Bell) and 0.15 degrees, respectively.