1. In a data processing system for processing data in accordance with read and write operations, comprising: a processing unit for processing input data after said read operation in accordance with a plurality of instructions provided thereto and producing output data for said write operation: instruction means for supplying said plurality of instructions successively to said processing unit; instruction counter means driven by a clock pulse signal for providing instruction addressing information to said instruction means, said instruction means successively producing said plurality of instructions in accordance with said instruction addressing information, said instruction addressing information comprising upper and lower bits; and a data memory unit having addressable storage areas for providing said input data to be processed in accordance with data addressing information, and for receiving said output data produced by said processing unit, said data addressing information comprising upper bits and lower bits; said data processing system being characterized in that said input data is transmitted serially bit by bit from said data memory unit to said processing unit during the read operation, and said output data is transmitted serially bit by bit from said processing unit to said data memory unit during the write operation; the improvement wherein said instruction counter means comprises an upper bits region for holding said upper bits of said instruction addressing information, and a lower bits region for holding said lower bits of both said instruction addressing information and said data addressing information; said instruction counter means including means for synchronously providing the contents of said lower bits region of said instruction counter means in synchronization both to said instruction means as said lower bits of said instruction addressing information and to said data memory unit as said lower bits of said data addressing information, whereby said lower bits of said instruction addressing information and said data addressing information, respectively, are provided by a common source; said instruction counter means also including first means for providing the contents of said upper bits region of said instruction counter means to said instruction means as said upper bits of said instruction addressing information; said system further comprising generating means for continuously generating random bits partially defining successive addressable storage areas in said data memory unit to be addressed, and second means connected to said generating means for providing said random bits to said data memory unit as said upper bits of said data addressing information, whereby said processing unit is instruction-addressed and said data memory unit is data-addressed in synchronization, one with the other, with resultant improved efficiency.