1. An integrated circuit comprising: a plurality of computational elements, a first computational element of the plurality of computational elements having a first fixed architecture and a second computational element of the plurality of computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture; a plurality of switching elements coupled to the plurality of computational elements, the plurality of switching elements capable of configuring the plurality of computational elements for performance of a first function of a plurality of functions in response to first configuration information, and the plurality of switching elements further capable of reconfiguring the plurality of computational elements for performance of a second function of the plurality of functions in response to second configuration information, the first function being different than the second function.