1. A node comprising: a plurality of processor cores, each processor core configured to have a plurality of threads active and each processor core including at least one first level cache; coherency control circuitry coupled to the plurality of processor cores and configured to manage intranode coherency among the plurality of processor cores; and at least one coherence unit coupled to the coherency control circuitry and configured to couple to an external interface of the node, the coherence unit configured to transmit and receive coherence messages on the external interface to maintain coherency with at least one other node having one or more processor cores and a coherence unit.