1. A processor, comprising: a fetch circuit to fetch a single instruction multiple data (SIMD) instruction comprising an opcode, first source, second source, and destination operands to specify first source, second source, and destination vectors, respectively, and a mask operand including a plurality of bits each indicating whether a corresponding data element is to be operated on; an inactive element detection circuit to analyze the mask operand during each of a fetch stage, a decode stage, an allocate stage, a rename stage, and a schedule stage of a pipeline, and to generate and store an inactive element indicator for each inactive element; a zero element prediction circuit to analyze the opcode and the first and second specified sources during the schedule stage to generate and store a zero element indicator for each destination element predicted to be zero; a plurality of processing elements, including an arithmetic logic unit (ALU), a register file, a data bus dispatch path, and a write-back path in a retirement unit, to process a plurality of data elements of the SIMD instruction in a vector manner; and a power management unit, including clock gating logic to reduce a clock frequency of a clock signal to processing elements identified by one or both of the stored zero element indicator and the stored inactive element indicator.