1. A method of fabricating an integrated circuit, the method comprising: forming a first gate electrode having a first bottom electrode surface proximate to a first gate dielectric disposed over a first semiconductor channel region and having a first top electrode surface at a first height from the first bottom gate electrode surface; forming a second gate electrode having a second bottom electrode surface proximate to a second gate dielectric disposed over a second semiconductor channel region and having a second top electrode surface at a second height from the second bottom electrode surface; and recessing at least a portion of a first top electrode surface below at least a portion of the second top electrode surface.