1. A processor, comprising: execution units; a register file with multiple register segments to store results for subsequent processing by the execution units, wherein the register file is configurable for different execution modes, including: the multiple register segments forming a single register file where each register segment stores the sources and results of a Multiple Instructions Multiple Data (MIMD) super instruction issuing simultaneous instructions where each individual instruction is a scalar or Single Instruction Multiple Data (SIMD); the multiple register segments forming individual independent register files with individual register state to support simultaneous processing of separate threads, wherein each instruction is associated with a separate thread and a separate register file segment; and the multiple register segments forming a single thread register file, wherein register segments are duplicated in multiple segments of the register file to store the results of simultaneously executed non-dependent instructions that are dynamically issued from a single thread instruction sequence.