1. A system comprising: a plurality of block-based processor cores, wherein each respective one of the cores is capable of executing one or more instruction blocks of a program; and an instruction block scheduler configured to: identify a given instruction block that is resident on a first processor core of the processor cores and is to be executed again; and adjust a mapping of in-flight instruction blocks to multiple processor cores of the plurality of the processor cores so that the given instruction block is re-executed on the first processor core without re-fetching the given instruction block.