1. In data processing apparatus employing a processor which is to be controlled by a program comprising sequential instructions each of which is selected from a first instruction set which differs from a native instruction set of said processor, a substantial number of which instructions comprise an operation code selected from a set of n such codes and an operand addressor sufficient to directly obtain an operand, the operand addressor being selected from a set of m such operand addressors, the improvement comprising: a store having approximately n times m locations with each location addressed by a consistent combination of an operation code and an operand addressor sufficient to directly obtain the operand, each location holding a series of instructions selected from a second instruction set different from the first instruction set, said second instruction set being the processor's native instruction set, and said series-performing the same function as an instruction corresponding to said operation code and operand addressor used to address the location without requiring additional indirection to obtain the operand; and control means for addressing said store, in response to each of the sequential program instructions, and for providing to said processor from said store, said series of instructions at the addressed location in the store and further for directly obtaining and providing to said processor each said operand without performing indirect addressing to obtain each said operand.