1. A three dimensional multilayer circuit ( 400 ) comprising: a via array ( 325 , 330 ) comprising a set of first vias ( 325 ) and a set of second vias ( 330 ); an area distributed CMOS layer ( 310 ) configured to selectively address the set of first vias ( 325 ) and the set of second vias ( 330 ); at least two crossbar arrays ( 305 , 420 ) configured to overlie the area distributed CMOS layer ( 310 ), each of the at least two crossbar arrays ( 305 , 420 ) comprising a plurality of intersecting crossbar segments ( 320 , 322 ); and programmable crosspoint devices ( 315 ) configured to be interposed between the intersecting crossbar segments ( 320 , 322 ), the via array being connected to the crossbar segments such that each of the programmable crosspoint devices ( 315 ) can be uniquely accessed using a first via ( 325 ) and a second via ( 330 ).