1. A combinatorial logic unit comprising: a cascaded multiplexer architecture having a plurality of multiplexer planes, each of said multiplexer planes including at least one multiplexer having inputs, at least one control input connected to at least one input node and at least one output; at least one multiplexer in a first of said multiplexer planes having said inputs connected to input nodes; inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane connected to said outputs of said at least one multiplexer in preceding multiplexer planes in said cascaded multiplexer architecture; at least one multiplexer in a last of said multiplexer planes having said at least one output connected to an output conductor; and at least one inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user-programmable interconnect elements.