1. A three dimensional multilayer circuit comprising: a via array comprising a set of first vias and a set of second vias; an area distributed CMOS layer configured to selectively address the set of first vias and the set of second vias; at least two crossbar arrays configured to overlie the area distributed CMOS layer, each of the at least two crossbar arrays comprising a plurality of intersecting crossbar segments; and programmable crosspoint devices configured to be interposed between the intersecting crossbar segments, the via array being connected to the crossbar segments such that each of the programmable crosspoint devices can be uniquely accessed using a first via and a second via.