1. An apparatus comprising: a memory device located within a secure boundary and configured to store one or more secret data objects; a processor located within the secure boundary and configured to execute security firmware and perform a set of operations limited to a plurality of secure operations for manipulating the one or more secret data objects; a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the plurality of secure operations; and one or more security assist hardware circuits configured to perform discrete operations using the one or more secret data objects, wherein each of the plurality of secure hardware registers corresponds to a different security assist hardware circuit, the discrete operations comprising at least one of data encryption, data decryption, signature calculation and checking, and random number generation.