1. A computer system having an interrupt handling apparatus, the computer system comprising: one or more processors; one or more hardware devices that are capable of interrupting the one or more processors using an interrupt signal; an interrupt controller that is capable of handling the interrupts from the one or more hardware devices and capable of independently generating a low priority interrupt signal and a high priority interrupt signal for each processor; the interrupt controller further comprising an enable device that is capable of enabling the interrupt signal independently for each processor and a priority device that is capable of assigning a priority to each interrupt signal destined for any processor wherein a particular interrupt signal is capable of being routed to either processor and is capable of being assigned a low priority or a high priority.