1. An apparatus, comprising: a processor coupleable to a shared memory that is shared by one or more other processors, wherein the processor is configured to execute a section of code that includes a plurality of memory access operations to the shared memory as an atomic transaction relative to the one or more other processors; wherein the processor is configured to determine whether the plurality of memory access operations includes at least one of a set of disallowed instructions, wherein the set of disallowed instructions includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment; and wherein the processor is configured to abort the transaction in response to one of the plurality of memory access operations including at least one of the set of disallowed instructions.