1. A vision processor, comprising: an image memory having two read ports and a write port; a block prediction error memory having two read ports and a write port; a discrete cosine transform ("DCT") memory configurable as a two read, two write port memory and as a four read, four write port memory; a shifter having an input coupled to a read port of said search memory, and an output; a shifter/transposer having an input selectively coupled to one of the other read port of said search memory and to two read ports of said DCT memory configured as a two read, two write port memory; an arithmetic logic unit having: a first input selectively coupled to one of the two read ports of said frame memory, to the output of said shifter, and to two read ports of said DCT memory configured as a four read, four write port memory, and a second input selectively coupled to one of the outputs of said shifter and said shifter/transposer, to the output of said shifter/transposer, and to the other two read ports of said DCT memory configured as a four read, four write port memory; and an output selectively configurable as an average of operandi and a difference of operandi coupled to the write ports of said image memory and block/prediction error memory; an output configured as an absolute difference of operandi; and an output configured as a sum of operandi and a difference of operandi coupled to the write ports of said DCT memory; a tree adder having an input coupled to the absolute difference output of said arithmetic logic unit; and a multiplier-accumulator having an input coupled to the four read ports of said DCT memory configured as a four read, four write port memory.