1. An instruction accelerator comprising: a processor for receiving a stream of instructions and a corresponding stream of instruction identifier values each of which uniquely identifies a corresponding instruction in the stream of instructions, wherein the instructions comprise a first non-quick instruction which has a first associated data set which must be accessed prior to executing the first non-quick instruction; and a memory coupled to the processor, the memory being adapted to: store one or more instruction identifier values, including a first instruction identifier value which identifies the first non-quick instruction; store one or more data sets, including the first associated data set; receive the stream of instruction identifier values; and compare a current instruction identifier value in the stream of instruction identifier values with the one or more instruction identifier values stored in the memory; wherein a data set is accessed from the memory when the current instruction identifier value in the stream of instruction identifier values matches an instruction identifier value stored in the memory, and wherein the data set remains in the memory for use by a subsequent non-quick instruction.