1. A co-processor for complex arithmetic processing, comprising: a complex arithmetic circuit that executes a complex arithmetic operation for complex data in accordance with an instruction from a primary processor, the complex arithmetic operation being required for radio communication; and a memory controller that operates in parallel with the complex arithmetic circuit, and accesses a memory, wherein the memory controller includes: a first address generator circuit that autonomously generates a write address to the memory; a second address generator circuit that autonomously generates read addresses from the memory; a first FIFO (First-In First-Out) that temporarily stores the arithmetic result data, and that outputs the arithmetic result data to the memory in synchronization with the write address; a second FIFO that temporarily stores complex data series input from the memory in synchronization with the read addresses, and that sequentially outputs the complex data series to the complex arithmetic circuit; and a preprocessing circuit that is provided between the memory and the second FIFO, and that normalizes, by using the normalization coefficient, the arithmetic result data input as second complex data series from the memory.