1. An apparatus for implementing random content of program loops in random test generation for processor verification comprising: a processor, a constrained random test generator tangibly embodied in a non-transitory machine readable medium used in the processor verification; said processor using said constrained random test generator for generating random instructions in a program loop comprising: a converged branch instruction stream being used by said constrained random test generator for converging all random conditional branches to a main program loop; a built in exception handling mechanism being provided in said constrained random test generator for enabling program interrupts to converge to the main program loop; mandatory read only registers being applied to said constrained random test generator for allowing register based storage addresses to maintain a value; global class restriction mechanism being applied to the test generator for avoiding inherently problematic operations for the program loops; and machine state detection and restoration mechanisms being provided in said constrained random test generator to preserve storage addressability.