1. A reduction circuit for sparse matrix-vector multiplication (SpMV) processing, comprising: an input configured to receive an incoming value of an accumulation set of a sparse matrix, the incoming value having an associated accumulation set id; an adder configured to sum input values provided to the adder and provide the summed value to an adder output; at least one buffer in operable communication with the input and the adder output, the at least one buffer configured to provide a buffered value to the adder; a plurality of data paths arranged to selectively deliver one or more of the incoming value, the buffered value, and the summed value to the adder and to the at least one buffer; and a controller configured to control delivery of the incoming value, the buffered value, and the summed value to the adder or to the at least one buffer based on an accumulation set id associated with one or more of the incoming value, the buffered value and the summed value.