1. An apparatus comprising: an address translation cache that includes a plurality of entries that each includes at least one translation mode bit that indicates an address translation mode for the corresponding entry in the address translation cache; and at least one processor coupled to the address translation cache, the at least one processor executing at least one instruction that selectively invalidates at least one entry in the address translation cache according to the at least one translation mode bit in the plurality of entries without invalidating all of the plurality of entries in the address translation cache.