1. A processor core, comprising: a plurality of dispatch queues for receiving instructions of a corresponding plurality of instruction streams; a plurality of parallel instruction execution slices for executing the plurality of instruction streams in parallel; and a dispatch routing network for routing the output of the dispatch queues to the instruction execution slices such that the routing network dynamically varies the relationship between the dispatch queues and the plurality of parallel instruction slices according to execution requirements for the plurality of instruction streams and resource availability in the plurality of parallel execution slices.