1. A supervisor addressability control system for controlling the quantity of limited addressability available to a supervisor and to a user in a main memory, comprising a status register having a first bit position providing a supervisor state signal for indicating whether the system is in supervisor state or not, and a second bit position providing an alternate protect mode (APM) signal indicating whether the system is in the alternate protect mode or not, a user address key register (UKR) for containing an address key that makes available to a processor a user's addressability in the main memory which may contain the user's programs and data, supervisor/user addressability switching AND gate means having inputs receiving the supervisor state signal, the APM signal, and an instruction fetch signal provided by the processor, an output of the switching AND gate means being enabled when the APM mode, supervisor state, and instruction fetch input signals all exist simultaneously, the output being disabled when any input signal is not activated, key-providing AND gate means having one input connected to the output of the UKR, and another input connected to an inverted output of the switching AND gate means, whereby the output state of the key-providing AND gate means provides the supervisor address key while the switching AND gate means is disabled so that an instruction must be fetched within the supervisor addressability, and provides the user address key while the switching AND gate means is enabled which occurs while the supervisor is not fetching an instruction so that an executing supervisor instruction can access operand(s) within the user addressability.