1. A method of forming a semiconductor device having a memory device, comprising: providing a semiconductor substrate having a surface region; forming a first dielectric layer overlying the surface region of the semiconductor substrate; forming a first via within the first dielectric layer material; depositing a liner material within the first via; depositing a metal-containing material over and in contact with the liner material and filling the first via; planarizing the liner material and the metal-containing material within the first via along with the first dielectric layer surface, exposing a top surface of the metal-containing material within the first via; depositing a contact material overlying the metal-containing material within the first via; depositing an undoped resistive switching silicon material overlying and touching the contact material; depositing a metal-containing material overlying and touching the undoped resistive switching silicon material; depositing a top barrier material overlying and touching the conductive metal-containing material; performing a patterning and etching process to form a plurality of pillar structures from at least the contact material, the undoped resistive switching silicon material, the metal-containing material, and the top barrier material; depositing a second dielectric material overlying at least the plurality of pillar structures, the second dielectric material having a non-planer surface region; planarizing the second dielectric material, exposing surface regions of the plurality of pillar structures, the surface regions of the plurality of pillar structures including surface regions of the top barrier material; and forming a top wiring structure overlying at least the surface regions of the plurality of pillar structures, wherein the forming the top wiring structure comprises: depositing a third dielectric material above the exposed surface regions of the plurality of pillar structures and a top surface of the second dielectric material; forming a second via within the third dielectric material; depositing the liner material within the second via; depositing the metal-containing material over the liner material and in contact with the liner material and filling the second via; planarizing the liner material and the metal-containing material within the second via along with the second dielectric layer surface, exposing a top surface of the metal-containing material within the second via.