1. A method of testing cache memory in a multiprocessor system, the method comprising: receiving a test mode initiation command from the multiprocessor system during a normal mode of operation of the multiprocessor system; terminating the normal mode of operation of the multiprocessor system and initiating a cache memory test of cache memory in response to the test mode initiation command; in response to initiating the cache memory test, suspending data transactions between a front side bus and the cache memory, and logically coupling a data cache exerciser to substantially the same components previously active during the normal mode of operation to perform the cache memory test; and returning to the normal mode of operation, logically decoupling the data cache exerciser, and returning to the data transactions between the front side bus and the cache memory upon completion of the cache memory test.