1. A context switching unit for switching a plurality of contexts, the context switching unit comprising: a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a register read port, a register write port, a context-switching read port, and a context-switching write port; a context cache used exclusively for saving and restoring contexts, the context cache comprising a read port and a write port, being connected directly to the register file and integrated in a central processing unit on a chip, the context cache being not connected to a memory through a bus, which connects the memory, an instruction cache and a data cache to each other, and being independent from a memory system including the memory, the instruction cache and the data cache, to realize context switching at a high processing speed without interference from the bus; a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit, wherein, in case of a context switch operation which executes both a save operation for saving a context from the register file to the context cache and a restore operation for restoring a context from the context cache to the register file in parallel at the same time, the thread control unit receives a context switch instruction for executing the context switch operation with the identifier of a new thread to be interchanged; the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and a save register identifier indicating a location where a current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier; the thread control unit sends the obtained address to the context cache and the register identifier to the register file; in parallel at the same time; the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port to the save bus for the save operation and holds the data of the context to be in parallel at the same time, sent from the read port of the context cache to the context-switching write port through the restore for the restore operation; the context cache, in accordance with the address given by the thread control unit, outputs the data of a context to be restored from the read port to the restore bus for the restore operation and holds the data of the context to be saved in parallel at the same time, sent from the context-switching read port of the register file to the write port via the save bus for the save operation; and whereby the context switching unit switches contexts the context switch operation which executes both the restore operation and the save operation in parallel at the same time.