1. A method for designing a circuit, wherein the circuit comprises a group of devices, comprising: initializing a set of design points, wherein a design point comprises a design of the circuit that meets a set of predefined design specifications; determining sizes for the group of devices using a size optimization iteration process; pausing the sizing optimization iteration process periodically for updating parasitic information of the circuit: selecting a subset of design points from the set of design points; generating a layout of the circuit using device sizes obtained from the set of design points; generating an extracted netlist using the layout, wherein the extracted netlist includes parasitic information of the circuit; simulating the circuit using the extracted netlist to verify the set of predefined design specifications are met.