1. A one-chip integrated circuit device comprising: a data processing unit for performing data processing in response to application program instructions applied thereto, said data processing unit comprising an instruction register and an instruction decoder coupled to said instruction register for decoding and instruction set therein, and generating an instruction-execution signal each time an instruction set in said instruction register has been executed; a first read only memory operatively coupled to said data processing unit for storing application program instructions and applying, when coupled to said data processing unit, the application programs to said data processing unit so that said data processing unit performs data processing according to the application program instructions; a second read only memory operatively coupled to said data processing unit for storing test programs adapted for testing functions of said data processing unit and said first and second read only memories, said second read only memory having an address space addressable in common with said first read only memory and applying, when coupled to said data processing unit, the test programs to said data processing unit so that said data processing unit performs the test programs, and the test programs including a first test program having a first instruction for setting test data to said data processing unit and a second instruction to couple said first read only memory to said data processing unit to process the test data according to the application program instructions stored in said first read only memory, and a second test program for deciding a result of the data processing on the test data performed by said data processing unit; an address register coupled to said first and second read only memories for addressing said first and second read only memories in common in accordance with address data set therein; a first selector coupled to said first and second read only memories for selectively coupling one of said first and second read only memories to said instruction register in said data processing unit; an increment circuit connected to receive the address data from said address register for incrementing the address data; a branch register connected to receive externally applied address data which specify a start address of part of the application program instructions to be executed by said data processing unit during a test mode; an interrupt table for storing a start address of the second teat program stored in said second read only memory; a second selector responsive to said data processing unit for selectively coupling one of said increment circuit, said branch register and said interrupt table to said address register; and test control means responsive to an externally applied test control signal and including a counter and a flip-flop, said counter being externally preset with the number of application program instructions to be executed by said data processing unit during the test mode and decremented by the instruction-execution complete signal to generate an output signal when all the application program instructions, the number of which has been preset in said counter, are executed, and said flip-flop being set by one of the test control signal and the output signal of said counter to cause said first selector to couple said second read only memory to said instruction register in said data processing unit to perform the first test program so that test data is set in said data processing unit, the start address and the number of the application program instructions are loaded in said branch register and said counter, respectively, and reset by an output of said instruction decoder when the second instruction is loaded in said instruction register at the end of the first test program to cause said first selector to couple said first read only memory to said instruction register so that the application program instructions are executed by said data processing unit from the start address set in said branch register; said second selector being controlled by said data processing unit to couple to said address register said increment circuit when the first test program is executed, said branch register when the second instruction is loaded in said instruction register, or said interrupt table when the execution of the application program instructions is completed so that said counter produces the output signal to initiate the execution of the second test program.