1. An electronic computing circuit processing two N-bit input operands of a bit length N and generating two M-bit output operands of a reduced bit length M, comprising: a) means for receiving said two N-bit operands as an input; b) means for adding the (N-M+1) most significant bits of said two N-bit operands in an auxiliary adder logic; and c) a decision logic processing the add result of said auxiliary adder logic for calculating at least the two most significant bits of reduced-bit-length output operands such that a predetermined post-processing can be correctly performed with said M-bit output operands.