1. A computer implemented method for performing selective branch prediction, the method comprising: fetching, by an instruction fetch unit of a processor, a stream of instructions from memory; decoding the stream of instructions by an instruction decode unit of the processor; issuing the stream of instructions by an issue unit of the processor; executing, by a plurality of execution units of the processor, the stream of instructions and a branch-prediction blocking instruction; turning on and off, by a branch prediction control circuit of the processor, a branch prediction function of a branch prediction unit of the processor based on a plurality of control signals provided from the plurality of execution units of the processor responsive to execution of the branch-prediction blocking instruction to block branch prediction operations of a predetermined number of branch instructions following the branch-prediction blocking instruction; preventing, by the branch prediction control circuit, the instruction fetch unit of the processor from accessing a branch target buffer of the branch prediction unit for the predetermined number of branch instructions following the branch-prediction blocking instruction, wherein the branch target buffer is configured to store a plurality of branch target addresses associated with predicted branches; and preventing, by the branch prediction control circuit, the execution units from providing branch information of the predetermined number of branch instructions to a branch history unit of the branch prediction unit responsive to execution of the predetermined number of branch instructions by the execution units, wherein the branch history unit is configured to store a plurality of patterns of taken and not-taken branch results for previously-resolved branch instructions, and the branch target buffer is separate from the branch history unit, and wherein the branch-prediction blocking instruction is generated and inserted into the stream of instructions by the branch prediction control circuit based on detecting a predetermined condition by the branch prediction unit.