1. A fused multiply-adder comprising: a Booth encoder for encoding a first operand; a fraction multiplier for multiplying said encoded first operand by a second operand to produce partial products, and for reducing said partial products to a set of sum and carry vectors, wherein one of said sum vectors includes a high sum vector and a low sum vector, and one of said carry vectors includes a high carry vector and a low carry vector; a carry corrector for generating a set of carry correction factors to correct an artifact carry bit when said first operand is less than a full-precision of said fused multiply-adder, wherein said carry correction factors are determined by S M OR C M , wherein said S M is a boundary bit position located between said high sum vector and said low sum vector, said C M is a boundary bit position located between said high carry vector and said low carry vector; and an adder circuit for operating on said sum and carry vectors, said set of carry correction factors and a third operand to produce a final result.