1. A memory array, comprising: a plurality of memory cells, each memory cell receiving a bit line, a first word line, and a second word line, each memory cell including: a cell selection circuit operably coupled to the first word line and the bit line to select the memory cell in response to activation of at lease one of the bit line and the first word line; and a two-terminal switching device comprising first and second conductive terminals in electrical communication with a nanotube article, the first terminal operably coupled to the cell selection circuit and the second terminal operably coupled to the second word line; a memory operation circuit operably coupled to the bit line, the first word line, and the second word line of each cell, said operation circuit capable of selecting the cell by activating at least one of the bit line and the first word line and applying a first electrical stimulus to at least one of the bit line, first word line, and second word line to change the resistance of the nanotube article between the first and second terminals to a relatively high resistance, said operation circuit capable of selecting the cell by activating at least one of the bit line and the first word line applying a second electrical stimulus to at least one of the bit line, first word line, and second word line to change the resistance of the nanotube article between the first and second terminals to a relatively low resistance, wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell.