1. An advanced processor, comprising: a packet distribution engine (PDE) configured to receive a plurality of packets from a networking input and to distribute the plurality of packets to a packet processing system having a plurality of processor cores; a packet ordering mechanism configured to receive processed packets from the packet processing system and to provide the processed packets to a networking output; and a fast messaging network (FMN) coupled to the PDE, said FMN also coupled to at least two of the processor cores and configured to link said at least two of the processor cores together such that at least one processor core can send data to another processor core without going through memory.