1. A processor executing a very long instruction word containing a plurality of instructions, comprising an address supply unit configured, when the processor fetches concurrently the very long instruction words of up to M instruction streams, from N instruction caches including a plurality of memory banks to store the very long instruction words of the M instruction streams, to: set instruction priority order for each of the instruction streams; designate a memory bank to be used by each of the instruction streams from the memory banks based on bank number information, which indicates a number of memory banks each instruction stream uses, and an instruction address of each of the instruction streams; determine a memory bank to be used in descending priority order based on the instruction stream priority order when a plurality of instruction streams are to use a same memory bank; and supply an instruction address of a corresponding instruction stream to the determined memory bank, the very long instruction words of the M instruction streams being allocated to different memory banks of the plurality of memory banks, respectively, the instruction stream priority order being set to a fixed value for each of the instruction streams, and the fixed value being set and changed based on one of an external instruction stream priority order control signal, a changing instruction for instruction priority order, and a instruction stream priority changing flag, which is included in a very long instruction word fetched in a previous cycle as a partial field thereof.