1. A flash memory device comprising: (a) a storage area including: (i) a main memory portion; and (ii) a cache memory portion, where said cache memory portion is operative to store at least one bit per cell less than said main memory portion; and (b) a controller operative to transfer data between said cache memory portion and said main memory portion and, in response to a status command received from a host, to send said host an indication of an amount of said data that is stored in said cache memory portion.