1. A computer implemented method for implementing full-chip optimization across boundaries of a block with reduced physical design data, comprising: using at least one processor that is programmed for performing executing one or more threads of execution to perform a process, the process comprising: identifying an original set of design data of an electronic design that comprises a plurality of blocks; performing full-chip optimization or closure using reduced physical design data; and merging a change made during the full-chip optimization or closure back to the original set of design data.