1. An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region of the substrate defined therebetween; an electrically conductive floating gate disposed over and insulated from at least a portion of the channel region, wherein the floating gate includes a horizontally oriented edge extending from a lateral side of the floating gate; and an electrically conductive control gate having at least a portion thereof disposed laterally adjacent to and insulated from the horizontally oriented edge.