1. In a data processing computer, a sequential parity error correcting circuit comprising: a memory device for storing data and associated parity information; a temporary memory operatively coupled to the memory device for temporarily storing data and its associated parity information retrieved from the memory device; a processing device, operatively coupled to the temporary memory, for processing the data temporarily stored in the temporary memory and providing the result at a data output terminal; a parity checker, operatively coupled to the temporary memory in parallel with the processing device, for testing the stored data with its associated parity information, and generating a signal indicating the status of the test; a parity generator, operatively coupled to the parity checker, for generating correct parity for the stored data and providing the result at a parity output terminal; a multiplexer having a first multiplexer input terminal coupled to the memory device, a second multiplexer input terminal coupled to the processing device data output terminal and the parity output terminal, and a select terminal; a control circuit, operatively coupled to the parity checker and responsive to the status test signal; the control circuit operating in response to a failed parity indication to pause data paths coupled to the processing device data output terminal, to cause the processing device to pass the stored data directly to its data output terminal and to select the second multiplexer input terminal; and the control circuit operating in response to the absence of a failed parity indication to select the first multiplexer input terminal; such that in the event of a failed parity indication, the correct parity is substituted for the stored parity information and input along with the stored data to the temporary memory for subsequent input to the processing device.