1. A data processing apparatus comprising: a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices; a master device operable to initiate a transaction, the transaction specifying a transaction address; a cache interposed between the master device and the bus and operable to receive the transaction, the cache having a cache memory and a cache controller operable to control access to the cache memory, the cache controller comprising caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address; control storage operable to identify a trace address range specifying a trace region; and trace logic operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range; the caching logic being operable to store the trace data at a location in the cache memory chosen dependent on the trace address.