1. A memory system comprising: a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and one or more transmission buffers, wherein M is an integer equal to or more than 2; a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices; and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full, wherein when the input of the program data is ended or the M-bit buffers of the selected memory device are full, the controller controls the selected memory device to perform the secondary preparation operation of the program preparation operation, and then one-shot programs data stored in the M-bit multi-buffers of the selected memory device to first M-bit MLCs of the selected memory device through transmission buffers of the selected memory device, wherein the necessary preparation operation of the program preparation operation comprises a data sorting operation of sorting the data stored in the M-bit multi-buffers of the selected memory device, and the secondary preparation operation of the program preparation operation comprises a data checking operation of checking data which are sorted and stored in the M-bit multi-buffers of the selected memory device through the data sorting operation, and an operation of generating a voltage which is used when data checked through the data checking operation are one-shot programmed to the first M-bit MLCs of the selected memory device, and wherein when a read operation is requested for the selected memory device before the input of the program data is ended or the M-bit multi-buffers of the first memory devices are full while the program data are programmed to the selected memory device, the controller outputs read data from second M-bit MLCs of the selected memory device through the transmission buffers of the selected memory device one bit by one bit, without using the M-bit multi-buffers of the selected memory device, the read data comprising data outputted from a memory block selected by a request of a host or valid data outputted from a victim block of the first or second memory devices during a garbage collection operation.