1. A reconfigurable interconnect network for coupling a plurality of processing elements to a plurality of memory elements, the reconfigurable interconnect network comprising: a switching element for providing a data path from any processing element to any memory element; a plurality of processor interface units, each processor interface unit coupled to one of the processing elements and to the switching element, for managing data flow to and from the processing element based on the performance of the processing element; a plurality of memory interface units, each memory interface unit coupled to one of the memory elements, for managing data flow to and from the memory element based on the physical configuration of the memory element; and a plurality of application control units, each application control unit coupled to one of the memory interface units and to the switching element, for managing the flow of data to and from the memory interface unit based on an application for which the memory element is storing data.