1. An integrated circuit comprising: one or more logic blocks generating one or more system operation signals at one or more system operation clock rates; and a service processor unit to perform test and debug operations of said logic blocks of said integrated circuit, further comprising: a control unit; a buffer memory; an analysis engine; a scan control unit, a test bus interface; and a built-in self test (BIST) engine; wherein, in a first mode of operation, said service processor unit performs capture and analysis of system operation signals during normal system operation through said test bus interface.