1. A processing system for performing a cryptographic operation comprising a byte substitution operation, the processing system comprising: a memory device; a cryptographic accelerator module operatively coupled to the memory device, the cryptographic accelerator module to implement the byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, wherein the first mapped affine transformation is represented by a first mapped affine transformation matrix produced by multiplying a first mapping matrix and a first transformation matrix, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.