1. A processor comprising: an execution unit having a data path including a plurality of lanes, each of the lanes to execute an operation on at least one channel of a plurality of channels of a single instruction multiple data (SIMD) instruction responsive to the SIMD instruction, the execution unit to perform the SIMD instruction in a number of execution cycles; and a decode logic including a compaction logic to reduce the number of execution cycles based at least in part on an execution mask associated with the SIMD instruction.