1. A method of code execution in a system having first and second processors, comprising: said first processor encountering a first exception; said first processor jumping to execute a first exception handler code at a first predetermined address; said first processor executing said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said first processor to read a value at a first data structure; said first processor jumping to execute a second exception handler code at a second address as a function of the value read from said first data structure; and said first processor executing said second exception handler code to handle said first exception.