1. A method for optimizing design of a microelectronic circuit using a plurality of processors, the design having a plurality of timing paths, a subset of the timing paths being characterized as critical paths, each of the timing paths having an endpoint, the method comprising the steps of: constructing a list of the critical paths; constructing a set of endpoints of said critical paths; partitioning said set of endpoints in accordance with predetermined rules regarding timing independence and geometric independence of the critical paths, thereby defining sub-sets of endpoints and paths associated therewith; and optimizing timing of the critical paths, wherein said optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets, and the microelectronic circuit includes a multiplicity of components, and said method is performed after placement of the components in the design.