1. An input/output (I/O) system for a massively parallel, single instruction, multiple data (SIMD) computer providing bi-directional, two-dimensional data transfer between a host computer and said SIMD computer, wherein the data transfer is two-dimensional because data comprising N words each word up to n-bits in length is simultaneously transferred one N-bit plane at a time between the host computer I/O system and all SIMD memory devices of the SIMD computer, said SIMD computer comprising a parallel array processor comprising N a parallel linked processors, with each processor being coupled to an associated one of N SIMD memory devices, each of said N SIMD memory devices organized as D memory planes each comprising N bits, said input/output system comprising: (a) a temporary storage means coupled between said host computer and said N SIMD memory devices for the bi-directional, two-dimensional transfer of data between said host computer and said SIMD computer, wherein said temporary storage means includes N corner turning buffers, each one of said plurality of corner turning buffers being coupled with one of said N SIMD memory devices; (b) an input/output processing means, controlled by a system clock which generates clock cycles, for controlling the flow of data between said host computer and said N corner turning buffers, and for controlling the flow of data between said N corner turning buffers and said N SIMD memory devices, said input/output processing means distributing the N words of up to n-bits length each of data from the host computer to said N corner turning buffers and arranging said data therein as n memory planes each comprising N bits therein, each of said n memory planes corresponding to an associated one of said D memory planes of said SIMD memory, and further distributing said N words of up to n-bits length each to said corresponding SIMD memory devices of the SIMD computer one N-bit plane at a time in a single system clock cycle.