1. A network on chip (‘NOC’) comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers; a multiplicity of computer processors within the IP blocks, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification replacing bits in a cache index for a cache line of a memory page, the replaced bits added to a corresponding cache line tag to preserve the original address of the cache line.