1. A data processor comprising: an instruction decoding unit for decoding a first type and a second type of instruction; an instruction execution unit, coupled to said instruction decoding unit, for executing said first and second type of instructions decoded in said instruction decoding unit and for asserting an exception signal when an arithmetic operation exception occurs during processing of said second type of instruction, and wherein said first and said second types of instruction execute independently; a control unit, coupled to said instruction execution unit for accepting said exception and for activating an exception processing handler; a register, coupled to said instruction execution unit and to said control unit for selectively controlling the time when said control unit accepts said exception and wherein when the exception signal is asserted during execution of said second type of instruction in said instruction execution unit, said control unit writes a new set of control data to said register, accepts an exception related to said second type of instruction, and activates the exception processing handler; and wherein said first type of instruction is an interger operation instruction and said second type of instruction is a floating-point operation instruction; and wherein each of said first and second types of instructions are executed by said instruction execution unit regardless of the status of the control data in said register.