1. A digital processing circuit comprising in combination: (a) a first local processor connected to a first address bus and a first data bus; (b) a second local processor connected to an input/output bus; (c) a second data bus and a second address bus; (d) a shared resource connected to a shared resource address bus and a shared resource data bus; (e) first transceiver means for selectively coupling the first data bus to the shared resource data bus and first address buffer means for selectively coupling the shared resource address bus to the first address bus; (f) second transceiver means for selectively coupling the shared resource data bus to the second data bus and second address buffer means for selectively coupling the shared resource address bus to the second address bus; (g) third transceiver means for selectively coupling the shared resource data bus to the input/output bus and third address buffer means for selectively coupling the shared resource address bus to the input/output bus; (h) means for arbitrating between a first bus request signal produced by the local processor and a second bus request signal produced by the input/output controller for generating a first bus grant signal or a second bus grant signal; (i) means responsive to the first bus grant signal for enabling the first address buffer means and the first transceiver means to effectuate accessing of the shared resource by the local processor; (j) means responsive to the second bus grant signal for enabling the third address buffer means and the third transceiver means to effectuate accessing of the shared resource by the input/output controller; (k) a system bus and buffer means for coupling the system bus to the second address bus and the second data bus; (l) a system processor coupled to the system bus and having higher priority than either the local processor or the input/output controller; (m) means responsive to an access request by the system processor for producing a third bus request signal for inserting a first preselected number of wait states into the local processor if the local processor is accessing the shared resource and for inserting a second preselected number of wait states into the input/output controller if the input/output controller is accessing the shared resource; (n) means for enabling the second address buffer to couple the second address bus to the shared resource address bus while the first preselected number of wait states are inserted and means for enabling the second transceiver means to couple the shared resource data bus to the second data bus while the first preselected number of wait states are inserted, and means for enabling the third address buffer to couple the input/output bus to the shared resource address bus while the second preselected number of wait states are inserted, and means for enabling the third transceiver means to couple the input/output bus to the shared resource data bus while the second preselected number of wait states are inserted, thereby effectuating top priority accessing of the shared resource by the system processor without any arbitration between the system processor and the local processor or the input/output controller.