1. A microprocessor arrangement comprising: an execution unit for controlling a program cycle and for processing arithmetic and logic operations; a working register which stores a result of an operation and which is coupled to a control element in the execution unit; a flag register which indicates information about the result of the operation using flag bits; and combinational logic elements which are connected to the working register, wherein the combinational logic elements are controlled such that the state of the flag bits in the flag register is updated after the executed operation only if execution of one of subsequent operations within the program cycle requires a status of the flag bits.