1. A digital system comprising: at least a first processor; and a memory cache connected to the first processor, the memory cache operable to respond to transfer requests from the first processor; wherein the memory cache comprises: a data array arranged as a plurality of lines each having one or more segments; a plurality of indicating bits, wherein each of the segments has a corresponding indicating bit within the plurality of indicating bits, each indicating bit operable to indicate the corresponding segment is in a first state; and block circuitry connected to the plurality of indicating bits, the block circuitry operable to operate on a selected range of lines according to the associated indicating bits in response to a directive from the first processor.