1. A processor comprising: a vector register comprising a first plurality of data fields to store values of vector elements; a decode stage to decode a first instruction specifying: a destination operand, a size of the vector elements, a portion of the first plurality of data fields, and a source operand; and an execution unit, responsive to the decoded first instruction, to: read values from data fields of the size of vector elements in the source operand; compare the values read from the data fields of the source operand for equality with each other; and responsive to a detection of an inequality of one or more data fields of the source operand, signaling said detection of the inequality.