1. A cache memory apparatus for use with a microprocessor that processes a plurality of instructions having associated data, said apparatus comprising: cache memory means for providing high speed memory cache operations with said microprocessor; miss indicating means for generating a miss indication associated with each instruction of said plurality of instructions having an associated data address which is not accessible by said cache memory means, said each instruction called a cache miss instruction; and selecting means for temporarily blocking said microprocessor from processing a first instruction type of said plurality of instructions that follows said miss indication from said miss indicating means, said selecting means also for allowing processing of a second instruction type of said plurality of instructions that follows said miss indication from said miss indicating means, said selecting means communicatively coupled to said miss indicating means.