1. A method to generate clock constraints for a design flow of a semiconductor product, the method comprising the steps of: (a) inputting resource definitions of a semiconductor platform having least one clocking function; (b) inputting design requirements of at least one desired clocking function to be implemented on the semiconductor product; and (c) determining if the design requirements are consistent with and physically realizable from the resource definitions; (d) if the design requirements are consistent with and physically realizable from the resource definitions, creating a set of clocking constraints; and (e) automatically generating correct and minimal clock constraints for the semiconductor product.