1. A semiconductor memory device comprising a plurality of memory cell arrays, each of which includes a memory cell group and a sense amplifier circuit, the device comprising: selecting means for concurrently selecting two or more memory cell arrays from among the plurality of memory cell arrays in response to a command, which is externally inputted, for selecting an automatic data refresh operation for the memory cell group; refreshing means for, in each of the selected two or more memory cell arrays, refreshing data in the memory cell group connected to word lines corresponding to address signals which are internally generated in an automatic manner; and switching means for, during the automatic data refresh operation, switching address signals for selecting word lines from address signals internally generated in an automatic manner to address signals externally inputted.