1. In a multi-processor system having multiple memory hierarchies each having an associated processor, a method for processing a load received by a first of the memory hierarchies, said method comprising: sending a direct intervention request containing the cache line address of the load to a second of the multiple memory hierarchies; and responsive to a cache miss within said first memory hierarchy and prior to issuing the load as a shared interconnect request, sending a push request to said second memory hierarchy to push the requested load data specified by the direct intervention request to said first memory hierarchy.