1. An information processor comprising: a plurality of first processing units; a direct memory access unit coupled to at least one first processing unit of the plurality of first processing units; and at least one first memory unit coupled to the direct memory access unit, the at least one first memory unit comprising: a second memory unit; a second processing unit adapted to process data stored in the second memory unit, wherein the second memory unit is adapted to be accessed by the at least one first processing unit of the plurality of first processing units through the direct memory access unit, and the second processing unit is separate from the plurality of first processing units and the direct memory access unit; and at least one register adapted to be accessed by the at least one first processing unit of the plurality of first processing units and the second processing unit, wherein the second processing unit is configured to receive operation instructions from the at least one register.