1. A computer-implemented method for creating a target hierarchical layout for an integrated circuit based on a source hierarchical layout, each hierarchical layout comprising a plurality of layers, cell instances and polygon, comprising: receiving by a computer-aided design (CAD) tool running on a computer scaling factors and bias values in X and Y directions for each layer in the source layout; creating by the CAD tool on the computer a source cell hierarchy tree based on the source hierarchical layout; based on the source cell hierarchy tree, creating by the CAD tool on the computer a target cell hierarchy tree by scaling each cell instance in the source hierarchical layout to provide a corresponding cell instance in the target cell hierarchy tree using the scaling factors in the X and Y dimensions; comparing positions of cell instances in the source cell hierarchy tree to positions of corresponding cell instances in the target cell hierarchy tree and modifying the target cell hierarchy tree to conform to the source cell hierarchy tree; and based on the target cell hierarchy tree, creating by the CAD tool on the computer the target hierarchical layout by applying the bias values on each layer of the target hierarchical layout.