1. A method of operating a processor, the method comprising: storing, by a memory array, a plurality of instruction threads; fetching, by a fetcher, a particular instruction thread from the memory array, the particular instruction thread including a particular branch instruction, the fetcher communicating with a thread priority controller; predicting, by a branch predictor, an outcome of the particular branch instruction of the particular instruction thread, thus providing a branch prediction; issuing, by an issue unit, the particular branch instruction of the particular instruction thread to a branch execution unit for execution; sending, by the issue unit, branch issue information to the thread priority controller; and changing, by the thread priority controller, a priority of the particular instruction thread in response to the branch issue information.