1. A processor comprising: a bit-shift circuit for inputting pieces of data held sequentially in a main register and an auxiliary register, shifting said piece of data bit after bit in accordance with a pointer and a bit count and outputting said shifted data by execution of an unpacking instruction specifying said bit count; a mask circuit for masking data output by said bit-shift circuit in accordance with said pointer and said bit count in the execution of said unpacking instruction; and a pointer-updating circuit for updating the value of said pointer by said bit count in the execution of said unpacking instruction.