1. A computer system for improving the tracking of a read sets and write sets associated with cache lines of a transaction in a pipelined processor, the computer system comprising: executing memory instructions, in a processor pipeline, having the read sets and write sets associated with the cache lines comprising: updating active read set and write set cache indicators associated with the memory operation of executing memory instructions; and updating read set and write set cache indicators associated with a recovery pool based on memory instructions being not-speculative, wherein the memory instruction is not-newer in program order than an un-resolved branch instruction; based on encountering a speculative branch instruction in the processor pipeline, copying a representation of the active read sets and write sets to the recovery pool; and based on completing the speculative branch instruction, updating the active read sets and write sets from the representations copied to the recovery pool associated with the branch instruction upon a detection of a misprediction.