1. An upconverting circuit comprising: a clock for defining a sequence of input polyphase cycles; a polyphase component generator that provides N p polyphase components at each input polyphase cycle, wherein N p >2; a memory that stores said polyphase components from at least one polyphase cycle prior to the current polyphase cycle; a plurality of filters, each filter processing a plurality of said polyphase components stored in said memory to generate a filtered polyphase component corresponding to that filter; and a multiplexer that outputs said filtered polyphase components in a predetermined order to generate a filtered output signal.