1. A circuit for converting the value of a digital word into a proportional time delay in response to a trigger signal, said circuit comprising, a digital-to-analog converter having a first current path and a second current path connected in parallel to a current output, means for drawing a DAC current from said current output, and means responsive to said digital word for changing the magnitude of a first current flowing through said first current path, means for generating a threshold voltage proportional to said first current, means responsive to said DAC current for generating a reference voltage, means responsive to said reference voltage for producing a proportional ramp current, and means responsive to said trigger signal for generating an increasing ramp voltage whose rate of increase is proportional to said ramp current, a differential comparator means responsive to said ramp voltage and said threshold voltage for generating an output representative of said time delay.