1. Data processing apparatus comprising: (i) a processor core operable to execute successive program instruction words of a predetermined plurality of instruction sets stored in a data memory; (ii) a program counter register for indicating an address of a next program instruction word in said data memory; (iii) logic operable to modify the contents of said program counter register in response to a current program instruction word; (iv) a processor core controller, responsive to one or more predetermined indicator bits of said program counter register, operable to control said processor core to execute program instruction words of a current instruction set selected from said predetermined plurality of instruction sets and specified by the state of said one or more indicator bits of said program counter register; and (v) a memory access controller operable to access program instruction words stored in said data memory, said access controller not being responsive to said one or more indicator bits of said program counter register.