1. A data processing system, comprising: a plurality of interrupt domains that each include at least one of a plurality of interconnected nodes, wherein each interrupt domain includes at least one processor capable of receiving external interrupts and at least one interrupt source capable of generating external interrupts, each of said plurality of interrupt domains having respective interrupt hardware that receives an external interrupt generated within that interrupt domain and first presents said external interrupt to a processor within that interrupt domain, wherein said processor to which said external interrupt is first presented invokes servicing of said external interrupt and a processor within a different interrupt domain services said external interrupt; wherein said interrupt hardware within each interrupt domain includes a globally-accessible memory mapped register utilized to communicate interrupts between interrupt domains, and wherein said interrupts include inter-processor interrupts.