1. An improved method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Device (PLD) comprising the steps of: selecting an unmapped or partially mapped LUT, identifying a group of circuit elements for mapping based on an available capacity of the selected LUT and a plurality of mapping constraints, mapping the group of circuit elements onto the selected LUT, continuing the process of selecting an LUT, forming a group of circuit elements and mapping until all the circuit elements have been mapped, wherein the cascade logic associated with each LUT is also incorporated in the steps of forming the group of circuit elements and the mapping of the group; and wherein the cascade logic is incorporated only after either all circuit elements have initially been mapped onto LUTs or some circuit elements remain unmapped even after all LUTs have been utilized.