1. A memory device comprising: a memory; and a memory controller comprising an encoder, wherein the encoder is configured to receive first data to be written to the memory, generate a first set of cyclic redundancy codes corresponding to the first data, determine whether the first data is valid data, in response to determining that the first data is valid data, (i) modify the first set of cyclic redundancy codes to generate a second set of cyclic redundancy codes, and (ii) append the second set of cyclic redundancy codes to the first data to generate modified data, and in response to determining that the first data represents erased data, append the first set of cyclic redundancy codes to the first data to generate the modified data, wherein the memory controller is configured to write, to the memory, the modified data.