1. An integrated circuit (IC) comprising: trace logic for operably coupling to a system memory element and for providing trace information for a signal processing system, the trace logic comprising: trigger detection logic for detecting a trace trigger in response to a first address being transmitted on a virtual bus between a system core element and a cache memory element; memory access logic arranged to provide a read request to memory access arbitration hardware, in response to the trace trigger, for data information stored at the system memory element; in response to receiving the data information, message generation logic arranged to generate a first trace message comprising the data information; and output logic for outputting the first trace message.