1. A processor, comprising: an instruction cache; and a loop control circuit configured to detect instruction loops; wherein the loop control circuit is configured, during execution of an instruction loop, to cause the processor to enter a first power saving mode of a plurality of power saving modes in response to detecting a first specified number of iterations of the instruction loop, wherein the loop control circuit is configured, during execution of the instruction loop, to cause the processor to enter a second power saving mode of the plurality of power saving modes in response to detecting a second specified number of iterations of the instruction loop, wherein the second specified number is larger than the first specified number, and wherein the processor is configured to reduce power to the instruction cache during the first power saving mode and during the second power saving mode.