1. A command decoder for a memory system configured to perform an operation requested through the use of a plurality of command signals, the command decoder comprising: a command latch having command input nodes at which a plurality of command signals are applied, the command latch configured to latch the logic states of the command signals; an operating state circuit configured to monitor a current operating state of the memory system and generate operating state signals having a combination of logic levels indicative of the current operating state; and a command decoder circuit coupled to the command latch and the operating state circuit, the command decoder circuit configured to generate a first set of clock and control signals to perform a first operation in response to a first combination of latched logic states of the command signals and a first combination of logic levels of the operating state signals and configured to generate a second set of clock and control signals to perform a second operation in response to the first combination of logic states of the command signals and a second combination of logic levels of the operating state signals, the command decoder circuit further configured to generate a third set of clock and control signals in accordance with a second combination of latched logic states of the command signals and the first combination of logic levels of the operating state signals.