1. A computing machine embodied in an integrated circuit comprising: a memory interface coupled to an external memory; a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory; a memory controller configured to allow accesses by the heterogeneous computational nodes to the memory in response to the memory requests; and a programmable interconnection network providing interconnections among the heterogeneous computational nodes and the memory controller, the interconnection network to route the requests from the heterogeneous computational nodes to the memory controller, route data for the requests between the heterogeneous computational nodes and the memory via the memory controller, and route data between the heterogeneous computational nodes.