1. An image processing pipeline having a plurality of serially chained stages for image processing in a digital still camera, said serially chained stages comprising: at least one combination of a line memory receiving data from a prior serially chained stage and a programmable data processor receiving data from said line memory operable to perform a programmable data processing function upon input data received from said line memory thereby producing output data, said at least one programmable data processor including a matrix of super arithmetic logic units and further including a data routing block for receiving data from the corresponding line memory and routing data to selected super arithmetic logic units, a constant routing block for receiving data constants and routing said data constants to selected super arithmetic logic units, and a data routing block connected to said data routing block and said constant routing block and programmable to control data routing and constant routing to said super arithmetic logic units; and at least one fixed hardware block receiving data from a prior serially chained stage and supplying data to a subsequent serially chained stage constructed to perform a fixed data processing function upon input data and thereby producing output data.