1. A memory, comprising: a memory array comprising a plurality of cells arranged in rows and columns, each cell comprising devices for storing a bit of data; a plurality of bit lines, each bit line coupled to the cells in a corresponding column of the memory array; a plurality of logic circuits, a first input of each logic circuit coupled to a corresponding bit line and an output of each logic circuit coupled to the corresponding bit line, wherein each logic circuit is configured to perform one or more logical operations using data received on the first input and output a result from the one or more logical operations to the corresponding bit line via the output; a row buffer comprising a plurality of memory elements, each memory element coupled between one of the plurality of logic circuits and a corresponding bit line, an input of each memory element coupled to the corresponding bit line, and an output of each memory element coupled to the first input of the one of the plurality of logic circuits; a plurality of read outputs; a plurality of read demultiplexers, each read demultiplexer coupled between one of the plurality of memory elements and the corresponding logic circuit, an input of each read demultiplexer coupled to the output of the one of the plurality of memory elements, a first output of each read demultiplexer coupled to a corresponding read output, and a second output of each read demultiplexer coupled to the first input of the corresponding logic circuit; and a logical operation input coupled to a select input of each read demultiplexer, wherein, based on a logical state of the logical operation input, each read demultiplexer selectively outputs a value from the output of the one of the plurality of memory elements to either the corresponding read output or the first input of the corresponding logic circuit.