1. An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP), comprising: a memory for storing a set of instructions of a test instruction set architecture; and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP; wherein the set of instructions of the test instruction set architecture comprises: a first set of instructions comprising a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor; and a second set of instructions comprising a plurality of test instructions associated with the TAP; wherein the instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form thereby the set of instructions of the test instruction set architecture.