1. A method for making an integrated circuit with an array of identical computational units on said integrated circuit, the method comprising the computer-implemented acts of: including a predetermined number of redundant computational units in said array of identical computational units; using a self-disabling logic in each of said identical computational units, wherein said self-disabling logic is adapted to preventing loading of initialization data and operation of defective computational units, if any; and automatic re-mapping from said defective computational units to non-disabled computational units in said array for receiving said initialization data that was prevented from being loaded at said defective computational units.