1. A simulation system for simulating a hardware description language (HDL), comprising: a controller that comprises: a time wheel module comprising a plurality of physical queues to which virtual queues that represent an HDL simulator description are mapped; and control logic which controls the mapping of the virtual queues to physical queues to represent an advancement of time; and a logic processor that comprises: an instruction fetch unit configured to retrieve and buffer a plurality of simulation instructions in response to the controller; an instruction decode unit configured to receive and decode instructions from the instruction fetch unit; a four-state register file comprising a plurality of pairs of registers to load data in accordance with the decoded instructions, each register of a pair corresponding to a Verilog data structure; and an arithmetic logic unit configured to use hardware device language semantic arithmetic, logical, and comparison operations on data in the pairs of registers.