1. A circuit for modifying data in a display memory organized in arrays of data for bit-mapped graphic display, comprising: first memory means for receiving and holding a first block of data from said display memory; a linear pattern generator, responsive to input signals, for generating signals corresponding to a selected linear pattern for said first block in approximately the same time as said first block is received by said first memory means; second memory means for holding said generated signals from said linear pattern generator; logic means for combining said first block and said second memory means signals into a modified first block for return to said display memory.