1. An integrated circuit which implements the multiplication of a multiplicand and a multiplier in two's complement format, the integrated circuit comprising: a plurality of logical gates, arranged to receive the multiplicand and the multiplier and to generate summands for two's complement multiplication, the summands arranged in columns; a reduction means, coupled to the plurality of logical gates, for reducing the summands generated by the plurality of logical gates so there is a maximum of two summands in each column, the reduction means including a plurality of adders arranged in rows so that each row of adders reduces a maximum number of summands in each column to a next lower predetermined number stage; and, a final adder row which performs a final addition on summands remaining after the summands have been reduced by the reduction means.