1. A processing network for receiving a source code having one or more code paths that are each associated with one or more conditions and one or more assignments of the source code, the network comprising: a plurality of processing elements on a programmable microchip, wherein each of the processing elements have one or more instruction tables each including one or more blocks, wherein each of the code paths is associated with a block address for each of the blocks; a plurality of on-chip routers on the microchip for routing the data between the processing elements, wherein each of the on-chip routers is communicatively coupled with one or more of the processing elements; and a compiler stored on a non-transitory computer-readable memory and comprising a logic generator that generates a bit expression for each bit of the block address for each of the blocks, wherein the bit expression is a logical combination of the conditions associated with selected code paths of the code paths whose block addresses for the block have a value indicating use of the bit associated with the bit expression.