1. A method of designing an integrated circuit comprising the steps of: providing a logic cell library to a synthesis tool, the cell library including a set of 40 or less complex and simple logic functions, the set of complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic minimization; providing a high-level representation of the integrated circuit to the synthesis tool, the high-level representation including circuit representations of Boolean logic functions; using the synthesis tool to translate the high level representation of the integrated circuit into the logic representation, wherein the logic representation is completely defined using the set of complex functions and the set of simple logic functions, and wherein a logic portion of the integrated circuit is substantially defined using the set of complex functions.