1. In a super scalar processor having a memory which is addressable with respect to the combination of a page address and a page offset address, a method for detecting an overlap condition between a present storage reference instruction and a previously executed storage reference instruction, the previously executed instruction being executed prior to execution of the present instruction, the method comprising: (a) determining the page offset and byte count for the present instruction; (b) in a first processing cycle, comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction; (c) determining the page address for the present instruction; and (d) comparing the page address for the present instruction to a page address for the previously executed instruction in a processing cycle after the first processing cycle.