1. In a computer including a control unit, an arithmetic-logic unit, an input unit, an output unit, a signal storage unit, and a plurality of signal conducting buses, the improvement wherein: said signal storage unit comprises at least three stack registers of arbitrary length, each said register presenting a plurality of binary word storage locations each capable of storing a binary word and the word storage locations of each said register being connected in succession to permit shifting of such words between locations; said input unit is connected to said buses to supply a succession of binary words constituting binary encoded elements representing the atoms and constructors of a complete preorder linearized binary tree expression of a complete logic relation representing a problem to be solved, each atom representing a parameter to be operated on, each constructor defining a particular relation between two such elements, and each element being composed of at least one binary word; each of said units is connected to communicate selectively with all of said buses, and each of said stack registers is connected to communicate selectively with all of said buses in a manner to transport binary encoded elements into and out of each said stack register only via the storage location at one end thereof; and said control unit comprises means for sensing the identities of the binary encoded elements contained in the storage locations at said one end of a plurality of said registers, and means for altering the binary word of said storage location at said one end of at least one said register as a function of the identities of the binary encoded elements sensed by said means for sensing.