1. A multi-threaded processor comprising: a thread scheduler configured to receive multiple threads, each of the threads having one or more thread registers, determine a dynamic size of each of the thread registers of each of the multiple threads, create, in a unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in a unified register file's unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers, wherein the non-contiguous internal address addresses a portion of the unified memory space, wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads, wherein the thread scheduler is further configured to allocate one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads, and store content of each of the thread registers of each of the multiple threads at the internal addresses in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads; the unified register file coupled to the thread scheduler; and a processing unit coupled to the unified register file and configured to retrieve content of the thread registers of each of the multiple threads from the internal addresses in the unified memory space in accordance with the virtual register mapping that maps the one or more allocated virtual registers to internal addresses in the unified memory space.