1. A computer-implemented process for code versioning for enabling transactional memory region promotion, the computer-implemented process comprising: receiving a portion of candidate source code; outlining the portion of candidate source code received for parallel execution; wrapping a critical region with entry and exit routines to enter into a speculation sub-process, wherein the entry and exit routines also gather conflict statistics at run time; generating an outlined code portion comprising multiple loop versions using a processor; executing the outlined code portion comprising multiple loop versions; determining whether a predetermined threshold for transactional memory (TM) promotion with a first versioning condition is being met using an expression of ((number of loads+stores in single loop iteration)*(k from Equation 1)<Equation 2) && !conflictH1, wherein k is a number of iterations of a loop to be bundled into a single transaction, and Equation 1 is defined as k>x/((c+nc)*(t−1)) and Equation 2 is defined as (M/T)/cache line, wherein M is a number of bytes in a speculative buffer cache, T is a number of hardware threads and cache line represents a machine specific value of a size of a line of cache in bytes and wherein there are n iterations in a loop, each iteration having c number of cycles in a critical region, and nc number of cycles in a non-critical region, a machine specific value of transaction region enter and exit overhead of x number of cycles and t number of threads; responsive to a determination the predetermined threshold for transaction memory (TM) promotion with the first versioning condition is met, determining whether a predetermined threshold for transaction memory (TM) promotion with a second versioning condition is met using the expression; and responsive to a determination the predetermined threshold for transaction memory (TM) promotion with the second versioning condition is met; using a default lock based approach.