1. A method for cache structure and management in data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation, in an arrangement consisting of: (a) an external memory where data to be accessed and processed are stored; (b) a plurality of processor units (PU 1 ) issuing control commands and generating control parameters and memory addresses of data to be processed in said external memory; (c) a plurality of processor units (PU 2 ) to process the data; said method using a cache system comprising: (i) a deeper secondary cache memory (SCM) with higher storage capacity, having a plurality of banks and each bank having a plurality of storage lines, to read data from said external memory; (ii) a faster and wider primary cache memory (PCM) with lower storage capacity, having a plurality of banks and each bank having a plurality of storage lines, from where data are read by said PU 2 ; (iii) a control logic containing control stages and control queues, providing pre-fetching and cache coherency; to access data in said external memory, upon receiving address sequences and control parameters form said PU 1 , and to prepare data for fast access and processing by said PU 2 , wherein, said method achieves cache coherency and hides memory read latency via: (a) identifying data blocks to be processed in said external memory based on the topology and structure of the processing operation in said PU 2 ; (b) generating sufficiently large SCM control queues based on the results of (a) and determining whether the data are present in said PCM, in order for said SCM to access data in said external memory sufficiently earlier than they are needed for processing by said PU 2 ; (c) reading a block of input data from multiple banks of said SCM simultaneously in a preset number of clock cycles and abstracting said external memory data organization from the cache data organization by uncompressing and reformatting the data to hide the external data organization from said PU 2 to speed up data processing in said PU 2 ; and (d) generating sufficiently large PCM control queues based on the results of (a) and (b) to store abstracted data in said PCM in advance of the data being required by said PU 2 ; and (e) synchronizing the arrival of data and control parameters in said PU 2 to achieve cache coherency.