1. A processing unit for a data processing system including a system memory, the processing unit comprising: a processor core; a lower level cache; a higher level cache coupled to the processor core and to the lower level cache, wherein the higher level cache is configured to perform: responsive to receipt at the higher level cache of a transactional store request of the processor core generated by execution of a transactional store instruction within a memory transaction, the transactional store request specifying a target real address of a target cache line and store data: in response to the target real address hitting in the higher level cache, the higher level cache transmitting, to the lower level cache, a backup copy of the target cache line unaltered by the store data, wherein the higher level cache transmits the backup copy of the target cache line to the lower level cache only in response to the target cache line having a dirty coherence state in the higher level cache and not already being recorded as belonging to a transaction footprint of the memory transaction; the higher level cache updating the target cache line with the store data to obtain an updated target cache line; the higher level cache recording the target real address as belonging to the transaction footprint of the memory transaction; and responsive to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signaling failure of the memory transaction to the processor core, invalidating the updated target cache line in the higher level cache, and causing the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line.