1. A method for controlling power dissipation in a pipelined processor, comprising: measuring a plurality of throughput rates for a corresponding plurality of pipeline stages operating in a high-performance mode; detecting when one or more of the plurality of throughput rates are reduced to a first predetermined throughput rate; and sending a first control signal to the plurality of pipeline stages upon detecting that the plurality of throughput rates are reduced to the first predetermined throughput rate; and reconfiguring the plurality of pipeline stages in response to the first control signal to operate in a low-performance mode, thereby reducing power dissipation by the plurality of pipeline stages.