1. A low power semiconductor memory device having a normal mode and a partial array self refresh mode, comprising: a plurality of banks comprising a memory cell array; a memory control unit for generating a pre-bank selection signal related to bank selection; a bank selection signal generating unit for generating a bank selection signal which selects a bank by using the pre-bank selection signal in the normal mode and for generating a bank selection signal according to refresh properties of the banks without using the pre-bank selection signal in the partial array self refresh mode.