1. A semiconductor system comprising: a first semiconductor device configured for outputting command signals and setting signals; and a second semiconductor device configured for decoding the command signals, configured for extracting setting codes from the setting signals, and configured for testing a memory cell array accessed by address patterns during at least one operation section corresponding to the setting codes to confirm whether the memory cell array includes at least one failed memory cell, wherein the second semiconductor device includes a command flag generation circuit configured for generating the command flags and wherein the command flags are provided back to the command flag generation circuit, wherein the second semiconductor device is configured to decode the command signals to generate a storage control signal and a test start signal, wherein the second semiconductor device extracts the setting codes from the setting signals in response to the storage control signal, wherein the second semiconductor device tests the memory cell array accessed by the address patterns during the at least one operation section corresponding to the setting codes in response to the test start signal, wherein the setting codes include a first setting code, a second setting code, a third setting code and a fourth setting code; and wherein the second semiconductor device includes: a code storage circuit configured for extracting the first to fourth setting codes from the setting signals to store and output the first to fourth setting codes in response to the storage control signal; the command flag generation circuit configured for generating first to third command flags from the first to fourth setting codes in response to the test start signal; and a test circuit configured for generating and storing pass/fail information using a write operation for writing data patterns into the memory cell array accessed by row address patterns and column address patterns generated in response to the test start signal and a read operation for reading out data stored in the memory cell array.