1. Double-precision floating-point multiplication circuitry that performs a double-precision floating-point multiplication of first and second double-precision floating-point numbers, comprising: a first specialized processing block that generates a first bit and a first partial result of the double-precision floating-point multiplication; and a second specialized processing block that comprises: a first arithmetic operator circuit that computes a product of a first portion of the first double-precision floating-point number and a second portion of the second double-precision floating-point number, a second arithmetic operator circuit that computes a sum of the product and the first partial result, and an inter-block signaling circuit that generates a second bit and a second partial result based on the sum, and a third bit based on the sum and the first bit.