1. A multi-channel shared resource processor coupled to an external dispatcher system which distributes a plurality of prioritized, independent tasks to a plurality of processor channels in the processor, said multi-channel shared resource processor comprising: a central processor unit; means coupled to said central processor for selecting which of the plurality of processor channels will be serviced on a prioritized basis by the central processor unit; means coupled to said central processor for monitoring the status of the processor channels selected to be serviced by the selecting means; means coupled to the selecting means and to said central processor unit, for decoding instructions to be processed by the selected processor channels to enable the operation of the central processor unit; an external memory means; means coupled to said selecting means and coupled between said central processor and said external memory means and responsive to the selecting means, for transferring blocks of data to and from the external memory means; wherein the plurality of processor channels share a multiphase instruction execution cycle having an odd and an even partition and wherein the selecting means includes: means for assigning the selected channels to an even partition and to an odd partition of the multiphase instruction cycle; a first means for generating a plurality of phase and gated-clock signals; and a first means, responsive to the first generating means, for determining which of the processor channels will contend for the even partition and for the odd partition of a multiphase instruction cycle.