1. A shared register system for a dual-instruction-set processor, the shared register system comprising: a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set, the first instruction set having a first encoding of operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes; first means, coupled to the shared register, for accessing the shared register from the first instruction set, the first means writing information into the shared register responsive to a first subset of instructions from the first instruction set; and second means, coupled to the shared register, for accessing the shared register from the second instruction set, the second means reading information from the shared register responsive to a second subset of instructions from the second instruction set, wherein each instruction in the first subset of instructions from the first instruction set comprises a first opcode field indicating the operation encoded and a destination field specifying the shared register, and wherein each instruction in the second subset of instructions from the second instruction set comprises a second opcode field indicating the operation encoded and a source field specifying the shared register; wherein the first subset of instructions have first opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations and wherein the second subset of instructions have second opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations; wherein the shared register is in a plurality of general-purpose registers in the dual-instruction-set processor, the source field and the destination field selecting any one register in the plurality of general-purpose registers, the one register selected being the shared register for transferring information between the first program and the second program; wherein the first means for accessing the shared register from the first instruction set includes means for reading and means for writing information into the shared register; and wherein the second instruction set is a reduced instruction set computer (RISC) instruction set and the first instruction set is a complex instruction set computer (CISC) instruction set, whereby information is transferred from the first program to the second program using the shared register.