1. A test access mechanism for a circuit under test, the circuit under test having a functional portion to be tested, the functional portion implementing one or more predetermined circuit functions, the test access mechanism comprising: a test portion coupled to the functional portion, the test portion being scannable to input predetermined test data and clock the predetermined test data through a scan path of the test portion, the test portion using at least two feedback paths from predetermined points in the scan path and performing a predetermined logic function to provide a series of-built-in self-test data bits which are clocked through the scan path to provide test data.