1. A semiconductor memory device comprising: a plurality of pairs of bit lines; a plurality of word lines intersecting said plurality of pairs of bit lines; a memory cell array having a plurality of memory cells arranged at intersections of said pairs of bit lines and said word lines in a matrix and each holding one of binary data; operating mode setting means responsive to an externally applied indication for activating a first operating mode signal; internal address generation means responsive to activation of said first operating mode signal for outputting internal address signals sequentially selecting said memory cells such that the order of said internal address signals corresponds to that of physical addresses of said memory cells; memory cell selecting means responsive to each of said internal address signals during the active state of said first operating mode signal for selecting a corresponding memory cell to write data; and internal data generation means for outputting internal data to said memory cell selecting means to write said binary data in a checker pattern into memory cells sequentially selected by said internal address signals depending on an arrangement of said plurality of pairs of bit lines, a plurality of word lines and of a plurality of memory cells.