1. A computer system, comprising: a) a microprocessor; b) an external memory containing a plurality of instructions to be executed by said microprocessor; said microprocessor including: a fetching unit adapted to retrieve program instructions for a plurality of instruction sets, including branch instructions; a branch prediction unit adapted to receive said program instructions from said fetching unit, analyze said program instructions to identify said branch instructions, determine a first branch prediction for each of said branch instructions, and direct said fetching unit to retrieve said program instructions in an order corresponding to said first branch predictions; a decode unit adapted to receive said program instructions in the order determined by said branch prediction unit, decode said program instructions into micro-operations, and determine a decoded branch micro-operation corresponding to each of said branch instructions requiring verification; an execution engine unit adapted to execute said micro-operations and determine said decoded branch outcome for each of said decoded branch micro-operations and communicate each said decoded branch outcome of taken to said first or second fetching unit such that said first or second fetching unit can re-retrieve said program instructions in a corrected order corresponding to each incorrect said first branch prediction; a branch target buffer adapted to receive said actual outcome of each said branch instruction from said execution engine and generate a set of previously encountered branches, wherein each of said program instructions received from said fetching unit has an address which is compared to said set, and wherein said branch target buffer determines a preliminary branch prediction based on the intersection of said set and said address; and a branch address calculator adapted to received decoded operation information from said decode unit corresponding to each of said program instructions, receive said preliminary branch prediction from said branch target buffer, and correct said preliminary branch prediction based on said decoded operation information to generate a corrected branch prediction, wherein said first branch prediction comprises said corrected branch prediction if said corrected branch prediction does not equal said preliminary branch prediction and said first branch prediction comprises said preliminary branch prediction if said preliminary branch prediction equals said corrected branch prediction.