1. A library test circuit for verifying functions of a plurality of, standard cell library logic cells, the library test circuit comprising: a core module including a plurality of standard cell library logic cells, each logic cell having a predetermined number of input vector combinations, the core module outputting test result signals according to a standard cell library; a first switch bank for outputting a first input signal to the core module so as to select cell identifiers corresponding to respective logic cells; and a second switch bank for outputting a second input signal to the core module so as to select pattern identifiers corresponding to input vector combinations of each logic cell.