1. A processor comprising: a fetch unit wherein said fetch unit, in sequence, fetches an instruction fetch group including at least one branch instruction and then prefetches an instruction prefetch group irrespective of a location of a branch target of said at least one branch; an instruction store for storing said instruction fetch group including at least one branch instruction and said instruction prefetch group wherein said instruction prefetch group sequentially follows said instruction fetch group; and logic to characterize a branch target of said at least one branch instruction with respect to fetch group boundaries of said instruction fetch group and said instruction prefetch group, and the processor tailoring instruction prefetching based, at least in part, on the characterizations of the branch target.