1. A superscalar microprocessor comprising: a prefetch unit to prefetch a plurality of instructions from a memory in a predetermined program order; a buffer placed subsequent to said prefetch unit to buffer said prefetched instructions, wherein the prefetched instructions are arranged in least two groups of instructions in the buffer; a decoder to decode two or more instructions among said buffered instructions simultaneously; a plurality of functional units to execute instructions simultaneously; a register file used by the functional units in executing decoded instructions, said register file comprising a plurality of registers for storing out of order execution results, said registers being arranged in a plurality of groups, wherein a register used for storing a result of a particular instruction is determined by a position of that instruction in the buffer, and a mechanism to avoid two or more of said functional units simultaneously referring to a same one of said registers when executing instructions simultaneously; a dependency check unit to determine a dependency among said decoded instructions in at least two groups of instructions from the buffer based on service conditions of said register and at least one flag of a processor state register; and a dispatch circuit to allocate out of order execution of said decoded instructions when said dependency check unit determines that there is no dependency among said decoded instructions, wherein the dispatch circuit is capable of allocating instructions from different groups for simultaneous execution.