1. A device structure comprising: a first transistor including a first gate electrode with a vertical sidewall, a first gate dielectric disposed on the vertical sidewall of said first gate electrode, a plurality of first semiconducting carbon nanotubes each having a first end, a second end, and a channel region between said first and second ends and disposed adjacent to said first gate dielectric on said vertical sidewall of said first gate electrode, a first source/drain contact electrically coupled with said first end of each of the first semiconducting carbon nanotubes, and a second source/drain contact electrically coupled with said second end of each of the first semiconducting carbon nanotubes; a second transistor including a second gate electrode with a top surface, a vertical sidewall intersecting the top surface, a second gate dielectric disposed on of the vertical sidewall of said second gate electrode and projecting above the top surface of said second gate electrode, a plurality of second semiconducting carbon nanotubes each having a first end, a second end, and a channel region between said first and second ends and disposed adjacent to said second gate dielectric on said vertical sidewall of said second gate electrode, a third source/drain contact electrically coupled with said first end of each of the second semiconducting carbon nanotubes, and a fourth source/drain contact electrically coupled with said second end of each of the second semiconducting carbon nanotubes; and a fill layer composed of a dielectric material and disposed between said second gate dielectric on said vertical sidewall of said second gate electrode and said first gate dielectric on said vertical sidewall of said first gate electrode, wherein each of the first semiconducting carbon nanotubes is positioned between said second gate dielectric on said vertical sidewall of said second gate electrode and said first gate dielectric on said vertical sidewall of said first gate electrode, and portions of the dielectric material of said fill layer are disposed between adjacent pairs of the plurality of first semiconducting carbon nanotubes and between adjacent pairs of the plurality of second semiconducting carbon nanotubes.