1. A microprocessor for executing encrypted instructions and non encrypted (plain text) instructions comprising: an instruction cache for storing both the encrypted instructions and the non encrypted instructions; fetch logic configured to fetch both the encrypted instructions and the non encrypted instructions from the instruction cache, the fetch logic further comprising: a key expander; a secure memory configured to store a plurality of master keys; key selection logic configured to select a set of one or more master keys from the secure memory based upon an instruction fetch address for an encrypted instruction, wherein the selected master keys are used by the key expander, along with the instruction fetch address, to decrypt the encrypted instructions fetched from the instruction cache; decryption logic configured to use the selected set of one or more master keys, or a decryption key provided by the key expander derived from the selected set of one or more master keys, to decrypt the encrypted instructions fetched from the instruction cache; and decryption key generation logic configured to derive a decryption key from the selected set of one or more master keys; wherein the encrypted instructions are grouped into blocks of instructions having a length not greater than the decryption key's length, and the decryption key generation logic is configured to derive a new decryption key for each block of instructions based upon a fetch address of an encrypted instruction in the block of instructions; and wherein the microprocessor executes the decrypted instructions.