1. A computer implemented method of checking electronic circuit netlists for compliance to at least one design rule, said method comprising: providing a computer readable netlist of an integrated circuit to be tested, said netlist comprising a plurality of subgraphs and candidate circuit elements; defining a template for at least one design rule, said at least one design rule comprising a candidate identifier portion and a design rule compliance portion; using said candidate identifier portion of said at least one design rule to define at least one subgraph and/or candidate circuit element to be tested, wherein said at least one subgraph or candidate circuit element to be tested are defined by either their net name pattern, connected device name pattern, arrangement of circuit components, or block of Boolean logic candidate selection rules; using a computer processor, said definition of at least one subgraph or candidate circuit element, said netlist, and said candidate identifier portion of said at least one design rule to perform a first search broadly identifying a first set of target candidate subgraphs; and using a computer processor, said first set of target subgraphs and the design rule compliance portion of said at least one design rule to identify compliance of said first set of target subgraphs to the design rule compliance portion of said at least one design rule, thereby identifying design rule noncompliant subgraphs; and either reporting or storing in memory said first set of target subgraphs and said design rule noncompliant subgraphs.