1. An array of logic simulation processors for simulating complex logic functions formed of primitive logic functions, said array comprising: a plurality of logic simulation processors; and node processing means coupled to each of said logic simulation processors for transmitting value change notices therebetween; each of said logic simulation processors including a function unit including circuit means having different logic gates for execution of different ones of said primitive logic functions; each of said logic processors further including value table means for storing present value signals, said value table means being coupled to said function unit to supply individual ones of said present value signals to said function unit; each of said logic simulation processors further including instruction table means for storing a sequence of instructions each of which specifies a particular primitive function to be executed and an address to said value table means to fetch a given one of said present value signals, said instruction table means being coupled to said value table means and said function unit to control the execution of a specified primitive function upon a given present value signal received from said value table means in response to the address contained in a given instruction.