1. An apparatus comprising: a many-core processor including a plurality of cores coupled via an interconnection fabric, each of the plurality of cores including at least one execution unit, register, buffer and cache; and a non-volatile memory coupled to the many-core processor to store resilient state data including a profile for each of the plurality of cores, the profile including an operational frequency, a power consumption level, and a functional correctness indicator for the associated core to indicate whether operation of the core is correct, as determined via self-testing performed within and by the many-core processor.