1. A method of designing a logic circuit, comprising the steps of converting an algorithm C description describing an algorithm of computation or control of the logic circuit in a C language into a functional C description describing control of hardware by rewriting the algorithm C description according to states in units of processing and describing the processing execution order as state transition (algorithm-functional C conversion step); converting the functional C description generated in the algorithm-functional C conversion step into a register transfer (RT) level C description by inserting a clock description as the conception of time into the functional C description (functional-RTLC conversion step); and converting the RT level C description generated in the functional-RTLC conversion step into a RT level description in HDL (RTLC-HDL conversion step).