1. A computing apparatus, comprising: a coarse-grained array including a plurality of processing elements; a host processor formed outside of the coarse-grained array; a central register file transmitting data between the coarse-grained array and the host processor; and an interrupt supervisor which stalls an operation of the coarse-grained array when an interrupt occurs while a loop is executed in the coarse-grained array, and enables the host processor to process the interrupt.