1. A computer processor comprising: at least one mask register that includes a number of interest bits whose values represent whether a possible event would be of interest if it did occur; and execution logic that performs operations that utilize pointers stored in a memory system operably coupled to the computer processor; wherein each pointer stores a value representing a memory address and is associated with a predefined number of event bits separate from the memory address value of the pointer; wherein the execution logic is configured to process the interest bits stored in the at least one mask register and the event bits associated with a given pointer in conjunction with the processing of a predefined memory-related operation that involves the given pointer in order to selectively output an event-of-interest signal that provides an indication that an event-of-interest has occurred; wherein the at least one mask register corresponds to at least one predefined class of memory-related operations; wherein the event bits of the given pointer are used to generate an index into the mask register; and wherein the index is used to access and select a corresponding interest bit of the mask register and then process the selected interest bit in order to selectively output the event-of-interest signal based upon the value of the selected interest bit.