1. A system, comprising: a hardware processor to execute computer instructions stored therein, the processor including: a first hardware storage structure to receive raw instruction bytes from an instruction cache; a second hardware storage structure to receive raw instruction bytes from the first storage structure and from the instruction cache; logic to consume the raw instruction bytes from the second storage structure to generate micro-instructions; logic to read the raw instruction bytes from the first storage structure for writing into the second storage structure; logic to determine a length of the micro-instructions; and logic to compare the determined length to an expected length, wherein if the determined length is equal to the expected length, de-allocating a memory location from the first storage structure corresponding to the consumed raw instruction bytes, and if the determined length is not equal to the expected length, reading raw instruction bytes corresponding to the micro-instructions of the determined length from the first storage structure and re-writing into memory locations in the second storage structure corresponding to the micro-instructions of the determined length.