1. An apparatus comprising: multiple parallel computing cores, each computing core configured to perform one or more processing operations and generate input data; multiple parallel coprocessors, wherein each of the coprocessors is part of one of the computing cores; multiple communication lines configured to transport the input data from each computing core to a designated one of the coprocessors associated with the one of the computing cores, the coprocessors configured to process the input data and generate output data; and multiple reducer circuits, wherein each of the reducer circuits is part of one of the computing cores, and wherein each of the reducer circuits is configured to receive the output data from each of the coprocessors of the associated computing core, to apply one or more functions to the output data, and to provide one or more results to the associated computing core.