1. A computer system comprising: a bus; at least one memory coupled to the bus, wherein the memory stores data and instructions; a processor having a plurality of pins coupled to the bus, wherein the processor executes a plurality of instructions that comprise an operating system and at least one application program designed to perform accesses to a first circuitry not present in the computer system, and further wherein the processor asserts a signal on a first of the plurality of pins when an access to the first circuitry occurs; a second circuitry for performing a function; and a controller coupled to the processor, said controller generating a system management interrupt in response to said signal, wherein the system management interrupt is transparent to said at least one application program and the operating system; wherein the processor receives the system management interrupt on a second of the plurality of pins, said processor further comprising a first trapping mechanism to trap accesses generated by said at least one application program in response to the system management interrupt, and a system management handler that handles the system management interrupt in an operating environment that underlies the operating system and said at least one application, such that the system management interrupt is handled transparently to the operating system and said at least one application, wherein said system management handler translates accesses generated by said at least one application program that are designated for said first circuitry to be compatible with said second circuitry in response to the system management interrupt, and the system management handler sends converted accesses to the second circuitry for completion and returns to said at least one application while said at least one application program and said operating system are unaware of the first circuitry being emulated by the processor.