1. An apparatus comprising: a decoder circuit to decode an instruction, wherein the instruction to include at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand; and execution circuitry to execute the decoded instruction to, for each data element position of the source operand, multiply to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the multiplication into a corresponding data element position of the packed data destination operand.