1. A method comprising: programming a memory cell coupled to a bit line by: programming the memory cell to an intermediate data state from an erased state; and programming the memory cell from the intermediate data state to a target data state by biasing the bit line to one of a plurality of bit line bias voltages, the bit line bias voltage determined based on the target data state, wherein the bit line bias voltage is based on a voltage difference between an intermediate state distribution and the target state distribution.