1. A cache controller for use with a processor, comprising: a plurality of mappers for receiving instructions of an instruction set, each mapper for mapping an instruction of said instruction set to a predetermined instruction width format (PIWF) configuration, wherein said plurality of mappers include at least one first mapper for receiving instructions from a fill buffer, and at least one second mapper for receiving instructions from an instruction cache; a multiplexor for receiving said PIWF configurations from said plurality of mappers and selecting, in response to a selector signal, a desired one of said PIWF configurations for decoding and execution by the processor; and a decoder for decoding the desired one of said PIWF configurations for execution by the processor.