1. A data processing apparatus comprising: processing circuitry configured to perform data processing operations in response to data processing instructions, said data processing instructions referencing logical registers; a set of physical registers configured to store data values for access by the processing circuitry when performing said data processing operations; register renaming storage configured to store a one-to-one mapping between said logical registers and said set of physical registers, the register renaming storage being accessed by the processing circuitry when performing said data processing operations in order to map the referenced logical registers to corresponding physical registers in said set of physical registers; update circuitry, responsive to a current data processing operation performed by the processing circuitry requiring data to be written in respect of multiple of said logical registers, to identify physical registers corresponding to said multiple of said logical registers in the register renaming storage, and to alter within the register renaming storage the one-to-one mapping between said multiple of said logical registers and those identified physical registers, such that the altered one-to-one mapping is employed when performing said current data processing operation; and in all instances, when said current data processing operation requires data to be written in respect of only one of said logical registers, the one-to-one mapping within the register renaming storage is retained unaltered such that the unaltered one-to-one mapping is employed when mapping each referenced logical register to the corresponding physical register during performance of said current data processing operation.