1. A method comprising: in a computer system including a first load/store execution unit, a first Level 1 (L1) data cache unit coupled to the first load/store execution unit, a second load/store execution unit, and a second L1 data cache unit coupled to the second load/store execution unit, the method comprises: directing some instructions to the first load/store execution unit and other instructions to the second load/store execution unit when executing a single thread of instructions, wherein each directed instruction is directed to one of the first or the second load/store execution units based on a characteristic of a register number which holds a base address of the load/store instruction or based on one or more prediction bits associated with the register number which holds the base address of the load/store instruction, wherein the one or more prediction bits indicate one of the first or second load/store execution units; dispatching a current load or store instruction to a selected load execution queue; if the current load or store instruction is selected for execution, accessing a selected one of the first and second L1 data cache units; determining if there is a cache hit in the selected one of the first and second L1 data cache units; and when there is no cache hit in the selected one of the first and selected L1 data cache units, determining if there is a cache hit in the one of the first and second L1 data cache units that was not selected.