1. A method of enabling a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation, the method comprising: obtaining a netlist of electrical elements, the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element.