1. A method of verifying a circuit design under test (DUT), comprising: generating a hardware model of the DUT; generating a software model of the DUT, wherein the software model includes timing information for the DUT; programming the hardware model of the DUT into a hardware functional verification system; emulating a behavior of the DUT that has been programmed into the hardware model from a first time to a second time to generate a state data set comprising bit values stored in storage components internal to the hardware functional verification system, wherein the state data set represents a state of the DUT at the second time; loading the state data set to the software simulator; and simulating a behavior of the DUT with the software model in a simulator programmed into a computer beginning from the state of the DUT at the second time.