1. An apparatus comprising a block-based processor, the block-based processor comprising: one or more processing cores; and a control unit configured, based at least in part on receiving a nullification instruction, to cause the cores to: obtain a memory instruction identification for a memory access instruction of a plurality of memory access instructions indicated by a first target field of the nullification instruction, the memory access instruction being encoded as a different instruction in a first instruction block than the nullification instruction; obtain a register identification of at least one of a plurality of registers, based on a second target field of the nullification instruction; nullify the memory access instruction associated with the memory instruction identification; nullify at least one register read associated with the register identification, wherein the at least one register read is in a second instruction block of a plurality of instruction blocks; and based on the nullified memory access instruction and the nullified at least one register, execute a subsequent memory instruction from the first instruction block, a subsequent register instruction from the second instruction block, or a subsequent memory instruction from the first instruction block and a subsequent register instruction from the second instruction block.