1. A memory cell, comprising: a silicon (Si) stack comprising a plurality of Si-based layers configured to have a first electrical state in response to application of a first electrical signal to the memory cell and a second electrical state in response to application of a second electrical singal to the memory cell, wherein the second electrical signal has a different magnitude or polarity than the first electrical signal; and a wiring layer comprised of Si or a Si derivative configured to facilitate application of the first electrical signal or the second electrical signal to the memory cell, wherein the wiring layer is formed adjacent to the Si stack at a temperature less than 400 degrees Celsius.