1. An apparatus, comprising: a processor; a memory system configured to receive instructions from the processor to access information stored by the memory system, the memory system including a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled directly to each other memory node of the plurality of memory nodes by a communications network and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation different than the instructions received from the processor, the internal message to be subsequently provided to another memory node of the plurality of memory nodes to perform the operation, wherein the other memory node subsequently generates a further internal message to forward to a subsequent one of the plurality of memory nodes, and wherein each memory node of the plurality of memory nodes is configured to aggregate the information from other memory nodes in the plurality of memory nodes to provide to the processor in response to the received instructions, a the memory node of the plurality of memory nodes comprising: a local memory configured to store information; computational logic configured to perform computational operations; and a node controller configured to control the local memory to perform memory operations and configured to control the computational logic to perform computational operations, the node controller further configured to generate messages including an instruction that is to be provided externally from the memory node, wherein the node controller is configured to determine a destination memory node for a message based on results of local operations performed in the memory node.