1. A flash memory device comprising: an array of addressable memory cells arranged in addressable blocks, the addressable blocks comprise a boot block and at least one additional memory cell block; a first address decoder circuit coupled to the boot block; a first voltage pump circuit coupled to the first address decoder circuit for providing a word line voltage signal to the boot block; a second address decoder circuit coupled to the additional memory cell block; and a second voltage pump circuit coupled to the second address decoder circuit for providing a word line voltage signal to the additional memory cell block.