1. An integrated circuit comprising: a plurality of computing nodes, at least one of the plurality computing node comprising memory; an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes to route data to at least one of the plurality of computing nodes; and a hardware task manager in the at least one of the plurality of computing nodes, the hardware task manager configured to write input data to a local memory address based on parameters associated with an input port assigned to the data.