1. A computer system comprising: a first physical processor and a second physical processor, said first physical processor having an embedded logical processor, and said second physical processor having an embedded logical processor; at least one of said logical processors in an active state, and at least one of said logical processors reserved in an inactive state; a processor error manager; a control manager adapted to determine availability of at least one of said reserved logical processors in response to an error detected in at least one of said active processors by said error manager; a processor manager in communication with said control manager, said processor manager adapted to activate at least one of said reserved logical processors determined to be available and to replace each logical processor embedded with said error detected physical processor with an available reserved logical processor of a non-failed physical processor.