1. A reconfigurable processor based on mini-cores (MCs), the reconfigurable processor comprising: MCs, each MC of the MCs comprising a group of function units (FUs), the group of FUs being configured to execute a loop iteration independently; a sub memory connected to the MCs and having a hierarchical structure with each section comprising a different code portion provided to the each MC of the MCs at delayed intervals between their respective loop iterations; wherein the MCs comprise: a first MC configured to execute a first loop iteration; and a second MC configured to execute a second loop iteration, wherein each MC executes different loop iterations according to loop scheduling based on software pipelining.