1. A semiconductor memory device comprising; a plurality of memory cell arrays constituting a plurality of memory sets; a plurality read/write circuits, connected to the memory cell arrays, respectively, for performing read/write of data for the memory cell arrays; a plurality of address setting circuits for setting an address for reading/writing of the read/write circuits, a number of the address setting circuits being a maximum number of the memory sets; and switching means for switching a correspondence relationship between the memory cell arrays and the address setting circuits in response to a signal selecting a number of memory sets.