1. A processor, comprising: a scheduler configured to issue operations; and a load store unit coupled to receive memory operations issued by the scheduler and configured to execute the memory operations; wherein said load store unit is further configured to: predict whether a given load operation is dependent upon an older store operation; execute said given load operation before an address of said older store operation is computed in response to predicting that said given load operation is independent of said older store operation; detect whether said given load operation has been mispredicted subsequent to predicting that said given load operation is independent of said older store operation; and provide a replay indication to said scheduler indicating that said load operation should be reissued in response to detecting that said given load operation has been mispredicted.