1. A system for predicting a branch target for a current branch instruction having a branch address in a processor, the system comprising: a register holding a current register value, where at least a portion of the current register value is formed from a first computation, the first computation comprising a first operation on a previous register value and a set of bits from a previous branch address; and a first table storing branch target values, the first table indexed by the result of second computation on the current register value and the branch address of the current branch instruction.