1. A nonvolatile memory device, comprising: a plurality of memory banks, each including a plurality of nonvolatile memory cells; write global bit lines shared by the plurality of memory banks; read global bit lines shared by the plurality of memory banks; and a dummy global bit line arranged between the write global bit lines and the read global bit lines, wherein the dummy global bit line is configured and operable to reduce noise affecting a write global bit line involved in a write operation or noise affecting a read global bit line involved in a read operation.