1. A nonvolatile memory device comprising: a memory array configured to store data; a data register selectively coupled to said memory array, said data register configured to copy at least one page of data between said memory array and said data register; a first portion of cache selectively coupled to said data register, said first portion of cache configured to copy said at least one page of data between said data register and said first portion of cache; a second portion of cache selectively coupled to said data register and said first portion of cache, said second portion of cache configured to copy said at least one page of data between said first portion of cache and said second portion of cache; an input-output circuit selectively coupled to said second portion of cache, said input-output circuit configured to serially output a plurality of data bits of said at least one page of data; and a control logic circuit selectively coupled to said memory array, said data register, said first portion of cache, said second portion of cache, and said input-output circuit said control logic circuit configured to selectively couple said second portion of cache to said input-output circuit to copy data between said second portion of cache and said input-output circuit, said control logic circuit is further configured to simultaneously selectively couple said memory array to said data register to copy data between said memory array and said data register or to simultaneously selectively couple said data register to said first portion of cache to copy data between said data register and said first portion of cache.