1. A memory device comprising: a first memory array disposed in a first memory array layer; a second memory array disposed in a second memory array layer over the first memory array layer; a first memory layer decoder communicatively coupled to the first memory array, the first memory layer decoder being configured to decode a portion of a memory address to determine if the memory address corresponds to the first memory array; a second memory layer decoder communicatively coupled to the second memory array, the second memory layer decoder being configured to decode a portion of the memory address to determine if the memory address corresponds to the second memory array; a plurality of first word lines disposed on the first memory array layer; a plurality of second word lines disposed on the second memory array layer; a first word line driver circuit communicatively coupled to the first memory array, the first work line driver circuit of the first memory array being configured to drive one of the plurality of first word lines disposed on the first memory array layer, wherein only one word line coupled to the first memory array is selected at a time; a second word line driver circuit communicatively coupled to the second memory array, the second word line driver circuit of the second memory array being configured to drive one of the plurality of second word lines disposed on the second memory array layer, wherein only one word line coupled to the second memory array is selected at a time; and a first bit line coupled to a single memory cell in the first memory array layer and a single memory cell in the second memory array layer.