1. A method for digital signal processing, the method comprising: initiating processing a sequence of instructions followed by an interrupt, the instructions are to be processed in a sequence of pipeline slots and the interrupt is to be processed in a slot following the sequence of pipeline slots; at a decode stage, detecting if an instruction in the sequence of instructions is a branch instruction; if the sequence of instructions does not include a branch instruction, complete processing the sequence without interrupt penalty; and if a branch instruction is detected and the interrupt occupies a delay slot associated with the detected branch instruction, annulling the detected branch instruction and any instruction in the sequence between the branch instruction and an interrupt address instruction associated with the interrupt and complete processing any instruction in the sequence that precedes the detected branch instruction.