1. A data processing apparatus comprising: a register data store having a plurality of registers arranged to store data elements; a vector processing unit for executing a sequence of vector instructions, the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of said sequence of vector instructions; a skip indication storage for maintaining a skip indicator for each of said lanes of parallel processing; the vector processing unit being responsive to a vector skip instruction within said sequence of vector instructions to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes of said plurality of lanes; and the vector processing unit being responsive to a vector operation instruction within said sequence of vector instructions to perform an operation in parallel on data elements input to said plurality of lanes of parallel processing, but to exclude from the performance of said operation any lane whose associated skip indicator is set.