1. A method of propagation delay testing a single-sided delay dependent level sensitive embedded array logic unit having primary inputs and primary outputs and formed of interconnected combinational network circuit means, array circuit means and sets of sequential circuit means having access for scanning independent of said primary inputs and outputs, said method including the steps of: a. selecting for test sensitization one path from a plurality of different paths, where each of said plurality of different paths extends from primary inputs of said single-sided delay dependent level sensitive embedded array logic unit to primary outputs of said unit; b. initializing the states of said sets of sequential circuits; c. applying a test pattern to at least some of said primary inputs for said selected path; d. altering at least one of said primary inputs to the selected path; e. monitoring the output of said selected path for a change of state after a given period of time has elapsed from the altering of the primary input, whereby an indication of the propagation delay through the selected path is obtained.