1. A method in a processor for semi-synchronously copying data from a first portion of memory to a second portion of memory, the method comprising: receiving, in a processor, a call for a semi-synchronous memory copy operation which preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit, the call including at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied; placing in a queue the memory copy operation for execution by a memory controller, wherein the queue is coupled to the memory controller; continuing to execute at least one subsequent instruction as the subsequent instruction becomes available from an instruction pipeline.