1. An instruction execution control device for executing a plurality of threads including a plurality of instructions, comprising: an instruction decoder that decodes an instruction; a reservation station that receives a decoding result from the instruction decoder, and controls computing processing; a main storage reservation station that controls the generation of an address of an operand to be stored in a main storage; an instruction control mechanism which controls executed instructions so that the instructions are completed according to the sequence of a program; and a hang prevention circuit, comprises: a thread selection circuit that, when the instruction control mechanism detects that an instruction in one thread cannot be completed in a predetermined period, selects a thread of an entry that can be executed from all of the reservation stations to be same thread; and an executability selection circuit that, when a thread selected by the thread selection circuit matches with a thread of an entry of the reservation station, enables the entry to be executed from the reservation station.