1. A processor comprising: a functional unit of an instruction execution pipeline to execute an instruction to cause: comparison bank circuitry to compare one or more elements of a first input vector against an element of a second input vector; and adder circuitry coupled to said comparison bank circuitry to add a number of elements of said second input vector that match a value of said first input vector on an element by element basis of said first input vector, wherein said functional unit comprises wiring to fan-out said element of said second input vector to multiple comparison circuits of said comparison bank circuitry to perform multiple comparisons of said element against said one or more elements of said first input vector, and wiring to fan-in multiple respective values from said multiple comparison circuits to said adder circuitry to produce a scalar summation value for said element of said second input vector against said one or more elements of said first input vector.