1. A method of processing data in a single programmable processor, the method comprising: decoding a single instruction for selectively arranging data, specifying a data selection operand and a first and a second register each having a register width, the single instruction independently specifying the first register and the second register, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting any one of the plurality of data elements and each field having a value not restricted by the other fields included in the data selection operand; and providing in parallel the data elements selected by the fields to respective predetermined positions in a catenated result, wherein the predetermined positions are in the same order as the fields of the data selection operand.