1. A memory device comprising: a plurality of multilevel memory cells, wherein individual ones of the memory cells are configured to store a value that represents at least three bits; and memory control circuitry configured to control the writing of a first codeword and a second codeword within the plurality of memory cells, wherein the first and second codewords individually include a plurality of bits representing data and an associated error correction code, wherein the associated error correction code of the first codeword is encoded such that two bit errors of the first codeword can be corrected, and wherein the memory control circuitry is further configured to control the values stored within the memory cells such that individual ones of the memory cells store at least two bits of the first codeword and at least one bit of the second codeword.