1. A method for generating test simulation code that executes to simulate testing of an integrated circuit device, the method performed on a computer having a memory, a processor, and a user interface, the method comprising: displaying a device under test graphic on the user interface as a component of a graphical environment model, the device under test graphic corresponding to source code that executes on a simulator to represent an integrated circuit device; receiving an add-graphic input signal via the interface; in response to receiving the add-graphic input signal, displaying at least one verification graphic as an element of a graphical environment model, each verification graphic associated with source code that executes on a simulator to simulate a verification model interacting with the integrated circuit device; presenting, via the user interface, an array of available connection signals; receiving an add-connection input signal via the user interface; in response to receiving the add-connection input signal, assigning, with the processor, at least one connection signal to the verification graphic in the graphical environment model based on the add-connection input signal, each connection signal corresponding to source code that executes on a simulator to represent a connection between the verification model and the integrated circuit device; receiving a generation input signal via the user interface; and in response to receiving the generation input signal, generating with the processor a test simulation code based at least in part on the source code associated with the verification graphic and the assigned connection signal in the graphical environment model, the test code simulating the operation of the integrated circuit device upon execution on a simulator.