1. A memory system comprising: a non-volatile semiconductor memory device including a memory area including a plurality of non-volatile memory cells, a status register indicating the internal condition and an external terminal for outputting at least a part of contents of said status register; and a controller for issuing instruction of write process to said non-volatile semiconductor memory device and management of defective write area, wherein said status register includes a first bit for indicating whether it is possible that normal write process can be conducted by executing again the write process or not and said controller issues again the write instruction to the same area depending on the condition of said first bit.