1. A digital processor having programmable exception processing latency, comprising: a central processing unit (CPU) of a digital processor operable to execute instructions with variable execution times, an exception controller coupled with said CPU, wherein when said CPU receives an exception signal a minimum exception latency time depends on an execution time of an instruction that needs to be executed before an exception can be served by the CPU, a control register coupled with said CPU, wherein the control register is operable to set the operation mode of said CPU in at least one of two modes, wherein in a first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time depending on an execution time of a pending instruction which must be completed before serving the exception.