1. A data processing system comprising: a system bus; an addressable main memory coupled to said bus, said main memory including a plurality of sets of word locations, each set of word locations being defined by an address; a central processor unit coupled to said bus; a cache coupled to said bus including, a data buffer having a plurality of word locations for storing data words arranged in a plurality of sets of word locations defined by said address; and a directory having a plurality of word locations corresponding to the number of sets in said data buffer, each word location of said directory storing an address of a corresponding one of said words of said set stored in said data buffer; said cache further including mode control means coupled to said bus for receiving an initialization signal therefrom, indicative of said system startup operation for initializing; cache main memory request means coupled to said mode control means for generating a sequence of main memory requests when conditioned by said mode control means; and address generation means for generating main memory addresses included within said requests, said address generation means coupled to said bus and to said main memory requests means, said address generation means being conditioned by said request means to transfer a predetermined sequence of addresses included within corresponding ones of said sequence of requests to said system bus, said main memory in response to said requests applying to said system bus, information read out from the word locations corresponding to said sequences of addresses for writing into said data buffer and said directory thereby placing information stored in said cache in a known state.