1. A system for implementing absolute address branching in a reduced instruction set computing (RISC) architecture, the system comprising: a memory; and a processing circuit, communicatively coupled to the memory, the system configured to perform: fetching, from the memory, an instruction group from the memory comprising a branch instruction of an instruction stream having a fixed instruction width; determining whether the instruction group includes the branch target address value; acquiring a branch target address value from the instruction stream, the branch target address value representing a target address of the branch instruction, the branch target address value formatted as an absolute address and sized as a multiple of the fixed instruction width; loading the branch target address value into a program counter based on the branch instruction; redirecting execution of the instruction stream to a next instruction based on the branch target address value in the program counter and determining that the instruction group includes the branch target address value; and based on determining that the instruction group does not include the branch target address value, generating and executing an internal operation sequence in a branch execution unit and a load-store unit to load the branch target address value from the memory and update the program counter.