1. In a microprocessor having a plurality of physical registers, a method for managing said plurality of physical registers, said method comprising steps of: providing a first structure for holding information identifying available physical registers that are free to be assigned as a destination operand for instructions executing on the microprocessor, said destination operand identifying where data resulting from an operation is to be stored; storing a physical register assignment in a second structure noting that a selected one of the physical registers is assigned as a destination operand for a selected instruction executing on the microprocessor; providing a third structure for holding information regarding available physical registers not utilized during execution of instructions; transferring said physical register assignment of said selected physical register from said second structure to said third structure after retirement of said selected instruction; and when said selected physical register is assigned as a destination operand for a subsequent instruction, transferring information identifying said physical register as available to said first structure.