1. An apparatus comprising: a memory physical layer interface (PHY) to couple to an external memory, the memory PHY comprising a controller, wherein the controller is to control training of the memory PHY for communication with the external memory based on a training algorithm so as to converge on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.