1. A processor having a first mode of operation in which it operates as a single-threaded (n.X)-bit processor and a second mode of operation in which it operates as an n-threaded X-bit processor, where n and X are positive integers greater than one, the processor comprising: a fetch stage arranged in the first mode of operation to fetch instructions from a single thread of software and in the second mode of operation to fetch instructions from each of the n threads of software; one or more configuration registers arranged to store a configuration parameter, the configuration parameter indicating a width of software visible registers; a register file comprising a plurality of general purpose registers; control logic associated with the register file and arranged, in the second mode of operation, to logically divide the register file into n portions and to control access to the portions, each portion being arranged to store data for one of the n threads of the software; and one or more execution units arranged to execute instructions from the single thread in the first mode of operation and to execute instructions from the n threads in the second mode of operation, wherein the fetch stage, control logic and functional units are each arranged to switch between the first and second modes of operation dependent upon a value of the configuration parameter.