1. A processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of said instructions defining a memory access operation, comprising: a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer; an instruction issue stage for issuing instructions from the instruction buffers; and a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage, said memory access stage comprising: (1) detecting logic adapted to detect whether a memory access operation is defined in each of said instructions issued by the instruction issue stage, and (2) instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected in one of said instructions issued by the instruction issue stage.