1. A parallel processor array system, and comprising, a plurality of elementary processors including a first and a final processor, said plurality of processors being configured into a parallel architecture, and a plurality of memories each of said memories for being associated with and connected to a respective one of said plurality of processors and to means for interconnecting said plurality of processors, each of said plurality of processors being adapted to perform synchronous data exchange between itself and neighboring processors for facilitating low level processing by said processors of data, wherein each of said processors includes an asynchronous addressing module and said parallel processor array system includes a plurality of cells, each of said cells being associated with and connected to a given processor and also being connected to cells associated with and connected to neighboring processors, the cell associated with and connected to said first processor being connected to the cell associated with and connected to said final processor, said cells thus connected forming a ring network for permitting circulation of messages involving asynchronous exchange of data between at least one of said plurality of processors and at least one other of said plurality of processors for permitting said plurality of processors to perform mid-level symbolic processing of said data.