1. An apparatus comprising: fetch circuitry to fetch instructions, including vector instructions; decode circuitry to decode fetched instructions, including fetched vector instructions; a plurality of vector registers; and execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to: receive a first decoded vector instruction to update a liner feedback shift register (LFSR) for stream cipher operations, wherein the first decoded vector instruction specifies two or more of the plurality of vector registers as operands; receive a second decoded vector instruction to update a state of a finite state machine (FSM), wherein the FSM receives inputs from re-ordered bits of the LFSR, and wherein the second decoded vector instruction specifies two or more of the plurality of vector registers as operands; and execute the first decoded vector instruction and the second decoded vector instruction in a single-instruction multiple data (SIMD) pipeline.