1. A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics, said method comprising the steps of: transforming circuit layout of said integrated circuit into a logic representation with PMOS part and NMOS part, and P and N devices of said integrated circuit into edges; selecting between said PMOS part and NMOS part of said logic representation the part with deepest serial stack; making weight assignment to the edges of said selected part, said weight assignment starting from an output terminal in said selected part to a Power V dd or Ground V ss in said selected part in a non-increasing order; generating a weighted graph based on said selected part and said weight assignment; and applying a heuristics algorithm using said weighted graph to generate said input vector for said integrated circuit.