1. A programmable processor comprising: a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a register file containing a plurality of registers each having a register width, the register file coupled to the data path and operable to support processing of a plurality of threads; an execution unit coupled to the data path, the execution unit operable to execute a plurality of instruction streams from the plurality of threads, each instruction stream including a single instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result, each of the data elements having an elemental width smaller than the register width.