1. A hybrid programmable logic device comprising: a processor comprising fixed logic elements, wherein in the processor is disposed in a first layer; a programmable logic element disposed in the first layer; and interface circuitry that delivers signal from the programmable logic element to the processor, the interface circuitry comprising: an input multiplexor coupled to the programmable logic element that receives the signal; an interface buffer that buffers the signal from the input multiplexor; and an interface port coupled to the processor that receives the signal from the interface buffer.