1. A data processing apparatus comprising: processing circuitry configured to process a plurality of threads each having associated thread state data; wherein the processing circuitry is configured to process the plurality of threads in a plurality of thread groups, each thread group comprising a number of threads processed in parallel with a common program being executed for each thread of the thread group; a plurality of thread state storage regions each comprising a fixed number of thread state entries, where each thread state entry is configured to store the thread state data for a corresponding thread of the plurality of threads; wherein at least two of the thread state storage regions have different fixed numbers of the thread state entries; and the processing circuitry is configured to process within the same thread group threads having thread state data stored in thread state entries of the same thread state storage region, and to process within different thread groups threads having thread state data stored in thread state entries of different thread state storage regions.