1. An apparatus for a dual mode low density parity check (LDPC) decoder comprising: edge random access memory (RAM); last-in-first-out/first-in-first-out (LIFO/FIFO) RAM; channel RAM; and a plurality of parallel datapath engines, wherein the datapath engines comprise a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, wherein the SBD datapath comprises a shifter, an accumulator, a plurality of multiplexers, and a g( )_sbd calculator, and wherein the LBD datapath comprises the shifter, the plurality of multiplexers, and a g′( )_lbd calculator.