1. A processor comprising: a memory; and logic configured to: store virtual address tag bits and physical address tag bits in a first portion of the memory, store data bits in a second portion of the memory, store alias way prediction values for execution of an instruction in a third portion of the memory, store exception values in a fourth portion of the memory, each exception value including exception-specific information, and store identification values in a fifth portion of the memory, each identification value based on a completion buffer identification value of a particular instruction, wherein an alias way prediction value is forwarded to an execution unit when no match exists between selected bits of a virtual address and the virtual address tag bits stored in the first portion of the memory at locations indexed by bits of the virtual address, and wherein upon a cache hit for a cache line using a way, the cache hit indicating physical address tag bits for data retrieved using the way match physical address tag bits associated with a virtual address associated with the used way, a corresponding line in the third portion of the memory is updated with a value corresponding to the used way.