1. A pipelined datapath with dynamically reconfigurable pipeline stages, comprising: a pipeline controller for receiving a system clock and a valid data signal and generating accordingly N+1 clock signals and N−1 select signals, where N is an integer greater than 1; an input register coupled to the pipeline controller, for receiving one of the clock signals and selectively receiving a datum according to the received clock signal; and N pipeline stages, coupled in series, wherein a first pipeline stage of the pipeline stages is coupled to an output terminal of the input register, and each of the pipeline stages includes: a combinational logic circuit for processing the datum; and a register for receiving one of the clock signal and selectively latching an output of the combination logic circuit according to the received clock signal; wherein each of the first to a (N−1)th pipeline stages further includes: a multiplexer for receiving one of the select signals, and selectively outputting the datum from one of the combinational logic circuit and the register into the combinational logic circuit of a next pipeline stage.