1. A circuit comprising: a storage device that stores a plurality of multi-bit node control values (NCVs) and a plurality of multi-bit result values (RVs); and a means for receiving a multi-bit input value (IV) and outputting one of the plurality of RVs, wherein the means is a hardware trie structure comprising: a plurality of internal node circuits, wherein each of the internal node circuits receives a corresponding respective one of the plurality of NCVs, wherein each of the internal node circuits further receives at least some of the bits of the IV.