1. A CORDIC engine, comprising: an N-stage CORDIC processor configured for performing N micro-iterations and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input; a counter configured for counting a number of M macro-iterations and indicating a start of the cycle iterations; and a multiplexer configured for selecting an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3 -vector CORDIC output at other times; wherein the 3-vector CORDIC output is configured to be complete after N*M clock cycles by generating the N micro-iterations for each of the M macro-iterations.