1. An integrated-circuit memory chip comprising: a memory core including an array of memory cells and a sense amplifier bank; a first signaling interface to receive a memory access command and a column address via command/address signaling links external to the integrated-circuit memory chip; a second signaling interface to receive a plurality of write data values via data signaling links external to the integrated-circuit memory chip the data signaling links being distinct from the command/address signaling links; a third signaling interface to receive a plurality of control values via external signaling links other than the command/address signaling links and the data signaling links; and core access circuitry to carry out a memory access operation with respect to the memory core in response to the memory access command, including circuitry to: decode the column address in response to the memory access command to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute the sense amplifier bank; read, out of the address-specified sense amplifiers and in response to the memory access command, first data constituted by a plurality of read data values; generate second data by selecting, as each of a plurality of constituent values of the second data, a respective read data value of the plurality of read data values of a respective write data value of the plurality of write data values based on a respective control value of the plurality of control values; and overwrite the first data within the address-specified sense amplifiers with second data in response to the memory access command.