1. A system comprising: a manufactured processor element having a fixed instruction set that defines instructions that the processor element can execute and that is not modifiable by a consumer, and a reconfigurable co-processor, wherein said processor element is not designed to natively offload to said reconfigurable co-processor instructions of an executable file that is running on the processor element; said reconfigurable co-processor comprising reconfigurable logic that is reconfigurable to have an entirety of any one of a plurality of predefined extended instruction sets for extending the fixed instruction set of the processor element for processing instructions of an executable file, each of said plurality of predefined extended instruction sets defining a plurality of instructions that the reconfigurable co-processor can execute, wherein said plurality of instructions comprise extended instructions that are not natively defined by the fixed instruction set of the processor element, and wherein the extended instruction sets are not embedded within said executable file; said processor element comprises a first instruction decode logic that is operable to decode instructions of the executable file that are defined by the processor element's fixed instruction set for execution by the processor element; and wherein the reconfigurable co-processor comprises a second instruction decode logic that is operable to decode instructions of the executable file that are defined by the extended instruction set that the reconfigurable co-processor is configured to have for execution by the reconfigurable co-processor; said reconfigurable co-processor sharing a common virtual and physical address space with said processor element; and a global shared, cache coherent physical address space, whereby the processor element comprises a physical memory and a cache, and whereby the co-processor comprises a physical memory and a cache, and wherein data contained in the processor element's cache and the co-processor's cache are maintained in a cache coherent state.