1. A data processing system comprising: memory means having an input and an output, said memory means providing a first series of instruction output signals in response to first address select signals applied to the input of said memory means and a second series of instruction output signals in response to second address select signals applied to the input of said memory means; first counter means coupled to said memory means and producing said first address select signals to be applied to the input of said memory means; second counter means coupled to said memory means and producing said second address select signals to be applied to the input of said memory means; enabling means interposed between the output of said memory means and a first input of each of said first and second counter means in coupled relationship therewith for producing one of either a first enable signal to said first counter means in response to a first predetermined instruction output signal from said memory means or a second enable signal to said second counter means in response to a second predetermined instruction output signal from said memory means; said first enable signal allowing said first counter means to produce said first address select signals applied to the input of said memory means to produce said first series of instruction output signals from said memory means, and said second enable signal allowing said second counter means to produce said second address select signals applied to the input of said memory means to produce said second series of instruction output signals from said memory means; and incrementing means coupled between the output of said memory means and a second input of each of said first and second counter means for producing a first increment signal to said first counter means in response to a third predetermined instruction output signal from said memory means or a second increment signal to said second counter means in response to a fourth predetermined instruction output signal from said memory means; said first increment signal incrementing said first counter when said first enable signal is present and said second increment signal incrementing said second counter when said second enable signal is present, and said first increment signal and said second increment signal respectively incrementing said first and second counters concurrently in response to a fifth predetermined instruction output signal from said memory means while said second enable signal is present.