1. A programmable, single chip embedded processor system for input/output applications, comprising: a modular, multiple bit, multithread processor core operable by at least four parallel and independent application threads sharing common execution logic segmented into a multiple stage processor pipeline, wherein said processor core is capable of having at least two states; a logic mechanism engaged with said processor core for executing an instruction set within said processor core; a supervisory control unit, controlled by at least one of said processor core threads, for examining said core processor state and for controlling said core processor operation; a memory for storing and executing said instruction set data; and a peripheral adaptor engaged with said processor core for transmitting input/output signals to and from said processor core.