1. A machine implemented method for use in the synthesis of RTL integrated circuit design, comprising: receiving a plurality of equivalent designs for synthesis in RTL; determining a data flow graph representation of each design, each data flow graph representation having at least one input with an input bit width, at least one internal signal with an internal bit width, and at a least one output with an output bit width; deriving first modified versions of each data flow graph representation by restricting bit width for each said at least one internal signal to be equal to a largest output bit width of all the outputs, when said at least one internal signal is polynomial; comparing each first modified design against the respective design from which it was derived to determine whether it is equivalent to the respective design from which it was derived; restricting the input bit widths of said at least one input to derive second modified versions of each respective first modified version of a design determined to be functionally equivalent to the design from which it was derived; comparing said second modified designs against each other to determine which are functionally equivalent; and providing any one or more designs determined to be functionally equivalent to an RTL synthesis unit.