1. An apparatus comprising: a first processor comprising a shared inclusive cache coupled to a first core and a second core; and a circuit to, in response to an access request from the first core to the shared inclusive cache for a first cache line that is to cause a cross snoop to the second core for the first cache line: save, in a storage external to the shared inclusive cache, coherency state information of the first cache line in the shared inclusive cache, and mark the first cache line in the shared inclusive cache with an invalid state to indicate to subsequent transactions that the first cache line is invalid.