1. An apparatus, comprising: one or more NAND strings having memory cells connected along word lines and in which the memory cells of each NAND string are connected through a corresponding select gate to a corresponding bit line; and a control circuit connected to the word lines and bit lines, the control circuit configured to concurrently program a plurality of memory cells connected to a first word line from an initial state to a corresponding one of a plurality of target states; a bit line biasing circuit configured to bias bit lines corresponding to non-selected memory cells along the first word line to a program inhibit level and to bias bit lines corresponding selected memory cells along the first word line to a low supply level; a word line biasing circuit configured to raise a voltage on a set of one or more word lines including the first word line from the low supply level to a first voltage level; wherein, while the word line biasing circuit is raising the voltage on the set of one or more word lines from the low supply level to the first voltage level, the bit line biasing circuit is configured to raise the voltage on the bit lines corresponding to selected memory cells from the low supply level to a second voltage level based on a level of the rising voltage on the set of one or more word lines dependent on the target state of the corresponding selected memory cell, the second voltage level having a magnitude sufficient to turn off the corresponding select gate through which the selected memory cells connect to the corresponding bit lines; and a programming circuit configured to subsequently send a program pulse to the first word line.