1. An integrated circuit comprising: a cache having a plurality of static portions and a dynamically shared portion; a plurality of computing resources, each computing resource operable to victimize one of the plurality of static portions of the cache assigned to the computing resource and the dynamically shared portion; and re-assignment logic to reassign at least one way within a first static portion of the plurality of static portions to the dynamically shared portion, in response to tracking, over a period of time, that an access activity level of a first computing resource associated with the first static portion is below a predetermined threshold.