1. A data processing apparatus comprising: SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements; instruction decoder circuitry coupled to said SIMD data processing circuitry and responsive to program instructions to generate said control signals; said instruction decoder circuitry being responsive to a repeating multiply-accumulate (repeating MAC) instruction having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations M required, to generate control signals to control said SIMD data processing circuitry: to perform said plurality of iterations of a multiply-accumulate process, each iteration of the multiply-accumulate process comprising performing N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements; for each iteration, to determine N input data elements from said first vector and a single coefficient data element from said second vector to be multiplied with each of the N input data elements during the N multiply-accumulate operations; and to output N multiply-accumulate results derived from the N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process.