1. In a method of testing a complex integrated circuit structure having substantially more internally interconnected logic devices and bistable devices than the number of input and output terminals to the structure, which construction renders the logic devices inaccessible for discrete testing, a method for determining the relative frequency of occurrence of binary ones and zeros to be applied as test stimuli to the input terminals of the structure comprising the steps of: (1) tracing and recording all possible circuit paths backwards from each of said output terminals, or bistable device operationally connected to an output terminal, to an input terminal or bistable device operationally connected to an input terminal; (2) partitioning each of said paths into successive connected segments, each of which consists of a pair of logic devices wherein each pair consists of a logic device from the next preceding pair and a logic device from the next succeeding pair; (3) identifying the first logic device in each pair in the direction of backward trace as an X device and the second one as a Y device; (4) counting and recording the number of device inputs (NDI) for each logic device, wherein NDI equals the summation of input terminals and bistable device outputs directly or indirectly connected through intervening logic devices to the inputs of the given logic device; (5) counting and recording the number of inputs (N) to each logic device, wherein the number of inputs equals the number of lines connected as inputs to the device; (6) identifying and recording which one of the following logical functions is performed by each logic device (a) AND (b) AND/INVERT (c) OR (d) OR/INVERT; (7) computing for each input of the logic devices in the structure the probability (P.sub.min) of placing the non-controlling value onto each input of each logic device where EQU P.sub.min =3-N-(N.sup.2 2-2N+5).sup.1/2 /(2-2N); (8) setting the zero and one weights for all logic blocks to an initial value of one: (9) starting with the segment nearest the output of the structure and proceeding backwards toward the input, computing and recording the zero weight (WO) and one weight (W1) for each successive segment in each of the possible circuit paths in accordance with the following relationships: (a) If device x is an AND EQU W0'.sub.y =MAX (W0.sub.x or W0.sub.y) EQU W1'.sub.y =MAX (KW1.sub.x or W1.sub.y) (b) if device x is an AND/INVERT EQU W0'.sub.y =MAX (W1.sub.x or W0.sub.y) EQU W1'.sub.y =MAX (KW0.sub.x or W1.sub.y) (c) if device x is an OR EQU W0.sub.7 =MAX (KWO.sub.x or W0.sub.y) EQU W1'.sub.y =MAX (W1.sub.x or W1.sub.y) (d) if device x is an OR/INVERT EQU W0'".sub.y =MAX (KW1.sub.x or W0.sub.y) EQU W1'.sub.y =MAX (WO.sub.x or W1.sub.y) wherein the value of W0 and W1 inititally set at one are successively altered as the computation proceeds from segment to segment, and EQU K=((NDI.sub.x /NDI.sub.y)+R.sub.min (N.sub.x))/2 is computed for each segment pair; (10) stopping the computing and recording of step 9 when the circuit path reaches an input terminal of a bistable device; (11) for each input terminal, determine the weight value WV in accordance with the following: (a) if W0'.sub.y =W1'.sub.y WV=0 (b) if W0".sub.y =W1'.sub.y WV=1 (12) determine the weighting factor (WF) by dividing the larger of W0 or W1 by the smaller thereof, which weighting factor is the ratio of binary values to be applied to a terminal in a succession of applied input test stimuli.