1. A method of verifying a circuit design having at least one gated-clock latch, comprising: receiving a clock tree for the circuit design; identifying the at least one gated-clock latch based on information obtained from the clock tree; replacing the at least one gated-clock latch with an explicit representation of a functionality of the gated-clock latch to thereby generate a modified circuit design; performing phase abstraction on the modified circuit design; and verifying the circuit design based on the phase abstraction of the modified circuit design.