1. Apparatus for processing data comprising: a plurality of sources of memory access requests; a cache memory coupled to said plurality of sources; and cache control circuitry coupled to said cache memory and configured to control insertion of cache lines into said cache memory and eviction of cache lines from said cache memory, wherein said cache control circuitry is configured to store respective retention priority values associated with each cache line inserted into said cache memory; said cache control circuitry is configured to select a cache line for eviction from said cache memory in dependence upon said retention priority values; and said cache control circuitry is configured to set a retention priority value associated with a cache line inserted into said cache memory in dependence upon at least one of: (i) which of instruction fetch circuitry of a processor to fetch program instructions for execution and load store unit circuitry of said processor to access data values under control of said program instructions issued a memory access request that resulted in insertion of said cache line into said cache memory; and (ii) a privilege level of program execution resulting in said memory access request.