1. A computer-implemented method for verification of an intellectual property (IP) core in a system-on-chip (SoC), the method comprising: generating a plurality of verification specific abstracted views of the IP core each said plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each said abstracted view of the IP-core; and generating a unified abstracted view of the IP-core, wherein the unified abstracted view of the IP core is generated using a process comprising: tagging each said plurality of verification specific attributes with a tag that is verification specific, to enable identification of each said attribute with corresponding said verification specific abstracted view and said verification type; comparing each said plurality of attributes from said plurality of verification specific abstracted views; generating from said comparing a first output set containing groups of redundant attributes that have at least two similar attributes with different tags, generating from said comparing a second output set containing a group of unique attributes, each with a single verification specific tag; selecting one tagged attribute as a retained attribute from each of the redundant group of attributes and attaching all tags from the redundant group of attributes to the retained attribute; deleting all unselected attributes; combining said first output set with said group of unique retained attributes with multiple tags with said second set with said group of unique attributes with single tags thereby creating a unified group of attributes; integrating said combined unified groups of attributes with the IP-core, wherein at least one of the steps is performed using the computer.