1. An apparatus, comprising: functional unit logic circuitry having: a) a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure, each element of said first vector operand specifying the size of its respective dimension; b) a second register to store a second input vector operand specifying coordinates of a particular segment of said multi-dimensional structure; c) logic circuitry to calculate an address offset for said particular segment relative to an address of an origin segment of said multi-dimensional structure.