1. A cache memory control device which controls a pipeline processing on a command to access a cache memory, the cache memory control device comprising: a cache access determination device that determines whether an externally received command is a command to access the cache memory during execution of the command or a command not to access the cache memory during execution of the command, the command not to access the cache memory being a request for an area in which data is not transferred to the cache memory from a main memory or a request to write/read data to/from an ASI (address space identify) register; and a path switch device that switches a path of a command in order to put the command to access the cache memory during execution of the command in the pipeline processing and in order to output the command not to access the cache memory during execution of the command to a system controller via an external interface unit without putting the command in the pipeline processing, the external interface unit located between the cache memory and the system controller, the system controller being a device that controls a communication of requests and data between a CPU and the main memory.