1. A method of fabricating a first portion of a two-terminal memory device, comprising: forming a bottom electrode (BE) of the two-terminal memory device overlying a substrate; forming a BE insulator layer overlying the BE and the substrate; performing a first chemical-mechanical planarization (CMP) process that removes a first portion of the BE insulator layer overlying a top surface of the BE and removes a first portion of the BE; and performing a second CMP process that removes a second portion of the BE insulator layer and a second portion of the BE, and exposes top surfaces of the BE insulator layer and a top surface of the BE, wherein a step height between the top surfaces of the BE insulator layer and the top surface of the BE is less than two nanometers.