1. A nonvolatile semiconductor memory device, comprising: a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor; a pulse generator operative to generate plural different types of write pulses for varying the resistance of said variable resistor in three or more stages based on ternary or higher write data; and a selection circuit operative to select a write target memory cell from said memory cell array based on a write address and supply said write pulse generated from said pulse generator to said selected memory cell, said pulse generator generating the different types of the write pulses each including a different number of unit pulses.