1. In a data processor comprising: oscillator means for providing a periodic clock signal except in response to receiving a power-down signal; reset means for providing a reset signal in response to a predetermined condition; and instruction execution control means, operative in synchronism with said clock signal, for receiving each of a plurality of different instructions comprising an instruction stream, and, in response to receiving a predetermined power-down instruction in said instruction stream, providing said power-down signal to said oscillator means to terminate said clock signal until said reset means next provides said reset signal, said instruction execution control means proceeding to a next instruction in said instruction stream only upon resumption of said clock signal; a circuit for selectively disabling said power-down instruction, comprising: control register means for storing a predetermined control code in response to said instruction execution control means receiving a different predetermined one of said instructions in said instruction stream; and logic means responsive to said control code being stored in said control register means, for preventing said instruction execution control means from providing said power-down signal to said oscillator in response to said power-down instruction, whereby said instruction execution control means will simply proceed to said next instruction in said instruction stream.