1. A method for decomposition of a circuit for implementation on a programmable chip, the method comprising: providing a data width, a cyclic redundancy check (CRC) width, and a polynomial associated with the CRC width; expressing CRC output bits as wide Exclusive OR (XOR) operations; performing factoring with cancellation to break the wide XOR operations into XOR operations that fit in programmable chip lookup tables (LUTs), wherein performing factoring with cancellation comprises determining a plurality of costs associated with proposed extractions.