1. A data processing architecture comprising: an input device for receiving an incoming stream of data packets of unpredictable size; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute batches of data packets of unpredictable size across said processing elements such that the number of said processing elements across which each data packet is distributed is dynamically determined based at least in part on the size of the data packet; a data packet greater than a predetermined size being divided into portions and each portion distributed to a respective processing element; and a data packet less than a predetermined size being distributed to a single processing element; wherein the data processing architecture is operable to process at least one data packet at a time, wherein the processing elements are arranged in a SIMD array and operable to process different respective packet protocols at once while executing a single common instruction stream.