1. A processor, comprising: a front end including circuitry to: determine whether to apply an acyclical thread assignment scheme to code received at the processor; determine whether to apply a cyclical thread assignment scheme to code received at the processor; based upon a determined thread assignment scheme, assign first code to a static logical thread; and based upon the determined thread assignment scheme, assign second code to a rotating logical thread; and a scheduler including circuitry to: assign the static logical thread to a first physical thread; assign the static logical thread to the first physical thread upon each subsequent control flow instruction of the static logical thread, the iteration including assign the rotating logical thread to a second physical thread; and assign the rotating logical thread to a third physical thread upon a subsequent execution of the rotating logical thread.