1. A memory apparatus adapted for use with a data processing machine generating logical addresses, a logical address including a first field and a second field, to identify requested lines of data, comprising: main store means for storing data at main store locations addressed by system addresses, a system address including a system page address portion identifying a page of a plurality of lines of data in the main store means; register means, adapted for communication with the data processing machine to receieve a requesting logical address, for storing the requesting logical address; translation buffer means, in communication with the register means, for storing translation information at a translation buffer location addressed by the first field of the requesting logical address, the translation information identifying a unique system page address corresponding to a logical address; cache means, in communication with the register means and the main store means, for storing at a cache location addressed by the second field of the requesting logical address a version of a line of data from the main store means and a means for associating the line of data with a unique system page address; first means, in communication with the register means and the translation buffer, for matching the translation information stored in the translation buffer location with the requesting logical address to generate a no translation buffer match signal when the requesting logical address and the translation information do not match; translator means, in communciation with the register means and the first means for matching, for generating translation information identifying a unique system page address corresponding to the requesting logical address in response to the no translation buffer match signal; second means, in communication with the translator means and the translation buffer means, for matching the system page address identified by the translation information generated by the translator means with the system page address identified by the translation information stored in the translation buffer location to generate a no system address match signal when the identified system page addresses do not match; eviction means, in communication with the second means for matching, the cache means and the translation buffer means, for evicting lines of data from the cache means that are associated with the system page address identified by the translation information stored at the translation buffer location in response to the no system address match signal.