1. A non-volatile memory apparatus, comprising: a non-volatile memory array; and a controller in communication with the memory array, the controller configured to: receive an n-bit data block X which would, without encoding, require a first number of programmed bits to store in the memory array; and encode the n-bit data block X as an n+k-bit data block X′ requiring a second number of programmed bits to store in the memory array, the second number less, on average, than the first number.