1. A memory bank having words that are addressable by addresses and having multiple sections, the memory bank comprising: a plurality of sections, each section representing a subdivision of a word of memory, each section having a row enable line for each row of the memory and a column enable line for each column of the memory for enabling access to a subdivision of a word of memory, each section having a section enable line for enabling access to that section; for each row of each section, row enabler logic that enables the row enable line for that row of that section only when the section enable line for that section is enabled; and for each section, column enabler logic that enables a column enable line for that section only when the section enable line for that section is enabled.