1. A digital processor of the type having: instruction word access means for producing instruction words on a plurality of parallel output lines; an arithmetic unit having inputs and outputs and control signal input means for receiving controls for defining the operation thereof; data storage means having input control means and output control means for defining store and recall of data therein, the data storage means having data outputs interconnected by coupling means with inputs of the arithmetic logic unit and having data inputs interconnected by coupling means with outputs of the arithmetic logic unit; control means including decoder means connected to receive instruction words from the plurality of parallel output lines and operative to produce control signals for defining the operation of the arithmetic unit and the coupling means and for defining store and recall of data in the data storage means via said input control means and output control means; the improvement wherein the control means comprises: first connection means for applying certain instructions from the plurality of parallel outputs in non-modified form to the decoder means, logic means responsive to the contents of the instruction words included in the first connection means for completing the connection; second connection means for applying other selected instructions from the plurality of parallel inputs to the decoder means in a modified form, conversion means included in the second connection means to change the logical content of parts of the instruction words in the other selected instructions to correspond to the contents of the instruction words of said certain instructions.