1. A logic circuit for multiplication of an matrix by a or by a matrix, where m is a number of rows and n is a number of columns, and wherein each successive row m of n elements is a predetermined row permutation of a preceding row, the circuit comprising: n multiplication circuits each having an input and an output which returns the value of said input multiplied by a predetermined multiplicand; n logic circuits, each for executing a predetermined logical combination of a first input and a second input to provide a logical output, the first input being coupled to the output of a corresponding one of the n multiplication circuits; n registers for receiving said logical output; feedback logic for routing the contents of each register to a selected one of the second inputs in accordance with a feedback plan that corresponds to the predetermined row permutation; and control means for successively providing as input to each of the n multiplication circuits each element in the or matrix.