1. An instruction level parallel processing processor system, comprising: N instruction execution units for executing sequences of instructions concurrently, where N is a non-zero positive integer; instruction supply means for supplying instructions to be executed by said N instruction execution units concurrently; and trap control means for controlling said N instruction execution units such that when M instructions are supplied concurrently from the instruction supply means to said N instruction execution units, where M is a non-zero positive integer and N.gtoreq.M, and when an exception is caused in an execution of at least one of said M instructions at one clock cycle, concurrent executions of all of said M instructions supplied to said N instruction execution units are aborted at said one clock cycle by sending abort signals to all of said N instruction execution units at said one clock cycle.