1. A circuit comprising: a memory element; and a control circuit to update contents of the memory element, the control circuit including a plurality of storage elements, each storage element corresponding to an entry of a plurality of entries of the memory element, circuitry to ascertain a state of each of the plurality of entries and to provide a first entry number corresponding to an entry of the plurality of entries in an invalid state, a counter to provide a count value to represent a second entry number of an entry to be modified when all of the plurality of entries are in a valid state, and a select element coupled to both the circuitry and the counter, the select element to output either the first entry number or the count value.