1. A method of interconnecting blocks of heterogeneous dimensions for a network-on-chip architecture, the method comprising: determining a size of a mesh reference grid based on physical dimensions of a chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions; overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on a guidance floor plan for placement of the blocks of heterogeneous dimensions; removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions; and mapping, using a computer, inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.