1. A Gray code counter wherein binary expressions are processed in a sequence, each expression differing from the preceding expression by one bit in one place only, comprising: a first logic circuit for receiving a clock input signal and for providing a first modular output of two binary bits and an increment signal; a carry logic circuit coupled to said first logic circuit for receiving said modular output of two binary bits and said increment signal, including means for providing a carry signal; at least one logic circuit coupled to said carry logic circuit, said at least one logic circuit having means for receiving a clock input signal, and a carry signal from said carry logic circuit, said carry signal being independent of the state of said at least one logic circuit, said at least one logic circuit providing a second modular output of a plurality of binary bits; means for combining said first and second modular outputs to form a sequence of binary bit expressions, each expression representing a state of said counter, wherein only one bit of each succeeding binary bit expression of said sequence is changed in one place of said expression.