1. A data processing system including a main memory subsystem, a plurality of I/O controllers, a central processing unit (CPU) and a cache memory, all coupled in common to a system bus, the system comprising: a monitor interface unit coupled to said system bus, said central processor unit by a CPU bus, and said cache memory by a cache bus for monitoring information signals and transferring hit signals representative of predetermined signals of said information signals to monitors for generating performance data, said monitor interface unit comprising: bus selection means for selecting said information signals from said system bus or from said cache bus; wherein said bus selection means comprises: mode switching means for generating a selection signal for selecting said information signals from said system bus or said cache bus; and multiplexer means coupled to said mode switching means and responsive to said selecting signal in a first state for selecting system bus signals representative of said information signals from said system bus and said selection signal in a second state for selecting cache bus signals representative of said information signals from said cache bus; interface input storage means coupled to said bus selection means for temporarily storing said information signals from said system bus and said cache bus and coupled to said CPU for storing said information signals from said CPU bus; wherein said input storage means comprises: input latch means coupled to said multiplexer means for storing said system bus signals when said multiplexer means is responsive to said system bus and storing said cache bus signals when said multiplexer means is responsive to said cache bus for generating a first set of address signals to the programmable hit matrix memory, and for storing CPU bus signals from said CPU bus for generating a second set of address signals to the programmable hit matrix memory; programmable hit matrix memory coupled to said input storage means and addressable by said information signals from said interface input storage means for generating said hit signals in response to said predetermined signals; and of said information signals; and the system further comprising monitor means coupled to said output storage means and responsive to the hit signals for generating statistical data regarding ocurrence of said predetermined signals on the system bus, CPU bus and cache bus.