1. A method of optimizing a routed layout of an integrated circuit design according to one or more optimization requirements, wherein said routed layout having a plurality of nets, said method comprising the steps of: constructing from said routed layout a geotopological encoding graph that encodes unmodifiable nets geometrically and modifiable nets topologically; generating a geotopological layout that simultaneously represents said unmodifiable nets with geometrical wiring paths and said modifiable nets with topological wiring paths; modifying said geotopological layout in accordance with said one or more optimization requirements; and transforming said geotopological layout to generate an optimized geometrical layout of said integrated circuit design.