1. A digital signal processor evaluation chip comprising: a clock generating circuit for generating a multi-phase clock signal; a first gating circuit coupled to said clock generating circuit, for gating said multi-phase clock signal with a first break signal, thus outputting a first clock signal when said first break signal is in one state in a first period and halting the first clock signal when said first break signal is in another state in a second period after said first period and in a third period after said second period; a second gating circuit coupled to said clock generating circuit, for gating said multi-phase clock signal with a second break signal, thus outputting a second clock signal when said second break signal is in one state in said first and second periods and halting said second clock signal when said second break signal is in another state in said third period; a controlling circuit, coupled to said first gating circuit and driven by said first clock signal, for fetching and decoding instructions when said first clock signal is output; a processing circuit, coupled to said second gating circuit and said controlling circuit, driven by said second clock signal, and having at least one register for performing arithmetic operations and a transfer operation on data in said register responsive to said instructions when said second clock signal is output; and a data bus, coupled to said processing circuit, for receiving data from said register when said transfer operation is performed.