1. A device, comprising: a Peripheral Component Interconnect (PCI) segment including a certain number of buses; a master processor and one or more slave processors, wherein at a booting of the device, each of the master and slave processors is to have access to a different subset of the buses of the PCI segment such that the master and slave processors do not have access to the same buses, wherein the master and slave processors are central processing units (CPUs); and a service unit to control the master and slave processors, wherein subsequent to the booting of the device, the master processor is to quiesce the one or more slave processors, wherein to quiesce is to pause a running process of the one or more slave processors, and after the master processor indicates that the one or more slave processors are quiesced, the service unit is to assign each of the master and slave processors to one of a plurality of instances of the PCI segment causing each of the master and slave processors to have access to all of the buses of the PCI segment at different instances of the PCI segment.