1. A central processing unit comprising, in combination: a control memory for storing a plurality of microprogram words each of which specifies the nature of a sub-operation performed by said processing unit and each of which comprises a plurality of control fields; a microprogram control unit comprising, in combination, first and second stack memories for respectively storing control counts and return addresses, a stack pointer counter for addressing said stack memories, means responsive to a first of said microprogram word control fields for selectively incrementing, retaining, or decrementing the count held in said stack pointer counter, means for supplying a control count from a second of said microprogram word control fields to the location in said first stack memory addressed by said stack pointer counter, and means responsive to said first control field and to the control count in the addressed location in said first stack memory for supplying microprogram word addresses to said control memory, each microprogram word address being selectively derived from (1) the return address in said second stack memory addressed by said stack pointer counter, (2) a branch address from a second of said microprogram word control fields, or (3) a current microprogram word address previously supplied to said control memory; a plurality of bipolar integrated circuit microprocessors cascaded to form an arithmetic and logic unit and a set of general registers, said arithmetic and logic unit have a control input connected to said control memory for selecting one of a plurality of predetermined operations under the control of a third one of said fields, said set of general registers having at least one address input; an instruction register for storing an operation code and at least one general register address; means connected between said instruction register and said microprogram control unit for translating said operation code into an initial control memory address; and means for connecting said instruction register to said address input of said set of general registers to selectively specify at least one of said general registers in response to said at least one general register address.