1. A method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor, the sets respectively relating to different hierarchical portions of the circuit design, the method comprising: (A) executing a computer processor-based circuit design editor to graphically render on a display device at least a portion of a circuit design within a circuit editor user-interface, the circuit design including a plurality of interconnected circuit objects maintained in a computer memory operably coupled to the computer processor; (B) detecting any violation of at least one circuit design constraint of the hierarchical sets of constraints responsive to an editing interaction executed on the circuit design editor with a circuit object of the displayed portion of the circuit design within the circuit editor user-interface; (C) graphically indicating a violating object relating to a detected violation of at least one circuit design constraint; (D) temporarily arresting execution of circuit editing operations by the circuit design editor and graphically rendering on the display device a constraint interface concurrently with the graphic rendering of the circuit design portion in the circuit editor user-interface, the constraint interface defining a graphic window adaptively superimposed in contextually registered and variably positioned manner proximate the violating object in the circuit design portion as graphically rendered, the constraint interface identifying to a user: a type of the detected violation and a hierarchical source of the circuit design constraint violated; and, (E) responsive to a user input within the circuit editor user-interface, selectively: (1) modifying the editing interaction, (2) modifying the application of at least one circuit design constraint of the hierarchical set of constraints, or (3) modifying at least one circuit design constraint of the hierarchical set of constraints, to reconcile the detected violation.