1. A memory system that provides error detection and correction, comprising: an access mechanism configured to access a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits, which are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is stored in a different memory component, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors generated in a memory component; and an error-detection circuit configured to, examine a block of data retrieved by the access mechanism, and determine whether a memory component has generated an error based on the examination.