1. Method for generating a hardware description of a multiplier which is used in the integration of a digital signal processing circuit, comprising the steps of: acquiring input parametric values including a word length m of a multiplicand, a word length n of a multiplier, a word length w of an operation output, an operation cycle time C of said multiplier and an operation time T of full adders used in said multiplier; generating a hardware description of a first add circuit for adding partial products of said multiplicand and multiplier using at least said full adders and for outputting a result in a redundancy notation; determining a redundancy index r in accordance with a time remaining from said operation cycle time C following an operation time of said first add circuit, said redundancy index r being equal to (C/T-(n-2)); and generating a hardware description of a second add circuit for performing a carry-add operation for every r bits of said addition output by said first add circuit, and for outputting a result of said carry-add operation in a redundancy notation of r bits.