1. A circuit for use in controlling the cycle-by-cycle interleaving of instructions between a number of instruction threads in a simultaneous multithreading processor, each respective instruction thread being stored in a respective queue of the simultaneous multithreading processor and being made up of instructions that have previously been fetched by a fetcher unit of the processor for execution, the circuit including: (a) a first priority input for receiving a first priority signal indicating a first base input processing priority associated with a first instruction thread included in the number of instruction threads; (b) a feedback input for receiving a feedback signal associated with one of the instruction threads; (c) first adjustment logic including a first input coupled to the first priority input, a second input coupled to the feedback input, and an output, the first adjustment logic for adjusting the first base input processing priority to generate a first adjusted input processing priority signal in response to the feedback signal; (d) an interleave rule enforcement circuit for receiving the first adjusted input processing priority signal and at least one additional input processing priority signal and for generating a thread selection control signal based in part upon the first adjusted input processing priority signal, the thread selection control signal for controlling the interleaving of instructions from the number of instruction threads according to an interleave rule which specifies a relative frequency at which instructions are to be taken from each of the number of instruction threads; and (e) a selection multiplexer connected to receive the thread selection control signal and having a respective input for each one of the number of instruction threads, the selection multiplexer for applying the thread selection control signal on a given clock cycle of the processor to pass an instruction from a respective one of the instruction threads for further processing.