1. A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means and; output register means interconnected to receive said output data and ones of said plurality of control signals for buffering said output data between said arithmetic and logic unit means and said data sources external of the processor under control of ones of said plurality of control signals.