1. A cascadable plurality of configurable logic elements, each configurable logic element configurable as a shift register and comprising: a plurality of memory cells including at least a first memory cell and a second memory cell, each of the plurality of memory cells having a memory cell input terminal and a memory cell output terminal; shift means for programmably connecting the memory cell output terminal of the first memory cell to the input terminal of the second memory cell; and a cascade multiplexer having an output terminal connected to the input terminal of the first memory cell and a first input terminal connected to the output terminal of a last memory cell of another configurable logic element.