1. An apparatus comprising: a non-volatile storage to store semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer, the SIC including an embedded memory logic (EML) to initialize a memory via initialization of a memory controller, and a mapping of memory signals using an on-die termination (ODT) data structure accessible via the EML, the ODT data structure provided by an original equipment manufacturer (OEM) and corresponding to a parameterized rule set for a platform dependent memory configuration of the memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to pre-boot code of the OEM.