1. A method for optimizing processor register allocation, comprising: identifying a plurality of variables from an acyclic call graph having a plurality of functions; creating a plurality of virtual registers by assigning each of the plurality of variables to at least one virtual register; constructing an interference graph based on the plurality of virtual registers; coloring the interference graph with a plurality of physical registers; and if the interference graph is not colorable, spilling at least one virtual register from the interference graph.