1. A processing core for executing instructions, comprising: a first source register including a plurality of source fields; a second source register including a plurality of result field select values and a plurality of operation fields; a multiplexer coupled to at least one of the source fields; a destination register including a plurality of result fields; and an operand processor coupled to at least one of the result fields, wherein the operand processor and multiplexer operate upon at least one of the plurality of source fields.