1. A processor, comprising: a first pipeline stage; a second pipeline stage; a first selector configured to provide data to the first pipeline stage; a first input register configured to provide data to the first selector; a second input register configured to provide data to the first selector; a second selector configured to receive data output of the first pipeline stage; a first output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage; a second output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage; a first thread allocation counter configured to store a first processor time allocation that controls first periods of processor time for a first processor thread such that the first processor thread fully uses each of the first periods of processor time, wherein the first processor time allocation exclusively provides equal amounts of processor time to the first processor thread in each of the first periods, wherein the processor is configured to cause data associated with the first processor thread to pass through the first input register, the first pipeline stage, the first output register, and the second pipeline stage during the first periods of processor time; a second thread allocation counter configured to store a second processor time allocation that controls second periods of processor time for a second processor thread such that the second processor thread fully uses each of the second periods of processor time, wherein the second processor time allocation exclusively provides equal amounts of processor time to the second processor thread in each of the second periods, wherein the processor is configured to cause data associated with the second processor thread to pass through the second input register, the first pipeline stage, the second output register, and the second pipeline stage during the second periods of processor time; and circuitry configured to receive an input defining processor time to be allocated to the first processor thread, the second processor thread, or both, and to use the input to change the first, second, or both thread allocation counters such that subsequent periods of processor times for the first, second, or both processor threads are affected.