1. In a data processing system having at least one central processor, a main memory including a memory controller coupled to said processor for providing access thereto, the combination comprising: a plurality of peripheral requestors external to said processor and said main memory, each requestor providing a data request indicating a request for main memory data; an interface coupled between said requestors and said main memory controller; said interface comprising: first means for receiving main memory data requests from said requestors; a cache memory for storing main memory data; second means for determining whether main memory data requested by a requestor is stored in said cache memory and if so for reading out the requested data from said cache memory and sending it to the requestor; third means for requesting data from said main memory when data requested by a requestor is found not to be stored in said cache memory; said third means including a queue for storing a plurality of main memory requests whose requested data are not stored in said cache memory, a data request from a requestor being stored in said queue when the requested data is found not to be stored in said cache memory; and fourth means for receiving main memory data sent from said main memory as a result of data requested by a requestor having been found not to be stored in said cache; said fourth means associating received main memory data with the corresponding data request stored in said queue and in response thereto routing the received main memory data to the corresponding requestor without the requestor having to send another request, said received main memory data also being stored in said cache memory; said fourth means providing for receiving cache control commands and data from said main memory for updating the data stored in said cache memory; said fourth means including accept table means responsive to said cache control commands for providing consistency status of data stored in said cache memory with respect to data stored in said main memory so that a cache control command is targeted to the proper data in said cache memory, and wherein said access table means is accessed by said fourth means before performing operations affecting data in said cache memory.