1. A scalable neural array processor unit comprising: a N neuron structure, said N neuron structure having input means for providing weights and/or values to the structure, and wherein the structure is interconnected to perform within a period; means for multiplication of values and weights provided to the neuron structure; means for summation of multiplied products of values by weights; means for generation of new neuron values through a neuron activation function; means for communicatably connecting each weight storage unit containing a W.sub.ji weight to one containing a W.sub.ij weight; and means for reverse communication of the neuron values generated through said neuron activation function to neuron input means of said N neuron structure using the same path as used for the summation of multiplied products, and wherein the means for multiplication of weights and values includes a multiplier having multiplier input registers including a weight input register and a Y value input register and there is included means for sequentially performing (a) the multiplication of neuron values Y.sub.j by weights W.sub.ij ; (b) the summing of the weighted neuron values by enabling summation means for outputting a summation function in one direction when said summation means is enabled, which summation means is capable, when disabled, to act as a communication path in a reverse direction; (c) generating neuron values Y.sub.i ' (prime) with neuron activation function elements at the neuron activation function outputs; (d) reversing the enable-disable state of the summation means to communicate neuron values Y.sub.i 's back to be received in a specified multiplier Y value input register, with said specified multiplier Y value input register indicating that the Y value register has been updated; and (e) repeating the steps (a)-(d) until a host specified number of iterations has been completed.