1. A method of data processing in a cache coherent data processing system including at least first and second coherency domains, said method comprising: in a first cache memory within said first coherency domain of said data processing system, holding a memory block in a storage location associated with an address tag and a coherency state field, wherein said memory block is concurrently cacheable in both the first and second coherency domains; and setting said coherency state field to a state that indicates that said memory block is possibly shared with a second cache memory in said first coherency domain and cached only within said first coherency domain.