1. Data processing unit comprising: a register file, a memory, a plurality of execution units, a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from said memory, a decode stage for decoding an operational code from said instruction, an execution stage for activating one of said execution units, and a write-back stage for writing back from said execution unit, a coprocessor interface for coupling at least one coprocessor with said data processing unit having: read- and write-lines coupling said register file with said coprocessor for exchanging operands, at least one control line indicating that said coprocessor is busy, and a plurality of control lines from said decode stage for controlling said coprocessor which are operated upon detection of a coprocessor instruction, whereby said coprocessor is using said registers from said register file 19 during execution of a coprocessor instruction.