1. A sequential implementation shuffler comprising: a register for holding an original uncompressed instruction; a mix mask register; an x bit group register; a y bit group register; and a multiplexer, wherein the multiplexer passes one bit from the x bit group register to said register for holding if the current most significant bit of the mix mask register is equal to one, and one bit from the y bit group register otherwise, and at the end of the cycle, all registers are shifted left by one and the process is repeated.