1. In a digital computer system, arithmetic processor means for performing operations on at least signed integer operands comprising numeric values in the form of binary integer values, said arithmetic processor means comprising: ALU means having a first input for receiving said operands and an output for providing results of ALU operations, said ALU means including means connected to said first input and responsive to said received operands for performing arithmetic, logical, and shifting operations on said operands, means responsive to said received operands for determining the numbers of leading digits containing zero numeric values in each of said operands, and means responsive to said received operands for determining the signs of each of said operands; memory means connected to said ALU means output for storing the results of said ALU operations; selector means having a first input connected to an output of said memory means, and a second input connected to said ALU means output, and a read output connected to a second input of said ALU means for selecting inputs to said second input of said ALU means; and, means for controlling the operations of said arithmetic processor means; said ALU means, said memory means, and said selector means responsive to said control means for performing said operations which operations comprise: (1) receiving first and second operands into said ALU means, and (a) determining the numbers of the leading digits containing zero numeric values of said first and second operands, (b) determining the signs of said first and second operands, and (c) storing said numbers of the leading digits containing zero numeric values, said signs of said first and second operands, and said first and second operands in said memory means, (2) reading said numbers of the leading digits of said first and second operands containing zero numeric values and said first and second operands from said memory means to said ALU means, and (a) shifting said first and second operands to reduce the required number of steps of an intended one of said operations by discarding certain of said leading digits containing zero numeric values, (b) performing said intended one of said operations on the remaining digits of said first and second operands to obtain an unsigned result, and (c) storing said unsigned result in said memory means, (3) reading said signs of said first and second operands from said memory means to said ALU means and determining the sign of the result of said intended one of said operations, and (4) providing said sign of said result and said unsigned result as the signed result of said intended one of said operations on said first and second operands.