1. A method of generating a set of test patterns for one of simulating and testing a layout of an integrated circuit, the method which comprises the steps of: (a) generating a set of test patterns on a random basis; (b) applying the set of test patterns to an integrated circuit by using an automatic test equipment; (c) determining outputs of the integrated circuit; (d) processing the outputs in order to determine whether given test criteria are met; and (e) depending on a determination result in step (d), generating a new set of test patterns based on the set of test patterns generated in step (a) by using a genetic algorithm.