1. A multiprocessing system comprising: a multithreaded microprocessor having a plurality of logical processor contexts each of which appears to an N-way symmetric multiprocessor (SMP) operating system executing on the multithreaded microprocessor as a multithreaded virtual processing element (VPE), wherein the SMP operating system manages a simultaneously executing plurality of threads that can be created and destroyed without operating system intervention, wherein threads can be scheduled in response to external conditions with no interrupt latency, and wherein each thread context comprises a result register having two read ports and one write port for supporting execution of an instruction that performs exactly two reads, one from a first operand register containing a first operand and one from a second operand register containing a second operand and a single write of the second operand to one destination register in a register set during a single clock cycle.