1. A multi-processor data processing system, comprising: a processor array comprising a plurality of processors, the processor array having a north array port, an east array port, a south array port, and a west array port; first interface circuitry, coupled to the east array port; second interface circuitry, coupled to the south array port; an address bus, coupled to said first interface circuitry, to said second interface circuitry, to said north array port, and to said west array port; a data bus, coupled to said first interface circuitry and to said second interface circuitry, but not coupled to said north array port and said west array port; a control bus, coupled to said first interface circuitry, to said second interface circuitry, to said north array port, and to said west array port; and a bus interface controller, coupled to said address bus, to said data bus, and to said control bus, said bus interface controller initiating a first transfer of information in the multi-processor data processing system, wherein the multi-processor data processing system has a data transfer mode in which addresses are received by the processor array at the north and west array ports and not at the south and east array ports, and in which data corresponding to said addresses is received by the processor array at the south and east array ports and not at the north and west array ports, said addresses indicating a source or destination of the data within the processor array.