1. A behavioral synthesis apparatus comprising: a control data flow graph generator configured to generate a control data flow graph specifying an execution order of a plurality of calculations written in a behavior description, including an external loop processing that includes an internal loop processing, without expanding the internal loop processing; a scheduling module configured to carry out scheduling of the plurality of calculations, based on the control data flow graph; and an assigning module configured to divide a first pipeline processing, which implements the external loop processing, and a second pipeline processing, which implements the internal loop processing, into a plurality of stages, based on scheduling results, and to assign a plurality of pipeline registers that store data transferred among the plurality of stages to the external loop processing and the internal loop processing.