1. A neuro-computer comprising: a neuron array having a plurality of neurons each including at least the following elements (a) to (l), (a) a rewritable memory and a register file, (b) a memory write value holding means for holding data to be written in said rewritable memory, (c) a shifter and an ALU (Arithmetic Logic Unit), (d) a signal selecting means for selecting two values, in accordance with a control signal from a control logic unit, from at least one signal including inputs from said rewritable memory, said register, and an external circuit of said neuron, and outputs from said ALU and said shifter, (e) a select signal holding means for holding said selected two values, (f) a multiplier for multiplying the values held by said select signal holding means, (g) a multiplication result holding means for holding a multiplication result of said multiplier, (h) an operation result holding means for holding an output from said ALU or said shifter, (i) a shifter input selecting means and an ALU input selecting means for selecting inputs to said shifter and said ALU from outputs from said operation result holding means, said select signal holding means, and said multiplication result holding means, (j) a first operation result selecting means for selecting outputs from said shifter and said ALU, and determining an input to said operation result holding means, (k) a second operation result selecting means for selecting the outputs from said shifter and said ALU, and determining an output to said memory write value holding means, said register file, output selecting means for selecting an output to the external circuit of said neuron, and said signal selecting means for selecting said two values, and (l) said output selecting means for selecting an output to the external circuit of said neuron, from the outputs from said shifter, said ALU, said rewritable memory, and said register file; a control storage unit for storing a microinstruction for controlling said neuron array; a global memory unit for storing data necessary for information processing at said neuron array; and said control logic unit including a means for controlling said control storage unit, a means for controlling said global memory unit, a neuron array controlling means for controlling said neuron array in accordance with said microinstruction in said control storage unit, and an external bus interface means for accessing data via an external bus.