1. A memory system capable of concurrent system management comprising: a core memory; primary interface logic coupled to the core memory; a secondary interface controller; an arbitration unit coupled to the primary interface logic, the secondary interface controller, and the core memory; a scratchpad memory coupled to the arbitration unit; a primary error detection and correction circuit coupled between the primary interface logic and the core memory; and a secondary error detection and correction circuit coupled between the secondary interface controller and the core memory.