1. An apparatus, comprising: a first level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the first level cache memory being operable to store an address tag and data; a next lower level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the next lower level cache memory being operable to store an address tag, status flags, and data; and an additional memory associated with the next lower level cache memory and including a plurality of memory lines, wherein the number of memory lines corresponds with the number of cache lines contained in a given way set of the first level cache memory.