1. A data storage device comprising: a memory cell array including a plurality of memory cells, each memory cell having one or more data states; a row decoder applying program pulses and verification pulses to selected memory cells via a word line, wherein the row decoder performs on the selected memory cells a plurality of program loops based on an incremental step pulse program (ISPP) algorithm; a memory cell counting circuit coupled to the memory cell array via one or more bit lines, wherein the memory cell counting circuit determines data states of the selected memory cells in response to the verification pulses, counts a number of programmed memory cells or a number of unprogrammed memory cells, and generates a count result; a program loop turn detector that receives the count result and detects a turn values of a program loop based on the count result; a comparing circuit that generates a comparison result by receiving the count result and comparing the count result to a set value; and a control logic that controls the row decoder, the memory cell counting circuit, and the comparing circuit, wherein the program loop turn detector detects a first turn value of a first program loop, wherein, in the first program loop, a first number or a first ratio of first unprogrammed memory cells is less than or equal to a first set value, wherein the control logic calculates a second turn value of a second program loop based on the first turn value, and then executes subsequent program loops on the unprogrammed memory cells up to the second program loop, wherein, in the second program loop, a second number or a second ratio of second unprogrammed memory cells is expected to be less than or equal to a second set value, and the second set value is less than the first set value, wherein the memory cell counting circuit detects a third number or a third ratio of third unprogrammed memory cells in the second program loop, wherein the comparing circuit compares the third number or the third ratio of the third unprogrammed memory cells to the second set value, wherein the first ratio of the first unprogrammed memory cells, the second ratio of the second unprogrammed memory cells, and the third ratio of the third unprogrammed memory cells are defined on a basis of a total number of memory cells to be programmed in a selected page, or on a basis of a total number of memory cells in the selected page, wherein the control logic determines a program pass when the third number or the third ratio of the third unprogrammed memory cells is less than or equal to the second set value, or a program fail when the third number or the third ratio of the third unprogrammed memory cells is greater than the second set value.