1. A content addressable memory (CAM) device comprising: a plurality of CAM blocks, each CAM block having an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers, each priority number indicating a priority of a respective one of the data words relative to others of the data words; and a block control circuit having an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks, each select signal to selectively disable a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.