1. An apparatus for recovery of a processor core in a chip of a symmetric multiprocessing system, the chip having a processor core and a host firmware for supervising resource allocation and error recovery, comprising: a means for providing a clock signal to recovery circuits; a means for blocking checkpointing of the processor core; a means for quiescing a cache functional unit; a means for establishing a coherent checkpoint in response to quiescing the cache functional unit; a means for logically removing the processor core from the symmetric multiprocessing system in response to quiescing the cache functional unit and establishing a coherent checkpoint; a means for resetting the processor core; a means for restoring a nearest checkpoint to the processor core after resetting the processor core; a means for indicating an interrupt in response to restoring a nearest checkpoint; a means for executing a preprogrammed number of instruction groups in a reduced execution mode; and a means for executing at least one instruction group in a normal execution mode.