1. In a system for controlling repetitive operations of a machine dependent on operating parameters such as the operation of electrical ignition in an internal combustion engine, which system comprises a microprocessor, a clock pulse generator, a read-only memory (ROM, PROM), a random access memory (RAM), a data bus and an address bus, both interconnecting said microprocessor with said read-only memory and said random access memory, and read and write enable connections for enabling the reading of said memories and writing into said random access memory the data on said data bus at the memory address specified on the said address bus, an input-output unit for said system connected to said address bus and read and write connections including a decoding circuit, connected to said data bus, and connected to said microprocessor also through "clear" and "interrupt" connections for receiving a clearing command from said microprocessor and for providing an interrupt to said microprocessor, said input-output unit comprising: a counter (61) for counting shaft rotation rate dependent signals arranged for operation in successive counting invervals, the length of which intervals are determined by setting of said counter through said data bus (14), and the position in time of which intervals is controlled by at least one timing reference mark of said machine, said counter having a multibit count state output and having input connections for having a count value set therein for initiation of counting and termination of and for counting said signals; a comparator (64) and a buffer store (68) therefor, said comparator having one multibit comparison input connected to the count-state output of said counter (61) and its other multibit comparison input connected to said buffer store (68), and having an output for indicating at least one comparison condition of signals at said inputs thereof, said buffer being arranged to have its content written through said data bus; a selectable multi-channel final stage array (75, 76, 49, 50) and providing a plurality of output command channels, and select logic circuits (72, 73) for sequential preselection of said channels of said final stage array, said select logic circuits being connected to said data bus for their control and to said final stage array for channel preselection in response to a signal of a control signal sequence (F) and including circuits for transferring timed signals (E) obtained in response to the output of said comparator to the channels preselected in sequence, said decoding circuit (100) being constituted so as to provide stepwise control of the various circuit components connected with said data bus (14) as selected over said address bus (15).