1. A method for performing formal verification of an integrated circuit (IC) design, the method comprising: identifying a set of remodeling-eligible latches in a synthesized layout of sequential logic for the IC design, each of the set of remodeling-eligible latches exhibiting flip flop-like output behavior; replacing each of the set of remodeling-eligible latches in the synthesized layout with a flip flop to form a remodeled layout; and performing clock modeling on the remodeled layout.