1. A computer-implemented method for synthesizing a gated clock tree with reduced clock skew comprising the following computer-implemented stages: providing a clock source operable to generate a clock signal; providing a plurality of edge-triggered state elements; providing a gated clock tree between the clock source and the plurality of edge-triggered state elements, wherein the gated clock tree comprises a level, wherein the level includes a plurality of logic gates; and matching the plurality of logic gates in the level such that each logic gate in the level has a common logic type.