1. A processor-implemented method for forming an optimized covering array used for generating one or more optimized test designs for at least one application under test (AUT), comprising: obtaining, via one or more hardware processors, one or more parameters and one or more corresponding values pertaining to at least one application under test (AUT); generating, by a first array generating module via the one or more hardware processors, a first set of arrays based on an analysis being performed on said one or more parameters and said one or more corresponding values pertaining to said at least one AUT, wherein two or more arrays in said first set of arrays comprises elements that are unique from each other; identifying, by an array grading module via the one or more hardware processors, two or more arrays in said first set of arrays to obtain a second set of arrays, wherein two or more arrays in said second set of arrays comprises pairwise interacting elements that are unique from each other are identified; interchanging, by an elements interchanging module via the one or more hardware processors, said identified pairwise interacting elements that are unique from each other across said two or more arrays in said second set of arrays to obtain a third set of arrays; combining, by a covering array generating module via the one or more hardware processors, two or more arrays in said third set of arrays to form an optimized covering array; and generating, by a test design generating module via the one or more hardware processors, one or more optimized test designs pertaining to said at least one AUT based on said optimized covering array.