1. An integrated circuit ternary content addressable memory (TCAM) system, comprising: an array of XY TCAM cells; respective translation circuits connected to respective pairs of the XY TCAM cells; and a memory controller structured to provide control signals to the respective translation circuits, wherein the memory controller and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and single cycle search operations, wherein each of the respective translation circuits is configured to: receive an external data in signal and an external bit enable signal from the memory controller; provide a first data in signal and a first bit enable signal to a first cell of one of the respective pairs of the XY TCAM cells; and provide a second data in signal and a second bit enable signal to a second cell of the one of the respective pairs of the XY TCAM cells.