1. An apparatus, comprising: a plurality of cores, wherein a first core of the plurality of cores is configured to process a plurality of instructions; and circuitry coupled to the first core, wherein the circuitry is configured to: detect that the first core has stopped committing a subset of the plurality of instructions; and send an indication to a second core of the plurality of cores that the first core has stopped committing the subset of the plurality of instructions; wherein the second core is configured to: disable the first core from further processing instructions of the subset of the plurality of instructions responsive to receiving the indication; and copy data from at least one memory location in the first core to at least one memory location in a third core of the plurality of cores responsive to disabling the first core; and wherein the third core is configured to resume processing the subset of the plurality of instructions dependent upon the data.