1. In a transaction memory system, a thread-level speculation mechanism for supporting inter-thread synchronization having content-addressable memory, an address register and a comparator, and also having a control logic circuit for supporting non-transaction memory access instructions, the thread-level speculation mechanism comprising: means for recording a memory address and an attribute operand of a non-transaction memory access instruction; means for detecting an access event to the memory address; and means for generating a priority up event in response to detection of the access event when the attribute operand of the non-transaction memory access instruction indicates a thread-execution priority rise.