1. A method performed for determining placement of circuitry during integrated circuit design, the method comprising: accessing a net list identifying circuitry connections; assigning a plurality of individual net weights to nets in timing paths within said net list, said individual net weights being valid irrespective of physical design parameters; determining a composite net weight for nets in said timing paths, said composite net weight being in response to said plurality of individual net weights; concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps; and determining placement of said circuitry in response to said composite net weight