1. A computer system for performing memory table cache reloads in a reduced number of cycles, comprising: a bus; main memory coupled to said bus, wherein said main memory is configured to store memory tables, each of said memory tables comprising a plurality of memory table entries, wherein each of said plurality of memory table entries includes information regarding memory blocks in said main memory; a processor coupled to said bus, said processor including a memory table cache configured to store a subset of said plurality of memory table entries, wherein said processor is configured to use said information in said plurality of memory table entries in said plurality of memory tables in the main memory to access data in said main memory, wherein said processor is configured to generate a memory table cache reload cycle to said main memory that causes one of said plurality of memory table entires to be read from said main memory into said memory table cache; and a memory controller coupled between said bus and said main memory, said memory controller being responsive to said memory table cache reload cycle to read one of said plurality of memory table entries from one of said memory tables, provide said one of said plurality of memory table entries to said processor, and set a status bit in said one of said memory table entries in said main memory, wherein said memory controller determines if said status bit in said one of said plurality of memory table entries is already set and, if said bit is set, does not set said status bit in said memory table entry.