1. A method of designing a hardware threaded circuit architecture, comprising: determining a total area available for processing elements; determining a set of task arrival times for tasks to be processed by the processing elements; determining a number of possible implementations for the processing elements within the area available, each of the possible implementations having a corresponding number of processing elements; interconnecting first and second ones of the processing elements; determining overall system wait times for the possible implementations; and selecting a first one of the possible implementations based upon the overall system wait times.