1. A computer-implemented method for verifying timing of a circuit including an interconnect part with RLC inputs and RLC outputs, the method comprising: expressing the interconnect part in terms of an admittance matrix for the RLC inputs and a voltage transfer from the RLC inputs to the RLC outputs; pre-characterizing the admittance matrix and the voltage transfer; and integrating the interconnect part with a driver part in time domain with both the admittance matrix and the voltage transfer in frequency domain, wherein one or more of the expressing, pre-characterizing and integrating steps are implemented by a computer.