1. A multi-core processor system comprising: a plurality of mutually communicatively inter-coupled processor cores, at least one processor core of the plurality of processor cores being configured to: receive an instruction directing the at least one processor core to read a value associated with a memory address; and in response to receiving the instruction and before execution of the instruction, cause ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.