1. A processing unit, comprising: a processor core including: an instruction sequencing circuit that orders instructions for execution; and an execution circuit that generates a store operation by executing a store instruction in an instruction sequence; a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and a marking circuit within at least one of set including the processor core and the cache memory, wherein the marking circuit selectively marks the store operation as a high priority store operation, wherein the marking circuit marks the store operation as a high priority store operation in response to detecting, in the instruction sequence, a precursor instruction that precedes the store instruction in program order and that includes an opcode field indicating the store operation should be accorded high priority, and wherein the marking circuit refrains from marking the store operation as a high priority store operation in response to not detecting, in the instruction sequence, a precursor instruction that precedes the store instruction in program order and that includes an opcode field indicating the store operation should be accorded high priority; wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue.