1. A microprocessor unit including an internal data bus N bits wide, N being an interger, coupled to a data output circuit comprising: parallel internal address bus means including first address bus means N bits wide coupled to first register means for transferring data representative of low order address bits, and second address bus means independent of said first address bus means N bits wide coupled to second register means for transferring data representative of high order address bus bits, said parallel internal bus means being coupled to data output circuit means; said first register means including first program register means coupled to said first address bus means for storing low order address bits of a current instruction and transferring said low order address bits to said first address bus means if said current instruction is of a first type or to said data bus if said current instruction is of a second type; said second register means including second program register means coupled between said second address bus means and said data bus for storing high order address bits of said current instruction and transferring said high order address bits to said second address bus if said current instruction is of said first type or to said data bus if said current instruction is of said second type; counter means coupled to said first and second register means for updating said low and high order address bits in said first and second program register means by incrementing or decrementing, under program control, an address stored in said first and second register means wherein said counter means includes a first counter coupled between said first address bus means and said data bus and also coupled to said first program register means for updating contents of said program register means; said counter means including a second counter coupled to said address bus means and said second program register means for updating contents of said second program register means independently of said second address means; said microprocessor unit also including arithmetic logic unit means coupled to said low order address bus and said data bus and control means coupled to said arithmetic logic unit means, said first and second register means, and said counter means for controlling transfers of data thereat.