1. A floating point unit comprising a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand, the combined adder-shifter including: (a) an adder portion that operates to generate a plurality of sum bits for an exponent difference between the two floating point operands, favoring generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits, the adder portion including a plurality of computational cells, serially coupled to each other, capable of implementing a ripple carry scheme for lower order ones of bits employed to determine said exponent difference; and (b) a shifter portion coupled to the adder portion that operates to shift said mantissa portion of the at least one floating point operand in accordance with the sum bits.