1. A memory controller for a processing device containing a plurality of computing resources, comprising: a first interface to couple the memory controller to a router, the first interface being configured to transmit and receive packets each comprising a header, the header containing a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol; a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory associated with the memory controller; and a controller core coupled to the first interface, the controller core being configured to: decode a packet received at the first interface; and perform an operation specified in the received packet.