1. A device adapted to be included in a host having a memory controller for accessing data in a high bandwidth memory (HBM) via a read data path and a write data path, the device comprising: a module adapted to perform training of one or both of the read data path and the write data path independently from the memory controller, wherein the host further includes a memory PHY and a DDR PHY interface (DFI) between the memory controller and the memory PHY, and wherein the memory PHY is configured to receive DFI commands for reading and writing data from and to the HBM from the memory controller via the DFI, and wherein, responsive to a setting by the memory controller, the module is adapted to independently issue DFI commands to the memory PHY during the training of one or both of the read data path and the write data path.