1. A microprocessor system for executing a program stream, said microprocessor system comprising: (a) an instruction fetch unit for fetching instructions from an instruction store and for providing a predetermined plurality of said instructions to an instruction buffer; (b) an execution unit, coupled to said instruction fetch unit, for executing said plurality of said instructions from said instruction buffer in an out-of-order fashion, said execution unit including a load store unit adapted to make load requests to a memory system out-of-order and store requests in-order, said load store unit having, (i) an address path adapted to manage a plurality of addresses associated with said plurality of said instructions being executed, (ii) address collision means for detecting and signaling whether address collisions and write pendings exist between each of said plurality of said instructions, wherein said load store unit performs said load requests if no address collisions and no write pendings are detected, (iii) a data path for transferring load and/or store data to and from said memory system and said execution unit, said data path configured to align data returned from said memory system to thereby permit data falling on a word boundary to be returned from said memory system to said execution unit in correct alignment.