1. A data processing device, comprising: a processing circuit operable at selectable ones of a plurality of performance levels, each performance level comprising a combination of power supply voltage and clock frequency, and configured to provide a supply of workload data indicating a workload of the processing circuit over a sampling period; a shift register circuit, operative to successively shift and store a predetermined number (N) of samples of workload data from the processing circuit over N corresponding successive sampling periods to generate a current workload data vector; a pattern memory circuit, operative to store control information to control a performance level of the processing circuit in combination with a plurality of reference workload data vectors, each reference workload data vector containing workload data for N successive sampling periods; a pattern matching circuit configured to compare a current workload data vector to the plurality of reference workload data vectors and to detect a match; and a performance level control circuit, configured to select a performance level of the processing circuit, based on the control information that is stored in combination with the matching workload data vector for at least the next sampling period.