1. A method of operating a processor, the processor being capable of operating in different states, at least two of the states supporting different instruction sets, the method comprising: retrieving a block of instructions from memory while the processor is operating in one of the states; pre-decoding the instructions in accordance with said one of the states; loading the pre-decoded instructions into cache; and determining whether the current state of the processor is the same as said one of the states used to pre-decode the instructions when one of the pre-decoded instructions in the cache is needed by the processor.