1. A method, performed by at least one processor, comprising: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on locations of the transistors in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data and a time-varying on-off status profile of the transistors; verifying whether the post-layout simulation meets a design specification; and manufacturing the chip using the netlist in response to the post-layout simulation being verified as meeting the design specification.