1. A processing system comprising: a plurality of processor cores; a plurality of private caches, each private cache associated with a corresponding processor core of the plurality of processor cores and comprising a corresponding set of cachelines; and a shared cache shared by the plurality of processor cores, the shared cache comprising: a second set of cachelines; and a shadow tag memory comprising a plurality of entries, each entry storing state and address information for a corresponding cacheline of the set of cachelines of one of the private caches.