1. An integrated circuit (IC) comprising: an input interface for receiving an external command and optional external data; a main memory (MM) coupled to the input interface, the MM comprising: a plurality of memory cells configured to store data; a memory controller (MC) configured to execute an access command to one or more of the plurality of memory cells; a coprocessor (CP) coupled to the input interface and the MM, the coprocessor comprising: a processing engine (PE) coupled to the MM, wherein the processing engine is configured to execute a command for a subroutine call on data without requiring an interrupt; an output interface for transmitting data, the output interface coupled to the MM and the PE; a local data memory coupled to the PE; a plurality of registers coupled to the PE; and wherein: the local data memory and the plurality of registers are partitioned into a plurality of multi-threaded processing domains; and data stored in the local data memory and in the plurality of registers is located in a partition of the local data memory and a partition of the plurality of registers, respectively, that matches a multi-threaded processing domain of the data.