1. A multi-core computer processor comprising: a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture; a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores; and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, and wherein each of the plurality of processor cores being configured to be able to address a main memory visible in the global memory address space via its respective cache memory.