1. A processing network comprising: a plurality of processing elements on a programmable microchip, wherein each of the processing elements have one or more instruction tables each including one or more blocks; and a compiler stored on a non-transitory computer-readable memory and comprising an instruction table mapper that maps one or more instructions derived from assignments of a source code into one or more lines of the blocks of the instruction tables, wherein the mapping of the instructions comprises a combining process including iteratively grouping a plurality of the instructions into a group based on one or more grouping parameters, wherein in each iteration of the combining process a size value equals the number of the groups in that iteration plus the number of the instructions that have not yet been grouped in that iteration, and further wherein in at least one iteration of the combining process the size value is less than the size value of the previous iteration of the combining process.