1. A processor, comprising: at least two cores, each of the at least two cores having a first level cache memory, each of the at least two cores being multi-threaded; a buffer switch core in communication with a plurality of cache bank memories, the buffer switch core configured to communicate with multiple input/output (I/O) interfaces; an input/output bridge in communication with a crossbar and external input/output devices, the input/output bridge enabling control register transfers with external input/output devices; and the plurality of cache bank memories in communication with the at least two cores, each of the plurality of cache bank memories in communication with a main memory interface, wherein the processor includes an interconnect structure that includes the crossbar in communication with each of the plurality of cache bank memories and the at least two cores and wherein a pathway through the input output bridge bypasses the plurality of cache bank memories.