1. A memory array, comprising: a plurality of memory banks; a plurality of respective address decoders that produce respective address signals for addressing the memory banks; and a plurality of multiplexers each of which has an output that provides a corresponding one of the address signals to a corresponding one of the address decoders, wherein each of the multiplexers has a plurality of inputs, each input having a respective address input and a respective control input, and wherein when a control signal is asserted on the control input of a given one of the inputs of a given multiplexer, address information on the address input of that given one of the inputs is routed to the output of the given multiplexer.