1. In a computer processor, said computer processor coupled to a memory, a branch prediction apparatus for predicting a stream of processor instructions to fetch, said branch prediction apparatus comprising the elements of: a branch target buffer comprising N branch prediction entries, each of said N branch prediction entries having an associated branch instruction in said stream of processor instructions, each of said N branch prediction entries comprising an actual branch history field, said actual branch history field storing a final resolved branch outcome of a last K occurrences of said associated branch instruction; a speculation bit, said branch prediction apparatus setting said speculation bit when said branch prediction apparatus makes a branch prediction for said associated branch instruction; a speculative branch history field, said branch speculative history field storing K bits of speculative branch history comprising branch predictions of recent occurrences of said associated branch instruction; a target address field, said target address field comprising a target address identifying where said computer processor should fetch from when said associated branch instruction is predicted taken; and a dynamic branch prediction circuit, said dynamic branch prediction circuit using said actual branch history to make a branch prediction when said speculation bit is clear, else said dynamic branch prediction circuit using said speculative branch history to make a branch prediction when said speculation bit is set.