1. An integrated design verification process, comprising: performing under approximation verification (UAV) processing using a design model of the integrated circuit; extracting and storing coverage data generated by the UAV process; responsive to the UAV processing failing to resolve a verification problem, performing over approximation verification (OAV) processing on the design model; responsive to the UAV processing failing to resolve the verification problem, evaluating a previously defined lighthouse, wherein the lighthouse is indicative of a defined state being achieved during the verification processing; and responsive to a lighthouse being disproven, storing at least one state disproving the lighthouse to use as a seed state for subsequent UAV processing and, responsive to a lighthouse being proven, simplifying the design model before subsequent verification processing by eliminating at least one latch from the design model.