1. A list vector control apparatus incorporated into a vector processor system comprising, at least a main memory segmented into N (where N is a positive integer equal to or larger than 2) number of banks to be accessed under an N-way interleave method, a plurality of vector registers for loading, from the main memory, successive vector elements therein, a plurality of address registers each connected to one of said vector registers, for accessing said vector elements located therein sequentially using address increment means, and a vector arithmetic unit receiving list vector data sequentially supplied from said vector registers to produce resultant data therefrom, said apparatus comprising: one of said vector registers acting as a list vector register and storing therein a set of list vector elements supplied from said main memory; at least one other of said vector registers acting as a list data vector register and storing therein, from said main memory, a set of vector data elements each corresponding to individual ones of said list vector elements, where said list vector elements indicate the order of the vector data elements; and at least one list vector transfer line, connected between the address register of said list data vector register and said list vector register, the list vector elements being sequentially transferred to and momentarily stored in the address register of said list data vector register, via said list vector transfer line, and used for accessing the vector data elements in said list data vector register specified thereby, to produce the list vector data.