1. A memory system, comprising: a memory bit cell comprising: a storage circuit configured to store data; and one or more P-type Field-effect Transistor (PFET) access transistors configured to pass the stored data from the storage circuit to a respective bit line among one or more bit lines in response to a read operation; and a sense amplifier comprising: a latch circuit, comprising: one or more storage nodes; one or more pull-up circuits each coupled to a respective storage node among the one or more storage nodes, wherein each pull-up circuit of the one or more pull-up circuits comprises at least one PFET transistor; and one or more pull-down circuits each coupled to a respective pull-up circuit among the one or more pull-up circuits and the respective storage node coupled to the respective pull-up circuit, wherein each pull-down circuit of the one or more pull-down circuits comprises at least one N-type FET (NFET) transistor; one or more PFET sense transistors coupled to the respective bit line among the one or more bit lines and the respective pull-up circuit among the one or more pull-up circuits in the latch circuit, the one or more PFET sense transistors each configured to sense the data on the respective bit line among the one or more bit lines in response to the read operation and control coupling of a voltage supply of a supply voltage to the respective pull-up circuit based on a state of the data on the respective bit line; and a second pull-up circuit comprising at least one PFET transistor and configured to electrically couple the voltage supply to the one or more PFET sense transistors in response to a sense amplifier enable signal indicating a sense state.