1. A test apparatus for at-speed testing a multi-clock-domain digital integrated circuit including at least a scan chain and combinational logic in each clock domain, configured to use external automatic test equipment and an automatic test pattern generator tool of automatic-test-pattern generation in an inter-domain mode for detecting time-related faults, the apparatus comprising: internal clock generators of different clocks at the frequency of operation of the different clock domains; a dedicated clock sourcing logic circuit for each clock domain, each clock sourcing logic circuit configured to deliver test clock pulses originating from the external automatic test equipment according to the pattern generated by the automatic test pattern generator tool, and from internal clock generators, to the scan chains of the respective clock domain; a controller circuit interfaced with each clock sourcing logic circuit and configured to synchronize the different clock sourcing logic circuits with said test clock pulses from said external automatic test equipment.