1. A field programmable gate array device comprising: (a) a first plurality P1 of repeated logic units wherein: (a.1) each said logic unit is user-configurable to receive and process at least a second plurality P2 of input logic bits and to responsively produce result data having at least a third plurality P3 of output logic bits, (a.2) said logic units are distributed among a plurality of horizontal rows, with each row of the plurality of rows having a fourth plurality P4 of said logic units; (a.3) said logic units are further distributed among a plurality of vertical columns, with each column of the plurality of columns having a fifth plurality P5 of said logic units; (a.4) said logic units include variable grain logic units (VG logic units) which are granulatable for implementing relatively coarse-grained functions of relatively high complexity from function spawning resources and for implementing with same function spawning resources, larger numbers of relatively finer-grained functions of relatively lower complexity but having independent input terms; (b) a sixth plurality P6 of horizontal interconnect channels (HIC's) correspondingly distributed adjacent to said horizontal rows of logic units, wherein: (b.1) each said horizontal interconnect channel (HIC) includes at least P3 interconnect lines, and (b.2) each said horizontal row of P4 logic units includes VG logic units that are each configurably couplable to a corresponding one of the P6 HIC's at least for receiving input logic bits from the corresponding HIC or at least for outputting result data to the corresponding HIC; and (c) switchbox areas distributed along the corresponding HIC of each said row of P4 logic units, wherein said switchbox areas include: (c.1) braided switchboxes for twisting physical distribution of signals among at least some of said interconnect lines of the corresponding HIC so that rotated coupling options are provided by way of said configurable couplings between the P4 logic units and the corresponding HIC.