1. A computer system, comprising: a register file configured to store a target result operand and to retrieve a source operand both addressed by register addresses; an execution unit for executing instructions, the execution unit configured to receive the source operand from the register file and write the target result operand back into the register file; a register address calculation logic configured to receive a current instruction address portion associated with a current instruction, a source register address portion and a target register address portion, and to concatenate the current instruction address portion onto the source register address portion and the target register address portion to yield a full source register address corresponding to the source operand and a full target register address corresponding to the target operand, and to provide the full source register address and the full target register address to the register file; and an instruction decode logic configured to decode the current instruction and provide the current instruction address portion and the source and target register address portions to the register address calculation logic.