1. A logic array comprising: an AND plane coupled to receive a plurality of inputs and provide a plurality of minterms, each minterm representing a logical AND combination of the inputs; a first OR plane coupled to receive the minterms and provide a plurality of intermediate outputs, each intermediate output representing a logical OR combination of the minterms; and a second OR plane coupled to receive the intermediate outputs from the first OR plane and reduce loading by removing identical redundancies or removing redundancies due to an output pattern for one minterm being a superset of output patterns of other minterms, when generating logical OR'ed logic array outputs of the minterms from the logic array.