1. A method for maintaining multi-level cache coherency in a processor with non-inclusive caches, comprising the steps of: (a) snooping a command on a system bus; (b) supplying said snooped command to each level of cache; (c) generating a response to said snooped command at each level of cache; and (d) generating a combined response to said snooped command from said responses output in said step (c); and wherein said step (b) delays supplying said snooped command to at least lower level caches such that lower level caches have a greater supply delay than higher level caches.