1. A semiconductor integrated circuit having a CPU for executing code comprising instructions from memory including an operating system (OS), the CPU being arranged to execute the instructions as a pipeline and to use a table to translate virtual addresses of the instructions to physical addresses in the memory, the CPU being further arranged to expose execution parameters including at least an address of an instruction, a mode of operation of the CPU and whether an instruction was executed to completion, the integrated circuit further comprising an instruction monitor arranged to receive the execution parameters and to determine an authenticity of code executed from the memory to selectively impair function of the integrated circuit if the code is not authentic.