1. A reconfigurable register file capable of storing and retrieving double and single width data types on a cycle by cycle basis comprising: two register files of equivalent capacity and equivalent number of store (write) and retrieve (read) ports; single and dual width data type instructions; a plurality of multiplexers to select one of the two register files or both for a single width or double width read operation; and combinatorial logic to select one of the two register files or both for a single width or double width write operation.