1. A method for manufacturing an embedded flash memory device, said method comprising: forming memory and logic shallow trench isolation (STI) regions respectively extending into memory and logic regions of a semiconductor substrate, wherein the memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the semiconductor substrate; forming a capping layer overlying the logic region of the semiconductor substrate; performing a first etch into the pad layer, through regions of the pad layer overlying the memory region of the semiconductor substrate, to expose memory gaps between the memory STI regions; forming a floating gate layer filling the memory gaps and overlying the capping layer; performing a second, dry etch into the floating gate layer to etch the floating gate layer back to below or about even with upper surfaces of the capping layer and the memory STI regions; performing a third etch into the memory STI regions to recess the memory STI regions relative to the floating gate layer; and performing a fourth etch into the floating gate layer to form an array of floating gates from the floating gate layer.