1. A microprocessor having architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising: a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions; wherein if the architectural instruction specifies that the architectural condition flags are to be updated, the first microinstruction indicates to write the architectural condition flags and the second microinstruction is of a first type; and wherein if the architectural instruction specifies that the architectural condition flags are not to be updated, the first microinstruction indicates not to write the architectural condition flags and the second microinstruction is of a second type; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the operation on the source operands to generate the result and a non-architectural indicator and a new value of the architectural condition flags based on the result, wherein the execution pipeline generates a true value of the non-architectural indicator if the first microinstruction indicates to write the architectural condition flags and architectural condition flags read by the execution pipeline satisfy the condition and otherwise generates a false value of the non-architectural indicator; wherein in response to the second microinstruction, the execution pipeline: determines whether the condition is met based on the non-architectural indicator if the second microinstruction is of the first type and based on the new value of the architectural condition flags if the second microinstruction is of a second type; writes the destination register with the result generated by the first microinstruction, if the condition is met; and writes the destination register with the current value of the destination register, if the condition is not met.