1. A method comprising: modeling a memory array using a first model, wherein modeling the memory array comprises modeling each memory cell of the memory array to include a first uni-directional transistor that controls write operations into the memory cell and a second uni-directional transistor that controls read operations out of the memory cell; storing the first model of the memory array in memory of a computer system; and executing software on the computer system to perform a static timing analysis of the first model of the memory array.