1. A 3D stacked non-volatile memory device, comprising: a substrate; a stacked non-volatile memory cell array carried by the substrate, the stacked non-volatile memory cell array comprising a memory string, the memory string comprising a plurality of memory cells between a first select transistor (SGD/SGS) at a first end of the memory string and a second select transistor (SGS/SGD) at a second end of the memory string, the first end of the memory string connected to a first control line (BL/SL), and the second end of the memory string connected to a second control line (SL/BL); and a control circuit in communication with the stacked non-volatile memory cell array, the first control line and the second control line, the control circuit, to perform each erase iteration of a plurality of erase iterations of an erase operation for one or more memory cells of the memory string: performs: (a) a preparation phase in which a voltage (Vbl or Vsl) of first control line and a voltage of the first select transistor (Vsgs, Vsgd) are driven higher (Vsg 0 , Vsg 1 ,. .. ), such that the voltage (Vbl or Vsl) of the first control line does not exceed the voltage of the first select transistor (Vsgs, Vsgd) by a sufficient margin to charge up a channel of the memory string by gate-induced drain leakage at the first select transistor, (b) a charge up phase in which a voltage (Vwl-selected) of a control gate of each of the one or more memory cells floats, and the voltage of the first control line is driven higher to a level (Verase 0 , Verase 1 ,. .. ) which exceeds the voltage (Vsg 0 , Vsg 1 ,. .. ) of the first select transistor (Vsgs, Vsgd) by the sufficient margin to charge up the channel of the memory string by gate-induced drain leakage at the at least the first select transistor, and (c) an erase phase in which the voltage of the control gate of each of the one or more memory cells is driven lower.