1. A method of performing a multi-register gather instruction in a computer processor, comprising: fetching the multi-register gather instruction, wherein the multi-register gather instruction includes a destination operand that specifies a destination vector register and a source operand that identifies content that indicates: a plurality of first vector registers, a first set of one or more indexes of each of the plurality of first vector registers, wherein each of the first set of indexes identifies a source data element in its corresponding one of the first vector registers, and a second set of one or more indexes of the destination vector register for each identified source data element; decoding the fetched multi-register gather instruction; and executing the decoded multi-register gather instruction which causes, for each of the first set of indicated indexes of each of the plurality of first vector registers, the source data element that corresponds to that indicated index of that one of the first vector registers to be stored in a set of one or more destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.