1. A circuit arrangement for a data processing system for executing a plurality of tasks using a central processing unit with a processing capacity, comprising: a circuit configured to allocate the processing unit to specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing, wherein: the circuit includes a prioritization order control unit configured to determine the order in which the tasks are to be executed; in response to each selection of a task for processing, the order of the tasks is redetermined and the selection is controlled so that, for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit; and at least one of: the order of the tasks to be executed is determined by a list including list positions of ascending priority, and a task currently selected for processing is to be put into the list position with the lowest priority; the circuit arrangement is configured to assign each of the tasks a respective channel with its own registers, to select the specific registers according to the allocation of the specific task to the processing unit, and to connect the selected registers to the processing unit; and the circuit arrangement is configured to allocate the processing unit, in each instance, to each of the tasks for which there is a current processing request, at the latest, after a maximum waiting time, and then, for a constant time period that is the same for all of the active tasks.