1. An apparatus comprising: at least one processor; and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to at least perform: assigning decoding of a respective video frame to a corresponding thread for each core processor of a multi-core processor, each respective video frame being divided into macroblock rows; resolving dependencies for the each respective video frame at a macroblock row level; and providing synchronization for video decoding of each corresponding thread at the macroblock row level.