1. A memory device comprising: a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack, the system element including: a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, wherein the test interface includes: a test data memory to store the test data for a write test event or a read test event; and a state machine to obtain at least a part of the test data for a write test event or a read test event from the test data memory, the state machine to provide the at least a part of the test data for a write test event or a read test event to a formatter of the test interface, the formatter to format the test data for the DRAM elements to generate formatted test data, and a memory controller, the memory controller to receive the formatted test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.