1. A method of utilizing a plurality of Arithmetic Logic Units (ALUs) of an array processor comprising: determining that a first quantity of the ALUs are scheduled to execute a function during a given processing cycle, with each ALU being scheduled to use a respective one of a plurality of selected input vectors as an input; determining that a second quantity of the ALUs are not scheduled for use during the given processing cycle; determining a plurality of predicted future input vectors that differ from the plurality of selected input vectors; scheduling the second quantity of ALUs to execute the function during the given processing cycle using respective ones of the plurality of predicted future input vectors as inputs; and after completion of the processing cycle, caching function outputs received from the first and second quantity of ALUs.