1. A method for decomposition of a circuit for implementation on a programmable chip, the method comprising: identifying a supported programmable chip lookup table (LUT) size, a cyclic redundancy check (CRC) width, and a polynomial associated with the CRC width; determining a plurality of wide Exclusive OR (XOR) operations corresponding to a plurality of CRC output bits for a system, wherein the wide XOR operations include a plurality of XOR inputs; and factoring the wide XOR operations with cancellation using a processor to break the wide XOR operations into XOR operations no wider than the supported LUT size.