1. A method for physically synthesizing a design of an integrated circuit, the method comprising: compiling a logical description of the design into a flattened netlist; extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move; and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy, wherein at least one of: the compiling, the extracting, or the placing is performed using a processor.