1. A processor comprising: a cache shared by a plurality of processor cores; and a cache allocation circuit configured to dynamically allocate space in the cache provided to each of the plurality of processor cores based on usage patterns for each of the plurality of processor cores; wherein: the cache includes a plurality of indexes; each index is associated with a plurality of usage bits, one subset of usage bits corresponding to a unique one of the plurality of processor cores; each subset of usage bits is indicative of usage of the cache at that index by that processor core; the cache allocation circuit includes at least one counter; each counter corresponds to a unique one of the plurality of processor cores; and each counter is configured to, responsive to an access of the cache by its corresponding processor core at a given index, update a value indicated by the subset of usage bits corresponding to that processor core and the given index.