1. An apparatus comprising: a plurality of hardware-based caching agents, each associated with a respective physical processor core; a hardware-based memory access request arbiter, configured to grant a memory access request from among a plurality of input memory access requests including, memory access requests originating from the plurality of caching agents; memory access requests originating from a plurality of hardware-based Input/Output (I/O) agents; and conflicting memory access requests, previously arbitrated by the arbiter, each memory access request identifying an address associated with a cacheline for which access is requested; a distributed memory fabric including a plurality of pipelines configured to operate in parallel; at least one hardware-based caching agent conflict queue; at least one hardware-based I/O conflict queue, separate from the at least one hardware-based caching agent conflict queue; and hardware-based address conflict handling logic, configured to determine if a currently-evaluated memory access request is in conflict with another pending memory access request and configured to enqueue conflicting memory access requests from caching agents in the at least one caching agent conflict queue and enqueue conflicting memory access requests from I/O agents in the at least one I/O agent conflict queue, wherein the at least one caching agent conflict queue only stores conflicting memory access requests from caching agents and the at least one I/O agent conflict queue only stores conflicting memory access requests from I/O agents.