1. A clustered superscalar processor comprising: a plurality of clusters, each including an instruction window for storing an instruction, an upper level register file for receiving an instruction from the instruction window, outputting a register value in accordance with the instructions, and storing an execution result of the instruction, and a functional unit for executing the instruction with the register value; a lower level register file, connected to the plurality of clusters, for storing execution results of the functional units; a bypass route connected between the plurality of clusters; and a control unit for communicating the execution result of the instruction generated by the functional unit of one of the clusters to another cluster via the bypass route.