1. A digital processor including apparatus for detecting a static bit fault condition therein, said processor comprising: a first portion of arithmetic units including a set of non-linear operators for arithmetically operating on a first set of binary coded digital words to generate a plurality of output digital words which are correspondingly associated with said non-linear operations; a second portion of arithmetic units for arithmetically operating on a second set of binary coded digital words and said output digital words generated from said first portion of arithmetic units to generate at least one output binary coded words; means for converting said first and second set of binary coded digital words to their modulo 3 equivalents; a first modeling means for detecting a static bit fault which may occur in said first portion of arithmetic units and said first modeling means by processing said modulo 3 equivalents of said first set of binary digital words in accordance with a modulo 3 emulation of the arithmetic operations of said first portion of arithmetic units to generate a set of modulo 3 coded results and by comparing said set of modulo 3 coded results and the modulo 3 equivalents of a correspondingly associated set of preselected binary digital words intermediate to the non-linear operations performed by said first portion of arithmetic units for non-equivalence, a non-equivalence condition being an indication of the existence of a static bit fault, said first modeling means being further operative to generate a third set of digital words which are the modulo 3 representatives of a predetermined portion of each of said preselected binary coded words, said predetermined portions being based on the non-linear operations from which the digital words were preselected; and a second modeling means for detecting a static bit fault which may occur in said second portion of arithmetic units and said second modeling means by processing said modulo 3 equivalents of said second set of binary digital words and said third set of digital words in accordance with a modulo 3 emulation of the arithmetic operations of said second portion of arithmetic units to generate at least one modulo 3 coded result and by comparing said at least one result and the modulo 3 equivalent of said at least one output binary word generated from said second portion of arithmetic units for non-equivalence, a non-equivalence condition being an indication of a static bit fault.