1. A computer implemented design conversion method for a field programmable gate array (FPGA) device that is convertible into a metal programmable gate array (MPGA) device, wherein each of the FPGA and MPGA devices comprises an exact transistor layout of a logic block array, the method comprising: receiving a bit stream to configure the FPGA, wherein a first portion of the bits determine functionality of one or more of said logic blocks in the FPGA; and generating a conductive pattern to configure the MPGA, wherein the result of said first portion of bits in the FPGA is replicated in a first portion of the conductive pattern to provide identical functionality of said one or more logic blocks in the MPGA wherein each of said FPGA and MPGA devices comprises an exact layout of a portion of interconnect wires to couple one or more of said logic blocks; and in said bit stream to configure the FPGA, a second portion of bits determine the interconnect wire coupling of said one or more logic blocks in the FPGA; and said conductive pattern to configure the MPGA, wherein the result of said second portion of bits in the FPGA is replicated in the second portion of the conductive pattern to provide identical interconnect wire coupling of said one or more logic blocks in the MPGA; wherein each of said FPGA and MPGA further comprises an exact layout of one or more pass-gate devices to couple said one or more logic blocks to said portion of interconnect wires, wherein: in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising: a logic one to couple the logic block to the interconnect wire; and a logic zero to decouple the logic block from the interconnect wire; and in the MPGA, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero; and in the MPGA, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one; and wherein an interconnect wire in the FPGA comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the MPGA comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire; and an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the FPGA, and wherein said interconnect wire coupled to the logic block in the MPGA encounters less resistance from the metal-jumper.