1. A parallel Huffman data decoder for decoding data encoded in accordance with a Huffman code, said parallel Huffman data decoder comprising: a holding register having a main portion holding a main data input, a lookahead portion holding a lookahead input, and a plurality of outputs; a plurality, M, of half-decoders, each having an input coupled to a corresponding one of said plurality of outputs of said holding register, and an output, said inputs each obtaining from said outputs of said holding register consecutive overlapping portions of data in said main portion and said lookahead portion of said holding register; a full decoder implemented in ternary content-addressable memory, said full decoder having an input selectively connectable to obtain a given one of said overlapping portions of data, and an output; a decoder selection and sequencing unit having a plurality of inputs coupled to said outputs of said half-decoders and said output of said full decoder, a selection output that controls said selective connection of said full decoder input, and a plurality of output lanes; wherein: said full decoder includes all code words of said Huffman code; said half-decoders includes a subset of frequently-occurring code words of said Huffman code; said half-decoders decode, in parallel, in a single clock cycle, when no code word not available in said half-decoders is encountered, M of said frequently-occurring code words; and when a code word not available in said half-decoders is encountered, said decoder selection and sequencing unit causes to be applied to said input of said full decoder, input intended for a corresponding one of said half-decoders, which input includes said code word not available in said corresponding one of said half-decoders.