1. Digital video processing apparatus comprising: a plurality of render processors arranged in a directed acyclic graph, each operable to render an output result relating to an image of a video signal from input data relating to that and/or other images received from a preceding render processor in said directed acyclic graph; and a render controller for controlling rendering operation of said render processors; each render processor being operable to communicate dependency data to said render controller, indicating which images must be rendered by a preceding render processor in order for that render processor to render output data relating to a required image; and said render controller being operable to control operation of said render processors so that images required by each render processor are rendered by preceding render processors in said directed acyclic graph.