1. A logic circuit apparatus, comprising: a plurality of programmable logic circuits each configured to have a changeable circuit component based on circuit data, each programmable logic circuit having a different processing performance; a circuit data memory to store a plurality of circuit data and performance requirements for each circuit data; and a control unit configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on a condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.