1. An interrupt control apparatus for acknowledging on a priority basis and validating one among several possible asynchronous interrupt requests (INT1, INTN) comprising: a priority encoding network receiving on its input terminals said interrupt requests and providing on its output terminals a code representative of the highest priority interrupt amoung those present simultaneously on its input terminals; a latching register receiving on its input terminals said code, said register being cyclically enabled to load said code; and, a selection circuit receiving on its data input terminals said interrupt and on its selection input terminals said code as output from said register, said selection circuit selecting that one among several said interrupts which is represented by said code, said selection circuit providing on its output terminal a validation signal at a first logic level when said selected interrupt is really present and an invalidation signal at a second logic level when said selected interrupt is not present.