1. An integrated circuit (“IC”) comprising: a plurality of configurable logic circuits; a first routing network for connecting the configurable logic circuits; a plurality of user design state (“UDS”) circuits; and a second debug network communicatively coupled to the UDS circuits, said second debug network for receiving addresses for a plurality of the UDS circuits in a random access manner and for randomly reading state values stored by the addressed UDS circuits during user-design operation of the IC; wherein to read the plurality of UDS circuits, a plurality of read instructions are transmitted over the second debug network of the IC.