1. A method for testing a circuit implemented on a programmable logic device using a host processor coupled to the programmable logic device via an interface device, the interface device having a plurality of signal pins for configuring the programmable logic device, comprising: connecting selected pins of the interface device to selected input pins of the programmable logic device; applying test vectors from the host processor to the selected input pins of the programmable logic device via the interface device, each test vector including one or more signal states to be applied to the programmable logic device; and analyzing states of signals appearing on output pins of the programmable logic device.