1. A processor comprising: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in said instruction pipeline or in an instruction prefetch buffer and an instruction code to be read next from an instruction cache memory or from a main memory, to judge whether or not the instruction codes are identical with each other; and a control unit whose control when the instruction codes are identical with each other is to read the instruction code neither from said instruction cache memory nor from said main memory but to process the instruction code stored in said instruction pipeline or in the instruction prefetch buffer again in said instruction pipeline or in the instruction prefetch buffer.