1. A processor comprising: a first memory comprising a first read port and a first write port, wherein the first write port is coupled to a direct memory accesses (DMA) interface for loading data to the first memory; a second memory comprising a second read port and a second write port, wherein the second write port is coupled to the DMA interface for loading data to the second memory; a first execution unit coupled to the first read port to receive a source operand, and wherein the first execution unit is further coupled to the first write port to write a first result value; a second execution unit coupled to the second read port to receive a source operand, and wherein the second execution unit is further coupled to the second write port to write a second result value; and an instruction storage unit for storing two instructions fetched from a program for execution in parallel, wherein a first instruction configures execution controls for the first memory and the first execution unit and a second instruction configures execution controls for the second memory and the second execution unit.