1. A method comprising: receiving, by a computer system, data upon which a cryptographic operation is to be performed, wherein the computer system includes a host central processing unit (CPU) and a cryptographic hardware accelerator coupled to the host CPU; dividing, by the CPU, the data into a plurality of blocks; offloading, by the CPU, performance of the cryptographic operation on a first block of the plurality of blocks to the cryptographic hardware accelerator; for each remaining block of the plurality of blocks: requesting, by the CPU, state information associated with the cryptographic hardware accelerator; when the state information satisfies a predetermined condition, then offloading, by the CPU, performance of the cryptographic operation on the remaining block to the cryptographic hardware accelerator; when the state information does not satisfy the predetermined condition, then performing, by the CPU, the cryptographic operation on the remaining block by invoking a native hardware supported cryptographic instruction on the remaining block; and wherein the cryptographic operation is performed on at least one of the plurality of blocks by the cryptographic hardware accelerator and the cryptographic operation is performed on at least another of the plurality of blocks by the CPU.