1. A memory cell, comprising: a silicon (Si) stack consisting of a plurality of Si-based layers formed into a resistive switching memory layer that enters a first electrical state in response to application of a first electrical signal to the memory cell and enters a second electrical state in response to application of a second electrical signal to the memory cell, wherein the second electrical signal has a different magnitude or polarity than the first electrical signal, wherein the plurality of Si-based layers comprise at least a first Si or Si derivative layer doped to a first resistance value and a second Si or Si derivative layer doped to a second resistance value different from the first resistance value, wherein the first Si or Si derivative layer and the second Si or Si derivative layer are adjacent layers within the Si stack without an intervening layer; and a wiring layer comprised of Si or a Si derivative configured to facilitate application of the first electrical signal or the second electrical signal to the memory cell, wherein the wiring layer is formed adjacent to the Si stack.