1. A memory control circuit comprising: a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting an individual bit of the individual bits that is read out from a memory cell among the memory cells to a corresponding expectation value expected to be stored in the memory cell when the memory cell is determined, prior to the conversion processing, to be successfully storing the individual bit as an expectation value; and a determination circuit determining a result of a write processing to write parallel expectation value data to the nonvolatile memory, based on the parallel readout bit data converted by the conversion circuit and the parallel expectation value data.