1. A computer-implemented process performed by a computer including a plurality of processors, comprising: an interrupt router assigning each interrupt source of a plurality of interrupt sources to a selected processor from among the plurality of processors, the plurality of interrupt sources having a corresponding plurality of interrupt handlers; in response to each interrupt from an interrupt source of the plurality of interrupt sources, executing the interrupt handler for the interrupt source on the processor assigned to the interrupt source; each interrupt handler storing, in a first data structure in a memory for the processor executing the interrupt handler, data indicating an amount of processing time consumed due to executing the interrupt handler; the interrupt router receiving from the plurality of processors, into a second data structure in a memory for the interrupt router, the data indicating the amount of processing time consumed by the plurality of processors due to executing the interrupt handlers; the interrupt router determining a load on the computer due to interrupt handling by the plurality of processors based on at least the received data; and the interrupt router reassigning the plurality of interrupt sources among the plurality of processors based on at least a function of the determined load so as to distribute the load among the processors while maximizing a number of processors that are idle.