1. An apparatus comprising: a first group of memory cells coupled to a first access line and configured to store a plurality of elements, the elements in the first group comprising a first element having a first bit length and a second element having a second bit length that is different from the first bit length; a second group of memory cells coupled to a second access line and configured to store a plurality of elements, the elements in the second group comprising a first element having a first bit length and a second element having a second bit length that is different from the first bit length; wherein the first element in the first group has a bit length that is the same as the bit length of the first element in the second group and the second element in the first group has a bit length that is the same as the bit length of the second element in the second group; wherein the first element in the first group and the first element in the second group comprise a first element pair; and wherein the second element in the first group and the second element in the second group comprise a second element pair; and a controller configured to cause: the first element pair to be compared by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line; and the second element pair to be compared in parallel with the first element pair.