1. A multiply-accumulate circuit comprising: a bit-wise AND gate having a plurality of bits, each bit having a first input receiving a corresponding input operand bit, a second input receiving a control signal ZERO and an output; a partial product generator having a first input receiving a first operand and a second input connected to said output of said a bit-wise AND gate, said partial product generator forming partial products of data supplied to said first and second inputs at an output; an adder tree having a first input connected to said partial product generator output and a second input, said adder tree forming a sum of said partial products and data supplied to said second input at an output; an accumulator having an input connected to said output of said adder tree for receiving and storing said sum and an output for supplying data stored therein; and a multiplexer having a first input connected to said output of said accumulator and a second input receiving external data, said multiplexer supplying a selected one of data on said first input or on said second input to an output connected to said second input of said adder tree.