1. An apparatus for concurrently dispatching instructions of a plurality of threads of execution in a microprocessor, the apparatus comprising: a group indicator, for each thread of the plurality of threads, for indicating which one of a plurality of groups of the plurality of threads said thread belongs to; a group priority indicator, for each group of said plurality of groups, for indicating a priority of said group, said priority indicating a priority for dispatching instructions of the plurality of threads of said group relative to other groups of said plurality of groups; and selection logic, coupled to said group indicators and said priority indicators, configured to select a thread of the plurality of threads, for dispatching to execution an instruction thereof, based on said group indicators and said group priority indicators.