1. A programmable integrated circuit device comprising: a multiplication stage that computes a product of a first data input and a second data input; a floating-point adder stage that computes a sum; a logic block that generates a flag signal; configurable interconnect circuitry that (i) routes signals into and out of each of the multiplication stage and the floating-point adder stage and (ii) selects one of the product generated by the multiplication stage and a third data input as a selected adder input; and a plurality of register banks that (i) pipelines a fourth data input, and (ii) provides the pipelined fourth data input in parallel with the selected adder input to the floating-point adder stage and to the logic block.