1. A digital signal processing circuit, in which first and second error correction words are generated from a predetermined number of words among data consisting of a plurality of words each consisting of n bits and which can process digital data of a data format where at least said predetermined number of words and said first and second error correction words constitute one block, comprising an input terminal 1 to which said plurality of n-bit data words are supplied, a first error correction word generating circuit 20 for generating said first error correction word from said predetermined number of data words, a second error correction word generating circuit 10 for generating said second error correction word, and a timing signal generating circuit for generating a timing signal for controlling said first and second error correction word generating circuits, a plurality of data words each consisting of m bits (m being a positive integer greater than n) being supplied to said input terminal 1, said second error correction word generating circuit 10 effecting operations necessary for generating said second error correction word with at least one clock signal among a bit clock of m-n bits and controlled by a timing pulse output from said timing signal generating circuit.