1. A digital processing apparatus comprising: a decoder to receive a control signal and to identify a first packed shift operation indicating a first shift count source if the control signal includes a first instruction encoding of a packed shift control signal format; a storage location to hold a first packed data having a set of data elements; a shifting circuit to shift the first packed data by a first number of positions responsive to the identified first packed shift operation and the indicated shift count source; and a correction circuit to generate a first replacement data for one of the first number of positions, the correction circuit coupled to the shifting circuit to produce a shifted first packed data comprising the first replacement data.