1. An integrated circuit microprocessor that configures and executes integrated finite state machines, that are dedicated to executing particular computer algorithms, by utilizing both integrated re-configurable logic, and configuration bit map codes that are generated by the said integrated circuit microprocessor itself by decoding, re-ordering, parsing and then converting the pre-compiled or pre-assembled sequences of binary encoded Complex Instruction Set Computer (CISC) type or Reduced Instruction Set Computer (RISC) type machine code instructions that are composed of members of a conventional CISC type or RISC type microprocessor's machine code instruction set, that represent the said particular computer algorithms, into the said configuration bit map codes that are used by the said integrated circuit microprocessor to configure the said integrated re-configurable logic into the said integrated finite state machines in order to execute the said particular computer algorithms at a faster rate than the rate at which the said conventional CISC type or RISC type microprocessor can execute the same said particular computer algorithms; And within the said integrated circuit microprocessor comprises: An integrated array of re-configurable gate logic hardware circuits; An integrated array of re-configurable register[s] logic hardware circuits; An integrated programmable switch network having direct operational connections to every element contained within both the said array of re-configurable gate logic hardware circuits and the said array of re-configurable register[s] logic hardware circuits; An integrated memory hardware circuit block containing both cache memory and non-volatile memory hardware circuits; An integrated binary code decoder hardware circuit block that provides the means for dynamically decoding, re-ordering, and parsing the said sequences of binary encoded CISC type or RISC type machine code instructions, that represent the said particular computer algorithms, into newly generated sequences of binary code which are then stored into the said integrated memory hardware circuit block; An integrated binary code converter hardware circuit block that provides the means for dynamically converting the said newly generated sequences of binary code, that are generated by the said integrated binary code decoder hardware circuit block, into newly generated configuration bit map[s] codes which are then stored into the said integrated memory hardware circuit block; An integrated constructer hardware circuit block that provides the means for constructing the said integrated finite state machines thru the use of the said configuration bit map[s] codes, that are generated by the said integrated binary code converter hardware circuit block, and the controlling of the said integrated programmable switch network; An integrated memory bus controller hardware circuit block that provides the means for directly interfacing with an external memory bus and operating the said external memory bus in order to fetch the said sequences of binary encoded CISC type or RISC type machine code instructions that are stored in externally shared memory which are then stored into the said integrated memory hardware circuit block; An integrated inter-processor communication bus controller hardware circuit block that provides the means for directly interfacing with an external inter-processor communication bus and operating the said external communication bus in order to communicate with the other processors; and An integrated main controller hardware circuit block that provides the means for controlling and coordinating the activities of all the said integrated hardware circuit blocks comprised within the said integrated circuit microprocessor.