1. A processor that performs pipeline processing on an instruction, the processor comprising: an acquisition unit constructed to acquire the instruction which has an operation code specifying a type of the instruction and destination register information; a pipeline register constructed to store a processing result based on the instruction acquired by the acquisition unit; and a storage control unit constructed to control a register to store the processing result stored in the pipeline register, wherein the register which stores the processing result is designated by the destination register information; and a control unit constructed to control processing based on a second instruction acquired by the acquisition unit and control storing of a processing result based on a first instruction acquired by the acquisition unit, wherein the control unit is further constructed to: determine whether both of conditions (i)-(ii) are satisfied (i) the second instruction indicates that the second instruction is for performing processing by using data stored in the register designated by the destination register information in the first instruction, and (ii) the operation code in the instruction acquired by the acquisition unit indicates that the second instruction is a last instruction for performing the processing by using data stored in the register designated by the destination register information in the first instruction; and in response to determining that both of conditions (i)-(ii) are satisfied, control the processing and the storing such that data used for the processing based on the second instruction is acquired from the pipeline register and the processing result based on the first instruction is not stored in the register designated by the destination register information in the first instruction, wherein whether to store the processing result based on the first instruction is determined based on an indication associated with the second instruction.