1. A method for early instruction text based operand store compare avoidance in a processor pipeline, the method comprising: creating addresses for a load store unit to access memory; sending instruction text to an instruction grouping, wherein the instruction grouping establishes dependencies between an operand in the instruction text of a load instruction following a store instruction in the processor pipeline; determining a delay period for delaying the load instruction; and delaying, based on the determined delay period, the load instruction in the processor pipeline prior to reaching the load store unit.