1. A method for modeling the resistance of a semiconductor contact via (CA) structure sensitive to layout-based and fabrication based variations, said method comprising the steps of: using a computer, obtaining layout contours of said contact via structure and semiconductor structures contacting said contact via structure accounting for various sets of lithographic processing condition parameters; determining from said layout contours an intersecting area of said contact via structure with said contacting semiconductor structures, said intersecting areas obtained for said various sets of lithographic processing condition parameters and stud dimensions; obtaining one or more CA resistance distributions with each distribution having layout-based variations, lithographic processing condition parameter variations, stud dimension variations, and material fill property and thickness variations; and, bucketizing CA resistance distributions; and, providing a device parasitic netlist with bucketized CA resistance values; and, utilizing said device parasitic netlist values to provide for more accurate circuit behavior modeling of circuits having said CA.