1. A configurable specialized processing block on an integrated circuit device, said configurable specialized processing block comprising: a first floating-point arithmetic operator stage; a second floating-point arithmetic operator stage; configurable interconnect within said configurable specialized processing block for routing signals into and out of each of said first and second floating-point arithmetic operator stages; and fixed rounding circuitry for performing a partial rounding operation on output of said second floating-point arithmetic operator stage, said fixed rounding circuitry comprising a rounding condition detector and an overflow detector, said overflow detector comprising: a first AND-gate combining output mantissa bits of said second floating-point arithmetic operator stage, and a second AND-gate combining output of said first AND-gate and output of said rounding condition detector.