1. A memory array, comprising: a plurality of memory cells each configured with greater than two information states, said information states of each of said plurality of memory cells being combinatorially mapped to a plurality of memory states which are further mapped to both a lesser plurality of valid data states corresponding to a plurality of binary data bits and one or more invalid data states; and a parity generator operably coupled to said plurality of memory cells for generating one or more parity bits representative of and for associating with said plurality of binary data bits.