1. An integrated circuit comprising a memory controller, the memory controller comprising: a first determining circuit to determine a first level for programming or erasing a memory segment as a function of an initial program/erase level; a second determining circuit to determine a first updated level for a subsequent program/erase operation of the memory segment; and a third determining circuit to determine a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment using the first level, wherein the second level is determined as a function of the first updated level.