1. A machine-learning accelerator (MLA) integrated circuit for extracting features from signals and performing inference computations comprising: a framework of finite state machine (FSM) kernels that are machine-learning algorithms implemented in hardware; a kernel controller having mathematical structures implemented in hardware in communication with the framework of FSM kernels; an arithmetic engine implemented in hardware in communication with the kernel controller to perform computations for the mathematical structures; and a power management unit (PMU) that provides an idle-mode for the framework of FSM kernels, the kernel controller, and the arithmetic engine.