1. A processor, comprising: a front end to fetch instructions and decode fetched instructions into operations; and an arithmetic logic unit (ALU) to execute an ALU operation, wherein the ALU includes logic to: receive input operands from dispatch logic; determine whether the ALU operation is eligible to execute with spatial redundancy; determine a redundant execution mode of the ALU; perform the operation in the ALU without spatially redundant execution when the ALU operation is ineligible; and perform the operation in the ALU with spatially redundant execution, to generate a first result and a second result, when the ALU operation is eligible and the redundant execution mode permits spatially redundant execution.