1. A processor, comprising: a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers; and a translation-lookaside buffer (TLB) having a plurality of address translations, wherein for each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers.