1. A processor comprising: a first core; a second core; a first cache memory coupled to the first core and the second core and to operate with a plurality of ways, the first cache memory comprising an N way set associative cache memory, wherein the first cache memory comprises a shared cache memory; first hardware logic to cause one or more of the first core and the second core to transition from a first power state to a second power state, wherein the second power state comprises a package low power state in which the first core and the second core are power gated and at least one way of the first cache memory is to be powered with a retention voltage to maintain a context of at least one of the first core and the second core; and second hardware logic to dynamically vary a size of the first cache memory based at least in part on a performance metric of a workload to be executed on at least one of the first core and the second core, wherein the second hardware logic is to cause a single first additional way of the N ways of the first cache memory to be enabled to increase a size of the first cache memory based on a comparison of a first value of the performance metric to a threshold.