1. A method of crossing pipelined control and data between clock domains in a multi-clock domain integrated circuit, comprising: storing, by a first circuit clocked by a first clock, an element of control information in a control queue, storing, by said first circuit, an element of data in a data queue, after a pipeline delay characterized by a pre-set number of clock events of the first clock; initializing a counter to an initial value; updating the counter; and reading the element of control information from the control queue by a second circuit clocked by a second clock operating at a different frequency than the first clock, responsive to the counter reaching a pre-determined value, and then reading the element of data from the data queue after the pre-set number of clock events have occurred for the second clock.