1. A Network-On-Chip (NOC) comprising: a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, the at least one cache memory bank is distinct from each of the plurality of core tiles, and an interconnect fabric comprising: a routing-free request tree to connect to a first cache memory bank of the at least one cache memory bank, each core tile of a first one of the subsets, the first subset corresponding to the first cache memory bank, wherein the routing-free request tree forms a many-to-one interconnect such that every core tile of the first subset is connected to the first cache memory bank only, to allow each data packet sent by the core tiles of the first subset to only be received by the same first cache memory bank, and wherein the routing-free request tree comprises a plurality of request nodes, each one of which is a two-input multiplexer that merges data packets from the first input and the second input and outputs a multiplexed stream of data packets, and a reply tree, separate from the routing-free request tree, to connect the first cache memory bank to each core tile of the first subset, and allow guiding data packets from the first cache memory bank to a core tile of the first subset.