1. Within a software-based development tool, a computer-implemented method of building a simulation for verifying a design block having an interface to a first bus, which is an interface bus of a processor, and an interface to a second bus, the method comprising: determining an interface description for a bus functional model of the interface bus of the processor, wherein the interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench; generating a hardware specification, which couples the first bus with the interface description, couples the HDL testbench with the second bus and with the synchronization bus of the interface description; automatically generating the simulation for verifying the design block from the bus functional model and the hardware specification; executing the simulation by a computer for verifying the design block; and storing results of the executed simulation.