1. A processor comprising: a first processing core; a second processing core; and a power control unit to provide a first clock signal to the first processing core and a second clock signal to the second processing core, the power control unit to: initialize a performance indicator counter; cause the first processing core to operate at an initial frequency of the first clock signal for a first duration; after the first duration, determine, based on the performance indicator counter, a first performance value of a first performance parameter of the first processing core; cause the first processing core to operate at a second frequency of the first clock signal for a second duration, the second duration substantially shorter than the first duration; after the second duration, determine, based on the performance indicator counter, a second performance value of the first performance parameter of the first processing core; calculate a performance scalability of the first performance parameter of the first processing core based on the first performance value and the second performance value; modify at least one of the first clock signal and the second clock signal based on the performance scalability, including to cause the first processing core to operate at the second frequency of the first clock signal for the second duration and to return to operate at the initial frequency of the first clock signal if the performance scalability is less than a first threshold value, wherein the first threshold value is based on an acceptable performance cost.