1. A logic circuit design method utilizing a computer system, said design method comprising the steps of: inputting a first logic circuit comprising a plurality of gates; generating a second logic circuit by replacing the gates of said first logic circuit by logically equivalent functional selector cells having two inputs and one output; generating a third logic circuit by modifying said second logic circuit to reduce the number of stages of paths within said second logic circuit; and outputting a fourth logic circuit generated by mapping said third logic circuit to a CMOS logic circuit through the use of a library included in said computer system, wherein said mapping is executed with a condition of inhibiting the use of cells with at least four inputs existing in said library.