1. An apparatus that is switchable to a low power operating mode and to a normal operating mode, the apparatus comprising: an instruction processing circuit ( 14 ); a main memory ( 18 ) for providing instructions for the instruction processing circuit ( 14 ) during execution by the instruction processing circuit ( 14 ); a cache memory ( 16 ) coupled between the instruction processing circuit ( 14 ) and the main memory ( 18 ), operable in the normal operating mode to cache a part of data and/or instructions that the instruction processing circuit ( 14 ) addresses in the main memory ( 18 ) during execution, and to substitute cached data and/or instructions when the instruction processing circuit ( 14 ) addresses the data and/or instructions in the main memory ( 18 ); low power operating mode activating circuit ( 10 , 12 , 14 ), arranged to keep part of the apparatus deactivated during operation in the low power operating mode, said part of the apparatus including the main memory ( 18 ), but excluding at least part of the cache memory ( 16 ), the low power mode activating circuit ( 10 , 12 , 14 ) being arranged to load a program of instructions for executing a function during operation in the low power operating mode into said at least part of the cache memory ( 16 ) before switching to the low power operating mode.