1. A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit configured and structured to perform DCT/IDCT operations, wherein each of the DCT/IDCT operations comprises a series of butterfly operations each employing multiple coefficients, the DCT and IDCT circuit comprising: a microcode memory configured and structured to store multiple microcode groups corresponding to the DCT/IDCT operations, wherein each of the microcode groups comprises a series of microcodes; a processor configured and structured to obtain one of the microcode groups corresponding to one of the DCT/IDCT operations, and retrieve microcodes in the obtained one of the microcode groups in sequence; a butterfly operation circuit configured and structured to perform butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations, wherein the butterfly operation circuit comprises: a coefficient register configured and structured to store coefficients employed by the butterfly operations; a result register configured and structured to store operation results of the butterfly operations; a selective input module configured and structured to select one from the coefficients in the coefficient register and the operation results in the result register according to the microcodes retrieved by the processor, and output the select result; and an operation module configured and structured to perform operations on the output of the selective input module according to the retrieved microcodes to obtain the operation results and store the operation results to the result register.