1. A multiple chip package processor having multiple operational modes, including a run mode and an in-system programming mode, said multiple chip package processor comprising; a processor die including a central processing unit, said processing unit having a data output terminal for outputting data and a program counter terminal for outputting addresses for instruction fetching, a memory die including a primary memory for storing instructions for operating said central processing unit in said run mode, said primary memory having a plurality of addressable storage locations, an address input terminal for accepting addresses for accessing said storage locations, a data input terminal for accepting data to be stored in said storage locations, and a data output terminal for outputting data stored in said storage locations, a package enclosing said processor die and said memory die, a plurality of multiplexers for altering signal paths between the terminals of said central processing unit and the terminals of said primary memory, each of said multiplexers having a plurality of input terminals, an output terminal, and a control input terminal for selecting which of said plurality of input terminals will be connected to said output terminal, and a first memory interface control register having an input terminal coupled to said data output terminal of said central processing unit for accepting memory interface control bits for controlling said multiplexers and an output terminal coupled to said control inputs of said multiplexers.