1. A computing device comprising a memory and one or more functional units, wherein the computing device is configured to implement a multi-layer control structure comprising: a data structure layer comprising a local high speed memory, wherein the local high speed memory stores information for a plurality of variables, wherein each of at least two of the variables corresponds to a conceptual unit and comprises: data comprising a set of operands; a variable descriptor; and a variable ID; a mentor layer comprising a plurality of mentor circuits, wherein each of at least two of the mentor circuits is assigned to a particular one or more of the variables, wherein each of the mentor circuits is configured to perform cache management and operand addressing calculations with respect to the one or more variables to which the mentor circuit is assigned; and an instruction interpretation/control layer comprising one or more control circuits configured to control a main program flow, wherein the main program flow includes calculating one or more end operands, wherein the mentor circuits are configured to perform the operand addressing calculations with respect to the variables in parallel with one another and with the one or more control circuits controlling the main program flow, wherein the computing device is configured to implement a frames/bins structure forming the variables' caches and comprising: a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames, wherein each of at least two of the bins comprises a logical element, wherein each of the at least two variables are assigned to a particular bin within one of the frames, wherein the computing device is configured to synchronize operand traffic to or from the bins as requested by or on behalf of the mentor circuits.