1. In combination with a plurality of heterogeneous data processors having different memory address and data structures, said processors being operatively connected to main store bus means common to all of said processors, an active intelligent main store comprising: (a) memory means for storing a plurality of data words and error correcting bits associated with each word; (b) control means operatively connected to said memory means, said control means including means for providing timing and control information to said memory means for reading and writing said memory means, means for providing physical addresses and data to said memory means, and means for providing error detection and correction responsive to the physical data and addresses presently available in said address and data providing means; (c) a multiplicity of function means each being separate from said processors and each being operatively connected to said control means and operatively connected to said main store bus means, each of said function means operating substantially at main store speed, said function means including means for functionally mapping arbitrary portions of the signals on said main store bus into physical data and address information required by said control means, said functional mapping including data mapping and memory management functions such as virtual to physical address translation and memory protection, said memory protection being performed as a function of said address information required by said control means, said function means further including means for reserving portions of said memory means in response to said main store bus signals, said main store bus signals being interpreted by said reserving means to provide information to reservation algorithms associated with said function means such as base and field length reservation; and (d) each of said function means implementing diverse virtual to physical address translation methods, memory protection methods and data mapping methods thereby allowing each of said function means to interpret said main store bus signals as different address and data structures, said function means being selected by said processors through said main store bus means.