1. A semiconductor memory device, comprising: a data coding logic enabled to generate converted data groups and inverted flag data from original data groups received by the semiconductor memory device, wherein a number of program bits in the converted data groups is less than or equal to a number of program bits in the original data groups, wherein a program bit indicates that a bit in a memory cell is programmed from a logic one to a logic zero; a data decoding logic enabled to generate the original data groups from the converted data groups and the inverted flag data; a peripheral circuit enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells; and a control logic enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.