1. A system, comprising: an offload processor module that includes at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus comprising parallel address lines and parallel data lines; the offload processor module further including context memory; and logic coupled to the at least one offload processor and context memory and configured to detect predetermined write operations over the memory bus; and a memory bus controller connected to the slave interface via the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus as data writes to system memory addresses, and to output context data to the context memory, and read context data from the context memory.