1. An interrupt controller offering orthogonal scalability of a plurality of interrupt requests for use by a processor, the interrupt controller comprising: an interrupt processing module that performs interrupt masking to a sub-set of interrupt requests within the plurality of interrupt requests; an interrupt arbitration module that assigns a priority level to each of the plurality interrupt requests within the plurality of interrupt requests, the priority level being programmable; and a processor interface module that transforms at least one of the plurality of interrupt requests for use by the processor, the at least one of the plurality of interrupt requests has a highest priority level.