1. A processor comprising: an issue engine to categorize operations as either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception, wherein each architectural operation to issue with an associated architectural micro-operation, wherein a first micro-operation to check whether a first speculative operation is dependent upon an intervening first architectural operation; and an in-order execution pipeline to execute the speculative operation, the architectural operation, and the associated architectural micro-operations.