1. In a data processing system of the type in which each set of a plurality of sets of registers, one set being provided for each interrupt priority level in the system, interacts with a common main storage and common arithmetic and logic control circuits to execute respective tasks of a program, and in which a task dispatching program means operates in conjunction with priority/interrupt controls to dispatch tasks in a desired sequence to the sets of registers so that each set of registers, the arithmetic and logic unit and the main storage can process a respective task currently assigned to the latter set of registers when its priority is highest, in combination with said register sets, storage, control circuits, program means and priority/interrupt controls, apparatus, controlled in accordance with the execution of one machine level task instruction for assisting the dispatching of tasks, comprising a main storage area for holding a task address and status block (LSB) for each task for which execution is to be initiated or continued, means for fetching from main storage the LSB of a selected task and for storing the fetched LSB in the register set of a selected level, means for determining the in-process status of the selected task and the relative priority levels on which said one instruction of a current task is being executed and on which the selected task is intended for execution, and means responsive to said in-process status and said relative priority levels for initiating the execution of the selected task when the in-process status is "on" and the priority level of the selected task is higher than that of the current task.