1. A method for manufacturing an integrated circuit (IC), comprising: providing a semiconductor substrate, which is made up of a memory array region and a boundary region surrounding the memory array region; forming a hard mask layer over the memory array region and the boundary region; patterning the hard mask layer to form a boundary hard mask having one or more slots to expose some portions of the boundary region while covering the remaining regions of the boundary region and to form a dummy pattern hard mask covering some portions of the memory array region and exposing other portions of the memory array region; forming a floating gate layer within the memory array region and extending over the dummy pattern hard mask; and performing a planarization to reduce a height of the floating gate layer and form a plurality of floating gates.