1. An integrated circuit comprising: A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead; B. first TAP circuitry having a first test data input, a first test data output, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead; C. second TAP circuitry having a second test data input, a second test data output, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead; D. linking circuitry selectively coupling the first and second test data inputs to the test data in lead, coupling the first and second test data outputs to the test data out lead, and having a link control input; and E. third TAP circuitry coupled in series with the test data in lead and the test data out lead and having a linking control output coupled to the link control input, the third TAP circuitry being free of any connection of control signals from the first and second TAP circuitry.