1. A computer system ( 10 ) comprising: a common memory ( 602 ), the memory ( 602 ) having a plurality of sections ( 6020 ); and a scalar/vector processor ( 100 ) coupled to the memory ( 602 ) using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory ( 602 ) is associated with each address bus and at least one of the sections of the memory ( 602 ) is associated with each read-data bus, the processor ( 100 ) having a plurality of scalar registers ( 150 ) and a plurality of vector registers ( 160 ) and operating on instructions which provide a reference address to a data word, the processor comprising: a scalar/vector cache unit ( 200 ), the cache unit ( 200 ) including: a cache array ( 530 ), and a FIFO unit ( 510 ) that tracks an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory ( 602 ), and a destination code that specifies which of the scalar registers and vector registers into which the read-data value is to be loaded when the read-data value is returned from the memory ( 602 ).