1. A system for enhancing timeliness of cache memory prefetching in a processing system, the system comprising: a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses; a confidence counter; and eager prefetching control logic for performing a method when the stride size is less than a cache line size, the method comprising: adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern; comparing the confidence counter to a confidence threshold; and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold.