1. An interconnection architecture for multilayer circuits comprising: an array of vias; a CMOS layer configured to selectively access the array of vias according to an address; a crossbar stack comprising layers of intersecting wire segments with programmable crosspoint devices interposed between intersecting wire segments; in which the array of vias is connected to the wire segments such that each programmable crosspoint device is uniquely addressed and every address within a contiguous address space accesses a programmable crosspoint device.