1. An apparatus for disabling writes to, but not reads from, main memory in a computer system during cache memory diagnostics, wherein the computer system comprises a CPU, cache memory coupled to the CPU, a cache controller coupled to the CPU and the cache memory, main memory, and a memory controller coupled to the main memory, the CPU, and the cache controller, the apparatus comprising: a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory; and a signal source coupled to said buffer which asserts a disable signal to said buffer during cache memory diagnostics, wherein said disable signal prevents assertion of said write signal to the main memory during said cache memory diagnostics but does not prevent assertion of read signals to the main memory during said cache memory diagnostics.