1. A processor comprising: a plurality of processing threads configured to: perform vertex processing operations to produce vertex output information; divide a display area into a plurality of sub-screens; store the vertex output information as a plurality of sub-screen tasks in a list of sub-screen tasks, wherein a sub-screen task comprises a plurality of the vertex output information for a particular sub-screen of the plurality of sub-screens; prioritize pixel rendering operations over available vertex processing operations when one of the sub-screen tasks in the list of sub-screen tasks is available for the pixel rendering operations.