1. Method for mapping an integral into a thread of a parallel architecture, in the course of which the integral is mapped into a summation expressed by coefficient values and summation values (S 100 ), characterised by generating a directed graph corresponding to the computation of the summation (S 110 ), the directed graph comprising input nodes ( 40 , 42 , 44 , 44 ′, 46 ) corresponding to the coefficient values and to the summation values, being connected to inputs of edges ( 48 , 49 ), respectively, and being adapted for giving their values, as intermediate values, to the edges ( 48 , 49 ) connected thereto with their inputs, at least one intermediate node ( 50 , 52 , 54 , 56 , 58 , 60 ) each corresponding to one operation of the summation, and being connected to outputs of two edges ( 48 , 49 ) and to an input of one edge ( 47 ), and being adapted for performing the operation on the values of the edges ( 48 , 49 ) connected thereto with their outputs, and for giving the result of the operation as an intermediate value to the edge ( 47 ) connected thereto with its input, and an output node being connected to the output of an edge corresponding to an intermediate value corresponding to at least a part of the summation, and being adapted for receiving the intermediate value thereof, assigning a level of a traversal sequence to each of the nodes ( 40 , 42 , 44 , 44 ′, 46 , 50 , 52 , 54 , 56 , 58 , 60 ), respectively (S 200 ), and specifying, at each level of the traversal sequence, a storage location of the intermediate value corresponding to the edge ( 47 , 48 , 49 ) connected with its input to the node ( 40 , 42 , 44 , 44 ′, 46 , 50 , 52 , 54 , 56 , 58 , 60 ) corresponding to the given level (S 300 ) in a memory corresponding to the thread and comprising a register storage ( 10 ), a local storage ( 20 ), and a global storage ( 30 ).