1. A processor, comprising: guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers; and root mode control registers supporting root mode operating behavior defined by root context specified in the root mode control registers, wherein the guest context and the root context are simultaneously active to control the guest mode operating behavior and support virtualization of hardware resources without a context switch to or from memory, such that multiple operating systems supporting multiple applications are executed by the hardware resources, and such that an interrupt or exception typically causing exits from the guest mode is handled using the root context without additional context switching.