1. An AND logic gate comprising: a first four-gate field emitter transistor (G4-FET) having three inputs and one output; and a second G4-FET having three inputs and one output, wherein: one of the inputs of the first G4-FET has a low logic value; a first input of the second G4-FET has a logic value which is opposite to a logic value of a second input of the second G4-FET; and a third input of the second G4-FET is connected to the output of the first G4-FET.