1. A method for use in a superscalar processor in which instructions of the same or different types are dispatched and executed in parallel in multiple execution units, comprising the steps of: decoding complex multifunctional and multi-cycle execution instructions in a decode unit that decodes said complex multifunction and multi-cycle execution instructions and loads them into an instruction queue buffer, and examining the loaded complex multifunctional and multi-cycle instructions in said instruction queue buffer and grouping them for execution, and dispatching said grouped complex multifunction and multi-cycle instructions to a fixed point execution unit (FXU) for execution of the dispatched instructions in parallel in multiple execution pipelines of said superscalar processor.