1. A macro layout verification apparatus comprising: a unit configured to assume as a virtual wiring line a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line, the unused intra-macro channel capable of being used for wiring a wiring line of a chip-level layout of a semiconductor device; a unit configured to calculate a parallel wiring length along which said virtual wiring line and said intra-macro wiring line run; a unit configured to compare said parallel wiring length with a reference value defined as a design rule to verify a layout of a macro to be placed as a functional block on the chip-level layout; and a unit configured to output information concerning said virtual wiring line when said parallel wiring length exceeds the reference value defined as a design rule.