1. A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including at least one synchronous element therein responsive to a clock signal, a set of clock lines including a plurality of main clock lines receiving different clock signals, and a plurality of column clock lines each associated with and selectively connectable to a particular column of logic cells, each column clock line being selectively connectable to any of said main clock lines to receive a selected clock signal therefrom, and each column clock line being selectively connectable to its particular associated column of logic cells by means of a plurality of sector clock lines connectable to that column clock line, each sector clock line connected to a subset of the logic cells in the associated column of logic cells.