1. A semiconductor memory comprising: a. an array of rows and columns of memory cells on a face of a semiconductor body; b. an MOS transistor included in each of said memory cells, each MOS transistor having gate, source and drain regions and a channel region, insulator material above the channel region and beneath the gate being much thinner than surrounding insulator material on said face; c. selected ones of the channel regions of the MOS transistors being implanted with conductivity-detemining imputities to a depth much less than that of the source and drain regions and to an extent whereby the threshold voltage is substantially zero and the source and drain regions are essentially shorted together at zero volts on the gate, to thereby permanently program certain cells of the memory.