1. A processor, comprising: decode logic coupled to a first storage unit and comprising a data structure; and a second storage unit coupled to said decode logic; wherein the decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in said data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand; wherein, if indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by said group of instructions.