1. An analog vector absolute differencing circuit comprising: a linear array of comparison circuits, each of said comparison circuits of said linear array including means for comparing a first analog signal value to a second analog signal value to produce an absolute difference signal, said linear array thereby producing a plurality of absolute difference signals; a common integration line coupled to said linear array of comparison circuits, said common integration line receiving said plurality of absolute difference signals; means, coupled to said integration line, for summing said absolute difference signals to yield a difference sum; wherein said comparing means includes a first transistor, the source of said first transistor being coupled to a first capacitor, the drain of said first transistor being coupled to said common integration line, and the gate of said first transistor being coupled to a first analog signal input node, a second transistor, the source of said second transistor being coupled to a second capacitor, the drain of said second transistor being coupled to said common integration line, and the gate of said second transistor being coupled to a second analog signal input node, wherein a first analog signal is stored on said first capacitor corresponding to said first analog signal value and a second analog signal is stored on said second capacitor corresponding to said second analog signal value during a precharge step, and wherein said first analog signal value is applied to said second analog signal input node and said second analog signal value is applied to said first analog signal input node during a compute step to generate said absolute difference signal.