1. A microprocessor, comprising: an instruction decoder to receive and decode a first instruction as a single SIMD instruction representing SKEIN256 MIX-PERMUTE operations, the first instruction having an opcode, a first operand indicating a first address associated with a first storage location to store a plurality of odd words, a second operand indicating a second address associated with a second storage location to store a plurality of even words, and a third operand indicating a third address associated with a third storage location; and a first execution unit to receive the decoded first instruction from the instruction decoder and to execute the decoded first instruction, wherein the execution of the first instruction comprises, retrieving the odd words from the first address, retrieving the even words from the second address, performing a plurality of rounds of the SKEIN256 MIX-PERMUTE operations based on the odd words and the even words using a first rotate value obtained from the third address indicated by the third operand, generating a plurality of new odd words, and storing the new odd words in the first address, wherein retrieving the odd words and the even words from the first and second addresses, performing the plurality of rounds of the SKEIN256 MIX-PERMUTE operations, and storing the new odd words in the first address are performed by the first execution unit in response to receiving the decoded first instruction as a single SIMD instruction, and wherein the instruction decoder decodes the opcode, the first operand, the second operand, and the third operand to derive the first, second, and third addresses corresponding to the first, second, and third operands, respectively, and passes each of the first, second, and third addresses to the first execution unit to execute the decoded first instruction using each of the first, second, and third addresses.