1. An apparatus, comprising: a memory controller with circuitry configured to: initiate a program verify sequence to verify data written to a non-volatile memory (NVM), said program verify sequence having one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified; detect an approximate percentage of memory cells for each program verify level in which data is successfully written; and determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold; wherein the memory controller further comprises logic configured to either: identify a voltage drop (Va-Vb) across a resistance (rpwr) in a NVM storage device, wherein the voltage drop (Va-Vb) is represented by a current limit (Ilimit) multiplied by a number of memory cells in a defined program verify level for which data is not successfully written (no_of_fails) multiplied by the resistance (rpwr); compare the voltage drop (Va-Vb) across the resistance (rpwr) to a predefined threshold; and either determine to skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is greater than the predefined threshold; or determine to not skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is less than the predefined threshold; or identify a rate of discharge of a voltage (Vreg0) through a current limited pull down path of a NVM storage device, wherein a shielded bit line architecture is utilized in the NVM storage device; and detect the approximate percentage of memory cells in a defined program verify level for which data is successfully written based on the rate of discharge of the voltage (Vreg0) and a current limit (Ilimit); and one or more of: the NVM, the NVM being communicatively coupled to the memory controller; a processor communicatively coupled to the memory controller; a network interface communicatively coupled to a processor; a display communicatively coupled to a processor; or a battery coupled to a processor.