1. A non-volatile memory cell of which includes a single MOS transistor, comprising: a semiconductor substrate; source and drain diffusion layers and a channel region between said source and diffusion layers formed on a surface of said semiconductor substrate; a gate electrode disposed over said semiconductor substrate with a gate insulating film interposed between said gate electrode and said channel region; and a programmable insulating film provided in self-alignment between said gate electrode and either one of said source and drain diffusion layers so that said programmable insulating film is selectively broken down by a predetermined voltage applied to said gate electrode to execute programming and electrically conduct between said gate electrode and either one of said source and drain diffusion layers, and a breakdown voltage of said gate insulating film is higher than that of said programmable insulating film and said predetermined voltage; said gate insulating film and said programmable insulating film disposed adjacent to each other under said gate electrode.