1. An apparatus, comprising: a multicore processor including a plurality of processing cores, a plurality of memory management units, and a plurality of peripheral access management units, each of the processing cores configured to operate exclusively with only one of the memory management units and each of the processing cores configured to operate with one or more of the peripheral access management units; a first cache and a second cache each configured to be shared by at least two of the processing cores; and a separation kernel configured to execute within each of the plurality of processing cores, the separation kernel configured to enforce static virtual address mappings that form at least two isolated memory domains within a shared system memory and the first and second shared caches, wherein two or more of the processing cores including a first processing core and excluding a second processing core are configured to employ the first shared cache, and wherein two or more of the processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache.