1. A memory controller for use with a memory having memory cells including spare memory cells, comprising: an internal self-test logic circuit built in within the memory controller, the self-test logic circuit including: a test pattern generator for generating test patterns and for testing memory cells within the memory using the generated test patterns; wherein the test pattern generator includes a plurality of generators including at least one address generator configured to generate a pattern of memory cell addresses in response to an address instruction to traverse a memory region of a plurality of memory cells, and at least one data generator configured to generate in response to a data instruction, a pattern of data for a pattern of test data, to be written in memory cells addressed by a pattern of memory cell addresses generated by the address generator wherein the generated pattern of data is a selectable function of the pattern of memory cell addresses of the memory cells in which the generated pattern of data is to be written.