1. A dynamic memory system comprising: a dynamic memory having a plurality of dynamic integrated circuit memory chips, each dynamic integrated circuit memory chip storing digital data bits; a memory refresh circuit coupled to the dynamic memory the memory refresh circuit refreshing the data bits stored by the plurality of dynamic integrated circuit memory chips; a memory address circuit generating a memory address; a decoder circuit coupled to the memory address circuit, the decoder circuit generating memory chip select signals in response to the memory address; a chip select circuit coupled to the plurality of dynamic integrated circuit memory chips and to the decoder circuit, the chip select circuit selecting at least one but not all of the plurality of dynamic integrated circuit memory chips in response to the memory chip select signals; a memory accessing circuit coupled to the plurality of dynamic integrated circuit memory chips and coupled to receive a memory address from the memory address circuit, the memory accessing circuit accessing a plurality of data bits stored by the selected at least one of the dynamic integrated circuit memory chips in response to the received memory address; and a plurality of memory output circuits coupled to the memory accessing circuit, the memory output circuits outputting at least one of the plurality of data bits accessed by the memory accessing circuit from a selected one of the plurality of dynamic integrated circuit memory chips onto a memory output signal that is selectively coupled to each of the plurality of dynamic integrated circuit memory chips.