1. A real time multiplier for multiplying digital serial operand electrical signals representing a multiplicand, a.sub.o a.sub.1 - - - a.sub.n.sub.-1 and a multiplier b.sub.0 b.sub.1 - - - b.sub.n.sub.-1 to provide a product c.sub.k c.sub.k.sub.+1 - - - c.sub.2n.sub.-1, where 0.ltoreq.k.ltoreq.2n-1 comprising a plurality of serially connected multiplier stages, a first, second, third, fourth, fifth and sixth electrically conducting lines, means for simultaneously applying each of the multiplicand and multiplier signals serially at a fixed rate in time coincidence to the input terminals of said first and second lines, respectively, with the signals corresponding to the least significant digit a.sub.0, b.sub.0, being applied first, a plurality of delay elements each having a delay of one digit-time-duration, said first and second lines being connected to corresponding inputs of each multiplier stage, said first and second lines having a delay element in each line between alternate mutiplier stages, the first delay element being in said first and second lines between the connections to the inputs of the second multiplier stage "1 " and the third multiplier stage "2", means for applying a first gating pulse to the input terminal of the third line t.sub.a connected to one input of each multiplier stage, said third line t.sub.a having a delay element between corresponding inputs of each multiplier stage and an additional delay element in line t.sub.a between the multiplier stages having said delay elements in said first and second lines, said first gating pulse being in time coincidence with the least significant digits a.sub.0, b.sub.0 of the operands at the input to said multiplier, means for applying a second gating pulse to the input terminal of a fourth line t.sub.b connected as a second input to each multiplier stage, said fourth line t.sub.b having a delay element between corresponding inputs of each multiplier stage and an additional delay element in line t.sub.b between the multiplier stages having said delay element in said first and second lines, said second gating pulse being applied to the input of the first multiplier stage at the same time as the most significant operand digits a.sub.n.sub.-1, b.sub.n.sub.-1 are applied on their respective signal lines to the input of the first multiplier stage, means for applying a third gating pulse to a fifth line t.sub.d, a plurality of two-input OR gates, the output of each OR gate being connected as an input to each of said multiplier stages, the input of each OR gate being connected to said fifth line at locations such that said third gating pulse on said fifth line is applied as an input to the OR gate connected to the input of stage n/2 at a time when operand signal a.sub.n/2 arrives to be stored in stage n/2 for n even, (or stage (n+1)/2 and at a time when operand signal a.sub.(n.sub.+1)/2 arrives to be stored in stage (n+1)/2 for n odd,) said fifth line t.sub.d containing a means for delay of one pulse interval between the first and second stages and alternate stages following the second stage, the OR gate whose output is connected to the input of the first multiplier stage "0" also being connected to the input of the sixth line, the sixth line being connected as an input to each OR gate connected to the remaining multiplier stages, said sixth line containing a delay element of unit-pulse-length delay after the second multiplier stage "1" and the following alternate multiplier stages, said third gating pulse being of time duration equal to that of two signal digits, means for effecting the storage of each successive digit of the multiplier and multiplicand in each successive serially-connected multiplier stage in response to the first gating pulse on said third line t.sub.a and the multiplicand and multiplier on said first and second lines, respectively, means for effecting the removal by gating from storage of said stored digit in each stage in response to the second gating pulse on line t.sub.b means for summing and providing a carry in the summing means of each stage of those product terms a.sub.i b.sub.j where i+j=r and where k.ltoreq.r.ltoreq.2n-1, r=2n-1 for the first multiplier stage and increasing by one for each stage until r=k for the last stage, said product terms being provided to the input of said summing means from said storage means and the delayed output of the summing means of the next successive stage, means for delaying the summed product terms, a.sub.c.sup.0 j of the output of a summing means of each stage by a delay element between the output of the summing means of a stage and an input of the summing means of a preceding stage, the first multiplier stage producing at its output c.degree. the product terms c.sub.k, c.sub.k.sub.+1,---c.sub.2n.sub.-1 in serial time sequence.