1. A shifter circuit for a processor, comprising: means for obtaining a word in a processor; an inverse butterfly circuit connected to said means for obtaining the word, the inverse butterfly circuit including a plurality of circuit stages, each of the circuit stages including a plurality of multiplexers; a control circuit in communication with the inverse butterfly circuit for selectively controlling the plurality of multiplexers of the inverse butterfly circuit to perform a bit manipulation operation on the word so as to produce a processed word; and means for supplying the processed word to the processor.