1. A system for automatically generating a hierarchical register consolidation structure, comprising: a graph generator that parses a High-level Design Language (HDL) file to generate an intermediate graph containing definitions of microprocessor-accessible registers, node interrelationships and summary bits and masks associated with alarm registers; a graph converter, associated with said graph generator, that selectively adds virtual elements and nodes to said intermediate graph to transform said intermediate graph into a mathematical tree; and a description generator, associated with said graph converter, that employs said mathematical tree to generate a static tree description in a programming language suitable for use by a device-independent condition management structure.