1. A processor comprising: a common supply rail, one or more processor cores, wherein the one or more processor cores share the common supply rail and wherein each of the one or more processor cores comprises: an output for outputting a core dynamic instructions per cycle (dIPC) value and an input for inputting a core throttling signal, and a chip power management logic, wherein the chip power management logic comprises: at least one input for inputting the core dIPC value, a threshold register for registering a dIPC threshold value, a chip dIPC register for registering a current global dIPC value derived from at least one core dIPC value, at least one chip dIPC history register for registering at least one historic global dIPC value, a subtractor providing an absolute difference of an average historic global dIPC derived from the historic global dIPC value and the current global dIPC value, a magnitude comparator providing a throttling signal when the absolute difference is above the dIPC threshold value, at least one output for outputting a core throttling signal to the at least one processor core.