1. A method of latency reduction when processing floating point stores in a floating point unit having a control unit, a data input register and a write stage register from which an instruction is transferred from the floating point unit to a storage unit, said floating point unit having a plurality of pipeline stages for arithmetic computation, a normalization stage, and a rounding stage, each of which pipeline stages may during processing of a stream of instructions contain a separate instruction and wherein the stages are connected in an ordered manner such that the processing of instructions occurs in a pipeline, wherein when an active instruction of the instruction stream enters the pipeline all necessary input data operands are accessed and put into a first stage of the pipeline, whereinafter said active instruction advances from stage to stage within the pipeline as permitted by said instruction stream, and wherein an active instruction is a "stalled" instruction within a pipeline when forward progress is not permitted to advance to a new stage in the pipeline because a successive pipeline stage contains another previous instruction that itself cannot advance because said previous instruction has no data to operate on because an earlier instruction has not updated the data that said another previous instruction at said successive pipeline stage will operate upon whereupon a next active instruction will "stall" at the entrance to the pipeline until the pipeline receives the updated data, characterized by, in the case of a data dependent floating point store instruction, the steps of: providing intermediate result data from a previous instruction, and providing a forwarding path for the said data dependent floating point store instruction to skip stages in the floating point pipeline, and allowing said data dependent floating point store instruction to progress in the pipeline even though its data is dependent on a previous instruction whose execution has not yet completed; and wherein when a floating point store instruction enters the pipeline, a check is done to determine if the source operand register of the store is dependent upon the results of a previous instruction that has not yet completed and is in the pipeline and there are no intervening instructions between the floating point store instruction and the instruction that it is dependent upon; and wherein said control unit maintains information about the instructions that exist in each of the floating point pipeline stages and uses that information to form control signals to the dataflow floating point pipeline, said control unit providing control to various control points within the dataflow floating point pipeline for control of the progression of instructions through four control stages of the floating point pipeline, each control stage containing control information for a multiple instruction which may coexist within the floating point pipeline, and in the case of a store instruction with an immediate data dependency, wherein an advancement of control state in the progression of instructions through the stages allows a data dependent floating point store instruction to progress in the pipeline even though its data is dependent on a previous instruction whose execution has not yet completed by providing a late wrap path to resolve data dependent stores at the end of the pipeline, and aligning data to be stored with a data alignment circuit just before the pipeline output register, said late wrap path being controlled by an interlock resolution circuit in which interlock resolution detection occurs as the store instruction enters the pipeline, said interlock resolution circuit also providing for interlock detection for non-store instructions wherein the detection information is used to wrap results from a previous instruction in the last stage of the pipeline back through the data alignment circuit and back into the result register, and wherein instruction data is held in four control stage staging registers that are held constant during a single execution cycle, and if an instruction cannot progress to the next pipeline stage then a staging register for that pipeline stage is held constant for another execution cycle until at the end of an execution cycle said staging register either accepts a new instruction data or holds the previous value.