1. A semiconductor memory device comprising: a memory cell having a gate, a source and a drain; and a circuit configured to rewrite data in the memory cell by applying a potential difference between the gate and the source or between the gate and the drain, which is larger than a power supply voltage, the circuit operating a first data programming mode and a second programming mode; wherein a source line potential in a period when data is rewritten in the first data programming mode is a first set level; and the source line potential in a period when data is rewritten in the second data programming mode is a second set level which is different from the first set level.