1. A method implemented as a generated-clock checker tool in a programmable computing system for checking timing definitions of generated-clocks against a register-level design for an integrated circuit, the method comprising: constructing waveform models from both user-specified timing definitions and a register-level design for each generated clock; comparing, using formal methods, the two sets of constructed waveform models obtained from the timing definitions and the register-level design; and reporting any discrepancies found between the two sets of waveforms.