1. A data processing apparatus comprising: processing circuitry configured to perform data processing operations in at least a first domain and a second domain, the processing circuitry comprising exception control circuitry for controlling exception processing, wherein when operating in the first domain the processing circuitry has access to data which is inaccessible to the processing circuitry when operating in the second domain; and a plurality of registers configured to store data, the registers including a first subset of registers and a second subset of registers; wherein in response to an initial exception from background processing performed by the processing circuitry, the exception control circuitry is configured to perform state saving of data from the first subset of registers before the processing circuitry performs an exception handling routine corresponding to the exception, wherein the exception handling routine has responsibility for performing state saving of data from the second subset of registers; and in response to a first exception causing a transition from the first domain to the second domain, where the background processing was performed by the processing circuitry in the first domain, the exception control circuitry is configured to perform additional state saving of the data from the second subset of registers before the processing circuitry performs the exception handling routine in the second domain.