1. A microcontroller for controlling the bidirectional transfer of data between two external units, each of which supplies data to said microcontroller selectively on a plurality of input byte busses and receives data from said microcontroller on a plurality of output byte busses, said microcontroller having a storage device for storing instructions at individually addressable locations, each of which is executable during a single machine cycle, an ALU unit including first and second inputs and an output, and means in said ALU for selectively connecting said ALU inputs to said output in response to said instructions, and an ALU register connected to receive the output of said ALU; an instruction register decoder connected to the output of said storage device for receiving an addressed instruction; a first bus extending from the output of said ALU register through a gated driver to one input of said ALU; an input port including a plurality of input funnels each selectively connectable to one of said input byte busses and said first bus, each said funnel including a gate input and an address input; an output port including a plurality of external output registers each selectively connectable to one of said output byte busses and said output of said ALU register, each said external register having a gate input and an address input; means connecting said decoder to said funnels and said registers to selectively simultaneously address one of each; and control means connected to said gate inputs, said gated driver, said decoder, said ALU and said ALU register to cause the transfer of a byte of data from an addressed funnel through said ALU to said ALU register during a first portion of a machine cycle and from said ALU register to said addressed register during a second portion of said machine cycle whereby an instruction read out from said storage unit to said decoder establishes a first data path during a first portion of said machine cycle between an addressed external funnel and said ALU register to transfer data thereto during said first portion of said machine cycle and a second data path from the output of said ALU register to said addressed register during said second portion of said machine cycle to transfer data from the output of said ALU register to said external register during said second portion of said machine cycle.