1. A processor comprising: logic to determine whether to execute a first instruction at a first stage of a plurality of stages or at a second stage of the plurality of stages later than the first stage; a schedule unit to schedule the first instruction for execution at the second stage based on a determination by the logic that a next sequential instruction needs a result of the first instruction at the second stage; and the schedule unit to schedule the first instruction for execution at the first stage based on a determination by the logic that the source for the first instruction is to be ready at the first stage, or that the next sequential instruction needs the result of the first instruction at the first stage.