1. An encryption circuit that generates from a cipher key a plurality of round keys having a number of bits corresponding to a predetermined processing block length and executing, for each processing block length, input data and round key encryption/decryption processing, by means of a round function unit comprising an XOR operation unit that XORs the input data and one of the round keys and a round processing unit that iterates round processing that includes Byte Sub transformation, Shift Row transformation, Mix Column transformation and Round Key Addition, wherein: said round processing unit comprises: a first selector that segments input data into execution block lengths smaller than said processing block length; a first Round Key Addition circuit that adds said round key value to input data for each said execution block length; an intermediate register/Shift Row transformation circuit that temporarily stores the output of said first Round Key Addition circuit and executes Shift Row transformation using said processing block length; a Byte Sub transformation circuit wherein said intermediate register/Shift Row transformation circuit value is inputted for each said execution block length and Byte Sub transformation is executed; a second Round Key Addition circuit wherein said intermediate register/Shift Row transformation circuit value is inputted for each said execution block length and said round key value is added for each said execution block length; a Mix Column transformation circuit executing Mix Column transformation on the output of said second Round Key Addition circuit; and a second selector that outputs to said first Round Key Addition circuit one output from among the outputs of said first selector, intermediate register/Shift Row transformation circuit, Byte Sub transformation circuit, or Mix Column transformation circuit.