1. An apparatus comprising: a memory configured to store a plurality of context variables; and a circuit configured to (i) generate a select signal that identifies a prediction of a plurality of next states in each of a plurality of next cycles that follow a current cycle of an arithmetic decode of an input signal, (ii) generate a prefetch signal in said current cycle in response to said select signal, (iii) prefetch in parallel from said memory two or more of said context variables suitable to use in said next states in two or more of said next cycles based on said prefetch signal and (iv) generate an output signal by decoding said input signal based on said two or more of said context variables.