1. A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: using a machine: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector.