1. An error detection system for a memory comprising: a memory block for storing a data word and a corresponding row parity bit; a local data I/O circuit for coupling the data word between the memory block and global datalines and for providing the corresponding row parity bit; and, a row parity circuit including a serial parity chain for receiving the data word from the local data I/O circuit and for providing a parity output corresponding to parity of the local data, and a sense circuit for receiving the parity output and the corresponding row parity bit, for providing an active local parity fail flag if the logic state of the parity output and the logic state of the local row parity bit mismatch.