1. Apparatus for processing data comprising: a plurality of registers configured to store data values to be processed; processing circuitry coupled to said plurality of registers and configured to perform data processing operations upon data values stored in said plurality of registers; an instruction decoder coupled to said processing circuitry and responsive to a stream of program instructions to control said processing circuitry to perform said data processing operations; wherein said instruction decoder is responsive to program instructions of a first instruction set to control said processing circuitry to perform said data processing operations using N-bit architectural registers provided by said plurality of registers, where N is a positive integer value; said instruction decoder is responsive to program instructions of a second instruction set to control said processing circuitry to perform said data processing operations using M-bit architectural registers provided by said plurality of registers, where M is a positive integer value and at least some of said plurality of registers are shared by program instructions of said first instruction set and program instructions of said second instruction set; said instruction decoder is configured to decode a register specifying field within a program instruction of said first instruction set when determining which of said plurality of registers to access as part of a first set of N-bit architectural registers presented for use by program instructions of said first instruction set; said instruction decoder is configured to decode a register specifying field within a program instruction of said second instruction set when determining which of said plurality of registers to access as part of a second set of M-bit architectural registers presented for use by program instructions of said second instruction set; and said instruction decoder is configured to provide a first mapping between values of said register specifying field within program instructions of said first instruction set and said plurality of registers and a second mapping between values of said register specifying field within program instructions of said second instruction set and said plurality of registers, said first mapping being different to said second mapping and said first mapping and said second mapping being such that each register of said first set has a predetermined one-to-one mapping to a register of said second set, shares with said register of said second set a shared part of a common register within said plurality of registers, an unshared part of said common register being unaccessible using instructions of said first instruction set, and stores a value that is accessible using a register of said second set.