1. A memory device comprising: a first dielectric layer disposed on a substrate; a charge trapping trapping layer disposed on the first dielectric layer; a second dielectric layer disposed on the charge trapping layer; a bit line layer formed in the substrate in spaces in which portions of the second dielectric layer, the charge trapping layer, and the first dielectric layer are absent; a silicide formed in the bit line layer, the silicide having lateral edges defined by the charge trapping layer; and a bit line oxide disposed over the second dielectric layer, the bit line oxide exposing the bit line layer.