1. A neuroprocessor comprising at least one synapse chip formed as a matrix of synapse nodes and comprising a plurality of voltage inputs and a plurality of current outputs, each such synapse node comprising a voltage-to-current converter, a two-quadrant multiplying digital-to-analog converter, a plurality of static weighting latches and a current steering circuit; a synapse-neuron composite chip comprising one said synapse chip in which a diagonal line of synapse nodes within said matrix of synapse nodes is replaced by a plurality of neurons; a thresholding comparator having a sigmoidal function to input currents, a current-to-voltage converter and a variable-gain voltage amplifier circuit for adjusting said sigmoidal function; wherein said synapse chip and said synapse-neuron composite chip are connected in a parallel cascaded configuration wherein output current variation of the synapse-neuron composite chip is added to an output current variation of the synapse chip to provide a combined resolution commensurate with a sum of resolutions of both chips.