1. An apparatus for performing bus tracing in a data processing system having a distributed memory coupled to an interconnect, said apparatus comprising: a plurality of memory controllers coupled to said interconnect; a plurality of multiplexors; and a plurality of bus trace macro (BTM) modules, each connected between said interconnect and a respective one of said memory controllers via at least two of said plurality of multiplexors, wherein a subset of said BTM modules is enabled for performing tracing operations such that address transactions from said interconnect are divided among said subset of said BTM modules to be selectively and separately intercepted by each of said subset of said BTM modules.