1. A computer-implemented method for assuring a reliability of a chip comprising: verifying a parity with a processor; traversing, via the processor, a netlist back from a plurality of netlist outputs; identifying, via the processor, one or more parity protected structures and one or more gates, wherein protected parity structures comprises a duplication protection; and generating, via the processor, a driver based on a logic structure and an assertion indicative of a parity validity.