1. In a logic simulation system, a reconfigurable interconnect network comprising: a plurality of groups of simulation processors having a plurality of outputs; for each of the groups of simulation processors, a corresponding one of a plurality of first reconfigurable interconnect stages each having a plurality of inputs coupled to the outputs from only the corresponding group of simulation processors, and further having a plurality of outputs; for each of the first reconfigurable interconnect stages, a corresponding one of a plurality of second reconfigurable interconnect stages each having a plurality of inputs coupled to a first subset of the outputs from only the corresponding first reconfigurable interconnect stage, and further having a plurality of outputs, wherein a first subset of the outputs from each second reconfigurable interconnect stage are coupled to a first subset of the inputs of only the corresponding first reconfigurable interconnect stage via a plurality of feedback paths; a third reconfigurable interconnect stage having a plurality of inputs coupled to a second subset of the outputs from the second reconfigurable interconnect stages, wherein the plurality of feedback paths each couples one of the outputs of the second reconfigurable interconnect stages to one of the inputs of the first reconfigurable interconnect stages without passing through the third reconfigurable interconnect stage; and memory, wherein the reconfigurable interconnect network is configured to dynamically re-configure the first, second, and third reconfigurable interconnect stages in accordance with a content of the memory.