1. An apparatus for mapping instructions in a data processing system to resolve dependencies in an original register assignment such that Write-After-Write (WAW) and Read-After-Write (RAW) dependencies are eliminated in an output mapped instructions, thereby permitting issuance of the output mapped instructions in any order relative to each other, the apparatus comprising: means for maintaining a logical register list having entries, each entry corresponding to each of a plurality of physical registers, each entry indicating a possible assignment of a logical register to a physical register, means for maintaining a valid vector, the valid vector having a number of bits corresponding to the plurality of physical registers, the bits of the valid vector indicating, together with the logical register list, a list of valid and invalid logical to physical register assignments, with logical false bits indicating a corresponding invalid logical register to physical register assignments, and logical true bits indicating a corresponding valid logical register to physical register assignments; means for obtaining an instruction to be mapped, the instruction including potentially source operands and destination operands; and means for mapping the instruction, the means for mapping examining the instruction to be mapped to determine whether each of the source operands includes a reference to a logical register, and if the instruction to be mapped includes logical source operand, the means for mapping also including replacing the logical source operand with a physical source operand by examining existing register assignments stored in the logical register list and their associated bits of the valid vector; if the instruction to be mapped includes a logical destination operand, the means for mapping also actuating: means for identifying a new logical register assignment from the existing register assignments stored in the logical register list and the valid vector; means for replacing the logical destination operand with a physical destination operand that identifies a physical register to which the identified new logical register is assigned; means for locating an entry in the logical register list previously assigning the referenced logical register to another physical register, and clearing a corresponding bit in the valid vector to a false state, in order to invalidate that previous assignment; and means for selecting an unused entry in the logical register list and setting contents of that selected entry to identify the new logical register, and thus considering the new logical register to be assigned to the physical register corresponding to the selected entry; and means for storing, for an instruction that is mapped, a copy of the valid vector to a vector silo memory.