1. A microprocessor, comprising: processor logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction; and sparse write logic, coupled to said processor logic, which causes said processor logic to provide one of a plurality of sparse memory write transactions on said request signals and to provide a corresponding plurality of enable bits on said address signals; wherein each of said plurality of sparse memory write transactions corresponds with one of a plurality of granularities of data.