1. A disk subsystem, comprising: a first cache board which comprises a first memory controller connected to a first volatile memory, a first shared memory, and a first non-volatile memory, respectively, a first processor which is connected to the first memory controller, and a first battery which temporarily supplies power when power is shut off; a second cache board which comprises a second memory controller connected to a second volatile memory, a second shared memory, and a second non-volatile memory, respectively, a second processor which is connected to the second memory controller, and a second battery which temporarily supplies power when power is shut off; and a transmission channel which communicably connects the first cache board and the second cache board, wherein, if power which is supplied to the first cache board is shut off, the first processor saves data which is stored in the first volatile memory to the first non-volatile memory and saves first management information for managing data which is stored in the first shared memory to the first non-volatile memory, by way of co-operation with the first memory controller while power is being supplied from the first battery, wherein, if power which is supplied to the first cache board is restored, the first processor restores first data among data which has been saved to the first non-volatile memory and second data which has been transferred via the transmission channel, to the first shared memory, on the basis of the first management information and transfers the first data to the second cache board via the transmission channel, by way of co-operation with the first memory controller, wherein, if power which is supplied to the second cache board is shut off, the second processor saves data which is stored in the second volatile memory to the second non-volatile memory and saves second management information for managing data which is stored in the second shared memory to the second non-volatile memory, by way of co-operation with the second memory controller while power is being supplied from the second battery, wherein, if power which is supplied to the second cache board is restored, the second processor restores the second data among data which has been saved to the second non-volatile memory and the first data which has been transferred via the transmission channel, to the second shared memory, on the basis of the second management information and transfers the second data to the first cache board via the transmission channel, by way of co-operation with the second memory controller, wherein the first processor determines, based on a predetermined conflict avoidance rule, whether data restoration is complete corresponding to a first order ranking, and on a condition that data restoration is not complete corresponding to the first order ranking, the first processor restores data corresponding to the first order ranking, and on a condition that the data restoration is complete corresponding to the first order ranking, the first processor determines, based on the predetermined avoidance rule, whether data restoration is complete corresponding to a second order ranking, and on a condition that data restoration is not complete corresponding to the second order ranking, the first processor restores data corresponding to the second order ranking, and on a condition that the data restoration is complete corresponding to the second order ranking, the first processor determines, based on the predetermined avoidance rule, whether data restoration is complete corresponding to a third order ranking, and on a condition that the data restoration is not complete corresponding to the third order ranking, the first processor restores data corresponding to the third order ranking, and on a condition that the data restoration is complete corresponding to the third order ranking, the first processor determines, based on the predetermined conflict avoidance rule, whether data restoration is complete corresponding to a fourth order ranking, and on a condition that data restoration is not complete corresponding to the fourth order ranking, the first processor restores data corresponding to the fourth order ranking, and on a condition that the data restoration is complete corresponding to the fourth order ranking, the fourth processor ends processing.