1. A circuit for testing a data memory, comprising: a processing unit connected to the data memory, said processing unit applying a first function to a predetermined test pattern for generating therefrom data items to be written to the data memory, said processing unit reading the data items from the data memory and applying a second function to the data items read from the data memory for generating therefrom test data items; wherein the second function is a reciprocal function of the first function and a number of the data items is greater than a number of test data items; and a test device connected to and outputting to said processing unit function data items defining the first function and the second function for said processing unit.