1. In a communications system having an origination storage device and a destination storage device, a data transfer pipeline apparatus for transferring data in a sequence of N stages, where N is a positive integer grater than 1, from said origination to said destination device, comprising: dedicated memory means having a predetermined number of buffers dedicated for carrying data associated with the transfer of data from said origination storage device to said destination device; and master control means for registering and controlling processes associated with said data transfer apparatus for participation in the N stage data transfer sequence, wherein said processes include at least a first stage process for initiating said data transfer and a last Nth stage process for completing data transfer, wherein said first stage process is operative to allocate a buffer from said predetermined number of buffers available within said dedicated memory means for collection, processing, and sending of said data from said origination device to a next stage process; and wherein said last Nth stage process is operative to receive a buffer allocated to said first stage process from the (N−1)th stage process in the data transfer sequence and to free said buffer upon processing completion and storage in the destination device to permit reallocation of said buffer, said master control means further including monitor means for monitoring the number of buffers from said pool of buffers allocated or assigned to particular processes in said pipeline, wherein said monitor means is operative to prevent allocation of further buffers to a particular process when said number of buffers currently allocated exceeds a predetermined threshold.