1. A processing machine comprising: an array having at least two processing elements (PEs), each of said PEs needing only a single send-receive port and a sequence processor (SP); a connection mechanism for interconnecting the PEs comprising at least one cluster switch and at least one multiplexer per processing element; a PE communication instruction which may be utilized to encode interconnection paths for communication between individual PEs; and combinatorial hardware to interpret the PE communication instruction and appropriately select a single PE for data to be received by.