1. A microprocessor apparatus for performing a pop-compare operation, comprising: paired operation translation logic, for receiving a macro instruction that prescribes the pop-compare operation, and for generating a pop-compare micro instruction, wherein said pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation; load logic, coupled to said paired operation translation logic, for receiving said pop-compare micro instruction, and for retrieving a first operand from an address in memory, wherein said address is specified by contents of a register, said register being prescribed by said pop-compare micro instruction; and execution logic, coupled to said load logic, for receiving said first operand, and for comparing said first operand to a second operand.