1. A computer-implemented method for optimizing design layout of an integrated circuit, comprising: receiving, via a processor of a system for optimizing design layout of an integrated circuit, a design layout of the integrated circuit from a design layout tool module; receiving an identification of a critical pitch in the design layout from a user using a critical pitch and rules forming design arc identification module through a graphical user interface; searching design rules forming design arc limited by the critical pitch from a plurality of design rules associated with the design layout; extracting, via a process variation and failure mechanism extraction module, a process variation and a plurality of failure mechanisms of the design layout based on the critical pitch and rules forming design arc identified; performing, via a layout based ground rule calculation module, layout based ground rule calculation based on the process variation and the plurality of failure mechanisms extracted; determining, via the layout based ground rule calculation module, whether wafer risks exist in the design layout; responsive to determining the wafer risks exist in the design layout, revising, via a design layout refinement module, the design layout, and performing additional layout based ground rule calculation after the revision; and responsive to determining the wafer risks do not exist in the integrated circuit design layout, outputting, via a layout bases ground rules calculation results output module, an optimized integrated circuit design layout.