1. A microprocessor comprising: decode logic to decode a first and a second instruction, wherein the first instruction has a reference to a linear address and the second instruction has a reference to a first physical address; a linear address to physical address translator to translate the linear address to a second physical address and to provide a representation of the second physical address to interface logic; and physical addressing logic to store a first memory type and to provide a representation of the first physical address to the interface logic.