1. An integrated circuit comprising: at least one active memory circuit; at least one variable resistance state retention circuit operatively coupled to the at least one active memory circuit and operative to save complimentary state information from the at least one active memory circuit; and wherein the at least one variable resistance state retention circuit comprises: at least one variable resistance cross coupled configured state retention circuit, operatively coupled to the at least one active memory circuit, comprising: a plurality of passive variable resistance memory (PVRM) cells in a cross coupled configuration; and control logic operatively coupled to the plurality of passive variable resistance memory (PVRM) cells in a cross coupled configuration, and operative to save state information from the at least one active memory circuit to the plurality of passive variable resistance memory (PVRM) cells in the cross coupled configuration and to restore the stored state information from the plurality of passive variable resistance memory (PVRM) cells to the active memory by configuring the plurality of passive variable resistance memory (PVRM) cells in a voltage divider configuration.