1. A processor chip, comprising: a processing core; at least one bank of DRAM memory; an I/O link configured to communicate with other like processor chips or compatible I/O devices; and a communication and memory controller in electrical communication with said processing core, said at least one bank of DRAM memory, and said I/O link; said communication and memory controller configured to control the exchange of data between said processor chip and said other processor chips or I/O devices, and said communication and memory controller configured to receive memory requests from said processing core and from said other processor chips via said I/O link, and process said memory requests with said at least one bank of DRAM memory.