1. A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; and erase circuitry coupled to selectively erase either a main erase block of the array or an erase sub-block of the array, wherein the main erase block comprises rows of the memory array that cross all of the array columns, and wherein the erase sub-block comprises rows of the memory array that cross only a portion of the array columns, wherein the memory cells have a location address, wherein the location addresses of the memory cells located in a single row of the array rows are contiguous, such that the main erase block comprises contiguous memory cell location addresses, and the erase sub-block comprises non-contiguous memory cell location addresses.