1. An apparatus comprising: a logic circuit configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal; a compare circuit configured to generate a compare signal in response to said check signal and said data signal; a control circuit configured to generate (i) said first control signal and (ii) a second control signal indicating a valid or invalid status of each of said LTUs, in response to a data valid signal and said compare signal; and a memory interface configured to generate an output data signal in response to said second control signal, wherein said memory interface stores only said LTUs having said valid status.