1. A monolithic programmable semiconductor memory comprising a semiconductor chip, a plurality of electrically conductive paths arranged in rows on said chip, a plurality of electrically conductive paths arranged in columns on said chip, a plurality of electrically permanently alterable devices each having a current voltage characteristic prior to permanent alteration different from the current voltage characteristic subsequent to alteration each device being connected between a row path and a column path forming a matrix of permanently alterable devices, means responsive to a code for permanently altering selective devices, means on said chip for sensing the altered and non-altered condition of the device, and wherein each of said devices comprises a section of a semiconductor chip including conductivity regions forming a PN junction by a washed emitter process close to a window one path connected to one region and the other path connected to another region on the other side of said junction, and a free metal piece electrically and physically contacting one region on one side of said junction but out of contact with said paths, and overlying one edge of said window and said one region.