1. A multi-clock single-instruction stream, multiple-data stream (SIMD) computer comprising: a global instruction broadcast subsystem regulated by a system clock signal oscillating at a system clock rate; a multi-chip subsystem (MCS) regulated by second clock signal; and a processing element (PE) module coupled to said global instruction broadcast subsystem and to said MCS, said PE module implemented on a single chip and including: a first internal subsystem regulated by a third clock signal: a second internal subsystem regulated by a fourth clock signal; and a multi-clock generating circuit, responsive to said system clock signal, for generating a plurality of clock signals including said second, third, and fourth clock signals, wherein one of said third and fourth clock signals is a PE module clock signal oscillating at a PE module clock rate higher than said system clock, and wherein said second clock signal oscillates at a MCS clock rate higher than said system clock rate but no higher than said PE module clock rate.