1. A cryptography accelerator, comprising: a plurality of input ports; a data input unit input controller coupled to the plurality of input ports, the data input unit input controller configured to write data blocks from the plurality of input ports into an input buffer and write entries corresponding to the data blocks into a buffer pointer table; policy security association lookup circuitry configured to receive header information and determine policy and security association information associated with the data blocks, wherein the policy and security association information is forwarded with the data blocks to cryptographic processing cores.