1. In a microcoded data processing system, said system providing for register-to-register operations and for memory-to-register operations, said system permitting common microcode execution routines to be employed in processing means operating on memory operands and register operands after effective address calculations for said operands; said system including: memory means for storing memory operands to be used in said memory-to-register operations; a plurality of separately addressable general purpose registers for storing register operands to be utilized in said register-to-register operations; first address register means for generating the address of a first of said general purpose registers containing one of said operands for one of said register-to-register operations; second address register means for generating the address of a second of said general purpose registers containing another of said operands for said one of said register-to-register operations; a memory data register for storing one of said memory operands for use in one of said memory-to-register operations, said memory data register having its own address designation; means responsive to initiation of a register-to-register operation for utilizing the addresses generated by said first and said second address register means to select those of said general purpose registers whose operands are to be utilized in said register-to-register operation; means for supplying said operands from said selected registers to said processing means; means responsive to initiation of a memory-to-register operation for causing said address designation of said memory address register to be generated by said second address generating means; means responsive to generating of said memory data register address designation for supplying one of said memory operands from said memory means to said memory data register; and means for supplying operands from said memory data register and the one of said general purpose registers selected by said first address generating means to said processing means; whereby said register-to-register operations and said memory-to-register operations can share common microcode execution routines.