1. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising: a static random-access-memory cell coupled between first and second complimentary static random-access-memory cell bit nodes; a static random-access-memory cell word line; first and second complimentary static random-access-memory cell bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through first and second access transistors, each of the first and second access transistors having a gate coupled to the static random-access-memory cell word line; a configuration word line; first and second complimentary configuration bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through third and fourth access transistors, each of the third and fourth access transistors having a gate coupled to the configuration word line; a serial shift register stage having first and second complementary clock lines, said serial shift register stage coupled to the first and second complimentary static random-access-memory cell bit nodes; a non-volatile memory cell having an output; a complementing transistor coupled to the output of the non-volatile memory; a first transistor switch coupled between the output of the non-volatile memory cell and the first static random-access-memory cell bit node, the first transistor switch having a gate; a second transistor switch coupled between the output of the complementing transistor and the second static random-access-memory cell bit node, the second transistor switch having a gate; a control circuit coupled to the gates of the first and second transistor switches.