1. A shared memory device comprising: a plurality of processor elements; a plurality of memory modules configured to be accessible by said plurality of processor elements; and a connection device configured to enable a specific processor element out of said plurality of processor elements to access a specific memory module out of said plurality of memory modules; wherein said plurality of processor elements are allowed to access via said connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of said plurality of memory systems accessible by different processor elements allows said plurality of memory modules to be partially shared and accessed by said different processor elements.