1. A method comprising: providing an implanted substrate including an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region; forming a doped band engineered p-type field effect transistor (PFET) threshold voltage (Vt) work function tuning layer over the PMOS region only; forming a high dielectric constant layer over the implanted substrate; forming an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; forming a metal layer over the NFET Vt work function tuning layer; and patterning a first gate over the NMOS region and a second gate over the PMOS region, the second gate including the doped band engineered PFET Vt work function tuning layer and the NFET Vt work function tuning layer over the PMOS region.