1. A method for validating a processor design by simulating program execution, comprising the steps of: identifying a resource that may be accessed by a test program that includes a first simulated process and a second simulated process; associating a set of non-unique values for said resource; executing said test program by the steps of: executing a first sequence of instructions in said first simulated process; and while performing said step of executing said first sequence, executing a second sequence of instructions in said second simulated process; wherein said resource is accessed by at least one of said first simulated process and said second simulated process, and wherein upon completion of said steps of executing said first sequence and executing said second sequence, a member of said set of non-unique values is required to be present in said resource; and verifying an equality between a content of said resource and a member of said set of non-unique values.