1. A data processing apparatus comprising: SIMD data processing circuitry, responsive to control signals, configured to perform data processing operations in parallel on multiple data elements; A SIMD register bank configured to store the data elements for access by the SIMD data processing circuitry; instruction decoder circuitry, coupled to said SIMD data processing circuitry and responsive to program instructions, configured to generate said control signals; said instruction decoder circuitry, responsive to a repeating multiply-accumulate (repeating MAC) instruction having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations M required, configured to generate corresponding control signals to control said SIMD data processing circuitry, said vectors stored in said SIMD register bank; said SIMD data processing circuitry, responsive to said corresponding control signals, configured to perform said plurality of iterations of a multiply-accumulate process, each iteration of the multiply-accumulate process comprising performing N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements; for each iteration, said SIMD data processing circuitry, responsive to said corresponding control signals, configured to determine N input data elements from said first vector and a single coefficient data element from said second vector to be multiplied with each of the N input data elements during the N multiply-accumulate operations; and said SIMD data processing circuitry, responsive to said corresponding control signals, configured to output N multiply-accumulate results derived from the N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process; said SIMD data processing circuitry configured to access said first and second vectors from registers of the SIMD register bank prior to performing said plurality of iterations of the multiply-accumulate process, whereby no further access to the SIMD register bank is required in respect of the first and second vectors during performance of said plurality of iterations of the multiply-accumulate process; and the SIMD data processing circuitry including a state machine for generating further control signals used to control circuitry within the SIMD data processing circuitry to select the N input data elements and the single coefficient data element for each iteration.