1. A memory circuit comprising: a plurality of magnetic tunnel junction (MTJ) stacks forming a corresponding plurality of magnetic storage elements in the memory circuit, wherein each of the plurality of MTJ include: a tunnel oxide layer between a free layer and a fixed layer; and a stress inducing layer disposed above the free layer, wherein: a first free layer of a first MTJ stack of the plurality of MTJ stacks is stressed to a first extent by a first stress inducing layer of the first MTJ stack; a second free layer of a second MTJ stack of the plurality of MTJ stacks is stressed to a second extent by a second stress inducing layer of the second MTJ stack; and the first extent and the second extent are different.