1. A fast Fourier transform (FFT) operating apparatus to carry out a FFT operation in a programmable processor chip, comprising: a program controller to generate a FFT start signal and control a programmable processor; a program memory to store an application of the programmable processor; an FFT address generator to remove a looping instruction used for the FFT and a cycle for an address generation, and generate an offset address of a butterfly input data and an operation stop signal; an address generator to calculate an address of a data memory using the offset address generated in the FFT address generator; a data memory to store a data; a data processor to carry out an arithmetic and logic operation using the data stored in the data memory; and a flag register to generate a FFT operation signal.