1. A hardware logic system for communications among tasks of a software program, the system comprising: a collection of source task specific buffers for buffering communication units, called packets, directed to a given task, referred to as a destination task, of the program; and hardware logic for selecting a buffer among the collection of buffers from which to transfer a next packet to the destination task, with the selecting done at least in part based on a priority rank for each of the buffers, wherein the priority rank for a given one of the buffers is based at least in part on a prioritization of a source task that the source buffer is specific to, with the prioritization assigned by the destination task.