1. A memory architecture comprising: a NAND Flash memory; and a serial peripheral interface (SPI) to couple said memory to a host device, said SPI comprising a data in line to supply output data from the host device to inputs of said memory, a data out line to supply output data from said memory to an input of the host device, a clock line to be driven by the host device, and an enable line to allow said memory to be turned on and off by the host device, said serial peripheral interface to detect an edge transition of a clock signal on said clock line and an active signal on said enable line, and in response to said edge transition and said active signal, and only in response thereto, beginning a new command transaction.