1. A synchronous data processor having a source of synchronizing clock pulses and multiple paths for processing instructions and data comprising an instruction path including a chain of instruction registers including a first and a last instruction register with all of said instruction registers coupled in cascade, said instruction path including a plurality of stages with each register constituting a stage of the instruction processing path through which all instructions are stepped in response to each of said synchronizing clock pulses, each stage including instruction decoding means coupled to the corresponding instruction register for decoding operation codes in said instructions and providing control signals, and a data processing path having a plurality of stages coupled to respond to selected control signals from corresponding stages in said instruction path and including an input stage and an output stage at the beginning and end of said data processing path, and at least one intermediate stage between said input and output stages, said input stage having a plurality of inputs independently receiving data.