1. A data processing apparatus comprising: processing circuitry for executing multiple program threads including at least one high priority thread and at least one lower priority thread; a cache memory hierarchy comprising multiple cache levels for storing instructions required for said program threads; responsive to the processing circuitry issuing an access request specifying an address of an instruction required for one of said program threads, the cache memory hierarchy performing a lookup procedure to determine if that instruction is stored within the cache memory hierarchy; and said cache memory hierarchy having a bypass path for omitting a predetermined level of said cache memory hierarchy from said lookup procedure and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry, said bypass path being used by default when said access request is for an instruction required for said at least one lower priority thread.