1. In a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, an exception handling system using the valid bits prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception comprising: prefetch logic including exception detection logic that determines, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, the prefetch logic stores the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and provides corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; and exception logic that monitors the prefetch logic, and stores exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, the exception logic detects the stall condition, and determines whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking the stored instruction status information; if the stall condition resulted from an exception condition, the exception logic causes an associated exception handling routine to be invoked.