1. A method for designing a system to be implemented on a target device, comprising: generating an intermediate representation of the system from a description provided by a designer; identifying an adder from the intermediate representation of the system before the intermediate representation of the system is transformed into a register transfer level (RTL) description; and designating components on the target device to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result, wherein at least one of the generating, identifying, and designating procedures are performed by a processor.