1. A method of performing RTL testability analysis for checking scan rule violations in an integrated circuit modeled at RTL (register-transfer level), the integrated circuit having a plurality of clock domains and each domain having one scan clock; said method comprising the computer-implemented steps of: (a) compiling the HDL (hardware description language) code that represents said integrated circuit at RTL into a design database; (b) receiving scan constraints from an external source, said scan constraints further comprising a list of scan clocks; and (c) based on said scan constraints, analyzing said design database and reporting all said scan rule violations including one or more of the following: generated set/reset signals, destructive set/reset signals, combinational gated set/reset signals, sequential gated set/reset signals, potential bus contention on tri-state busses, generated clocks, constant clocks, clocks connected to data inputs of storage elements, combinational gated clocks, sequential gated clocks, pulse generators, and potential combinational feedback loops.