1. A method of implementing hardware security in an electronic device, comprising: storing, within a memory of the electronic device, a support vector model which is derived from verification data to define secure behavior for a first circuit on the electronic device; monitoring signals associated with the first circuit with a runtime classifier hardware circuit on the electronic device which compares the signals to the support vector model, thereby detecting an outlier signal for the first circuit; and blocking the outlier signal from being input to or output from the first circuit.