1. A memory, comprising: an array of memory cells coupled to pairs of bit lines and word lines; column logic coupled to the array for coupling a selected pair of bit lines to a pair of data lines; a write driver coupled to the pair of data lines; a voltage detector that provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver; and a bootstrap circuit that reduces the voltage of a first data line in response to the boost enable signal.