1. A single-instruction, multiple-data processor having a register file that may be dynamically reconfigured, said single-instruction, multiple-data processor comprising: a controller; a plurality of registers coupled to said controller and arranged in an array having a configuration of N rows of M columns of said registers, where N and M are integers; means for storing a vector size, VS, within said controller, wherein said vector size specifies a number of said plurality of registers comprising a vector register, where VS is an integer less than M multiplied by N; means, responsive to said vector size, for selecting selected ones of said M columns to form said vector register having at least VS registers; and means for performing a vector operation utilizing data stored in said vector register.