1. A processor system made to carry out a plurality of threads, each having one or more instructions, in parallel through the use of one or more arithmetic units, comprising: a multithread control unit for selectively making switching among said threads to be executed in said arithmetic unit; a loop predicting unit for predicting a loop of an instruction string on the basis of a processing history of a branch instruction in said thread; and a loop detecting unit for, when said loop predicting unit predicts said loop, detecting said loop on the basis of said instruction, when said loop detecting unit detects said loop, said multithread control unit making the switching from said thread, which is in execution in said arithmetic unit, to a different thread.