1. A flexible, hardware programmable, scalable, and reconfigurable parallel processor (parallel processor), comprising: a plurality of parallel processing units each including: a processing engine including one or more processing elements configured to process input data samples; one or more Mux Delay Dual-Port Random Access Memory (MDDP-RAM) blocks; and one or more parameter blocks; wherein the parallel processing units are connected together to perform processing functions; and wherein each of the MDDP-RAM blocks comprises: an input multiplexer having an input coupled to multiple first input buses; an input register having an input coupled to an output of the input multiplexer; a dual-port-random access memory (DP-RAM) having an input coupled to an output of the input register; an output multiplexer having an input coupled to multiple second input buses; and an output register having an input coupled to an output of the output multiplexer.