1. A processor comprising: a first physical core, having a first instruction set and a first power consumption level, to execute a thread at a first performance level, wherein the first physical core is to act as a bootstrap processor; a second physical core, having a second instruction set and a second power consumption level, to execute a thread at a second performance level, the first and second cores being in a dynamic multi-core unit; a third physical core having the first instruction set and the first power consumption level; and a virtual-to-physical (V-P) mapping circuit, coupled to the first, second, and third physical cores, to map the first and third physical cores to a system firmware interface via a first and second virtual core respectively and to hide the second processor core from the system firmware interface and an operating system, wherein after the second physical core has performed an initialization sequence it enters a masked power state in which the second processor core is placed into a low power state and it not accessible by system triggers, and wherein the first and third physical cores are accessible by system triggers.