1. A memory controller comprising: (a) an encoder for encoding K information bits as a codeword of N>K codeword bits; and (b) a decoder including: (i) a read/write memory; and (ii) at least one processor for decoding the representation of the codeword by executing an algorithm for, in a graph that includes N bit nodes and N−K check nodes, each bit node being connected to at least one check node by a respective edge, there being E edges in total, exchanging messages between the bit nodes and the check nodes that are so connected to each other, while storing fewer than E of the messages in the read/write memory at any time during the exchanging of the messages.