1. A data storage device comprising: a memory cell array including a plurality of memory cells, each memory cell having one or more data states; a row decoder applying program pulses and verification pulses to selected memory cells via a word line, wherein the row decoder performs on the selected memory cells a plurality of program loops based on an incremental step pulse program (ISPP) algorithm; a memory cell counting circuit coupled to the memory cell array via one or more bit lines, wherein the memory cell counting circuit determines data states of the selected memory cells in response to the verification pulses, counts a number of programmed memory cells or a number of unprogrammed memory cells, and generates a count result; a program loop turn detector that receives the count result and detects a turn value of a program loop based on the count result; a comparing circuit that generates a comparison result by receiving the count result and comparing the count result to a set value; and a control logic that controls the row decoder, the memory cell counting circuit, and the comparing circuit, wherein the control logic further controls the plurality of program loops by performing at least two memory cell counting operations and an expected turn value of the program loop, each memory cell counting operation includes one or more program loops in which the memory cell counting circuit counts the number of programmed memory cells or the number of unprogrammed memory cells, and wherein the control logic determines a program pass or a program fail by detecting abnormally slow memory cells, abnormally fast memory cells, or a page including the abnormally slow memory cells or abnormally fast memory cells based on the comparison result.