1. A computer-implemented method for verifying a design of an electronic circuit including a register, the method comprising: receiving specification information of a register, said specification information comprising information regarding the parts included in the register; automatically generating a register monitor module based on said received specification information, said register monitor module comprising a scoreboard for each part of the register, said scoreboard comprising an expected data value queue for receiving expected data values which are expected to be included in the respective part of the register and an actual data value queue for receiving actual data values actually included in the respective part of the register, the register monitor module further including a matching strategy for comparing expected data values with actual data values; calculating expected data values using a reference model of the electronic circuit and providing said expected data values to the expected data value queue of the respective scoreboard; calculating actual data values using a simulation environment simulating the electronic circuit and providing said actual data values to the actual data value queue of the respective scoreboard; comparing, for each scoreboard, the values of the expected data value queue with the values of the actual data value queue based on the matching strategy; and generating an error indication if the result of the comparison step does not fulfill the requirements specified in the matching strategy.