1. An apparatus comprising: a queue comprising a plurality of entries; a control unit coupled to the queue, wherein the control unit is configured to allocate a first entry of the plurality of entries to a store memory operation, wherein the control unit is configured to write a first base address, a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry, and wherein the control unit is coupled to receive an input base address, an input even offset, and input even mask, an input odd offset, and an input odd mask that each correspond to a load memory operation, wherein the control unit is configured to determine if the store memory operation writes at least one byte read by the load memory operation responsive, at least in part, to the first base address, the first even offset, the first even mask, the first odd offset, the first odd mask, the input base address, the input even offset, the input even mask, the input odd offset and the input odd mask, and if the control unit determines that the store memory operation writes at least one byte read by the load memory operation by comparing the input base address, the input even offset, the input even mask, the input odd offset and the input odd mask to the first base address, the first even offset, the first even mask, the first odd offset and the first odd mask, respectively, the control unit is configured to signal a hit on the store memory operation; wherein a group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges, wherein a number of bytes in each byte range is an integer greater than one, and wherein a given store memory operation writes at most one even byte range and one adjacent odd byte range, and wherein a given store memory operation writes at least one of the even byte range and the adjacent odd byte range, and wherein at least one given store memory operation writes at least one byte in each of the even byte range and the adjacent odd byte range; wherein the first even offset identifies a first even byte range in the group of contiguous memory locations that is potentially written by the store memory operation and the first odd offset identifies a first odd byte range in the group that is potentially written by the store memory operation; and wherein the first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation, and wherein the first even mask comprises a first bit vector having a bit corresponding to each byte in the first even byte range; wherein a state of the bit indicates whether or not the corresponding byte is written by the store memory operation; and wherein the first odd mask comprises a second bit vector having a bit corresponding to each byte in the first odd byte range; wherein a state of the bit indicates whether or not the corresponding byte is written by the store memory operation.