1. A testability analysis system, comprising: an input part inputting functional description data to define hardware function; a register variable identifying part identifying register variables whereby memory elements in said functional description data are inferred; a random pattern generator applying random patterns to the register variables identified by said register variable identifying part; a simulator conducting a simulation of events caused by applying the random patterns; and an analysis part analyzing a cause of decrease of a fault coverage by Scan-Based Logic BIST based upon toggle rates and simulation events of variables such as net and bus in said functional description data in accordance with a result of said simulation.