1. A memory system for use with a central processor unit having an address register comprising: a. a fixed memory having a plurality of fixed memory registers addressable by the address register of the central processor unit, and a control input for enabling or disabling the fixed memory in accordance with the state of the control input; b. an overlay memory having a plurality of sections of overlay memory registers, corresponding registers in each section being addressable simultaneously by a first portion of the address in the address register of the central processor unit; c. each section of the overlay memory having a control input for enabling or disabling such section in accordance with the state of its control input; and d. a mapping memory having a plurality of mapping memory registers addressed by a second portion of the address of the address register of the central processor unit; e. a first cell of each register of the mapping memory having a predetermined content and being connected to the control input of the fixed memory for establishing the state of such control input; and f. the remaining cells of each register having predetermined contents and being respectively connected to the control inputs of the sections of the overlay memory for establishing the state of each of such sections whereby the contents of the first cell of the addressed memory register determines whether the fixed memory is enabled or disabled, and the contents of the remaining cells of the addressed memory register disables all of the sections when the fixed memory is enabled, and enables one and only one of the sections when the fixed memory is disabled.