1. An apparatus for use in a pipelined continuous-time analog-to-digital converter (CT ADC), including a plurality of pipelined sub-analog-to-digital converters (sub-ADCs), including at least a first stage sub-ADC and a final stage sub-ADC, the apparatus comprising: a first pipelined stage, including the first stage sub-ADC, and including an input delay circuit positioned in a continuous-time signal path of the pipelined CT ADC and coupled to a first summing circuit; and at least one digital delay circuit coupled to an output of the first stage sub-ADC, the at least one digital delay circuit coupled to each of the first summing circuit and an output summing circuit; the output summing circuit coupled to the at least one digital delay circuit of the first stage sub-ADC, and an output of the final stage sub-ADC.