1. A processor comprising: a cache hierarchy including at least a first level-1 cache and a higher-level cache; wherein the processor is configured to: map a first portion of a physical memory space to a first portion of the higher-level cache; execute instructions, at least some of which comprise microcode; allow microcode to access the first portion of the higher-level cache; and prevent instructions that do not comprise microcode from accessing the first portion of the higher-level cache.