1. An apparatus in a pipeline microprocessor for avoiding a pipeline stall caused by a load instruction, the microprocessor including execution units, the apparatus comprising: first dispatch logic, configured to request from a cache data specified by the load instruction, to receive from said cache an indication that said data is not presently available from said cache, and to provide the load instruction and a tag identifying said unavailable data to one of the execution units; and second dispatch logic in each of the execution units, coupled to said cache, configured to monitor a bus coupling said cache and the execution units to detect a valid match of said tag which indicates said data is now available from said cache, to obtain said data from said cache in response to detecting said valid match of said tag, and to dispatch the load instruction and said data for execution in response to obtaining said data from said cache.