1. A processor adapted to execute a plurality of instances of an instruction, the instruction comprising an opcode and at least one argument, the processor comprising: a) a plurality of lanes, each lane adapted to execute an instruction; b) coupling circuitry adapted to couple at least one incoming lane of the plurality of lanes to a respective at least one coupled lane of the plurality of lanes in response to a control signal, the coupling circuitry comprising for each respective coupled lane: i) at least one opcode switching element, each opcode switching element connected between the at least one incoming lane and the respective coupled lane, the opcode switching element adapted to couple the opcode of an instruction in the at least one incoming lane to the at least one respective coupled lane, whereby instances of the instruction are executed in the at least one incoming lane and the at least one coupled lane, respectively; and ii) at least one argument switching element, each argument switching element connected between the at least one incoming lane and the respective coupled lane, the argument switching element adapted to selectively modify an address of at least one argument of an instruction in the at least one incoming lane and couple the at least one modified address to the respective coupled lane; and c) control circuitry adapted to control the opcode switching element and the argument switching element.