1. An apparatus, comprising: a plurality of memory dies coupled as a memory block to commonly receive a control signal group; wherein the memory block has an access width defined as a system word length divided by a burst length associated with the plurality of memory dies; wherein the system word length is equal to or greater than 12 bits; wherein the burst length is greater than a one beat burst of the system word length; wherein the memory block is configured to have a single word having the system word length written or read in a write operation or a read operation, respectively, through a write burst or a read burst, respectively, for random access memory operation with a granularity of the single word.