1. A burst mode architecture to provide burst mode access to a plurality of data words in a memory, the architecture comprising: a first circuit to access a plurality of data words, beginning with an initial access of a first data word and a second data word; a control circuit coupled to the first circuit and generating a timing signal having pulses, and a second signal upon completion of the initial access of the first data word and the second data word, and wherein the first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal; and a data buffer having an output and selectively coupled to the first circuit by the control circuit, the data buffer producing the first data word at the output and successively producing, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output, the subsequent data words corresponding to the subsequent accesses of the plurality of data words.