1. A method comprising: providing a layout having a first transistor cell abutted against a second transistor cell, wherein a place and route boundary between the first transistor cell and the second transistor cell intersects a polysilicon feature; shifting, by a computer, the place and route boundary to define a modified first transistor cell comprising the polysilicon feature and a modified second transistor cell; generating, by a computer, a netlist in accordance with the modified first transistor cell and the modified second transistor cell, the netlist comprising a device associated with the polysilicon feature, wherein shifting the place and route boundary reduces a mismatch between the netlist and a post-simulation netlist; and manufacturing a semiconductor chip using the post-simulation netlist.