1. A memory-mapped microprocessor integrated on a single chip including an on-chip memory and a plurality of on-chip input/output ports, adapted for connection to an external bus (210, 222) and thence to at least one off-chip memory, and having means for addresing a memory address space (100) that includes: a memory address range for on-chip memory (102, 104, 314, 316), a memory address range (106) for any off-chip memory (212, 214) and a memory address range (112) for off-chip references, passing through on-chip input/output ports (318, 319, 324, 326) when use of said external bus is requested, comprising on said chip a CPU (Central Processing Unit) (202, 302); at least one input/output port (318, 319, 324, 326); an on-chip memory (102, 104, 314, 316); at least one register (303) for storing an address in said memory address space; a plurality of signal lines (304, 306) interconnecting said CPU, port, said on-chip memory and said memory address register (303); a microprocessor selection means (310) connected to an output of said memory address register (303); a memory expansion mode control (320), whose mode can change, during the course of a program by execution of a predetermined instruction thereof, to select which of said on-chip memory and said off-chip memory is addressed, thereby obviating delays due to external bus requests when only on-chip memory is addressed, said memory expansion mode control being connected to said selection means (310) and means (324) for controlling an external bus (210, 222) connected to said selection means (310) and to said at least one input/output port, said microprocessor selection means (310) automatically testing a memory address stored within said register (303) to determine whether said address indicates an off-chip reference and hence requires use of said external bus, and responding to memory addresses within a predetermined off-chip range (106) by activating an on-chip bus control circuit (322, 410, 420, 430) which, in turn, arbitrates use of said external bus (210, 222), thereby permitting a user to mix on-chip and off-chip references without coding specific bus control instructions.