1. A multiple-input, multiple-output system, comprising: M input ports configured to respectively receive a different one of M discrete-time input signals; an integrated inverse-sinc hardware module configured to simultaneously process the M discrete-time input signals to generate M discrete-time output signals such that, when the M discrete-time output signals are interleaved to produce a first signal, the first signal, is equivalent to that produced by inverse-sinc filtering, using an inverse sinc filter, a second signal created by interleaving the M discrete-time input signals; and M output ports configured to respectively provide a different one of the M discrete-time output signals, wherein the integrated inverse-sinc hardware module comprises only a minimum number of delay elements equal to an order of the inverse-sine filter.