1. A processor to operate in a first mode and a second mode, comprising: front-end hardware including: a decoder to decode a plurality of control transfer instructions, the plurality of control transfer instructions including a call instruction and a return instruction; and a state machine to raise a fault in the first mode if a next instruction to be executed immediately after the return instruction is not the call instruction; wherein, in the first mode, execution of the call instruction is to include pushing on a stack an address of the call instruction, and wherein, in the second mode, execution of the call instruction is to include pushing on the stack an address of an instruction immediately following the call instruction.