1. A multithread execution device comprising: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction of the program retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution speed memory that stores target execution speed of the instruction; an execution speed monitor that monitors an execution speed of the instruction; and a feedback control unit that commands the instruction issue unit to issue the instruction so that the execution speed approximately equal to the target execution speed, wherein the target execution speed is calculated based upon a ratio between an operating frequency of an emulated CPU and an operating frequency of a CPU in the multithread execution device.