1. A system comprising: a synchronous dynamic random access memory (SDRAM) controller coupled to an SDRAM; a plurality of programmable multithreaded processors to process network packets, the plurality of programmable multithreaded processors comprising memory mapped registers; a reduced instruction set computer (RISC) processor coupled to the SDRAM controller and the plurality of programmable multithreaded processors, the RISC processor to receive and process packets from the plurality of programmable multithreaded processors; circuitry to enable the RISC processor to transfer data to and from the memory mapped registers of the plurality of programmable multithreaded processors; and a gigabit Ethernet device coupled to the plurality of programmable multithreaded processors.