1. A computer implemented method for performing semiconductor failure analysis comprising: importing a semiconductor layout; having a set of rules wherein each rule of the set of rules describes a design rule check for the semiconductor layout; selecting a rule from the set of rules to apply to the semiconductor layout wherein the rule describes a two-dimensional Boolean operation on shapes where the rule further describes shapes of one or more layers and shapes of potential defects derived from defect scanning tools or yield managements systems; identifying a portion of the semiconductor layout by searching through the semiconductor layout for a match to the rule which was selected; and displaying the portion of the semiconductor layout.