1. A microprogrammable system comprising: A. a plurality of microprogrammable subunits, one of said subunits being a master subunit which generates microinstruction addresses; B. A control store made up of a plurality of control substores, each of said plurality of control substores for controlling a corresponding one of said plurality of subunits, each of said plurality of control substores for storing a portion of ones of said microinstruction addresses wherein the reading of one of said microinstruction from said control store occurs by reading a portion of said microinstruction from each of said plurality of control substores in parallel, each of said plurality of control substores having an address input and a data output, said address input of each of said plurality of control substores coupled to said master subunit for receiving ones of said microinstruction addresses, said data output of each of said plurality of control substores having microinstructions thereon and is coupled to its said corresponding subunit to control microoperations executed thereby; C. a next address generation means included in said master subunit for generating said microinstruction addresses; D. trap request means included in a first subunit of said plurality of subunits for generating a trap signal to said master subunit indicating that an exception condition has occurred in said first subunit which requires an exception condition microprogram to be executed; E. trap responsive means included in said next address generation means which causes said next address generation means to generate a predetermined trap address as said microinstruction address to said plurality of control substores, said predetermined trap address pointing to where segments of said exception condition microprogram are stored; in each of the control substores, said plurality of subunits each being responsive to the generation of said trap address for executing segment of the microinstruction located within the corresponding one of said control substores in parallel F. a first syndrome register in said first subunit for storing one or more indicators regarding the status of processing being done in said first subunit ,said exception condition microprogram causing said indicators to be read from said first syndrome register and forwarded to said masater subunit to be tested for exception conditions within said first subunit, and G. a first decoder means included in said first subunit and coupled to said first syndrome register, said first decoder means being responsive to segment of the microinstruction in said exception condition microprogram output from the control substore of said first subunit to enable the contents of said first syndrome register to be read out to said master subunit; wherein during normal operation of said system, the execution of said microinstructions in said first subunit is controlled by conditions within said master subunit, but wherein said first subunit can cause said exception condition microprogram to be executed to remove said exception conditions by generating said trap signal.