1. An apparatus comprising: a decode unit to decode a first instruction into a decoded first instruction and a second instruction into a decoded second instruction; and an execution unit to: execute the decoded first instruction to cause a first logic circuit to allocate a first portion of one or more operations corresponding to a virtual vector request to a first processor core, and a second logic circuit to generate a first signal corresponding to a second portion of the one or more operations to cause allocation of the second portion to a second processor core, and execute the decoded second instruction to cause a first computational result corresponding to the first portion of the one or more operations and a second computational result corresponding to the second portion of the one or more operations to be aggregated and stored to a memory location.