1. Single-precision floating-point multiplication circuitry that performs first and second half-precision floating-point multiplication operations, comprising: a first arithmetic operator circuit that generates a first partial product of first and second half-precision floating-point numbers; a second arithmetic operator circuit that generates a second partial product of third and fourth half-precision floating-point numbers; a compressor circuit that generates a carry vector signal and a sum vector signal based on the first and second partial products; and a third arithmetic operator circuit that generates at least first and second results of the first half-precision floating-point multiplication operation in parallel to each other and at least third and fourth results of the second half-precision floating-point multiplication operation in parallel to each other based on the carry and sum vector signals to anticipate rounding and normalization operations.