1. A data transfer network for data transfers between a main host computer and a plurality of remote data sets operating under different protocol and timing disciplines wherein said main host computer initiates I/O data transfer commands to a line support processor means having a plurality of line support processors, each one of which manages data transfers between one of said remote data sets and said main host computer, said data transfer network comprising: (a) said main host computer connected to each one of said line support processors and including: (a1) main memory means for storing data to be transmitted to/received from said remote data sets and including: (a1a) a first dedicated memory area for storing a I/O data transfer commands for transmittal to said line support processors; (a1b) a second dedicated memory area for storing operational codes for transmittal to said line support processors wherein said operational codes contain information translatable, by said line support processor, into control data for selecting timing and protocol discipline for a selected line adapter; (a2) a main processor for selecting said I/O data transfer commands and said operational codes for communication and control of said line support processor, said processor including: (a2a) connection means to a distribution control circuit; (b) a base module providing backplane connection means for slide-in circuitry cards, said base module including: (b1) said distribution control circuit functioning to connect and/or disconnect said host computer to/from a selected line support processor in line support processor means; (b2) said line support processor means functioning to execute said I/O data transfer commands by controlling a selected line adapter to a remote data set, said line support processor means including: (b2a) a plurality of line support processors connected to said distribution control circuit wherein each said line support processor includes: (B2a1) interface circuit means connecting said main host computer, via said distribution control circuit, to a plurality of line adapter means and to a state machine processor means; (b2a2) said state machine processor means including a state machine processor operating to translate said operational codes into control data for operating a selected line adapter in a desired timing and protocol discipline for managing data transfers between said selected line adapter and an associated said data set, said state machine processor means including: (i) a first auxiliary memory storage area for receiving said operational codes from said host computer; (ii) program memory means for enabling said state machine processor to translate said operation codes into control data for operating a selected line adapter; (iii) said state machine processor operating to transmit said control data to said selected line adapter for selecting and managing the timing and protocol discipline for data transfers, and including: (ie) means for selecting a particular line adapter in said plurality of line adapter means; (iie) means for identifying the required timing and protocol discipline for said particular line adapter; (iiie) means for generating address signals for selecting a desired control register in said particular line adapter and placing said control data therein; (ive) means for transferring data to/from said particular line adapter; (ve) means for selecting a group of multiplexors associated with said selected particular line adapter; (c) said plurality of line adapter means connected to said state machine processor means and including a plurality of line adapters, wherein each line adapter includes: (c1) a data communication line to an associated said remote data set; (c2) a plurality of control registers holding said control data for managing data transfers according to a desired timing and protocol discipline, said control data being derived from said state machine processor means; (d) transceiver-controller means, operating under control of said state machine processor means, for switching a data bus to connect said state machine processor to a selected line adapter or to connect said selected line adapter to a multiplexor means; (e) said data bus connecting each of said line adapters to said transceiver-controller means; (f) multiplexor means including: (f1) a plurality of groups of multiplexors whereby each group of multiplexors is connected to an associated line adapter for conveying bytes of data from said remote data set to said state machine processor means for subsequent transfer to said host computer, and wherein each said group of multiplexors includes: (f1a) coded input signal means for identifying the particular timing and protocol discipline required for the said associated line adapter.