1. A method for synchronizing multiple processing units, the method comprising the steps of: providing a synchronization register in a target processing unit; assigning a distinct bit position of the synchronization register to each processing unit; executing a program thread in each processing unit; when the program thread of a current processing unit reaches a synchronization point: executing a single write instruction in the current processing unit, targeting the synchronization register and conveying a mask word in which the bit position assigned to the current processing unit is set, responding to the single write instruction in a single cycle by overwriting the content of the synchronization register with an output of a connected bitwise logic gate to compare the content of the synchronization register with the mask word, and suspending the program thread; and when all the bits assigned to the processing units are set in the synchronization register, resuming execution of the suspended program threads.