1. A processing system, comprising: a processing core communicatively coupled to a cache via a cache controller; a cache repair memory communicatively coupled to the cache controller; wherein the cache controller is configured, responsive to receiving a read request referencing a physical address, to: retrieve cache data from a cache location identified by the physical address, retrieve, from the cache repair memory a bit repair value associated with a specific bit of the cache location, a column repair value associated with a specific column of the cache location, and a row repair value associated with the a specific row of cache location, produce cache repair data by multiplexing the bit repair value, the column repair value, and the row repair value, and output the cache data multiplexed with the cache repair data.