1. A processor, comprising: a floating-point unit configured to execute an unfused multiply-accumulate instruction defined with an instruction set architecture, wherein the unfused multiply-accumulate instruction includes a multiply sub-operation and an accumulate sub-operation; a storage configured to maintain floating-point exception state information; and exception logic including a storage array and configured to capture uncommitted floating-point exception state within the storage array after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, and to update the storage, after the unfused multiply-accumulate instruction commits, with the floating-point exception state from the storage array; wherein the storage array includes a first port and a second port; and wherein the exception logic is further configured to: read exception information for a first unfused multiply-accumulate instruction defined in the instruction set architecture from the first port in response to a determination that the first unfused multiply-accumulate instruction has committed; read exception information for a second unfused multiply-accumulate instruction defined the in the instruction set architecture from the second port in response to a determination that the second unfused multiply-accumulate instruction has committed; select one of the exception information for the first unfused multiply-accumulate instruction and the exception information for the second unfused multiply-accumulate instruction dependent upon which of the first unfused multiply-accumulate instruction and the second unfused multiply-accumulate instruction commits; and determine an architectural state dependent upon the selected exception information; wherein the first unfused multiply-accumulate instruction and the second unfused multiply-accumulate instruction are concurrently executed.