1. A processor, comprising: a first processor core including: a first cache including a first logic to store one or more translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; a second logic to execute a translated instruction, the translated instruction translated from an instruction stored in a first memory location; a third logic to set a first translation indicator in the first cache corresponding to the first memory location to indicate that the first memory location includes translated code to be protected; and a fourth logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.