1. A pattern recognition system including means for detecting one of a maximum data signal or a minimum data signal from a plurality of data signals, wherein said plurality of data signals are ordinarily arranged from a first data signal to an nth data signal, said system comprising: first memory means wherein a plurality of standard pattern data signals are stored in advance; input means for acquiring input pattern data signals; calculating means for successively generating a plurality of calculation signals representing a plurality of differences or correlations between each one of said input pattern data signals and one of said plurality of standard pattern data signals; second memory means for receiving and storing said plurality of calculation signals, wherein said plurality of calculation signals are ordinarily arranged from a first calculation signal to a nth calculation signal; reading means for reading and transmitting each of said calculation signals of said plurality of calculation signals in succession; first store means coupled to said reading means wherein a calculation signal which is initially calculated is stored; second store means coupled to said reading means wherein one of each of a second calculation signal of each of said plurality of calculation signals through the nth calculation signal of said plurality of calculation signals is successively stored; third store means wherein an address signal of the calculation signal stored in said first store means is stored; means for obtaining and transmitting the address signal of said first calculation signal of said plurality of calculation signals to said third store means; comparison means for comparing said calculation signal stored in said first store means and said calculation signal stored in said second store means and for generating and transmitting a comparison signal indicative of said comparison; a first selector for receiving said comparison signal from said comparison means and for selectively replacing the calculation signal stored in said first store means with the calculation signal stored in said second store means; a second selector for receiving said comparison signal from said comparison means and for selectively replacing the address signal stored in said third store means with the address signal of the calculation signal contained within said second store means.