1. A method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design, the method comprising: executing, using a processor, a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters; determining, using the processor, a quality measure associated with each of the two or more scenarios; and performing the intra-run decision using the processor, by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis, the eliminating based on the quality measure associated with each of the two or more scenarios.