1. A controller for a signal processing computer, comprising: a microinstruction storage having an address input and a microinstruction word output, for storing microinstruction words, each having a page control field, a microinstruction address stack sequencing pointer field, and a main memory pointer field; a first clock connected to said microinstruction storage, for producing a first clock signal at a first repetition rate to signal said microinstruction storage to output said microinstruction words at said first repetition rate, each microinstruction word respectively accessed at an address applied to said address input thereof during a corresponding microinstruction interval; a microinstruction address stack having a clock input connected to said first clock, having a page address input connected to the page control field of said microinstrudtion storage output, having a pointer address input connected to the microinstruction address stack sequencing pointer field of said microinstruction storage output, and having an output connected to said address input of said microinstruction storage, for storing microinstruction word addresses in a plurality of page groups, each page group being accessed by said page address input, each respective page group having a plurality of said microword addresses which are accessed by said pointer address input, said microinstruction address stack selectively accessing new microinstruction words from said microinstruction storage in response to said page field and sequencing pointer field of a current microinstruction word at said first repetition rate; a main memory address stack having a clock input connected to said first clock, having a page address input connected to said page control field of said microinstruction storage output, having a pointer address input connected to the main memory pointer field of said microinstruction storage output, and having an output connected to an address input of a main data memory, for storing main data memory addresses in a plurality of page groups, each page group being accessed by said page address input thereof, each respective page group having a plurality of said main data memory addresses which are accessed by said pointer address input thereof, said main memory address stack selectively accessing data words from said main data memory in response to said page field and main memory pointer field of said current microinstruction word at said first repetition rate; said microinstruction words further including a first scratch pad pointer field and a second scratch pad pointer field; a second clock having an output, for producing a second clock signal at a second repetition rate which is twice said first repetition rate, producing two second clock pulses initiating the first half and the second half, respectively of said microinstruction interval; a first multiplexer having a clock input connected to said second clock, having a first input connected to the first scratch pad pointer field of said microinstruction storage output, having a second input connected to the second scratch pad pointer field of said microinstruction storage output, and having an output, for connecting said output thereof to said first input thereof during said first half of said microinstruction interval and to said second input thereof during said second half of said microinstruction interval; a first scratch pad memory having a clock input connected to said second clock, having an address input connected to said output of said first multiplexer, having a data input connected to a data output of said data memory and having a data output connected to a first input to a first arithmetic element, for reading a first data word from a first location therein, and outputting it to said arithmetic element, in response to said first scratch pad pointer field during said first half of said microinstruction interval and writing a second data word into a second location therein applied at said data input thereof from said main memory, in response to said second scratch pad pointer field during said second half of said microinstruction interval; whereby said first scratch pad is controlled by said microinstruction word to operate at twice the rate at which said microinstructions are accessed from said microinstruction storage.