1. For a host processor which executes host instructions and includes a host processor addressable memory, a system for decoding guest instructions, comprising: a sequence of guest instructions in said host processor addressable memory; an emulation program store, in said host processor addressable memory, said emulation program store containing emulation programs, each of said emulation programs having a starting address within said emulation program store, each of said emulation programs including a host instruction routine for emulation of a particular guest instruction; and logic, within said emulation programs, which is implemented by decoding instructions that are executable by said host processor including an instruction to retrieve a next guest instruction in said sequence, and an instruction to determine one of said starting addresses in response to said next guest instruction by multiplying said next guest instruction by a constant value and by adding a base address of said emulation program store, and an instruction to jump directly to said emulation program store in response to said one of said starting addresses.