1. A data processing device using pipeline control, comprising: an instruction queue in which a plurality of instruction codes are fetched; a fetch address operation circuit which calculates a fetch address used to fetch an instruction code in the instruction queue; a fetch circuit which fetches an instruction code that is read out based on the fetch address into the instruction queue; and a branch information setting circuit which decodes a branch setting instruction instructing a branch to a branch target address when the fetch address is a branch address, stores the branch address in a branch address storage register, and stores the branch target address in a branch target address storage register, wherein the fetch address operation circuit includes a circuit which compares one of a previous fetch address and an expected next fetch address with a value stored in the branch address storage register, and then determines whether or not to output a value stored in the branch target address storage register as a next fetch address, based on the comparison result.