1. A method of designing a system-on-chip, the method comprising: obtaining a plurality of processing modules each representing in software one of a plurality of processing units of a system-on-chip architecture, the plurality of processing units including a central processor, a video processor, an audio processor, and a graphic processing unit; modeling data communications sent between the central processor, the video processor, the audio processor, the graphic processing unit and other processing modules of the plurality of processing modules as accesses to memory; generating a coherent memory module associated with the plurality of processing modules based on the modeling of the data communications sent between the central processor, the video processor, the audio processor, the graphic processing unit and the other processing modules as accesses to memory, the coherent memory module representing in software a plurality of first caches, each of the first caches being associated with one of the plurality of processing modules, a second cache communicatively coupled to each of the plurality of first caches, and a cache controller to control the data communications from one or more of the plurality of processing modules to other of the plurality of processing modules by controlling read and write operations between the plurality of first caches and the second cache; and implementing the coherent memory module, the central processor, the video processor, the audio processor, and the graphic processing unit of the system-on-chip architecture on a single chip.