1. A reduced instruction set computer (RISC) processor, comprising: a register set comprising registers having respective indices; a processing core, which accepts one or more instruction for performing an operation on an operand held in a first register, which is identified by an index held in a second register that is specified by the one or more instruction, and which is further arranged, responsively to the one or more instruction, to extract the index of the first register from the second register and to perform the operation on the operand in the first register as identified by the extracted index.