1. A processor implemented method for eliminating or reducing an operand line crossing penalty, the method comprising: performing an initial fetch for an operand from a data cache of a processor by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary; performing a plurality of subsequent fetches for a corresponding plurality of operands from the data cache wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines of the data cache; and maintaining a steady stream of data by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.