1. A system comprising: a plurality of processors; a first interconnect to communicatively couple two or more of the plurality of processors; a second interconnect to communicatively couple one or more of the plurality of processors to one or more other system components; and a system memory communicatively coupled to one or more of the processors; at least one processor comprising: a plurality of simultaneous multithreading (SMT) cores, each of the SMT cores to perform out-of-order instruction execution for a plurality of threads; at least one shared cache circuit to be shared among two or more of the SMT cores; at least one of the SMT cores comprising: an instruction fetch circuit to fetch instructions of one or more of the threads, an instruction decode circuit to decode the instructions, a register renaming circuit to rename registers of a register file, an instruction cache circuit to store instructions to be executed, a data cache circuit to store data; at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit; a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit, the PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of one or more of the processors including the at least one shared cache circuit; and a memory access circuit to identify an accelerator context save/restore region of the accelerator device in a memory space that stores data from execution of an application, the application invoking the accelerator device during the application's execution, the accelerator context save/restore region pointed by a context save/restore pointer, and the accelerator context save/restore region to store an accelerator context state.