1. A multi-processor system comprising: an arrangement of a plurality of processor nodes, each processor node having a processor, local memory and a communications bus interface; a plurality of point-to-point communication busses disposed between pairs of said communications bus interfaces such that data may be moved across said point-to-point busses between said local memories of said processor nodes; one or more I/O busses disposed to communicate with all said processor nodes as well with sources and destinations outside said arrangement; and one or more configurable signal processing frameworks selectably disposed in series with one or more communication bus or I/O bus such that data traversing a bus may be processed by logic hosted by said processing frameworks.