1. A computer-implemented method for creating in computer memory a representation of a hierarchical circuit design, comprising the steps of: storing in the computer memory a very large scale integrated (VLSI) circuit design component representing a leaf design entity from the hierarchical circuit design; storing in the computer memory a set of locations in the design where the VLSI circuit design component appears, the locations representing instances of the leaf design entity; associating with the VLSI circuit design component and the locations a set of links, the links connecting various ones of the locations to one another to denote placement of the VLSI circuit design component within the hierarchical circuit design; storing the set of links in the computer memory; and computing an instance count denoting a number of instances of the VLSI circuit design component represented at the location with which the instance count is associated.