1. A method for determining capacitance gradients of a Very Large Integrated Circuit (VLSI) chip layout, comprising: i. using a computer, decomposing one or more layout shapes into elementary patterns; ii. translating physical parameter variations into variations on parameters of elementary patterns into which the layout shapes are decomposed; iii. computing capacitance gradients of said elementary patterns using a lookup table; iv. combining said capacitance gradients into capacitance gradients of said one or more layout shapes of said chip layout; v. transferring said capacitance gradients to a netlist providing electrical-level descriptions of said chip layout; and vi. translating physical parameter variations into variations on edges of elementary patterns into which said chip layout shapes are decomposed, and mapping layout patterns into layout configurations extracted from said look out tables.