1. A method of analysis of a circuit design, the method comprising: receiving a timing graph of a circuit including delay arcs with a statistical function of delay, slew, slack, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; evaluating the timing pins from input ports to output ports to determine if one or more timing pins can be merged out and reduce the timing graph down to a reduced timing graph; automatically generating top level timing constraints and standalone timing constraints for the reduced timing graph in response to one or more original timing constraints of the timing graph, and reduction in the reduced timing graph from the timing graph; and wherein one or more of the receiving, the determining, the identifying, the evaluating, and the automatically generating are performed with a processor.