1. A method comprising: translating, by a processor, a speculative transaction among a plurality of speculative transactions in a hardware transactional memory (HTM) to a non-speculative transaction; acquiring a global hardware lock for the non-speculative transaction, wherein a storage for a central processing unit (CPU) identifier (ID) is associated with the global hardware lock and stores the CPU ID corresponding to a CPU core for a thread executing the non-speculative transaction that acquires the global hardware lock, wherein instructions of remaining ones of the speculative transactions are executed speculatively and mark transactional bits in a cache for a cache coherency protocol of the HTM, wherein the global hardware lock is to be read by the remaining ones of the speculative transactions as part of a commit procedure subsequent to speculative execution that abort if the global hardware lock has been acquired, and wherein instructions of the non-speculative transaction are not executed speculatively and do not mark transactional bits in the cache; executing the instructions of the non-speculative transaction without speculation while the global hardware lock has been acquired for the non-speculative transaction; and releasing the global hardware lock and clearing the CPU ID from the storage upon completion of the execution of the instructions of the non-speculative transaction and in response to determining that the CPU ID of the CPU core executing the non-speculative transaction matches the CPU ID in the storage associated with the global hardware lock.