1. For use in a system for controlling data-accessing of a common bus, an improved DRAM architecture comprising a multi-port internally cached DRAM (AMPIC DRAM) comprising a plurality of independent serial data interfaces each connected between a separate external I/O resources and internal DRAM memory through corresponding buffers competing for access to a common internal bus; a switching module interposed between the serial interfaces and the buffers; and a switching module logic control for the connecting of any of the I/O resources through serial interfaces with any of the buffers under a dynamic configuration of switching allocation as appropriate for the desired data routability among the interfaces wherein the number of the serial interfaces is independent of the number of buffers and the number of serial interfaces varies under the dynamic configuration.