1. A cache circuit comprising: cache memory for holding at least either data read/written by an information processor from/into main memory connected to a bus or an instruction code read from the main memory; a cache control circuit for reading data or an instruction code from the cache memory and outputting the read data or instruction code to the information processor in response to a read request for the data or the instruction code from the information processor if a cache hit is determined, reading data or an instruction code from the main memory and allowing the read data or instruction code to be held in the cache memory as well as outputting the read data or instruction code to the information processor if a cache miss is determined, and writing data in the cache memory in response to a write request for the data from the information processor; and a cache memory disabling circuit for disabling data or an instruction code held in the cache memory according to the number of cache hits.