1. A system for designing and emulating an embedded processor design, which system comprises: (i) a verification module and system controller comprising: (a) an interface to a user workstation; (b) at least one field programmable logic device configured as an conventional embedded logic analyzer IP circuit description; (c) at least one first clock and user signal compression tunnel portal; (d) a plurality of gigabit transceivers; and (ii) at least one system on chip (SoC) partition logic module coupled to the first clock; and user signal logic value compression tunnel portal of the verification module, each SoC partition logic module comprising: (e) a plurality of field programmable logic devices for emulating the user design wherein each field programmable logic device comprises, in addition to the user design, a circuit for a user signal compression tunnel, the circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal, whereby a portion of the user design assigned to the programmable logic device communicates with portions of the user design assigned to other programmable logic devices through gigabit transceivers; and (f) at least one field programmable logic device configured as a processor coupled by a circuit for user signal compression tunnel portal to each other field programmable logic device, whereby monitoring all on-board global clocks in real time, monitoring and displaying voltage, current and temperature; setting external I/O voltages through software, and global reset is provided remotely through software.