1. An integrated circuit, comprising: a first memory; a second memory; and a built-in self-test controller, comprising: a first memory interface, coupled to the first memory, having the ability to perform a first plurality of test algorithms; a second memory interface, coupled to the second memory, having the ability to perform the first plurality of test algorithms; and a sequencer, coupled to the first and second memory interfaces, that provides a plurality of sequencing control signals for controlling a performance sequence of the first plurality of test algorithms for both the first memory interface and the second memory interface.