1. A programmable logic cell, capable of receiving a first input signal, a second input signal, and a third input signal, and providing an output signal, comprising: a first multiplexer having a first input, a second input, an output, and a selector; a NAND gate having a first input, a second input, and an output, wherein the first input of the NAND gate receives the output from the first multiplexer; a second multiplexer having a first input, a second input, an output, and a selector; a third multiplexer having a first input coupled to the output of the second multiplexer, a second input, an output providing the output signal for the programmable logic cell, and a selector; a plurality of programmable elements coupled to the first multiplexer, the second multiplexer, and the third multiplexer such that the combination of the first multiplexer, the second multiplexer, the third multiplexer, and the NAND gate together perform each one of a set of functions depending on which of the plurality of programmable elements are programmed, said set of functions comprising: a D flip-flop, a D latch, and a LUT capable of implementing any three input logic function.