1. A data processing apparatus for accessing a plurality of memories, wherein the data processing apparatus comprises: a function control circuitry, utilized to record a first memory address where a first function is implemented in the function control circuitry after the first function is implemented and to determine which one of the plurality of memories is a target memory according to the first memory address; and an address generation circuitry, utilized to output the first memory address to the target memory, wherein the function control circuitry is configured to determine the target memory in the same processing cycle in which the address generation circuitry is configured to output the first memory address.