1. A digital adder circuit operable to form the sum of two n-bit operands representing binary-coded numbers of radix other than a power of two, comprising (a) a plurality of multiplexers each having two selection control inputs, four data inputs, and a data output, (b) means for feeding corresponding pairs of bits of the two operands to the selection control inputs of the respective multiplexers, and (c) means for applying a predetermined pattern of bits to the data inputs of the multiplexers to condition the multiplexers to produce, at their data outputs, inter-bit carry generate and carry propagate signals corresponding to the binary addition of the two operands plus a correction value equal to the difference between 2.sup.n and said radix.