1. A signal processing device comprising a first discrete time analog signal filter section, said first section comprising: an input for accepting a time series of input signal values; an output for providing a time series of output signal values; an analog signal storage section comprising a plurality of capacitors, the analog signal storage section comprising a first storage section having a plurality of capacitors configured for selective charging according to input signal values; a first plurality of scaling sections, each scaling section being associated with a different part of the first storage section; switching circuit elements configurable to, for each time step of the time series of input signal values, (a) charge a subset of the capacitors of the first storage section according to the input signal value for that time step, (b) in a series of one or more phases, couple multiple subsets of two or more capacitors each subset being selected from capacitors of one of the scaling sections and capacitors in the part of the first storage section associated with the one of the scaling section, and (c) couple a group of capacitors to form an intermediate signal value, the group of capacitors including at least one capacitors from the analog signal storage section and at least one capacitor from the first plurality of scaling sections, circuitry for forming each output signal value of the time series of output signal values from a corresponding intermediate signal value; control logic for controlling configuration of the switching circuit elements in successive phases of a clock signal to form the time series of output signal values as an application of a filter to the time series of input signal values.