1. A method for using a micro-op cache in a processor, the method comprising: performing a tag match for an instruction pointer to retrieve a first set of micro-op cache line access tuples having matching tags; storing the first set of micro-op cache line access tuples in a match queue; and concurrently accessing a first plurality of cache lines in a micro-op cache data array responsive to a corresponding first plurality of micro-op cache line access tuples from the match queue to retrieve a second plurality of micro-ops.