1. A memory device, comprising: an n-type doped silicon substrate; a tunnel oxide layer formed on the n-type doped silicon substrate; a floating nanocrystal gate embedded in a control oxide layer and formed on the tunnel oxide layer; a drain region formed by implantation of a p-type dopant material in the n-type silicon substrate; a source region formed by implantation of a p-type dopant material in the n-type silicon substrate; a photon source coupled to the floating nanocrystal gate; and a control gate formed on the control oxide layer, wherein a first memory state is produced by: applying photons generated by the photon source to the floating nanocrystal gate to induce electron-hole pairs, and applying one or more bias voltages to at least one among the control gate, the drain region and the source region to induce a removal of electrons from the floating nanocrystal gate.