1. A controller apparatus comprising: one or more hardware engines; memory connected to the one or more hardware engines; one or more host ports connected to the one or more hardware engines, configured to connect to one or more host devices; and one or more device ports connected to the one or more hardware engines, configured to connect to one or more peripheral component interconnect express devices, wherein the one or more hardware engines are configured to: determine a transaction size; allocate a buffer header; allocate a virtual buffer, associated with one or more memory addresses in the peripheral component interconnect device, in a virtual memory according to the transaction size; associate the virtual buffer with the buffer header; associate the virtual buffer with a scatter/gather list element, associated with a memory address in a host; and link the buffer header and the scatter/gather list element in a state table entry.