1. A processor comprising: a control logic circuit; and one or more resources in a pipeline shared by a plurality of active software threads, wherein each of the one or more resources comprises a plurality of entries allocated to at least two of the plurality of active software threads; wherein in response to detecting a load operation miss corresponding to a load operation in a given active thread of the plurality of active software threads to a last-level cache, the control logic circuit is configured to: select the load operation as a given instruction from the given active thread of the plurality of active software threads, in response to determining the load operation qualifies for instruction replay by determining the load operation is permitted to be interrupted once started; select an oldest instruction of one or more instructions younger than the load operation as the given instruction, in response to determining the load operation does not qualify for instruction replay by determining the load operation is not permitted to be interrupted once started; flush from the pipeline at least one or more instructions younger than the given instruction, wherein flushing the pipeline prevents further execution of the at least one or more instructions younger than the given instruction; re-fetch at least the flushed one or more instructions younger than the given instruction; and hold at a given stage of the pipeline at least the re-fetched one or more instructions younger than the given instruction until the load operation is serviced with data corresponding to the load operation, wherein said hold prevents one or more resources past the given stage from being allocated to at least the re-fetched one or more instructions younger than the given instruction within the given active thread.