1. A computer implemented method for absolute address branching in a reduced instruction set computing (RISC) architecture, the method comprising: fetching a branch instruction from an instruction stream having a fixed instruction width; acquiring a branch target address value from the instruction stream, the branch target address value representing a target address of the branch instruction, the branch target address value formatted as an absolute address and sized as a multiple of the fixed instruction width; loading the branch target address value into a program counter based on the branch instruction; and redirecting execution of the instruction stream to a next instruction based on the branch target address value in the program counter.