1. A partially depleted silicon-on-insulator transistor, comprising: a silicon body formed on an insulating film, wherein said silicon body has a top surface, a first laterally opposite sidewall, and a second laterally opposite sidewall; a gate dielectric formed on and around said silicon body; a gate electrode formed on said gate dielectric on and around said silicon body; and a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrode, wherein said gate electrode has a gate length less than or equal to half of a width between laterally opposite sidewalls of said silicon body, and when said transistor is turned “ON” said silicon body between said source/drain regions is partially depleted to create a storage node.