1. A device, comprising: a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (LBAs); a secondary memory implemented as a cache for the primary host memory; and a hybrid controller configured directly map clusters of host LBAs to clusters of secondary memory, the secondary memory clusters corresponding to a memory space of the cache, the mapping of the host LBA clusters to the secondary memory clusters being fully associative wherein any host LBA cluster can be mapped to any secondary memory cluster.