1. An apparatus, comprising: a processor including a macro-code instruction interceptor to detect input/output access operations associated with an input/output address space and a first memory address bit size; and a scratch pad memory to record a configuration address associated with an operating system thread and the input/output address space, wherein the macro-code instruction interceptor is to combine the configuration memory address and associated configuration data into a packet having a second memory address bit size greater than the first memory bit size.