1. A method of forming a memory device; comprising: forming a first dielectric material overlying a surface region of a semiconductor substrate; forming a first bottom wiring structure spatially extending in a first direction and including a portion extending into a first peripheral region; forming a first top wiring structure spatially extending in a second direction perpendicular to the first direction and including a portion extending into a second peripheral region; forming first switching regions sandwiched in intersection regions between the first top wiring structure and the first bottom wiring structure, wherein the forming the first switching regions comprises, forming an adhesion layer comprising a metal nitride on the first bottom wiring structure; depositing a resistive switching material layer overlying the adhesion layer, wherein the resistive switching material layer comprises a silicon-containing resistive switching material; forming a second dielectric material overlying the first top wiring structure; forming a second bottom wiring structure spatially extending in the first direction and including a portion extending into the first peripheral region; forming a second top wiring structure spatially extending in the second direction perpendicular to the first direction and including a portion extending into the second peripheral region; forming second switching regions sandwiched in intersection regions between the second top wiring structure and the second bottom wiring structure, forming a third dielectric material overlying the second top wiring structure; forming a via opening in a portion of the first periphery region, the via opening exposing a portion of the first bottom wiring structure, a portion of the second bottom wiring structure and a portion of the semiconductor substrate; and depositing a conductive wiring material to fill the via opening and form a via structure, wherein the via structure is contacting both the portion of the second bottom wiring structure extending into the peripheral region and the portion of the first bottom wiring structure extending into the peripheral region, and electrically connecting the second bottom wiring structure and the first bottom wiring structure to a first control circuitry on the semiconductor substrate.