1. A normalization/denormalization circuit included in a cryptography accelerator unit coupled to an external processor, comprising: a normalization sub-circuit arranged to generate normalized data based upon corresponding unnornalized data; a context sub-circuit coupled to the normalization sub-circuit for characterizing the normalized data in relation to the unnormalized data; and a denormalization sub-circuit coupled to the context sub-circuit arranged to provide the unnormalized data based upon the normalized data and the characterization, wherein the normalization/denormalization circuit efficiently provides a normalization/denormalization service to the cryptography accelerator unit such that substantially no external processor resources are used to normalize or denormalize data.