1. A processor, comprising: an instruction pipeline including execution circuitry and instruction sequencing logic that provides a stream of instructions including a test instruction for execution; and pipeline control logic that, responsive to receipt of the test instruction, interlocks the instruction pipeline to prevent advancement of at least one first instruction in the instruction pipeline while permitting advancement of at least one second instruction in the instruction pipeline until a release condition occurs and, in response to the release condition, releases the interlock to enable advancement of said at least one first instruction in the instruction pipeline.