1. An apparatus, comprising: an execution unit comprising a multiply add computation unit, a first ALU logic unit and a second ALU logic unit, the execution unit to perform: a first instruction, said first instruction being a multiply add instruction; a second instruction, said second instruction to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction; a third instruction, said third instruction to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction; a fourth instruction, said fourth instruction to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate to determine first and second division resultant digit values.