1. An FFT computing apparatus comprising: a computation-unit switching detection unit that detects timing at which a complex multiplication is not being carried out in a butterfly computation of FFT (Fast Fourier Transform) computation; and a complex-multiplication power-computation unit that switches computation between complex multiplication and power computation, based on a detection result by said computation-unit switching detection unit, wherein said complex-multiplication power-computation unit performs power computation at timing at which complex multiplication is not carried out in said butterfly computation of FFT computation.