1. An application specific integrated circuit comprising: a) a first functional block for providing a first address, a first column address strobe signal, and a first read/write signal; b) a second functional block for providing a second address, a second column address strobe signal, and a second read/write signal; and c) an embedded memory interface coupled to the first functional block and the second functional block for providing the first functional block and the second functional block access to an embedded memory at the same time when predetermined conditions are met and providing the first functional block and the second functional block access to the embedded memory at different times when the predetermined conditions are not met.