1. A method comprising: defining, by a computing system, coverage for system level functionality of a circuit design as a set of system level coverage points, each corresponding to a different portion of system level functionality of the circuit design, wherein at least a portion of the circuit design is provided for subsequent design and manufacturing of electronic devices; generating, by the computing system, a matrix having multiple nodes corresponding to the system level coverage points in the set, wherein the nodes are arranged in the matrix based on characteristics of the different portions of the system level functionality corresponding to the system level coverage points; simulating, by the computing system, the circuit design with one or more regressions; populating, by the computing system, the nodes of the matrix with indications of events performed during the simulation; and utilizing, by the computing system, the matrix to identify holes in the coverage for system level functionality of the circuit design based on a distribution of the indications populated in the matrix.