1. A dynamic clock mode switch for switching clock frequencies in response to an enable signal, while allowing continuing operation of a depending system, said switch comprising: a phase-locked loop circuit (PLL) for locking onto an input clock signal having a first frequency in response to said enable signal and for providing a first output clock signal, phase locked to said input clock signal, having a second frequency automatic clock switching means for providing said first output clock signal as the dynamic clock mode switch output clock signal, and for automatically switching to said input clock signal as the dynamic clock mode switch output clock signal when said PLL loses lock, but only at a subsequent clock phase boundary.