1. A method of designing at least a part of an integrated circuit, IC, design, the method comprising: identifying a first and at least one further module within the IC design that are mutually exclusive; selecting at least one register within the first identified module and at least one register within the at least one further identified module to be shared; merging the first and at least one further mutually exclusive modules such that a register is shared between the first and at least one further mutually exclusive modules for the registers selected to be shared; generating, by a signal processing module arranged to perform logic synthesis, a merged gate level netlist for the first and at least one further mutually exclusive modules; and outputting a merged gate level netlist to a subsequent design phase.