1. A circuit arrangement, comprising: a vector execution unit configured to execute a floating point instruction to perform a floating point operation using at least one operand identified by the instruction, wherein at least one operand of the floating point instruction is a denormal value, the vector execution unit comprising: a first processing lane comprising logic for performing floating point operations and configured to prenormalize the denormal value operand loaded in the first processing lane, a second processing lane comprising logic for performing floating point operations, a dot product adder including a first input that is connected to the first processing lane and a second input that is connected to the second processing lane, and the dot product adder is configured to perform at least a portion of the floating point operation using the prenormalized value, wherein the first processing lane is configured to communicate the prenormalized value through the logic of the first processing lane to the first input of the dot product adder, and the first processing lane prenormalizes the denormal value, communicates the prenormalized value through the logic to the first input of the dot product adder, and the dot product adder performs the at least a portion of the floating point operation in a single pass of an execution pipeline of the vector execution unit, wherein the floating point instruction includes the denormal value operand and a second operand, wherein the vector execution unit further comprises multiplexing logic connected between the first processing lane and the second input of the dot product adder, and the first processing lane is further configured to: load the denormal value operand and the second operand for processing, communicate the second operand to the second input of the dot product adder through the multiplexing logic such that the second operand bypasses the first processing lane, and communicate the prenormalized value to the first input of the dot product adder.