1. A rasterizer in a graphic processor device implemented on a field programmable gate array circuitry, comprising: a preprocessor that receives commands and vertices and creates data packets to generate at least one line; a main module that generates a stream of data fragments that become pixels, wherein the main module further comprises a multi-threading packet processing engine that determines a dominant axis having a larger change in value in the line and sequences the vertices so that vertex coordinates increase along the dominant axis; and a postprocessor that combines the data fragments and pipeline commands into one output to a fragment processor.