1. A multithreaded processor comprising: a plurality of hardware thread units each comprising at least one memory unit; an instruction decoder coupled to the plurality of hardware thread units for decoding instructions received from at least one of the at least one memory unit; a plurality of execution units responsive to the instruction decoder for executing the decoded instructions; a first non-partitioned register file including a first plurality of registers, the first non-partitioned register file coupled to at least one of the at least one memory unit and coupled to each of the plurality of execution units, the first non-partitioned register file supporting execution of a program instruction of a first program thread, the first non-partitioned register file including at least one data operand and at least one address operand; and a second non-partitioned register file including a second plurality of registers, the second non-partitioned register file coupled to at least one of the at least one memory unit and coupled to each of the plurality of execution units, the second non-partitioned register file supporting execution of a program instruction of a second program thread, the second register file including at least one data operand and at least one address operand.