1. A method for analyzing a circuit including a memory array, the memory array comprising a plurality of array terminals interconnected with a plurality of memory cells, the method comprising defining a SPICE model for the circuit, wherein defining the SPICE model comprises: defining a set of state variables for each of the plurality of array terminals; and defining a plurality of boundary elements, wherein each of the plurality of boundary elements is associated with one of the plurality of array terminals, and wherein defining the plurality of boundary elements comprises defining a tallying equation set for each of the plurality of boundary elements for tracking a distribution of cell states for the memory cells connected to the array terminal associated with the each of the plurality of boundary elements.