1. A speech analysis device implementing an inverse lattice filter, said speech analysis device comprising: input means for receiving digital signals repesentative of speech; memory means storing a plurality of digital speech parameters representative of filter coefficients; a single multiplier means only, said multiplier means having first and second inputs and an output; said memory means being coupled to said first input of said multiplier means for providing digital speech parameters thereto; a single adder means only, said adder means having first and second inputs and an output; the output of said multiplier means being coupled to said first input of said adder means; said input means being adapted to be coupled to said second input of said adder means; first and second delay means respectively adapted to be coupled to the output of said adder means and to said input means; a first feed-back loop adapted to connect the output of said first delay means to said second input of said adder means; a second feed-back loop connecting the output of said second delay means to said second input of said multiplier means; a third feed-back loop adapted to connect the output of said adder means to said second input of said adder means; first sequentially operable switching means interposed between the output of said adder means and the input of said first delay means and between said input means and the input of said first delay means and sequentially positionable in at least a first switching position connecting the output of said adder means to said first delay means but disconnecting said input means from said first delay means, and a second switching position connecting said input means to said first delay means but disconnecting the output of said adder means from said first delay means; second sequentially operable switching means interposed between the output of said adder means and the input of said second delay means and between said input means and the input of said second delay means, said second delay means being serially arranged with respect to said first switching means, said second switching means being sequentially positionable in a first switching position connecting the input of said second delay means to the output of said adder means but disconnecting said input means from said second delay means, and a second switching position connecting said input means to said second delay means but disconnecting the output of said adder means from said second delay means; third sequentially operable switching means interposed between said input means and said second input of said adder means and sequentially positionable in a plurality of switching positions to alternatively connect said input means to said second input of said adder means, to complete said third feed-back loop connecting the output of said adder means to said second input of said adder means, and to complete said first feed-back loop connecting the output of said first delay means to said second input of said adder means; and fourth switching means interposed in the output of said adder means at a position independent of said first and second switching means, said fourth switching means normally being open but closing at a predetermined time interval to enable the output of said adder means to provide an output signal of the speech analysis device.