1. A computer comprising: an information bus for connection to an external memory containing a user program in a plurality of memory locations and for connection to a console; a plurality of internal registers and multiplexers and a program counter coupled to said information bus; an arithmetic logic unit for doing arithmetic and logical functions and coupled to said information bus via said multiplexers and registers; a programmable logic array (PLA) for coupling to said console via said information bus and coupled to said internal registers, said program counter, said multiplexers and said arithmetic logic unit, said PLA having microcode stored therein, said PLA also for receiving a selected, predetermined code word from said console on said information bus thereby causing said PLA to generate a predetermined sequence of microinstructions to be executed by said computer to cause a selected one of several events to occur, said events including, writing data to or reading data from any of said internal registers, or any location in said external memory, or said program counter, said PLA also for executing a self-test sequence of microinstructions upon receipt of a predetermined code word from said console said test routine for testing the ability of a majority of the registers, multiplexers and data paths to function correctly and for testing a majority of the arithmetic and logical functions of said arithmetic logic unit.