1. A processor, comprising: at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including branch target address prediction circuitry concurrently holding: a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address, wherein said first entry indicates a first instruction address type for the first instruction fetch address; and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address, wherein the second entry indicates a second instruction address type for the first instruction fetch address.