1. A memory circuit, comprising: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing a potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell, wherein the sense timing differs in accordance with a position of the selected memory cell in the memory cell array.