1. A non-volatile memory storage system, comprising: a non-volatile storage array; an interface to a host system, the interface configured to receive a command from the host system; and a processor configured to process the command, the processor including: a high performance path, including a pre-allocated memory buffer, capable of submitting a plurality of parallel command accesses to the storage array, the high performance path configured to reduce command processing delay, and a low performance path capable of submitting a plurality of sequenced command accesses to the storage array, the low performance path including a set of buffers for storing data corresponding to the plurality of sequenced commands, wherein the processor is configured to perform a first determination, the first determination comprising a determination of whether the command is suitable for processing with the high performance path, wherein the processor is further configured to perform a second determination, the second determination comprising a determination of whether a subsequent command received by the interface is to be processed with the low performance path, wherein the second determination is based at least in part on the first determination, and wherein the processor is further configured to, in response to determining that the command is not suitable for processing with the high performance path, disable the high performance path until a threshold number of commands are successfully processed via the low performance path.