1. A method of data processing in a data processing system including a processor core having a store-through upper level cache and a store-in lower level cache, a memory controller, and a memory-mapped device, the method comprising: the processor core executing a memory move instruction sequence, wherein the executing includes: in response to a first instruction, the processor core generating a copy-type request specifying a source real address and transmitting the copy-type request to the lower level cache; in response to a second instruction, the processor core generating a paste-type request specifying a destination real address associated with the memory-mapped device and transmitting the paste-type request to the lower level cache; in response to the copy-type request, the lower level cache copying a data granule from a storage location specified by the source real address into a non-architected buffer; and in response to the paste-type request, the lower level cache issuing a command to write the data granule from the non-architected buffer to the memory-mapped device associated with the destination real address; and in response to receipt from the memory-mapped device of a busy response to the command, the processor core abandoning execution of the memory move instruction sequence and performing alternative processing.