1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions; and an optimizing compiler residing in the memory and executed by the at least one processor, the optimizing compiler including a strength reduction mechanism that analyzes the computer program in a single pass, determines whether an operation in the computer program that has an unknown stride at compile-time could be improved by substituting at least one alternative instruction for at least one original instruction in the operation, and when the operation in the computer program that has an unknown stride at compile-time could be improved, substituting the at least one alternative instruction for the at least one original instruction, wherein the strength reduction mechanism determines whether an operation in the computer program that has an unknown stride at compile-time could be improved by computing a number of operations to execute the at least one alternative instruction, computing a number of operations to execute the at least one original instruction, and when the a number of operations to execute the at least one alternative instruction is less than the a number of operations to execute the at least one original instruction, determining the operation in the computer program could be improved.