1. A method to formally verify a circuit design, the method comprising: simplifying a first set of assumptions to obtain a second set of assumptions, wherein the second set of assumptions is logically equivalent to the first set of assumptions, and wherein the first set of assumptions and the second set of assumptions correspond to allowable input assignments for the circuit design; associating, by computer, a first subset of assumptions with an assertion in a set of assertions, wherein the first subset of assumptions is a subset of the second set of assumptions, and wherein satisfying the assertion corresponds to a desired behavior of circuit design; modifying the first subset of assumptions to obtain a second subset of assumptions which is not logically equivalent to the first subset of assumptions; and proving that the circuit design satisfies the assertion when the second subset of assumptions is satisfied.