1. A computer comprising: plural word-length registers including a result register having plural subword locations; an instruction decoder for decoding computer-executable program instructions, said program instructions being program-instruction instances of instruction-set instructions of an instruction set; and an execution unit for executing said program instructions; said instruction set including a subset of one or more parallel-subword instruction-subset instructions all program-instruction instances of which yield the same subword-length operation result given the same word-length operands, said subset being characterized in that for each of said plural subword locations there exists a series of program-instruction instances of said instruction-subset instructions for which a last program-instruction instance of said series writes a subword-length operation result into that subword location, a first program-instruction instance of said series writing said subword-length operation result into said result register.