1. A three dimensional semiconductor memory device, comprising: a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, the first string selection gates being disposed over an uppermost cell gate of the cell gates; vertical active patterns extending through the first string selection gates, each vertical active pattern extending through each of the cell gates stacked under the first string selection gates; multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates; and at least one first supplement conductive pattern, the first supplement conductive pattern being in contact with a sidewall of one of the first string selection gates.