1. A bridge for a multi-processor system, the bridge comprising a first I/O bus interface for connection to a first I/O bus for a first processing set, a second I/O bus interface for connection to a second I/O bus for a second processing set, a device bus interface for connection to a device bus, a bridge control mechanism configured to be operable to compare address and data phases of I/O accesses by the first and second processing sets and at least one dissimilar data register for each processing set, wherein the bridge control mechanism is configured to be operable in response to an address phase of a dissimilar data register write access to disregard any differences in data for the dissimilar data write access.