1. A method of predicting branch instructions in a processor, comprising: storing an entry in a Branch Target Address Cache (BTAC), the BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken, the BTAC entry having a tag associated with a full address of the first instruction in the block; and upon fetching a group of instructions, accessing the BTAC to determine if an instruction in a corresponding block of instructions is a taken branch instruction.