1. An apparatus for executing application code having multiple instruction set architectures, the apparatus comprising: one or more processors; physical memory, coupled with the one or more processors, and configured to store application code to be loaded into the physical memory for execution by the one or more processors, including first code compiled according to a first instruction set architecture and second code compiled according a second extended instruction set architecture of the first instruction set architecture; and a runtime environment, having a sandbox for execution of the second code, to be loaded into the physical memory and operated by the one or more processors, to: insert a switch gate associated with a switch between the first and second instruction set architectures; intercept, during execution of the application code, an interaction associated with the first code or the second code; and adapt, during the execution of the application code and using the switch gate, the intercepted interaction from the first instruction set architecture to the second instruction set architecture or from the second instruction set architecture to the first instruction set architecture.