1. A multiplier accumulator block on an integrated circuit, comprising: first, second, and third inputs directly coupled to external configurable interconnect circuitry that is formed outside of the multiplier accumulator block; an output; a first arithmetic operator stage that receives signals from the first and second inputs; a second arithmetic operator stage that receives signals from the third input and has an output port that is coupled to the output; internal configurable interconnect circuitry that is formed within the multiplier accumulator block and that includes: a first multiplexer that selects between signals generated from the first arithmetic operator stage and signals generated at the output port of the second arithmetic operator stage.