1. An apparatus, comprising: a memory device, comprising: a plurality of subarrays of memory cells, the plurality of subarrays including a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays; first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component; second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier and no compute component; and a controller configured to direct: a movement of a data value to a selected subarray in the first subset responsive to determining that an in-memory logical operation is to be performed on the data value; and the movement of the data value to a selected subarray in the second subset responsive to determining that an in-memory logical operation is not to be performed on the data value; and wherein the compute component of the first sensing circuitry is configured to operate as a one bit processing element on data values to perform in-memory logical operations on the data values provided to the first sensing circuitry.