1. A method of storing data cache content in a microprocessor, comprising the steps of: recognizing in a pipeline for instructions a runahead after a data cashe miss, and when an address generation interlock (AGI) potential penalty is encountered during the recognized runahead, a AGI pertinent data calculation used to resolve an AGI is stored in a value table (AVT) if first resolved with a pertinent data calculation and the pertinent data calculation used to resolve the AGI, and subsequently, when the same potential AGI penalty is encounterd outside of the runahead, the AGI is re-executed and the pertinent data calculation later retrieved based upon the instruction address of an instruction which is accessing the data cache.