1. A multi-core processor comprising: a first processing core and a second processing core, each including one or more arithmetic logic units and an instruction decoder; wherein the first processing core is capable of operating at a higher processing throughput than that of the second processing core, wherein the first and second processing cores have different instruction sets; wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred from the first processing core to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core; and wherein instructions to run on the second processing core are to be translated from the instruction set of the first processing core to the instruction set of the second processing core by a software binary translation shell, wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.