1. A method stored on a computer readable medium for providing a bitwise constraint for computer based test generation for design verification via device simulation, the method comprising: encoding a processing device according to a language structure for expressing the bitwise constraint, said language structure including at least one constraint parameter and at least one operator, said constraint parameter being further constrained to an interval containing at least one value, said interval having interval limits; actuating the processing device to propagate information bi-directionally to determine interval limits for said constraint parameters at least partially according to the bitwise constraint; and actuating the processing device to compute one or more permissible values for the constraint parameter, thereby to resolve arithmetic and bitwise constraints together.