1. A laser programmable read only memory suitable for incorporation into a monolithic integrated circuit, said circuit including a plurality of transistors, each of which has a pair of controlled conduction electrodes and a control electrode, and a surrounding field oxide, said memory comprising: a plurality of memory locations arranged in a configuration of columns and rows, each location comprising one of said transistors and severable link means coupled in series therewith; word line means associated with each row of said configuration and coupled to each transistor in said row, means connected to each word line means for electrically actuating said word line to a first logic state; address line means associated with each column of said configuration, said address line means coupled to said control electrode of each of said transistors in said column, whereby when said address line is electrically operated to turn said transistors on, the transistor by way of said severable link means will actuate said word line means to a second logic state.