1. A semiconductor storage device, comprising: an input controller including a register, a comparator, and a mode controller; and a content-addressable memory block connected to the input controller, the content-addressable memory block comprising a plurality of word circuits, wherein each of the word circuits comprises: a k-bit 1st-stage sub-word circuit connected to a first search line of the input controller; an (n-k)-bit (where n-k>k) 2nd-stage sub-word circuit connected to a second search line of the input controller, and a segmentation circuit connected between the 1st-stage sub-word circuit and the 2nd-stage sub-word circuit, the 2nd-stage sub-word circuit comprises: a plurality of local match circuits, each having a sub-sub-word circuit connected thereto; and a global match circuit, the input controller sends a search word to the sub-sub-word circuit of each of the local match circuits in parallel, the local match circuits judge a match between the search word and a stored word in the sub-sub-word circuit of each of the local match circuits, and the local match circuits output to the global match circuit.