1. A method for verification of a hardware system-under-test including at least one processor, the method comprising: embedding in an executable image of a hardware exerciser, which is adapted to control a test cycle of the hardware system-under-test, data corresponding to architectural knowledge of the system-under-test, testing knowledge of the system-under-test, and a test template for the system-under-test, wherein said test template is defined in a context-free formal language and includes biasing directives to control one or more parameters of a randomly generated test of said system-under-test.