1. A method for determining scan chain correspondence between a reference design level and an implementation design level of an integrated circuit, comprising: defining a reference scan chain at the reference design level having reference latches and reference constraints, each of the reference latches having a reference latch logic cone, each of the reference constraints having a reference constraint logic cone with at least one reference constraint logic cone input and being associated with at least one of the reference latches wherein each of the reference latch logic cones has at least one reference latch logic cone input; defining an implementation scan chain at the implementation design level having implementation latches and at least one implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with at least one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with any associated implementation constraint logic cone, wherein the determining includes determining a reference constrained function for each of the reference latches from the reference latch logic cone for the reference latch and any reference constraint logic cone for the reference constraint associated with the reference latch by constructing a reference latch function for each of the reference latches from the reference latch logic cone for the reference latch, constructing a reference constraint function for each of the reference constraints from the reference constraint logic cone for the reference constraint, determining for each of the reference latches whether at least one of the reference latch logic cone inputs for the reference latch is the same as at least one of the reference constraint logic cone inputs, defining the reference latch function as the reference constrained function when at least one of the reference latch logic cone inputs for the reference latch is not the same as at least one of the reference constraint logic cone inputs, ANDing the reference latch function and the reference constraint function to generate an intermediate reference function having an intermediate reference logic cone with intermediate reference logic cone inputs for each of the reference latches when at least one of the reference latch logic cone inputs for the reference latch is the same as at least one of the reference constraint logic cone inputs, determining for each of the reference latches having an intermediate reference function whether at least one of the intermediate reference logic cone inputs for the reference latch is the same as at least one of the reference constraint logic cone inputs, ANDing the intermediate reference function and the reference constraint function to modify the intermediate reference function for each of the reference latches having an intermediate reference function when at least one of the intermediate reference logic cone inputs for the reference latch is the same as at least one of the reference constraint logic cone inputs, repeating the determining for each of the reference latches having an intermediate reference function whether at least one of the intermediate reference logic cone inputs for the reference latch is the same as at least one of the reference constraint logic cone inputs and the ANDing the intermediate reference function and the reference constraint function to modify the intermediate reference function until no additional intermediate reference logic cone inputs for the reference latch are the same as the reference constraint logic cone inputs, and simplifying the intermediate reference function to generate the reference constrained function; determining an implementation constrained function for each of the implementation latches from the implementation latch logic cone for the implementation latch and any implementation constraint logic cone for the implementation constraint associated with the implementation latch; comparing the reference constrained functions and the implementation constrained functions; and merging the reference latches and the implementation latches for which the reference constrained functions match the implementation constrained functions.