1. A system for executing variable width vector processing instructions, comprising: at least one vector register, operable to store a vector; at least one processing unit, communicably coupled to the at least one vector register, operable to execute code of at least one program that includes at least one variable vector processing instruction and at least one vector register width instruction and to supply a width of the at least one vector register in response to executing the at least one vector register width instruction; wherein the at least one processing unit processes the at least one variable vector processing instruction utilizing the at least one vector register with a vector width of the width of the at least one vector register supplied by the at least one processing unit.