1. In a computer system including one or more computer processors and a common memory means for storing instructions and data, each of said computer processors including an instruction decode means for receiving, decoding and executing said instructions and a plurality of memory ports, each of said memory ports including pipeline means for storing a plurality of memory requests each of said memory ports accessing said memory means in response to the execution of any one of said instructions, a selection apparatus for queuing said memory requests whereby said memory requests execute in the order issued by said instruction decode means said instructions including one or more mark instruction and one or more wait instruction separate from said mark instruction inserted by a compiler in a sequence of instructions upon identification of a memory hazard by said compiler in said sequence of instructions said selection apparatus comprising: mark means for identifying all memory requests which are stored in said pipeline means as marked memory requests in response to the execution of said mark instruction when issued by said instruction decode means; means for generating said mark instruction in response to detection of said memory hazard; wait means for preventing in response to said wait instruction being issued by said instruction decode means the execution of any additional memory requests until all of said marked memory requests are queued by said selection apparatus whereby said marked memory requests are guaranteed to execute in the order issued by said instruction decode means; means for generating said wait instruction after said mark instruction has been generated in response to detection of said memory hazard.