1. A method for optimized buffer placement based on timing and capacitance assertions in a functional chip unit comprising a single source and multiple macros, each having a sink, wherein the placement of the source and the macros with the sinks is pre-designed and the buffers are placed in branches connecting the source with the multiple sinks, the method comprising: calculating an estimated slack for each branch based on cycle reach, arranging the branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the at least one most critical branch and placing decoupling buffers close to the source, globally routing the at least one most critical branch and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this at least one branch, and routing all remaining branches.