1. A field programmable gate array (FPGA), comprising: an input data bus coupled to receive a plurality of configuration data values in parallel; an input register coupled to receive the configuration data values from the input data bus, the input register having a width of N bits; a shadow input register coupled to receive the configuration data values from the input register, the shadow input register having a width of N bits; a multiplexer array coupled to receive the configuration data values from the input register and the shadow input register, the multiplexer array having an output width of M bits, wherein M is greater than N; a configuration register coupled to receive the configuration data values from the multiplexer array, the configuration register having a width of M bits; and a configuration memory array coupled to receive the configuration data values from the configuration register.