1. A method for emulating a guest instruction set architecture on an integrated circuit, the integrated circuit comprising a plurality of processor cores associated with a host instruction set architecture, the method comprising: providing a spatial pipeline mapping to pass results of execution of a plurality of host processes that emulate guest functions performed in native instruction set architecture; receiving by the plurality of processor cores guest instructions of the guest instruction set architecture, with each of the processor cores comprising a processor and a switch for interconnecting the processor cores; running the plurality of host processes on a respective set of the plurality of processor cores, the host processes including instructions of the host instruction set architecture that emulate native hardware of the guest instruction set architecture; and providing results of a first of the host processes to a second of the host processes according to the spatial pipeline mapping to execute the guest instructions.