1. In a pipelined processor comprising an instruction control unit, a method for queuing and requeuing instructions for said instruction control unit, said method comprising the steps of: a) queuing a plurality of sequential instructions in a sequential instruction queue; b) queuing a plurality of branch target instructions in a branch target instruction queue; c) providing selected ones of said sequential and branch target instructions from said sequential and target instruction queues to said instruction control unit; and d) requeuing said instructions provided to said instruction control unit into said sequential queue if said provided instructions are not issued for execution by said instruction control unit.