1. A digital fuzzy logic system comprising: a source of a plurality of input signal values; a processor; a memory connected to said processor for storing data and for further storing instructions which are executable by said processor for manipulating said data, and a utilization device connected to said processor and responsive to a digital output signal value produced by said processor; wherein said processor and said memory operate cooperatively to form a fuzzy logic controller comprising: means for processing said input signal values into a corresponding set of input integer values; means for storing plural sets of function definition values, means for storing instructions for performing a plurality of different standard membership functions, each of said functions when executed producing a degree-of-membership value in accordance with the combination of a supplied integer value and a specified one of said sets of function definition values; means for storing data representative of a plurality of rules, each of said rules specifying at least: (a) a first one of said input integer values, (b) a first one of said sets of function definition values, (c) a first one of said standard membership functions, (d) a second one of said set of function definition values, and (e) a second one of said standard membership functions; means responsive to each given one of said rules for forming a strength value for said rule, said means comprising: means for executing said first standard membership function specified in said given rule to produce an intermediate integer value in accordance with the first input integer value specified by said given rule and the first set of function definition values specified by said given rule, and means for executing said second standard membership function specified by said given rule to produce said strength value for said given rule in accordance with said intermediate integer value and the second set of function definition values specified by said given rule; and means for producing said digital output signal value by forming the weighted combination of the strength value formed in response to each of said plurality of rules.