1. A method for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory with a faster speed than the first memory and a third memory with a faster speed than the second memory, the method comprising: examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; and filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instruction, such that the processor core fetches the at least one or more instructions from the third memory.