1. A logic circuitry comprising logic components forming equality nodes and parity check nodes, the equality nodes and the parity check nodes for performing an equality function and a parity check function in a stochastic decoding process, respectively, the equality nodes and the parity check nodes being electrically coupled such that they represent a factor graph of a parity check matrix of a linear code, the logic circuitry comprising a plurality of counter circuitries, each counter circuitry comprising a counter electrically coupled to a respective equality node, each counter circuitry for providing a chosen symbol in dependence upon the respective equality node being in a hold state.