1. A method of invalidating translation entries without deadlock in a multithreaded data processing system including a plurality of processor cores, the method comprising: receiving, in a shared queue, storage-modifying requests of a plurality of concurrently executing hardware threads of an initiating processor core among the plurality of processor cores, wherein the plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread among the plurality of hardware threads; in response to receiving the translation invalidation request in the shared queue, removing the translation invalidation request from the shared queue and buffering the translation invalidation request in sidecar logic; while the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasting the translation invalidation request such that the translation invalidation request is received and processed by the plurality of processor cores; in response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removing the translation invalidation request from the sidecar; ensuring completion of processing of the translation invalidation request at all of the plurality of processor cores by a broadcast synchronization request; and ordering subsequent memory referent instruction with reference to the broadcast synchronization request by execution of a synchronization instruction.