1. A microprocessor chip, comprising: instruction pipeline circuitry; instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value; an on-chip table, each entry of the on-chip table corresponding to a range of addresses of a memory of the computer and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer; lookup circuitry designed to fetch an entry from a on-chip table as part of the basic instruction processing cycle of the microprocessor; a mask whose value is set at least in part by a timer; pipeline control circuitry designed to consult the on-chip table and to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the on-chip table entry corresponding to the address of an instruction processed by the instruction pipeline circuitry, the current value of the mask, and the recorded classification code; and control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to control operation of the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.