1. A video processor for implementing forward transform, in compliance with a version of the H.264 standard, said video processor comprising: an input for receiving a block of image data, said data comprising a plurality of pixel data; an internal register for storing said plurality of pixel data; a multiplier, comprising a register storing fixed values representing a transform matrix, wherein said multiplier is configured to receive Single Instruction Multiple Data (SIMD) instructions from a software control structure, wherein in response to receiving a first transform SIMD instruction, said multiplier operable to perform a 1-D transform of said plurality of pixel data using said transform matrix, operable to produce a partially transformed plurality of pixel data, and further operable to write said partially transformed plurality of pixel data directly in a transposed manner to said internal register as transposed plurality of pixel data, and wherein said multiplier is operable to transpose said partially transformed plurality of pixel data during said write to save processor cycles; and wherein upon receiving a second transform SIMD instruction, said multiplier is operable to perform a 1-D transform of said transposed plurality of pixel data using said transform matrix, producing a transformed plurality of pixel data, and is operable to write said transformed plurality of pixel data directly in a transposed manner to said internal register to save processor cycles.