1. A method of synthesis of multiple implementations of an integrated circuit design, comprising: providing a model of the design comprising an algorithm implemented by the design; using a computer system to perform steps of: providing a first constraint file including at least one first constraint upon implementation of the model; inputting the model of the design and the first constraint file to a synthesis tool; receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint; providing a second constraint file including at least one second constraint upon implementation of the model; inputting the model of the design and the second constraint file to the synthesis tool; receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint; changing the model of the design to produce a changed model of the design; inputting the changed model of the design and the first constraint file to the synthesis tool; and receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.