1. A method for testing an integrated circuit having a hardwired embedded core and memory, the memory being coupled to the embedded core in the integrated circuit, the method comprising: writing a test vector to the memory while the embedded core is operative; inputting the test vector from the memory to the embedded core to mimic scan chain input to the embedded core; obtaining a test result from the embedded core responsive in part to the test vector input; loading a portion of the test vector into a shift register of a first controller; outputting the portion of the test vector from the shift register into a second controller for subsequent writing to the memory; and wherein the writing of the portion of the test vector is from the second controller to the memory.