1. A system for coordinated data execution in a computer system, comprising: a graphics processor including a first functionality table; a core logic component including a second functionality table coupled to a system memory; and a graphics bus coupling the graphics processor and the core logic component, wherein the graphics processor and the core logic component implement a configuration communication to determine a nonstandard mutually supported coordinated data execution mode by the graphics processor accessing the first functionality table and the core logic component accessing the second functionality table to identify a cooperative processing function supported by the graphics processor and the core logic component and to selectively configure the coordinated data execution mode between the graphics processor and the core logic component via communication across the graphics bus.