1. A method in a processor for semi-synchronously copying data from a first portion of memory to a second portion of memory, the method comprising: receiving, in a processor, a call for a semi-synchronous memory copy operation which preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit, wherein preserving temporal persistence of validity includes preventing at least one of a load operation and a store operation to at least one of the source location and the target location during the semi-synchronous memory copy operation, the call including at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied, wherein the semi-synchronous memory copy operation operates semi-synchronously with the processor to provide maximum processor utilization such that the processor is able to execute at least one additional instruction during the semi-synchronous memory copy operation; placing in a queue the memory copy operation for execution by a memory controller, wherein the queue is coupled to the memory controller; continuing to execute at least one subsequent instruction during the semi-synchronous memory copy operation as the subsequent instruction becomes available from an instruction pipeline.