1. A branch predictor having a fetch address input on which a fetch address is received during use, wherein the fetch address is also input to an instruction cache to fetch instructions, the branch predictor comprising: a plurality of branch predictor tables, each branch predictor table indexed using a different index generated from a different combination of the fetch address, a path history, and a global history, wherein each branch predictor table comprises a plurality of entries, wherein each entry of the plurality of entries corresponds to a cache line in the instruction cache, and wherein a fetch group that begins at the fetch address crosses a cache line boundary for at least some values of the fetch address, and wherein a selected entry of the plurality of entries is selected in response to the different index provided to the branch predictor table, and wherein the selected entry and a consecutive entry of the branch predictor table each store a plurality of branch prediction values that correspond to potential branches in the cache lines that correspond to the selected entry and the consecutive entry, and wherein a subset of the plurality of branch prediction values from the selected entry and the plurality of branch prediction values from the consecutive entry are selected responsive to the fetch address and are combined to form a plurality of branch predictions corresponding to potential branches in the fetch group, wherein the subset corresponds to portions of the corresponding cache lines that are within the fetch group; and a control circuit coupled to the plurality of branch predictor tables and configured to generate the indexes and select the plurality of branch prediction values.