1. A processing device for use in a communication system, the device comprising: scheduling circuitry configured to schedule data blocks for transmission from a plurality of transmission elements in timeslots of a frame, utilizing at least a mapping table; the mapping table comprising at least one entry specifying a mapping between a particular timeslot of the frame and a particular one of the transmission elements; the scheduling circuitry being further configured to determine a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry to identify the particular transmission element; and memory circuitry associated with the scheduling circuitry and configurable to store at least a portion of the mapping table in a compressed format; the mapping table being stored as a compressed mapping table in which a particular entry identifies one of a plurality of stored values which is processed to determine a corresponding uncompressed mapping table entry.