1. A computer-implemented method of verifying timing of a multi-phase, multi-frequency and multi-cycle circuit with level sensitive latches, comprising: generating an event graph of nodes for paths in the circuit including at least one level-sensitive latch; identifying clock phases of destination memory elements in the circuit corresponding to all nodes included in said event graph; identifying late arrival times for the all nodes included in said event graph with respect to a plurality of clock phases; and tracing back from the destination memory elements to find a failing path in the circuit, wherein one or more of the generating, identifying clock phases, identifying late arrival times, and tracing steps are implemented by a computer.