1. A microprocessor, comprising: an instruction cache; a trace cache; and a prefetch unit coupled to the instruction cache and the trace cache; wherein the prefetch unit is configured to prefetch instruction code from a system memory for storage within the instruction cache, wherein the system memory is distinct from the instruction cache and the trace cache, wherein the prefetch unit is further configured to prefetch a line of instructions from the system memory into the instruction cache in response to a trace being evicted from the trace cache, wherein the line of instructions is not currently needed for execution, wherein the line of instructions prefetched from the system memory is dependent on contents of the trace evicted from the trace cache, and wherein the line of instructions is prefetched in anticipation of instructions included in the evicted trace being re-executed.