1. A hardware system for providing branch misprediction prediction in a microprocessor, said system comprising: a mispredicted branch table that includes address, distance, and true/not true fields; and an index to the mispredicted branch table that is formed responsive to 1) a current mispredicted branch, 2) a global history, 3) a global misprediction history, and 4) a branch misprediction distance, wherein a plurality of incorrect predictions are required to evict a mispredicted branch table entry to protect the mispredicted branch table entry from being evicted based on a single misprediction or aliasing event only.