1. A system comprising: a processor comprising: a plurality of registers; an instruction decoder to decode a shift right merge instruction indicating a first 32-bit source operand and a second 32-bit source operand, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements; and an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to: shift the second 32-bit source operand right by one byte; merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of the shifted second 32-bit source operand to generate a result; and store the result in a 32-bit destination indicated by the shift right merge instruction; a Bluetooth universal asynchronous receiver/transmitter (UART) interface; a universal serial bus (USB) interface; a synchronous dynamic random access memory (SDRAM) control interface; and a flash interface.