1. A programmable logic device (PLD) comprising: PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD; a logic analyzer integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer; a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD; and a plurality of I/O cells arranged to receive command signals from said JTAG port and to provide said command signals to said logic analyzer.