1. A computing device comprising: an instruction decoding unit that decodes a multiple data processing instruction performing a processing operation on multiple data including first data and second data; a plurality of first allocatable registers to hold data; a plurality of second allocatable registers to hold data; an allocatable register selection unit that selects one of the first allocatable registers and one of the second allocatable registers based on a decoding result of the multiple data processing instruction, respectively; a first processing unit that performs first processing on the first data based on the decoding result of the multiple data processing instruction and makes the selected first allocatable register hold a first processing result obtained as a result of the first processing; a second processing unit that performs second processing on the second data based on the decoding result of the multiple data processing instruction and makes the selected second allocatable register hold a second processing result obtained as a result of the second processing; a first result register that stores the first processing result held in the selected first allocatable register; and a second result register that stores the second processing result held in the selected second allocatable register.