1. A method of performing statistical timing analysis of a logic design, including effects of signal coupling, comprising: performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design; performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair; and using the statistical effective capacitance to determine timing data used in the statistical timing analysis.