1. A chip comprising: a memory having a plurality of non-redundant memory lines and a plurality of redundant memory lines; and a first circuit being operable to allocate a redundant memory line to a failed memory line, the first circuit being further operable to detect a failure in a memory line during runtime and to compile a first list of such failed memory lines; and a second circuit being operable to read a second list of any failed memory lines generated during manufacture of the chip and to merge the first list with a second list, the second circuit being further operable to allocate a redundant memory line for each of the failed memory lines of the merged list.