1. The Reduced-Width Low-Error Multiplier method, wherein makes proper compensation in accordance with the values of a multiplicator and a multiplicand. If a multiplicand X, has a bit length of m and is denoted by X m-1... X 1... X 0, and a multiplicator Y, has a bit length of n and is denoted by Y n−1... Y j... Y 0, then the product term PD, will have (m&plus;n−p) bits and is denoted by PD m&plus;n−1... PD n... PD p. i is the ith bit of a multiplicand X, while j is the jth bit of a multiplicator Y; The compensation signal is &bgr;, which is the sum of x i y j when i&plus;j&equals;p−1. 14 β = &Sum; i + j = p - 1 &it; x i &it; y j = x p - 1 &it; y 0 + x p - 2 &it; y 1 + … &it; + x 1 &it; y p - 2 + x 0 &it; y p - 1 And, p is the bit length of the product term to be removed. A reduced-width low-error multiplication operation can be created, by adding the value of &bgr; directly to the vertical column at the end of the right hand side of the reserved summand.