1. An apparatus for performing floating-point arithmetic operations comprising: a near processing path circuit; a far processing path circuit in parallel with the near processing path circuit; an input data bus for providing first and second floating point operands to the near processing path circuit and the far processing path circuit substantially simultaneously, wherein each of the first and second floating point operands include a sign-bit, a mantissa, and an exponent, wherein the near processing path circuit generates a plurality of exponent difference signals as a function of a pattern of exponents in the first and second floating point operands, wherein the near processing path circuit generates a near path subtraction result based on the exponent difference signals, wherein the near processing path circuit computes an exponent difference of the first and second floating point operands, and wherein the near processing path circuit generates an exponent difference signal based on the computed exponent difference, wherein the near processing path circuit generates GT, LT, and EQ exponent difference signals as a function of the pattern of exponents of the first and second floating point operands based on the equations: 
 GT =(EXPsame[1] and X EXP[0] and ˜ Y EXP[0]) or 
 (EXPdiffr[1] and YEXP[0] and ˜XEXP[0]), 
 LT =(EXPsame[1] and Y EXP[0] and ˜ X EXP[0]) or 
 (EXPdiffr[1] and XEXP[0] and ˜YEXP[0]), and 
 EQ=EXPsame[0], and wherein “˜” denotes inversion, EXPsame[i]=XEXP[i] xnor YEXP[i], and EXPdiffr[i]=XEXP[i] xor YEXP[i], and GT, LT, and EQ are the exponent difference signals, and wherein the far processing path circuit computes a mantissa difference of the first and second floating point operands, and wherein the far processing path circuit generates a far path subtraction result based on the computed mantissa difference, if the computed exponent difference is not equal to 0, 1, or −1; and a final result multiplexer coupled to the near processing path circuit and the far processing path circuit that selects and outputs either the far path subtraction result, the near path subtraction result, or a standard result based on the generated exponent difference signal, wherein the standard result is selected based on a status of the near path or the far path subtraction result.