1. A computer implemented method of generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology, the method comprising: obtaining a process technology independent layout representation associated with the circuit component, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations; providing a mapping database having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology; for selected grid locations within the grid array, performing a lookup operation in the mapping database to determine a matching mapping entry, the matching mapping entry being a highest priority mapping entry within the priority ordered list whose process technology independent layout section matches a portion of the process technology independent layout representation at that selected grid location; and generating the layout of the cell by incorporating, at each of the selected grid locations, the layout pattern section for the target process technology stored in the matching mapping entry.