1. A processor core comprising: a shared memory having a plurality of banks, each bank comprising a plurality of addressable storage locations and each bank accessible by two or more of a plurality of processing engines, wherein addressable storage locations in different banks are accessible in parallel; the plurality of processing engines each having a unique identifier and adapted to generate a plurality of requests to the shared memory in parallel, each request specifying a target address in the shared memory; and conflict logic coupled between the processing engines and the shared memory, the conflict logic being adapted to: receive the plurality of requests from the plurality of processing engines including two or more requests for a selected one of the plurality of banks; select a satisfiable set from the received requests, the satisfiable set including requests specifying at most one target address in each of the plurality of banks; and deliver the satisfiable set of requests in parallel to the shared memory, wherein the conflict logic comprises a conflict detection module and decision logic, wherein the conflict detection module is adapted such that the requests have a priority ranking, wherein in the event that the target addresses for two of the requests are in the same bank, the conflict detection module asserts a conflict signal corresponding to the request with the lower priority, wherein the decision logic is coupled to the conflict detection module and adapted to determine, based at least in part on the conflict signal, which of the requests to include in the satisfiable set, the processing core further comprising: an instruction unit adapted to issue a same instruction from a sequence of instructions in parallel to all of the processing engines, wherein the sequence of instructions includes a first instruction to request access to the shared memory, wherein the conflict logic is further adapted to signal the instruction unit to issue the first instruction again to any of the processing engines for which the request was not included in the satisfiable set.