1. A system for emulation of multiple electronic designs in a single testbench on FPGA or Emulation system, said system comprising: stimulus generation logics; a bus coupled with said stimulus generation logics; a deselection unit connected to the bus; and selection unit; wherein, a wrapper design is created to run multiple instance(s) of a design or different design (s) on FPGA or Emulation system to decrease the area, the wrapper design generates a stimulus using the stimulus generation logics which acts as an input to the deselection unit through the bus; the deselection unit passes multiple inputs received from the stimulus generation logic(s) in parallel; and the output of said instance(s) of design or different design(s) are connected to selection unit which selects one output of a design at a time.