1. A fault-tolerant FPGA computation cell, comprising: an original function/error detection code storage unit for storing an original function, or storing a error detection code-1 corresponding to the original function, and for outputting an original function output required to route the original function or a error detection code-1 required to detect an error in the original function when the original function is input; a spare function/error detection code storage unit for storing an spare function or storing a error detection code-2 corresponding to the spare function, and outputting a spare function output required to route the spare function or a error detection code-2 required to detect an error in the spare function when the spare function is input; a totally self checker for receiving the original function output, the error detection code-1, the spare function output, and the error detection code-2, determining whether a fault has occurred in the original function or the spare function, and then outputting a faulty signal_original and a faulty signal_spare; a function router/permanent error indicator for performing an operation on the original function output, the spare function output, the faulty signal_original, the faulty signal_spare, and a stem function input from a stem cell, and then outputting a function routing signal or a permanent error flag signal; and a free router for routing the permanent error flag signal.