1. A method of configuring a programmable integrated circuit device with a user logic design, said method comprising: analyzing said user logic design to identify unidirectional logic paths within said user logic design and cyclic logic paths within said user logic design; assigning said cyclic logic paths to logic in a first portion of said programmable integrated circuit device that operates at a first data rate, and assigning said unidirectional logic paths to logic in a second portion of said programmable integrated circuit device that operates at a second data rate lower than said first data rate; and pipelining said unidirectional logic paths in said second portion of said programmable integrated circuit device to compensate for said lower second data rate.