1. An integrated circuit for stochastic computation, said integrated circuit comprising: circuitry forming a plurality of processing nodes, including a first processing node and a second processing node, each of said processing nodes configured to process an outcome stream having a plurality of outcomes, each of said plurality of outcomes in said outcome stream being in one of a plurality of states, wherein an outcome from said outcome stream is in a particular state with a particular probability; circuitry forming communication links configured to transmit outcome streams between pairs of said plurality of processing nodes; and circuitry forming a delay module on each of said communication links, said delay module configured to delay outcome streams traversing said communication link by an assigned delay; wherein said first and second processing nodes are connected by a plurality of data paths, at least one of which comprises a plurality of communication links, each of said data paths connecting the first and second processing nodes and causing an aggregate delay to an outcome stream traversing said data path; wherein the assigned delays of the communication links traversed by each of said data paths connecting the first and second processing nodes are selected subject to the constraint that no two aggregate delays impose the same delay on an outcome stream.