1. At a defect metrology computing device, a method for correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location, comprising: receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for a portion including the defect location, wherein the physical representation of the semiconductor device is configured to include an electrically significant region defined based on densities of scan cells on the semiconductor device; generating a significance determination indicating whether the defect is located in the electrically significant region in the physical representation of the semiconductor device; and displaying the significance determination.