1. A device for sharing a memory of a microcontroller with an external device said microcontroller having a CPU, said device, comprising: a communication unit for exchanging information between said external device and said memory; bus control circuitry for exchanging information, between said CPU of said microcontroller and said memory, and for generating CPU status signals; memory arbitration circuitry, coupled to said communication unit and to said bus control circuitry, for receiving said CPU status signals and responsive thereto operatively coupling said communication unit to said memory when said CPU status signals indicate that said CPU will not access said memory for a predetermined time.