1. A programmable logic device comprising: memories for logic which are arranged in series to store LUTs (look up tables) of logic functions; plural external input lines for input variables connecting to said memories for logic; one or more memories for interconnection which store(s) information for connection how to select either output lines of said memory for logic of the preceding stage or said external input lines connecting to each input line of said memory for logic of the succeeding stage; and one or more reconfigurable interconnection circuits which connect(s) the output lines of said memory for logic of the preceding stage or the external input lines with the input lines of said memory for logic of the succeeding stage according to the output of said memory for interconnection.