1. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of processor cores, the method comprising: assigning blocks of instructions to a set of one or more processor cores to translate the instructions into translated instructions, the blocks of instructions being associated with an execution order; determining whether a first translated instruction is stored in a cache accessible to an execution processor core, and sending a request from the execution processor core to at least one processor core in the set to translate one or more instructions to generate the first translated instruction if the first translated instruction is not stored in the cache; and executing in the execution processor core the first translated instruction while the set of one or more processor cores are translating instructions that occur later in the execution order than the first translated instruction.