1. A segmented subsystem, for use within an automated test platform, comprising: a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment, wherein the first subsystem segment is at least one of a first instrument card and a first digital signal processing card, and wherein the first subsystem segment includes a first DMA engine configured to allow the first subsystem segment to read data from and/or write data to a remote memory system; one or more PCIe based event fabrics including one or more PCIe switches, the one or more PCIe switches configured to interface one or more CPU subsystems with at least one of the first instrument card and the first digital signal processing card, wherein at least one of the first instrument card and the first digital signal processing card is separate from each of the one or more PCIe switches; and a second subsystem segment including a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment, wherein the second subsystem segment is at least one of a second instrument card and a second digital signal processing card, wherein the first subsystem segment is further configured to provide one or more variable input signals to a device under test for a first defined period of time based on a timing signal, wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the first defined period of time, wherein after expiration of the first defined period of time, the first subsystem segment is further configured to provide one or more variable input signals to the device under test for a second defined period of time based on a timing signal, and wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the second defined period of time.