1. Matrix operations circuitry for performing a vector operation on an input matrix having a first number of columns, said vector operation including operations combining one row of said matrix and each row of said matrix, said matrix operations circuitry comprising: a first set of a second number of column memories, said second number being smaller than said first number, whereby at least one row of said input matrix is stored in multiple rows of said column memories; a vector operations circuit that performs said operations combining a selected row of said matrix and each row of said matrix; a first set of first input registers equal in number to said second number, for inputting each said row to said vector operations circuit from said column memories; a first set of second input registers equal in number to said second number, for inputting said one row to said vector operations circuit; a first circular latch for storing said one row; and selection circuitry for circulating values from said selected row between said first set of second input registers and said first circular latch.