1. A method for quantum gate optimization, the method comprising: reviewing a quantum circuit for sequences of one-wire gates; for one or more sequences of one-wire gates, replacing the one-wire gates of the sequence of one-wire gates with a respective replacement one-wire gate; reviewing the quantum circuit for sequences of logical two-wire gates, wherein at least one sequence of logical two-wire gates includes at least two one-wire gates on different wires, at least two two-wire gates on at least one common wire, or a combination of gates that spans two wires; for one or more sequences of logical two-wire gates, replacing the logical two-wire gates of the sequence of logical two-wire gates with a respective replacement two-wire gate; and storing one or more replacement one-wire gates and one or more replacement two-wire gates in a memory.