1. A method of forming a nonplanar transistor comprising: forming a semiconductor body having a top surface and bottom surface and a pair of laterally opposite sidewalls on an insulating substrate; forming a sacrificial gate electrode above said top surface of said semiconductor body and adjacent to said laterally opposite sidewalls of said semiconductor body, said sacrificial gate electrode having a pair of laterally opposite sidewalls; placing dopants into said semiconductor body on opposite sides of said sacrificial gate electrode to form a pair of source/drain extensions on opposite sides of said gate electrode; forming a pair of sidewall spacers along laterally opposite sidewalls of said sacrificial gate electrode; forming silicon on said semiconductor body adjacent to said sidewall spacers; placing dopants into said silicon and into said semiconductor body in alignment with said sidewall spacers; forming a silicide on said silicon formed on said semiconductor body adjacent to said sidewall spacers; forming a dielectric layer over said silicide, said sacrificial gate electrode and said sidewall spacers; planarizing said dielectric layer until the top surface of said dielectric layer is planar with the top surface of said sacrificial gate electrode and said sacrificial gate electrode is exposed; removing said sacrificial gate electrode to expose the channel region of said semiconductor body and said insulating substrate; removing a portion of said insulating substrate in said opening beneath said semiconductor body to expose at least a portion of said bottom surface of said semiconductor body; forming a gate dielectric layer on said top surface and said sidewalls of said semiconductor body in said opening and on said portion of said exposed bottom surface of said semiconductor body; blanket depositing a gate electrode material on said gate dielectric layer and into said opening and on said gate dielectric layer on said top surface of said semiconductor body, adjacent to said gate dielectric on said sidewalls of said semiconductor body, and beneath said gate dielectric on said exposed portion of said bottom surface of said semiconductor body; and removing said gate electrode material from the top surface of said dielectric film to form a gate electrode.