1. An apparatus for testing a computer processing device comprising: a cache; a main memory; a cache inhibited memory; a first slice of test data is replicated into the cache on the computer processing device; a second slice of test data is replicated into the cache inhibited memory, wherein the second slice of test data is located a minimum distance from the first slice of test data and the minimum distance is at least a granularity of a prefetch operation in the computer processing device; wherein the first and second slices of test data comprise a plurality of segments of test data on non-naturally aligned boundaries that together make a slice of test data, wherein the plurality of segments are non-naturally aligned where the beginning and ending of each of the plurality of segments does not line up with a cache line boundary; wherein the computer processing device executes test code on the first slice of the test data using a base address and then reruns the test code after adjusting the base address with an offset to point to the second slice of the test data where the offset includes the minimum distance.