1. A method of executing a floating-point multiply instruction to account for one or more of denormal inputs and a denormal product, the method comprising: in a denormal support mode: converting the floating-point multiply instruction to a floating-point multiply-add instruction operative to cause a floating-point multiplier to perform a floating-point multiply operation and to cause a floating-point adder to perform a floating-point add operation such that a product of the floating-point multiplier is routed to the floating-point adder, wherein the floating-point multiply instruction is a non-fused floating-point multiply-add instruction, wherein the floating-point multiply-add instruction comprises a floating-point multiply operation and a floating-point add operation, and wherein converting the floating-point multiply instruction comprises: substituting a zero addend for the addend of the floating-point multiply-add instruction; and inserting after the floating-point multiply-add instruction a floating-point add instruction having the addend of the floating-point multiply-add instruction; forcing one addend of the floating-point add operation to zero and presenting a result of the floating-point multiply operation as another addend to the floating-point add operation; using a normalization circuit of the floating-point adder to normalize the result of the floating-point multiply operation; inspecting a multiplier and multiplicand of the floating-point multiply-add instruction; determining, based on the inspection, that a product of the multiply operation will not be a denormal number; determining, based on the inspection, that inputs to the multiply operation are not denormal numbers; and in response to the determinations, replacing the zero addend with the addend of the multiply-add instruction and converting the floating-point add instruction to a no operation (NOP); and when not in the denormal support mode, performing the floating-point multiply instruction in the floating-point multiplier and bypassing the floating-point adder and the normalization circuit.