1. An integrated circuit comprising (i) a memory component and (ii) an integrated circuit, the integrated circuit comprising: a processing core configured to be coupled to a first memory, wherein the first memory is external to the integrated circuit; a second memory internal to the integrated circuit, the second memory containing a first test routine that is to be executed by the processing core when power is applied to the integrated circuit, wherein the processing core executes the first test routine to test the integrated circuit, and a second test routine that is to be executed by the processing core, wherein the processing core executes the second test routine to test the first memory; and an interface coupled to the processing core, wherein the interface is configured to permit activation of an output signal, wherein the output signal indicates a test result from execution of (i) the first test routine or (ii) the second test routine.