1. An egress port queue associated with an egress port of a switch, the egress port queue comprising: a first queue memory being configured to receive and enqueue a pointer corresponding to a received data packet, the first queue memory having a first access time; a second queue memory in communication with the first queue memory, the second queue memory having a second access time, the first access time being shorter than the second access time such that the pointer corresponding to the received data packet may additionally be enqueued in one or more other egress port queues associated with one or more other egress ports of the switch during a single port cycle; and control logic configured to transfer a plurality of pointers from the first queue memory to the second queue memory in a single transfer cycle, the plurality of pointer including the enqueued pointer corresponding to the received data packet and one or more previously enqueued pointers corresponding to one or more previously received data packets.