1. A processing system comprising: a plurality of shadow register sets; an interrupt vector generator, for generating an exception vector associating with an interrupt handler, when the processing system receives an interrupt; shadow set mapping logic, coupled to both said plurality of shadow register sets, and said interrupt vector generator, for selecting one of said plurality of shadow register sets to be used by said interrupt handler; wherein said shadow set mapping logic comprises a plurality of entries, each of which is programmable to associate exception vectors with at least one of said plurality of shadow register sets, wherein each of said entries: corresponds to one of a plurality of exception vectors; and contains data referencing one of said plurality of shadow register sets; wherein the entries are programmable by kernel mode instructions.