1. A built-in, on-chip test system for testing a memory array for array and tag data, comprising: a first subsystem for logically bit-wise XORing corresponding array compare bits and tag address inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches; a second subsystem for further receiving ABIST control logic as an input to either: a. combine array valid bits and tag valid inputs to produce valid output, or b. compare array valid bits with tag valid inputs; and a logical NOR for outputs of the first and second subsystems.