1. A memory device comprising: a plurality of memory tiles, each of which includes a plurality of memory cells; a plurality of word lines each configured to be coupled to a row of the memory cells; a plurality of column select circuits configured to be coupled to each of the memory cells; and a common bit line configured to be coupled to the plurality of column select circuits, the common bit line also coupled to a sense and program circuit; wherein a plurality of subtiles are located in each of the memory tiles.