1. A memory network comprising: memory nodes, wherein each memory node includes memory and memory controller logic; inter-node links connecting the memory nodes with each other, wherein the memory controller logic of a memory node in the memory network is to receive a memory access request from a main memory controller of a processor connected to the memory network and detect an error in data for the memory access, and a resiliency group for the memory node to provide error correction for the detected error, the resiliency group including at least one memory node in the memory network.