1. A method to determine test coverage of a design, comprising: defining a hardware description language (HDL) system architecture within an HLD interface configured to define HLD code, wherein the HLD system architecture comprises a control vector further comprising a binary vector; modifying a component of the HDL system architecture with the HLD interface by operating on the HDL system architecture with the control vector; simulating a functionality of the HDL system architecture with a simulator using a test case of a plurality of test cases to determine if a modification of the component is detected; and verifying a physical system architecture synthesized from the HDL system architecture within a verification tool to determine if the modification of the component is detected.