1. A circuit arrangement, comprising: network on chip hardware logic including a plurality of processing cores defining a plurality of hardware threads and an on chip network coupling the plurality of processing cores to one another; a memory subsystem coupled to the plurality of processing cores and storing a plurality of level of detail components for a plurality of objects in a scene; a physics engine executed by at least a portion of the plurality of hardware threads, the physics engine including a multithreaded software pipeline including a plurality of stages configured to detect collisions between objects from among the plurality of objects; and at least one component loader hardware thread and a plurality of collision detection hardware threads defined among the plurality of stages, the component loader hardware thread configured to retrieve level of detail components for objects in the scene from the memory subsystem and stream each level of detail component to sequences of collision detection hardware threads among the plurality of collision detection hardware threads such that the collision detection hardware threads are able to access the level of detail components streamed thereto without directly accessing the memory subsystem, each collision detection hardware thread allocated to a spatial region of the scene and configured to perform collision detection for the spatial region using the level of detail components streamed thereto, and at least one collision detection hardware thread configured to stream level of detail components to another collision detection hardware disposed later in the multithreaded software pipeline, wherein the plurality of collision detection hardware threads are further configured to detect future collisions between objects in the scene, and wherein the component loader hardware thread is configured to initiate a workload reallocation among the plurality of collision detection hardware threads in response to a detected future collision.