1. A method of identifying memory nodes in a design, the method comprising: for a sequential cell of the design, extracting constraint arcs between constraint and related pins; for each constraint arc, generating an original vector set including initialization waveforms; using a computer, running a plurality of simulations using a plurality of vector sets to generate a plurality of node sets, each simulation generating a corresponding node set that toggles based on waveforms provided by a corresponding vector set, each vector set derived from the original vector set; and calculating a final node set of memory nodes for the sequential cell by subtracting one node set from another node set.