1. An integrated circuit comprising: a plurality of logic elements, said plurality of logic elements divided into plurality of subsets of logic elements; a plurality of first level interconnects, each of said plurality of first level interconnects interconnecting one of said plurality of subsets of logic elements, thereby forming a plurality of first level logical units, said plurality of first level logical units divided into a plurality of subsets of first level logical units; a plurality of second level interconnects, each of said second level interconnects interconnecting one of said plurality of subsets of first level logic units, thereby forming a plurality of second level logic units; and a third level interconnect, said third level interconnect interconnecting said plurality of second level logic units, thereby forming a third level logic unit.