1. A method of testing a target electronic device, wherein the target electronic device is to be implemented in a particular configurable integrated circuit device, comprising: receiving a baseline design for the target electronic device in a hardware description language; establishing a fault model for the particular configurable integrated circuit device; synthesizing the fault model in the hardware description language; embedding the synthesized fault model into the baseline design to create a modified baseline design in the hardware description language which enables one or more targeted signals to be selectively corrupted; creating a fault model enabled target device on the particular configurable integrated circuit device using the modified baseline design; and performing a number of fault injection experiments on the fault model enabled target device, wherein each fault injection experiment includes causing at least one of the one or more targeted signals to be corrupted within the fault model enabled target device.