1. A computer readable memory comprising: a circuit layer; a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces; a first switching crossbar array disposed on a first side of the memory box; and a plurality of vias connecting the circuit layer to the first switching crossbar layer; in which the first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer.