1. A method for controlling access to a cache memory unit in an electronic processor, the method comprising: determining whether an operation directed to the cache memory unit from a processing core of the electronic processor is a read operation or a write operation; and if the operation is a read operation that executes unsuccessfully in the cache memory unit: (a) executing the read operation in another memory unit; (b) determining whether the read operation is a cache obstruction by determining a miss rate for the read operation and an obstruction threshold value based on execution of the read operation in the cache memory unit by the processing core; and (c) writing data obtained in step (a) to the cache memory unit if the read operation is not a cache obstruction.