1. A programmable counter system comprising: a prescaler for frequency dividing an input signal by a selected one of frequency division factors "2.sup.n -1" and "2.sup.n "; programmable counter means comprising first and second programmable counters connected to said prescaler, said first and second programmable counters receiving and counting an output signal of said prescaler and comprising an output terminal and preset terminals for receiving program data inputs; first division number means for supplying a plurality of binary bits as lower digit bits of program data, second division number means for supplying upper digit bits of program data; first setting means for supplying the complement of said lower digit bits of program data to said preset terminals of said first programmable counter as a division number; second setting means for supplying said upper digit bits of program data to said preset terminals of said second programmable counter as a division number; and selecting means connected to said programmable counter means for receiving output signals of said first and second programmable counters, and for selecting one of said frequency division factors "2.sup.n -1" and "2.sup.n " according to output signals of said first and second programmable counters.