1. A logic simulator for carrying out logic simulation of a logic circuit comprising successive groups of gates, said logic simulator comprising: an input memory for memorizing input bits which are input to the gates of a selected one of said successive groups, said successive groups being selected in sequence; pattern memory means for memorizing pattern bit sequences corresponding to respective ones of said gates, each of said pattern bit sequences consisting of a plurality of bits such that, for a particular pattern bit sequence corresponding to a particular group of gates, each bit corresponds to a respective gate of the group preceding said particular group and represents a connection state of said respective gate to a gate in said particular group; function memory means for memorizing logic functions of the gates of said logic circuit; calculating means, responsive to said input bits supplied from said input memory, the particular pattern bit sequence corresponding to the gates of said particular group and supplied from said pattern memory means, and the logic functions of the gates of said particular group and supplied from said function memory means, for calculating successively, for the gates of said particular group, output bits which are produced from the gates of said particular group; and supplying means for supplying said output bits to said input memory as said input bits to be given to the gates belonging to the next successive group to be selected as said particular group.