1. A memory system comprising: a memory controller; a level 1 (L1) cache including L1 tag memory and L1 data memory; and a level 2 (L2) cache coupled to the L1 cache, the L2 cache including L2 tag memory having a first set of L2 tag entries and a L2 data memory having a second set of L2 data entries; wherein the number of entries in the first set is greater than the number of entries in the second set.