1. A computer system, comprising: a first bus system; a second bus system; and interface means for connecting the first bus system to the second bus, the interface means including logical interpreter means for receiving input signals from the first bus system representative of a desired operation and for providing output signals to the second bus system in a series of logical states based on the signals received from the first bus system, the series of logical states required to accomplish the desired operation comprising an output cycle; and time controller means, coupled to the logical interpreter means, for receiving a clock signal having clock pulses and a frequency from the first bus system, and for adjusting timing in the logical interpreter means based on variation in the clock frequency so the duration of each of the logical states in the output cycle corresponds to a number of clock pulses so that the output cycle is within predetermined time limits, the time controller means including a counter coupled to the logical interpreter means and providing timed inputs to the logical interpreter means, the timed inputs controlling the duration of each of the logical states.