1. Configurable electronic device, characterized in that it comprises at least one configurable basic assembly (ENSB) comprising a programmable circuit (FPGA) possessing programmable elements (LUT) that are mutually connected by a first configurable interconnection network (RIT 1 ) and having a programming granularity of a few bits, several configurable arithmetic cells (CA) that are mutually connected by a second specific configurable interconnection network (BDT, CSB, BSV) and that each include at least one arithmetic and logic unit (ALU), an address generator (GAD) and a memory (MM), a third specific configurable interconnection network (RIT 3 ) linking the programmable circuit and the arithmetic cells, and a control bus (BSC) running between the programmable circuit and the arithmetic cells and also inside the latter, and in that the programmable circuit (FPGA) is able to generate clock and control signals for the arithmetic cells.