1. An integrated circuit comprising: a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, the pipeline to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, wherein the cache line validation logic to invalidate the cache line speculatively written into the cache when determined invalid and wherein the store instruction is allowed to retire from the pipeline when the cache line is determined valid.