1. An integrated circuit for implementing reconfigurable logic comprising: a field programmable gate array; a first input/output buffer circuit; an input/output pin coupled to said first input/output buffer circuit; an output multiplexer associated with said field programmable gate array, said output multiplexer capable of receiving two signals and time-multiplexing the two signals onto said input/output pin; and an input multiplexer associated with said field programmable gate array, said input multiplexer capable of receiving a time-multiplexed signal and demultiplexing the time-multiplexed signal into two separate signals; a core within said field programmable gate array; and a first core connection between said core and said first input/output buffer circuit so that said core may either transmit a signal to said first input/output buffer circuit or receive a signal from said first input/output buffer circuit over said first core connection.