1. A data processing system comprising: a plurality of data processors; debug logic coupled to each data processor of the plurality of data processors, the debug logic for providing an instruction for exiting debug mode to the plurality of data processors; and linking logic, coupled to the debug logic and to each of the plurality of data processors, the linking logic for linking selected ones of the plurality of data processors with each other and to the debug logic, wherein the debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.