1. An information processing apparatus comprising: a memory for storing a plurality of descriptors, wherein each of said plurality of descriptors contains input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data; and a stream processor for performing a plurality of processes parallel to each other by acquiring said plurality of descriptors from said memory, reading data to be processed from said memory according to said input address information contained in each of said plurality of descriptors, processing said data by a predetermined process, and storing the processed data back into said memory according to the output address information contained in each of said plurality of descriptors, and wherein said stream processor can process a plurality of said predetermined processes parallel to each other.