1. A microprocessor having an instruction set architecture that defines a conditional store instruction, the microprocessor comprising: a store queue; a register file; an instruction translator, that translates the conditional store instruction into at least two microinstructions, wherein the conditional store instruction specifies a data register, a base register, and an offset register of the register file, wherein the conditional store instruction instructs the microprocessor to store data from the data register to a memory location if condition flags of the microprocessor satisfy a specified condition; and an out-of-order execution pipeline, comprising a plurality of execution units that execute the microinstructions; wherein to execute a first of the microinstructions, one of the execution units receives a base value and an offset from the register file, and in response generates a first result as a function of the base value and the offset, wherein the first result specifies an address of the memory location; wherein to execute a second of the microinstructions, one of the execution units receives the first result, and in response: if the condition flags satisfy the condition, writes the first result to an allocated entry in the store queue, wherein the store queue is configured to subsequently write the data to the memory location specified by the address; and if the condition flags do not satisfy the condition, kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.