1. A processing device, comprising: a memory interface having one or more first ports and one or more second ports; a memory array coupled to the one or more first ports of the memory interface; a processor core associated with a reduced instruction set computer (RISC) instruction set, the processor core including an instruction decode stage for decoding at least an extension instruction that is an extension of the RISC instruction set; and at least one macro function coupled to the one or more second ports of the memory interface, the macro function accessing the memory array via the memory interface responsive to the extension instruction decoded in the instruction decode stage of the processor core.