1. A processor unit for a data processing system including a branch unit for operating on conditional branch on count instructions and calculating target addresses for use in fetching instructions from a memory device, the processor unit comprising: a source of an initial version of a count value related to a conditional branch; an update register for storing the initial version of the count value; a register for storing a dispatch version of the count value; a register for storing a completion version of a count value corresponding to nonspeculatively executed instructions; means responsive to beginning execution of a move to count instruction for loading the initial version of the count value into the register for storing the dispatch version; means responsive to completion of a move to count instruction for moving the initial version of the count value to the register for storing the completion version and for transferring the content of the update register to the register for storing the completion version; means responsive to dispatch of a branch on count instruction for decrementing the dispatch version; means responsive to completion of a branch for decrementing the contents of the register for storing the completion version; and means responsive to an interrupt for loading the contents of the register for storing the completion version into the register for storing the dispatch version.