1. A circuit tester comprising: a set of n test pins on which an n-bit indirect counter is to be produced, where n is an integer; driving means, responsive to derivative mode data vectors having n digits, each digit being associated one-to-one with one of said n test pins, for driving test vectors onto the set of test pins; means for generating an ordered sequence of n distinct derivative mode data vectors that will produce an indirect counter on said n test pins when supplied to the driving means in order; and means for supplying said ordered sequence of derivative mode data vectors to said driving means.