1. A resistance change memory comprising: a memory cell array in which a plurality of blocks are provided; a plurality of resistance change storage elements which are provided in the plurality of blocks and which store data in accordance with a change in resistance state; a plurality of first wirings along a first direction in the plurality of blocks, each of the first wirings being connected to each of the plurality of resistance change storage elements; a plurality of second wirings along a second direction in the plurality of blocks, each of the second wirings being connected to each of the plurality of resistance change storage elements; and a control circuit which controls the state of a selected block targeted for operation and the state of a plurality of unselected blocks except the selected block among the plurality of blocks, wherein the control circuit respectively applies first and second unselect potentials to the first and second wirings in at least one of the unselected blocks during a period in which the selected block is in operation.