1. An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, which switches the execution of conditional instructions of said processor between a energy-saving mode and a high-performance mode, said apparatus comprising: one or more instruction decoders being involved in a decode stage for loading and decoding said instructions from a fetch unit; one or more arithmetic logic unit (ALU) with control units, for executing said decoded instructions from said instruction decoders; and a register file including a plurality of registers for storing and forwarding the executed results of said ALU with control units to said instruction decoders to support said conditional execution.