1. An integrated device comprising: a hard logic portion comprising a plurality of hard logic blocks; a field programmable gate array (“FPGA”) fabric comprising control logic and a plurality of soft logic modules; and an interface configured to route signals between the hard logic portion and the FPGA fabric; wherein, responsive to a control signal from the control logic, the interface is further configured to selectively couple a first node in the hard logic portion to one of a first soft logic module of the plurality of soft logic modules and a first hard logic block of the plurality of hard logic blocks.