1. An integrated circuit memory product comprising: at least one bank of antifuse elements in which the top plates of the antifuse elements are joined in a common connection to a programming voltage; a selection transistor in series with each antifuse element in the bank, the enablement of a particular selection transistor resulting in a path being provided for the programming of the antifuse element associated with the enabled selection transistor; and a feedback circuit associated with each antifuse element in the bank to stop the flow of current through its associated antifuse element once the antifuse element is programmed.