1. A data processing system comprising: a processor unit that includes: an instruction decode/issue unit including a re-order buffer having entries that include an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned; a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result; and a forward indicator to indicate that a status bit can be forwarded to an execution queue of an instruction that is waiting to receive the status bit.