1. In a data processing system having an instruction fetch unit, a decode unit, and a branch execution unit, the instruction fetch unit having a branch target buffer (BTB), a first instruction queue for providing instructions to the decode unit, and a second instruction queue for providing instructions to the decode unit, the decode unit issuing instructions for execution, a method comprising: providing a first instruction address to the instruction fetch unit; fetching a first instruction from the first instruction address and storing the first instruction in the first instruction queue; determining whether the first instruction address hits in the BTB; in response to determining that the first instruction address hits in the BTB, using an entry in the BTB which resulted in the hit to determine whether the first instruction is a conditional branch and whether it is predicted as a taken branch or a non-taken branch; in response to determining that the first instruction is a conditional branch and predicted as a taken branch: providing a target address from the entry in the BTB to the instruction fetch unit; fetching a second instruction from the target address and storing the second instruction in the first instruction queue; and fetching one or more sequential instructions which are sequential to the first instruction and storing the one or more sequential instructions in the second instruction queue; and in response to determining that the first instruction is a conditional branch and predicted as a non-taken branch: providing the target address from the entry in the BTB to the instruction fetch unit; fetching a third instruction fetched from the target address and storing the third instruction in the second instruction queue; providing a sequential address to the first instruction to the instruction fetch unit; and storing a fourth instruction fetched from the sequential address in the first instruction queue.