1. A microprocessor configured to transition through a plurality of performance running states, ranging between lowest and highest, each comparatively characterized by differences in clock frequencies and/or voltage levels, the microprocessor comprising: functional units; and control registers, writeable to cause the functional units to institute one or more power-saving actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state; wherein the lowest performance running state comprises a non-sleeping state in which the microprocessor runs at its lowest supported clock frequency; wherein the microprocessor is configured with microcode to write the control registers to institute the one or more instructions-per-clock rate reducing actions, wherein the microcode is invoked in response to an instruction instructing the microprocessor to transition to the lowest performing running state.