1. A computing device, comprising: a memory structure storing information for a plurality of variables, wherein each of at least two of the variables corresponds to a conceptual unit and comprises: data comprising a set of operands; a variable descriptor; and a variable ID; two or more logical mentors, wherein each logical mentor is a logical entity that performs one or more functions associated with at least one variable assigned to the logical entity, wherein each of at least two of the logical mentors is assigned to a particular one or more of the variables, wherein each of the at least two logical mentors is configured to perform cache management and operand addressing operations with respect to at least one of the one or more variables to which the logical mentor is assigned, a control circuit configured to control a main program flow, wherein the main program flow includes calculating one or more end operands; and a resource allocation circuit, wherein the computing device is configured to implement a frames/bins structure forming the variables' caches and comprising: a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames, wherein each of at least two of the bins comprises a logical element, wherein each of the at least two variables are assigned to a particular bin within one of the frames, wherein the resource allocation circuit is configured to assign a logical mentor to each of the at least two variables and to allocate bin space in the frames to each of the at least two variables, wherein the logical mentors are configured to perform at least some of the cache management and operand addressing operations with respect to the variables in parallel with one another and in parallel with operations by the control circuit in the main program flow.