1. A computing device, comprising: a main memory; a local high speed memory configured to implement a frames/bins structure, wherein the local high speed memory comprises: a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames, wherein each of the bins comprises a logical element, wherein each of at least two of the plurality of bins is configured to store information for a variable, wherein each of at least two of the variables corresponds to a conceptual unit and comprises: data comprising a set of operands; a variable descriptor; and a variable ID; a plurality of mentor circuits, wherein each of at least two of the mentor circuits is assigned to a particular one or more of the variables, wherein each of the at least two mentor circuits is configured to perform cache management and operand addressing operations with respect to at least one of the particular one or more variables to which the mentor circuit is assigned; a control circuit configured to control a main program flow, wherein the main program flow includes calculating one or more end operands; one or more functional units configured to perform operations relating to one or more variables stored in at least one of the bins, wherein each of at least one of the variables comprises one or more words; one or more interconnects between the main memory and the local high speed memory; and one or more interconnects between the local high speed memory and the one or more functional units, wherein the mentor circuits are configured to perform the cache management and operand addressing operations with respect to the variables in parallel with one another and in parallel with operations by the control circuit in the main program flow, and wherein each of the at least two of the variables is assigned to a particular bin within one of the frames of the local high speed memory, wherein the computing device is configured to synchronize operand traffic streams to or from the bins of the local high speed memory as requested by or on behalf of the mentor circuits by main or other control, wherein, for each mentor circuit assigned to one or more variables, the mentor circuit performs cache management with respect to the particular bin or bins assigned to those one or more variables.