1. A processor comprising a first mode of operation and a second mode of operation, wherein a state of said processor in said first mode of operation comprises a first plurality of variables, said first plurality of variables comprising a return address, and wherein a state of said processor in said second mode of operation comprises a second plurality of variables in addition to said first plurality of variables; wherein said processor comprises a trampoline instruction; said processor being configured to perform, in case of an interrupt or exception occurring during said second mode of operation, the steps of saving said second plurality of variables and said return address to a buffer memory, replacing said return address with an address of said trampoline instruction, and switching into said first mode of operation, said steps being performed independently of an operating system; and wherein said trampoline instruction is adapted to switch said processor from said first mode of operation to said second mode of operation, to read said second plurality of variables and said return address from said buffer memory and to jump to said return address.