1. A network processor system comprising: a field programmable gate array (FPGA) comprising a hardware multiplication macro and a plurality of configurable logic blocks (CLBs); a multiplier configured from the hardware multiplication macro, wherein the multiplier is coupled to a plurality of multiplexors coupled to an output and the multiplier receives a digital signal from an input, wherein the digital signal includes a plurality of data bytes; and a control element operatively coupled to the multiplier and to the plurality of multiplexors, the plurality of multiplexors configured from the plurality of CLBs, wherein the control element signals the multiplier and signals the plurality of multiplexors to shift the plurality of data bytes to result in an altered digital signal at the output.