1. A system comprising a master processor and at least one slave processor, wherein a state of said master processor comprises a first plurality of variables and a state of said slave processor comprises a second plurality of variables, said system comprising a parallel mode of operation wherein data are processed by said master processor and said slave processor and a serial mode of operation wherein data are processed by said master processor; said system being configured to perform, in case of an interrupt or exception occurring in said parallel mode of operation, the steps of saving at least a portion of said first plurality of variables and said second plurality of variables to a buffer memory and switching said system to said serial mode of operation; said system further being configured to set at least one of said first plurality of variables to a value of at least one of said second plurality of variables in case said interrupt or exception is occurring in said slave processor.