1. A memory device, comprising: at least one test memory cell comprising a symmetric storage latch including a first inverter stage and a second inverter stage with an output of the first inverter stage providing an input to the second inverter stage and an output of the second inverter stage providing an input to the first inverter stage whereby a state of the memory cell is statically maintained; and an asymmetric pair of connections, a first connection to said first inverter stage and a second connection to said second inverter stage, whereby a stability of said memory cell can be evaluated by varying the asymmetry between said pair of connections and observing operation of said at least one memory cell.