1. A method of logic synthesis using a computer, comprising: providing a plurality of register transfer statements describing a target logic system within said computer; tagging selected register transfer statements within said computer to specify a plurality of directed control levels including an open level and a structure dominance level; parsing the plurality of register transfer statements to generate a node graph where a node corresponds to a register transfer statement and allowing each node to receive an attribute indicating a directed control level; transforming the nodes having the attribute indicating the structure dominance level by searching a target technology book for exact match patterns to the nodes and adding any exact match patterns located to the nodes; optimizing the node graph on the nodes having an attribute indicating the open control level and through the nodes having the attribute indicating the structure dominance level; and covering the optimized node graph using the nodes having the attribute indicating the structure dominance level.