1. A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor, said method comprising: in advance of executing a first sequence of target instructions, committing state of the target processor and storing memory stores generated by previously-executed sequences of instructions to produce a known state of the target processor, in advance of executing of a speculative sequence of host instructions following a branch from the first sequence of target instructions, committing state and storing memory stores of the host processor to a known state, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, and rolling back to a last committed state of the target processor and discarding memory stores generated by the speculative sequence of host instructions if execution fails.