1. An apparatus comprising: a comparator having a pair of cross coupled PFETs with sources coupled to an I/O power supply, and a differential pair of NFETs with sources coupled to ground and gates respectively coupled to a data input and an inverted data input, wherein the cross coupled PFETs and the differential pair of NFETs to level translate low swing logic levels at the data input to high swing logic levels on a node between the pair of cross coupled PFETs and the differential pair of NFETs; and, first and second pull-up PFETs with sources coupled to a pull-up voltage supply and drains respectively coupled between the differential pair of NFETs and the pair of cross coupled PFETs, the first and second pull-up PFETs to speed the level translation on the node in response to the data input and the inverted data input.