1. An interleaving structure, comprising: a sample selector configured to sample an analog input based on multiple phases of a sampling clock to separate the analog input into a plurality of selected analog inputs; a clock generation circuit configured to provide the multiple phases of the sampling clock to the sample selector and to generate a plurality of reset signals; and a plurality of switches configured to toggle the plurality of selected analog inputs between a first logical value and a second logical value in response to the plurality of reset signals.