1. A processing network for receiving a source code, the network comprising: a plurality of processing elements on a programmable microchip; a plurality of on-chip routers on the microchip for routing the data between the processing elements, wherein each of the on-chip routers is communicatively coupled with one or more of the processing elements; and a compiler stored on a non-transitory computer-readable memory and comprising a parser that based on one or more conditions and one or more assignments of the source code generates a control tree that indicates all possible code paths through the source code.