1. A system, comprising: resources within processor cores that are each in communication with a debug bus such that the cores receive packets over the debug bus, the cores executing transactions in response to the packets, the packets each being a type of packet selected from a group that includes Second Access Bus (SAB) packets and Debug Access Bus (DAB) packets, the resources including specified resources and non-specified resources, a core that executes a transaction in response to a DAB packet accesses a specified resource and a core that executes a transaction in response to a SAB packet accesses a non-specified resource, a debug specification identifies the specified resources as being accessible by a debug controller but does not identify the non-specified resources as being accessible by the debug controller.