1. A processor comprising: a hardware decoder to decode a single Advanced Encryption Standard (AES) generation assist instruction that is to assist in generation of a round key for a key schedule; and a hardware execution unit, responsive to the single AES generation assist instruction, to modify a data operand having a plurality of dwords including to: overwrite a second dword and a fourth dword in the data operand by copying a first dword in the data operand to the second dword and copying a third dword in the data operand to the fourth dword; concurrently perform a byte substitution on bytes of each of the plurality of dwords in the data operand; concurrently perform a rotate word function on the first dword and a rotate word function on the third dword; and concurrently perform an exclusive OR operation on the first dword and an immediate data identified in the single AES generation assist instruction and an exclusive OR operation on the fourth dword and the immediate data.