1. A computer system comprising plural processing units and memory that implement a video decoder system, the video decoder system comprising: a buffer configured to receive encoded video information; and a video decoder configured to perform decoding the encoded video information using plural decoding tasks, wherein a first video decoding stage is split into plural segmented decoding tasks among the plural decoding tasks, the plural segmented decoding tasks being associated with different segments of a picture, wherein the first video decoding stage includes one or more of entropy decoding operations, motion compensation operations, intra decoding operations, and inverse frequency transform operations, and wherein the decoding includes: scheduling and executing plural parallel runnable segmented tasks, among the plural segmented decoding tasks, wherein at least two of the plural parallel runnable segmented tasks are at least in part executed in parallel by different ones of plural hardware threads; scheduling and executing another decoding task, among the plural decoding tasks, wherein the other decoding task includes a second decoding stage for the picture, wherein the second decoding stage includes loop filtering operations, wherein the other decoding task has at least one task dependency on at least one of the plural segmented decoding tasks, and wherein the other decoding task is scheduled based at least in part on the at least one task dependency on the at least one of the plural segmented decoding tasks, including performing the other decoding task with one of the plural hardware threads.