1. A memory device comprising: a memory array having cells for storing data; test circuitry for detecting a defective cell in the memory array and providing a local defect signal when the defective cell is detected, the test circuitry combining the local defect signal with a global defect signal to provide an updated global defect signal; and output path circuitry for providing the global defect signal to the test circuitry and for outputting the updated global defect signal.