1. A method for performing design partitioning at the behavioral circuit design level comprising: receiving, processing, and parsing hardware descriptive language of a circuit design; tracing identified signal dependencies to determine dependent elements along selected paths within the circuit design; removing existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; defining selected paths within the circuit design; wherein the selected paths are traced from inputs to outputs according to a partition specification; separating a flattened circuit design hierarchy according to the partition specification; creating a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the hardware descriptive language of the circuit design; and outputting the second hierarchical circuit design structure for analysis.