1. An adaptive instruction generator for use in a computer system having a central processing unit (CPU), random access memory (RAM), a system bus including an address bus, data bus and control bus, all coupled to said instruction generator, comprising: a startup decoder coupled to said system bus, said startup decoder generating a startup signal when a predefined startup signal pattern is detected; state means for denoting the current state of said adaptive instruction generator; data processing means, coupled to said data bus, for generating one or more synthesized data values, including means for generating data values corresponding to data received from said data bus; state updating means for responding to said startup signal by causing said state means to denote an active state, and for generating a new current state in accordance with the previous current state and said synthesized data values; instruction generating means responsive to memory access signals from said CPU on said control bus when said state means denote an active state, for generating and transmitting onto said data bus instructions to be used by said CPU, including means for generating instructions corresponding to said current state of said adaptive instruction generator and said synthesized data values generated by said data processing means; and deactivation means for deactivating said instruction generation means when said state means denotes a preseelcted inactive state; whereby said adaptive instruction generator can perform data processing operations that would otherwise be performed by said CPU, and produce instructions for execution by said CPU based on the results of said data processing operations, thereby reducing the number of instructions executed by said CPU to perform a predefined task.