1. A graphics processor comprising: a plurality of hardware units operable to execute instructions in parallel and independently of one another, each of the plurality of hardware units supporting a respective set of operations, wherein each of the plurality of hardware units comprises a different hardware unit relative to other ones of the plurality of hardware units; and a scheduler operable to dispatch instructions for multiple threads to the plurality of hardware units concurrently, wherein each of the plurality of hardware units executes one instruction independently of the other ones of the plurality of hardware units, and performs a different operation corresponding to the one instruction executed by the respective one of the plurality of hardware units.