1. A computer-implemented method for minimizing constraints in a formal verification of an integrated circuit comprising: obtaining, via a computing device, an unisolated list of constraints initially comprising all known constraints for the integrated circuit design; obtaining, via the computing device, an isolated list of constraints initially comprising none of the known constraints; attempting, via the computing device, to prove an assertion without the known constraints; determining, via the computing device, if the assertion is valid; and updating the isolated list of constraints.