1. A processor, comprising: a plurality of cores; a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a first Advanced Encryption Standard (AES) instruction; an L1 data cache; instruction fetch logic to fetch instructions from the L1 instruction cache; decode logic to decode instructions; a first source register to store a round key to be used for a final round of an AES decryption operation; a second source register to store input data to be decrypted by the final round of the AES decryption operation; an execution unit including AES execution logic to execute the first AES instruction to perform the final round of the AES decryption operation, the final round of the AES decryption operation to use the round key from the first source register to decrypt input data from the second source register and to store a final decrypted result of the AES decryption operation in a destination register; wherein the final round of the AES decryption operation is to include: a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box), an inverse Shift Rows operation, and an Add Round Key operation in which an exclusive OR function is to use data from the round key.