1. An execution unit for use in a computer system for conditionally performing a vector operation defined in a computer instruction, the execution unit comprising: first and second input vector registers for holding respective first and second source vector operands on which said vector operation defined in the instruction is to be carried out, wherein each of said first and second input vector registers holds a plurality of vector elements of a predetermined size, each vector element defining one of a plurality of vector element positions; a vector condition flag register for storing a plurality of condition flags for each of said plurality of vector element positions, each element of said plurality of condition flags defining a true or false condition value; means for loading said first and second input vector registers; a plurality of operators associated respectively with said plurality of vector element positions for carrying out said vector operation on respective vector elements of said first source vector operand and said second source vector operand; a vector compare unit for comparing said first and second source vector operands in accordance with a test field defined in the instruction, and generating a test condition flag for each of said plurality of vector element positions; a vector condition code calculate logic that compounds said test condition flag with a prior generated condition flag of said vector condition flag register to generate a resultant condition flag for each of said plurality of vector element positions, said prior generated condition flag selected in accordance with a condition field defined in the instruction; means to store said resultant condition flag into a destination condition flag of said vector condition flag register for each of said plurality of vector element positions, said destination condition flag selected in accordance with destination field defined in the instruction; and means for storing the output of said vector operation to a destination vector register in accordance with said prior generated condition flag of each respective vector element of said vector condition flag register on a vector element-by-element basis.