1. An apparatus for programming each of a plurality of programmable tiles in a FPGA wherein said FPGA includes said plurality of individually programmable tiles of logic modules, each logic module including a plurality of programmable elements, said apparatus comprising: means for loading address data identifying one of the plurality of programmable elements designated for programming in each said tile; means for selecting an address of said programmable element designated for programming, wherein a mask bit for said programmable element is set from said loaded address data in each said tile; means for programming concurrently said programmable element identified by said address; means for determining whether said selected programmable elements designated for programming have been programmed; means for continuing to program said programmable element designated for programming if said programmable element designated for programming has not been programmed; means for soaking said programmable element in each said tile while concurrently resetting said mask register bit in each said tile; means for determining whether said programmable element designated for programming in each said tile has been programmed; and means for reapplying said means for loading, said means for programming, said means for determining and said means for soaking if said programmable element designated for programming has not been programmed.