1. A system comprising: a processor and a memory of a computing device; and an n-way interoperative debugger comprising a plurality of modules configured to cause the processor of the computing device to interoperatively debug a plurality of n-way interoperative debugger compatible runtime debuggees executing in a single debuggee process, the n-way interoperative debugger providing a holistic view of the single debuggee process, the n-way interoperative debugger comprising: a stepping manager module comprising a communication channel for the plurality of runtime debuggees, the stepping manager module performing top-level step arbitration comprising: contacting in priority order at least one of the plurality of runtime debuggees; receiving a response from a contacted runtime debuggee of the plurality of runtime debuggees claiming ownership of a current debug instruction, the claiming runtime debuggee comprising a current controlling runtime; notifying the plurality of runtime debuggees of the current controlling runtime; and a debug monitor module that routes the debug events to a corresponding runtime runtime debugger based on the between the n-way interoperative debugger and the plurality of runtime debuggees to a common protocol.