1. A Network On a Chip (NOC), the NOC comprising: a first node; and a second node that is coupled via an on-chip network to the first node, wherein the second node comprises: a first set of shadow latches for reading a row of data words from a first Compressed Direct Inter-thread Communications Buffer Packet (CDICBP), wherein received data from the first CDICBP is stored in an input Compressed Direct Inter-thread Communication Buffer (CDICB) in the second node, wherein the input CDICB has no empty buffer cells between any two data words that are stored in the input CDICB, wherein the first CDICBP is populated with data words from an Uncompressed Direct Inter-thread Communication Outbox Buffer (UDICOB) that comprises at least one empty buffer cell between at least two data words that are stored in the UDICOB, and wherein the UDICOB and the input CDICB contain multiple different data word aggregates; a first set of multiplexers, wherein the first set of multiplexers selectively reads individual data words from first CDICB-stored data word aggregates that contain at least two data words; a processor that processes each of the data words from the first CDICB-stored data word aggregates to produce an output of uncompressed rows of data words; and a second set of multiplexers, wherein the second set of multiplexers compresses the output of uncompressed rows of data words from the processor to generate a second CDICB that has no empty buffer cells between any two data words that are stored in the second CDICB.