1. A protocol bridge comprising: a processor; memory connected to the processor; a plurality of PHYs, at least two of the plurality of PHYs configured to connect to at least two separate data storage devices, and at least one of the plurality of PHYs configured to connect to at least one initiator device; and computer executable program code configured to execute on the processor, wherein: the memory is configured as a data cache for at least two separate data storage devices; and the computer executable program code is configured to cache data from two or more data storage devices in the memory.