1. A system-on-chip design integration platform, comprising: a pre-defined system-on-chip (SoC) architecture that includes synthesized and verified semiconductor intellectual property (SIP) hardware description language (HDL) versions of at least an integrated central processing unit (CPU), a shared memory controller, a peripheral controller, a set of system peripherals, a DMA controller, an embedded memory, and general system control; a pair of matching CPU-bridges providing for a standardized interface between them such that said CPU can be any of a variety of types; and a mechanism for incorporating a user-defined SIP HDL device on a common semiconductor chip.