1. A circuit architecture comprising a plurality of cells having a fixed arrangement of structures configurable for construction of logic circuitry and memory circuitry with a formation of variable overlying layers, wherein the fixed arrangement of structures within each of the plurality of cells comprises: a first set of NMOS transistors configured to function when coupled to some of the variable overlying layers as either pass devices of memory circuitry or tri-state pass gates of particular logic circuitry depending on a layout of the variable overlying layers coupled thereto; a second set of NMOS transistors comprising greater widths than the first set of NMOS transistors and configured to function when coupled to some of the variable overlying layers as either pull down devices of memory circuitry or logic gates of logic circuitry depending on the layout of the variable overlying layers coupled thereto; a first set of PMOS transistors configured to function when coupled to some of the variable overlying layers as pull up devices of memory circuitry; a second set of PMOS transistors configured to function when coupled to some of the variable overlying layers as tri-state pass gates of particular logic circuitry; and a third set of PMOS transistors comprising greater widths than at least the first set of PMOS transistors and configured to function when coupled to some of the variable overlying layers as logic gates of logic circuitry.