1. An integrated circuit performance modeling system comprising: a memory storing a design layout of an integrated circuit and a model library, said memory being a non-transitory computer readable storage medium and said model library storing a plurality of connectivity-based condensed resistance models for conductive shapes; and, a computer comprising a tangible processor comprising: an integrated circuit design layout analyzer in communication with said memory, said integrated circuit design layout analyzer accessing said memory and, during an integrated circuit design flow, analyzing said design layout in order to identify, within said design layout, a diffusion boundary shape of a semiconductor device, a first conductive shape on said diffusion boundary shape, and any second conductive shapes connected to said first conductive shape and, said integrated circuit design layout analyzer further analyzing said design layout to determine, for each second conductive shape identified as being connected to said first conductive shape, a corresponding interface location of a point of connectivity between said second conductive shape and said first conductive shape relative to said diffusion boundary shape, said corresponding interface location being any of entirely outside said diffusion boundary shape and at least partially within said diffusion boundary shape; a model selector in communication with said integrated circuit design layout analyzer and said model library, said model selector accessing said model library and selecting, from said model library, a specific condensed resistance model for said first conductive shape based on whether any corresponding interface locations between said first conductive shape and any second conductive shapes are entirely outside said diffusion boundary shape or at least partially within said diffusion boundary shape; a netlist extractor in communication with said model selector and generating a condensed netlist for said first conductive shape based on said specific condensed resistance model; and a simulator in communication with said netlist extractor and simulating a performance of said integrated circuit using said condensed netlist for said first conductive shape, wherein said using of said condensed netlist for said first conductive shape as opposed to a full netlist for said first conductive shape to perform said simulating reduces a number of simulation runs required to complete said simulating, reduces overall processing time to complete said simulating and reduces processing capability required by said computer for performing said simulating.