1. A processor comprising: a mask register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the mask register corresponds to an element location in a vector; a decode stage to decode a first instruction specifying a vector source operand, the mask register, a vector destination operand and a vector destination offset; and one or more execution units, responsive to the decoded first instruction, to: read the values of the first plurality of data fields in the mask register; and for each the first plurality of data fields in the mask register having the first value, copy the corresponding vector elements from the vector source operand to adjacent sequential element locations in the vector destination, starting at the vector destination offset location.