1. A processor, comprising: an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants; and an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction, wherein the instruction decoder receives a second instruction that includes a third operand, a fourth operand, and a fifth operand, wherein for a current iteration i of SHA-2 round operations, the third operand specifies a location to store messages w(i−13), w(i−14), w(i−15), and w(i−16), wherein the fourth operand specifies a location to store messages w(i−9), w(i−10), w(i−11), and w(i−12), and wherein the intermediate result is stored in a location specified by the fifth operand, and wherein in response to the second instruction, the execution unit is configured to perform a first part of message scheduling operations based on a plurality of first previous messages specified by the second instruction and to generate an intermediate result.