1. A processor comprising: a plurality of programmable logic arrays (PLAs); an instruction pointer queue coupled to said plurality of PLAs; an instruction pointer sequencing logic/predictor component coupled to said instruction pointer queue; a micro-operation cache coupled to said instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to said micro-operation cache; and a trace pipe (TPIPE) coupled to said micro-operation cache and said instruction pointer queue.