1. A method of operating a multiple bit per cell memory device comprising: providing said multiple bit per cell memory device with x multiple bit per cell memory cells, each with y states; applying power to said multiple bit per cell memory device; running a self-test on each of y x possible states of said multiple bit per cell memory device to identify z faulty states, wherein z&gE;0; assigning a unique state to each of y x - z working states of said multiple bit per cell memory device; mapping each assigned unique state to a unique binary state of n binary bits, where 2 n <y x and n is an integer; and designating y x - z - 2 n spare states as invalid data states.