1. A method for reducing the size of a logic network design, prior to verification of the logic network design, utilizing a resubstitution, wherein the resubstitution is a Boolean function resubstitution, said method comprising: dynamically selecting a relevant register of a Boolean function basis set; identifying one or more resubstitutions of the relevant register, wherein the resubstitutions are compatible resubstitutions that expresses the selected relevant register as one or more pre-existing registers of fixed initial state; refining the resubstitution utilizing design invariants; and generating a logic network design of reduced size utilizing the one or more resubstitutions.