1. A processor comprising: an instruction decode logic to decode one or more instructions into a first operation comprising a reference to a first physical address and a second operation comprising a reference to a linear address in a virtual memory; a sequencing logic to receive the first operation and the second operation from the instruction decode logic on an input path, direct the first operation to physical address logic on a first output path, and to direct the second operation to translation logic on a second output path; the physical address logic to decode the reference to the first physical address to a representation of the first physical address and to provide the representation of the first physical address to a common interface without disabling paging of the virtual memory for the processor; and the translation logic to decode the reference to the linear address to a representation of a second physical address and to provide the representation of the second physical address to the common interface.