1. A method of supporting load-linked/store-conditional (LL/SC) synchronization on a processor that does not directly support load-linked and store-conditional operations, the method comprising: emulating a load-linked operation that targets a location, wherein said emulating the load-linked operation comprises: reading an application value associated with the targeted location, storing the read value in an auxiliary location associated with an id and storing using a first linearizable synchronization operation, the id in the targeted location, and emulating a store-conditional operation that targets the targeted location, wherein said emulating the store-conditional operation comprises employing a second linearizable synchronization operation to ensure that the application value associated with the targeted location has not changed since success of the first linearizable synchronization operation.