1. A multiprocessor system, comprising: a plurality of processors coupled with a plurality of higher-level caches; a lower-level cache coupled with the plurality of higher-level caches, such that each higher-level cache performs memory accesses through the lower-level cache; and a reverse directory system coupled to the lower-level cache and comprising a plurality of reverse directories, each reverse directory being associated with one of the plurality of higher-level caches and identifying entries in the lower-level cache associated with lines in the associated higher-level cache, each reverse directory comprising: a first reverse sub-directory for higher-frequency memory accesses; and a second reverse sub-directory for lower-frequency memory accesses.