1. A multi-storage state non-volatile random access memory device, comprising: a first memory cell and a second memory cell, the first memory cell and the second memory cell each comprising; a first transistor having a first terminal coupled to a first node, a second terminal coupled to a first programmable resistive device, and a control terminal coupled to a write line; a second transistor having a first terminal coupled to a second node, a second terminal coupled to a second programmable resistive device, and a control terminal coupled to the write line; the first programmable resistive device being coupled between a first bit line and the second terminal of the first transistor; and the second programmable resistive device being coupled between a second bit line and the second terminal of the second transistor, and a third transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a write enable line, wherein the third transistor is configured to activate in response to a write enable signal being asserted on the write enable line such that current flows either from the first bit line to the second bit line, or from the second bit line to the first bit line, to store a logic high state or a logic low state in a corresponding one of the first memory cell or the second memory cell.