1. In a computer system having a CPU, a main memory, a data bus and an address bus, a cache architecture comprising: a plurality of set associative cache memories wherein each of said plurality of set associative cache memories is coupled to the address bus for receiving a main memory address having at least a TAG portion; each of said plurality of set associative cache memories having: (a) an address storage means including: (i) a programmable address register for storing said main memory address, said programmable address register having an address value; and (ii) a programmable address mask register coupled to said programmable address register and having a masked value, said programmable address mask register outputting a masked TAG address corresponding to said masked value and said address value of said programmable address register, said masked TAG address masking bits in at least said TAG portion of said main memory address to establish a set of TAG addresses defining data to be cached and wherein the address value of each programmable address register is correlated with the masked value of each programmable address mask register such that each one of said plurality of set associative cache memories stores a different set of TAG addresses than any remaining ones of said plurality of set associative cache memories; (b) a TAG memory, coupled to said address storage means, having a plurality of TAG storage locations for storing said set of TAG addresses; (c) a data memory, coupled to said TAG memory and to the data bus, and having a plurality of storage locations, wherein each storage location corresponds to a TAG location of one of the TAG storage locations in the TAG memory; and (d) means, coupled to the data bus and to said data memory, for outputting to the data bus a data word stored at a data location corresponding to said TAG location when said TAG location corresponds to the TAG portion of said main memory address.