1. A neuristor-based reservoir computing device comprising: support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer; input nodes connected to the support circuitry; output nodes connected to the support circuitry; thin film neuristor nodes disposed over the CMOS layer, a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes; and interconnections between the neuristor nodes to form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes.