1. A processor comprising: an instruction pipeline including: a fetch pipeline including: a first fetch substage, wherein said first fetch substage translates virtual addresses into physical addresses; a plurality of other fetch substages including: a second fetch substage coupled to said first fetch substage, wherein said second fetch substage performs branch prediction and accesses an instruction cache; a third fetch substage coupled to said second fetch substage, wherein said third fetch substage determines whether there is a hit or a miss in said instruction cache; and a fourth fetch substage wherein said fourth fetch substage determines a branch taken target, and further wherein in transition from said third fetch substage to said fourth fetch substage, an instruction instance read from said instruction cache is fetched into a fetch buffer; and a page boundary crossing event indicator wherein following said page boundary crossing event indicator indicating a page crossing event processing in said fetch pipeline goes to said first fetch substage, and otherwise processing in said fetch pipeline bypasses said first fetch substage wherein upon said bypassing, a cycle normally used by said first fetch substage is used by another fetch substage in said plurality of other fetch substages thereby enhancing the execution performance of said processor.