1. A microprocessor, for executing a floating point macro instruction having relative references to registers within a floating point register file, the microprocessor comprising: translation logic, configured to translate the floating point macro instruction into associated floating point micro instructions, wherein said associated floating point micro instructions have absolute references to the registers within the floating point register file, said translation logic comprising: a pseudo top-of-stack generator, configured to generate an absolute reference to a top-of-stack register for each of said associated floating point micro instructions; and an offset converter, coupled to said pseudo top-of-stack generator, configured to compute a second absolute reference to a second register within the floating point register file; and top-of-stack synchronization logic, coupled to said translation logic, configured to synchronize said pseudo top-of-stack generator with an architected top-of-stack register.