1. An apparatus, comprising: an out of order issue engine that has a set of micro-operations that the out of order issue engine issues using two different sets of architectural semantics; a first set of architectural semantics that includes speculative operations that can be issued whenever their operand data is available; and a second set of architectural semantics that includes architectural operations that issue after all earlier architectural operations in program order have been issued and all previous speculative operations associated with this architectural operation have issued.