1. An electronic computer coordinating access to common memory by multiple program threads comprising by performing the steps of: in each given program thread, (a) detecting the beginning of a critical section of the given program thread in which interruption to access of the common memory could occur resulting from execution of other program threads; (b) speculatively executing the critical section; and (c) committing the speculative execution of the critical section if there has been no interruption to access of the common memory and squashing the speculative execution of the critical section if there has been an interruption wherein step (a) deduces the beginning of a critical section by detecting special delimiter instructions.