1. A method of processing instructions in a processor core, the method comprising: examining, by predecode logic, instructions in an instruction stream of a processor to determine properties of the instructions, wherein the properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO); determining, by grouping logic, whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group; grouping, by the grouping logic, the instructions with compatible ones of the properties into a first instruction group; decoding, by a decode unit, the instructions of the first instruction group subsequent to formation of the first instruction group; verifying, by the decode unit, whether the first instruction group actually includes a DTIO sequence based on the decoding; in response to the first instruction group actually including a DTIO sequence based on the verifying, performing, by the decode unit, DTIO on the instructions of the first instruction group; and in response to the first instruction group not actually including a DTIO sequence based on the verifying, refraining from performing, by the decode unit, DTIO on the instructions of the first instruction group.