1. A device comprising: an integrated circuit comprising a computational unit configured to process at least a first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value, wherein the computational unit comprises: a convolver configured to generate pair-wise bit combinations of a first bit sequence and a second bit sequence that deterministically encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the data bits in the sequence that are low, wherein a subset of the plurality of pair-wise bit combinations pairs a data bit of the first bit sequence with multiple different data bits of the second bit sequence, and a stochastic computational unit configured to: perform a computational operation on the pair-wise bit combinations; and produce an output bit stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit stream represent the result based on a probability that any data bit in the set of data bits of the output bit stream is high.