1. A data transfer control apparatus comprising: a channel controller including an event input receiving each of a plurality of event signals indicative of occurrence of corresponding events, a first priority encoder connected to said event input selecting one of said event signals indicating occurrence of an event, a memory monitor detecting a memory write to one of a plurality of predetermined memory addresses, said memory monitor including a bus write address input receiving the address of a bus write, a plurality of target address registers, each storing a corresponding address, a plurality of address comparators, each connected to said bus write address input and a corresponding one of said plurality of target address registers, each generating a match signal if an address on said bus write address input matches said address stored in said corresponding target address register, a second priority encoder connected to said memory monitor selecting one of said memory writes, and an event queue connected to said first and second priority encoders storing a queue of data transfer requests corresponding to event signals and memory writes to said predetermined memory addresses; and a transfer controller connected to said event queue for controlling data transfers corresponding to data transfer requests recalled from said event queue.