1. A non-Flash multi-layer memory array, comprising: one or more back-en-of-the-line (BEOL) word line (WL) layers; one or more BEOL bit line (BL) layers interleaved with the one or more WL layers; and a plurality of BEOL memory layers, each memory layer disposed between an adjacent WL layer and an adjacent BL layer, and each memory layer including a plurality of discrete re-writeable non-volatile two-terminal memory elements configured between crossings of WLs and BLs of the adjacent WL and BL layers, wherein the memory elements in adjacent memory layers are configured with opposing orientations.