1. A system for secure execution of processor instructions, the system comprising: a processor; an instruction cache in communication with said processor; a memory controller in communication with said instruction cache; and a security controller in communication with said instruction cache and configured to decrypt, using a first key, an encrypted first block of data comprising executable code, decrypt an encrypted second block of data by executing said executable code in said first block, and encrypt said second block on a per instruction basis, wherein said memory controller is configured to intercept fetches of instructions to be executed by said processor, and fetch an instruction of said second block encrypted on a per instruction basis; and wherein said security controller is further configured to decrypt said fetched instruction to obtain a resulting instruction, and load said resulting instruction into said instruction cache to be executed by said processor.