1. A differential flip-flop including: a master cell comprising a first data set circuit having a first differential input and a first differential output, a first data store circuit coupled to the input of the first data set circuit, a differential clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits, and a differential reset circuit tied to the differential output and operative in response to a reset signal to force the differential output to a predetermined logic level, the differential reset circuit including matched complementary reset driver circuitry; and a slave cell formed substantially similar to the master cell, the slave cell having a second differential input coupled to the first differential output of the master cell.