1. A processor comprising: a first hardware thread and a second hardware thread; a cache to store cache coherent data in a cache line for a shared memory address accessible by said second hardware thread; a decode stage to decode a first instruction for execution by said first hardware thread, the first instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address; and one or more execution units, responsive to the decoded first instruction, to: copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread in the cache when said one or more owner includes said second hardware thread.