1. An information processing apparatus comprising: a memory interface module configured to read an instruction stored in a memory in accordance with a memory address designated by a fetch request from a processor; an error detection module configured to detect an error in the read instruction; and an instruction transmitter configured to send to the processor a first instruction to store the memory address designated by the fetch request into a stack and a second instruction to jump to an error correction module for correcting an error of the read instruction upon detection of the error in the read instruction.