1. A method performed in a data processing system for determining leakage current in a CMOS circuit having a plurality of devices comprising the steps of: reading netlist data from a data processing system memory containing information on each of the plurality of devices and their respective connections within the circuit; reading a plurality of input state data from said data processing system memory, each input state specifying input signals provided to the circuit; determining which devices in the circuit are in an OFF state for each of the plurality of input states; computing leakage current for only those devices that are in the OFF state and do not have the same source and drain voltage; and providing to a data processing system display resulting leakage information for each input state.