1. A data processor comprising: an instruction execution pipeline comprising N processing stages; and an instruction issue unit capable of fetching into said instruction execution pipeline instructions fetched from an instruction cache associated with said data processor, each of said fetched instructions comprising from one to S syllables, said instruction issue unit comprising; a first buffer comprising S storage locations capable of receiving and storing said one to S syllables associated with said fetched instructions, each of said S storage locations capable of storing one of said one to S syllables of each fetched instruction; a second buffer comprising S storage locations capable of receiving and storing said one to S syllables associated with said fetched instructions, each of said S storage locations capable of storing one of said one to S syllables of each fetched instruction; and a controller capable of determining if a first one of said S storage locations in said first buffer is full, wherein said controller, in response to a determination that said first one of said S storage locations is full, causes a corresponding syllable in an incoming fetched instruction to be stored in a corresponding one of said S storage locations in said second buffer.