1. In a data processor adapted to communicate with a peripheral device, the data processor comprising: an instruction register for storing an instruction to be executed by said data processor; and instruction execution control means, for (1) executing instructions stored in the instruction register, and, in response to executing a breakpoint instruction, (2) providing a control signal to said peripheral device; (3) receiving a first response from said peripheral device and (4a) either performing a breakpoint, if the first response is of a first type; (4b) or sorting a successive instruction in the instruction register, if the first response is of a second type; the improvement wherein the instruction execution control means also receives a second response from said peripheral device, the instruction execution control means storing said second response in said instruction register as said successive instruction if said first response is of said second type.