1. A memory controller, comprising: a bank decoder for determining a destination bank of a memory for each memory request of a plurality of memory requests in a received order responsive to a memory address for each of the memory requests; a plurality of bank queues, each bank queue for storing pending memory requests for a memory bank associated with that bank queue and tracking the received order; an ordering unit for determining a memory cycle order different from the received order responsive to a presence of at least two memory requests in a same bank queue and to a same memory page; and a memory interface for executing each memory request in the memory cycle order.