1. A programmable processor configured to perform one or more packet modifications comprising: a pipelined processor core configured to modify a packet through execution of one or more commands comprising, a first stage configured to selectively shift and mask data in each of one or more categories, comprising packet data and other data, responsive to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories; and a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands.