1. A processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions, the processor comprising: an instruction unit fetching and decoding a group of instructions; an instruction register receiving said group of instructions having at least one instruction opcode; a control register including a control word including a control opcode and an action field defining said processor action; an execution unit having compare logic comparing said instruction opcode and said control opcode, said execution unit initiating said processor action upon said compare logic detecting a hit between said instruction opcode and said control opcode; wherein: said control word includes multiple control opcodes and a field indicating grouped mode or non-grouped mode; in grouped mode, said compare logic indicates a hit if all of said control opcodes are present in said instruction opcodes of said group of instructions; in non-grouped mode, said compare logic indicates a hit if one of said control opcodes is present in said instruction opcodes of said group of instructions.