1. An apparatus comprising: a first memory address generator to receive a plurality of first memory command signals and to retrieve a plurality of first sets of memory data from a first memory according to the first memory command signals; a bypass storage unit to receive the first sets of memory data from the first memory address generator and provide access to the first sets of memory data by a second memory address generator; a first bypass control circuit to reroute the first sets of memory data directly to the bypass storage unit, instead of to a processing element, until a first memory command signal deactivates a first bypass signal; and a second bypass control circuit to reroute a first read operation by the second memory address generator to read the first set of memory data directly from the bypass storage unit, instead of reading first data provided from a processing element, until a second memory command signal deactivates a second bypass signal.