1. A code sequence generator comprising a memory, a feedback logic network and an output logic network which is configured to perform a logic function on the contents of elements of the memory to generate bits of the code sequence, the code sequence generator being configured to output a plurality of bits of the code sequence simultaneously, wherein the output logic network implements a plurality of output bit masks which define how the output bits of the code generator are generated, and wherein a most significant bit of an nth output bit mask of the plurality of the output bit masks is set to logic 1 and the (n+1)th output bit mask is derived from the nth output bit mask and a feedback bit mask.