1. A single instruction multiple data (SIMD) array cell for processing a data stream, said array including a plurality of cells, each cell comprising: a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to said identification number and a single command common to all cells in a load mode to compute the unique start position for its cell for receiving the predetermined region of the direct memory access data stream.