1. A hybrid dynamic-static encoder, comprising: an array structure having X rows that are each coupled to a plurality of device active area (DAA) columns and a respective match line that is asserted to indicate that the row corresponds to an entry in the array structure that matches a search key or unasserted to indicate that the entry corresponding to the row mismatches the search key, wherein each DAA column comprises a physical area that houses: a plurality of dynamic nets; X dynamic pull-down devices coupled to the plurality of dynamic nets such that the X rows in the array structure each include one of the X dynamic pull-down devices and the match line coupled to each row in the array structure that matches the search key is asserted; and a static circuit coupled to the plurality of dynamic nets, wherein the static circuit comprises a plurality of multi-input logic gates configured to produce a plurality of signals that include at least one or more encoded index signals and at least one multi-hit detection signal; and a logic circuit configured to receive the plurality of signals produced by the static circuit in each DAA column and to derive at least a hit signal that indicates whether one or more rows in the array structure match the search key and a multi-hit signal that indicates whether multiple rows in the array structure match the search key.