1. A semiconductor memory device, comprising: a memory array including memory cells arranged in a matrix of rows and columns; a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array; a DLL circuit receiving and delaying an external clock signal and generating said first clock signal; and a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device.