1. A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may cause a break in an instruction flow and non-exception instructions being instructions that execute in a statically determinable way, said data processing apparatus comprising: at least two processing blocks for processing instructions from said stream of instructions; a first processing block having a set of physical registers associated with it for storing data values being processed by said first processing block, renaming circuitry associated with said first processing block for mapping architectural registers specified in instructions to be processed by said first processing block to physical registers within said set of physical registers; a second processing block having a set of physical registers associated with it for storing data values being processed by said second processing block, said second processing block and registers not supporting renaming; control circuitry configured to identify exception instructions in said instruction stream and to detect when said exception instructions have been committed; said second processing block being configured to receive signals from said control circuitry and to suspend processing of an instruction in said second processing block until all preceding exception instructions have been committed.