1. An adder tree structure comprising a plurality of adder stages, each of said plurality of adder stages being arranged to sum a plurality of vector inputs (A-H) to provide partial vector products, at least one of said adder stages including an adder arrangement comprising first and second half-adder series, each of said half-adder series having vector inputs and vector outputs; said vector outputs of said first half-adder series being coupled to said vector inputs of said second half-adder series such that said first and second half-adders are in cascaded arrangement within said at least one stage.