1. A receiver for performing a decimation on a signal for pattern detection, said apparatus comprising: a frequency-domain decimator component coupled to at least one antenna to receive an input sequence of samples of the signal received at the at least one antenna, wherein the received signal comprises an access pattern, wherein the frequency-domain decimator component is configured to apply an anti-aliasing filter and to decimate the input sequence, wherein the frequency-domain decimator component is further arranged to output the input sequence filtered and decimated as output sequence; and a pattern detector component coupled to the frequency-domain decimator component to receive the output sequence, wherein the pattern detection component is configured to perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns; wherein the frequency-domain decimator component further comprises: a signal partitioner component arranged to partition the input sequence into a number of input blocks each having the same length and overlapping in time by a predefined number of samples; a signal concatenator component arranged to remove a predefined number of samples overlapping from output blocks and to concatenate the remaining part of the of the output blocks to form the output sequence; an N-point frequency-domain transform component arranged to sequentially receive the input blocks and to transform the input blocks into frequency-mapped input blocks in frequency domain; and an L-point time-domain transform component arranged to sequentially receive frequency-mapped output blocks and to transform the frequency-mapped output blocks into output blocks in time domain.