1. A multiprocessor architecture comprising: a plurality of processors; a plurality of low level buses, wherein each processing node is coupled to one of said plurality of low level buses; a plurality of repeaters, wherein each repeater is coupled to one of said low level buses; a top level bus, wherein a plurality of said repeaters are connected to said top level bus and said repeaters control the transfer of data between said low level buses and said top level bus; and a system memory including a plurality of memory locations, and each of said processors is configured to access all of said memory locations; wherein: said system memory locations map to a plurality of address partitions, whereby said system memory locations are addressed by a plurality of address aliases, and properties of said address partitions dictate said control of said transfer of data between said low level buses and said top level bus by said repeaters.