1. A computer-implemented method for performing static timing analysis of a circuit design comprising: partitioning a circuit design into a plurality of levels of gates including at least a first level of gates and a second level of gates, each of the gates in the first level having an input independent of outputs of other gates in the first level, each of the gates in the second level having an input independent of outputs of other gates in the second level; using a processor, performing a first static timing analysis on the first level of gates responsive to loading the first level of gates into a first memory of a computing device; storing results of the first static timing analysis into a second memory of the computing device responsive to performing the static timing analysis on the first level of gates; and responsive to loading the second level of gates into the first memory, performing a second static timing analysis on the second level of gates using the results of the first static timing analysis as arrival times of inputs for the second level of gates.