1. A one terminal capacitor interface circuit for sensing the capacitance of a capacitor comprising: a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to said input common mode voltage; a switching circuit for charging said capacitor to a first voltage level in a first phase, connecting, in a second phase, said capacitor to one of said summing nodes of said differential amplifier to provide a first output change substantially representative of the difference between said first voltage level and said input common mode voltage, and also representative of said capacitor; charging said capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, said capacitor to the other summing node of said differential amplifier to provide a second output change substantially representative of the difference between said second voltage level and said input common mode voltage, and also representative of said capacitor; the combined first and second output changes representing the capacitance of said capacitor substantially independent of said input common mode voltage.