1. A system for improving yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores, the system comprising: a first tester conducting a first test on one or more processor cores in the multiprocessor semiconductor chip; the first tester encoding results of the first test in an on-chip non-volatile memory device in the multiprocessor semiconductor chip; a second tester conducting a second test on the one or more processor cores in the multiprocessor semiconductor chip; the second tester encoding results of the second test in an external non-volatile storage device; the second tester encoding an override bit in the external non-volatile storage device, in response to determining that at least one processor core in the multiprocessor semiconductor chip fails the second test; a controller reading the override bit from the external non-volatile storage device; a multiplexer selecting, in response to the read override bit, a physical-to-logical mapping of IDs (identifiers) of the primary processor cores and the redundant processor cores according to one of: the encoded results in the on-chip non-volatile memory device, or the encoded results in the external non-volatile storage device; and an on-chip logic configuring the primary processor cores and the redundant processor cores according to the selected physical-to-logical mapping of IDs.