1. A memory device having 1-transistor memory cells that allow erase of selected multi-bit words, comprising: multiple 1-transistor memory cells each having a drain, source, floating gate and control gate connected in an array of rows and columns with the control gates of the memory cells in a row connected to a respective wordline and the drains of cells in a column connected to a respective bitline; sources of a selected number of memory cells in rows making up multi-bit words connected to source connect lines; and source bitlines connected to the source connect lines making up columns of multi-bit words having the selected number of bits.