1. An error correction code decoder comprising: a computational memory array having at least a variable node section and a check node section, said computational memory array comprising a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on said bit and each cell implementing one node; and a controller to instruct said computational memory to perform said operations and to write the results of computations on a block of variable nodes into its associated set of blocks of check nodes and to write the results of computations on a block of check nodes into its associated set of blocks of variable nodes.