1. An adder tree structure comprising: first and second adder stages, the first adder stage configured to generate a first and second bit of a first weight, the first adder stage also configured to generate bits of a second weight, the second weight being one bit more significant than the first weight; the second adder stage comprising: an adder configured to receive the bits of the second weight generated in the first adder stage; and an AND gate configured to receive the first and second bits of the first weight, the AND gate configured to generate a carry-in bit for the adder.