1. A processor comprising: a load buffer including a plurality of load buffer entries, each of which having a predictor table entry associated therewith, the predictor table entry including a saturation counter to record a history of previous conflicts between loads and stores corresponding to the same target address; and a watchdog unit coupled to the load buffer and configured to disable a memory disambiguation (MD) logic if the MD logic causes a maximum rate of mispredictions of whether load operations from a first memory address and store operations to the first memory address will conflict with each other, wherein the MD logic is to be disabled if a ratio of the saturation counter value and a flush counter value reaches a threshold value.