1. A semiconductor device comprising: a memory for storing a plurality of instructions therein; an instruction queue which temporarily stores instructions fetched from the memory; a central processing unit which executes instructions supplied from the instruction queue; an instruction cache which stores instructions which have been executed in the past by the central processing unit; and a control circuit which controls fetching of instructions, wherein: when the central processing unit executes a branch instruction, and an instruction of a branch destination is stored in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes: the instruction queue to fetch the instruction of the branch destination from the instruction cache; and the instruction queue not to fetch the instruction following the instruction of the branch destination; wherein when the central processing unit executes a branch instruction and an instruction of a branch destination is not stored in the instruction cache, the control circuit causes: the instruction cache to fetch the instruction of the branch destination from the memory; and the instruction cache to store the same therein; wherein when the central processing unit executes a branch instruction, and an instruction of a branch destination is stored in the instruction cache and an instruction following the instruction of the branch destination is not stored in the instruction queue, the control circuit causes: the instruction queue to fetch the instruction of the branch destination from the instruction cache; and the instruction queue to fetch the instruction following the instruction of the branch destination from the memory; wherein the instruction queue includes a number N entries, N≧2, each entry capable of storing one or more instructions therein, wherein the instruction queue fetches instructions from the memory in entry units, wherein the instruction cache includes a plurality of entries, each entry storing therein instructions corresponding to a number M entries of the instruction queue, M<N; wherein when the central processing unit executes a branch request and an instruction of a branch destination is stored in any entry of the instruction cache, the control circuit causes instructions to be fetched into the first through Mth entries of the instruction queue from the entry of the instruction cache in which the instruction of the branch destination is stored; wherein the control circuit determines whether a reuse condition is being satisfied, the reuse condition being that the instruction stored in each of the M+1th through Pth entries of the instruction queue, P being a number such that M<P≦N, has not yet been supplied to the central processing unit after a branch instruction has been executed previously or the instruction is not fetched anew from the memory after having been supplied to the central processing unit, and wherein when the central processing unit executes a branch instruction, and an instruction of a branch destination is stored in the most recently used entry of the instruction cache and the reuse condition is being satisfied, the control circuit causes instructions not to be fetched into the M+1th through Pth entries of the instruction queue so that they are available for reuse by the central processing unit.