1. A data storage device comprising: a non-volatile solid-state memory array comprising a plurality of non-volatile solid-state memory devices configured to store data; and a controller configured to: determine a known reference bit stream comprising a plurality of bit values recorded in a plurality of memory cells, respectively, at a reference memory location; obtain a bit pattern for each of the plurality of memory cells at the reference memory location by performing a first plurality of reads on each of the plurality of memory cells at the reference memory location at a plurality of voltage read levels, wherein the bit pattern comprises a bit value from each of the first plurality of reads, wherein the bit pattern is correlated with a respective bit value of the reference bit stream recorded in a respective memory cell at the reference memory location; determine probability data based at least in part on a number of occurrences of the respective bit patterns obtained for the plurality of memory cells at the reference memory location and the correlated respective bit values of the reference bit stream; generate possible log likelihood ratios (LLRs) based at least in part on the probability data; store the possible LLRs in association with the reference memory location; select, in connection with a multiple read operation on a target memory location, the stored possible LLRs based on a predetermined association between the target memory location and the reference memory location; generate a sequence of LLRs based at least in part on the selected possible LLRs and on bit patterns from a multiple read operation on a target memory location; and decode data stored in the target memory location using the generated sequence of LLRs.