1. A method for chargeback with simultaneous multithreading (SMT) by a computer, the method comprising: managing, by one or more of an operating system and a second-level hypervisor of the computer, a logical core configuration for simultaneous multithreading, the one or more of the operating system and the second-level hypervisor having control over a logical core and control over logical threads on the logical core; configuring, by the one or more of the operating system and the second-level hypervisor of the computer, a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core; running the logical core on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core; determining a capacity use time for each of the logical threads executing on the physical threads of the single physical core; determining core cycles operating at a thread density of 1 (C_1); determining core instructions complete at a thread density of 1 (I_1); determining core cycles operating at a thread density of 2 (C_2); and determining core instructions complete at a thread density of 2 (I_2); determining instructions per cycle (IPC) at a thread density of 1 as IPC 1=I_1/C_1; and determining instructions per cycle (IPC) at a thread density of 2 as IPC 2=I_2/C_2; calculating a workload instructions per cycle as workload IPC=(I_1+I_2)/(C_1+C_2); calculating an effective runtime capacity metric as effective runtime capacity=(workload IPC)/(IPC_1); calculating a runtime average thread density as average thread density=(C_1+2*C_2)/(C_1+C_2); calculating a runtime chargeback factor as runtime chargeback factor=(runtime capacity)/(runtime average thread density); calculating a capacity use time metric as capacity use time=(thread timer delta)*(runtime chargeback factor); wherein the thread timer delta is the timing for one of the logical threads.