1. In a data processing system having a central processing unit having an internal memory including a plurality of addressable register locations, and a means for addressing said register locations in response to address data stored in a particular address register, the combination comprising, (A) a program counter register allocated in said internal memory; (B) a program status word register allocated in said internal memory; (C) a plurality of memory areas disposed in said internal memory storing for use of interrupt programs a plurality of sets of a start address, a program status word, and a register bank pointer code; said central processing unit including: a pointer address register storing a first register bank pointer code for designating a first register location group in said internal memory; a first address register storing a register address code for designating a selected register location in said first register location group designated by said first register bank pointer code; means for combining said first register bank pointer code from said pointer address register with an address code from said first address register, and for generating an address for accessing said selected register location in said first register location group in said internal memory through said addressing means during execution of a first program which may be a so-called main program or an interrupt program; means for detecting an interrupt request for initiating execution of a second program which is an interrupt program; and means for swapping the respective contents of said program counter register, said program status word register, or said pointer address register with one of said plurality of memory areas in response to said interrupt request and for swapping the contents of said program counter register with the contents of one of the registers in the register location group which is selected by the current value of said pointer address register.