1. A computing resource attached to a memory that is external to the computing resource, the memory-attached computing resource comprising: (a) a first set of logical gates configured as a packet reader state machine to receive a packet from a first one of a plurality of computing resources different from the memory-attached computing resource and unattached to the memory, the memory-attached computing resource and at least a subset of the plurality of computing resources being implemented as a system on a chip, the received packet comprising (i) a memory address of the memory, (ii) one or more operation codes, and (iii) an address of a second one of the plurality of computing resources; (b) a second set of logical gates configured as a memory reader state machine to access the memory and read data from the memory address; (c) an arithmetic logic unit (ALU) configured to process the read data based at least in part on the one or more operation codes; (d) a third set of logical gates configured as a memory writer state machine to access the memory and write the processed data; (e) a fourth set of logical gates configured as a packet writer state machine to transmit, to the address of the second one of the plurality of computing resources, one of the following packets: (i) a packet including an indication that the data at the memory address has been processed, or (ii) a packet including the processed data; and (f) a multiplexer configured to route, within the memory-attached computing resource, at least the following data: (i) the read data from the second set of logical gates to the ALU, and (ii) the processed data from the ALU to the third set of logical gates and to the fourth set of logical gates.