1. An apparatus comprising: a processor core integrated on a die, the processor core having an embedded trace macrocell (ETM) interface; a memory coupled to the processor core by way of an instruction bus, the memory integrated on the die; and a hardware-based state machine coupled to the processor core via the instruction bus and the ETM interface, the hardware-based state machine integrated on the die, wherein the hardware-based state machine checks the instruction bus to determine that an instruction having a proper sequence of signals is delivered to the processor core, and wherein the hardware-based state machine checks the ETM interface to determine whether the instruction is properly executed by the processor core.