1. A pulse width determining circuit block, comprising: means for producing a set of specified delays of the DPPM signal relative to a leading signal pulse edge, the specified delays being selected to correspond to all but the longest expected pulse transition times for a set of possible N-bit data values; a set of AND logic gates, each AND logic gate having a first input coupled to receive the DPPM signal without a delay and a second input coupled to receive the DPPM signal with one of the specified delays, each AND logic gate also having an output; a set of registers, each register having a reset input for resetting that register to a known state at a start of each DPPM signal pulse, a data input tied to receive an opposite value from said known state, a clock input coupled to the output of a corresponding AND logic gate, and a register output; and logic means, coupled to the register outputs from the set of registers, for converting the set of registered states to the corresponding N-bit data value for each DPPM signal pulse.