1. A configurable computing processor chip comprising: configurable elements for configurably processing data, the configurable elements being arranged in an array and being interconnected via a configurable interconnect system, the array comprising: a plurality of programmable gate array (PGA) elements; a plurality of dedicated multi-bit ALU elements each having at least one multi-bit adder and one multi-bit multiplier and being configurable in function; and a plurality of multi-bit configurable RAM elements; and at least one configurable multi-bit IO function unit communicatively coupled to the array.