1. A computer implemented method for implementing a heterogeneous core microarchitecture, the method comprising: binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows; issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds; determining the tag associated with the instruction; responsive to the determining, dispatching the instruction to first hardware or a second hardware according to the tag, wherein the first hardware comprises a dedicated L1 instruction cache coupled to two 3-way flow dispatching units, the two 3-way dispatching units being coupled to a plurality of execution units and an L1 data cache, and the second hardware comprises a 64 kilobyte local instruction cache which loads instructions from an L2 cache; and executing the instruction by the flow in the core that is indicated by the tag.