1. A microprogram controller having output means for generating through said output means microinstruction address signals used to access a program memory element containing a plurality of microinstructions, there being a first register means connected to said memory element for receiving and temporarily holding microinstructions accessed from said memory element by said microinstruction address signals and bus means for communicating a portion of said accessed microinstruction from said first register means to said microprogram controller, said microprogram controller comprising: input means connected to said bus means for receiving instruction words and data words; decode means connected to said input means for receiving said instruction words to generate therefrom a plurality of control signals; first address generating means, having second register means and incrementing means operably interconnected to provide sequentially incremented address signals; storage means responsive to said control signals for selectively storing address signals; and first multiplex means, connected to said input means, said first address generating means and said storage means, for selectively coupling said input means, said first address generating means, and said storage means to said output means in response to said control signals, said first address generating means and said storage means further connected to a first multiplex output terminal means for receiving signals therefrom in response to said control signals; whereby said microinstruction address signals are generated.