1. A processor comprising: a plurality of cores to issue a corresponding plurality of operating requirements; and coordination logic coupled to the plurality of cores, the coordination logic to coordinate a shared resource setting of the plurality of cores with the plurality of operating requirements, the coordination logic to coordinate the shared resource setting with an independent resource setting of at least one of the plurality of cores, the coordination logic to select the shared resource setting according to a first operating requirement of a first core and a second operating requirement of a second core, the first core to select an adjusted value for the independent resource setting that enables the first operating requirement to be satisfied.