1. A processor, comprising: at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions, wherein the BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon a combination of at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address, wherein the set of higher order bits and the set of lower order bits are discontiguous.