1. A superscalar pipelined microprocessor, comprising: a register set, defined by an instruction set architecture of the microprocessor; a cache memory; execution units; and a load unit, coupled to the cache memory, wherein the load unit is distinct from the other execution units of the microprocessor, the load unit comprising an arithmetic/logic unit (ALU); wherein the load unit is configured to receive an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored; wherein the load unit is configured to read the source operand from the cache memory; wherein the ALU is configured to perform the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result; wherein the load unit is further configured to output the result for subsequent retirement to the destination register.