1. In a data processing machine having an instruction processing unit including of stages in a pipeline configuration, having a pipeline offset of P, where P is a number of stages greater than or equal to 1, for executing a stream of instructions in which stage N is responsive to a stage release signal to release a current instruction and proceed with processing of a following instruction; in which the instruction processing unit includes validity logic generating stage valid control signals indicating current processing of a valid instruction in corresponding stages; and in which processing in the Nth stage of a dependent instruction is dependent is dependent on processing in the Mth stage of a previous instruction in the stream of instructions, where M-N is greater than P; an improvement comprising: release enabling means, in communication with the Nth stage and the validity logic and receiving a delay interlock signal, for enabling an Nth stage release signal in response to a characteristic of the stage valid control signals identified by the delay interlock signal; and interlock control means, responsive to prespecified instructions in the stream of instructions for generating the delay interlock signal.