1. A circuit arrangement, comprising: a plurality of functionally interchangeable dynamic logic cells disposed in an array, each functionally interchangeable dynamic logic cell including a plurality of inputs, a logic circuit configured to generate an output as a function of the plurality of inputs using dynamic logic, and an output latch configured to latch the output of the logic circuit; and a plurality of conductors electrically interconnecting inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells to configure the plurality of functionally interchangeable dynamic logic cells to collectively implement an application specific logic function.