1. In a processor having a register set that includes a plurality of physical registers to which a plurality of logical registers are mapped, a method comprising: providing an array having a plurality of entries each corresponding to a respective one of a plurality of instructions in an instruction stream; and in response to dispatch of an instruction among the plurality of instructions within said instruction stream: setting, in an entry among the plurality of entries in a row of the array corresponding to the instruction, one or more fields corresponding to one or more of said plurality of logical registers on which said instruction is data dependent; after said setting, comparing the entry to a vector indicating one or more logical registers ready to serve as operand sources for data dependent instructions; and in response to said comparing, outputting an indication of any instruction having no remaining data dependency.