1. A parallel pulse signal processing apparatus including a plurality of pulse output arithmetic elements, a plurality of connection elements which parallelly connect predetermined elements of the arithmetic elements, and a gate circuit which selectively passes pulse signals from the plurality of connection elements, characterized in that said arithmetic element comprises input means for inputting a plurality of time series pulse signals, modulation processing means for executing predetermined modulation processing on the basis of the plurality of time series pulse signals which are input, and pulse output means for outputting a pulse signal on the basis of a result of modulation processing, and said gate circuit selectively passes, of the signals from said plurality of connection elements, a finite number of pulse signals corresponding to predetermined upper output levels.