1. A data processing apparatus comprising: processing circuitry configured to execute a sequence of instructions; pre-decoding circuitry configured to receive the instructions fetched from memory and to perform a pre-decoding operation to generate corresponding pre-decoded instructions; a cache configured to store the pre-decoded instructions for access by said processing circuitry; wherein the pre-decode operation, for each instruction fetched from the memory, detects whether the instruction is an abnormal instruction, wherein an abnormal instruction is an undefined instruction or an unpredictable instruction, and upon such detection provides, in association with a corresponding pre-decoded instruction, an identifier identifying that instruction as abnormal, wherein said identifier identifies said abnormal instruction as undefined irrespective of whether the abnormal instruction is an unpredictable instruction or an undefined instruction.