1. An instruction processing circuit configured to: detect a first conditional write instruction in an instruction stream indicating an operation writing a first value to a target register based on evaluating a first condition; detect a second conditional write instruction in the instruction stream indicating an operation writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition; select one of the first condition or the second condition as a fused instruction condition; select one of the first value or the second value corresponding to the fused instruction condition as an if-true value; select one of the first value or the second value not corresponding to the fused instruction condition as an if-false value; and generate a fused instruction indicating an operation selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.