1. An integrated structure layout for an instruction execution unit of an integrated circuit chip, comprising: a row of data dependency comparator blocks, wherein each data dependency comparator block is configured to compare at least one source operand address of a first instruction to a destination operand address of a second instruction and to output data dependency information; and a tag assignment logic block coupled to the data dependency comparator blocks to receive the data dependency information, wherein the tag assignment block is positioned approximately at the center of the row of data dependency comparator blocks to conserve area on the integrated circuit chip, and wherein the tag assignment logic block outputs tag information identifying an address in a register file responsive to receiving the data dependency information.