1. A cross point memory array comprising: a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other; a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer; and a plurality of memory plugs, each memory plug having a memory element that in a first write mode, switches from a first resistance state to a second resistance state upon application of a first write voltage pulse across the memory element; in a second write mode, reversibly switches from the second resistance state back to the first resistance state upon application of a second write voltage pulse across the memory element; and in a read mode, does not experience any significant resistive changes upon application of a read voltage across the memory element; and being in electrical contact with one conductive array line from the first layer and one conductive array line from the second layer, the conductive array lines forming a unique pair for each memory plug; wherein both the first write mode and the second write mode are preceded by the read mode to determine the resistive state of the memory element.