1. A high speed and low power fixed-point multiplier, comprising: a partial product calculation means for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying a fixed coefficient for each bit group, and summing partial products included in a corresponding bit group, to thereby generate a summed partial products; and an adding means for adding the summed partial products of each bit group generated from the partial product calculation means.