1. An integrated dynamic memory, comprising: a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells, said regular memory cells, said first test cells and said second test cells being for storing a charge corresponding to an information bit; a control unit for refreshing charge contents of said regular memory cells with a first refresh time; a control unit for refreshing charge contents of said first test cells with a second refresh time, and for refreshing charge contents of said second test cells with a third refresh time; and an evaluation unit for detecting memory cell defects in said first test cell area and in said second test cell area; said first refresh time being shorter than said second refresh time; and said second refresh time being shorter than said third refresh time.