1. An apparatus, comprising a set of multiple programmable units integrated within a processor, wherein the apparatus comprises circuitry to: map addresses in a single address space to resources within the set of multiple programmable units integrated within the processor, the single address space including addresses for different ones of the resources in different ones of the multiple programmable units; and provide data access to a resource within a first of the multiple programmable units to a second one of the multiple programmable units in response to a data access request of the second one of the multiple programmable units that specifies an address within the single address space, wherein there is a one-to-one correspondence between respective addresses in the single address space and respective resources within the multiple programmable units.