1. A microprocessor comprising: a fetch unit operative to fetch architectural instructions from memory; an uncompressed microcode memory storage having M-bit wide addressable words; a compressed microcode memory storage having N-bit wide addressable words, where N<M; an instruction translator operative to receive the architectural instructions supplied by the fetch unit and translate them into microinstructions executable according to a microinstruction set architecture of the microprocessor; and an execution stage operative to receive microinstructions from the instruction translator and execute them; wherein when the instruction translator receives an architectural instruction, it: writes information identifying source and destination registers specified by the architectural instruction to an indirection register; issues one or more fetch addresses to retrieve a sequence of one or more microcode instructions from one of the uncompressed microcode memory storage and the compressed microcode memory storage to implement the architectural instruction; merges information in the indirection register with the sequence of one or more microcode instructions to generate a sequence of one or more implementing microinstructions; a plurality of cores, each core having a corresponding core ROM that is private to the core; an uncore ROM shared by the plurality of cores; arbitration logic configured to arbitrate among the cores when they request access to the uncore ROM; and wherein each core is configured to fetch microcode instructions from its own core ROM and the uncore ROM.