1. An accumulating multiplication circuit including a multiplication part and an arithmetical operation part, said multiplication part comprising: first to four registers for holding most significant "n" bits of a multiplier, where "n" is a positive integer, least significant "n" bits of said multiplier, most significant "n" bits of a multiplicand, and least significant "n" bits of said multiplicand, respectively, a first multiplexor for selecting either an output data of said first register or an output data of said second register, so as to supply the selected output data, a Booth's decoder receiving said selected output data outputted from said first multiplexor, a second multiplexor for selecting either an output data of said third register or an output data of said fourth register, so as to supply the selected output data, a partial product generating circuit receiving an output of said Booth's decoder and an output of said second multiplexor, for generating a partial product, and a partial product adder circuit receiving and summing said partial product from said partial product generating circuit and for outputting the summed result to said arithmetical operation part, said arithmetical operation part comprising: fifth and sixth registers for respectively holding the most significant "n" bits and the least significant "n" bits of data used for the arithmetical operation with the partial product generated in said multiplication part, a third multiplexor having a first input receiving the "2n" bit--data held in said fifth and sixth registers, a second input receiving 0 and a third input, a shifter receiving an output data of said third multiplexor for shifting the received data rightward by "n" bits, a fourth multiplexor selecting either said output data of said third multiplexor or an output data of the shifter so as to supply the selected data, an arithmetical operation circuit receiving an output of said fourth multiplexor and an output of said partial product adder circuit, for outputting a "2n-bit" output data which is a result of the operation, an output of said arithmetical operation circuit being supplied to said third input of said third multiplexor, and seventh and eighth registers respectively receiving and holding the most significant "n" bits and the least significant "n" bits of said "2n-bit" output data outputted from said arithmetical operation circuit.