1. A memory-control device that is located between a processor and a plurality of memory ranks, and that controls access to the memory ranks, comprising: a memory-management unit that receives and buffers an access request from the processor to any of the memory ranks, and issues an access request to a rank-management unit based on scheduling for memory management; and a rank-management unit that connects the plurality of ranks, receives and buffers said access request from said memory-management unit, and gives said access request to any one concerned of the memory ranks based on scheduling for rank management.