1. In combination with a logic performing array comprising a grid of intersecting input and output lines with operative logic means located in at least some of the intersections and having a plurality of input decoders each interrogating a selected one of a plurality of input lines so that logic functions are performed on interrogating signals by the logic means and results presented on the output lines, apparatus for testing the array comprising; a control decoder in which each different combination of input signals to the decoder causes the decoder to select a different one of the output lines of the control decoder; and, And circuit means in each input decoder for ANDing one output of the control decoder with a true or inverted signal for each of the inputs of the decoder to generate an interrogation signal for each of the input lines of the array that is dependent on the presence of a select signal from the control decoder, check line means intersecting the input lines for maintaining check information on the number of operative logic means located along each of the input lines of the array whereby the number of bits of each input line can be read out along with the check information to be used in a determination to see if the line is properly configured.