1. An interface between a memory subsystem and a processor, wherein the memory subsystem is capable of multiple concurrent transactions, the interface comprising: means for sending memory requests from the processor to the memory subsystem, the memory requests including read requests and write requests; means, within the memory subsystem, for reordering memory requests from an order of receipt from the processor to an alternate order; and means, within the memory subsystem, for receiving reordering constraints from the processor and for constraining the means for reordering according to the received reordering constraints.