1. A method of producing a physical layout for a structured ASIC that is functionally equivalent to an FPGA programmed to implement a user's logic design comprising: for each circuit block in a netlist for a structured ASIC implementation of the user's logic design, retrieving from a library a structured ASIC physical layout of that block; placing the physical layouts of the blocks on a structured ASIC template; and laying out on the structured ASIC template interconnections between the physical layouts of the blocks in accordance with the netlist.