1. A processor, comprising: an instruction fetch unit to provide an instruction address; an instruction cache to produce an instruction tag and instruction cache content corresponding to the instruction address; a boundary byte predictor to receive the instruction tag and generate a prediction vector to indicate a prediction of a first byte of an instruction, the prediction vector including a bit corresponding to each byte in a group of instruction cache content bytes, wherein the boundary byte predictor includes an array of filters, and further wherein each filter is to produce a bit value based on a hash of the instruction tag; and an instruction decoder including boundary byte logic to determine an instruction boundary in the instruction cache content, wherein the boundary byte logic is to form an initial prediction of the first byte of the instruction based on the prediction vector, and to decode the instruction beginning with the predicted first byte of the instruction.