1. A processor core, having an execution unit for processing instructions, comprising: a programmable mask register; a decoder to decode each instruction in a sequence of instructions to generate decoded bits; an encoder coupled to the decoder and configured to selectively encode the decoded bits to produce values representing the sequence of instructions, wherein each value is smaller in size than an instruction that it represents; a buffer that stores the values representing the sequence of instructions; and control logic to determine whether there is a match between a sequence in the mask register and the values representing the sequence of instructions in the buffer and, upon detecting a match, to generate control signals to perform a desired action.