1. A cache controller used in a computer system that includes a cache memory, a main memory, and a microprocessor which concurrently executes a plurality of tasks, comprising: a region managing unit operable to manage a plurality of regions in the cache memory in correspondence with the plurality of tasks; an address receiving unit operable to receive, from the microprocessor, an address of a location in the main memory at which data to be accessed to execute one of the plurality of tasks is stored; and a caching unit operable to acquire, if the data to be accessed is not stored in the cache memory, a data block including the data from the main memory, and store the acquired data block into a region in the cache memory corresponding to the task.