1. A clocked accumulating logic processor without feedback and responsive to a single bit input signal (LB) for converting a single bit logic answer signal (LA) to the result of a "load", "and", "or" or "exclusive or" operation represented by function code signals, said processor comprising, in combination: (a) a JK type flip-flop having J and K control terminals, a clock input CP, and having an output terminal Q upon which the answer signal LA appears, (b) means responsive solely to "load" function code signals and said input signal (LB) for applying to said J or K terminals a 1 level signal when the input signal (LB) is respectively at a 1 or 0 level, (c) means responsive solely to "and" function code signals and said input signal (LB) for applying to said K terminal a 1 level signal only when the input signal (LB) is at a 0 level, (d) means responsive solely to "or" function code signals and said input signal (LB) for applying to said J terminal a 1 level signal only when the input signal (LB) is at a 1 level, (e) means responsive solely to "exclusive or" function code signals and said input signal (LB) for applying to both said J and K terminals a 1 level signal only when said input signal (LB) is at a 1 level, said means (b)-(e) including means for applying 0 level signals to said J and K terminals except in the cases specified above, and (f) means for applying a pulse to said clock input after any of said means (b)-(e) has applied the respectively specified 1 level signals, whereby said answer signal (IA) takes on a new bistate value LA.sub.n respectively according to the Boolean functions LA.sub.n =LB, LA.sub.n =LA.sub.o .multidot.LB, LA.sub.n =LA.sub.o +LB, or LA.sub.n =LA.sub.o .sym.LB despite the fact that said signal LA.sub.o does not participate in the operation of said means (b)-(e).