1. A digital instruction processor control which cyclically executes, in a single cycle, instructions from a set, including a plurality of plural-bit branch instructions, stored in an instruction cache having a plurality of locations each with a designator, said processor control comprising: means for generating signals indicative of a "continue with instruction" address; means responsive to continue address signals and to predetermined bit portions of said branch instructions for generating signals indicative of a "branch target" address; and first multiplexer means having an output terminal connected to said instruction cache responsive to a control signal indicative of contents of a predetermined "condition" bit portion of said branch instruction, responsive to branch target address signals applied to a first input terminal of said first multiplexer means and responsive to said continue address signals applied to a second input terminal of said first multiplexer means for selectively conducting to said output terminal one of said address signals indicative of a location within said instruction cache from which to fetch a next instruction to be processed by said instruction processor; wherein said branch target address generating means comprises: second multiplexer/register means having an output terminal connected to said first input terminal of said first multiplexer means responsive to a control signal indicative of which of said plurality of branch instructions is being executed, responsive to signals applied to a first input terminal indicative of an "indirect address" determined by said branch instructions, and responsive to signals applied to a second input terminal indicative of a "relative or absolute branch address" for selectively conducting to said output terminal one of said address signals indicative of said branch target address; and adder means having an output terminal connected to said second input terminal of said second mutliplexer/register means responsive to said control signal indicative of which of said plurality of branch instructions is being executed, responsive to signals applied to a first input terminal indicative of a "branch displacement" portion of said branch instructions, and responsive to said continue address signals applied to a second input terminal for selectively generating at said output terminal said relative or absolute branch address. PG,15