1. A processor, comprising: a floating-point unit configured to execute an unfused multiply-accumulate instruction defined with an instruction set architecture (ISA), wherein the unfused multiply-accumulate instruction includes a multiply sub-operation and an accumulate sub-operation; a storage configured to maintain floating-point exception state information; and exception logic configured to capture floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, and to update the storage to reflect the floating-point exception state.