1. A dimension reduction apparatus comprising: a memory; and processing circuitry configured to, obtain a first vector made up of a plurality of elements; generate a plurality of first partial vectors, each of the first partial vectors being made up of one or more elements of the plurality of elements; transform each of the first partial vectors into a second partial vector by reducing number of elements constituting the first partial vector using first mapping corresponding to the first partial vector, concatenate the second partial vectors formed after transformation, and generate a second vector as a result of reducing number of dimensions of the first vector; apply, with respect to the second vector, second mapping which maps the second vector into a space having number of dimensions equal to or smaller than number of dimensions of the second vector, and generate a third vector as a result of reducing the number of dimensions of the second vector to equal to or smaller than the number of dimensions of the second vector; and output the third vector.