1. A multi-channel SPI interface memory controller, disposed between a central processing unit (CPU) and a multi-channel serial peripheral interface (SPI) interface memory, comprising: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; and a register bank disposed between the master controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface, wherein the master controller comprises a main state machine, wherein the main state machine has six logical states: idle, instruction, address, dummy, wait, and data, wherein the master controller controls the main state machine to transition to one of the six logical states after parsing an instruction in the register bank.