1. A method for performing delay, area, and leakage power optimization on a circuit design, the method comprising: iteratively performing, by computer, at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: performing numerical delay optimization on the circuit design using a numerical delay model that is generated using gates whose threshold voltages are equal to the current threshold voltage; and performing a worst negative slack touchup optimization on the circuit design, wherein the worst negative slack touchup optimization uses gates whose threshold voltages are greater than or equal to the current threshold voltage.