1. A low-power amplifier with adaptive power biasing for use in multi-electrode arrays, wherein the amplifier is implemented using a modified version of a standard folded-cascode topology, the modification involving biasing an operational transconductance amplifier such that only currents in transistors of a folded branch are only a fraction of the current in the input differential pair transistors, whereby the fraction is achieved by controlling a resistance and controlling a transistor as a parallel combination of a first set of transistors while the input differential pair transistors are each constructed from a second set of transistors in parallel.