1. A method comprising: performing a stress test of a memory device in a memory subsystem with a test component embedded in a host, including testing an operation of the memory device at a performance level higher than a maximum guaranteed performance rating for the memory device, the host including a processor and a memory controller, the memory controller coupled to the memory device, the test component within the memory controller and/or outside the memory controller on a processor side of the memory controller and coupled to an input of the memory controller; detecting within the host specific bits that experience failure in response to the stress test; and the host configuring the memory device for mapping out the detected specific bits to disallow use of the detected specific bits in runtime operation of the memory subsystem.