1. A method comprising: storing in a memory a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model; automatically generating, by a processor configured to access the first intermediate representation from the memory, hardware description language (HDL) code from the first intermediate representation; receiving one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code; mapping the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation; selecting, by the processor, an optimization technique; applying the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption; repeating the automatically generating, the receiving, the mapping, the selecting, and the applying steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code; and configuring a programmable hardware element based on the HDL code or the revised HDL code.