1. A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block including a logic/memory circuit comprising: a first plurality of input terminals for receiving a first set of input signals from the interconnect resources; a decoder for generating address signals in response to the first plurality of input signals; an array including programmable elements for storing a plurality of bit values, word lines connected to the decoder for receiving the address signals, and bit lines for transmitting bit values to the programmable elements in response to the address signals; an input control circuit connected to the first plurality of input terminals for selectively transmitting the first set of input signals onto a group of the bit lines; and a product term circuit for generating a plurality of product terms in response to the first set of input signals transmitted on the group of the bit lines and the bit values stored in the programmable elements.