1. A computer implemented method of placing a system on a structured application specific integrated circuit (ASIC), the method comprising: identifying a subregion from a layout design placement solution for structured ASIC cells that includes a first structured ASIC cell that overlaps a component and is positioned illegally; removing the first structured ASIC cells and a second structured ASIC cell in the subregion from the layout design placement solution; determining a legal position for any of the first and the second structured ASIC cells residing in a crowded area of the subregion as determined from the layout design placement solution prior to determining a legal position for any of the first and second structured ASIC cells residing in an un-crowded area of the subregion as determined from the layout design placement solution; and placing the first and the second structured ASIC cells from the subregion at determined legal positions.