1. A computing device for memory encryption, the computing device comprising: a cryptography module to generate a keyed hash of a data line based on a statistical counter value and a memory address to which to write the data line, wherein the statistical counter value has a reference probability of incrementing at each write operation; and a data access module to store the keyed hash to a cache line, wherein the cache line includes a plurality of keyed hashes and each of the keyed hashes corresponds with a different data line; wherein the cryptography module is further to encrypt the data line based on the keyed hash, the memory address, and the statistical counter value.