1. A low-power data processor in which an instruction module to be repeatedly executed is read out from an instruction memory and fetched by an instruction fetch register in such a way as to decrease the power consumption of the processor, said data processor comprising: an on-chip instruction buffer for storing only at least a part of the instructions of an instruction module to be repeatedly executed; and repeat control means for successively transferring the instructions in said instruction module from said instruction memory to said instruction buffer as well as to said instruction fetch register at the first time of execution of said instruction module, and, when the number of the instructions of said instruction module to be repeatedly executed as stored in said instruction buffer equals the capacity of said instruction buffer, stopping storage of the remaining instructions of said instruction module in said instruction buffer while continuing to transfer the remaining instructions to said instruction fetch register from said instruction memory and storing information used for controlling reading of each of the instructions stored in said instruction buffer, including means operating during each subsequent time of execution of the instructions of said instruction module for transferring the instructions stored in said instruction buffer to said instruction fetch register only from said instruction buffer and for transferring the remaining instructions which are not stored in said instruction buffer to said instruction fetch register from said instruction memory, on the basis of said stored reading control information.