1. An apparatus comprising: an execution unit within a processor to execute a process, the execution unit adapted to: execute a save instruction to cause the processor to store a micro-architectural state and an architectural state of the processor in a common buffer located within a memory upon a context switch that suspends an execution of the process, wherein the micro-architectural state contains performance data resulting from the execution of the process; and execute a restore instruction to cause the processor to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process; and power management hardware coupled to execution unit, wherein the power management hardware is adapted to: use the micro-architectural state as an intermediate starting point for the resume execution to increase efficiency of the execution.