1. An apparatus with circuit redundancy comprising: a first subset of parallel arithmetic logic units; a second subset of parallel arithmetic logic units; a redundant ALU in parallel with said first and second subsets of parallel ALUs; and input data shifting logic, operatively coupled to the first and second subsets of parallel arithmetic logic units comprising multiplexing logic that is operatively coupled to receive input data for an end ALU in each of the first and second subsets of parallel ALUs and wherein the multiplexing logic is operatively coupled to the redundant parallel ALU and is operative to provide selected input data from either of an end ALU from said first subset of ALUs or an end ALU from the second subset of ALUs, such that the data shifting logic, in response to a defect, is operative to shift input data, using the multiplexing logic, among a plurality of subsets of parallel ALUs to provide input data to the redundant ALU.