1. A method for use in a computer system having a central processing unit (CPU) having a processor and a system management interrupt dispatcher, a cache coupled to the CPU, and a chipset memory controller that interfaces the CPU to a memory comprising system memory and system management random access memory (SMRAM), the method comprising the steps of: un-caching the SMRAM while operating outside of system management mode; transferring CPU operation to system management mode in response to execution of a system management interrupt; changing cache settings to cache the extended memory and system management random access memory with write-through; changing cache settings to cache the extended memory with write-back and uncache the SMRAM; and executing a resume instruction to exit SMM mode.