1. A computer implemented method for verifying an electronic design with a graph-based verification flow, comprising: determining a data propagation diagram for an electronic design model of an integrated circuit at least by identifying a set of data locations as a plurality of nodes connected by a plurality of connections identified as a plurality of edges in the data propagation diagram of the electronic design model, wherein a data location includes a circuit component storing signal values in the electronic design model; determining, at a helper property generation module that is stored at least partially in memory of a computing system and functions in tandem with at least one processor executing a sequence of instructions, a set of helper properties for the data propagation diagram at least by traversing at least a portion of the data propagation diagram and reducing a search space for a verification engine at least by removing from verification at least one node determined to be unreachable, wherein a helper property is used to help verify at least another property for the electronic design model; verifying the electronic design model with the verification engine that examines at least one helper property and determines whether the at least one helper property is verified to generate verification results for the electronic design model; and implementing the electronic design model of the integrated circuit based in part or in whole upon the verification results.