1. A method of operating a processor to execute a plurality of instances of an instruction, the instruction comprising an opcode, the processor having a plurality of lanes for parallel execution of instructions, the instruction being supplied in a first lane of the plurality of lanes, the method comprising: a) determining a number of instances of the instruction to be executed in parallel; and b) replicating the opcode of the instruction in at least one second lane of the plurality of lanes, whereby the number of instances of the instruction is executed in parallel.