1. Configurable logic device comprising a plurality of configurable logic cells, a configurable logic cell comprising: a plurality of multi-bit registers, at least one being accessible both in a parallel and in a serial fashion, a functional unit coupled to two or more of the registers, comprising a chain of functional unit segments that each comprise an AND gate and a 1-bit full adder receiving an output of the AND-gate, an output selection facility for providing an output signal of the configurable logic cell selected from two or more input signals, at least one of the input signals being provided by one of the multi-bit registers, and another provided by the functional unit, an input selection facility for selectively providing one of two or more input signals to one of the multi-bit registers, at least one of the input signals being provided by the functional unit, the input selection facility causing a bit-shift-operation to a first of the input signals when selected and causing another one of the input signals when selected to be passed unchanged, and a bit selection facility for selectively providing a bit of an output signal of one of the multi-bit registers to the functional unit.