1. A processor for floating point underflow detection, comprising: circuitry to decode a first instruction, the first instruction when executed by the processor is to perform a fused multiply-add (FMA) operation; and a floating point unit including circuitry to: determine a non-normalized result of the first instruction based on a first input, a second input, and a third input; determine whether underflow exists in the non-normalized result based on a first exponent of the first input, a second exponent of the second input, and a third exponent of the third input; determine an unrounded normalized result and an unrounded result bypass extension based on the non-normalized result; and route the unrounded normalized result and the unrounded result bypass extension via a bypass path to the floating point unit for a second instruction, the second instruction when executed by the processor is to perform another FMA operation.