1. A microprocessor comprising a plurality of functional units configured to execute instructions including a prefetch instruction, said prefetch instruction including: (i) a functional unit field identifying one of said plurality of functional units which is to operate upon data identified by said prefetch instruction; and (ii) a read/write specifier field indicating an access mode for said data; wherein said microprocessor is configured to prefetch said data in response to said prefetch instruction; wherein said microprocessor further comprises a plurality of read-only caches, wherein each one of said plurality of read-only caches is coupled to a different one of said plurality of functional units, and wherein said microprocessor is configured to store said data into said one of said plurality of read-only caches coupled to said one of said plurality of functional units identified by said functional unit field if said access mode is read-only, and wherein said each one of said plurality of read-only caches is configured to provide read access to said different one of said plurality of functional units responsive to a load memory operation specifying said data.