1. An apparatus, comprising: a first switch core having a multi-stage switch fabric, the first switch core configured to be logically partitioned into a first virtual switch core and a second virtual switch core, the first virtual switch core and the second virtual switch core being logical partitions of the first switch core and not a second switch core; and a processor remote from and operatively coupled to the first switch core, the processor, when operative, assigning a first plurality of peripheral processing devices coupled to the first virtual switch core of the multi-stage switch fabric, to a first virtual application cluster (VAC) of the first virtual switch core, the first VAC of the first virtual switch core being controlled by a first administration entity and defining a first resource of a first resource type that includes a first set of physical resources of the first switch core that are interconnected; the processor, when operative, assigning a second plurality of peripheral processing devices coupled to the first virtual switch core of the multi-stage switch fabric, to a second VAC of the first virtual switch core being controlled by a second administration entity different from the first administration entity, the second VAC associated with the first virtual switch core and defining a resource of a second resource type that includes a second set of physical resources of the first virtual switch core that are different from the first set of physical resources, the second plurality of peripheral processing devices including a subset of the first plurality of peripheral processing devices coupled to the first virtual switch core; the processor, when operative, assigning a third plurality of peripheral processing devices coupled to the second virtual switch core of the multi-stage switch fabric, to a VAC of the second virtual switch core, the VAC of the second virtual switch core defining a second resource of the first resource type that includes a set of physical resources of the second virtual switch core that are interconnected; the second VAC is associated with the first virtual switch core at a first time; the second VAC is associated with the second virtual switch core at a second time different from the first time; and the second plurality of peripheral processing devices is de-allocated from the first virtual switch core at the second time as a result of the second VAC being associated with the second virtual switch core.