1. A processor comprising: a memory; one or more functional units coupled to the memory; and a page miss handler interruption module coupled to the memory and the one or more functional units and to: identify a first operation associated with a request for a page miss handler; identify a second operation associated with a current execution of the page miss handler; determine an age of the first operation and an age of the second operation; identify a state of the page miss handler that is associated with an amount of time for the page miss handler to complete a translation of an address of the second operation; and interrupt the page miss handler based on the ages of the first and second operations and the state of the page miss handler by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.