1. A method of data processing in a multiprocessor data processing system including multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies, the method comprising: in response to receipt of a load-and-reserve request from a first processor core, a first cache memory in a first vertical cache hierarchy supporting the first processor core issuing on the system interconnect an interconnect memory access request for a target cache line of the load-and-reserve request; responsive to the interconnect memory access request and prior to receiving a systemwide coherence response for the interconnect memory access request, the first cache memory receiving from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the interconnect memory access request; and in response to receiving a store-conditional request from the first processor core and the early indication of the systemwide coherence response, and prior to receiving the systemwide coherence response, the first cache memory initiating servicing of the store-conditional request to update the target cache line in the first cache memory.