1. A processing core, comprising: execution unit logic circuitry having: a) a first register to store a first vector input operand V2[ ]; b) a second register to a store a second vector input operand V3[ ]; c) a third register to store a packed data structure containing scalar input operands a, b, c d) a multiplier to perform the operation (a*V2[ ])+(b*V3[ ])+c