1. A register allocation unit, comprising: a value cache having a hit/miss output and a register ID output, comprising: an input for a new value signal, a plurality of cache entries, each to store values in association with a physical register ID, value portions of the cache entries including content addressable logic, and a controller, responsive to a match identified by the content addressable logic, to generate a HIT signal on the hit/miss output; and a free list having a register ID output, and a selector coupled to the register ID outputs of the value cache and the free list and having a control input coupled to the hit/miss output, and a register file having an addressing input coupled to the selector output and comprising a plurality of registers, each register comprising a first portion to store data and a second portion to store a counter.