1. A system having memory addressing, comprising: an address permutation control register having a first bit field; control circuitry for receiving a non-permutated address and for receiving the first bit field from said address permutation control register, said control circuitry permutating the non-permutated address under direction of the first bit field to generate a permutated address; and memory array for receiving the permutated address from said control circuitry and for using the permutated address to access said memory array.