1. A digital encoder comprising: a master processing means that encodes a multibit digital input signal into prescribed parallel codes, and a plurality of slave processing means, each of which has 3 or more output nodes, encodes the codes output in parallel from said master processing means into parallel codes corresponding to the configuration of said 3 or more output nodes and with the same weighting for all of the codes on the basis of a prescribed dynamic element matching algorithm, and outputs said parallel codes in parallel from 3 or more output nodes.