1. A Programmable Logic Device (PLD) having an arithmetic circuit comprising: a product generator having: a multiplier port receiving a first operand; a multiplicand port receiving a second operand; a product port providing a product of the first and second operands; a product-generator bypass port; multiplexing circuitry having: a first multiplexer input port connected to the product port and receiving the product; a second multiplexer input port connected to the bypass port; and a multiplexer output port; and an adder having a first addend port connected to the multiplexer output port, a second addend port, and a sum port.