1. A microprocessor architecture, comprising: a trusted instruction set execution path; a secure loader that evaluates security information associated with an extension as part of a loading process, the secure loader configures the reconfigurable execution path based on the security and management information, if the security information is evaluated as safe; a reconfigurable execution path corresponding to the extension, if the security information evaluated as safe by the secure loader; a mechanism that determines when a fetched instruction is to be handled by the reconfigurable execution path; and means for dynamically unloading the extension based upon a configuration change.