1. A digital signal processor dedicated to digital signal processing, comprising a memory portion, a control portion, an arithmetic operation portion and a data bus serving as a data transmission line among said memory portion, said control portion and said arithmetic operation portion, said memory portion comprising data memories for storing data to be multiplied, said control portion comprising: a program memory for storing data, reading means for reading out successively the program data stored in said program memory, and output means for providing various control signals based on said program data read out from said program memory, said arithmetic operation portion comprising: a plurality of multipliers connected directly with said data memories for multiplying data provided from said data memories, an arithmetic and logic unit including a plurality of arithmetic and logic circuits, said arithmetic and logic unit connected directly with said plurlaity of multipliers for applying determined arithmetic and logic operation to outputs of said multipliers, and an accumulator for storing temporarily an output of said arithmetic and logic unit so that said output is supplied to said data bus.