1. A system for accessing a sequence of instructions from an instruction set stored in a control store that includes a plurality of memory elements, with the sequence accessed over a series of clock cycles, with the series divided into even and odd clock cycles, with each instruction accessed during a clock cycle and including a control field, with the clock cycle of shorter duration than the access time of the memory elements comprising the control store, and with the system for executing, without delay, a branch instruction that includes a target address, said system comprisng: first and second control store memory elements, each characterized by a given access time and each storing a complete instructuion set including branch and non-branch instructions; a program counter for providing a first sequence of instruction addresses; means for providing the target address of a branch instruction accessed from the control store; address storage means, having an input port and an output port, for storing an instruction address for one clock cycle; a multiplexer, having a control port adapted to receive the control field of each accessed instruction, a first input port adapted to receive said first sequence of addresses, a second input port adapted to receive the target address of an accessed branch instruction, and an output port coupled to the input port of said address storage means, with said multiplexer for transferring the target address of a given branch instruction, accessed from the control store, to said address storage means when the control field of said given branch instruction is received at the control port and for transferring the address received at the first input port to said address storage means when the control field of a non-branch instruction is received at the control port; and means, coupled to the output port of a said address storage means, for transferring the address stored in said address storage means to said first memory element during even clock cycles and to said second memory element during odd clock cycles regardless of whether the instruction accessed from the control store is a branch instruction or a non-branch instruction thereby providing for unrestricted branch operations.