1. A design structure embodied in a machine readable medium, the design structure comprising an integrated event monitor for a system-on-a-chip (SOC), comprising: a plurality of functional cores each comprising one of a plurality of functional debug logic elements each of which is specifically dedicated to a function of a corresponding one of said cores, wherein each of said functional debug logic elements is adapted to generate a table of function-specific system events; an interconnect structure connected to said cores, wherein said interconnect structure is adapted to link said functional debug logic elements; and a controller connected to said cores, wherein said controller is adapted to capture said system events in a chronological sequence from each of said functional debug logic elements.