1. A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor, the method comprising: obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles, the graph comprising at least one data path to be implemented in hardware as part of said stream processor and comprising at least one input, at least one output and a plurality of parallel branches configured to enable data values to be streamed therethrough from the at least one input to the at least one output as a function of increasing clock cycle; performing, on a computing device, partitioning of said at least one data path to divide said at least one data path into a plurality of discrete regions; assigning, on the computing device, discrete control logic elements to each of said regions of said data path; and utilizing, on the computing device, said graph and control logic assigned during said high level synthesis steps to define a hardware design for implementation in hardware as said pipelined parallel stream processor.