1. In a data processor which executes predetermined sequences of instructions comprising programs stored in a memory, each instruction consisting of at least one (1) instruction unit but no more than m instruction units, where m is an integer greater than one (1), the data processor comprising: an n-stage instruction pipeline for storing in each stage one instruction unit, where n is an integer greater than one (1); instruction execution means, coupled to the instruction pipeline and responsive to the one of said instructions stored in the instruction pipeline beginning at an output end thereof, the instruction execution means executing said one of said instructions and providing an instruction prefetch signal during the execution thereof; instruction prefetch means, coupled to the instruction execution means and responsive to the instruction prefetch signal, for fetching each instruction unit of the next instruction in said predetermined sequence of instructions from said memory; and instruction pipeline control means, coupled to the instruction prefetch means and to the instruction pipeline, for storing each instruction unit fetched by the instruction prefetch means into an input stage of the instruction pipeline after advancing the instruction unit stored in each stage of the instruction pipeline into the next higher stage thereof, until the first instruction unit of said next instruction is stored in the output stage of the instruction pipeline; a prefetch validation circuit comprising: n serially-connected validation latches, each corresponding to a respective stage of the instruction pipeline and serially advancing in synchronism therewith, for storing a validation bit indicative of the invalidity of the instruction unit stored in the corresponding stage of the instruction pipeline; prefetch error detecting means, coupled to the instruction prefetch means and to the validation latch corresponding to the input stage the instruction pipeline, for detecting errors occurring during the fetch of each instruction unit which indicate the invalidity of that instruction unit, and storing the validity bit as an indication of said detected error in the validation latch corresponding to the input stage of the instruction pipeline into which said invalid instruction unit is stored; and instruction validation means, coupled to the instruction pipeline and to the validation latches, for generating an invalid instruction signal if the validation bit stored in the validation latch corresponding to any of the instruction units comprising said next instruction, indicates that the instruction unit stored in the corresponding stage of the instruction pipeline is invalid.