1. An apparatus comprising: a processing core in a multi-processing core system, wherein the processing core is configured to execute a sequence of instructions as an atomic memory transaction, wherein the processing core is configured to issue each instruction in the sequence to an execution pipeline, wherein the execution pipeline is configured to validate each instruction of the sequence during a validate stage of the pipeline that is prior to an execute stage of the pipeline in which instruction results are computed; wherein the validate stage is configured to determine whether each instruction meets a set of one or more atomicity criteria including that executing the instruction does not require accessing shared memory.