1. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising: receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, the target architecture having a limited number of hardware resources available in a class of hardware resources; determining assignment information indicative of how operator instances in the RTL description are to be implemented using the hardware resources in the class of hardware resources; and displaying to a user one or more of a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been assigned without using a user-selected implementation constraint, or a total number of hardware resources in the class that are remaining after accounting for current assignments, wherein the displaying is performed prior to a gate-level netlist being generated according to the assignment information.