1. A memory array layer for use in a 3D RRAM comprising, on a silicon substrate having peripheral circuitry thereon: a first layer of silicon oxide, deposited and planarized; a bottom electrode formed of a material taken from the group of materials consisting of Pt, PtRhO x , PtIrO x and TiN/Pt; a second oxide layer having a thickness of at least 1.5× that of the thickness of the bottom electrode, deposited and plainarized to a level where at the bottom electrode is exposed; a layer of memory resistor material; a layer of Si 3 N 4 ; a third oxide layer having a thickness of about 1.5× of that of the memory resistor material; CMPd to expose the memory resistor surface; a top electrode formed of a material taken from the group of materials consisting of Pt, PtRhO x , PtIrO x and TiN/Pt; and a covering oxide layer.