1. A processor programmable PLD device comprising: a Non-Volatile memory; a JTAG interface in communication with the Non-Volatile memory and connected to an external JTAG bus; at least one I/O register connected with the JTAG interface; and a interface logic block connection connected to a bus arranged for receiving data from an external processor and the at least one I/O register connected with the JTAG interface, wherein said interface logic block connection includes logic for translating data on the bus into a data format for the I/O register.