1. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising: traversing the chip to identify a plurality of components with in a chip circuit of the chip, each of the plurality of components including a plurality of nodes; defining a waveform graph for the plurality of nodes; assigning a level for groups of one or more nodes from the plurality of nodes; processing all of the nodes in one level using two or more threads before processing all of the nodes in a next level; and performing a timing check, the timing check determining an acceptable design of the chip.