1. A computer system comprising at least two clustered processing cores for processing VLIW operations, said each clustered processing core comprising a partitioned register file unit, an instruction pre-fetch decoder and a hardware pre-fetch unit in which said instruction pre-fetch decoder comprises means for identifying remote registers required for executing an Nth VLIW and means for controlling said hardware pre-fetch unit to pre-fetch said remote registers from both local register files of remote processing cores and from bypass paths in said remote processing cores.