1. A built-in self-test circuit within an integrated circuit, comprising: a plurality of scan chains for receiving test patterns; a pseudo random pattern generator coupled to the scan chains to provide test patterns of predetermined weights; and weight select logic, including a decompressor, coupled between the scan chains and the pseudo random pattern generator to control weightings of the test patterns that are loaded into the scan chains; the weight select logic further including at least one shift register within the integrated circuit, the decompressor including a ring generator with the at least one shift register having an output that is coupled as an input to the ring generator.