1. A method comprising: determining whether a default matrix processor-to-processor routing algorithm would deliver an inter-processor message from a first matrix processor to a second matrix processor in a chip comprising a microprocessor matrix of mesh-interconnected matrix processors, wherein the message routed according to the default matrix processor-to-processor routing algorithm would be routed from the first matrix processor by a data switch in each matrix processor along a default message path originating at the first matrix processor; in response to determining whether the default matrix processor-to-processor routing algorithm would deliver the message from the first matrix processor to the second matrix processor, when the default processor-to-processor routing algorithm would not deliver the message from the first matrix processor to the second processor, determining whether designating a third matrix processor as a proxy for the message would cause the message to be delivered to the second matrix processor using the default matrix processor-to-processor routing algorithm from the first matrix processor to the third matrix processor and subsequently from the third matrix processor to the second matrix processor, wherein the third matrix processor is not in the default message path; and in response to determining whether designating the third matrix processor as a proxy for the message would cause the message to be delivered to the second matrix processor, designating the third matrix processor as a proxy for the message when designating the third matrix processor as a proxy for the message would cause the message to be delivered to the second matrix processor; wherein the default matrix processor-to-processor routing algorithm determines a message propagation direction at a current matrix processor according to a comparison between a first quantity and a second quantity, wherein the first quantity is a difference between vertical position indexes of the current matrix processor and a destination matrix processor, and wherein the second quantity is a difference between horizontal position indexes of the current matrix processor and the destination matrix processor.