1. An integrated circuit device, comprising: a first memory block comprising memory cells, configurable to store data for a first pattern of data usage in response to a first operation algorithm; a second memory block comprising memory cells, configurable to store data for a second pattern of data usage in response to a second operation algorithm; and controller circuitry coupled to the first and second memory blocks, and configured to execute the first operation algorithm in response to a first selected cell being in the first memory block and to execute the second operation algorithm in response to a second selected cell being in the second memory block, wherein a word line pass voltage applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage applied in the second operation algorithm.