1. A processor comprising: a hardware event counter to count a number of performance-limiting events resulting from the execution of one or more user-level threads of a user-level multi-threaded program, wherein the one or more user-level threads are to be modified as they are being issued; an operating system (OS) invisible sequencer to execute a first instruction, in response to occurrence of a trigger event, to cause saving of an execution context of a thread whose execution generated the trigger event; and an OS visible sequencer to execute a proxy thread, in response to a second instruction, wherein upon completion of the proxy thread, execution of the thread whose execution generated the trigger event is to be resumed based on the saved execution context.