1. A digital-to-analog converter comprising: an array of at least two digital input streams; a differential output, comprising a positive and a negative output; an input connected to a main clock; an array of inputs having as many inputs as digital input streams, connected to an array of clocks, wherein only one of the said clocks is active (logic high) at any time; an array of differential pairs of PMOS switches having as many pairs as digital input streams, wherein the drains of the first switch from each pair are all connected together and further connected to the said positive output, and the drains of the second switch from each pair are all connected together and further connected to the said negative output; a switch driver being connected to the said digital inputs, to the said main clock, to the said array of clock inputs, and to the gates of the said array of PMOS switches, the switch driver further comprising: an array of positive outputs, each positive output being connected to the gate of the first PMOS switch from the array of PMOS switches; an array of negative outputs, each negative output being connected to the gate of the second PMOS switch from the array of PMOS switches; a first array of MOS circuits, each MOS circuit comprising three series NMOS transistors and a group of parallel PMOS transistors, wherein in each MOS circuit: the first NMOS transistor has the source connected to ground and the gate connected to the said main clock; the second NMOS transistor has the source connected to the drain of the first transistor and the gate connected to one of the digital input streams; the third NMOS transistor has the source connected to the drain of the second transistor and the gate connected to one of the said array of clocks; the PMOS transistors have the sources connected to VDD, the drains connected to the drain of the third NMOS transistor and further connected to an output from the array of positive outputs; and the gate of each PMOS transistor is connected to either a positive or a negative output, with the exception of the specific output to which the drain of the PMOS transistor drain is connected; and a second array of MOS circuits, each MOS circuit comprising three series NMOS transistors and a group of parallel PMOS transistors, wherein in each MOS circuit: the first NMOS transistor has the source connected to ground and the gate connected to the said main clock; the second NMOS transistor has the source connected to the drain of the first transistor and the gate connected to one of the logically inverted digital input streams; the third NMOS transistor has the source connected to the drain of the second transistor and the gate connected to one of the said array of clocks; the PMOS transistors have the sources connected to VDD, the drains connected to the drain of the third NMOS transistor and further connected to an output from the array of negative outputs; and the gate of each PMOS transistor is connected to either a positive or a negative output, with the exception of the specific output to which the drain of the PMOS transistor drain is connected.