1. A command decoder for a memory system having a plurality of operating states at which a respective operation is performed, the command decoder comprising: a command signal latch having command nodes to which command signals are applied, the command signal latch configured to latch logic levels of the command signals; and a command decoder circuit coupled to the command signal latch, the command decoder circuit configured to monitor the operating state of the memory system and further configured to generate internal control signals to perform an operation selected from a first set of operations according to the latched logic levels of the command signals when the memory system is in a first operating state and configured to generate internal control signals to perform an operation selected from a second set of operations according to the latched logic levels of the command signals when the memory system is in a second operating state, the second set of operations having at least one different operation from the first set of operations.