1. A cache comprising: an associative memory having a plurality of entries, each of said plurality of entries configured to store a cache line of data, said plurality of entries arranged in a plurality of ways; and a replacement circuit configured to select an entry of said associative memory for eviction responsive to a cache miss by a memory transaction, and wherein said replacement circuit is configured, responsive to a first transaction specifying an explicit update of said replacement circuit to select a first way of said plurality of ways, to establish a first state corresponding to a selection of said first way.