1. A method of implementing a wide multiplexer in an FPGA having a plurality of carry/cascade chains, each chain being driven by a plurality of lookup tables, the method comprising the steps of: recognizing an instantiation of a multiplexer having input signals and select signals; for each input signal to the multiplexer, forming from that input signal and all the select signals a decoded input signal on one of the FPGA carry/cascade chains; and applying the decoded input signals to a plurality of LUTs having their outputs applied to adjacent positions on a carry/cascade chain, each LUT programmed to implement a second function, the second function being one of a NOR function and an AND function.