1. A method implemented with a processor for managing hierarchical layout data, comprising: using at least the processor to performing a process, the process comprising: configuring a set of hierarchical grids for the hierarchical layout of an electronic design, wherein the set of hierarchical grids comprises of grid-cells having a larger grid size at a higher hierarchical level of a hierarchy than grid-cells at a lower hierarchical level to represent layout objects; and assigning a layout object canonically to a specific hierarchical grid cell level based at least in part upon a size of the layout object and a grid size of the specific hierarchical grid cell level in the electronic design by using a canonical assignment.