1. An integrated circuit comprising: a memory including non-volatile memory cells disposed in-multiple layers of memory; and a disturb controller configured to regulate memory disturbs among two or more vertically stacked layers of the multiple layers of memory, the disturb controller configured to generate a plurality of composite signals to be applied to at least one cross-point memory array disposed in the multiple layers of memory, wherein the plurality of composite signals comprises a composite write signal, wherein the composite write signal comprises at least two signals that include shaped portions.