1. An apparatus comprising: a register map to store up to M×N values to map M registers for N threads, a set of N values being associated with each of the M registers; a plurality of M sets of state bits, each set of state bits being associated with one of said M registers and to indicate which of N values are valid for each of said M registers for each thread and whether ones of said N sets of values have been written to during execution of a dynamic execution thread.