1. A high availability computer system comprising: a plurality of general data processors connected respectively as Master/Checker pair units having two processors to each said data processor unit, said processors being connected to one-another within the processor unit by a local bus and connected to a bus extension unit; the bus extension unit being connected further to a system bus, thereby providing data communication to all of the computer system; a parameter controller communicating through at least one COM-line to each bus extension unit to control identification and parameterization during a system initialization; each bus extension unit including an INIT counter maintained by said parameter controller during each initializaton; each of said processors thus connected to its bus extension unit reading its respective INIT counter and deciding whether to continue data processing or to stop; each said processor receiving either a Master or a Checker identification during initialization and storing said identification; identification and parameterization being always assigned the same way such that a logic 0 or a logic 1 of said processor always starts the same process; and each INIT counter being incremented after each warm start such that on each subsequent warm said processor performing the initialization is different from the previous processor performing the initialization.