1. A single chip digital signal processor (DSP), comprising: a multiplicity of memory mapped resources, said memory mapped resources including: memory locations in a data memory for storing DSP data, memory locations in a program memory for storing DSP instructions, and a plurality of on-chip peripheral interfaces for interfacing the DSP with peripheral devices external to said DSP; said plurality of on-chip peripheral interfaces generating data read and data write interrupt signals when said peripheral devices are ready to transfer data to and from said memory mapped resources; a DSP core coupled to said data memory and program memory for executing said stored DSP instructions; a direct memory access (DMA) controller coupled to said data memory, program memory, and on-chip peripheral interfaces for performing local data transfers between specified ones of said memory mapped resources; a plurality of data and address bus pairs, each data and address bus pair coupled to a predefined subset of said data memory, program memory, on-chip peripheral interfaces, DSP core and DMA controller; wherein a first of said data and address bus pairs is dedicated to data transfers performed by said DMA controller, and a second of said data and address bus pairs is dedicated to data transfers controlled by said DSP core for transferring data to and from said DSP core; said DMA controller including a data transfer register, a first set of transfer control registers for local data transfers that are initiated by said DSP core and performed by said DMA controller, and a second set of transfer control registers for data transfers that are initiated by interrupts from said on-chip peripheral interfaces and performed by said DMA controller; said first set of registers including a first address source register, a first address destination register and a first repeat counter register to specify source and destination addresses for said local data transfer and to specify a quantity of data to be transferred by said local data transfer; said second set of registers including a second address source register, a second address destination register and a second repeat counter register; and said DMA controller including an DMA interrupt controller for interrupting a local data transfer being performed using said first set of registers when any of said data read and data write interrupt signals is received from any of said on-chip peripheral interfaces, for performing a distinct data transfer corresponding to said received interrupt signal using said second set of registers to specify source and destination addresses for said distinct data transfer and to specify a quantity of data to be transferred by said distinct data transfer, and for resuming said local data transfer when said distinct data transfer is completed.