1. A method for compiling a hardware description language circuit description, tangibly embodied on computer readable media as instructions adapted to control a processor, comprising the steps of: finding a state domain within a circuit specified in a hardware description language description; tracing combinational logic operations which are incidental to the state domain; identifying combinational logic operations which are shared by a plurality of state domains; generating a plurality of binary files adapted to program an FPGA to perform combinational logic operations; and compiling means for asynchronous completion handshaking into a plurality of binary files adapted to program an FPGA to perform combinational logic operations wherein the means for asynchronous completion handshaking is not specified in said hardware description language circuit description.