1. A cell circuit for data readout in a memory block of a multiport memory array, the memory block having a plurality of address inputs and storing a plurality of write data signals, the cell circuit comprising: a first decoder receiving as first decoder inputs a subset of the address inputs and outputting a plurality of select signals; a multiplexer coupled to the first decoder for receiving the select signals and selecting one of the write data signals based on the select signals; and a plurality of read wordlines coupled to the first decoder for carrying the subset of the address inputs to the first decoder.