1. Method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement (e.g. FPGAs, DPGAs, DFPs or the like), characterized in that 1.1 a plurality of cells and arithmetic units (CEL) are combined to form a plurality of groups, a cache unit (CT) being assigned to each subgroup; 1.2 the cache units of the individual subgroups are connected, via a tree structure, to a higher level cache unit (ROOT CT) having access to the command memory memory &lsqb;sic&rsqb; (ECR) in which the commands are stored; 1.3 commands are combined to form command sequences (KR), which are always cached as a whole and transmitted between the caches; 1.4 each cache unit on the lowermost or middle level of the tree requests the required commands from the respectively assigned higher level cache unit; 1.5 a higher level cache unit sends a requested command sequence to the lower level unit if it holds the command sequences in its local memory; 1.6 a higher level cache unit requests a requested command sequence from the respective higher level cache unit if it does not hold the command sequences in its local memory;