1. A circuit for calculating a Fast Fourier Transform (FFT) of a plurality of data values comprising: a memory device for storing data values and coefficient values; a first circuit configured to multiply data values and coefficient values retrieved from the memory device to provide a first result; a second circuit configured to receive and add another value to said first result to provide a second result, wherein the second result is stored in the memory device; a detector having an input from the memory device for monitoring the processing of data values; a state machine in communication with the detector, wherein the input from the detector is used to increment the state machine and wherein the state machine is configured to control the processing of coefficient values through the first circuit; and means for performing the 2's compliment of the coefficient values in communication with the state machine.