1. A processor-implemented performance test steady-state determination method, comprising: executing, via one or more hardware processors, a performance test of a web-based application; calculating, via the one or more hardware processors, a plurality of output metrics based on the performance test; determining, via the one or more hardware processors, whether each of the output metrics has achieved steady state within micro, macro, and global initial time windows; and providing an overall steadiness indication based on the determination of whether each of the output metrics has achieved steady state within the micro, macro, and global time windows.