1. A method for fabricating ICs from a semiconductor wafer, the method comprising: performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion; removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance of a second process.