1. An electronic memory apparatus, comprising: a memory cell in electronic communication with a digit line, the memory cell configured to store a plurality of logic states; a current generator coupled to the digit line, the current generator configured to charge the digit line to a voltage level; a sense component coupled to a node of the current generator different from the digit line, the sense component configured to detect a voltage present on the node, wherein the voltage is based at least in part on the voltage level of the digit line; a latch coupled to an output of the sense component, the latch configured to output a value of a time-varying signal based at least in part on receiving a signal from the sense component; and a controller coupled to the memory cell, the controller operable to identify a logic state of the memory cell based at least in part on a duration of time to charge the digit line to the voltage level, wherein the controller is coupled to the latch, the controller operable to identify the logic state of the memory cell based at least in part on the value of the time-varying signal received from the latch.