1. A processor comprising: a first branch predictor configured to: provide an indication whether a given branch instruction has hysteresis; and generate first branch prediction data for the given branch instruction; a second branch predictor configured to generate second branch prediction data for the given branch instruction; and control logic configured to: generate an output based at least in part on at least one of the first and the second prediction data and the indication of hysteresis, responsive to determining there is a mismatch between the first prediction data and the second prediction data; wherein the output is used to determine whether to train the first branch predictor.