1. A processor comprising: an execution core configured to execute an instruction having a plurality of operands that specify a first one or more addresses corresponding to a first vector memory operation and a second one or more addresses corresponding to a second vector memory operation, wherein at least one of the first one or more addresses and the second one or more addresses are based on a scalar address in the plurality of operands and further based on a vector attribute of the corresponding first vector memory operation or second vector memory operation, wherein the execution unit is configured to detect whether or not a dependency exists between the first vector memory operation and the second memory operation, and wherein the execution core is configured to generate a dependency vector that indicates, for each first element of the first vector memory operation that depends on a second element of the second memory operation, which second element that the first element depends on.