1. A performance monitor included in a processor, said performance monitor comprising: a plurality of performance event signals received by said performance monitor, said plurality of performance event signals indicating the current full event state of said processor; a plurality of counters for counting only selected ones of said performance event signals; an event register that intercepts said plurality of performance event signals prior to selected ones of said performance event signals being counted; and current values of said plurality of performance event signals being stored together as a single unit in said event register, said unit being a full set of available performance event signals that indicate the current full event state of said processor.