1. A controller apparatus comprising: a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter; a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error; and a control circuit for adjusting the adjustable operating parameter in response to a performance criterion, including adjusting a processor subsystem voltage in response to the performance criterion corresponding to a minimization of processor subsystem time to execute the sequence of instructions.