1. An apparatus for detecting bugs in a logic-based processing device during post-silicon validation, said apparatus comprising: a test bench having a processor for converting an original test program to a modified test program; and a Proactive Load and Check (PLC) hardware checker including a controller for initiating a PLC operation in response to a determination that a predetermined set of criteria is met; an address generator for generating an address of an original variable in an uncore component with which said PLC hardware checker is associated, wherein said uncore component is located within said logic-based processing device to be tested; a data register for storing a value at said original variable address; and a comparator for comparing said value stored within said data register to a value at a corresponding shadow variable address within said modified test program, and for indicating an existence of a bug within said logic-based processing device to be tested when said value stored within said data register does not match said value from said corresponding shadow variable address within said modified test program.