1. A processor core, comprising: a plurality of dispatch queues for receiving instructions of a corresponding plurality of instruction streams, wherein individual ones of the plurality of dispatch queues store the instructions of the corresponding one of the plurality of instruction streams, wherein individual ones of the plurality of dispatch queues have outputs for dispatching the instructions of the corresponding instruction streams; a plurality of parallel instruction execution slices for executing the plurality of instruction streams in parallel, wherein individual ones of the plurality of parallel instruction execution slices have multiple internal issue queues coupled to multiple internal pipelines corresponding to the multiple internal issue queues that receive instructions of a selected instruction stream for the parallel instruction execution slice in which the individual issue queues and multiple internal pipelines are included, whereby the multiple internal pipelines support out-of-order execution of instructions of an instruction stream selected for execution by the parallel instruction execution slice in parallel as the instructions are received by the multiple internal pipelines from the corresponding issue queue; and a dispatch routing network having multiple inputs coupled to corresponding ones of the outputs of the dispatch queues for routing the output of the dispatch queues to the instruction execution slices so that there is not a fixed relationship between the instruction streams and the instruction execution slices and such that the routing network dynamically varies the relationship between the dispatch queues and the plurality of parallel instruction execution slices according to execution requirements for the plurality of instruction streams and resource availability in the plurality of parallel instruction execution slices to select from among the plurality of instruction streams one or more selected instruction streams selected for execution by the individual ones of the parallel instruction execution slices, by selecting from which of the instructions streams instructions are sent to the individual ones of the plurality of parallel execution slices, wherein the internal issue queues of the plurality of parallel instruction execution slices receive dispatched instructions of the selected instruction stream selected for execution by the parallel instruction execution slice in which they are included from the dispatch routing network.