1. An apparatus, comprising: a host memory controller to: send a mode register command to a memory module, over a bus, comprising one of a first memory module supporting a first data rate memory protocol and a second memory module supporting a second data rate memory protocol, during initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates a mode register comprising one of the mode registers and includes data for the mode register, wherein the mode register command is sent on a first number of at least one clock cycle, and wherein after a training of the memory module, commands used to communicate with the memory module are sent on a second number of clock cycles, wherein the first number of at least one clock cycle is less than the second number of clock cycles, wherein when sending to the first memory module, the mode register command causes writing of the data to the mode register in a memory chip of the first memory module, and wherein when sending to the second memory module, the mode register command causes writing of the data to the mode register in a memory module controller of the second memory module.