1. A bit enhancement circuit for a page-table-look-aside-buffer (TLB) in a virtual memory computing system comprising: an input buffer register for receiving an absolute address from an instruction processor, said absolute address comprising a page compare address, a page set address and a page offset address, an address input pointer coupled to said page address and to said TLB for accessing a memory address in said TLB, memory storage means in said TLB containing stored memory addresses to be accessed by said input pointer, dynamic bit storage means in said memory storage means at each said input pointer location, said dynamic bit storage means in said TLB comprising means for storing validity, degrade and age bit information capable of inhibiting access to a page address stored at the memory address to be accessed, logic circuit means coupled to said TLB for generating and storing said validity, degrade and age bit information in said dynamic bit storage means, said logic storage means including means for generating said degrade bit information comprising a parity check input and an error input, and means for comparing said page compare address with the contents of said memory address to be accessed, and selection means coupled to the memory storage means in said TLB at the address to be accessed for reading a translated real page address from said TLB upon a successful comparison of the page compare address and said memory address to be accessed when not inhibited by degrade and validly bit information in said dynamic bit storage means.