1. A memory architecture comprising: a plurality of transistors arranged to form a bit cell, said bit cell comprising a first transistor, a second transistor, a third transistor and a fourth transistor configured to store a bit of data; a fifth transistor having a gate coupled to a Data Bar Port A (DB_PORTA) signal, said fifth transistor having a drain coupled to a drain of said first transistor (Node T) and a Source coupled to an XWRA node also selectively connected to a Word Line for port A Bar/Word Line Bar (WLAB/WLB) signal; and a sixth transistor having a gate coupled to a Data Bar Port B (DB_PORTB) signal, a drain coupled to a drain of said third transistor (Node B) and a source coupled to an XWRB node also selectively connected to a Word Line for port B Bar/Word Line Bar (WLBB/WLB) signal.