1. A cache memory of an affiliated processor core of a multiprocessor data processing system including the affiliated processor core, a plurality of remote processor cores, and an interconnect communicatively coupling the cache memory to receive operations initiated by the plurality of remote processor cores, the cache memory comprising: a data array; a directory of contents of the data array, wherein the directory includes coherence state information; and snoop logic that processes operations snooped from the interconnect by reference to the data array and the directory, wherein the snoop logic, responsive to snooping on the interconnect a first storage-modifying operation of the plurality of remote processor cores that specifies a same target address as that of a first read-type operation of the plurality of remote processor cores that was previously snooped from the interconnect and is then being serviced by the cache memory, determines whether the cache memory is designated by the coherence state information as responsible for servicing operations specifying the target address, and in response to a determination that the coherence state information designates the cache memory as responsible for servicing operations specifying the target address, causes the cache memory to provide a retry response to the first storage-modifying operation and, in response to completion of the cache memory's servicing of the first read-type operation, enter a referee mode, wherein the snoop logic, while in the referee mode, maintains designation of the cache memory by the coherence state information as responsible for servicing operations specifying the target address and temporarily dynamically increases priority of any second storage-modifying operation of the plurality of remote processor cores snooped from the interconnect that specifies the target address in relation to any second read-type operation of the plurality of remote processor cores snooped from the interconnect that specifies the target address.