1. An apparatus comprising: a first register to store an interrupt destination identifier (ID); a second register to store an interrupt vector and a delivery status bit; a third register to store an interrupt command register (ICR) offset; logic to communicate interrupt information from at least a first agent to at least a second agent, wherein the logic includes an interrupt control interface (ICI) to communicate interrupt information to be manipulated by an instruction without accessing memory-mapped input/output (MMIO) regions, and to co-exist with a legacy ICI; said first agent to store a destination ID portion to a first memory location in response to a determination that the delivery status bit indicates availability of the ICR, and to perform the instruction to write the contents of said first and second registers to the ICR offset address of the third register; and said second agent to store the interrupt vector and said delivery status bit deasserted to a second memory location.