1. A computer-implemented method comprising: receiving a test case that includes a bit mask; configuring a plurality of machine state register bits into a first machine state register bit set based upon the bit mask; loading the test case and the first machine state register bit set into a processor, wherein the first machine state register bit set enables the processor to operate in a first processor mode; executing the test case using the processor operating in the first processor mode; after executing the test case, re-configuring the plurality of machine state register bits into a second machine state register bit set based upon the bit mask; re-loading the test case and the second machine state register bit set into the processor, wherein the second machine state register bit set enables the processor to operate in a second processor mode that is different than the first processor mode; and re-executing the test case using the processor operating in the second processor mode.