1. A data processing apparatus comprising: a vector register store configured to store vector operands; vector processing circuitry providing N lanes of parallel processing, and configured to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of said N lanes, said up to N data elements forming a plurality of segments, and performance of the segmented operation comprising performing a separate operation on the data elements of each segment, said separate operation involving interaction between the lanes containing the data elements of the associated segment; and predicate generation circuitry configured to be responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing said segmented operation to maintain a boundary between each of said plurality of segments, in order to prevent interaction between lanes containing data elements from different segments.