1. A memory device, comprising: an external port coupling memory commands, memory addresses, and write data into the memory device, the external port further coupling read data from the memory device; a plurality of internal address buses; a plurality of internal data buses; an address coupling circuit operable to couple memory address signals corresponding to the memory addresses from the external port to a selected one of the internal address buses; a data coupling circuit operable to couple write data signals corresponding to the write data from the external port to a selected one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to the read data from a selected one of the internal data buses to the external port; a plurality of banks of memory cells; a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from a selected one of the internal address buses to the respective bank, the bank coupling circuit further being operable to couple the write data signals from a selected one of the internal data buses to the respective bank and to couple the read data signals from the respective bank to a selected one of the internal data buses; and control circuitry coupled to control inputs of the address coupling circuit, the data coupling circuit, and the bank coupling circuit, the control circuitry being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select the internal address bus to which the address signals are coupled, to apply signals to the data coupling circuit to cause the data coupling circuit to select the internal data bus to which the write data signals are coupled and from which the read data signals are coupled, and to apply signals to the bank coupling circuit to cause the bank coupling circuit to select the internal address bus from which the address signals are coupled and to select the internal data bus to and from which write data and read data are coupled.