1. A method comprising: when one or more logic circuits of a component of a processor are in a state of reduced power consumption in which an internal state of said component is not read: monitoring one or more signals received by said component, the signals affecting said internal state; and predicting based solely on said one or more signals at what future time to increase the power consumption of one or more of said one or more logic circuits in order to read said affected internal state and in order not to diminish functioning of said processor beyond an acceptable level.