1. An apparatus comprising: a decoder to decode three different instructions into three decoded, different instructions; instruction execution circuitry comprising: input vector element routing circuitry to perform the following for each of the three decoded, different instructions: for each of a plurality of output vector element locations of an output mask vector, route into an output vector element location an input vector element from one of a plurality of input vector element locations of an input mask vector that are available to source an output vector element, said output vector element and each of said input vector elements being one of three available bit widths for said three different instructions, and said plurality of input vector element locations corresponding to a contiguous chunk of said input mask vector that is smaller than said input mask vector for at least one instruction of the three different instructions; and masking layer circuitry coupled to said input vector element routing circuitry to mask the output mask vector created by said input vector element routing circuitry, said masking layer circuitry to mask at three different levels of granularity that correspond to said three available bit widths.