1. A digital arithmetic integrated circuit, comprising: an arithmetic data storing memory for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m×n)-bits n-times longer than that m-bits of the unit word length of the first arithmetic data string; arithmetic operand storing registers for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle; and an arithmetic result storing register for storing the arithmetic results outputted by said arithmetic logical unit.