1. A computation cell for a fault-tolerant field programmable gate array (FPGA), comprising: an original function/error detection code storage unit for storing an original function, or storing an error detection code- 1 corresponding to the original function, and for outputting an original function output required to do routing the original function and an error detection code- 1 required to detect an error in the original function when the original function is input; a spare function/error detection code storage unit for storing a spare function or storing an error detection code- 2 corresponding to the spare function, and outputting a spare function output required to do routing the spare function and an error detection code- 2 required to detect an error in the spare function when the spare function is input; a totally self checker comprising: an error detection code generator for performing an operation on the original and spare function outputs and generating an error detection code for original function required to detect an operation of the original function or occurrence of a unidirectional fault and an error detection code for spare function required to detect an operation of the spare function or occurrence of a unidirectional fault; and a fault checker for performing an operation on the error detection code- 1 , the error detection code- 2 , the error detection code for original function, and the error detection code for spare function and generating a faulty signal_original and a faulty signal_spare required to determine occurrence of errors in the original and spare functions, respectively; a function router/permanent error indicator for performing an operation on the original function output, the spare function output, the faulty signal_original, the faulty signal_spare, and a stem function input from a stem cell, and then outputting a function routing signal or a permanent error flag signal; a free router for routing the permanent error flag signal; a free look-up table- 1 including a router for routing a permanent error signal or at least one look-up table for storing the error detection code- 1 corresponding to the original function, depending on the number of bits of the original function; and a free look-up table- 2 including a router for routing a permanent error signal or at least one look-up table for storing the error detection code- 2 corresponding to the spare function, depending on the number of bits of the spare function, wherein, when the original and spare functions are k-bit functions, the original and spare function/error detection code storage units store the original function and the spare function, respectively, and the free look-up table- 1 and free look-up table- 2 pre-store the error detection code- 1 and error detection code- 2 , respectively when the original and spare functions are functions of k−1 or less bits, the free look-up table- 1 and free look-up table- 2 do routing the permanent error signal.