1. A method for fabricating a digital circuit, said method comprising the steps of: generating a tree graph comprising a multiplicity of nodes and respective children, each of said nodes corresponding to a digital function within said digital circuit and each of said children representing an input for one of the digital functions; for each of a multiplicity of said nodes, if the node is an AND gate, determining s.sub.cell =s of node itself plus summation (s of each child-1), if the node is an OR gate, determining s.sub.cell =max (s of each child), and if the node is an Inverter, determining s.sub.cell =s of child plus 1, wherein s=1 for an Inverter, s=n for an n input AND gate, and s=1 for an n input OR gate; and fabricating the circuit based on a physical representation of a plurality of partial subgraphs rooted at respective nodes which have "s.sub.cell " values less than or equal to a specified number, each of said partial subgraphs comprising the respective root node and one or more descendants of said root node.