1. A method for selecting a set of n paths with which to test an integrated circuit chip, the method comprising: organizing the set of n paths into a plurality of sub-sets; receiving a new candidate path; adding the new candidate path to one of the plurality of sub-sets when the new candidate path improves a process coverage metric associated with the one of the plurality of sub-sets; and creating a new sub-set for inclusion in the plurality of sub-sets when the new candidate path does not improve a process coverage metric associated with any of the plurality of sub-sets, where the new sub-set contains the new candidate path, wherein at least one of the organizing, the receiving, and the adding is performed by a processor.