1. A processor comprising: a register file having a first portion corresponding to a first operand size and a first data type and a second portion corresponding to a second operand size and the first data type, wherein registers in the first portion are a first width specified by the first operand size and registers in the second portion are a second width specified by the second operand size, and wherein the first operand size is different from the second operand size, and wherein the first data type defines an interpretation of data in the registers; and a map unit coupled to receive an instruction operation and configured to assign a register in the register file to a result of the instruction operation, wherein the map unit is configured to select the register from the first portion responsive to the instruction operation having the first operand size, and wherein the map unit is configured to select the register from the second portion responsive to the instruction operation having the second operand size.