1. A comparison circuit that compares a first address with a second address, the second address being stored in a load queue and/or store queue of a microprocessor, the comparison circuit comprising: a first comparison unit that compares a first subset of bits of the first address with a corresponding second subset of bits of the second address to produce a first comparison result indicating whether the first subset of bits is equal to the second subset of bits; and a second comparison unit coupled to the first comparison unit to receive the first comparison result, wherein the second comparison unit is enabled and disabled based on the first comparison result, wherein, when the second comparison unit is enabled, the second comparison unit compares a third subset of bits of the first address with a corresponding fourth subset of bits of the second address.