1. A monolithic discrete-time digital convolution circuit, comprising: a pluralith (N) of storage circuits for holding N respective values of a first function; a like plurality (N) of multipliers having first inputs connected to respective ones of said storage circuits and second inputs connected together to receive N successive values of a second function, and providing output signals indicative of the products of the respective values of the first function and the successive values of the second function; a like plurality (N) of shift registers; a like plurality (N) of adders having first inputs connected to receive products from respective ones of said multipliers, outputs connected to respective ones of said shift registers, and second inputs connected to receive accumulated data from adjacent ones of said shift registers, said adders and shift registers being connected together in a chain in which each adder combines a multiplier product with a cumulative sum derived from an adjacent adder in the chain, and the final adder in the chain produces a sucession of N accumulated product summations proportional to the discrete values of the convolution of the first and second functions.