1. In a data processing system comprising a processor and memory, said memory comprising means for storing data in response to store instructions from said processor and delivering data to said processor in response to lead instructions from said processor, a memory processor for preventing a lead instruction that has been moved in a code sequence from returning erroneous results because of a store instruction to the memory location specified in said lead instruction, said memory processor comprising: means for receiving said store and moved load instructions, each said store instruction referencing a store address and including data to be stored at said store address, and each said moved load instruction including a load address, said receiving means including means for detecting said moved load instructions, and for determining a watch window associated with each said moved load instruction; means connected to said receiving means for storing said received moved load instructions during the execution of other said instructions in said code sequence, said storing means further comprising means for defining said watch window associated with each said moved load instruction and a flag corresponding to each said received moved load instruction stored in said storing means, said flag having one of two states, said flag being set to the first of said two states when moved load instruction is received; means connected to said receiving means and said storing means for comparing said store address of each received store instruction with the load address of each said moved load instruction stored in said storing means and for setting said flag corresponding to said moved load instruction to the second of said two states if said load address matches said store address; and control means connected to said storing means for determining if the watch window for one of said stored moved load instructions has terminated, said control means further comprising data delivery means for causing the data included in the last said store instruction having a store address matching said load address of said moved load instruction to be outputted to said processing unit if said flag associated with said moved load instruction has been set to said second state.