1. A computer processor comprising: a Multiplex device (MUX) comprised of two inputs and one output, wherein said first input is coupled to a branch fetch address or hash thereof, said second input is connected to a branch computation register read port or hash thereof, and said MUX output or hash thereof is coupled to a branch target prediction table; a branch target register; a logic in said computer processor, wherein said logic is capable of autonomously determining when a preload instruction is being executed, and autonomously causing said MUX to select said branch computation register read port and write data from said branch computation register read port or hash thereof and said branch fetch address or hash thereof into an index of said branch target prediction table indicated by said MUX output; and a processor core coupled to said branch target prediction table, wherein said processor core is capable of using said branch fetch address of a branch to index said branch target prediction table and begin fetching at a predicted target address stored in said branch target prediction table, if a predicted branch is taken.