1. In a reduction processing system having storage means for receiving two-cell nodes representing binary directed graphs employing a variable-free applicative language code, one of such cells in some of each nodes containing a storage address of another node, another of said cells in some of each nodes containing a code representing a functional argument and another of said cells in some of each nodes containing a variable-free operator code specifying a function substitution, a graph manager comprising: a plurality of registers coupled to said storage means for receiving a plurality of said nodes for reduction by a function substitution; interconnection means coupling said registers together for parallel transfer of fields of information from some of said registers to other of said registers; condition testing means coupled to various fields of said registers containing said nodes to detect what function substitution is to be performed and to generate a displacement address therefrom; and control store means coupled to said condition testing means for receiving said displacement address to retrieve a set of control signals to activate transfer between said registers to accomplish said function substitution.