1. A processor comprising: a plurality of branch predictors, wherein each branch predictor is adapted to provide a prediction and an override signal; and a branch prediction control circuit adapted to generate a branch prediction based on the prediction and the override signal from each predictor, wherein the override signal of a particular predictor results in one of (i) the prediction of the particular predictor being accepted by the processor regardless of the predictions of the other predictors and (ii) the prediction of the particular predictor not being accepted by the processor regardless of the prediction of the particular predictor.