1. A method of manufacturing an integrated circuit, comprising: providing a data file that includes a scaling enhanced circuit layout; and designing a first standard cell layout using a plurality of design rules and the data file, wherein the scaling enhanced circuit layout includes a design rule violation layer that violates at least one of the plurality of design rules, and the designing the first standard cell layout includes: implementing a first layout region of the first standard cell layout to correspond to the data file; and designing a second layout region of the first standard cell layout using the plurality of design rules.