1. A specialized multiplier block for use in a programmable device, said specialized multiplier block comprising: a plurality of multipliers having multiplier inputs; at least one input chain of shift registers, each shift register in said chain of shift registers being of depth n, at least one input of each of said multipliers being connected to said input chain of shift registers; a plurality of adders; and programmable connections connecting outputs of said multipliers to inputs of said adders whereby said specialized multiplier block is configurable as an n-channel Direct Form II finite impulse response filter.