1. A method for providing secure external memory that stores instructions for a processor, comprising the steps of: receiving a plurality of encrypted instructions into a buffer of the processor from the external memory, said plurality of encrypted instructions comprise a plurality of consecutive encrypted instructions, and said step of receiving said plurality of encrypted instructions into a buffer of the processor from the external memory comprises the step of receiving the plurality of consecutive encrypted instructions from a bus having a width equivalent to that of each consecutive encrypted instruction of the plurality of consecutive encrypted instructions; decrypting the plurality of encrypted instructions substantially simultaneously using a selected decryption algorithm to produce a plurality of decrypted instructions; and forwarding at least one decrypted instruction of the plurality of decrypted instructions to a processing area of the processor.