1. A circuit implemented method of handling exceptions in a pipelined out-of-order microprocessor, said pipelined out-of-order microprocessor comprising an instruction fetch section, a decoder section, a register renaming section, an out-of-order section, and an execution section, said method comprising the steps of: fetching consecutive instructions using said instruction fetch section; decoding said instructions within said decoder section to generate decoded instructions; placing said decoded instructions in a reorder buffer of said out-of-order section using said register renaming section; executing said instructions in said execution section and storing executed instruction results back into said reorder buffer; retiring said executed instruction results in an original program order, said step of retiring comprising the substeps of testing an exception field associated with executed instruction results stored said reorder buffer; and handling an exception if said exception field indicates an exception occurred during instruction execution.