1. A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, wherein the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables, the method comprising the steps of: (a) forming a set of linearly independent electrical test parameters based on a subset of the set of electrical test variables; (b) mapping the set of process factors to the linearly independent electrical test parameters; (c) forming a plurality of figure-of-merit (FOM) performance models based on the process factors; and (d) combining the FOM models with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.