1. A method for fabricating electrical contacts for dynamic random access memory (DRAM) devices on a semiconductor substrate comprising the steps of: providing said semiconductor substrate having device areas for memory cells surrounded and electrically isolated from each other by field oxide areas; depositing a first polysilicon layer on said substrate; depositing a first hard mask layer on said first polysilicon layer; patterning said first hard mask layer and said first polysilicon layer to form field effect transistor (FET) gate electrodes over said device areas and to form word lines over said field oxide areas, where said FETs include source/drain areas and sidewall spacers on said gate electrodes; depositing a first insulating layer on said substrate and over said FETs, and planarizing said first insulating layer; etching capacitor node contact openings in said first insulating layer to said source/drain areas; depositing a second polysilicon layer and polishing back to form polysilicon plugs in said capacitor node contact openings; depositing a third polysilicon layer and patterning to form capacitor bottom electrodes over and contacting said polysilicon plugs; forming an interelectrode dielectric layer on said bottom electrodes; depositing a fourth polysilicon layer, a second insulating layer, and a second hard-mask layer; patterning said second hard-mask layer, said second insulating layer, and said fourth polysilicon layer to form capacitor top electrodes, while exposing said first insulating layer over said word lines on said field oxide areas; using a first photoresist mask that is sufficiently thin to provide high resolution patterns for etching first contact openings, and using anisotropic plasma etching to etch said first contact openings in said first insulating layer to said first hard mask, while said second hard-mask layer protects said capacitors from etching; etching said first hard-mask layer in said first contact openings to said word lines, while said second hard-mask layer is etched selectively to said second insulating layer; removing remaining portions of said first photoresist mask; forming first conducting plugs in said first contact openings; depositing and planarizing a third insulating layer over said capacitors; using a second photoresist mask and anisotropic plasma etching to etch second contact openings in said third insulating layer over and to said first conducting plugs; forming second conducting plugs in said second contact openings to complete said electrical contacts for said DRAMs.