1. A reconfigurable semiconductor device, comprising: a plurality of logic units connected to each other by address lines or data lines, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a first address decoder that decodes an address inputted from some of the plurality of address lines; a second address decoder that decodes an address inputted from the other of the plurality of address lines; a first memory cell unit having a plurality of memory cells, the first memory cell receiving the address decoded by the first address decoder and selecting, among the plurality of memory cells, a predetermined number of memory cells in accordance with the decoded address; and a second memory cell unit having a plurality of memory cells, the first memory cell receiving the address decoded by the second address decoder and selecting, among the plurality of memory cells, a predetermined number of memory cells in accordance with the decoded address.