1. An operation processing apparatus comprising: first register means for holding a first operand having a sign bit; second register means for holding a second operand having a sign bit, the length of said second operand being smaller than that of the first operand; expanding means connected to the second register means to produce an expanded second operand having additional bits based on the sign bit of said second operand in the upper bits thereof and having said second operand in the lower bits thereof so that the expanded second operand has the same length as that of said first operand, said expanding means including first gate means for outputting the second operand in said second register as the lower bits of said expanded second operand, and second gate means for outputting additional bits based on the sign bit of said second operand to form the upper bits of said expanded second operand, said second gate means including a plurality of gates each corresponding to a respective one of the upper bits of said expanded second operand, said sign bit being applied in common to an input of each of said plurality of gates; and arithmetic means for executing an arithmetic operation on said first operand from said first register means and said expanded second operand from said expanding means.