1. An apparatus comprising: a first processor core to be placed in a low power mode, in which at least modified information stored within the first processor core's local cache is to be stored in a shared cache; a second processor core to access the shared cache for information accessible within the local cache prior to the first processor core entering the low power mode, the second processor core to access the shared cache instead of the local cache in response to the first processor core being placed into the low power mode.