1. A method of operating a pipelined computer processor, said method comprising: identifying program instructions dependent upon results of prior program instructions in a set of instructions; dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, each instruction of said set belonging to only one subset; and processing at least two of said subsets concurrently, each of said two subsets operating on a different piece of input data.