1. A system for automatically generating a hierarchical register consolidation structure, comprising: a processor; a graph generator that parses a Hardware Description High level Design Language (HDL) file in three different passes to generate an intermediate graph containing definitions of microprocessor-accessible registers, node interrelationships and summary bits, bit offsets and masks associated with alarm registers of external devices identified by said HDL file, wherein: a first pass extracts information associated with said microprocessor-accessible registers; a second pass identifies said node interrelationships and associates said alarm registers with mask registers and persistency and delta information; and a third pass generates said bit offsets and said masks associated with said alarm registers and associates said summary bits therewith; a graph converter, associated with said graph generator, that selectively adds virtual elements and nodes to said intermediate graph to transform said intermediate graph into a mathematical tree; and a description generator, associated with said graph converter, that employs said mathematical tree to generate a static tree description in a programming language suitable for use by a device-independent condition management structure and an HTML traversable tree representation based on said mathematical tree, wherein both of said static tree description and said HTML traversable tree representation form a hierarchical register consolidation structure to provide a logical representation of said microprocessor-accessible registers, node interrelationships, summary bits, bit offsets, and masks of said external devices.