1. A method for simulating a circuit design, the method comprising: checking a state of one or more inputs of one or more logic elements of the circuit design; for each input of the one or more logic elements having a state indicating an input change: computing a logic level depth associated with the input, the logic level depth based at least in part on a number of primitives included in a signal path from the input to an input of a register included in the signal path; determining a maximum logic level depth of the one or more logic elements based on the computed logic level depths; and for one or more logic elements having an input with the state indicating the input change, scheduling for simulation by one or more processors a simulation range of logic levels, the simulation range comprising a first logic level to a last logic level, the last logic level having a logic level depth corresponding to the determined maximum logic level depth.