1. A Peripheral Component Interconnect-Express (PCIe) switch comprising: a memory to store a first base address in an endpoint device, wherein the first base address points to a first location of firmware code in the endpoint device; and a processor that: receives a first transaction from a first information handling system to a physical function of an endpoint device; determines that the first information handling system can not access firmware code from the endpoint device, based upon the first transaction being to the first physical function; determines that the first transaction is a first request to receive the firmware code from the endpoint device, and that the first transaction is issued to the first base address; blocks the first transaction from being issued to the endpoint device; receives a second transaction from the first information handling system to the second base address; and provides the firmware code to the first information handling system from the memory in response to the second transaction, wherein in providing the firmware code, the processor further provides a second base address to the first information handling system, wherein the second base address points to a second location of the firmware code in the memory.