1. A superscalar pipelined microprocessor, comprising: a register set, defined by an instruction set architecture of the microprocessor; a cache memory; execution units; and a store unit, coupled to the cache memory, wherein the store unit is distinct from the other execution units of the microprocessor, the store unit comprising an arithmetic/logic unit (ALU); wherein the store unit is configured to receive an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result; wherein the store unit is configured to read the source operand from the source register; wherein the ALU is configured to perform the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result; wherein the store unit is further configured to operatively write the result to the cache memory.