1. A bus arbiter circuit comprising: a bus arbitration logic circuit; a command logic circuit coupled to said bus arbitration logic circuit; a decode circuit having a plurality of programmable option select registers, said decode circuit coupled to said bus arbitration circuit and to said command logic circuit; and an operating mode decode logic circuit coupled to said bus arbitration logic circuit, said operating mode decode logic circuit decoding a received signal to determine which one out of a plurality of operating modes the bus arbiter circuit is to operate in and to command, as a function of the operating mode selected, operation of said bus arbitration logic circuit, said command logic circuit and said decode circuit; and to interpret the contents of said plurality of programmable option select registers.