1. A Reduced Instruction Set Computing (RISC) processor having a MIPS instruction set and supporting an X86 virtual machine, comprising: an instruction module; a decoder that includes a top-of-stack (TOP) pointer register and a look-up table module; a look-up table; a fixed-point operation component; a floating-point operation component; and a floating-point register pile that includes a floating-point control register, floating point register stacks, and numbers 1-3 floating-point registers, wherein: the instruction module is adapted for storing a virtual machine instruction set that supports the X86 virtual machine; the decoder is adapted for, during the decoding of an instruction of the virtual machine instruction set, distinguishing a virtual machine instruction set mode of the instruction, decoding the instruction according to the distinguished virtual machine instruction set mode, and outputting the decoded instruction to the fixed point operation component or the floating-point operation component; the look-up table is adapted for storing jump addresses in an X86 program and MIPS jump addresses, and looking up translations from the jump addresses in the X86 program to the MIPS jump addresses according to the output of the decoder; the fixed-point operation component is adapted for, when the instruction is a fixed-point instruction of the virtual machine instruction set, processing the fixed-point instruction of the virtual machine instruction set according to the output of the decoder and outputting an execution result; the floating-point operation component is adapted for, when the instruction is a floating-point instruction of the virtual machine instruction set, processing the floating-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result; the TOP pointer register is adapted for maintaining a floating-point stack operation pointer and storing a value of the floating-point stack operation pointer; and the look-up table module is adapted for realizing a conversion from an X86 source instruction address to an MIPS target instruction address by using the lookup table according to an instruction related to the look-up table.