1. A method for timing analysis of an electronic circuit design for an electronic circuit, the electronic circuit design having a plurality of cells interconnected at a plurality of nodes, the method comprising: establishing a timing graph defining a plurality of timing paths through different subsections of the electronic circuit design; defining a timing window for each of the nodes included in at least one timing path, the timing window of each node having early and late edges respectively defining worst case early and late signal arrival times at the node; executing at least one preliminary round of a predetermined signal integrity analysis on the electronic circuit design based on the timing windows of the nodes to identify at least one pair of the nodes as victim and aggressor nodes subject to crosstalk coupling; adaptively adjusting the timing window of at least one said victim node within said subsections of the electronic circuit design according to a predetermined timing property acquired therefor to form an optimized timing window for said victim node; executing at least one primary round of the predetermined signal integrity analysis on the electronic circuit design based in part on said optimized timing window for said victim node to generate a delay; annotating the delay to the timing graph; and, executing a predetermined static timing analysis on all said subsections of the electronic circuit design based on the annotated timing graph to generate an optimized timing report, wherein the electronic circuit is adaptively updated responsive to the optimized timing report.