1. In an information processing system including an address translation and generation system, a memory unit in which is stored a segmented program comprising instructions including first and second instructions and in which is stored at least one address conversion table used for converting logical addresses into segment base addresses, and an arithmetic logic unit including an accumulator, the improvement comprising: (A) means for generating a physical address through addition of a segment base address and a segment relative address, the segment base address being obtained by address conversion from a logical address to be converted specified directly or indirectly by a field of said first instruction, said segment relative address being specified by a field of said first instruction, and the addition being specified by an op code of said first instruction; (B) a register specified by a field of said first instruction for storing said physical address and (C) means for generating an effective address through addition of said physical address stored in said register and a displacement specified by a displacement field of said second instruction.