1. A processor comprising: an operand register file having a plurality of operand registers, the operand register file capable of being provided both as a one-dimensional file of registers corresponding to a first addressing dimension being one and as a multi-dimensional matrix file of registers corresponding to a second addressing dimension being greater than one; and execution units coupled to the operand register file for executing instructions that reference the operand registers, wherein at least one of the execution units is capable of executing both first instructions that reference the operand registers using the first addressing dimension and second instructions that reference the operand registers using the second addressing dimension.