1. A data flow-type digital processing apparatus comprising: an input latch including a first section storing a first data, a second section storing a second data, and a third section storing a designation code; a processing unit having a first input end, a second input end and an output end and adapted to execute an arithmetic operation and/or a logic operation using two input data which are supplied to said first and second input ends; an output latch including a section storing a result of the arithmetic operation and/or a logic operation of said processing unit; a multiplexer having a first input portion, a second input portion and an output portion and inserted between said input latch and said processing unit; a first bus coupling said first section of said input latch to said first input end of said processing unit; a second bus coupling said second section of said input latch to said first input portion of said multiplexer; a third bus coupling said output portion of said multiplexer to said second input end of said processing unit; a fourth bus coupling said output end of said processing unit to the storing section of said output latch; a fifth bus coupled to said output latch for deriving the result of the storing section of said output latch; a sixth bus coupling said output latch to said second input portion of said multiplexer to feed back the result of the storing section to said multiplexer; and, a control unit coupled to said input latch and said multiplexer for selectively applying a first signal and a second signal to said multiplexer according to said designation code stored in said third section of said input latch, said second bus being coupled to said third bus in response to said first signal, said sixth bus being coupled to said third bus in response to said second signal.