1 A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of: (a) providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; (b) receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and (c) performing by the emulator the atomic instruction for the processor using the data and the address location from the request.