1. A VLIW instruction processor comprising: a long instruction supply circuit which sequentially supplies a plurality of compressed long instructions constituting a program to be executed; an instruction expanding unit which expands one compressed long instruction supplied from said long instruction supply circuit and generates a plurality of small instructions; and a plurality of function units which execute the plurality of small instructions in parallel, wherein the plurality of function units are divided into a plurality of function unit groups; wherein said instruction expanding unit has a plurality of instruction expanding circuits operating in parallel and provided in correspondence with one of the plurality of function unit groups; wherein each compressed long instruction has a plurality of instruction fields corresponding to one of the plurality of function unit groups, each instruction field includes a compressed, grouped instruction representative of a group of small instructions to be executed in parallel by each function unit corresponding to said each instruction field, the compressed, grouped instruction being represented by a smaller number of bits than the number of total bits of the group of small instructions; wherein each instruction expanding circuit expands a compressed, grouped instruction in a long instruction supplied from said instruction supply unit, the compressed, grouped instruction being contained in one instruction field corresponding to one function unit group corresponding to said each instruction expanding circuit, generates a group of small instructions represented by the grouped instruction, and outputs in parallel the generated group of small instructions to the corresponding one function unit group; wherein the compressed, grouped instruction contained in each instruction field of each long instruction includes a compressed group code representative of a group of operation codes (OP codes) necessary for each of the group of small instructions represented by the grouped instruction, the compressed group code being represented by the smaller number of bits than the number of total bits of the group of OP codes, and a group of operand information sets representative of at least one operand necessary for one of the croup of small instructions; wherein each instruction expanding circuit comprises: a group code expanding circuit which expands the compressed group code in a long instruction supplied from said instruction supply unit, the compressed group code being contained in an instruction field corresponding to said each instruction expanding circuit, generates a group of OP codes necessary for the group of small instructions represented by the group code, and outputs in parallel the croup of generated OP codes, and a small instruction generating unit which generates a croup of small instructions by combining each of the group of output OP codes with one of the croup of operand information sets, and outputs in parallel the group of generated small instructions to the corresponding one function unit group corresponding to said each instruction expanding circuit; wherein the compressed group code in each instruction field of each long instruction is set as a pointer to an entry of one instruction table among a plurality of predetermined instruction tables; wherein the plurality of instruction tables each register a plurality group of OP codes; wherein each instruction table is set in correspondence with each instruction field of a plurality of long instructions, said each instruction field corresponding to each of the plurality of function unit groups; wherein combinations of the plurality group of OP codes registered in each instruction table are combinations of a plurality group of unique OP codes, among the combinations of a plurality group of OP codes represented by a plurality of compressed group codes in a plurality of instruction fields corresponding to said each instruction table and contained in the plurality of long instructions; and wherein one entry of each instruction table registers one combination of a group of OP codes represented by the group code of each instruction field contained in each long instruction.