1. A processor comprising: a synchronous dynamic random access memory (SDRAM) controller to couple to an SDRAM; a reduced instruction set computer (RISC) processor coupled to a first bus and the SDRAM controller; a plurality of programmable multithreaded processing engines to process network packets; a bus interface unit coupled to a second bus and the plurality of programmable multithreaded processing engines, the bus interface unit comprising memory mapped registers, a transmit first-in-first-out (FIFO) queue, a receive FIFO queue, and logic to transfer data between the transmit and receive FIFO queues and a shared resource; and logic coupled to the first bus and the second bus to enable access to memory mapped registers of the bus interface unit by the RISC processor; wherein the logic is to convert a read or write operation in a first format to a corresponding read or write operation in a second format to allow the RISC processor to transfer data to and from the memory mapped registers of the bus interface unit.