1. A method of routing a semiconductor chip's global nets, comprising: ranking said semiconductor chip's global nets, wherein said ranking includes at least one of the following: ranking power/ground nets over clock signal nets; ranking power/ground nets over timing/slew critical nets; ranking clock signal nets over timing/slew critical nets; ranking shorter length and lower fan-out nets over longer length and higher fan-out nets; identifying a subset of said global nets; routing said subset of global nets using multiple threads, each of said global nets within said subset routed by one of said threads in isolation of said subset's other global nets; identifying a second subset of said global nets; routing said second subset of global nets using said multiple threads, each of said global nets within said second subset routed by one of said threads in isolation of said second subset's other global nets but in respect of the routes of said subset of global nets.