1. An integrated circuit, comprising: scan chains, each of the scan chains reconfigurable to operate, based on a control signal, in one of at least three modes, a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, a scan chain in the capturing-compacting-shifting mode shifting out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data.