1. A method of assessing printability of a very-large-scale integration design for creating an integrated circuit, the method comprising: performing a first set of steps during a training phase, said first set of steps comprising: generating a training set of very-large-scale integration design shapes representative of a population of very-large-scale integration design shapes; obtaining a set of mathematical representations of respective shapes in the training set; identifying at least two classes of physical events causally linked to the printability for the very-large-scale integration design shapes, each of the classes being associated to a respective level of printability; labeling each mathematical representation of the set according to one of the identified classes, based on a lithography model; and selecting a probabilistic model function maximizing a probability of a class, given the set of mathematical representations; and performing a second set of steps during a testing phase, said second set of steps comprising: providing a very-large-scale integration design shape to be tested; testing the provided very-large-scale integration design shape, by obtaining a mathematical representation of the provided very-large-scale integration design shape; by computing estimates of posterior probabilities for each of the identified classes, given the obtained mathematical representation; and by identifying the class with the highest estimate of posterior probabilities obtained; and labeling the provided very-large-scale including at least one memory drive and a processor drive integration design shape according to the identified class, wherein a computer system including at least one memory device and a processor device is configured to perform one or more said first set and second set of steps.