1. A method of verifying a circuit design of a network switching logic block comprising: generating, by a processor, a reduced model of the circuit design of the network switching logic block, wherein the generating the reduced model comprises applying induction to define properties of initial states of the circuit design as a superset of the initial states of the circuit design to verify a property against an entire table of the network switching logic block by verifying the property against a subset of the entire table; checking the reduced model by applying at least one performance property to the reduced model; generating at least one model of a sequential operation of the circuit design, the sequential operation comprising a lookup request on a bucket of the reduced model; and applying the at least one model to the reduced model to verify the circuit design, wherein the switching logic block includes a plurality of Ethernet ports and MAC addresses mapped to the plurality of Ethernet ports.