1. A multi-core processor system comprising a plurality of cores and a plurality of cache memories accessed by the plurality of cores, wherein a given core of the plurality of cores is configured to: detect a second thread executed by a second core other than a first core upon detecting a first thread executed by the first core among the cores; and stop a broadcast between a first cache memory corresponding to the first core, among the plurality of cache memories, and a second cache memory corresponding to the second core, among the plurality of cache memories, to stop establishment of coherency for the first cache memory and the second cache memory upon determining that no shared data commonly accessed by the first thread and the second thread when the threads are being executed, is present based on a dependency information of threads sharing no data stored in a storage area of the given core of the plurality of cores, wherein the dependency information includes a list of threads that do not access the shared data as an arbitrary thread.