1. A device comprising: a conditional arithmetic logic unit, implemented at least partially in hardware, to: perform, based on a microinstruction associated with processing received data, a first operation to generate a first result, and output the first result via a particular bus of a plurality of buses; and a main arithmetic logic unit, implemented at least partially in hardware, to: select, based on the microinstruction, the particular bus from the plurality of buses to determine the first result as corresponding to a first input, select, based on the microinstruction, a set of input buses from the plurality of buses to determine a second input, perform a second operation on the first input and the second input to generate a second result, and output, based on the microinstruction, the second result, the received data being processed based on the second result.