1. A microprocessor, comprising: a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode; wherein a first core of the plurality of processing cores is configured to: encounter an instruction that instructs the first core to apply a microcode patch; and in response to encountering the instruction: inform each core of the other of the plurality of processing cores of the microcode patch; and apply the microcode patch to the hardware of the first core; and wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.