1. An apparatus comprising: a first set of multiple cores; a first buffer associated with the first set; a second set of multiple cores; a second buffer associated with the second set; communication circuitry configured to transfer messages from cores not in the first set to the first buffer, and to transfer messages from cores not in the second set to the second buffer; and wherein a first core of the first set is configured to send messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry, where at least one first type of instruction corresponds to a first operation that is performed by the second core without requiring any instructions to be transmitted through the communication circuitry to complete the first operation, and at least one second type of instruction corresponds to a second operation that is performed by the second core requiring at least one message to be transmitted through the communication circuitry to complete the second operation, the at least one message including an acknowledgement associated with an instruction of the first type, the instruction of the first type having been initiated in response to the second operation; and wherein the buffer of the second set is large enough to store a maximum number of instructions of the second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of the first type.