1. A method to perturb field programmable gate array (FPGA) code to prevent a side channel attack, the method comprising: receiving a set of circuit design instructions associated with an FPGA processor; analyzing security factors associated with the set of circuit design instructions to determine whether one or more security risk factors associated with the set of circuit design instructions are present; and in response to a confirmation that the one or more security risk factors are present, executing a perturbation of the set of circuit design instructions.