1. A memory controller comprising: a controller token output interface coupled to a token input interface of a first memory device of the plurality of memory devices coupled together in series; a controller token input interface coupled to a token output interface of a last memory device of the plurality of memory devices; and token generation circuitry configured to circulate a token pulse through the plurality of memory devices, wherein the token generation circuitry is further configured to: generate and provide the token pulse via the controller token output interface to the first memory device; receive the token pulse from the last memory device; and in response to receiving the token pulse from the last memory device, provide the token pulse to the first memory device, thereby causing each given memory device to conditionally execute storage commands dependent upon a presence of the token pulse at the token input interface of the given memory device.