1. A multi-core processor comprising: a first processing core and a second processing core, each including one or more arithmetic logic units and an instruction decoder; wherein the first processing core is capable of operating at a higher processing throughput than that of the second processing core; wherein, in response to an occurrence of an event, a task processed on the first processing core is to be transferred from the first processing core to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core; and wherein the first processing core is to be placed in a lower power state after the second processing core resumes processing the task.