1. A processing apparatus, comprising: a first register file; a second register file configured to hold a part of data held by the first register file; an operation unit configured to perform an operation using data in the second register file, and to output an operation result as output data; an instruction unit configured to issue a write instruction to write the output data and an error detection code for detection of an error in the output data to both the first and second register files, and first and second occurrence instructions to generate respective simulated faults in the first and second register files; a first control unit configured to issue a first generation instruction upon receipt of the write instruction and the first occurrence instruction; a first generation unit configured to generate first simulated fault data according to the output data and the error detection code to output the first simulated fault data to the first register file upon receipt of the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction; a second control unit configured to issue a second generation instruction upon receipt of the write instruction and the second occurrence instruction; and a second generation unit configured to generate second simulated fault data according to the output data and the error detection code to output the second simulated fault data to the second register file upon receipt of the second generation instruction, and to output the output data and the error detection code to the second register file in absence of the second generation instruction.