1. An integrated circuit comprising a built-in self test (BIST) state machine, having: a plurality of states to conduct a plurality of tests for a random access memory (RAM), each state capable of performing a null operation, a write operation, a read operation, and a read/write operation; a command register coupled to the plurality of states and storing a test pattern for use with the plurality of states; and an address counter coupled to the plurality of states to determine a test location in the RAM.