1. An apparatus for computer hardware multithreading comprising: a plurality of processors, each processor having hardware support for the capability of executing a plurality of threads; a memory coupled to the plurality of processors; a thread dispatch mechanism residing in the memory and executed by at least one of the plurality of processors, the thread dispatch mechanism determining which of the plurality of processors are idle, which of the plurality of processors is busy processing a thread but can accept a new thread, and which of the plurality of processors cannot accept the new thread since it is working on a maximum number of threads the processor can execute and, the thread dispatch mechanism dispatching the new thread to an idle processor, if one exists; and wherein all processors are made busy with a first thread before dispatching a second thread to any processor.