1. In a system including a clock source for generating a clock signal, a system machine cycle being determined by reference to the clock signal, a refreshable memory means, a sequence and interrupt logic circuit, and a control store for producing micro-code instruction signals each system machine cycle in response to addresses generated by the sequence and interrupt logic circuit, a memory refresh request circuit comprising, in combination: a counter, responsive to the clock signal, for producing at least one count signal representing at least one count of the clock signal, the counter also being responsive to a clock reset signal to reset the counter; an array logic device, responsive to the at least one count and to the micro-code instruction signals, (a) for producing a memory refresh request signal and the clock reset signal when a specified count has been achieved, (b) for producing a freeze clock signal to block further sequencing of the sequence and interrupt logic circuit during a machine cycle referred to as an after cycle, which after cycle follows a machine cycle referred to as a start cycle, when the micro-code instruction signal to be executed during the after cycle requires an access to the memory means, a start cycle being determined by the array logic device to occur when the memory refresh request signal has been produced and the micro-code instruction signal to be executed during that machine cycle does not require an access to the memory means, and (c) for producing an interrupt signal which is input into the sequence and logic circuit when a second specified count has been achieved after the memory refresh request signal has been produced without a start cycle being determined to have occurred.