1. A static random access memory array comprising: a plurality of memory cells each having a memory storage element, wherein each memory storage element is accessible via a word line and at least one bit line; a plurality of arithmetic and logic circuits being fabricated in selected locations in said memory array in place of selected memory cells, whereby certain memory cells in said memory array are configured as an arithmetic or logic cell to perform arithmetic or logic functions respectively; said arithmetic and logic circuits are coupled to selected memory cells for receiving bits of information relating to operand values, upon which an arithmetic or logic operation will be performed; said arithmetic and logic circuits and memory cells being fabricated in a single integrated circuit; and wherein said arithmetic and logic circuits comprise: a first and a second pass transistor; a third transistor; and pull down logic circuitry; said first and second pass transistors each has its gate coupled to a word line, said first pass transistor further has its source coupled to a bit line and its drain coupled to the source of said third transistor, said third transistor further has its drain coupled to ground and its gate is coupled to a common node, said second pass transistor is coupled between an inverted bit line and said common node; said pull down logic circuitry is coupled between said common node and a ground voltage and is comprised of n channel MOS devices which only sink current and said pull down logic circuitry is coupled to at least one selected memory cell for receiving at least one bit of information relating to operand values upon which arithmetic or logic operations are to be performed in the pull down logic circuitry.