1. A synchronous DRAM (SDRAM) memory interface, comprising: a pipeline buffer having an input connection and an output connection, the pipeline buffer having a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles; a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a plurality of inputs; and a plurality of SDRAM-compatible interconnects, wherein one or more interconnects of the plurality of SDRAM-compatible interconnects are coupled to the output connection of the pipeline buffer.