1. A coding process for a signal processor for automatically determining a first coding for storage addresses for a plurality of outputs in an output array, said signal processor including a clock, the coding process comprising the steps of: determining a first output multidimensional space, including a first set of axes and a second set of axes; inputting an input array including a first plurality of input data elements; selecting a second plurality of data elements from said first plurality of data elements by using an input pattern according to a first input relation and a second input relation; transforming said input pattern according to an elementary transformation to generate an output pattern of output data elements; generating said output array by ordering a plurality of said output pattern of said output data elements based on a first output relation and a second output relation, wherein said first set of axes correspond to axes of a quotient array generated by dividing said output array by said output pattern, said second set of axes correspond to axes of said output pattern, and said first output multidimensional space includes all output data elements of said output array ordered for successive traversal according to a first incrementation of said clock; and determining a first projection matrix from said first output multidimensional space to said output array.