1. A semiconductor memory receiving command signals, the memory comprising: a register configured to store data representative of selections for a plurality of memory operating options, the register having a plurality of mode registers, a first mode register of the plurality configured to store data corresponding to a selection from a set of selections for a first memory option, a second mode register of the plurality configured to store data corresponding to one of a plurality of sets of selections for the first memory option; and a command decoder coupled to the register and configured to decode the command signals and in response thereto generate internal control signals in accordance with the data stored in the register.