1. A device comprising: an integrated circuit comprising a computational unit configured to process at least a first input bit stream and a second input bit stream, wherein each input bit stream of the first input bit stream and second input bit stream comprises a sequential set of data bits or two or more sets of data bits in parallel, and wherein each set of data bits of the sets of data bits is deterministically encoded to represent numerical values based on a probability that any data bit in the respective set of data bits is high, and wherein the computational unit comprises: a convolver configured to generate pair-wise bit combinations of the data bits of the first input bit stream and the data bits of the second bit stream, and a stochastic computational unit configured to: perform a computational operation on the pair-wise bit combinations; and produce an output bit stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit stream represent the result based on a probability that any data bit in the set of data bits of the output bit stream is high.