1. A processor comprising: a circuit coupled to receive an indication of a memory operation to be executed in the processor, wherein the circuit is configured to predict whether or not the memory operation is misaligned responsive to the indication, and wherein the indication comprises at least a portion of an address that locates an instruction corresponding to the memory operation in memory; wherein a number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned.