1. A computer-implemented method for managing evaluation of third party silicon intellectual properties (IPs) and integration of the IPs into a chip design, the method comprising: receiving directly from a third party IP vendor at a Web-based IP portal; executing on one or more processors, external IP information associated with a third party IP from the third party IP vendor via a secure access layer, the external IP information comprising a design and functional specification associated with a third party silicon IP of the third party IP vendor; automatically converting by the IP portal the received external IP design and functional specification to a schema describing inputs, outputs, available design files and languages, design rule checker reports, EDA platforms used for design and validation, and interface protocols of the third party IP without disclosing proprietary information about internal company chip design requirements to the third party IP vendor, the schema having a specified dynamic format consistent with the internal design requirements and utilizing a hardware description language (HDL); wherein automatically converting the received external IP design and functional specification to the schema comprises analyzing the design and functional specification using rule-based analysis, decomposing, and classifying a structure of the schema, and wherein automatically converting the received external IP information to the schema further comprises dynamically binding IP features and schema attributes at runtime during the analysis of the third party IP; qualifying by the IP portal the received external IP information received directly from the third party IP vendor as a third party IP submission in conformance with the internal company chip design requirements; performing by the IP portal one or more functions on the received IP information; authorizing by the IP portal user access privileges and encrypting a message based on an interface protocol; and transmitting by the IP portal the encrypted message.