1. A scalable graphics processor architecture comprising: a base graphics architecture; wherein the base graphics architecture further comprises: a plurality of rendering processors; a first bus coupled to the plurality of processors for providing I/O signals to the processors; a first expansion connector coupled to the first bus; a plurality of video digital to analog converters (VDACs), each of the VDACs adapted for driving a display; a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; a switch coupled to the plurality of processors, the switch being for selectively driving the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and such that the rendering processors drive all of the plurality of VDACs when the switch is in a second mode; and a second expansion connector coupled to the switch for providing image data to at least one of the plurality of digital analog converters; and an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture.