1. A memory cell, comprising: a memory cell write enable node and a memory cell output node; a fuse having a first node and a second node; and an antifuse having a trigger node, a first node, and a second node, wherein the trigger node is coupled to the memory cell write enable node, wherein the first node of the antifuse and the second node of the fuse are coupled to the memory cell output node, wherein first and second voltages appearing at the memory cell output node are indicative of first and second binary states of the memory cell.