1. A processor, comprising: a decoder, configured to decode an instruction that instructs the processor to perform subsequent computations in an approximate manner; architectural registers configured to hold operands; error storage associated with each architectural register that is configured to indicate an amount of error in a result stored in the architectural register; and a functional unit, configured to receive one or more operands from the architectural registers and error amounts from the associated error storages, perform a subsequent computation on the operands in the approximate manner in response to the instruction, accumulate the error amounts associated with the one or more operands prior to the approximate computation with an error amount introduced by performing the approximate computation, and store the result and the accumulated error amount in a destination architectural register and its associated error storage.