1. A clock generation circuit, comprising: a random number generator configured to generate random numbers according to a first probability distribution; a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto; and a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution, wherein probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.