1. A method of executing a machine instruction in a central processing unit, the method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation; a first register field to be used to designate a first register, the first register comprising a first operand, the first operand comprising a vector having a plurality of elements; a first field to specify a starting position; and a second field to specify an ending position; and executing the machine instruction, the executing comprising: generating a plurality of masks for the plurality of elements of the first operand, the generating for a mask comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position.