1. An indexed table circuit, comprising: a plurality of banks for storing data to be accessed; a split index array for storing split indices; wherein: each of the plurality of banks and the split index array includes multiple storage locations; the indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, each entry including a storage location in each of the plurality of banks and a storage location in the split index array; and selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.