1. A storage device for logical-to-physical address mapping, comprising: a memory that stores machine instructions; and a processor coupled to the memory that executes the machine instructions to: construct a mapping table comprising a plurality of table entries, wherein the mapping table is indexed by logical addresses and each of the table entries comprises a corresponding physical address in a storage, replace a first sequence of the plurality of table entries comprising sequential physical addresses with a first compressed mapping table entry in the mapping table to generate a compressed mapping table, store the compressed mapping table in the memory, store a plurality of uncompressed mapping table entries starting at a first location in a cache, and map a first logical address associated with a first uncompressed mapping table entry to the first location in the cache.