1. A method comprising: receiving functionalities of multiple components of a system-on-chip (SoC); generating a graphical layout of the functionalities, the graphical layout including module representations, wherein each of the module representations is associated with a corresponding one of the functionalities; receiving an expected output of the graphical layout; back propagating the expected output from an output node of the graphical layout via two or more of the module representations to generate a stimulus at an input of a portion of the graphical layout, wherein said back propagating is performed to generate a scenario model, wherein the scenario model includes the portion of the graphical layout; and providing the graphical layout with the expected output and the stimulus to a test bench program for performing a test on a design of the SoC.