1. A microprocessor, comprising: a central processing unit core, for processing data according to operations defined by instructions to be executed in a program order, wherein at least one of said instructions is of a conditional branch type; a write buffer having a plurality of buffer entries, coupled to said central processing unit core, for receiving data therefrom corresponding to results of said instructions, wherein each of said buffer entries includes at least one speculation control bit indicating, when set, that data to be written to each of said buffer entries is from the execution of an instruction in a predicted branch in program order after an instruction of the conditional branch type; a cache, having a plurality of locations, said cache coupled to said write buffer for receiving data therefrom, and coupled to said central processing unit core for presenting data thereto; a memory bus, coupled to said central processing unit core, said write buffer, and said cache, for receiving data from and presenting data to said cache; and control logic for controlling the presenting of data by said write buffer to said cache so that the contents of each of said buffer entries are presented to said cache only if the speculation control bit is not set.