1. A system for implementing coherent accelerator function isolation for virtualization in a hardware input/output (IO) adapter comprising: a processor; a hypervisor managing functions associated with the hardware I/O adapter; the hardware I/O adapter comprising a coherent accelerator including an interface services layer providing Partitionable Endpoint (PE) functions and multiple accelerator function units (AFUs); each AFU being enabled to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor; each AFU having access to system memory bound to the application software and each AFU being adapted to make copies of memory within AFU memory-cache in the AFU; and each of the AFU memory-cache and processor memory-cache being adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy for memory coherency domain; the system further comprising a Peripheral Component Interconnect Express (PCIE) host bridge (PHB) providing coherent accelerator PE (Partitionable Endpoint) support including an adapter PE and an AFU PE; wherein said AFUs are recognized and operated by an operating system (OS) as memory-mapped AFU devices; and wherein said hypervisor detects and recovers error involving the interface services layer or AFUs, without requiring the termination of the operating system (OS) to restore operation of its respective AFU, with the AFUs sharing a common PCI-Express Services Layer (PSL) endpoint function.