1. A method for designing a logic circuit, comprising: implementing a first logic function as a first transistor network and a complementary second transistor network connected at a central node, said central node serving as a first logic output, each of said first and said second transistor networks being further connected to a respective root; selecting an intermediate node in said first transistor network; determining a logical path from said intermediate node to said central node; implementing a third transistor network having a complementary structure to the transistors in said determined path, being of the opposite transistor type as said first network, and having equivalent inputs relative to the transistors in said determined path; and placing said third transistor network between said intermediate node and said root of said first transistor network.