1. A processor comprising: at least one execution unit; and a vector completion mask (VCM) logic to store information into at least one VCM register, the at least one VCM register to hold a plurality of bits each associated with at least one operand, wherein the VCM logic is to change a first bit stored in the at least one VCM register to a first state if a first operation using a first operand associated with the first bit is successfully performed, wherein the first bit is of a second state to indicate that the first operation using the first operand has not been successfully performed.