1. A method of performing statistical timing analysis on a circuit design upon receipt of a signal path in the circuit design, the method comprising: by using a computing device, receiving the signal path that traverses a plurality of gates; for each of the plurality of gates, receiving a gate statistical distribution that represents delay variation at the gate using a number of statistical moments that comprises a standard deviation and at least one moment that has a higher order than the standard deviation; computing statistical moments for a signal path distribution representing delay on the signal path by applying one or more operations to the gate statistical distributions based on a configuration of the plurality of gates; and converting statistical moments of the signal path distribution to timing moments; converting the timing moments to timing parameters by extracting a set of poles and residues from the timing moments; reconstructing a resulting distribution function based on the computed poles and residues; and using the reconstructed resulting distribution function in timing analysis for the circuit design.