1. A method of testing a memory array on an integrated circuit with built in self test circuitry that includes test control register circuitry and configurable state machine logic, the method comprising: loading memory test control settings into the test control register circuitry; and with the configurable state machine logic, performing memory tests on the memory array based on the loaded memory test control settings, wherein the memory test control settings include march element settings for a march sequence, wherein performing the memory tests comprises performing tests on the memory array with the configurable state machine logic using the march sequence, and wherein the march element settings include march element settings that specify how the configurable state machine logic is to perform a read-during-write memory cell operation when performing the tests on the memory array.