1. A processing system comprising: a plurality of first interrupts generated by a core, said plurality of first interrupts having programmable priorities; a plurality of second interrupts that are generated external to said core, said second interrupts having architecturally fixed interrupt priorities; a status register, coupled to said core, said status register comprising a vector table, and an interrupt register, said interrupt register having a plurality of configurable priority registers for storing said programmable priorities; and a priority encoder, coupled to both said first interrupts and to said second interrupts, and to said status register, said priority encoder prioritizing said first and second pluralities of interrupts utilizing said programmable priorities for said first interrupts and said architecturally fixed interrupt priorities for said second interrupts.