1. A programmable filter processor which is adaptable to different filtering algorithms, and via which a plurality of different software algorithms is executable, the programmable filter processor, comprising: a logic unit including a data path to transmit at least one of a time stamp and an angle stamp along with and in parallel to data generated from an analog-to-digital converter through a plurality of pipeline stages of the logic unit; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filtering algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit adapted to generate control commands for the second memory and the logic unit.