1. A digital signal processor chip for performing a plurality of signal processings of audio and video input signal data in a data processing system having memory means and providing processed output data, comprising: said chip being connected to said system; a first processor part and a second progammable logic part each connected for input and output of data with said system, said second part having programmable logic that is selectively programmed by configuring said programmable logic with circuit configuration data of at least one of a plurality of predetermined logic programs that correspond with a respective one of said signal processings; an internal processor bus for connecting the first and second parts; and said first part having control means receiving commands from said system for initiating said signal processings and in response for controlling transfer of said circuit configuration data of said plurality of predetermined logic programs from said memory means to the second part so that said circuit configuration data of said predetermined logic programs is successively transferred from said memory means to said second part each time a different one of said plurality of signal processings is commanded to be executed, and said control means controlling inputting of the audio and video input signal data to the second part for executing said respective signal processings following configuring of said programmable logic with said circuit configuration data of said respective logic programs, and further controlling outputting of said output data from said second part to said system.