1. An interface between a multi-core shared memory controller and one of a plurality of processing cores comprising: a read address bus adapted for receiving a read address from the processing core; a read data bus adapted for supplying read data from the interface to the processing core; a write address bus adapted for receiving a write address from the processing core; a write data bus adapted for supplying write data from the processing core to the interface; a snoop response bus adapted for supplying a snoop response signal from the processing core to the interface; a snoop data bus adapted for supplying snoop data from the processing core to the interface; a first snoop address bus adapted for supplying a snoop address from the interface to the processing core; a command address bus adapted for supplying one of a read data address or a write data address to the multi-core shared memory controller; a data bus adapted for one of (1) receiving read data from the multi-core shared memory controller, (2) supplying write data to the multi-core shared memory controller or (3) supplying snoop response data to the multi-core shared memory controller; and a second snoop address bus adapted for receiving a snoop address from the multi-core shared memory controller.