1. A processor comprising: a circuit coupled to receive an indication of a string memory operation to be executed in the processor, wherein the circuit is configured to predict whether or not at least one of a plurality of memory operations performed in response to the string memory operation is misaligned, and wherein the circuit is configured to identify a predicted memory operation of the plurality of memory operations that is predicted to be misaligned; wherein a first number of accesses performed by the processor to execute the predicted memory operation is greater than a second number of accesses performed for each other one of the plurality of memory operations.