1. A method for performing memory interleaving comprising: performing, in a first level of a two-level interleaving scheme, interleaving across full cache lines of a memory, performing, in a second level of the two-level interleaving scheme, interleaving across sub-cache lines of the memory; using a prime number of groups of banks for the first level of the two-level interleaving scheme; and using a prime number of banks within each of said groups of banks for the second level of the two-level interleaving scheme; wherein said memory interleaving is performed for a system comprising a host processor having a fixed instruction set that defines instructions that the host processor can execute; and a reconfigurable co-processor comprising reconfigurable logic that is reconfigurable to have any one of a plurality of predefined extended instruction sets for extending the fixed instruction set of the host processor for processing instructions of an executable file, each of said plurality of predefined extended instruction sets defining a plurality of instructions that the reconfigurable co-processor can execute, wherein said plurality of instructions comprise extended instructions that are not natively defined by the fixed instruction set of the host processor.