1. An apparatus for pipelined continuous-time analog-to-digital converters (CT ADCs) comprising: an input delay circuit positioned in a continuous-time signal path of the pipelined CT ADC and coupled to a first summing circuit; and at least one digital delay circuit positioned at an output of a first stage sub-analog-to-digital converter (sub-ADC) of a plurality of pipelined sub-ADCs, the at least one digital delay circuit coupled to each of the first summing circuit and a second summing circuit, the at least one digital delay circuit varying a delay of the at least one digital delay circuit for reducing a residue magnitude and phase, the residue magnitude and phase representing a difference between magnitude and phase of a signal path of the first stage sub-ADC and magnitude and phase of a continuous-time signal path of the pipelined CT ADC, the first summing circuit generating the residue magnitude and phase, the second summing circuit positioned at an output of a second stage sub-ADC, the second stage sub-ADC coupled to an output of the first summing circuit.