1. A multicore processor, comprising: a plurality of cache memories configured to store one or more cache lines; and a plurality of processor cores, each associated with one of the cache memories; with each respective cache memory of at least some of the cache memories configured to maintain at least a portion of the respective cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores, and with each respective cache memory of at least some of the cache memories assigned as a home location for caching a corresponding portion of a main memory in cache lines that are shared among multiple processor cores, and the processor cores configured to access a portion of the main memory at a given address by hashing the address according to a hash function to an index used to access a mapping table to obtain the home location of a cache line that includes the address.