1. A data processing apparatus comprising: a processor configured to process a plurality of threads each having associated thread state data; wherein the processor is configured to process the plurality of threads in a plurality of thread groups, each thread group comprising a number of threads processed in parallel with a common program being executed for each thread of the thread group; a plurality of thread state storage regions each comprising a fixed number of thread state entries, where each thread state entry is configured to store the thread state data including a thread program counter indicative of a next program instruction to be executed for a corresponding thread of the plurality of threads; wherein at least two of the thread state storage regions have different fixed numbers of the thread state entries; wherein the processor is configured to automatically select and process within the same thread group threads having thread state data stored in thread state entries of the same thread state storage region, and to automatically select and process within different thread groups threads having thread state data stored in thread state entries of different thread state storage regions; and a migration control circuitry configured to maintain a divergence counter indicative of a number of times a difference in behavior is detected between at least one selected thread and at least one remaining thread; wherein the migration control circuitry is configured to detect said difference in behavior in response to a divergence indicating instruction included in the common program, the divergence indicating instruction comprising a predetermined instruction having an associated divergence indicating flag, and to migrate said at least one selected thread in response to said divergence counter being greater than a predetermined migration threshold.