1. A processor comprising a reconfigurable minimum operator adapted to compare first and second multi-bit values to determine whether or not the first multi-bit value is less than the second multi-bit value, wherein: the reconfigurable minimum operator is selectively configurable to operate in a first operating mode, in which each of the first and second multi-bit values has a first number of bits; and the reconfigurable minimum operator is selectively configurable to operate in a second operating mode, in which each of the first and second multi-bit values has a second number of bits different from the first number of bits.