1. An integrated circuit device comprising: a processor core for executing a stream of program instructions; core monitoring circuitry for calculating one or more digital metric output values indicating selected ongoing usage-level metrics of the processor core; core performance-state selection circuitry for selecting a desired performance state from among at least two possible desired performance states based, at least in part, on one or more digital metric output values calculated by the core monitoring circuitry, and for outputting a desired performance state output value, the core performance-state selection circuitry operable independent of the stream of program instructions; and actuator circuitry for receiving the desired performance state value from the core performance-state selection circuitry and, in response, adjusting a core power-performance state between at least a first and second level based on the performance state output value the actuator circuitry operable independent of the stream of program instructions.