1. A processing unit for a multiprocessor data processing system, said processing unit comprising: a processor core including a store-through upper level cache, an instruction execution unit, and a flag; wherein the processor core is configured to: responsive to the instruction execution unit executing in a memory transaction a transactional load instruction that speculatively binds to a value held in the store-through upper level cache: set the flag; transmit a transactional load operation to a store-in lower level cache that tracks a target cache line address of a target cache line containing the value; monitor, during a core TM tracking interval, the target cache line address for invalidation messages from the store-in lower level cache until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the target cache line address; responsive to receipt during the core TM tracking interval of an invalidation message indicating presence of a conflicting snooped operation, reset the flag; and at termination of the memory transaction, fail the memory transaction responsive to the flag being reset.