1. A vector reduction circuit configured to reduce an input vector of elements, the vector reduction circuit comprising: a plurality of cells, wherein each of the plurality of cells comprises: an input vector element register configured to receive a particular element of the input vector; a temporary reduction element register configured to receive, from another cell, a temporary reduction element; computation circuitry having one or more computation units, wherein each of the one or more computation units is configured to perform a respective reduction operation using the particular element and the temporary reduction element; and a result register configured to: receive a result of the respective reduction operation, receive a control vector element that corresponds to a respective one of the plurality of cells, provide, when the control vector element indicates the respective one of the plurality of cells is not a last cell for a segment of the input vector, and as a new temporary reduction element to another of the plurality of cells, the result of performing the reduction operation using the particular element and the temporary reduction element, and provide, when the control vector element indicates the respective one of the plurality of cells is a last cell for a segment of the input vector, the result of performing the reduction operation using the particular element and the temporary reduction element to an output circuit, wherein the output circuit is configured to provide, for output as a reduction of a segment of the input vector, the result of performing the reduction operation using the particular element and the temporary reduction element.