1. A programmable logic device configured to include a Finite Impulse Response (FIR) filter structure for selectively operating in one of an interpolation filter mode and decimation filter mode; said programmable logic device having at least one specialized processing block each of which includes a plurality of multipliers and circuitry for adding outputs of said multipliers, at least one said specialized processing block being programmably configured as said FIR filter structure, said FIR filter structure comprising: (1) a number N of multipliers, where: N=INT [CT/(snSH)]+1 when MOD [CT/(snSH)]≠0, N=CT/(snSH) when MOD [CT/(snSH)]=0, C=the number of channels, T=the number of taps, s=1 for an asymmetric filter, s=2 for a symmetric filter, n=the interpolation/decimation factor, S=a timesharing factor representing the number of clock cycles available to the system to process one input or output sample, H is a factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero, MOD [x]=x−INT[x], and INT[x] is the largest integer in x; (2) a sample input and a coefficient input for each of said N multipliers, said coefficient input cycling, during operation of said FIR filter structure, through a plurality of coefficients; (3) at least one circuit for adding outputs of said multipliers to each other; and (4) a respective selectable delay located at least one of (a) before, and (b) after, each said circuit for adding; wherein: selection between said interpolation filter mode and said decimation filter mode occurs during operation of said FIR filter structure; and said selection comprises selection of at least one said respective selectable delay.