1. An interleaver, comprising: multiple processors generating read-addresses in parallel for respective bits of multiple write-words; multiple address queues queuing the read-addresses received from the respective processors, each of the address queues outputting status thereof; a first arbiter selecting an address queue among the multiple address queues that is not empty based on the status of each address queue, the first arbiter being outputting an address from the selected address queue while outputting an address queue ID of the selected address queue; a decoder decoding the address from the selected address queue into a word-address and a bit-address; an input storage storing data to be interleaved, the input storage outputting a read-word based on the word-address; a first selector selecting a write-bit from the read-word based on the bit-address; a write controller arbitrating an individual write-bit to one of the write-words based on the address queue ID, the write controller generating write-addresses for respective write-words; and an output storage storing the write-word based on the write-address.