1. A processor, comprising: at least two cores, each of the at least two cores having a first level cache memory, each of the at least two cores being multi-threaded; a crossbar; a plurality of cache bank memories in communication with the at least two cores through the crossbar, each of the plurality of cache bank memories in communication with a main memory interface; a plurality of input/output (I/O) interface modules in communication with the main memory interface and providing a link to the at least two cores, the link bypassing the plurality of cache bank memories and the crossbar; threading hardware configured to enable each of the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses.