1. A method of calculating a sum in a processor, said method comprising: storing a data set as a sequential series of data values in a memory, the data values being associated with lanes of data values of a selectable bit width; sequentially adding a subset of said sequential series of data values to contents of a register using lane arithmetic to generate a sequence of partial sums within the register, the subset of said sequential series of data values are selected such that lanes of data values within the subset of said sequential series of data values are aligned and added within lanes of the register; and executing bit field arithmetic operations on the contents of the resister within the lanes in order to reduce said sequence of partial sums into a final sum within a lane of the register.