1. A configurable gate array, comprising: at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function.