1. An instruction prefetch buffer connected to an n-bit bus and an output n-bit bus comprising: an array having one n-bit input write port and two m-bit output read ports where n=2 m, said n-bit input port being connected to said input n-bit bus for receiving an n-bit, two m-bit or a mixture of portions of n-bit and m-bit instructions from a main memory for writing into said array and two m-bit output ports each providing respectively m-bits of an instruction read out of said array, said array storing a mixture of n-bit and m-bit instructions which start on m-bit address boundaries within said array; a write pointer register for temporarily storing a first binary number which points to an n-bit location in said array where n bits from said main memory is to be written, said array being connected to said write pointer register and responsive to said first binary number for writing an instruction at said location; and address generation and control logic means connected to said array for accessing the instructions in said array on m-bit address boundaries within said array and providing m-bit instructions on the most significant bit lines of said output n-bit bus and combining two m-bit outputs from said two m-bit output ports in the proper order to form an n-bit instruction on said output bus.