1. A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of operation and the number of operands, comprising: (A) instruction fetch means for fetching an instruction from memory means storing instructions and operands; (B) decoding means connected to said instruction fetch means and for decoding an operation code and an operand specifier; (C) address calculating means connected to said decoding means and for calculating an address of an operand on the basis of the decoded result of the operand specifier from said decoding means; (D) operand fetch means connected to said address calculating means and for fetching the operand from said memory means on the basis of the calculated address; and (E) executing means connected to said operand fetch means as well as said decoding means and for executing the instruction successively by the use of the operands from said operand fetch means and in accordance with the decoded results of the operation codes from said decoding means, said decoding means including: (i) operation code decoding means for decoding the operation codes of the instruction and delivering information on the operands in the operand specifiers, (ii) operand specifier decoding means for decoding information added to specific fields of the respective operand specifiers on deciding whether or not the particular operand specifier is the last operand specifier, and (iii) means for causing the operand specifier to be used again, when the information indicative of the last operand specifier has been received from said operand specifier decoding means and the information indicative of the last operand is not received from said operation code decoding means.