1. A computer implemented method for implementing full-chip optimization across boundaries of a block with reduced physical design data, comprising: using at least one processor executing one or more threads of execution to perform a process, the process comprising: identifying an original set of physical design data of a physical electronic design that comprises a plurality of blocks; generating reduced physical design data of the physical electronic design at least by including a first side instance located on a first path or a first net associated with a block in the physical electronic design; performing full-chip optimization or closure using the reduced physical design data of the physical electronic design, wherein the reduced physical design data are identified from the physical electronic design by using a partial, incomplete netlist that is not yet completely implemented and is to be physically implemented to complete the physical electronic design for at least a part of the original set of physical design data rather than using logic reduction techniques; and merging a change made during the full-chip optimization or closure back to the original set of physical design data.