1. A method for verification of a hardware system-under-test including at least one processor, the method comprising: building an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, wherein the test cycle comprises at least generation and execution of a test; said building comprises embedding in the executable image data corresponding to: architectural knowledge of the system-under-test, testing knowledge of the system-under-test, and a test template for the system-under-test, wherein said test template is defined in a formal language and includes biasing directives to control one or more parameters of a randomly generated test of said system-under-test; wherein said building further comprises storing the executable image in a non-transitory computer readable medium; and wherein said executable image of the hardware exerciser is configured to be executed by the hardware system-under-test.