1. A data processing apparatus comprising: processing circuitry configured to perform data processing; a plurality of registers configured to store data for processing by the processing circuitry; and a memory rename table configured to store a plurality of memory rename entries, each memory rename entry identifying a mapping between a memory address of a location in a memory and a mapped register of said plurality of registers, the memory rename entry specifying a register number identifying the mapped register; wherein the processing circuitry is configured, in response to a store instruction specifying a store target memory address, to store a data value to a store destination register, and to provide a memory rename entry in said memory rename table identifying a mapping between said store target memory address and the store destination register; and the processing circuitry is configured, in response to a load instruction specifying a load target memory address, to detect whether the memory rename table comprises a corresponding memory rename entry corresponding to said load target memory address, and if the memory rename table comprises the corresponding memory rename entry, to read a data value from the mapped register identified by the corresponding memory rename entry, write the read data value to a load destination register.