1. A method comprising: decoding, in a decode stage of hardware processor pipeline, one particular instruction of a plurality of instructions; determining that said particular instruction requires a memory access; responsive to determining that said particular instruction requires a memory access, predicting whether said memory access will result in a cache miss based on a program counter of said particular instruction, said predicting in turn comprising accessing one of a plurality of entries in a pattern history table stored as a hardware table in said decode stage, said accessing being based, at least in part, upon at least a most recent entry in a global history buffer, said pattern history table storing a plurality of predictions, said global history buffer storing actual results of previous memory accesses as one of cache hits and cache misses; scheduling at least one additional one of said plurality of instructions in accordance with said predicting; and updating said pattern history table and said global history buffer subsequent to actual execution of said particular instruction in an execution stage of said hardware processor pipeline, to reflect whether said predicting was accurate.