1. A processor comprising: an instruction decoder that decodes an extension instruction and decodes a subsequent instruction, which includes address information, subsequent to the extension instruction; an extension register that stores address extension information for extending the address information when the extension instruction is decoded by the instruction decoder; and an operation unit that extends the subsequent instruction so that the subsequent instruction designates a register, which stores an operand, concatenating the address information included in the subsequent instruction and the address extension information stored in the extension register wherein a plurality of subsequent instructions subsequent to the extension instruction and a plurality of address extension information for the plurality of subsequent instructions are stored in the extension register in response to decoding of the extension instruction.