1. A floating point unit (FPU) for a computer system, comprising a FPU dataflow pipeline having multiple pipeline stages for arithmetic computation, a normalization stage, and a rounding stage, each of which pipeline stages occurs during processing of a stream of instructions in said dataflow pipeline, said FPU dataflow pipeline having data inputs and control inputs for receiving data and control input data and instructions for performing a floating point computation, said FPU dataflow pipeline also having data outputs wherein resultant data are outputted from the FPU dataflow pipeline and a control output used to update architectural information including floating point array write enables and addresses, condition codes, and a completion signal which will advance a program pointer for said floating point unit, a detector of special conditions unit for dynamically detecting an event occurring during execution of an instruction in the floating point unit that hardware execution of an IEEE compliant binary floating point instruction will require millicode emulation, said detector of special conditions unit being controlled by system registers which are set by millicode or set at initial program load, and when one of the events occurring during execution of the instruction in the floating point unit that hardware execution of an IEEE compliant binary floating point instruction will require millicode emulation is detected, a corresponding system register mask is checked by an exception handling unit to determine if a floating point computation should be completed or suppressed.