1. A CPU having a pipeline for processing a plurality of instructions from two separate instruction sets, said pipeline comprising: first instruction decode means for decoding instructions from said first instruction set, said first decode means providing decoded instructions to said plurality of functional units, said first instruction set having a first encoding of opcodes to instructions; second instruction decode means for decoding instructions from said second instruction set, said second instruction set having a second encoding of opcodes to instructions, said second encoding of opcodes to instructions being separate and independent from said first encoding of optodes to instructions, said second decode means providing decoded instructions to said plurality of functional units; enable means for enabling either said first instruction decode means or said second instruction decode means, said enable means coupled to said first instruction decode means and coupled to said second instruction decode means; a plurality of functional units for processing said plurality of instructions; a relocatable functional unit in said plurality of functional units, said relocatable functional unit for executing native instructions from both of said two separate instruction sets; means for indicating which one of said two separate instruction sets is being processed by said plurality of functional units; and means for relocating, responsive to said indicating means, said relocating means for temporally relocating said relocatable functional unit in time and sequence order to other functional units in said plurality of functional units.