1. A method for testing control logic of caches to detect invalid cache states in a multiprocessor system having a main memory coupled to a plurality of processor associated with a plurality of caches, each of said caches having a plurality of blocks, said control logic configured to examine states of control store flags contained in a selected block, said method comprising the steps of: acquiring information from said selected block of said caches and from a location in the main memory corresponding to said selected block, the information including said control store flags of said selected block; generating additional flags from the information acquired from said caches, said additional flags indicating the state of said caches relative to each other and to the main memory; deriving a bit index from said control store flags and said additional flags, said bit index having a value corresponding to a value of the control store flags and additional flags; creating a bit vector from an array of valid cache states of said system, said valid cache states contained in a state table, said bit vector having a plurality of bit positions and a value associated with each position; and indexing into said bit vector in response to said bit index to test said bit position value of said bit vector, thereby detecting invalid cache states of said system.