1. A data processing apparatus comprising: a mapping node comprising mapping units configured to process input data in parallel to generate and output mapping results; a shuffle node comprising shuffle units and a memory buffer, the shuffle units configured to process the mapping results output from the mapping units in parallel to generate and output shuffle results, and the shuffle node configured to write the shuffle results output from the shuffle units in the memory buffer; and a merge node comprising merge units configured to merge the shuffle results written in the memory buffer to generate merging results.