1. A digital signal processor comprising: a memory for storing data words including instructions and operands for performing digital signal computations, said memory organized in rows each having locations for two or more of said data words; a program sequencer for generating instruction addresses for fetching instructions from said memory and data addresses for fetching operands from said memory; a computation unit for performing said digital signal computations using said instructions and said operands fetched from said memory; an instruction decoder for generating one or more control signals in response to an instruction indicating an unaligned data access to specified operands stored in different rows of said memory; and a data alignment buffer for receiving lines of operands from different rows of said memory and for providing said specified operands to said computation unit in response to said one or more control signals, said one or more control signals including an offset value that identifies memory locations of the specified operands relative to a row of said memory, wherein different specified operands are selected from the different rows of said memory based on the offset value.