1. An IC comprising: a memory cell array having a plurality of memory cells; a first and a second port, each of said memory cells being coupled to said first and second ports; a cache memory coupled to said first and second ports, wherein during a read operation subject to one of said memory cells through one of said first and second ports a data stored in said one of said memory cells is read out from said cache memory if it is determined that said cache memory contains said data stored in said one of said memory cells; and a refresh control circuit performing a refresh of the information stored within said memory cells, said refresh control circuit refreshing memory cells through one of said ports while reading data out of said cache memory.