1. In a digital computer system capable of processing two or more instructions in parallel, the combination comprising: a larger capacity, lower-speed storage mechanism for storing instructions to be processed; a smaller-capacity, higher speed mechanism for storing instructions and a plurality of data bits indicating pairs of instructions stored in said memory that can be executed in parallel; an instruction compounding mechanism having an input means and an output means; means coupling said input means of said instruction compounding mechanism to an output of said larger-capacity, lower-speed storage mechanism for transferring instructions from said larger-capacity, lower-speed storage mechanism to said instruction compounding mechanism; said instruction compounding mechanism analyzing dependencies between pairs of instructions and generating said data bits which indicate pairs of instructions that can be executed in parallel based upon said analysis; means to couple said output means of said instruction compounding unit to an input of said smaller-capacity, higher-speed storage mechanism for transferring instruction pairs and said data bits indicating parallel execution of said instruction pairs to said smaller-capacity, higher-speed storage mechanism prior to an instruction fetch and issue unit issuing a command to fetch an instruction of a pair of instructions; said smaller-capacity, higher-speed storage mechanism storing said pairs of instructions and said data bits indicating parallel execution of said instruction pairs; and means to couple an instruction pair from said smaller-capacity higher-speed storage mechanism to a functional instruction processing unit in response to said command to fetch an instruction issued by said instruction fetch and issue unit when said data bits indicate parallel execution of said instruction pair.