1. An embedded DRAM coprocessor formed on a first semiconductive substrate, comprising: an interface adapted to couple the embedded DRAM coprocessor to a processor, the processor being formed on a second semiconductive substrate; a set of one or more functional units; a memory for storing instructions for the set of one or more functional units; an embedded DRAM array; and control logic responsive to a command sent via the interface from the processor, the control logic operative to fork and execute an execution thread in support of a multithreaded program executing on the processor; wherein the embedded DRAM array includes a plurality of DRAM banks and at least one SRAM buffer register operable to buffer a row of a DRAM bank and to allow individual data words in the row to be accessed from the at least one SRAM buffer register.