1. A method for routing of a circuit design netlist, comprising: determining placement of a netlist of the circuit design on a target device; determining a processing time for each net in the netlist; defining a plurality of regions of the target device, wherein boundaries of the plurality of regions are defined to balance a total of the processing times of nets within each region of the plurality of regions with a total of the processing times of nets within each other region of the plurality of regions; concurrent with routing one or more nets of a first one of the plurality of regions by a first processor, routing one or more nets in at least one other of the plurality of regions by at least one other processor; and routing unrouted nets of the netlist.