1. An apparatus for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test, comprising: a first processor configured to: execute a set of instructions configured to control testing of at least a portion of the system under test via the TAP, the set of instructions comprising a TAP-related instruction associated with control of the TAP, the TAP-related instruction comprising an opcode supported by a second processor, the second processor configured to support an interface to the TAP and configured to process the TAP-related instruction for generating one or more TAP control signals adapted to control at least one scan operation via the TAP; detect the TAP-related instruction during execution of the set of instructions; and propagate the TAP-related instruction toward the second processor.