1. A process for reading data from and/or writing data to a random access memory array, comprising the steps of: (A) transferring a first plurality of data bits either to or from a first random address in response to a first transition or logic level of a read/write control signal, and (B) independently transferring a second plurality of data bits either to or from a second random address in response to a second, complementary transition or logic level of said read/write control signal.