1. A method comprising: receiving an instruction, wherein the received instruction is a store instruction, at an out-of-order processor, wherein the out-of-order processor enforces in-order requirements for a cache; performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and in response to the received instruction being the store instruction, executing a pre-fetch operation for a cache line data based on the store instruction and for the same calculated physical address while the store instruction is pending and before the store instruction retires.