1. A method of performing an incremental recompile of a compiled design comprising: skipping database building, logic synthesis and technology mapping stages of a full compilation; creating an atom for a chosen output pin; connecting an internal signal to be viewed to said output pin atom; building an original routing netlist for said compiled design; routing said internal signal to an output pin of said design without changing said original routing netlist to create a final routing netlist; and outputting said final routing netlist into a programming output file (POF) in a form suitable for programming, whereby said design is debugged using said internal signal.