1. A signal processing apparatus comprising: memory means for storing digital signals and processes for processing said digital signals; input and output (I/O) means for inputting and outputting said digital signals to and from said signal processing apparatus; a direct memory access (DMA) controller connected to said memory means and said I/O means for storing/reading said digital signals to/from said memory means and said I/O means in a direct memory access mode; a digital signal processor (DSP) connected to said DMA controller, said I/O means, and said memory means for processing said digital signals stored in said memory means, said DSP executing a data empty check program under the control of a real-time monitor including a semaphore for checking for the existence of said digital signals to be processed and executing another process when said digital signals are not available for processing; and a host CPU connected to said DMA and said DSP for determining whether a data transfer requested by a task of said processes is performed by said DMA controller or said DSP based upon a comparison between an I/O data period and a processing time of said task, whereby said data transfer requested by said task is performed by said DMA when said I/O period is shorter than said processing time of said task.