1. A threshold value logic circuit, comprising: a first weighting subcircuit for forming a carry; a second weighting subcircuit for forming a summation signal; a non-inverting circuit path having a first neuron transistor and a second neuron transistor and an inverting circuit path having a further first neuron transistor and a further second neuron transistor; a weighting terminal of the first weighting subcircuit for forming the carry connected to reference-ground potential via the first neuron transistor and a comparison terminal of the first weighting subcircuit connected to reference-ground potential via the further first transistor; a weighting terminal of the second weighting subcircuit for forming the summation signal connected to reference-ground potential via the second neuron transistor and a comparison terminal of the second weighting subcircuit for forming the summation signal connected to reference-ground potential via the further second neuron transistor a first gate of the first neuron transistor connected to a multiplicand, a second gate of the first neuron transistor connected to a multiplication factor, a third gate of the first neuron transistor connected to a carry signal of a preceding stage, a fourth gate of the first neuron transistor connected to a summation signal of the preceding stage and a fifth gate of the first neuron transistor connected to reference-ground potential; a first gate of the second neuron transistor connected to an inverted carry signal, a second gate of the second neuron transistor connected to the multiplicand, a third gate of the second neuron transistor connected to the multiplication factor, a fourth gate of the second neuron transistor connected to the carry signal of the preceding stage, a fifth gate of the second neuron transistor connected to the summation signal of the preceding stage and a sixth gate of the second neuron transistor connected to reference-ground potential; gates of the further first and further second neuron transistors being supplied with signals, which are inverse of signals present at corresponding gates of the first and second neuron transistors.