1. A processor comprising: an instruction execution pipeline comprising: an instruction fetch stage to fetch a first instruction and a second instruction, an instruction format of the first instruction specifying a first register storing a first input vector that is misaligned with respect to memory addressing space, a second register storing a second, next input vector that is misaligned with respect to the memory addressing space, a first resultant vector, and a third input operand, and an instruction format of the second instruction specifying the second register storing the second, next input vector that is misaligned with respect to the memory addressing space, a third register storing a third, next input vector that is misaligned with respect to the memory addressing space, a second resultant vector, and a fourth input operand; an instruction decoder to decode said first instruction into a decoded first instruction, and decode said second instruction into a decoded second instruction; and an execution unit to: execute the decoded first instruction to cause a routing network to route a first contiguous group of elements from a first end of the first input vector to a second end of said first resultant vector, route a second contiguous group of elements from a second end of the second, next input vector to a first end of said first resultant vector, said first end of the first input vector and said second end of the second, next input vector being opposite vector ends, and preserve the second, next input vector in the second register after execution of the decoded first instruction, wherein said first and second contiguous groups of elements of the first input vector and the second, next input vector are defined from said third input operand, and execute the decoded second instruction to cause the routing network to route a first contiguous group of elements from a first end of the second, next input vector to a second end of said second resultant vector, route a second contiguous group of elements from a second end of the third, next input vector to a first end of said second resultant vector, said first end of the second, next input vector and said second end of the third, next input vector being opposite vector ends, wherein said first and second contiguous groups of elements of the second, next input vector and the third, next input vector are defined from said fourth input operand.