1. A quantum-logic test-development system comprising a processor, a memory coupled to the processor, and a computer-readable hardware storage device coupled to the processor, the storage device containing program code configured to be run by the processor via the memory to implement a method for optimizing testing of a partially symmetric quantum-logic circuit by using wreath products and invariance groups, the method comprising: the system receiving architectural information about a quantum-logic circuit capable of being represented by a function (f); the system evenly dividing a set of inputs of the circuit into a set of non-intersecting first-level blocks, where every first-level block contains a same number of inputs; the system evenly partitioning the set of first-level blocks into a set of non-intersecting second-level blocks, where every second-level block contains a same number of first-level blocks; the system creating a first-level group G1 that comprises a set of first-level indices and a set of one or more first-level permutation operations capable of being performed upon the set of first-level indices; the system defining a second-level group G2 that comprises a set of second-level indices and a set of one or more second-level permutation operations capable of being performed upon the set of second-level indices, where a number of the set of second-level indices equals the number of first-level blocks in each second-level block; and the system generating a first wreath product G1 G2 as a function of the evenly dividing and the evenly partitioning, where is an unrestricted wreath-product operator, and where the first wreath product represents a first invariance group of the function f( ).