1. An interrupt controller, coupled to a plurality of processors, being utilized for routing at least one interrupt request event to at least one of the processors, wherein the interrupt controller comprises: a receiving circuit, for receiving at least one interrupt input; and a controlling circuit, coupled to the receiving circuit, for generating at least one interrupt request event based on the received interrupt input and routing the interrupt request event generated to at least one of the processors; wherein the plurality of processors includes at least a first processor and a second processor, at least the first and second processors being utilized for processing interrupt request event(s); and the controlling circuit may be arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.