1. A memory device comprising: a dynamic random-access memory (DRAM) including a plurality of memory dies, each memory die including a plurality of memory arrays, each memory array including peripheral logic circuits and a configurable logic; and a system element coupled with the DRAM, the system element including a memory controller; wherein the memory controller is to control the configurable logic of the memory arrays to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O (input/output) connections between the memory arrays.