1. An apparatus comprising a block-based processor, the block-based processor comprising: one or more processing cores; and a control unit configured, based at least in part on executing a nullification instruction encoded in a first instruction block, to cause at least one of the processing cores to: obtain an instruction identification for a memory access instruction of a plurality of memory access instructions encoded in the first instruction block, based on a target field of the nullification instruction; nullify the memory access instruction associated with the instruction identification, causing the nullified memory access instruction to not execute; and based on the nullified memory access instruction, execute a subsequent memory access instruction from the first instruction block.