1. A digital data processor comprising: an instruction memory storing instructions each specifying a data processing operation and at least one data operand field; a central processing unit core including: an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand, and at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results; a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including an address generator for generating stream memory addresses corresponding to said stream of an instruction specified sequence of a plurality of data elements, a stream buffer receiving and temporarily storing data corresponding to said stream memory addresses, a stream head register storing a data element of said stream next to be used by said at least one functional unit; wherein said at least one functional unit is responsive to a stream operand instruction to receive at least one operand from said stream head register; and said streaming engine configured to upon occurrence of a fault reading data from the memory identifying said data element triggering said fault, and signaling said fault to said central processing unit core only upon said at least one functional unit receiving said identified data element as an operand.