1. A three-dimensional (3D) non-volatile memory (NVM) array comprising: a plurality of parallel, spaced-apart horizontally-disposed bitline structures that are arranged in a vertical stack, wherein an air-filled gap is defined between each adjacent pair of bitline structures in the vertical stack, and wherein each said bitline structure includes: a mono-crystalline silicon beam; a charge storage layer disposed on said mono-crystalline silicon beam, said charge storage layer comprising a first oxide layer that entirely covers said mono-crystalline silicon beam, and includes a charge trapping material disposed on said first oxide layer; and a plurality of vertically-disposed conductive posts disposed next to the stack such that each said post contacts substantially only a side portion of a corresponding charge storage layer of each of the charge storage layers disposed on each bitline structure.