1. A reconfigurable gate array assembly, comprising: a gate array with a plurality of function blocks connected to one another via controllable wiring, said function blocks being individually controllable, for a respective execution of a specific function; a first interface for data and address communication between said gate array and a processor; a second interface for supplying configurations from a configuration memory, in each case needed to control one of said function blocks and said controllable wiring; and a buffer memory device connected to said second interface for selectively storing configurations from the configuration memory and for direct selective access from said gate array to any configuration stored in said buffer memory device; said buffer memory device having a reconfiguration controller, operating in accordance with a caching strategy, for removing little-used, unused, or last-used configurations from said buffer memory device to create space for new configurations.