1. Method of optimizing a global integrated circuit layout comprised of a number of polygons having a predetermined geometrical relation relative to each other, comprising: providing an initial global integrated circuit layout; assessing local quality numbers, each as a function of a local pattern of shapes in said initial global integrated circuit layout; aggregating approximated functions of said local quality numbers, to derive an integral quality number associated to said initial global integrated circuit layout; perturbing said integral quality number by varying said initial global integrated circuit layout; and selecting perturbations that optimize improve the integral quality number, so as to optimize said global integrated circuit layout.