1. A computer-implemented method, comprising: creating, by a memory management of a computing device, a page table (PT) hierarchy associated with a thread to be run on a processor of the computing device; collecting, by a scheduler of the computing device, access bit information from the PT hierarchy associated with the thread, wherein the access bit information includes any access bits in the PT hierarchy that are set by a memory management unit (MMU) of the processor to identify a page of memory accessed by the thread; determining, by the scheduler, memory access statistics for the thread; and utilizing, by the scheduler, the memory access statistics for the thread in a determination of whether to migrate the thread to another processor.