1. A method for performing an efficient execution of a cryptographic operation comprising: receiving, data upon which the cryptographic operation is to be performed by a computer system being configured with dual-mode cryptographic processing capabilities, wherein the computer system includes a host central processing unit (CPU) and a cryptographic hardware accelerator coupled to the host CPU; dividing, by the CPU, the received data into a plurality of blocks with a block size according to the block size of a respective cryptographic algorithm being employed, wherein the cryptographic operation, in accordance with the configured dial-mode cryptographic processing capabilities, is performed on at least one of the plurality of blocks by the cryptographic hardware accelerator and is performed on at least another of the plurality of blocks by the CPU in a following sequence as directed by a scheduler running on the CPU: offloading, by the CPU, performance of the cryptographic operation on a first block of the plurality of blocks to the cryptographic hardware accelerator; and subsequently, for each remaining subsequent block of the plurality of blocks; requesting, by the CPU, state information associated with the availability of the cryptographic hardware accelerator including at least a resource utilization; when the state information satisfies a predetermined condition of the availability, then offloading, by the CPU, performance of the cryptographic operation on the remaining subsequent block to the cryptographic hardware accelerator; when the state information does not satisfy the predetermined condition of the availability, then performing, by the CPU, the cryptographic operation on the remaining subsequent block by invoking a native hardware supported cryptographic instruction on the remaining subsequent block rather than waiting for the availability of the cryptographic hardware accelerator to facilitate the efficient execution of the cryptographic operation.