1. A branch prediction circuit for performing branch prediction of fetched instructions in a processor, comprising: a first branch predictor configured to: predict a first branch prediction of a conditional branch instruction in an instruction queue; and update a first branch prediction history register based on the first branch prediction for the conditional branch instruction; a forwarding circuit configured to forward the first branch prediction for the conditional branch instruction to a second branch prediction history register as a speculative prediction; and a second branch predictor configured to predict a second branch prediction of the conditional branch instruction in the instruction queue based on the second branch prediction history register including the speculative prediction.