1. An integrated circuit, comprising: at least one memory module; a first bus having a first memory coherency protocol for managing data transfers therein; a first plurality of processors operably connected to said first bus; a second bus having said first memory coherency protocol for managing data transfers therein; a second plurality of processors operably connected to said second bus; a switch operably connected to said memory; a first controller for operably connecting said first bus to said switch, thereby establishing a second level of coherency using a second memory coherency protocol; and a second controller for operably connecting said second bus to said switch, thereby establishing a second level of coherency using said second memory coherency protocol.