1. A data processor with speculative instruction fetching for use with an external memory system, the data processor comprising: a programmable register storing a first number representative of a maximum number of unresolved branch instructions beyond which said data processor may not fetch instructions; a branch prediction unit coupled to said programmable register, said branch prediction unit generating a fetch address responsive to a sequence of programmed instructions regardless of the first number, said branch prediction unit storing a completion signal representative of a number of unresolved branch instructions, said branch prediction unit asserting a control signal if said completion signal is representative of a number of unresolved branch instructions less than or equal to said first number, said branch prediction unit de-asserting said control signal if said completion signal is representative of a number of unresolved branch instructions greater than said first number; a cache memory storing a plurality of insreactions to be executed by the data processor, the cache memory outputting an instruction indexed by the fetch address if the instruction is stored in the cache memory regardless of the first number, an execution unit coupled to the cache memory, the execution unit executing the instruction indexed by the fetch address if the instruction is stored in the cache memory regardless of the first number; and an instruction fetch circuitry coupled to said branch prediction unit, said instruction fetch circuitry fetching the instruction from an external memory system if said branch prediction unit asserts said control signal and if the instruction is not stored in the cache memory.