1. A microprocessor, comprising: execution units, configured to resolve conditional branch instructions; a plurality of call/return stacks (CRS); and a fetch unit, coupled to the plurality of call/return stacks (CRS), configured to fetch a call or return instruction, the fetch unit further configured to determine whether a state exists, wherein said state comprises that the call or return instruction is the first call or return instruction fetched by the fetch unit after it has fetched a conditional branch instruction that has yet to be resolved by the execution units, the fetch unit further configured to copy a contents of a current one of the plurality of CRS to another one of the plurality of CRS and designate the other one of the plurality of CRS as the current one of the plurality of CRS, if said state exists; wherein after the fetch unit determines whether the state exists, and if said state exists, copies and designates: if the call or return instruction is a call instruction, the fetch unit pushes a first return address onto the current one of the plurality of CRS and fetches an instruction at a target address specified by the call instruction, wherein the first return address is an address of a next sequential instruction after the call instruction; and if the call or return instruction is a return instruction, the fetch unit pops a second return address from the current one of the plurality of CRS and fetches an instruction at the second return address.