1. A processing device, comprising: an execute processor configured to execute data processing instructions, the execute processor comprising an execute processor input register file with input registers; and an access processor configured to be coupled with a memory system to execute memory access instructions; wherein the memory access instructions are executed by the access processor in response to determining that an input register is available; wherein the execute processor and the access processor are logically separated units and a data processing instruction is executed as soon as all operands for the data processing instruction are available in the input registers, each operand directly transferred from the memory system to a targeted input register of the execute processor input register file; wherein an input register address for each targeted input register is directly transferred from the access processor to the execute processor; and wherein the access processor controls scheduling of read operations from the memory system for the execute processor by controlling all operand transfers to the input registers.