1. A processor comprising: a plurality of branch predictors, wherein each branch predictor is configured to produce and provide a prediction, a confidence level and an override signal, each override signal from each branch predictor being determined uniquely from other override signals of other branch predictors, and wherein each override signal from each branch predictor comprises an independent override signal produced using an independent override logic associated with each branch predictor; and a branch prediction control circuit configured to generate a branch prediction based on the prediction, the confidence level and the override signal from each predictor, wherein the override signal of a particular predictor results in one of (i) the prediction of the particular predictor being accepted by the processor regardless of the confidence levels of the other predictors and the confidence level of the particular predictor and (ii) the prediction of the particular predictor not being accepted by the processor regardless of the confidence level of the particular predictor.