1. A processor, comprising: an interface for receiving an instruction comprising a memory segment identifier corresponding to a memory segment and further comprising a memory segment mask, wherein the memory segment mask comprises a plurality of mask bits corresponding to a plurality of memory locations in the memory segment, and wherein each mask bit indicates if a corresponding memory location is to receive a data unit; a first digital circuit configured to select the memory segment based on the memory segment identifier; and a second digital circuit configured to select one or more memory locations from the memory locations in the memory segment based on the mask bits of the memory segment mask; a third digital circuit configured to determine, based at least in part on the instruction, a register count, wherein the register count indicates a number of data units to be loaded into the selected one or more memory locations; a fourth digital circuit configured to load the data units into the selected one or more memory locations.