1. An apparatus for packet processing in a switching network comprising: processing circuitry coupled to memory arrays and receiving circuitry; the receiving circuitry being operable to receive packet headers vectors wherein each packet header vector comprises a plurality of packet header words; the processing circuitry operable to produce packet match operations; the processing circuitry operable to produce actions that modify at least one of the packet header words based on the packet match operations; wherein the processing circuitry comprises at least one processor for each packet header word; wherein the at least one processor for each packet header word perform the actions that modify the at least one packet header word; wherein the at least one processor for each packet header word receives instructions from an instruction word; wherein the at least one processor for each packet header word performs an operation responsive to the instruction word; wherein a VLIW instruction word comprises all of the instruction words.