1. A system for reducing the floating point register file reads during an iterative loop on a processor, comprising: a processor including a floating point unit having a floating point register, and one or more source registers, the processor selectively executing iterative loops; and a register read monitor that compares a source register address value with a current value generated from one iteration of a loop, and upon determining that the value in the source register is the same as the current generated value, the monitor inhibiting a floating point register file read of the equal value from the one or more source registers.