1. A device, comprising: a core module; a core bus coupled to the core module; and a bus translator coupled to the core module via the core bus, wherein the bus translator is configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus, wherein the core module comprises a pattern-recognition processor, wherein the pattern recognition processor comprises: a decoder having an input configured to receive a data stream to be searched; and a plurality of feature cells coupled to the row decoder, wherein each of the plurality of feature cells comprise a plurality of memory cells each addressable by a conductor coupled to an output of the decoder.