1. A programming method for a nonvolatile memory device comprising multi-level memory cells (MLCs) arranged in a plurality of physical pages (PPs), each PP being respectively associated with one of N word lines (WLs) disposed in a consecutive arrangement order, the MLCs being further arranged in a plurality of logical pages (LPs), wherein each PP comprises a Most Significant Bit (MSB) LP and a Least Significant Bit (LSB) LP, the method comprising: performing a LSB programming operation programming all the LSB LPs, and thereafter performing a MSB programming operation programming all the MSB LPs, wherein during the LSB programming operation a selected MLC connected between a selected word line and selected bit line is programmed to a negative intermediate program state.