1. A method of data processing in a processing unit, including a processor core, an upper level cache memory, a lower level cache memory, and a memory storage, the method comprising: in response to the processor core executing a data cache block touch (DCBT) instruction, identifying a cache block that may be accessed; and in response to the DCBT instruction: determining an effective address in memory storage that contains the cache block from a first subfield of the DCBT instruction, determining a specific portion of data in the cache block to be prefetched from a second subfield of the DCBT instruction, prefetching only the specific portion of the cache block at the effective address to an entry in the lower level cache memory, and denoting a remainder portion of the cache block that was not prefetched as invalid.