1. A system comprising: one or more computing devices configured to model a main memory that is to be accessed by a first circuit design under test; and an emulator configured to: communicate with the one or more computing devices; emulate the first circuit design under test; emulate a cache memory that provides a subset of data stored by the main memory; perform a part of an emulation process for emulating the first circuit design under test; and during the part of the emulation process, update one or more stored values in the cache memory to synchronize the subset of the data between the cache memory and the main memory.