1. An apparatus for emulating a hardware design, comprising: a data array memory; an intracluster crossbar; a plurality of processors in a heterogeneous cluster coupled to the intracluster crossbar; a data fetch processor of the plurality of processors configured to, within one instruction cycle time, retrieve data from the data array memory, and write the data to the intracluster crossbar; a data store processor of the plurality of processors configured to, within the one instruction cycle time, select the data from the intracluster crossbar, and store the data in the data array memory; and an intercluster memory configured to store control bits used to select the data from the intracluster crossbar and from an intercluster crossbar operatively connected to the intercluster memory.