1. An apparatus comprising: a first set of five NMOS fingers; a second set of five NMOS fingers; an N-well located between said first set of five NMOS fingers and said second set of five NMOS fingers, said N-well comprising a plurality of N regions and a plurality of P regions wherein one of said plurality of N regions is electrically connected to a plurality of drains associated with said first set of five NMOS fingers and another of said plurality of N regions is electrically connected to a plurality of drains associated with said second set of five NMOS fingers; a P-well tap surrounding said first set of five NMOS fingers, said second set of five NMOS fingers and said N-well.