1. A programmable memory system for enabling one or more processor devices access to shared memory in a computing system, said shared memory comprising one or more memory storage structures having addressable locations for storing data for said one or more processor devices, said system comprising: one or more first logic devices associated with a respective said one or more processor devices, each one or more first programmable logic devices for receiving physical memory address bits, each one or more first logic devices programmed to generate a respective memory structure select signal upon receipt of address bit values at pre-determined physical memory address bit locations: a second logic device responsive to each said respective select signal for generating an address signal used for selecting a memory storage structure for processor access, wherein each processor device of said computing system enables memory storage access distributed across said one or more memory storage structures, and, means for receiving unselected bit values of said received physical memory address for generating an offset bit vector signal used to enable processor device access to memory locations within a selected memory storage structure, wherein each said respective select signal comprises an asserted bit value output, said second logic device for concatenating one or more said asserted bit value outputs from said associated first logic devices to generate a bit vector for use as said address signal used to select a memory storage structure.