1. A computer-implemented method for dynamically load balancing instruction execution in a single-instruction multiple-data (SIMD) architecture with heterogeneous processing engines, comprising: computing, prior to assigning instructions included in a set of unassigned instructions, a first initial weighted instruction count associated with a first processing engine of the heterogeneous processing engines and a second initial weighted instruction count associated with a second processing engine of the heterogeneous processing engines, based on a set of expected latencies associated with the set of unassigned instructions, wherein a dual-issue instruction that is included in the set of unassigned instructions and that is configured to specify the first processing engine as a target is assigned a weighted value of zero in both the first initial weighted instruction count and the second initial weighted instruction count, wherein only the first processing engine is configured to execute instructions of a first single-issue type included in the set of unassigned instructions, wherein only the second processing engine is configured to execute instructions of a second single-issue type that is different than the instructions of the first single-issue type included in the set of unassigned instructions, and wherein the dual-issue instruction is executable in parallel for multiple threads in a SIMD thread group by the first processing engine and the second processing engine; assigning the instructions in the set of unassigned instructions to the first processing engine or the second processing engine based on the first initial weighted instruction count and the second initial weighted instruction count; computing a first weighted instruction count for the instructions assigned to the first processing engine that is proportional to an execution latency corresponding to instructions that are assigned to the first processing engine; computing a second weighted instruction count for the instructions assigned to the second processing engine that is proportional to an execution latency corresponding to instructions that are assigned to the second processing engine; determining that the first weighted instruction count associated with the first processing engine is greater than the second weighted instruction count associated with the second processing engine; overriding the target specified by the dual-issue instruction; assigning the dual-issue instruction for execution by the second processing engine based on the first weighted instruction count being greater than the second weighted instruction count; receiving a control instruction; extracting a target address from the control instruction; and reading and executing one or more instructions starting at the target address.