1. A physical design automation system for producing an optimized cell placement for an integrated circuit chip, comprising: a decomposer for decomposing a placement optimization methodology into a plurality of cell placement optimization processes; a plurality of parallel processors for performing said optimization processes simultaneously on input data representing said chip; a recomposer for recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and a controller for analyzing a fitness of said optimized cell placement and controlling the parallel processors to selectively repeat performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion; in which the controller identifies low fitness areas of said optimized placement and selectively assigns the processors to repeat performing said optimization processes on said low fitness areas respectively.