1. A static storage cell, comprising: first and second cross-coupled inverters respectively formed of first and second field effect transistors and first and second resistor elements connected in series thereto; a first circuit node between the first field effect transistor and the first resistor element being connected to a gate terminal of the second field effect transistor; a second circuit node between the second field effect transistor and the second resistor element being connected to a gate terminal of the first field effect transistor; said first and second circuit nodes being respectively connected to base terminals of respective second and first hot electron transistors (HETs), collector terminals of which being connected to respective second and first bit lines and emitter terminals of which being connected to an addressing word line; the first and second hot electron transistors being of a tunnel emission type and each having an emitter layer, an insulator layer, a base layer, and a collector layer; said first and second field effect transistors respectively having source and drain regions which are inserted in a body of doped semiconductor material, a channel region lying between them at which an inversion layer forms, and a gate electrode covering said channel region; the first and second hot electron transistors being combined with te respective first and second field effect transistors such that the HET transistor emitter layer is the inversion layer in the channel region of the field effect transistor, the HET base layer is the gate electrode of the field effect transistor, the insulator layer is disposed between the base layer and the channel region, collector layer has a terminal connected to the respective bit and a source terminal connected to the source region of the field effect transistor forming a terminal of said emitter of the respective hot electron transistor connected to said addressing word line.