1. A nonvolatile semiconductor memory, comprising: a plurality of sectors, each having a plurality of nonvolatile memory cells and at least one local bit line connected to the memory cells; at least one write global bit line, wired commonly to said sectors, that transfers write data to said memory cells during write operation and transfers verify data from said memory cells during verify operation after write operation and after erase operation; at least one read global bit line, wired commonly to said sectors, that transfers read data from said memory cells during read operation; a plurality of switch circuits, formed in said sectors respectively, that connect said local bit line to said write global bit line or said read global bit line according to operation modes; a plurality of global bit line pairs, each configured of one write global bit line and one read global bit line; and a plurality of local bit line pairs, each configured by a pair of said local bit lines, wherein said global bit line pairs are wired along said local bit lines and are wired in correspondence with said local bit line pairs, respectively.