1. A processing unit, comprising: a processor core including: an instruction sequencing unit that orders instructions for execution; and one or more execution units that execute a code segment including a memory transaction and a non-transactional memory access instructions preceding the memory transaction in program order, wherein: the memory transaction includes at least an initiating instruction, a transactional memory access instruction, and a terminating instruction; the initiating instruction has an implicit barrier that imparts the effect of ordering execution of the transactional memory access instruction within the memory transaction with respect to the non-transactional memory access instructions preceding the memory transaction in program order; and transactional memory tracking logic, coupled to the processor core, that tracks a transaction footprint of the memory transaction for conflicts; wherein the processor core executes the transactional memory access instruction within the memory transaction concurrently with at least one of the non-transactional memory access instructions preceding the memory transaction in program order and enforces the barrier implicit in the initiating instruction following execution of the initiating instruction only if the memory transaction commits successfully to a shared memory system coupled to the processing unit.