1. A dynamically testable programmable circuit array having a plurality of input terminals, each input terminal adapted to receive one of a plurality of input signals, comprising: (a) input buffer means, having a plurality of output terminals and inverted output terminals, said input buffer means operatively connected to said input terminals, for outputting equivalent input signals and inverted input signals, said equivalent input signals forming a first output group and said inverted input signals forming a second output group; (b) programmable product array means, operatively connected to the output terminals and the inverted output terminals of said input buffer means thereby receiving said equivalent input signals and said inverted input signals, for generating a plurality of product terms; (c) programmable sum array means, operatively connected to said programmable product array means, for combining said plurality of product terms to generate a plurality of sum terms, each of said plurality of sum terms being an output of said dynamically testable programmable circuit array; and (d) test means, having a first and second control input terminal adapted to receive a first and second control signal, operatively coupled to the output terminals of said input buffer means, for causing one of said output groups to have a predetermined logic state, said test means including; (i) a plurality of first circuit component means, each of said first circuit component means operatively connected to a respective output terminal and inverted output terminal of said input buffer means, and further, each of said first circuit component means which is operatively connected to a respective output terminal of said input buffer means being operatively connected to said first control input terminal, and each of said first circuit component means which is operatively connected to a respective inverted output terminal of said input buffer means being operatively connected to said second control input terminal, for causing each of said output terminals and each of said inverted output terminals of said input buffer means to be forced to a first predetermined logic level in response to said first and second control signals, respectively; and (ii) second circuit component means, operatively connected to one of said control input terminals, for forcing a second predetermined logic level to the respective control input terminal in the absence of the respective control signals, said second predetermined logic level partially enabling the respective inputs of said programmable product array means.