1. A data processing apparatus comprising: an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a Boolean function prior to an arithmetic function; a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit; a second data source supplying a second multibit digital signal to said second data input of said arithmetic logic unit; a third data source supplying a third multibit digital signal; a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal.