1. A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation, comprising: a pre-charge circuit for pre-charging a global bitline to restore the global bitline, wherein the global bitline is initialized to a high state; a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices; a keeper circuit coupled to the global bitline, wherein the keeper circuit provides feedback to maintain a state of the global bitline; the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline; and an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit, wherein the gate of the effective pull-up transistor is coupled to the sleep mode control circuit and a drain of the effective pull-up transistor is coupled to the logic function circuit.