1. An apparatus, comprising: a first array of capacitances coupled to a common node, each successive capacitance of the first array having a capacitance value that is less than a capacitance value of a previous adjacent capacitance, according to a predetermined non-binary numerical pattern; and a second array of capacitances coupled to the common node, each capacitance of the first array having an associated capacitance within the second array with an approximately equivalent capacitance value, the first array and the second array in combination arranged to determine a digital approximation for an analog input value.