1. A method of providing fault tolerance in a massively parallel computer system which includes a plurality of parallel processors interconnected in 3 dimensions to render the computer system tolerant to hardware failures comprising: providing the computer system with extra groups of redundant standby processors interconnected in 3-dimensions; designing the computer system so that the extra groups of redundant standby processors can be switched to operate in place of a group of processors in 3 dimensions of the computer system which experiences a hardware failure.