1. In an information system for processing, storage and transmission of data, the improvement characterized by: providing a finite field serial-serial multiplication/reduction structure wherein an initial delay and clock-cycle are inherently independent of word length, wherein input operands are serially entered one digit at a time and the output result is computed serially one digit at a time, wherein a digit can consist of one bit or a group of bits, and wherein these are achieved without the need for extra pipeline registers, irregular adder structure, serial-in-parallel-out register for the input operand, and parallel-in-serial-out register for the output operand.