1. A method of data processing in a processor, said method comprising: in the processor, holding operands of a plurality of threads in a shared first level register file having a lower access latency and holding operands of the plurality of threads in a shared second level register file having a higher access latency; at dispatch of an instruction specifying a source logical register, a mapper in the processor initiating a swap of a first operand associated with the source logical register that is held in the second level register file with a second operand in the first level register file; and in response to a signal from the mapper, issuing the instruction for execution.