1. A multi-threaded processor comprising: a thread scheduler configured to receive a thread, allocate one or more virtual registers mapped to one or more internal addresses in a unified memory space, and store content of thread registers associated with the thread in the one or more mapped internal addresses in the unified memory space; a unified register file coupled to the thread scheduler, the unified register file including the unified memory space that stores the thread registers; and a processing unit coupled to the unified register file and configured to retrieve content of thread registers from the internal addresses in the unified memory space based on the virtual register mapping.