1. An information processing method using an information processing apparatus, wherein the information processing apparatus comprises: a plurality of cores; a shared resource that can be shared by the plurality of cores; and a local register that stores configuration information peculiar to each of the plurality of cores, the shared resource is provided independently of the plurality of cores, the local register is provided in each of the plurality of cores, the shared resource comprises a memory protection circuit that protects a shared memory from invalid access by each of the plurality of cores, each of the plurality of cores comprises a local memory protection circuit that evaluates whether or not the corresponding core can access the shared memory prior to evaluation by the memory protection circuit, each of the local memory protection circuit comprises: a second protected area configuration register storing protected area information relating to a protected area of the shared memory; a second access evaluation circuit provided to correspond to the second protected area configuration register; and a rewrite control circuit that rewrites the protected area information stored in the second protected area configuration register, the memory protection circuit comprises: a first protected area configuration register storing the protected area information relating to the protected area of the shared memory; and a first access evaluation circuit that evaluates whether or not the core is allowed to access the shared memory, and the information processing method comprises: referring, in each of the local memory protection circuits, by the second access evaluation circuit, to the second protected area configuration register and evaluating whether or not each of the plurality of cores is allowed to access the shared memory based on the memory access information and the protected area information; evaluating, in the memory protection circuit, when the memory address included in the memory access information is not included in the memory area stored in the second protected area configuration register, by the first access evaluation circuit, whether or not the core is allowed to access the shared memory; and rewriting, by a rewrite control circuit, protected area information stored in the second protected area configuration register by using protected area information relating to a protected area of the shared memory stored in the first protected area configuration register included in the memory protection circuit.