1. A method of data processing in a data processing system having a system memory controlled by a memory controller, said method comprising: the memory controller receiving a plurality of data prefetch requests from multiple processor cores in the data processing system, the plurality of prefetch load requests including a data prefetch request issued by a particular processor core among the multiple processor cores; in response to receipt of the data prefetch request, the memory controller providing a coherency response indicating an excess number of data prefetch requests; and in response to the coherency response, the particular processor core reducing a rate of issuance of data prefetch requests.