1. A memory device comprising: a block of memory cells that is a random access memory with multiple ports, the block of memory cells partitioned into a plurality of subunits that each has only a single port; a cache coupled to the block of memory cells, wherein: the cache is adapted to store data; the cache is adapted to handle a plurality of accesses to the subunits of memory cells without a conflict such that the memory device appears to be a random access memory to the plurality of accesses; the cache contains validity data that indicates whether data stored in the cache is valid; and a read command is able to be performed without latency relative to a write command; and a bank-conflict resolution logic (BCR) that is adapted to: test validity data of the data stored in the cache; and write a data word of the write command to a memory location of a memory bank in the memory partition if the validity data stored in the cache indicates that the data stored in the cache is invalid; and wherein: the block of memory cells is a memory partition; and the subunit of memory cells is a memory banks.