1. A method for operating a highly integrated wavefront array processor having n.times.m processor cells arranged in n horizontal rows and m vertical columns with each processor cell connected to each of its horizontally and vertically adjacent processor cells, comprising the steps of shifting an instruction code in horizontal and vertical directions between adjacent processor cells from one processor cell to the respective next horizontally and vertically adjacent processor cell, and shifting a first group of n row selection bits and a second group of m column selection bits through the processor cell array to release certain processor cells for the execution of said instructions.