1. A method of operating a digital system having a processor and associated translation lookaside buffer (TLB), comprising the steps of: executing a plurality of program tasks within the processor; initiating a plurality of memory access requests in response to the plurality of program tasks; caching a plurality of translated memory addresses in the TLB responsive to the plurality of memory access requests; incorporating a task identification value with each translated memory address to identify which of the plurality of program tasks requested the respective translated memory address; incorporating a shared indicator with each translated memory address to indicate when a translated memory address is shared by more than one of the plurality of program tasks; and invalidating a portion of the plurality of translated memory address in the TLB in a manner that is qualified by the shared indicator.