1. A processing unit for a data processing system including a shared memory system, the processing unit comprising: a processor core; a cache memory coupled to the processor core, wherein the cache memory includes: a cache array; a directory of contents of the cache array, wherein entries in the cache array and directory have a set associative organization and are grouped in multiple congruence classes; and transactional memory tracking logic that tracks a transaction footprint including one or more cache lines in the cache array accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core, said transactional memory transaction logic comprising: a directory structure comprising entries for tracking the cache lines within the load and store footprints of memory transactions; each entry comprising: an address tag field, a congruence class (CC) field, a way number field for specifying the particular way of the identified congruence class that holds directory information for the specific cache line in the transaction footprint, a load valid (LV) field including a bit indicating whether the cache line is part of a load footprint of a memory transaction, and a store valid (SV) field including a bit indicating whether the cache line is part of a store footprint; one or more comparator devices, each comparator device comparing a congruence class field of a real address of a transactional or non-transactional memory access request received with the congruence class indicated by the congruence class field of a respective associated TM directory entry and generating a comparator match vector output to identify the set of cache lines in one or more transaction footprints that are at risk of being replaced from the congruence class accessed by the memory access request; a load mask generator for receiving the match vector output and the way number fields and LV fields of TM directory entries, and generating a load mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in LV field, the load mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s); and a store mask generator for receiving the match vector output and the way number fields and SVfields of TM directory entries, and generating a store mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in SV field, the store mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s); wherein the cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory, forms based on the load mask or store mask a working set of ways in the congruence class containing one or more cache lines within the transaction footprint and updates a replacement order of the cache lines in the congruence class, wherein the update to the replacement order promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set.