1. A data processing apparatus comprising: processing circuitry configured to execute a sequence of instructions, each instruction having an associated memory address and said sequence of instructions including cacheable instructions whose associated memory addresses are within a cacheable memory region; an instruction cache configured to store cacheable instructions for access by the processing circuitry, said instruction cache having a data storage comprising a plurality of cache lines and a tag storage comprising a plurality of tag entries, each cache line configured to store instruction data specifying a plurality of cacheable instructions, and each tag entry configured to store an address identifier for the instruction data stored in an associated cache line, the instruction cache further comprising valid flag storage configured to identify for each cache line whether that cache line is valid; instruction cache control circuitry configured to store within a selected cache line of the data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage; the instruction cache control circuitry further being configured to receive data of a predetermined data type, said predetermined data type not being instruction data for a plurality of cacheable instructions; the instruction cache control circuitry being responsive to receipt of said data of a predetermined data type to store said data in a chosen cache line of the data storage of the instruction cache, but to identify the chosen cache line as invalid within the valid flag storage; and the instruction cache control circuitry further comprising control state circuitry configured to maintain a record of the chosen cache line in which said data of a predetermined data type has been written, and upon receipt of a request for that data to provide that data from the instruction cache, wherein said data of a predetermined data type is instruction data for non-cacheable instructions.