1. A falling edge controller comprising: A. a controller having an inverted TCK input, a TMS input, a shift register control output, an update register control output, and a shift output; B. a shift register having a TDI input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO output; C. an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and D. address circuitry having address inputs coupled to the address outputs, and having an enable output.