1. A cryptographic processor comprising: a processing circuit configured to perform a round function of an iterated cryptographic algorithm; a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm; a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration; wherein the transformation circuit is implemented using a circuit camouflage technique.