1. A method for addressing a memory comprising: selecting a nanoscale wire from a plurality of nanoscale wires through a first set of microscale inputs; associating a code to the selected nanoscale wire through a second set of microscale inputs; repeating the selecting and associating steps in accordance with a number of nanoscale wires to be programmed; associating memory addresses of the memory to codes associated with the selected nanoscale wires; and selecting memory addresses of the memory by means of the second set of microscale inputs.