1. A programmable integrated circuit comprising: (a) a plurality of programmably configurable logic blocks for carrying out program-defined logic functions; (b) a programmably configurable interconnect network for providing program-defined routing of signals between the plurality of programmably configurable logic blocks, wherein said configurable logic blocks each includes: (a.1) a programmable first memory area for storing a function-defining first set of lookup bits; (a.2) a programmable second memory area for storing a function-defining second set of lookup bits; (a.3) a programmable third memory area for storing a function-defining third set of lookup bits; (a.4) a programmable fourth memory area for storing a function-defining fourth set of lookup bits; (a.5) first select means coupled to the first memory area and responsive to a supplied first plurality of input signals for selecting a subset of the first set of lookup bits in accordance with the first plurality of input signals, wherein the combination of the first memory area and the first select means defines a first lookup table (first LUT); (a.6) second select means coupled to the second memory area and responsive to the supplied first plurality of input signals for selecting a subset of the second set of lookup bits in accordance with the first plurality of input signals, wherein the combination of the second memory area and the second select means defines a second lookup table (second LUT); (a.7) third select means coupled to the third memory area and responsive to a supplied second plurality of input signals for selecting a subset of the third set of lookup bits in accordance with the second plurality of input signals, wherein the combination of the third memory area and the third select means defines a third lookup table (third LUT); (a.8) fourth select means coupled to the fourth memory area and responsive to the supplied second plurality of input signals for selecting a subset of the second set of lookup bits in accordance with the second plurality of input signals, wherein the combination of the fourth memory area and the fourth select means defines a fourth lookup table (fourth LUT); and (a.9) first internal connect means for coupling an output of the second LUT such that said coupled output defines at least one input of said second plurality of input signals, thereby cascading the coupled output of the second LUT to an input of the third and fourth LUT's.