1. A high speed and low power fixed-point multiplier for performing multiplication of an input data multiplicand by a fixed coefficient multiplier, comprising: partial product calculation logic circuitry for dividing the input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying the fixed coefficient for each bit group, and summing partial products included in a corresponding bit group, to thereby generate summed partial products; and adding circuitry for adding the summed partial products of each bit group generated from the partial product calculation logic circuitry, wherein the number of bits of the input data divided by the number of the plurality of bit groups is less than a number of non-zero bits of the fixed coefficient, wherein the partial product calculation logic circuitry includes a partial product calculation unit for each of the plurality of bit groups, wherein independently multiplying the fixed coefficient for each bit group is performed by a corresponding partial product calculation unit for each of the respective bit groups, and wherein the partial product units perform the respective multiplications in parallel.