1. A method of reducing test time for a target programmable logic device (PLD) that includes an array of similar tiles each including similar routing resources, the method comprising: identifying a first set of routing resources present in the target PLD that are not to be used in implementing user designs; supplying a device model for the target PLD to one or more users, the device model specifying as inaccessible the first set of routing resources; and generating a set of test patterns for the target PLD that do not test the first set of routing resources.