1. A processor, comprising: a front end including: a first logic to decode an instruction; a second logic to identify a multiplier to be multiplied with a multiplicand based on the instruction and a mathematical mode of the instruction; and a multiplier circuit including: a third logic to apply Booth encoding to multiply the multiplier and multiplicand; a first circuitry including a fourth logic to determine leftmost partial products of multiplying the multiplier and multiplicand using Booth encoding, the first selector circuitry including a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier; a second circuitry including a fifth logic to determine rightmost partial products of multiplying the multiplier and multiplicand using Booth encoding, the second selector circuitry including a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier; and a sixth logic to selectively enable selectors of the first circuitry and the second circuitry to find partial products based upon the mathematical mode of the instruction.