1. A microcontroller system comprising: a microcontroller having a plurality of cores, each of the plurality of cores having an interrupt controller, an operating frequency and voltage; and a common peripheral electrically coupled to each of the plurality of cores by a common interrupt line that connects directly between the common peripheral and each of the plurality of cores such that a common interrupt is received in parallel at each of the plurality of cores, the interrupt controller of each of the plurality of cores handling the common interrupt received in parallel at each of the plurality of cores from the common peripheral over the common interrupt line such that a first task signaled by the common interrupt is handled in parallel with a second task signaled by the common interrupt, wherein the first task is a real time task and the second task is a non-real time task, by having the first task signaled by the common interrupt running on a first one of the plurality of cores while the second task signaled by the common interrupt is running in parallel on a second one of the plurality of cores, wherein the operating frequency and voltage of the first one of the plurality of cores and the operating frequency and voltage of the second one of the plurality of cores are scaled down relative to a case in which the first task and the second task signaled by the common interrupt are handled by the same core of the plurality of cores to reduce power consumption.