1. A computer-implemented layout design method of a semiconductor integrated circuit, comprising: degenerating, by a processor, a layout netlist extracted from a layout data, to produce a degenerated layout netlist; comparing the degenerated layout netlist with a circuit diagram netlist, to produce a layout circuit association table of a degenerated layout cell and a circuit element; creating a before and after reduction association table based on the layout netlist and the degenerated layout netlist; counting a number of layout elements in a layout cell before the degenerating; comparing the number of layout elements counted and a number of degenerated elements; and creating a mapping information associating the layout cell with the circuit element.