1. A method for verifying an error of a programmable logic device capable of changing an arithmetic operation function by changing a combination of a plurality of circuit blocks, the method comprising: a circuit forming step of (a) generating a plurality of net lists corresponding to a plurality of arithmetic operation circuits from same arithmetic operation circuit description information described in a hardware description language by performing logic synthesis using a plurality of synthesis parameters that is different in condition regarding the combination of the plurality of circuit blocks, and (b) writing configuration information generated from the plurality of net lists into the programmable logic device to form the plurality of arithmetic operation circuits that corresponds to the plurality of net lists, shares the arithmetic operation function, differs in the combination of the plurality of circuit blocks, and differs in connection states of the plurality of circuit blocks; an arithmetic operation step of performing an arithmetic operation by each of the plurality of arithmetic operation circuits; and a verification step of verifying arithmetic operation results from the plurality of arithmetic operation circuits by a verification circuit.