1. A multiprocessor system, comprising: a plurality of processors; a lower-level cache; a plurality of higher-level caches coupled to the plurality of processors; wherein each of the plurality of higher-level caches is configured to perform memory accesses through the lower-level cache; a reverse directory coupled to the lower-level cache; wherein the reverse directory includes entries for lines in the plurality of higher-level caches, wherein each entry identifies an associated entry in the lower-level cache.