1. A data processing device comprising: a plurality of CPUs; and a plurality of memories corresponding to the CPUs, wherein when the CPUs issue requests for fetching instruction codes of different addresses from the corresponding memories, the instruction codes are supplied from the corresponding memories to the corresponding CPUs, and wherein when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, the instruction code read from one of the memories by one access to the same address is parallelly supplied to the CPUs.