1. A processor system comprising: a main processor; and a coprocessor connected to the main processor, wherein if the number of instruction execution cycles of an extended instruction executed by the coprocessor is larger than the number of instruction execution cycles of a basic instruction executed by the main processor, a pipeline process for a subsequent instruction retrieved after the extended instruction is stopped at least for a period corresponding to a difference between the number of instruction execution cycles of the extended instruction and the number of instruction execution cycles of the basic instruction.