1. A pipelined processor comprising (a) a pipeline instruction control unit; (b) at least one primary data flow facility having a plurality of inputs and having a subassembly processing a finite number (n) of said inputs in parallel, to process a stream of instructions defined by the instruction control unit; (c) one or more secondary data flow facilities having a plurality of inputs and each said data flow facility having a subassembly processing a greater number (n)+(k-1)(n-1) of said inputs than the finite number of inputs being processed by said primary data flow facility, said secondary data flow facility comprising at least one comparable subassembly similar in function to said subassembly in said primary data flow facility but with a greater number of inputs, whereby said secondary data flow facility can process all the inputs required to emulate the apparent result of processing by said comparable subassembly of the primary data flow facility and process said apparent result together with an additional input; (d) an instruction unit comprising means to detect adjacent instruction groups including: interlocked instruction sequences where on adjacent instruction necessarily must be delayed pending completion of another; adjacent instruction sequences in which one of a group of adjacent instructions requires operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group; and independent adjacent instruction sequences which require unrelated operand inputs; (e) control means connected to said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlocked instruction sequences; wherein said primary data flow facility is a minimum data flow facility equipped to process inputs, and said one or more secondary data flow facilities, in sequence by complexity, are equipped to process (n)+(k-1)(n-1) inputs, where (n) is the number of inputs to said minimum facility, (n) being an integer equal to or greater than 1, and (k) is the facility sequence position number.