1. A method for performing equivalence checking between integrated circuit (IC) designs, comprising: receiving a first IC design and a second IC design for equivalence checking; converting the first IC design and the second IC design into a first data-flow graph and a second data-flow graph, respectively; generating a combining structure by combining the first data-flow graph and the second data-flow graph, wherein the combining structure is in a data-flow graph; and checking if the first and second IC designs are equivalent by applying a formal analysis process to the first data-flow graph, the second data-flow graph, and the combining structure.