1. A data processing system for performing a fuzzy inference operation, comprising: bus means for transferring a plurality of input labels, a plurality of grades, and a plurality of valid bits, each of the plurality of input labels corresponding to one of the plurality of grades and each of the plurality of valid bits corresponding to the plurality of input labels; an input label sorter for receiving the plurality of input labels and the plurality of grades, the input label sorter sorting a first portion of the plurality of grades in a first order based on magnitude, the input label sorter sorting each of the plurality of input labels and storing each of the plurality of input labels in a memory location which corresponds to a one of the first portion of the plurality of grades; a rule bits generating circuit coupled to the input label sorter for receiving the plurality of input labels corresponding to the first portion of the plurality of grades in a second order based on magnitude, the rule bits generating circuit successively comparing each of the plurality of input labels with a first one of a plurality of antecedents of a first rule and selectively asserting a first rule signal each time one of the plurality of input labels corresponds to the first one of the plurality of antecedents of the first rule, the rule bits generating circuit concurrently successively comparing each of the plurality of input labels with a first one of the plurality of antecedents of a second rule and selectively asserting a second rule signal each time one of the plurality of input labels corresponds to the first one of the plurality of antecedents of the second rule; a minimum determination circuit coupled to the rule bits generating circuit to indicate a first minimum value corresponding to the first rule and a second minimum value corresponding to the second rule, the minimum determination circuit indicating the first minimum value when the first rule signal is first asserted and a first corresponding one of the plurality of valid bits is in a first logic state which inhibits determination of the first minimum value and the minimum determination circuit indicating the second minimum value when the second rule signal is first asserted and a second corresponding one of the plurality of valid bits is in a second logic state which inhibits determination of the second minimum value; a maximum determination circuit coupled to the minimum determination circuit, the maximum determination circuit asserting an enable signal when one of the first minimum value and the second minimum value is asserted; and latch means coupled to the maximum determination circuit for receiving the enable signal and coupled to the bus means for selectively receiving the plurality of grades, the latch means latching a one of the plurality of grades when the enable signal is asserted, wherein a last one of the plurality of grades latched by the latch means is a first maximum output value.