1. An address translation register control device in a multiprocessor system including a plurality of processors, said address translation register control device comprising: a plurality of address translation registers commonly used by said plurality of processors for address translation of a virtual address within a virtual address space into a physical address within a physical address space, said virtual address space being partitioned into a plurality of groups of virtual addresses, each one of said groups of virtual addresses including a plurality of partial spaces of equal size; and management circuit, responsive to a request from one of said plurality of processors, for assigning said one processor to one of said address translation registers, said management circuit including a processor data storage means for storing processor information indicative of which of said processors are currently assigned to use each of said address translation registers, and a partial space data storage means for storing partial space information indicative of said partial spaces corresponding to said address translation registers, said management means assigning one of said address translation registers to said one processor by storing said processor information in said processor data storage means and by storing said partial space information in said partial space data storage means.