1. A method for working around a processing flaw in a processor, the method comprising: fetching at least one instruction from a memory location; decoding the at least one instruction; performing, by a set of opcode compare logic associated with one of an instruction decode unit and a set of global completion tables, an opcode compare operation with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding; marking, based on the opcode compare operation, the instruction with a pattern, wherein the pattern indicates that the instruction is associated with a processing flaw, wherein the pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.