1. An integrated circuit having power management comprising: processing circuitry for executing instructions; at least one memory array coupled to the processing circuitry for providing data to the processing circuitry; and control circuitry coupled to the at least one memory array, the control circuitry removing electrical connectivity of the at least one memory array to a supply voltage terminal by firstly disabling all accesses to the at least one memory array and secondly removing electrical power to all of the at least one memory array to reduce leakage current in the at least one memory array.