1. A microprogrammable processor capable of accessing unused portions of an external, single-port control store as fast data memory, comprising: an internal control store which stores microinstructions that control operation of the microprogrammable processor; a microsequencer operable to control program flow and to access microinstructions from either said internal control store or the external control store, said microsequencer further operable to access said internal control store at the same time as the microprogrammable processor accesses said external control store as fast data memory; a first internal communication bus that provides said microsequencer electrical communication to said internal control store; a second internal communication bus that provides said microsequencer communication to said external control store, said second internal communication bus further operable to allow the microprogrammable processor to access said external control store as fast data memory; a multiplexer in electrical communication with said second internal communication bus, said multiplexer configured to select operation of said second internal communication bus; a detection circuit operable to control operation of said multiplexer, said detection circuit operable to detect an access by said microsequencer to said internal control store, said detection circuit further operable to configure said multiplexer to allow said second internal communications bus to provide said microprogrammable processor access to said external control store as fast data memory; a memory address unit operable to access data from an external control store when said microsequencer accesses microinstructions from said internal control store; a memory boundary address register programmable to configure portions of external control store as fast data memory; an adder coupled to said memory address unit for generating a physical data address in said external control store from a logical data address provided in said microinstruction, said adder operable to add the contents of said memory boundary address register to said logical data address when said detection circuit detects an access by said memory address unit to microinstructions stored in said internal control store; and a boot loader operable to load microinstructions from external non-volatile storage memory to control store.