1. A processor, comprising: a front end; and an allocation unit including circuitry to: receive a logical move instruction through the front end with a source logical register as a source parameter and a destination logical register as a destination parameter, the source logical register assigned to a source physical register and the destination logical register assigned to a destination physical register; assign a first value of the source logical register to the destination logical register; and maintain a second value in the destination physical register before and after the assignment of the first value of the source logical register to the destination logical register.