1. An integrated circuit having a cell arrangement, the cell arrangement comprising: at least one magnetoresistive memory cell; a first line providing a first line current; a second line providing a second line current; and a controller controlling the application of the first line current and the second line current such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that a transition time of the magnetic field is shorter than a time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state.