1. A processor, comprising: a memory that stores a system management mode value indicative of whether the processor is in a system management mode; a translation address cache comprising a plurality of entries for storing address translations, wherein each of said plurality of entries includes a system management mode identifier; hit logic that compares a lookup address with address translations stored in said plurality of entries of said translation address cache for determining a hit, wherein said hit logic determines a hit only when a corresponding system management mode identifier of an entry matches said system management mode value; entry logic that selects one of said plurality of entries of said translation address cache for storing a determined address translation and that programs a system management mode identifier of the selected entry of said translation address cache to match said system management mode value; and flush logic that flushes only those address translations stored in said translation address cache that have a corresponding system management mode identifier matching said system management mode value in response to either entering said system management mode or exiting said system management mode.