1. Cache circuitry for use in a data processing apparatus, the cache circuitry comprising: a cache storage comprising a plurality of cache lines for storing data values for access by a device of the data processing apparatus; a plurality of slots, each slot arranged to store attributes associated with a pending access request issued by said device, each pending access request being either a write access request or a read access request; identifier circuitry for maintaining a record of identifiers that are available to associate with pending access requests to uniquely identify each pending access request; control circuitry, responsive to an access request issued by said device, to accept that access request as a pending access request by allocating one of said plurality of slots to that access request, obtaining from the identifier circuitry one of said identifiers to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier; the control circuitry being arranged to perform a check procedure to determine, for each pending access request, whether that access request is allowed to proceed; a write access buffer comprising a plurality of write entries; for a speculative pending write access request seeking to write data, the control circuitry being responsive to a determination that that pending access request is allowed to proceed to transfer from the allocated slot to one of said write entries the identifier associated with that access request and at least the attributes associated with that access request that are required to enable the access request to be completed, and to then free the allocated slot for allocation to a subsequent access request; the write access buffer being responsive to a speculative confirmed signal from the device specifying said identifier, to output the attributes from the write entry having that identifier to store circuitry used to complete the access request.