1. A microprocessor, comprising: a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource; wherein a first core of the plurality of processing cores is configured to: encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction; and in response to encountering the architectural instruction: provide the value to each of the other of the plurality of processing cores; and update the respective architecturally-visible storage resource of the first core with the value; and wherein each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction; wherein the architecturally-visible storage resource comprises an x86 architecture memory type range register (MTRR); wherein the MTRR comprises an x86 architecture variable range MTRR comprising a base register and a mask register, wherein the mask register includes a valid bit; wherein the first core, in response to encountering the architectural instruction, is further configured to: if the architectural instruction specifies the mask register: provide a current value of the base register of the first core to each of the other of the plurality of processing cores and set a flag readable by each of the other of the plurality of processing cores; if the architectural instruction specifies the base register and the valid bit of the mask register of the first core is currently set: provide a current value of the mask register of the first core to each of the other of the plurality of processing cores and set the flag; and otherwise: clear the flag; and wherein to update the value, each of the plurality of processing cores updates both the base register and the mask register if the flag is set, and otherwise update only the base register or mask register as specified by the architectural instruction.