1. A device ( 100 ) comprising a pipelined processors; an instruction memory unit; and a register file; wherein the pipelined processor comprises a write-back unit; and an execution unit a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instructions and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information; wherein the second register group size information and the second register identification information define a second group of target registers associated with a second instruction; and wherein the second instruction is provided to the pipelined processor before the first instruction.