1. A computer processing system comprising: a memory system that is configured to store a plurality of instruction blocks, wherein each instruction block is associated with an entry address and multiple distinct instruction streams within the instruction block, wherein the multiple distinct instruction streams include at least a first instruction stream and a second instruction stream, the first instruction stream having an instruction order that logically extends in a direction of increasing memory space relative to said entry address, and the second instruction stream having an instruction order that logically extends in a direction of decreasing memory space relative to said entry address; a computer processor, operably coupled to the memory system, including a plurality of multi-stage instruction processing components corresponding to the multiple distinct instruction streams within each instruction block, wherein the plurality of multi-stage instruction processing components are configured to access and process in parallel instructions belonging to multiple distinct instruction streams of a particular instruction block stored in the memory system.