1. A method of translating a verification process for implementation in a hardware emulator of a logic verification system, comprising: identifying a recursive task called by the verification process; incorporating a copy of the recursive task into the verification process instantiating interface registers for the recursive task; defining control flow transfer points in the verification process; converting calls of the recursive task in the verification process to constructs for accessing of the interface registers and transferring control flow among the control flow transfer points; and reorganizing the verification process to describe a finite state machine (FSM) configured for implementation in the hardware emulator.