1. An apparatus, comprising: a processor having: a processing core to execute an instruction that specifies a performance state of an application thread, said instruction belonging to said application thread; a first register to store said performance state; a second register to store a system edict value to indicate whether the processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption; and power management control logic coupled to the first register and the second register to set a performance state of the processing core as a function of said performance state of said application thread and said system edict value.