1. An electrically programmable integrated logic array comprising n inputs for variables (Ai), m outputs (Si) for logic combinations of the variables, a programmable product matrix having 2n.times.p programmable elements arranged in 2n lines and p columns and having n pairs of inputs and p outputs for supplying p intermediate products of said variables, and a programmable sum matrix having m.times.p programmable elements arranged in p lines and m columns and having p inputs connected through an interface logic circuit respectively to said p outputs of said product matrix, said sum matrix having also m outputs connected through an output interface circuit to said m outputs of the array, a logic control circuit for supplying to the array reading mode control signals and writing mode control signals among which two successive writing mode control signals (VA1, VA2) providing a two step transmission of said variables from each of the n inputs for variables to a respective pair of inputs of said product matrix, said array further including a decoder connected to said interface logic circuit for selecting a given output of said product matrix and a respective input of said sum matrix, and an input interface circuit controlled by said logic control circuit and connected to said n inputs for variables and supplying signals to each of the 2n inputs of said product matrix, wherein said input interface circuit comprises, for each input for variable, a first latching circuit receiving a logical level from said input for variable and a first one of the two successive writing mode control signals, and supplying, after reception of said first signal, a first programming signal on a first input of a pair of inputs of said product matrix, for programming the elements of a line of the product matrix corresponding to this first input, a second latching circuit receiving a logical level from said input for variable and a second one of the two successive writing mode control signals, and supplying, after reception of said second signal, a second programming signal on a second input of said pair of inputs of said product matrix, for programming the elements of a line of the product matrix corresponding to the second input, at least one by-pass gate controlled by said reading mode control signals for transmitting directly, in a reading mode, a logical level present on said input for variable to one input of said pair of inputs of said product matrix and a complementary logical level to the other input of said pair, and wherein said interface logic circuit between the product and sum matrix receives writing control signals for supplying programming signals, in a writing mode, to a selected output of said product matrix and to a respective input of said sum matrix, for programming the elements of a column of the product matrix and of a corresponding line of the sum matrix.