1. An electronic circuit comprising: a memory; a first set of storage elements having a first width; a second set of storage elements having a second width, wherein the first width is greater than the second width; an instruction operand value generating circuit configured to generate a succession of values in an operand value range; an address pipeline coupled to the instruction operand value generating circuit and configured to use the succession of values to access a succession of memory locations in the memory; and selection circuitry coupled to the instruction operand value generating circuit and configured to use the succession of values to access the first and second sets of storage elements concurrently with the accessing of the succession of the memory locations by the address pipeline to effectuate transferring of information between the first and second sets of storage elements and the memory.