1. A computer system for executing a program made up of instructions having a program order, the computer system comprising: a plurality of processor/memory units communicating with each other over an interconnect having a first data rate limit, each processor/memory unit including: (a) a memory having: (i) addresses designated as REPLICATED holding program portions local to the processor/memory unit in common with other processor/memory units; (ii) addresses designated as COMMUNICATED AND OWNED holding program portions local to the processor/memory unit exclusive of other processor/memory units; (iii) addresses designated as COMMUNICATED AND NOT OWNED not holding program portions local to the processor/memory unit; (b) a processor communicating with the memory over a channel having a second data rate limit, wherein the processor operates to: (i) process a first portion of the program at the REPLICATED addresses without communication of the first portion on the interconnect; (ii) process a second portion of the program at the COMMUNICATED AND OWNED addresses with a communication of the second portion on the interconnect to other processor/memory units without a request by the other processor/memory units for the second portion; (iii) process a third portion of the program at the COMMUNICATED AND NOT OWNED addresses by receiving the third portion from the interconnect as transmitted by another processor/memory unit without requesting the third portion over the interconnect; and (iv) during the processing of the program at (iii) but prior to receiving the third portion, processing another portion of the program.