1. A method for testing a memory array, comprising: (a) establishing a stored data vector, including a plurality of data bits, within at least one circuit; (b) applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; (c) transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; (d) comparing the succession of exercised data vectors to the succession of respective original data vectors; and (e) determining whether the memory array passes or fails based on the comparing step.