1. A processor, comprising: a coprocessor interface unit that couples a coprocessor that executes instructions in-program order to an execution unit that executes instructions out-of-program order, wherein the coprocessor interface unit includes a coprocessor store data queue, and if data stored in a register of the coprocessor is to be stored in a register file of the execution unit, the data is transferred from the coprocessor to the coprocessor store data queue; and a graduation unit coupled to the coprocessor, wherein the graduation unit provides a signal to the coprocessor that determines whether an instruction executed by the coprocessor is permitted to alter an architectural state of the processor.