1. An integrated circuit for detection of malicious code hiding in a first level instruction cache, comprising: a processor; the first level instruction cache having a first storage capacity; and a second level cache having a second storage capacity that is larger than the first storage capacity; the first level instruction cache is coupled between the processor and the second level cache, the first level instruction cache is configured to store a subset of instructions stored in the second level cache, the second level cache is coupled between the first level instruction cache and an external memory, the second level cache is configured to store a subset of data and instructions stored in the external memory, and the processor is configured to execute an inner loop of a detection routine, monitor an execution time of the inner loop, and compare the monitored execution time with an execution time threshold to detect malicious code hiding in the first level instruction cache, wherein code for a total number of detection routine instructions is larger than the first storage capacity, wherein the inner loop, during execution, requires fetching of detection routine instructions from the second level cache, and wherein code for an execution number of instructions executed during execution of the inner loop is smaller than the first storage capacity based on executing selected code of the detection routine instructions.