1. A low-density parity-check (hereinafter referred to as LDPC) apparatus configured to decode an original codeword into a decoded codeword, the LDPC apparatus comprising: an LDPC iteration calculating circuit configured to perform an LDPC iteration calculation by using the original codeword to obtain a new decision bit value of a corresponding variable node among a plurality of variable nodes; a decision-bit storage circuit, coupled to the LDPC iteration calculating circuit to receive the new decision bit value of the corresponding variable node, configured to use the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values of the variable nodes stored in the decision-bit storage circuit, wherein the old decision bit values of the variable nodes stored in the decision-bit storage circuit are used as the decoded codeword when the LDPC iteration calculation is converged; and a convergence detection circuit coupled to the LDPC iteration calculating circuit to receive the new decision bit value and coupled to the decision-bit storage circuit to read the corresponding old decision bit value, wherein the convergence detection circuit is configured to store multiple check sums, and each of the check sums corresponds to each of a plurality of check nodes, and the convergence detection circuit is configured to use the new decision bit value and the corresponding old decision bit value to update a corresponding check sum among the check sums, and determine whether the LDPC iteration calculation is converged when one of the check sums is updated.