1. A circuit comprising a plurality of pipeline stages, each of the plurality of pipeline stages comprising: at least one asynchronous, delay-insensitive input channel, each input channel being operable to communicate with a preceding one of the pipeline stages by waiting for input data on the input channel, asserting an input acknowledge signal in response to the input data, waiting for the input channel to be set neutral, and deasserting the input acknowledge signal in response to the input channel being set neutral; at least one asynchronous, delay-insensitive output channel, each output channel being operable to communicate with a subsequent one of the pipeline stages by waiting for an output acknowledge signal associated with the subsequent pipeline stage to be deasserted, transmitting output data on the output channel in response to deassertion of the output acknowledge signal, waiting for the output acknowledge signal to be asserted, and setting the output channel neutral in response to assertion of the output acknowledge signal; input completion circuitry configured to generate an input completion signal indicative of validity of the input data; output completion circuitry configured to generate an output completion signal indicative of validity of the output data; enable circuitry configured to generate the input acknowledge signal and an internal enable signal using the input completion signal and the output completion signal as input; and domino logic configured to compute the output data directly from the input data, the domino logic being configured to hold a state of the output data until reset in response to the output acknowledge signal associated with the subsequent pipeline stage and the internal enable signal.