1. An apparatus comprising: a processor including: marking logic to mark a first speculation identifier associated with a speculative store instruction of a speculative thread as speculative; and blocker logic to prevent data associated with the speculative store instruction of the speculative thread from being forwarded to a non-speculative instruction of a non-speculative thread based on a first address associated with the speculative store instruction and the first speculation identifier in comparison to a second address associated with the non-speculative store instruction and a second speculation identifier associated with the non-speculative instruction and in response to a first speculation identifier not matching a second speculation identifier.