1. A memory device, comprising: a memory array partitioned into a plurality of memory banks; a first sense amplifier including a first latch, the first sense amplifier operably coupled with a first memory bank of the plurality of memory banks; a second sense amplifier including a second latch, the second sense amplifier operably coupled with a second memory bank of the plurality of memory banks; and a buffer operably coupled with the first latch and the second latch, wherein the buffer is configured to receive first data, receive second data after sending the first data to the first latch to be programmed in the first memory bank, and send the second data to the second latch to be programmed in the second memory bank.