1. A processor having a plurality of registers and a plurality of operation units, which executes a very long instruction word including (i) a register specifying field which specifies at least one of said plurality of registers, (ii) a plurality of instructions which specify operations using said operation units, and (iii) register allocation information which indicates a corresponding relationship between the register specified by said register specifying field and the instruction which uses the register, the processor comprising: an output port which outputs a value in the register specified by said register specifying field; and an input selection control unit operable to execute selection and control so that the value outputted from said output port is inputted into said operation unit according to the corresponding relationship indicated by said register allocation information.