1. A Built-In Self Test (BIST) circuit for testing a memory, comprising: a microcode sequencer for storing and performing a memory-test procedure suitable for testing a memory by generating memory operation codes, address codes, and data codes; at least one address register operably coupled to the microcode sequencer, each address register responsive to the address codes to generate a BIST address; at least one data register operably coupled to the microcode sequencer, each data register responsive to the data codes to generate BIST data; and a command constructor operably coupled to the memory operation codes, the BIST address, and the BIST data, the command constructor configured for developing command signals, address signals, and data signals for operating the memory.