1. An event processing apparatus for use with an event based test system for testing a semiconductor device under test (DUT), comprising: an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period (event count data) and a fraction of the clock period (event vernier data); an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form; and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic; wherein the events in the event data are specified as groups of events where each group is configured by one base event and at least one companion event.