1. A system, comprising: a first processor configured to: load from a first memory an instruction block comprising a plurality of opcodes and a stored error code; for each opcode of the plurality of opcodes of the instruction block, determine a first determined signature depending on said opcode; determine, for the instruction block, a determined error code which depends on each opcode and on the first determined signature of each opcode of the plurality of opcodes of the instruction block; and determine that a first error occurred, if the determined error code is different from the stored error code; and a second processor configured to: determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode; and determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.