1. A circuit comprising: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to said devices, the DMA engine comprising a plurality of DMA contexts each for fetching a DMA descriptor indicated by the CPU and for transferring data from one to another of said devices based on a fetched descriptor; wherein the DMA engine further comprises switching means operable to control a group of said contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.