1. A hardware processor comprising: a hardware decoder to decode a first instruction into a decoded first instruction, a second instruction into a decoded second instruction, and an add instruction into a decoded add instruction; and a hardware execution unit to: execute the decoded first instruction to multiply a first input operand and a second input operand and store a lower portion of a result, said first and second input operands being respective elements of a first input vector and a second input vector, execute the decoded second instruction to multiply the first input operand and the second input operand and store an upper portion of a result, said first and second input operands being the respective elements of the first input vector and the second input vector, and execute the decoded add instruction to add aligned elements of the upper portion and the lower portion with a previous, corresponding carry term from an input operand and store a result.