1. A processor, having a plurality of instruction slots each of which stores an instruction to be executed in parallel, wherein one of the plurality of instruction slots is a first instruction slot and another one of the plurality of instruction slots is a second instruction slot, the processor being characterized by: a special instruction stored in the first instruction slot being executed by a first functional unit that executes instructions stored in the first instruction slot and a second functional unit that executes instructions stored in the second instruction slot, while an instruction in the second instruction slot is executed by a third functional unit that executes instructions stored in the second instruction slot.