1. A method of design rule checking, comprising: forming a multi-tiered integrated chip (IC) design comprising a graphical representation of a multi-tiered integrated chip having a plurality of stacked tiers respectively comprising an integrated chip die using a design tool; defining one or more individual design layer definitions within a design rule checking (DRC) deck, wherein respective design layer definitions correspond to a design layer within the plurality of stacked tiers comprising the design layer, wherein the one or more individual design layer definitions are defined as functions of one or more first layer numbers, which are stored within a first layer database and that identify layers within a first tier, and one or more second layer numbers, which are stored within a second layer database and that identify layers within a second tier; and defining one or more design rules for respective ones of the one or more individual design layer definitions within the DRC deck using a DRC generation element, wherein the one or more design rules separately apply to design layers associated with the individual layer definitions within the plurality of stacked tiers in the multi-tiered IC design.