1. A VLIW Processor, comprising: a program memory; a fetching pipeline connected to said program memory; an execution pipeline connected to said fetching pipeline; latching circuitry connected to said fetching pipeline and said execution pipeline; a register file connected to said execution pipeline; and wherein said program memory houses an OCB VLIW program memory map containing a plurality of OCB VLIW instructions, with each instruction of said plurality of OCB VLIW instructions having a respective memory address, a respective operation code, a respective comparison and branch code; and at least two respective pointer branches.