1. A reconfigurable circuit comprising: a plurality of reconfigurable interconnect devices; a plurality of clusters of reconfigurable logic devices, each cluster being coupled to the plurality of reconfigurable interconnect devices; and a programming interface coupled to the plurality of reconfigurable interconnect devices and to the plurality of clusters of reconfigurable logic, the programming interface configured to receive configuration data to configure a first combination of the reconfigurable interconnect and logic devices to implement a circuit, and to remap a portion of the received configuration data, corresponding to a defective cluster, from the defective cluster to another non-defective cluster of the plurality of clusters to configure a second combination of the reconfigurable interconnect and logic devices to implement the circuit.