1. A writeback and refresh circuit for a direct sense architecture memory comprising: a global data line; a plurality of primary sense amps connected to the global data line and also connected to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines; a single secondary sense amp connected to the global data line, wherein the secondary sense amp receives data from the primary sense amps over the global data line, and includes a restore/writeback circuit to writeback data over the global data line to a primary sense amp and back into the memory.