1. A method of coupling a content of a Branch Target Buffer (BTB) with an instruction cache content of an instruction cache comprising: in a block-based BTB, tagging a plurality of target buffer entries that belong to branches within a same instruction block with a corresponding instruction block address and a branch bitmap to indicate individual branches in the block, whereby a predefined number of BTB entries tagged with an instruction block address and a bitmap constitute a bundle; coupling an overflow buffer with the BTB to accommodate further BTB entries of instruction blocks, distinct from the plurality of BTB entries, which have more branches than the bundle is configured to accommodate in a corresponding instruction bundle in the BTB; and predicting instructions or instruction blocks that are likely to be fetched by a core and fetching those instructions from lower levels of a memory hierarchy.