1. A cache control device that controls access requests to a cache shared by plural threads that are simultaneously executed, the cache control device comprising: a storing unit provided in association with each of the threads, the storing unit storing a flag that indicates a first defined value when the thread enters execution of an atomic instruction for indivisibly executing plural kinds of processing and indicates a second defined value different from the first defined value when the atomic instruction is completed; a determining unit for determining, when an access request is issued from a certain thread, referring to the flag value stored by the storing unit, whether a thread different from the thread that issues the access request is executing an atomic instruction; and an executing unit for executing, when the determining unit determines that the different thread is executing the atomic instruction, processing for putting the issued access request on standby.