1. A processor comprising: a decode unit to decode a load instruction, wherein if the load instruction is predicted to be memory renamed, a predicted store identifier is associated with the load instruction and the decode unit is to transform the load instruction into a data move instruction and a load check instruction; a cache, wherein the data move instruction is to read data from the cache based on the predicted store identifier and the load check instruction is to compare an identifier associated with an identified source store with the predicted store identifier; and a retirement unit to retire the load instruction if the predicted store identifier matches the identifier associated with the identified source store.