1. In a compiler that compiles an electronic design to define a fitting of the electronic design on one or more target hardware devices, the electronic design having a logical hierarchical structure including parent logical entities and children logical entities, a method of compiling with parallel processing, the method comprising: providing a compilation project including (i) a first compilation task associated with a first child logical entity and (ii) a second compilation task associated with the second child logical entity; allocating a first processing resource for running the first compilation task; allocating a second processing resource, which is separate from the first processing resource, for running the second compilation task; and contemporaneously running the fit compilation task on the first processing resource and running the second compilation task on the second processing resource, wherein the first compilation task associated with the first child logical entity comprises: (a) mapping the first child logical entity into a plurality of logic cells representing discrete units of logic to be implemented on discrete logic elements on the one or more target hardware devices, (b) providing a partitioning project for grouping the individual logic cells into blocks of proximate logic elements, the partitioning project including (i) a first partitioning task including performing a bipartitioning routine on a fist pair of blocks of the logic elements of the one or more target hardware devices and (ii) a second partitioning task including performing said bipartitioning routine on a second pair of blocks, different from the first pair, of the logic elements of the one or more target hardware devices, and (c) contemporaneously running the first and second partitioning tasks, wherein the bipartitioning algorithm includes swapping the logic cells between individual blocks of the pairs of blocks to reduce the number of signal crossings between blocks, and wherein the first and second child logical entities are (i) isolated from one another by one or more resisters, (ii) represent separate stages of pipelined logic, (iii) are separated by a state machine, or (iv) are separate regions identified for resynthesis during incremental compilation.