1. A memory macro, comprising: a plurality of memory array segments, each having a predetermined number of data inputs and outputs; a segment decoder circuit configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value; and a plurality of output drivers coupled to the segment decoder circuit and to respective ones of the outputs, the plurality of output drivers configured to selectively output data from the respective outputs of each of the respective activated memory array segments.