1. A performance monitor hardware unit that is included in a processor, said performance monitor hardware unit monitoring the performance of said processor, said performance monitor hardware unit comprising: a plurality of performance event signals received by said performance monitor hardware unit, said plurality of performance event signals indicating the current full event state of said processor at a particular time; a plurality of hardware counters for counting only a selected subset of said plurality of performance event signals; a hardware event register that intercepts said plurality of performance event signals and outputs the selected subset of said plurality of performance signals to said plurality of hardware counters; and current values of said plurality of performance event signals being stored together as a single unit in said hardware event register, said single unit being a full set of available performance event signals that indicate the current full event state of said processor at said particular time.