1. A semiconductor device comprising: a memory cell array including a first memory region and a second memory region; a plurality of register sets for storing a plurality of parameter sets; and a control logic circuit configured to, load each of the plurality of parameter sets into each of the plurality of register sets, select a first register set among the plurality of register sets in response to a selection signal, and perform an access operation on the first memory region using a parameter set stored in the first register set from among the plurality of register sets, wherein the parameter set stored in the first register set is loaded into the first register set before the first register set is selected in response to the selection signal.