1. An interconnect structure for connecting logic cells of a programmable array to a core region within the array, the core region being generally characterized by circuits therein of a functional type different than that of the logic cells, the interconnect structure comprising: a plurality of general interconnect buses for interconnecting the logic cells; and a first row/column of ports for carrying signals to or from the core region and selectively connectable, independent of the general interconnect buses, to logic cells of a first interior row/column of the logic cells, at least some ports of the row/column of ports positioned proximate a respective column/row of the logic cells, the at least some ports being selectively connectable to at least one interconnect bus of the general interconnect buses associated with their respective column/row of logic cells.