1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a processor integrated circuit, the design structure comprising: a plurality of master processor cores; a plurality of cache memories, each cache memory being coupled to a respective master processor core; and a processor bus controller (PBC) coupled to the plurality of master processor cores, the PBC being configured to couple to a system memory indirectly via a memory controller, the PBC being further configured to couple directly to a master I/O device controller and a slave I/O device controller, wherein the PBC receives an initial command data request from a master processor core or a master I/O device, the initial command data request including a referenced address range in the system memory, and in response to the initial command data request sending the PBC sends a reflected command to any master processor core, system memory and I/O slave device that the PBC determines to be within the referenced address range; wherein in response to the reflected command, the master processor cores, system memory and slave I/O device in the referenced address range, send respective partial responses to the PBC, such that the PBC blocks the partial response of the memory controller, the master processor cores, and the master I/O device but not the slave I/O device from inclusion in a combined response that the PBC sends to master processor cores, master I/O devices and system memory.