1. An apparatus for providing data coherency, comprising: a global persistent memory, wherein the global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics; a reflected memory region, wherein the reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable; and a semaphore memory, wherein the semaphore memory provides a hardware assist for enforced data coherency.