1. A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus comprising: a multiplier block comprising two 16-bit by 32-bit multiplier circuits that together transform a number of input multipliers and a number of input multiplicands into a number of multiplication products; and an accumulator block that adds the multiplication products to a number of input addends and tangibly outputs a number of multiply-accumulate results, wherein sign extension for the multiply-accumulate results is performed: (i) under a first format for at least a first number of bits for the input multipliers and the input multiplicands and (ii) under a second format for at least a second number of bits for the input multipliers and the input multiplicands.