1. An apparatus comprising: a memory controller to provide access to a main memory; at least one central processing unit having an L1 cache; an L2 cache coupled to the at least one central processing unit; a graphics processing unit in a different cache coherency domain than the L1 cache; and interconnect logic including at least some hardware and coupled to the at least one central processing unit and coupled to the graphics processing unit, the interconnect logic to enable information sharing between the at least one central processing unit and the graphics processing unit and to allow the graphics processing unit to access information within the L2 cache without first resorting to main memory; wherein the at least one central processing unit and the graphics processing unit maintain coherency with the L2 cache.