1. An apparatus, comprising: an array of memory cells coupled to sensing circuitry including a sense amplifier and a compute component, wherein the sensing circuitry is controlled to: receive a scan vector from a first portion of the array of memory cells; perform a scan chain operation on the scan vector to yield a resulting scan vector; perform a compression operation using the sensing circuitry to reduce a size of the resulting scan vector; and write the resulting scan vector to a second portion of the array of memory cells.