1. A memory error detection method of a computing device using a baseboard management controller (BMC) of the computing device, the method comprising: adjusting an operating frequency of a microprocessor of the BMC according to a bus frequency of a platform environment control interface (PECI) bus; controlling the microprocessor to communicate with a processor of the computing device based on the operating frequency of the microprocessor; reading data of a state register of the processor when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor; determining whether the internal error is a multiple-bit error of a memory of the computing device according to the read data; and recording error information of the multiple-bit error in a storage system of the BMC upon the condition that the internal error is the multiple-bit error.