1. A method of decreasing memory access latency in a system processing items held in memory, the method comprising: providing a cache memory having a set of cache partitions, each cache partition comprising a plurality of addressable storage locations for holding the items fetched from said memory for use by a processor; loading an item fetched from said memory into one of the cache partitions in accordance with partition indicator for the item, wherein the partition indicator identifies into which cache partition the item may be loaded; and when the processor executes at least two processes simultaneously, altering the number of cache partitions when the processor switches from executing a process to executing another process.