1. A method of compiling code, comprising: partitioning instructions in the code among a plurality of processors based on memory access latency associated with the instructions by: partitioning memory access dependence chains into an upstream stage by assigning a first number of desired upstream nodes to the upstream stage, and also assigning instructions in the code on which the first number of desired upstream nodes are dependent to the upstream stage, wherein the first number of desired upstream nodes is N/d where N is a length of the memory access dependence chain and d is a pipelining degree; and partitioning the memory access dependence chains into a downstream stage by assigning a last number of desired downstream nodes to the downstream stage, and assigning instructions in the code which are dependent on the last number of desired downstream nodes to the downstream stage, wherein the last number of desired downstream nodes is N*(d−1)/d; performing the partitioning a plurality of times with subsequent partitioning being performed on the instructions assigned to the downstream stage.