1. A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field and branches to an address obtained by adding a value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit and outputting a decoded result; an instruction execution unit for executing the instructions on the basis of the said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the instruction being decoded in said instruction decoding unit; and a branch target address calculation unit including first adding means for calculating a first address in parallel with decoding of a first instruction in said instruction decoding unit, by adding a value of the first branch displacement field of said first instruction inputted from said instruction fetch unit, and an address of said first instruction inputted from said program counter, said first adding means starting calculation of said first address before said first instruction is identified as said first branch instruction, second adding means for calculating a second address in parallel with decoding of said first instruction in said instruction decoding unit, by adding a value of the second branch displacement field of said first instruction inputted from said instruction fetch unit, and an address of said first instruction inputted from said program counter, said second adding means starting calculation of said second address before said first instruction is identified as said second branch instruction, and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.