1. A multithread processor designed to carry out a plurality of threads, each having one or more instructions, in parallel through the use of one or more arithmetic units, comprising: a multithread control unit for selectively switching said thread to be executed by said arithmetic unit and for setting a thread identifier indicative of one of said plurality of threads to which said instruction pertains; an instruction control unit for setting an instruction identifier which specifies said instruction in said thread; a plurality of caches arranged hierarchically and each made to retain data temporarily; and a cache control unit for managing writing/readout of said data in/from said plurality of caches, in a case in which a cache miss occurs on a request related to said instruction in, of said plurality of caches, said cache which is at the lowest place in the hierarchy, with respect to said request related to said cache miss, said cache control unit notifying said instruction identifier and said thread identifier, related to said instruction, to said multithread control unit, and said multithread control unit making the switching of said thread, which is in execution in said arithmetic unit, to a different thread on the basis of said instruction identifier and said thread identifier notified from said cache control unit.