1. A system comprising: at least one reduced instruction set computer (RISC) processor; a memory controller integrated with the RISC processor; and a network interface, the network interface coupled to the RISC processor to enable the RISC processor to send and receive data via a network, wherein the RISC processor comprises: a decoder to decode an instruction; and execution logic to perform operations specified by the instruction; wherein, to perform the operations, the execution logic is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location; wherein an element bit-width of the plurality of elements is greater than a sub-element bit-width of the M sub-elements.