1. A microprocessor for performing both graphics and non-graphics operations, comprising: a first source register; a second source register; a destination register; multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of values in each of said two registers in response to a multiply/add Opcode; and an adder having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned addition of a plurality of values in said third register with a plurality of values output from said multiplier in response to said multiply/add Opcode.