1. A computer-implemented method of generating a circuit design comprising: receiving target data comprising a specification of a target application, the target data comprising netlists associated with one or more target applications; receiving training data comprising a specification of a training application or a training feature, or comprising a modification to the target data; generating a circuit design for implementing the target application, wherein the circuit design comprises nodes and interconnects and is over-provisioned with respect to the target data according to the training data; and merging the netlists to find a minimum number of nodes required to run the target applications of the target data and to provide a corresponding node and interconnect layout, thereby generating the circuit design for implementing the target applications.