1. A method comprising: identifying during operation of an integrated circuit a first portion of a cache memory for servicing access requests from a random access generator, and identifying a second portion of the cache memory that cannot service access requests from the random access generator; executing a security sensitive operation at a processor core that includes the cache memory; and in response to being identified, using the first portion of the cache memory to service access requests generated by the random access generator during execution of the security sensitive operation.