1. An integer cluster device comprising: a processor; a positive coding device and a negative coding device; a real number reception unit that operates on the processor for receiving one or multiple real number signal values at time intervals of said positive coding device and said negative coding device receiving nonnegative real number signal values and outputting nonnegative integer signal values, and supplying: (a) a real number value v to said positive coding device as a nonnegative real number signal value and â€œ0â€ to said negative coding device as a nonnegative real number signal value when the sum total v of the real number signal values is nonnegative; and (b) â€œ0â€ to said positive coding device as a nonnegative real number signal value and a real number value âˆ’v to said negative coding device as a nonnegative real number signal value when the sum total v of the real number signal values is negative; a positive neural network receiving a nonnegative integer signal value from said positive coding device and performing arithmetic operations on the nonnegative integer; a negative neural network receiving a nonnegative integer signal value from said negative coding device and having the same circuit structure as said positive neural network; and an integer arithmetic operation output unit that operates on the processor for outputting as an integer arithmetic operation result signal a value obtained by subtracting the signal value output from said negative neural network from the signal value output from said positive neural network, wherein each of the positive coding device and the negative coding device comprises: N neuron devices; a nonnegative real number reception unit that operates on the processor for receiving one or multiple nonnegative real number signal values at time intervals of said N neuron devices receiving input signal values and outputting output signal values, and outputting the sum total u of the nonnegative real number signal values to said N neuron devices as an input signal value; and a nonnegative integer output unit that operates on the processor for outputting the sum total of the output signal values from said N neuron devices as a nonnegative integer signal value, wherein each of said N neuron devices comprises: a threshold storage unit that operates on the processor for storing a threshold variable Î¸ and two threshold coefficients Î”Î¸ 1 and Î”Î¸ 2 ; an input reception unit that operates on the processor for receiving one or multiple input signal values at predetermined time intervals; an output unit that operates on the processor for outputting, as an output signal value, a value â€œ1â€ for indicating that the neuron device is firing when the sum total s of received input signal values is equal to or greater than the value of said stored threshold variable Î¸, and otherwise a value â€œ0â€ for indicating that the neuron device is resting; and a threshold updating unit that operates on the processor for calculating: 
 Î”Î¸1X+Î”Î¸2(Xâˆ’1); and using said output signal value X and said stored threshold coefficients Î”Î¸ 1 and Î”Î¸ 2 , and updating the value of the threshold variable Î¸ stored in said threshold storage unit by increasing the threshold variable Î¸ by the calculation result, and wherein said N neuron devices store 1, 2,. .. ,N as the initial value of the threshold variable Î¸ and store â€œ0â€ as the values of the threshold coefficients Î”Î¸ 1 and Î”Î¸ 2 in their threshold storage units.