1. A memory device comprising: input/output (I/O) circuitry to receive signals; a plurality of memory banks; detector logic comprising circuitry configured to detect for a signal, the signal to specify that received commands include successive write commands each to access a same memory bank of the plurality of memory banks; a buffer, wherein, if the detector logic detects the signal, the detector logic to signal the buffer to store first write data of the successive write commands until a receipt of second write data of the successive write commands; and error correction logic configured to calculate error check information based on the first write data and the second write data.