1. A bus interface comprising: an interface coupled between a bus and at least two processor cores; and a queue coupled to the interface and adapted to snoop responses from the at least two processor cores and coalesce snoop responses from the at least two processor cores into a single snoop response to the bus that reflects snoop responses from the at least two processor cores; wherein the queue is operative as a snoop coalesce queue comprising an array of multiple-bit storage elements per processor core, bit fields of the storage elements comprising a hit response bit, a hit modified (hitm) response bit, and a valid bit.