1. A computer implemented method of code optimization in presence of hardware constraints, the method comprising: scheduling instruction codes using virtual registers in a manner that tends to minimize simultaneous active registers while minimizing a number of passes of a processing unit; allocating the virtual registers to physical registers according to a plurality of register allocation orders to produce a corresponding plurality of physical register allocations; determining a conflict value for each register allocation from the plurality of physical register allocations, wherein the conflict value is determined based on a number of times a read or a write bandwidth constraint of the processing unit is exceeded, the read and write bandwidth constraints corresponding to a maximum number of register read or write operations, respectively, that the processing unit can perform in a given pass; determining a physical register allocation corresponding to a least conflict value; and rescheduling the instruction codes using the physical register allocation to optimize the code by further reducing a number of conflicts.