1. A method of stalling one or more stages in a pipeline of an integrated circuit comprising the steps of: creating a stall signal for stalling a stage in the pipeline; and creating one or more delayed stall signals, causally related to said stall signal, the delayed stall signals stalling one or more adjacent upstream stages a delay time later than said stage is stalled, wherein the stages of said pipeline operate in lock step and unstalled valid data may be stored only in every other stage at any given time, upstream stages progressively filling with valid data in each stage during a stall condition, filled said upstream stages buffering stored valid data during said stall condition.