1. A pipelined processor comprising circuitry adapted for store forwarding, the microprocessor comprising circuits for performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated completed block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate and the data is available in a store data queue, selecting an appropriate block of data from the store data queue on a block-by-block basis and forwarding the selected block of data to the additional store request to be used as the most recent value; or if store forwarding is appropriate and the data is not available in the store data queue, recording the queue entry number for the additional store request in a cold forwarding state for the store queue entry that would have been forwarded.