1. A measurement system comprising in combination: first means for generating a first binary number of more than four bits representative of a coarse measurement of a predetermined parameter; second means, coupled to said first means, for generating a second binary number of four or more bits representative of a fine measurement of a portion of said predetermined parameter; coarse/fine comparator means, responsive to the lower four bits of said first binary number and to the upper four bits of said second binary number, for generating first, second, and third command signal conditions; means, responsive to said command signal conditions, for respectively adding one count to, subtracting one count from, or leaving unchanged the upper bit portion of said first binary word to provide a corrected or unchanged first binary word, and; means for combining said corrected or unchanged first binary word with said second binary word to provide a combined binary word representative of said predetermined parameter; said coarse/fine comparator means comprising a four bit binary full adder having four first bit inputs, four second bit inputs, a carry-out output and a .SIGMA.4 output, first inverter means for inserting inputs to said four first inputs, a first AND gate having first and second input connections, a second AND gate having first and second input connections, second inverter means for inverting inputs to said first and second input connections of said second AND gate, said carry out output being connected to one of said input connections to said first AND gate and by said second inverter means to one of said first AND gate and by said second inverter means to one of said inputs connections to said second AND gate, and said .SIGMA.4 output being connected to the other of said input connections to said first AND gate and by said second inverter means to the other of said input connections of said second AND gate, whereby said first AND gate provides a true output only when said carry out and said .SIGMA.4 outputs are both true, and said second AND gate provides a true output only when said carry out and said .SIGMA.4 outputs are both not true, said first output signal condition existing when only one of said AND gates has a true output, said second output signal condition existing when only the other of said AND gates has a true output, and said third output signal condition existing when neither of said AND gates has a true output.