1. A computer for executing a task, the task being segmented into a plurality of instructions to be executed sequentially, said computer comprising: (a) an interconnection network; (b) a first cell coupled to said interconnection network, said first cell including: a first receive queue coupled to said interconnection network for receiving a first incoming transmission packet containing a first instruction and a first link address, said first link address identifying a first memory packet and forming a portion of a linked list of memory packets specifying an order of execution; a first memory coupled to said first receive queue for storing said first memory packet, said first memory packet being selectively disposed in said first cell and including a second instruction, a first data element and a second link address, said second link address identifying a second memory packet and forming a portion of said linked list of memory packets specifying an order of execution; a bypass queue coupled to said first memory for outputting a second incoming transmission packet that addresses no memory packet residing in said first memory; a first arithmetic and logic unit (ALU) coupled to said first memory for executing said first instruction; means coupled to said first ALU for generating a first outgoing transmission packet containing said second instruction and a link field for storing said second link address; and (c) a second cell coupled to said first cell through said interconnection network, said second cell comprising: a second receive queue coupled to said interconnection network for receiving said first outgoing transmission packet; a second memory coupled to said second receive queue for storing said second memory packet, said second memory packet being selectively disposed in said second cell and including a third instruction, a second data element and a third link address, said third link address identifying a third memory packet and forming a portion of said linked list of memory packets specifying an order of execution; a second ALU coupled to said second memory for executing said second instruction stored in said first outgoing transmission packet; and means coupled to said second ALU for generating a second outgoing transmission packet containing said third instruction and said third link address.