1. A programmable logic array integrated circuit organized as a two-dimensional array of cells comprising: a first plurality of conductors, each of which extends along a first dimension of said two dimensional array; a second plurality of conductors, each of which extends along a second dimension of said two dimensional array, said second plurality of conductors programmably coupled to said first plurality of conductors; an array of logic array blocks devoted substantially to logic functions, said array of logic array blocks programmably coupled to at least one of said first or second plurality of conductors, each logic array block comprising an equal number of substantially identical programmable logic elements, each programmable logic element having at least one programmable logic element input and at least one programmable logic element output; and an array of random access memory blocks devoted substantially to user memory, said array of random access memory blocks programmably coupled to at least one of said first or second plurality of conductors, each random access memory block comprising a plurality of memory columns and a control unit coupling said first plurality of conductors to said plurality of memory columns.