1. A reconfigurable processor comprising: a processor core to request access to configuration data regarding a schedule of loop operations to be performed in parallel by function units by using virtual addresses; a configuration memory to store the configuration data loaded from a main memory; and a configuration memory management unit to control the access of the processor core to the configuration data and read the configuration data from addresses of the configuration memory mapped to the virtual addresses, wherein the configuration memory management unit manages addresses of the main memory and the addresses of the configuration memory by mapping the addresses of the main memory and the addresses of the configuration memory to each other, based on the virtual addresses, wherein: the configuration memory management unit allocates the addresses of the configuration memory to the configuration data so as to sequentially load the configuration data into the configuration memory if a size of the configuration data stored in the main memory exceeds a size of the configuration memory, and the configuration memory management unit maps the virtual addresses to the addresses of the configuration memory in a non-overlapping manner if the size of the configuration data stored in the main memory does not exceed the size of the configuration memory.