1. A non-volatile memory (NVM) device, comprising: a) an interface configured to receive write and read commands from a host; b) a memory array comprising a plurality of NVM cells arranged in a plurality of array planes; c) a memory controller configured to execute a write operation on a first of the plurality of array planes in response to a write command, and to execute a read operation on a second of the plurality of array planes in response to a read command, wherein the memory controller is configured to suspend the write operation in response to detection of the read command during execution of the write operation, and wherein the memory controller is configured to resume the write operation during execution of the read operation on the memory array; and d) a regulator circuit configured to supply a bias voltage for the write operation, wherein the read command comprises a time slot to allow capture of a state of the write operation, and to transition the regulator circuit to a standby state, in order to suspend the write operation.