1. An out-of-order execution in-order retire microprocessor, comprising: a branch information table, comprising N entries, each of the N entries configured to store information associated with a branch instruction; and a reorder buffer, coupled to the branch information table, comprising M entries, each of the M entries configured to store information associated with an unretired instruction within the microprocessor, wherein each of the M entries includes a field that indicates whether the unretired instruction is a branch instruction and, if so, a tag identifying one of the N entries in the branch information table storing information associated with the branch instruction; wherein N is less than M.