1. An MOS integrated circuit comprising; a. an array of CMOS devices, said CMOS devices having polysilicon gates, said array of CMOS devices comprising n-channel MOS devices and p-channel MOS devices, with a first plurality of polysilicon gates of at least some of said n-channel MOS devices connected serially to a second plurality of polysilicon gates of said p-channel MOS devices, said first plurality of polysilicon gates being doped with n-type impurities and said second plurality of polysilicon gates being doped with p-type impurities, and b. an array of n-channel ROM MOS devices, said ROM MOS devices having polysilicon gates, with the polysilicon gates of selected devices in said array being doped with p-type impurities.