1. A digital signal processor comprising: a mathematical processor; an input processor to process input signals received from a first buffer coupled to the input processor; an output processor to process output signals to be output via a second buffer coupled to the output processor; a master processor to control the mathematical processor, the input processor and the output processor, and to provide synchronization for the other processors; and a storage to store data from each of the processors so as to be accessible by each of the processors, the storage including a plurality of registers, including a first register to transfer data from the first register to a second register when new data is written into the first register.