1. A data processing device comprising an external memory for storing data defining at least part of a program in an Endian form, and an integrated circuit coupled to said external memory via a memory bus having an N-bit width, and comprising i) an embedded processor adapted to run with said program, ii) an internal memory for storing at least a bootstrap code of said program, iii) an external memory interface coupled to said memory bus and iv) a processor bus coupling said internal memory and said external memory interface to said embedded processor, wherein said external memory is arranged to store, at a chosen address, an N-bit data word having a value representative of its size, equal to N/8 bits, and of the Endian form of the stored program data, and in that it also comprises a configuration means coupled to said embedded processor and to said external memory interface and arranged to deduce from at least one part of 8 bits of said N-bit data word, read by said external memory interface at the chosen address of said external memory, the size and the Endian form of storage of said external memory and to set the width of said external memory interface according to said deduced external memory size and a data processing mode of said embedded processor according to said deduced Endian form of storage, and wherein said configuration means is arranged to generate N/8 8-bit accesses to said external memory at consecutive addresses starting from said chosen address to read at least said one part of said N-bit data word, and in that said embedded processor comprises a dedicated memory having a size equal to N and arranged to store each read part of said N-bit data word at N/8 consecutive addresses.