1. An integrated circuit architecture comprising: a first array of first memory devices disposed on a first substrate layer, the first memory devices having a first power and performance specification; a second array of second memory devices different from the first array disposed on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification; and a plurality of logic devices disposed on a third substrate layer, the plurality of logic devices being coupled to the first array and the second array.