1. An apparatus for use in performing a floating point multiply-accumulate operation, comprising: a plurality of latches that contain a plurality of operands for the operation; a carry-save adder, coupled to the latches, that receives the operands and performs a carry-save add operation on the operands to produce a first result; and a logic block, coupled to the carry-save adder, that receives the first result and performs a carry-lookahead add operation on the first result to produce a second result, the logic block having a logic circuit that performs a logic operation on the second result based upon a control signal to produce a value for use in the floating point multiply-accumulate operation.