1. A data processing unit (VPU) comprising a field of clocked logic cells (PAES) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking, wherein the clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.