1. Memory circuitry, comprising: an array of memory cells, wherein each memory cell has associated first and second data lines; and control circuitry that selectively loads new data into a given set of the memory cells in place of old data by maintaining the first and second data lines for a first part of the given set of the memory cells at a given logic value while the given set of memory cells is addressed so that the old data in the first part of the given set of memory cells is undisturbed and by maintaining the first and second data lines for a second part of the given set of memory cells at respective complementary logic values while the given set of memory cells is addressed.