1. An instruction retirement system of a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, said retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor, said retirement system comprising: (a) a first means for monitoring the status of the instructions to determine which instruction or instructions have been executed; (b) a second means, coupled to said first means, for determining whether each executed instruction is retirable; (c) a temporary buffer for storing results of instructions executed out of program order; (d) a register array, coupled to said temporary buffer, for storing retirable-instruction results; and (e) a third means, coupled to said second means, said temporary buffer, and said register array, (i) for retiring a group of said instructions determined by said second means to be retirable, by simultaneously transferring their results from said temporary buffer to said register array, and (ii) for retiring instructions executed in order by storing their results directly in said register array.