1. A method for statistically analyzing timing in a digital circuit, the method comprising: receiving a canonical form representing a timing quantity for a first timing region; propagating the form through the first timing region; collapsing a first set of terms of the canonical form; propagating the form through a second timing region; and reporting results of the statistical timing analysis to a user; wherein: the collapsed first set of terms represents one or more sources of variation sensitive to the first timing region but not sensitive to the second timing region; and the collapsing involves placing the first set of terms in a cache and replacing the first set of terms in the canonical form with a single combined term referencing the cached first set of terms.