1. A data decoder circuit, the data decoder circuit comprising: a plurality of variable nodes; a plurality of check nodes; a plurality of serial connections between the plurality of variable nodes and the plurality of check nodes; wherein the plurality of variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring member of the plurality of check nodes, wherein the plurality of check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring member of the plurality of variable nodes, and wherein the variable node to check node messages and the check node to variable node messages are passed iteratively between the plurality of variable nodes and the plurality of check nodes.