1. A processor, comprising: an instruction execution pipeline comprising a re-order buffer, register renaming circuitry and a register alias table, said register alias table to hold entries to correlate logical registers to physical registers, each of said entries having space to indicate whether its logical register to physical register correlation existed during a transition from a non speculative region of code to a speculative region of code, said speculative region of code capable of extending beyond a size of said re-order buffer such that architectural state is written to during extended speculative execution, said instruction execution pipeline having logic circuitry to perform the following upon retirement of an overwriter instruction of a logical register having an entry in said register alias table: enter an identifier of a physical register correlated to said logical register into a free list if said entry does not indicate existence of said entry during a non-speculative code to speculative code transition, said physical register freely useable after placement of its identifier into said free list; enter an identifier of a physical register correlated to said logical register into a store if said entry indicates existence of said entry during a non-speculative code to speculative code transition, said physical register not being freely useable after placement of its identifier into said store, said identifier of said physical register and an identifier of said logical register to be moved from said store back into said register alias table upon roll-back of extended speculative code execution to the end of non-speculative code execution.