1. An arrangement for partial release of a debug interface of a first programmable hardware component, the arrangement comprising: a first programmable hardware component comprising a configuration interface adapted to program the first programmable hardware component, a data interface and a debug interface that debugs and programs the first programmable hardware component; a configuration device; and a configuration memory having therein a first logic stored, the configuration device being configured to program the first programmable hardware component with the first logic, wherein the configuration device registers a programming process of the first programmable hardware component occurring via the debug interface according to a second logic and reprograms the first programmable hardware component with the first logic upon termination of the programming process occurring via the debug interface.