1. A method of transmitting data streams between (a) a reconfigurable processor device including an at least two-dimensional matrix of configurable elements having arithmetic logic units (ALUs) and (b) devices that are external to the reconfigurable processor device, the method comprising: using at least one address generator, generating addresses according to which the external data streams are addressed; and at least one of: (a) buffering write data streams by storing output write addresses and corresponding output write data in a FIFO memory system; and (b) buffering read data streams by storing output read addresses and input read data in the FIFO memory system.