1. A processor, comprising: a core including locally-gated circuitry; a decode unit including circuitry to decode a store broadcast instruction of a specified width; a local power gate (LPG) coupled to the locally gated circuitry and including circuitry to: selectively provide power to the locally-gated circuitry; activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations; deactivate power to a second portion of the locally-gated circuitry; and an execution unit including circuitry to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.