1. In a telecommunication system wherein a processor exchanges data through a controller with a mass memory, the improvement wherein said mass memory comprises: a plurality of solid-state memory modules including a first group of memory modules for the storage of a multiplicity of information words, a second group of memory modules for the storage of as many redundancy words respectively associated with said information words, and at least one spare module, the number of modules of said first group equaling the number of bits in each information word, the number of modules of said second group equaling the number of bits in each redundancy word, each of said memory modules including a multiplicity of integrated charge-transfer circuits for the continuous recirculation of respective bits, each of said charge-transfer circuits consisting of several randomly accessible blocks of series-parallel-series registers responsive to shift and transfer signals; and a command module responsive to signals from said controller for writing and reading respective bits of an information word and of an associated redundancy word at corresponding locations of selected charge-transfer circuits of all memory modules of said first and second groups, said command module including a time base emitting said shift and transfer signals, an address generator identifying said locations, and corrective logical circuitry communicating with said memory modules through an input/output unit for verifying the accuracy of bits written and read, said input/output unit comprising switching means responsive to an instruction from said controller for loading said spare module with the contents of a defective memory module of either of said groups and substituting the spare module so loaded for the defective module in subsequent reading and writing operations.