1. A microprocessor, comprising: a communication bus within the processor accessible through an external port; an execution pipeline; a pipeline satellite circuit coupling the pipeline to the bus wherein the satellite circuit enables an external agent to provide an executable instruction directly to the execution pipeline via the communication bus; and a dedicated register and register satellite circuit coupling the register to the communication bus, wherein the execution pipeline is enabled to access the dedicated register during execution of the instruction and wherein the pipeline satellite circuit and the register satellite circuit enable access of architected registers in the microprocessor through the external port.