1. An apparatus comprising a voltage boosting circuit adapted to apply a temporarily boosted voltage to a gate structure of a non-volatile memory cell during a data write operation, the memory cell comprising a programmable resistive sense element (RSE) in series with a switching device, the gate structure forming a portion of said switching device, the voltage boosting circuit comprising a capacitor which adds charge to a nominal non-zero voltage applied to the gate structure responsive to a write enable signal that facilitates the writing of data in a hard direction through the cell.