1. A device for prefetching data for a processor of a computer system, comprising: a memory controller for interfacing the processor to system memory via a system memory bus; and a prefetch cache having a short-term storage portion and a long-term storage portion included in the memory controller, the prefetch cache configured to access said system memory to retrieve and store a plurality of sequential cache lines subsequent to a processor access to said system memory, wherein the memory controller is configured to track memory accesses by a CPU to said system memory and is configured to interrupt a prefetch access to system memory upon detection of a CPU access to said system memory, wherein the short-term storage portion is configured to initially store the sequential cache lines, wherein a plurality of non-hit cache lines are transferred from the short-term storage portion to the long-term storage portion to retain the plurality of non-hit cache lines for a relatively long period in the prefetch cache, and wherein further, upon a cache line that is stored in the long-term storage portion being hit, the cache line is promoted to said CPU from the long-term storage portion.