1. A memory device, comprising: a number of logical units, wherein each of the number of logical units has a unique address; and control circuitry coupled to the number of logical units, wherein the control circuitry, in response to an operating parameter being set to a particular value and until the operating parameter changes to a different value, issues one command to move data simultaneously from more than one of the number of logical units, wherein address information associated with the one command corresponds to only one of the more than one of the number of logical units.