1. In a data processor comprising memory means containing subroutines each having low level instructions with the last instruction being an INTERPRET instruction, and high level language instructions which point to memory locations in said memory means containing the starting addresses of said subroutines said data processor having, a hardware high level language interpret capability and further comprising: first and second program counter means which point respectively to said high level language instructions and to said subroutine instructions; control and timing means responsive to said INTERPRET instruction to load said second program counter means with the subroutine starting address contained in the memory location accessed by the high level language instruction pointed to by said first program counter means; said second program counter means responsive to signals generated by said control and timing means to act as program counter and point to the instructions in said subroutine; and in which predetermined ones of said subroutines contain a BRANCH ON CONDITION ON PCI instruction which tests a condition and in which said control and timing means is responsive to said BRANCH ON CONDITION ON PCI instruction, when said tested condition is true and followed by said INTERPRET instruction, to load said first program counter means with the address contained in the next high level instruction pointed to by said first program counter means, and is further responsive to said BRANCH ON CONDITION ON PCI when said tested condition is false to increment said first program counter means to skip said next high level language instruction.