1. An information processing device comprising: a plurality of memory banks configured to store an instruction word group including a very long instruction; a program counter configured to output an instruction address indicating a head memory bank which stores a head part of the very long instruction of a next cycle; a memory bank control device configured to specify a use memory bank which is used in a next cycle and a nonuse memory bank which is not used in a next cycle from the instruction address to the very long instruction and the number of the plurality of the memory banks relating to the very long instruction to control an operation of the nonuse memory bank; an instruction decoder configured to decode the very long instruction which is fetched from the use memory bank; and an arithmetic device configured to perform the decoded very long instruction.