1. A method for determining scan lanes, the method comprising: for a set of patterns, a pattern compiler estimating a number of scan lanes to be utilized on an accelerator of a computer processor; the pattern compiler iteratively incrementing, by one scan lane, the number of the scan lanes estimated for the set of patterns to optimize a throughput of the accelerator, each of the scan lanes having been iteratively incremented comprises a group of synchronized finite state machine engines that read and modify contents of a register and an execution unit on the accelerator, wherein iteratively incrementing the number of the scan lanes comprises incrementing from a lower number of the scan lanes to a higher number of the scan lanes; the pattern compiler distributing the set of patterns to the number of the scan lanes as a distribution; the pattern compiler evaluating a size of a memory space needed for the distribution to distribute the set of patterns onto the lower number of the scan lanes versus the higher number of the scan lanes; and the pattern compiler selecting the number of the scan lanes as the lower number of the scan lanes or the higher number of the scan lanes based on which one of the lower number or the higher number has a smallest size of the memory space needed for distributing the set of patterns; wherein the number of the scan lanes selected for the set of patterns comprises a first physical scan lane through a last physical scan lane on the accelerator based on selecting the number of scan lanes as the lower number or the higher number; wherein a result processor comprises the register and the execution unit; wherein the group of engines is a same number in each of the first through the last physical scan lanes; wherein the group of engines in one of the first through the last physical scan lanes do not physically connect to the execution unit and the register in another one of the first through the last physical scan lanes.