1. A circuit design data path optimization method comprising: obtaining a limit upon clock cycle duration applicable to the circuit design; determining for a register in the circuit design, from structural cycles in which the circuit element is a constituent, a limit upon addition of structural cycle delay to such structural cycles, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration; determining combinational slack for a combinational path in the circuit design; using a limit upon addition of structural cycle delay determined for the register and combinational slack determined for the combinational path to identify a change in a data path in the circuit design involving both a combinational logic change and register retiming; and making the identified change in the circuit design involving both the identified combinational logic change and the identified register retiming.