1. A method for creating a system for verifying a digital circuit design using a testbench that comprises an HDL component and an HAL component, the method comprising: synthesizing the digital circuit design into a structural model; transforming the HDL component of the testbench into a structural model maintaining exact simulation semantics, wherein the structural model includes a plurality of finite state machines (FSMs) corresponding to timed and untimed parallel blocks of code in the behavioral model; mapping the FSMs onto a reconfigurable hardware platform; and automatically synthesizing a communication interface between the FSMs running on the reconfigurable hardware platform and the HAL component of the testbench running on a sequential computation platform.