1. A computer system for applying stress conditions to a chip device comprising an integrated circuit during accelerated stress testing, the computer system comprising: one or more computer processors, one or more computer-readable storage media, and program instructions stored on the one or more of the computer-readable storage media for execution by at least one of the one or more processors, the program instructions comprising: program instructions to partition the integrated circuit into a first region having a first functional element; program instructions to partition the integrated circuit into a second region having a second functional element; program instructions to apply a first stress condition to the first functional element until the first functional element is no longer operational; program instructions to apply a second stress condition to the second functional element until the second functional element is no longer operational; program instructions to measure a first time period between starting the program instructions to apply the first stress condition and when the first functional element is no longer operational; program instructions to measure a second time period between starting the program instructions to apply the second stress condition and when the second functional element is no longer operational; and program instructions to derive an acceleration model parameter based on the first stress condition and the corresponding first time period, and the second stress condition and the corresponding second time period.