1. A memory controller controlling a NAND memory having D bits/cell, comprising: a code encoder which generates a code word having correction capability of t symbols by performing an error correction coding process based on an information data which is to be written in the NAND memory; a write control unit which controls writing of the code word to the NAND memory; a read control unit which controls reading of the code word from the NAND memory; a code decoder which decodes the code word read from the NAND memory; and a memory interface which performs writing in the NAND memory and reading from the NAND memory, wherein the write control unit dispersedly allocates 2×D pages stored in adjacent two word lines in a block of the NAND memory to 2×D/t or more code words, sets the number of pages allocated to the one code word among the 2×D pages to t or less pages, controls writing so that data stored in L (L is an integer of one or more) blocks of the NAND memory are included in the one code word, and wherein n is code length, and L is smaller than n/t.