1. A microprocessor comprising: (a) a first instruction pipeline for executing a first instruction, said first instruction being a member of an instruction set; (b) a second instruction pipeline for executing in a first clock cycle a second instruction in parallel with execution of the first instruction, said second instruction being a member of a subset of said instruction set; (c) an apparatus for pairing the first and second instructions for parallel execution comprising: (i) a plurality of comparators for comparing a destination register of the first instruction with each register used to execute the second instruction, each of said plurality of comparators having a respective output; (ii) a plurality of AND gates, each of said AND gates receiving a first input from a corresponding one of the comparator outputs and a second input indicating that a valid register field is identified in one of the first and second instructions, each of said AND gates having a respective output; (iii) an OR gate receiving as inputs all of the outputs of said AND gates, said OR gate having an output; (d) pipeline control logic coupled to the output of said OR gate for enabling parallel execution of the first and second instructions in said first clock cycle if and only if conditions for parallel execution of instruction pairs are met, said conditions for parallel execution of instruction pairs being (1) the destination register of the first instruction is different from all of the registers used to execute the second instruction and (2) all register fields identified in the first and second instructions are valid, wherein, when said conditions for parallel execution of instruction pairs are not met, only said first instruction is executed in said first clock cycle and said microprocessor executes said second instruction in parallel with a third instruction during a second clock cycle following said first clock cycle if said second and third instructions meet said conditions for parallel execution of instruction pairs.