1. A digital processing device implemented on a single semiconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; a first inhibit logic means connected between said nonvolatile memory means and said information transfer means for selectively inhibiting transfer of data and instructions from said nonvolatile memory means to said information transfer means; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one security bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said information transfer means for transfer of data and instructions between said digital processing device and at least one external device; an external interface inhibit logic means connected to said external interface means for selectively inhibiting transfer of data and instructions by said external interface means; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said first inhibit logic means, said external interface inhibit logic means, said at least one security bit register and said central processing unit for determining when an instruction is being fetched and further connected to said instruction acquisition logic to indicate when a protected status portion of said nonvolatile memory means is being accessed and for selectively causing said first inhibit logic means and said external interface inhibit logic means to inhibit data and instruction transfer upon performance of selected operations by said central processing unit, thereby preventing unauthorized access to data and instructions stored in said protected, status portion of said nonvolatile memory means.