1. A fabrication method of copper interconnects using dual damascene processing, comprising: providing doped amorphous silicon or polysilicon as an active surface; selectively depositing palladium on the silicon by immersion plating technique; depositing a layer of cobalt phosphorus or alloy cobalt/nickel phosphorus or nickel phosphorus on the palladium layer using electroless plating technique; cobalt/phosphorus, cobalt nickel phosphorus alloy, or nickel phosphorus layer serves as a copper diffusion barrier; filling up via and trench by copper from electroless copper plating; and removing excess copper and planarize/polish the copper/dielectric surface.