1. An apparatus for determining page faulting behavior of at least two memory operations of a subject code block represented by an intermediate representation and a subject order list, the apparatus comprising: an inspector component for identifying, from the intermediate representation and subject order list, a first object node having a first dependency path and second object node having a second dependency path; a calculation component for calculating a numerical difference between a first addressing value and a second addressing value, the first and second addressing values respectively associated with the first and second dependency paths; and a dependency generator for ordering the subject order list in an object dependency non-page-faulting order, in response to the numerical difference being equal or less than an assigned memory page size.