1. A method for cache management in a processor with a cache, the method comprising: receiving a bulk memory modification instruction; identifying one or more data blocks of the cache associated with the bulk memory modification instruction; and updating a cache coherence state of the identified one or more data blocks, wherein the updated cache coherence state is indicative of a zero value of the one or more data blocks, and wherein the cache coherence state of the identified one or more data blocks is updated without modification to a cache data array.