1. In a branch cache system for a pipelined processor having overlapping parcel prefetch and execution stages, the improvement comprising plural memory set means, for storing plural indexed sets of branch address prediction data words, each of said address prediction data words being representative of branch address predictions, and control circuitry means, connected to said plural memory set means, for determining whether there is stored in said plural memory set means an address prediction data word corresponding to a branch instruction fetched by said prefetch stage, and for causing, a responsive to detection of a data word corresponding to said branch instruction, said execution stage to execute said branch instruction to the branch address represented by said data word.