1. A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor; an instruction code register for storing an instruction code supplied from said CPU, means for determining whether the instruction code currently stored in said instruction code register requires instruction code switching, and storing a signal representing a determination result, a register for storing an instruction code switching signal resettable from said CPU, and modification circuit means for modifying an output form said instruction code register on the basis of outputs from said determining means and said register and for outputting a modified signal.