1. A data processor for emulating an instruction-handling processor, the data processor comprising: a cache memory comprising a plurality of cache lines and holding a plurality of instructions; a single vector processor for emulating a pipelined execution, the single processor being configured to operate in both an instruction preparation stage and an instruction execution stage; the instruction preparation stage comprising: selecting two or more instructions from the plurality of instructions, the number and position of instructions being selected so that the two or more instructions are retrieved from the same cache page, and generating a group of prepared instructions from the selected instructions, and the single processor is configured, during the instruction execution stage, to complete execution of each of the prepared instructions in the group serially in an instruction order; wherein, during the instruction preparation stage, the single vector processor is configured to fetch the two or more instructions in parallel.