1. A specialized processing block for a programmable integrated circuit device having a plurality of instances of said specialized processing block, each instance of said specialized processing block comprising: multiplier circuitry that performs at least one multiplication and provides partial sum/carry signals for each said at least one multiplication; a chain output for propagating partial sum/carry signals to any other of said instances of said specialized processing block; a chain input for receiving partial sum/carry signals propagated from any other of said instances of said specialized processing block; combining circuitry that combines said partial sum/carry signals for each said at least one multiplication and any said partial sum/carry signals propagated from any other of said instances of said specialized processing block, for propagation to said chain output; and circuitry for programmably routing signals within said specialized processing block.