1. A decode unit for a processor, comprising: an input for an element of machine code representing an instruction, wherein the element of machine code comprises identifying data for two or more elements, selected from an ordered set; and circuitry configured to: responsive to an opcode identifier portion of the element of machine code identifying a virtually-encoded instruction, use both the opcode identifier portion and at least part of a remaining portion of the element of machine code to decode the element of machine code into data defining an executable operation for execution on an execution unit coupled with the decode unit, wherein a relative order in which the identifying data for the two or more elements appears in the element of machine code is used to determine the operation to be executed.