1. A static noninverting memory cell for a one propagation delay memory circuit, which comprises: (a) a first field effect transistor having a gate, source, and drain; (b) a second field effect transistor having a gate, source, and drain; (c) means for connecting a drain voltage supply to the drain of said first transistor; (d) means for connecting the gate of said first transistor to an input signal; (e) means for connecting the source of said first transistor to the drain of said second transistor; (f) means for connecting the source of said first transistor, and the drain of said second transistor, to another input signal; (g) means for connecting the gate of said second transistor to a constant voltage reference source; (h) a third field effect transistor having a gate, source, and drain; (i) means for connecting the drain voltage supply to the drain of said third transistor; (j) means for connecting the gate of said third transistor to the source of said third transistor; (k) means for connecting the source-gate of said third transistor to the drain of said second transistor, and the source of said first transistor; (l) a fourth field effect transistor having a gate, source, and drain; (m) means for connecting the drain voltage supply to the drain of said fourth transistor; (n) means for connecting the gate of said fourth transistor to the source-gate of said third transistor, and the source-drain of said first and second transistor, respectively; (o) means for connecting the source of said fourth transistor to the source of said second transistor; (p) a diode having a cathode and an anode; (q) means for connecting the anode of said diode to the source of said second, and said fourth, transistor; (r) a fifth field effect transistor having a gate, source, and drain; (s) means for connecting the cathode of said diode to the drain of said fifth transistor; (t) means for connecting the gate of said fifth transistor to the source of said fifth transistor; (u) means for connecting the gate-source of said fifth transistor to a source voltage supply; (v) said third, fourth, and fifth field effect transistors, and said diode defining a memory section in which a logic state may be retained; and (w) output means connected at a location between the cathode of said diode and the drain of said fifth transistor and responsive to said memory section for sensing the logic state retained therein.