1. An arrangement for vector permutation in a single-instruction multiple-data microprocessor, the arrangement comprising: a vector register file; a permutation logic block coupled to receive and permutate vectors from at least one vector register of the vector register file according to control parameters, the permutation of the vectors being a side operation of an instruction; a plurality of control registers separate from the vector register file, each of the plurality of control registers being coupled to selectively provide control parameters to the permutation logic block; and a controller coupled between the plurality of control registers and the permutation logic block and arranged for selecting by an order one of the plurality of control registers and for providing the control parameters from the selected one of the plurality of control registers to the permutation logic block.