1. A digital hardware logic system for exchanging information between an array of processing cores for processing a set of data processing tasks and task-specific memory segments, the system comprising: a first set of multiplexers, wherein each multiplexer is specific to one of the task-specific memory segments; a second set of multiplexers, wherein each multiplexer is specific to one of the cores of the array; and a hardware logic module, referred to as a controller, which is configured to repeatedly assign individual cores of the array to process individual tasks among said set and provide input selection configuration for at least one multiplexer among said first and second set of multiplexers.