1. An incremental logic synthesis method executed by a computer, for synthesizing an up-dated gate-level logic circuit which performs up-dated functions of current functions which are performed by a current gate-level logic circuit so that part thereof is used in the up-dated circuit, wherein the current circuit may include a modification to an original gate-level logic circuit synthesized by a computer for performing the current functions, said method comprising the steps of: (a) synthesizing an intermediate gate-level logic circuit which performs the up-dated functions, in response to input data describing the up-dated functions; (b) synthesizing the up-dated circuit in response to data describing the synthesized intermediate circuit and to data describing the current circuit, wherein the synthesizing step includes the steps of (b1) identifying a corresponding-portion pair which includes a first portion within the current circuit and a second portion within the intermediate circuit, wherein the first and second portions are mutually equivalent, and (b2) combing the first portion within the current circuit with a portion other than the second portion, within the intermediate circuit, so as to obtain the up-dated circuit as a result of the combining.