1. In a computer aided design system capable of simple parameter passing, a method for generating a hierarchical netlist for a circuit schematic hierarchically diagramed from a leaf level to a top level, the method comprising machine executed steps of: (a) starting from the leaf level; (b) identifying all components having property values defined by algebraic expressions which contain references to variables defined at a higher level in the hierarchy; (c) gathering all occurrences of said algebraic expressions in a list; (d) replacing each algebraic expression in a line in the hierarchical netlist with a macro argument token, said token identifying an associated member of said list; (e) evaluating an expression when said expression does not contain references to a variable on a higher level of hierarchy; (f) moving up the hierarchy to a parent level above the leaf level, and repeating steps (b) through (e) until all expressions have been evaluated.