1. A method for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task execution queue, and a low priority task execution queue, the method including the steps of: (a) allocating all tasks controlled by the software executive to the low priority task execution queue; (b) allocating all software interrupts to the low priority interrupt execution space; (c) allocating all tasks controlled by the high priority scheduler of the hardware executive to the high priority task execution queue; and (d) allocating all hardware interrupts to the high priority interrupt execution space; whereby all low priority tasks are under the control of the software executive and all high priority tasks are under the control of the hardware executive, thereby permitting hardware processes within the microprocessor to be serviced by the hardware executive as high priority tasks without interruption by tasks under the control of the software executive.