1. A central processing unit (CPU) comprising: instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction; at least one register to store a plurality of 16-bit data elements to be operated upon by the SIMD shift instruction; and a barrel shifter to concurrently shift the plurality of 16-bit data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction being performed.