1. A microprocessor configured to natively translate and execute instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA, the microprocessor comprising: an execution pipeline; a hardware instruction pre-processing and translation apparatus coupled to the execution pipeline, the hardware instruction pre-processing and translation apparatus comprising an instruction formatter and an instruction translator; and wherein the instruction formatter is configured to extract distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and format them; wherein the instruction formatter includes an ARM instruction length decoder that is configured to decode ARM instruction bytes and determine instruction lengths of ARM instructions; wherein the instruction formatter is configured to extract distinct x86 instruction bytes from a stream of instruction bytes received from an instruction cache and format them; wherein the instruction formatter also includes an x86 instruction length decoder that is configured to decode x86 instruction bytes and determine instruction lengths of x86 instructions; wherein the instruction translator is configured to translate the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor; and wherein the execution pipeline is configured to execute the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.