1. A stacked memory device comprising: a memory stack including one or more layers of dynamic random-access memory (DRAM); and a system element coupled with the memory stack, the system element including: a memory controller for control of the memory stack, and repair logic coupled with the memory controller to provide generic redundancy repair for the memory stack, wherein the repair logic includes: a repair logic memory for storage of repair addresses that have been identified as failing addresses and of data corresponding to the repair addresses, the repair logic memory including an input to receive operation addresses and data from the memory controller and an output to provide stored data corresponding to repair addresses, wherein the repair logic is to generate an enable signal with a value based on whether a received operation address from the memory controller matches any of the repair addresses stored on the repair logic memory, a latch device including an input to receive operation addresses and data from the memory controller and an output coupled with the memory stack, the output of the latch device being enabled or disabled based on the enable signal, and a multiplexer including a first input to receive data from the memory stack, a second input to receive data from the repair logic memory, and an output to provide data to the memory controller, wherein the multiplexer is configured to choose either the first input or the second input as the output of the multiplexer based on the enable signal; wherein the repair logic is configured to: receive a memory operation request including an operation address from the memory controller, process the memory operation request using the memory stack if the operation address does not match any of the repair addresses stored in the repair logic memory, and process the memory operation request using the repair logic memory if the operation address matches any of the repair addresses stored in the repair logic memory.