1. A device for simultaneously detecting more than one condition, each said condition corresponding to a specific memory cell of an array of more than one memory cell, each said specific memory cell of said array having a distinct index given by a first number of bits and a distinct associativity given by a second number of bits, each said condition triggering a particular, distinct task, and prioritizing each said task, if more than one, comprising: more than one input signal, each said input signal being relative to and indicative of said condition for one said specific memory cell; circuitry for simultaneously receiving each said more than one input signal and logically determining said distinct associativity and said distinct index for each said specific memory cell and prioritizing each said task dictated by each said condition indicated by each said input with respect to each other said task dictated by each other said condition indicated by each other said input; and output signals for sequentially outputting each said distinct associativity and said distinct index for each specific memory cell in the order of prioritization of each said task.