1. A memory controller for a plurality of banks of memory, the memory controller including an interface connectable to a bus to communicate with a processor, the memory controller redundantly mapping the plurality of banks of memory to a memory space and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space and/or one or more of the plurality of banks of memory, wherein, responsive to receipt at said interface of a request from said processor for one of said memory operators, the memory controller is configured to execute, independently of the processor, the respective memory operator on the memory space and/or one or more of the plurality of banks of memory.