1. A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions to a plurality of execution units during each single processor cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, said method comprising the steps of: providing a plurality of intermediate storage buffers within said superscalar processor system; during said single processor cycle: determining if an appropriate one of said plurality of execution units is available for execution of a selected one of said multiple scalar instructions; determining if a destination operand within a preceding one of said multiple scalar instructions is equal to a source operand within said selected one of said multiple scalar instructions; assigning a particular one of said plurality of intermediate storage buffers to said destination operand within said selected one of said multiple scalar instructions; and dispatching said selected one of said multiple scalar instructions to said appropriate one of said plurality of execution units in response to said availability thereof, said assignment of said particular one of said plurality of intermediate storage buffers to said destination operand and an assignment of another one of said plurality of intermediate storage buffers to said destination operand within said preceding one of said multiple scalar instructions wherein results of execution of said selected one of said multiple scalar instructions may be written to said particular one of said plurality of intermediate storage buffers.