1. An apparatus comprising: memory access hardware logic to refer to an entry in a memory access data structure to translate a guest physical address to a host physical address, the guest physical address stored in a first field of the entry and the host physical address stored in a second field of the entry, and to determine whether to allow a direct memory access to the host physical address based on a value stored in a third field of the entry; and transaction hardware logic to assign direct cache access attributes to a transaction to the host physical address, the direct cache access attributes stored in a fourth field of the entry, and to encode the transaction based on the direct cache access attributes.