1. A method, in a data processing system, for predicting effects of soft errors on an integrated circuit device design, comprising: configuring the data processing system to implement a unified derating tool, wherein the unified derating tool comprises a machine derating front-end engine used to generate machine derating information for the integrated circuit device design, and an application derating front-end engine used to generate application derating information for the integrated circuit device design; executing in the data processing system, by the unified derating tool, the machine derating front-end engine on a simulation of the integrated circuit device design to generate the machine derating information; executing in the data processing system, by the milled derating tool, the application derating front-end engine to execute an application workload on existing hardware and inject a fault into the existing hardware during the execution of the application workload on the existing hardware to generate the application derating information ,wherein the application workload is not simulated but actually executed on the existing hardware, wherein the integrated circuit device design comprises a new processor chip design, and wherein the existing hardware comprises an existing fabricated processor chip in a same family of processor chips as the new processor ship design; and combining, by the data processing system, the machine derating information with the application derating information to generate at least one soft error rate (SER) value for the integrated circuit device design.