1. An event signalling system for a digital signal processor apparatus which has a central data RAM having a plurality of data buffers, a data RAM bus having address and data lines coupled to the central data RAM, a computing processor coupled to said central data RAM, and a data I/O processor coupled to the data RAM bus, wherein said data I/O processor receives data from external said digital signal processor apparatus and writes that data via said data RAM bus to at least one of said data buffers of said central data RAM associated with said I/O processor, the event signalling system comprising: a) address code generating means in said data I/O processor for generating a predetermined address code other than an address code of said at least one data buffer associated with said I/O processor and for writing said predetermined address code onto said address lines of said data RAM bus each time said data I/O processor fills its associated at least one data buffer; b) a data RAM bus address decoder coupled to said address lines of said data RAM bus for monitoring said address lines of said data RAM bus for said predetermined address code, and for generating a signal when said predetermined address code is written to said address lines of said data RAM bus; c) event occurrence circuitry in said computing processor, wherein said computing processor writes to and reads from said central data RAM; and d) a flag bus coupled to said data RAM bus address decoder and to said event occurrence circuitry, for transmitting said signal generated by said data RAM bus address decoder to said event occurrence circuitry of said computing processor to indicate to said computing processor the occurrence of the filling of a said data buffer associated with said I/O processor as indicated by said I/O processor, wherein said signal generated by said data RAM bus address decoder to said event occurrence circuitry is broadcast over said flag bus, and said event occurrence circuitry which receives said broadcast signal permits said computing processor to ascertain that said at least one data buffer associated with said I/O processor has been filled.