1. A circuit arrangement, comprising: a processing unit; a memory address translation data structure for use in performing memory address translation for instructions in an instruction stream being executed by the processing unit, wherein the memory address translation data structure includes a decode-related attribute associated with an instruction from the instruction stream, wherein the instruction is associated with an address at which the instruction is stored in an address space, and wherein the decode-related attribute is accessed using at least a portion of the address; and decode logic configured to access the decode-related attribute in the memory address translation data structure and decode at least a portion of an opcode for the instruction using the decode-related attribute.