1. A computer-implemented method, comprising: encountering a store operation during a compile-time of a program, the store operation applicable to a memory line; determining that a last processing element to access the memory line prior to the store operation is part of an accelerator; and generating, during the compile-time of the program, a store-without-coherence-action instruction for the store operation, responsive to the last processing element to access the memory line prior to the store operation being part of the accelerator; wherein the store-without-coherence-action instruction specifies that the store operation be performed without a cache coherence action, and wherein cache coherence is maintained upon execution of the store-without-coherence-action instruction.