1. A processor, comprising: a front end including a first logic to receive an instruction and to dispatch the instruction to a binary translator; an execution pipeline; and a binary translator including a second logic to: determine whether the instruction includes a control-flow instruction; identify a source address of the instruction; identify a target address of the instruction, the target address including an address to which execution would indirectly branch upon execution of the instruction; determine whether the target address is a known destination based upon the source address; and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address.