1. An apparatus comprising: an array of memory cells in a package; volatile memory configured to store defective address data responsive to entering a soft post-package repair mode; non-volatile memory configured to store other defective address data; a match logic circuit configured to generate a match signal indicating whether address data corresponding to an address of the array to be accessed matches the defective address data stored in the volatile memory; and a decoder configured to select a first portion of the memory cells of the array to be accessed instead of a second portion of the memory cells of the array responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory, wherein the second portion of the memory cells of the array corresponds to a replacement address for the address of the array to be accessed associated with the other defective address data stored in the non-volatile memory.