1. A method for a first data processor to coordinate, via a communication bus, execution by a second data processor of an instruction received by said first processor for execution thereby, using only standard bus cycles on said communication bus, said instruction including a type field indicative of instruction type, the method comprising the steps of: receiving said instruction; writing to said second processor at a unique address within the address space of said first processor, using said standard common bus cycles, at least the type field of said received instruction; immediately reading a response from said second processor at said unique address using said standard bus cycles after said second processor has received said type field on said received instruction; examining said response; selectively performing a predetermined task selected by said response when said response indicates that said task must be performed by said first processor in support of the execution of said instruction by said second processor; but vectoring to a predetermined exception handler when said response selects a task other than said predetermined task must be performed by said first processor in support of the execution of said instruction by said second processor.