1. A method of performing a design rule check on a layout for an integrated circuit (IC) comprising the steps of: (a) providing at least a first set of design rules for a first region of the layout; (b) providing at least a second set of design rules for a second region of the layout; wherein said first region and said second region correspond to different types of circuitry to be embodied in the IC; (c) processing a layer of the layout such that any said first region is checked in accordance with at least said first set of design rules, and said second region is checked in accordance with at least said second set of design rules.