1. A memory device, comprising: an array of bitcells, each bitcell having two elements including a single antifuse element for storing a bitcell state and a single access element for providing access to the antifuse element for bitcell programming and readout; and power select circuitry for biasing a gate line of the array to a first voltage level for bitcell programming and a second voltage level for bitcell readout, the gate line connected to at least one of the antifuse elements.