1. An apparatus comprising: a polynomial register having a plurality of bits, configured to store a user-defined polynomial; a first bus; a second bus; a transceiver coupled to the first bus, the second bus, and the polynomial register, the transceiver including: a pseudorandom bit sequence (PRBS) generator configured to generate a PRBS signal based on the user-defined polynomial; and a PRBS checker configured to generate an error signal from a received signal using the user-defined polynomial, the PRBS checker including: a first matrix circuit configured to include a first matrix corresponding to the user-defined polynomial; a second matrix circuit configured to include a second matrix corresponding to the user-defined polynomial; a first multiplier coupled to the second matrix circuit and configured to receive an input associated with the first bus; a data register configured to receive the input associated with the first bus; a second multiplier coupled to the first matrix circuit and the data register; an XOR circuit coupled to the first and second multipliers; and an error counter coupled to the XOR circuit.