1. A processor comprising: a decoder to decode an instruction into a decoded instruction; and an execution unit to execute the decoded instruction to: apply a read mask against a first input vector operand to extract a first set of elements of the first input vector operand for operation, and against a second input vector operand to extract a second set of elements of the second input vector operand for operation, create an output vector having multiple instances of a scalar result of an operation performed on the first set of elements and the second set of elements, and apply a write mask, different than the read mask, against the output vector to create a resultant vector, wherein the operation: adds the first set of elements together to produce a first sum, adds the second set of elements together to produce a second sum, and multiplies the first sum and the second sum to produce the scalar result, multiplies the first set of elements together to produce a first product, multiplies the second set of elements together to produce a second product, and adds the first product and the second product to produce the scalar result, adds the first set of elements together to produce a first sum, adds the second set of elements together to produce a second sum, and divides the first sum by the second sum to produce the scalar result, or multiplies the first set of elements together to produce a first product, multiplies the second set of elements together to produce a second product, and divides the first product by the second product to produce the scalar result.