1. A locally synchronous shared built in self test (BIST) architecture for testing a plurality of embedded memories comprising: a programmable master controller configured to initialize testing by generating and controlling a plurality of control signals; one or more memory wrappers operatively coupled to the programmable master controller and configured to execute the plurality of control signals; and an interface coupled to the programmable master controller and the one or more memory wrappers for the initializing, wherein said interface comprises a globally asynchronous locally synchronous (GALS) interface.