1. An apparatus comprising: a dispatch queue configured to store and dispatch decoded instructions to a scheduler; a microcode engine; a microcode engine input queue; one or more microcode output queues configured to store micro-ops generated by the microcode engine; and circuitry configured to: scan the dispatch queue for microcode instructions responsive to determining the microcode engine is not currently cracking a microcode instruction; scan the dispatch queue for microcode instructions responsive to determining the microcode engine input queue is empty; detect a given microcode instruction within the dispatch queue; and convey the given microcode instruction to the microcode engine prior to the given microcode instruction being ready for dispatch from the dispatch queue; wherein the microcode engine is configured to: crack the given microcode instruction into one or more micro-ops; and store the one or more micro-ops in a microcode output queue of the one or more microcode output queues; wherein in response to detecting a next instruction to be dispatched from the dispatch queue is the given microcode instruction, the one or more micro-ops are conveyed from the microcode output queue for execution.