1. An apparatus for producing a branch-trimming and instruction grouping and ungrouping comprising: an adaptive microprocessor as an adaptive hardware component; and convert a microprocessor to an adaptive microprocessor by integrating adaptive hardware components including adaptive instruction memory, adaptive pre-fetch/fetch units, and adaptive instruction decoder; pre-fetch/fetch grouped and ungrouped instructions from the adaptive instruction memory to the adaptive pre-fetch/fetch units; load adaptive microware code from the adaptive instruction memory to the adaptive instruction decoder via the adaptive pre-fetch/fetch units; load adaptive configware code from the adaptive instruction memory to the adaptive instruction decoder; identify and decode both of the non-grouped and grouped instructions differently in the adaptive instruction decoder; fetch and use pre-decoded sequences of control words and decoding information of the grouped instructions from the instruction memory via the adaptive pre-fetch/fetch units, instead of decoding the non-grouped instructions; generate sequences of control words and extract decoding information of the non-grouped instructions through the decoding hardware in the adaptive instruction decoder; execute the operations of the non-grouped and the grouped instructions including the branch-trimmed instructions from the software program at the same back-end processing engines of the microprocessor; continue to use different instruction sets including grouped instructions after fabrication of the adaptive microprocessors; be implemented by using reconfigurable devices, such as field-programmable gate array (FPGA) and/or be fabricated in the form of application-specific integrated circuit (ASIC); and adaptive compilers as adaptive software components.