1. A method for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage, characterized by the steps of: a) operating at least one logic stage of relatively high switching activity implemented in static hardware logic and at least one logic stage of relatively low switching activity implemented in dynamic hardware logic, b) operating a predetermined stage with an input ( 60 , 62 ) directly obtained from a stage being positioned earlier than a preceding bypass stage preceding said predetermined stage, in order to avoid input from said earlier stage into said bypass stage.