1. A shared write back buffer, comprising: a plurality of address inputs, wherein each said address input is configured to receive an address data originating from one of a plurality of processing units; a plurality of storage data inputs, wherein each said storage data input is configured to receive a storage data originating from one of said plurality of processing units, each said address data being associated with one of said storage data; a data bank that includes a plurality of data registers; an address bank that includes a plurality of address registers; and an output port that is configured to provide said storage data from said data bank to said main memory.