1. A microprocessor apparatus, providing for write back and invalidation of a block of data from cache to memory, the apparatus comprising: translation logic, configured to translate a block write back and invalidate instruction into a micro instruction sequence that directs a microprocessor to write back and invalidate a specified number of cache lines; and execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus that write back data corresponding to said specified number of said cache lines.