1. A microprocessor having delayed instructions comprising: an instruction decoder for decoding instructions including said delayed instructions; and an instruction execution section for executing said instructions according to output transferred from said instruction decoder, wherein said instruction execution section comprises a program counter controller (PC controller) for controlling a program counter value and said PC controller comprises delayed branch instruction storing means for storing values indicating target branch addresses of delayed branch instructions as said delayed instructions and a program counter value related to a delayed value specified by said delayed branch instructions.