1. A processor comprising: an interface to access a memory, wherein a region in the memory is user memory; execution hardware to execute an instruction; control logic to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode; a paging unit, wherein the paging unit is to translate a linear address to a physical address using a page table hierarchy, and the region may be designated as user memory by a flag at any level in the page table hierarchy; and wherein the execution unit is also to execute a processor identification instruction by returning an indication that the processor includes control logic to prevent the processor from executing from user memory when the processor is in supervisor mode.