1. An integrated circuit comprising: a first memory comprising a first set of test routines; a processing core, wherein the processing core is configured to test a first one or more components of the integrated circuit using the first set of test routines; and an interface, wherein the processing core is configured to receive, via the interface and from a second memory that is external to the integrated circuit, firmware, wherein the firmware is configured to replace at least a part of the first set of test routines to generate a second set of test routines, wherein the second set of test routines is stored in the first memory, and wherein the processing core is configured to test a second one or more components of the integrated circuit using the second set of test routines.