1. A circuit having an input means for receiving instructions, an output data bus, and output means for generating an audible tone, said circuit for the synthesization of a plurality of audible tones comprising: a central processor coupled to said input means for transferring and manipulating digital information in a selectively controlled and timed sequence; a frequency register coupled to said central processor for storing a tone number indicative of one of said plurality of audible tones; frequency/address generator means for generating a plurality of addresses at a rate in response to said tone number, said frequency/address generator means including digital integrating means for generating an increment in address by integrating said tone number over time and generating said increment when integration of said tone number equals a predetermined magnitude, said frequency/address generator means being coupled to said frequency register; waveform memory means for storing and writing a plurality of binary numbers indicative of waveform on said output data bus, said frequency address generator means being coupled to said waveform memory means, said waveform memory means writing said plurality of binary numbers in response to said plurality of addresses, said data bus being coupled to said output means, said output means generating one of said plurality of audible tones in response to said plurality of binary numbers coupled thereto, whereby tone frequency is determined by the rate at which said waveform memory means is collectively read and waveshape is determined by the stored contents of said waveform memory means.