1. A computing device for memory encryption, the computing device comprising: one or more processors; one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the computing device to: determine, at each cache write operation in the one or more memory devices, that a reference probability is satisfied; generate a keyed hash of a data line based on a statistical counter value and a memory address to which to write the data line, wherein the statistical counter value is incremented in response to the determination; store the keyed hash to a cache line, wherein the cache line includes a plurality of keyed hashes and each of the keyed hashes corresponds with a different data line; and encrypt the data line based on the keyed hash, the memory address, and the statistical counter value.