1. A circuit for use in conjunction with a memory controller for an integrated circuit memory device incorporating a primary memory array and a secondary cache memory, said memory device additionally including a last row accessed register for indicating an address of the last row accessed in said memory device by an associated data processor, said last row accessed register being adapted to receive a clocking signal to cause said last row accessed register to register therein an address signal applied thereto, said circuit comprising: an n-bit register having a data input bus coupled to receive said address signal and a clock terminal coupled to receive said clocking signal to cause said address signal to be inputted into said n-bit register, said n-bit register further having an output bus for supplying a last accessed address signal registered in said n-bit register; an n-bit comparator having first and second input terminals coupled respectively to said data input and output busses of said n-bit register, said n-bit comparator providing a first cache signal to said controller when said address and output signals are coincident and a second cache signal to said controller when said address and output signals are not coincident; and an additional register having a data input terminal coupled to receive a write/read operation signal from said associated data processor indicative of either a write or read operation to said memory device by said data processor and a clock terminal coupled to receive an operation cycle signal, said additional register having an output terminal for supplying an output signal to said controller representative of a previous state of said write/read operation signal when said operation cycle signal is in a predetermined binary state; whereby said controller is enabled to support both cache reads and page-mode writes for said memory device.