1. A processor comprising: an instruction execution unit that executes an instruction; a branch prediction unit that stores history information and weight tables including weights corresponding to instructions, before an instruction fetch of a branch prediction target instruction is performed, obtains the history information and the weights related to instruction fetches performed a certain number of times before the instruction fetch of the branch prediction target instruction, performs a weight product-sum operation using the obtained history information and weights, and at the time of the instruction fetch of the branch prediction target instruction, performs an operation of a result obtained by the weight product-sum operation and a weight of the branch prediction target instruction, and predicts the branch prediction target instruction to be branch-taken or branch-not-taken, the history information indicating every instruction fetch performed the certain number of times whether the instruction predicted as branch-taken is included, and the weight tables including the weights to be obtained by search using indexes based on addresses of the instruction fetches.