1. An integrated circuit comprising: a branch cache that stores, in a single branch cache entry, branch information about a primary branch and a secondary branch, the branch information including a branch target address for the primary branch in an instruction fetch block and an address offset of the secondary branch in the instruction fetch block; and a branch prediction logic module that calculates a branch target address for the secondary branch in the instruction fetch block based on the address offset of the secondary branch and a predicted branch direction of the secondary branch.