1. A hardwired core embedded in an integrated circuit, the hardwired core comprising: a microprocessor, wherein the integrated circuit comprising the hardwired core with the microprocessor comprises programmable circuitry capable of being coupled to the hardwired core by programming of programmable interconnects of the programmable circuitry, wherein the programmable circuitry is programmable to implement a user circuit design; a crossbar interconnect coupled to processor local buses of the microprocessor; the crossbar interconnect providing pipelines for coupling the hardwired core to the programmable circuitry; a memory controller interface coupled the crossbar interconnect; the memory controller interface configurable for communication with a memory controller external to the hardwired core and capable of being coupled to the memory controller via the programmable circuitry of the integrated circuit; the microprocessor, the crossbar interconnect, and the memory controller interface all capable of operating at a first frequency of operation; the memory controller interface further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation, wherein the second frequency is different from the first frequency; and the crossbar interconnect configured to direct first transactions initiated by the microprocessor from one or more of the processor local buses to the memory controller interface for accessing one or more memory devices coupled to the memory controller.