1. A system comprising: a first memory module; a second memory module coupled to the first memory module via a first interface; and a host processor coupled to the first memory module via a second interface different from the first interface, wherein the host processor is configured to cache data in the first memory module, and wherein the first memory module is external to the host processor; wherein the system is configured to: transfer data between the host processor and the first memory module via the second interface; transfer data between the first memory module and the second memory module via the first interface without consuming bandwidth on the second interface; and send a retry signal from the first memory module to the host processor responsive to the host processor requesting data that is not stored in the first memory module, wherein the retry signal causes the host processor to resend a request to the first memory module at a later point in time.