1. A data processing system comprising a central processor unit for processing address words and data words and at least one memory unit connected in communication with said central processor unit for storing address words and data words, said central processor unit including a skew protected quadriport register file having first and second read ports and first and second write ports for permitting the writing of information into said register file subsequent to the reading of information therefrom during the same processor cycle has been inserted; an arithmetic logic unit having a first input, a second input and an output; a parallel shifter unit having an input and an output; said first read port of said register file connected to said first input of said arithmetic logic unit for supplying address words or data words to said arithmetic logic unit; said second read port of said register file connected to said second input of said arithmetic logic unit and to said first write port of said register file for supplying address words or data words to said arithmetic logic unit or to said first write port; the output from said arithmetic logic unit connected to the input of said shifter unit and the output of said shifter unit connected to said second write port of said register file for writing the logic unit result in parallel into the register file.