1. In a programmable logic device (PLD), a memory architecture comprising: an array of memory cells arranged in a plurality of rows and columns; an array of shadow storage units arranged in said plurality of rows and columns corresponding to said array of memory cells, each memory cell being coupled to a corresponding shadow storage unit; a plurality of bidirectional data lines each coupled to a respective row of shadow storage units; a data shift register coupled between said plurality of bidirectional data lines and PLD input/output terminals; and an address shift register coupled to said array of shadow storage units.