1. A CPU comprising: a NOR cell, the NOR cell comprising: a first input side NOT gate including a first transistor; a second input side NOT gate including a second transistor; a NAND gate having a first input terminal connected to the first input side NOT gate and a second input terminal connected to the second input side NOT gate; and an output side NOT gate having a third input terminal connected to an output terminal of the NAND gate, the output side NOT gate including a third transistor, wherein a first channel width of the first transistor is smaller than a third channel width of the third transistor, wherein a second channel width of the second transistor is smaller than the third channel width of the third transistor, and wherein each of the first transistor, the second transistor and the third transistor comprises a semiconductor layer on an insulating layer, the semiconductor layer comprising a channel region.