1. In a processor, a method comprising: mapping a logical register to a physical register in a map table data structure in response to a first instruction; recording a second instruction as a most recently dispatched instruction in said map table data structure when said second instruction maps said logical register to said physical register, wherein said second instruction is executed speculatively by an execution unit; setting an evictor instruction tag (ITAG) of said first instruction in said map table data structure when said second instruction maps the logical register of said first instruction to a same logical register of said first instruction; detecting a mispredicted speculative instruction; determining which instructions in said map table data structure were dispatched prior to said mispredicted speculative instruction; and restoring said map table data structure to a state prior to said mispredicted speculative instruction by utilizing said evictor ITAG to restore one or more A bits in said map table data structure.