1. A computer-implemented method of facilitating processor/memory co-exploration, said method comprising: accessing a description of a processor in an architecture description language, wherein said architectural description language models said processor on one or more of a plurality of abstraction levels; accessing a description of a memory system in said architectural description language, wherein said architectural description language models said memory system on said one or more of said plurality of abstraction levels; accessing a description of a communication protocol formed from primitives, suitable for said one or more of said plurality of abstraction levels; and automatically generating a processor/memory system simulation model from said description of said processor said memory system and said communication protocol, wherein said processor/memory system simulation model comprises a processor simulation model, a memory system simulation model and a processor/memory interface coupling said processor core simulation model and said memory system simulation model.