1. A computer-implemented method for generating test patterns, the method comprising: receiving, at a first spreading network of XOR logic gates, a plurality of scan inputs from a tester; feeding, with outputs of the first spreading network, a linear shift register; updating, using the outputs of the first spreading network, bits in the linear shift register, each bit of the linear shift register being shifted at each shift cycle for a plurality of shift cycles, wherein one of the outputs of the first spreading network is shifted between a plurality of shift registers of the linear shift register; feeding a set of outputs from the linear shift register to a second spreading network of XOR logic gates; and feeding a set of outputs from the second spreading network to a set of scan channels.