1. A processor comprising: multiple levels of cache, including a Level 1 (L1) cache; a first register; a second register; a plurality of registers to store 128-bit packed data operands; a decoder to decode instructions including a packed comparison instruction, wherein the packed comparison instruction is to identify a first 128-bit source packed data operand in said plurality of registers, and a second 128-bit source packed data operand in memory or said plurality of registers, wherein bits indicating a number of valid data elements of the first 128-bit source packed data operand are to be stored in the first register, and bits indicating a number of valid data elements of the second 128-bit source packed data operand are to be stored in the second register, and wherein the packed comparison instruction is to have an immediate that is to include: a first two bits, wherein the first two bits being equal to 00 B is to indicate that data elements of the first and second 128-bit source packed data operands are unsigned bytes, being equal to 01 B is to indicate that the data elements are unsigned words, being equal to 10 B is to indicate that the data elements are signed bytes, and being equal to 11 B is to indicate that the data elements are signed words; a second two bits, wherein the second two bits being equal to 00 B is to indicate that comparisons to be performed are to determine whether any of the valid data elements of the first and second 128-bit source packed data operands are equal, being equal to 01 B is to indicate that the comparisons are to involve ranges, and being equal to 11 B is to indicate that the comparisons are to determine whether the first and second 128-bit source packed data operands have an equal ordered plurality of data elements; a third two bits to control a negation operation, wherein the third two bits being equal to 00 B is to indicate that all bits of a result of the comparisons are not to be negated, being equal to 01 B is to indicate that said all bits of the result of the comparisons are to be negated, and being equal to 11 B is to indicate that only bits of the result of the comparisons that correspond to the valid data elements of one of the first and second 128-bit source packed data operands are to be negated; and a fourth bit, wherein the fourth bit being equal to 0 B is to indicate that a result of the negation operation is to be zero extended to a mask, and being equal to 1 B is to indicate that the result of the negation operation is to be expanded to one of a byte mask and word mask; and an execution unit coupled with the decoder to execute the packed comparison instruction.