1. In a data communication system having a communication channel (101) which carries data messages to a processor (200) having data, address, and control busses and an associated memory (201) connected to said data, address and control busses, a channel interface circuit (100) for interconnecting said data, address and control busses with said communication channel (101) comprising: interface means (102) connected to said communication channel (101) and responsive to said data message, which contains a header field having address and control portions, appearing on said communication channel (101) for outputting said data message as received on a byte-by-byte basis; pattern matcher means (105) connected to said interface means and responsive to only said header field of said data message for generating a hardware address as the last byte of said header field is received to identify the location in said associated processor memory (201) wherein said data message is to be stored if said processor (200) is the designated destination of said data message; incoming state controller means (104) responsive to said last byte of said header field as it is being received for seizing said data, address and control busses; driver means (108) connected to said processor address bus and said pattern matcher means (105) and responsive to said hardware address for transmitting said hardware address on said processor address bus to activate said identified memory store location in said associated processor memory (201); and wherein said driver means (108) is also connected to said interface means (102) and said processor data bus and is responsive to said hardware address for directly storing, as received, the data portion of said data message as outputted by said interface means (102) in said activated memory store location via said processor data bus.