1. A computer-implemented method for design analysis comprising: obtaining a design with a logic component; computing, one or more processors, a first representation of the logic component in redundant form; computing a second representation of the logic component in non-redundant form which was derived from the redundant form; injecting a factor into the second representation where the factor includes a randomness factor which is introduced into a verification process by computing an output value based on a carry-save circuit form; constraining the second representation for the logic component; simulating, with downstream logic, the first representation and the constrained second representation; and verifying the logic component with the downstream logic wherein the verifying comprises analyzing the logic component with the downstream logic using the first representation and the constrained second representation to provide a resulting analysis.