1. A processor comprising: a memory dependence detector configured to: detect a given store instruction; store an address operand base register ID corresponding to an address operand base register and an address operand immediate value of the given store instruction in a first entry of a table; in response to detecting an instruction that is configured to perform a modification of the address operand base register: adjust the value of the address operand immediate value for the given store instruction in the first entry of the table, in response to determining the modification is an immediate value based modification; and invalidate the first entry in the table, in response to determining the modification is other than an immediate value based modification; and determine a memory dependence for a given load instruction on the given store instruction responsive to detecting a valid entry in the table indicates the given store instruction and the given load instruction have matching values for an address operand base register ID and an address operand immediate value; and a register rename unit; wherein in response to receiving an indication of the memory dependence, the register rename unit is configured to: assign a rename register identifier (ID) associated with a source operand register ID of the given store instruction to a destination operand register ID of the given load instruction; store a duplicate count associated with the rename register ID, wherein the duplicate count indicates a number of architectural register IDs currently mapped to a given rename register ID; and prevent the given load instruction from reading data associated with the source operand from memory.