1. Circuitry for converting a plurality of multi-bit, arbitrarily signed, coded digital input signals into a single analog output signal of predetermined amplitude but a duty cycle related to said digital input signals, said circuitry comprising, in combination: a source of clock pulses; divider means for providing a start pulse one out of every n clock pulses; a pair of presettable counters, each operative while the respective counter is enabled by an enabling signal to count in a predetermined direction and at a rate determined by successive clock pulses from any numerical value set therein to a predetermined base value indicative of a count termination state; means for setting the numerical value of each input signal into a respective one of said counters responsively to a start pulse; means denoting whether the sign of each input signal is positive or negative; and means for providing an enabling signal to each counter successively if the signs of both input signals are identical and concurrently if the signs of the input signals are different, thereby to generate a pair of binary signals representing the magnitude and sign, respectively, of a ternary analog output signal, the average value of which varies substantially linearly with changes in algebraic sum of the numerical values represented by said input signals and said predetermined base value.