1. A system for operating a short data word length memory device with a wider bus having address/data multiplex operable devices connected thereto comprising: means for connecting the data lines of the memory device to a first group of bus lines; means for connecting the address lines of the memory device to a second group of bus lines; means for executing a first mode of bus operation, characterizing a read of data from the memory device, by writing a memory address on the second group of bus lines and reading memory data from the first group of bus lines; and means for executing a second mode of bus operation, characterizing a multiplexed operation of the bus with the memory device disabled, by writing an address on the combination of the first and second groups of bus lines and thereafter reading data from or writing data onto the combination of the first and second groups of bus lines.