1. An integrated verification and manufacturability tool comprising: a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical manner; an optical and process correction (OPC) component that operates on the integrated device layout by accessing said hierarchical database, and determining corrections for one or more edge fragments in the integrated device layout and storing the corrections in the hierarchical database; and an optical and process correction (OPC) verification component that operates on the integrated device layout by accessing the OPC corrections stored in the hierarchical database and analyzing them with a simulation engine to ensure that the edge fragments of the integrated device design will print as desired.