1. A system for programmably designating semiconductor device pins comprising, in combination: a programming port for receiving a plurality of pin designation instructions; configuration logic coupled to the programming port for storing the plurality of pin designation instructions; selection logic coupled to the programming port for selecting the function of at least one pin designation; at least one pin coupled to the selection logic and that is programmably designated to perform one of a plurality of I/O functions; a plurality of pins with a predesignated address function; and programming logic coupled to the programming port for interpreting the plurality of pin designation instructions.