1. A multi-processor system that conforms to a cache coherency protocol, the system comprising: a processor that executes program instructions beyond at least one memory barrier of at least one executed load instruction; a request engine that retrieves an updated data fill with an undetermined coherency state from one or more other processors of the multi-processor system via a prosessor-to-processor data fill, the updated data fill corresponding to an invalid cache line from which data had been retrieved by the at least one executed load instruction; and a load compare component that compares the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction prior to retiring the at least one executed load instruction.