1. A system for testing embedded logic circuitry coupled to a memory array, said system comprising: a Built-In Self-Test (BIST) for generating a test pattern for testing said logic circuitry; and means for providing said test pattern to said logic circuitry including means for writing at least a portion of said test pattern into said memory array and then applying said portion of said test pattern out of said memory array to said logic circuitry for testing said logic circuitry.