1. A data shuffler apparatus for shuffling input bits comprising: a plurality of bit shufflers each inputting corresponding two bits x 0 and x 1 of the input bits and outputting a vector &lcub;x 0 ′, x 1 ′&rcub; such that 5 Current State Next State Vector of Bit Shuffler Input Bits of Bit Shuffler &lcub;x 0 ′, x 1 ′&rcub; S 0 (0) x 0 &equals; x 1 S 0 (0) &lcub;x 0, x 1 &rcub; S 0 (0) x 0 ≠ x 1 S 1 (1) &lcub;x 1, x 0 &rcub; S 1 (1) x 0 &equals; x 1 S 1 (1) &lcub;x 0, x 1 &rcub; S 1 (1) x 0 ≠ x 1 S 0 (0) &lcub;x 0, x 1 &rcub; ;and at least two 4-bit vector shufflers each inputting two of the vectors &lcub;x 0 ′, x 1 ′&rcub; and outputting 4-bit vectors each corresponding to a combination of two vectors &lcub;x 0 ′, x 1 ′&rcub;, such that the 4-bit vector shufflers operate on the vectors &lcub;x 0 ′, x 1 ′&rcub; in the same manner as the bit shufflers operate on the bits x 0 and x 1, wherein the current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.