1. A method for mapping logic functions implemented in logic elements into synchronous embedded memory blocks within a programmable logic device (“PLD”) design comprising: determining, using a processor, the availability of the logic elements within the PLD design; determining the availability of the synchronous embedded memory blocks within the PLD design; mapping at least a portion of a logic function implemented in the logic elements into a portion of the available synchronous embedded memory blocks; adjusting the determined availability of the logic elements and the embedded memory block based on the mapping; and determining whether to perform additional mappings of logic functions from the logic elements into the synchronous embedded memory blocks based on the adjusted availability.