1. A processor circuit, comprising: at least one execution unit that executes instructions including those of a controlling thread among a plurality of threads of a program; event detection logic that detects occurrence of a particular asynchronous event during execution of the controlling thread; a plurality of status and control registers each associated with a respective one of the plurality of threads, wherein a status and control register among the plurality of status and control registers provides status information to the controlling thread; and thread initiation logic that, in response to occurrence of the particular asynchronous event during execution of the controlling thread: initiates execution of an assist thread of the program by the at least one execution unit such that the processor circuit executes the assist thread and controlling thread simultaneously; and updates the status and control register of the controlling thread to identify to the controlling thread the particular asynchronous event for which the occurrence was detected and to indicate to the controlling thread that the assist thread is currently being executed in response to the occurrence of the particular asynchronous event.