1. A microprocessor, comprising: a plurality of processing cores, wherein each core of the plurality of processing cores comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other of the plurality of processing cores (hereinafter “core memory”); a memory physically located outside all of the plurality of processing cores and readable by all of the plurality of processing cores (hereinafter “uncore memory”); wherein, for each core of the cores, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage; and the corresponding core memory provides K of the M words of microcode instruction storage, wherein J, K and M are counting numbers, wherein M=J+K.