1. A fault tolerant memory system comprising a random access memory serving a digital computer and addressed by a free-running address counter means counting first clock pulses to generate a cyclic sequence of memory addresses for serial transfer between the memory and the computer of a block of groups of bits, where each group of bits consists of n bits and n is 1 or a larger integer, an interface between the computer and the memory, the interface being responsive to second clock pulses to effect the transfer between the computer and the memory, characterized by storage means storing data identifying the address of at least one of said groups within the block, and control means utilizing the stored data to inhibit the transfer of the identified at least one group, and wherein the control means selectively gates the first clock pulses to provide the second clock pulses.