1. An apparatus for generating a test case for verifying a computer processor design, the apparatus comprising: at least one processor configured to execute computer readable instructions to, define a total verification space using a computer processor architecture specification, the total verification space based on information types included in the computer processor architecture specification associated with the computer processor design, generate a computer processor architecture description for the total verification space, define a plurality of constrained verification spaces in the total verification space based on the computer processor architecture description, generate a constrained description for each of the plurality of constrained verification spaces, generate at least one test case for verifying the computer processor design using each of the constrained descriptions, and verify the computer processor design based on the at least one test case and a simulation of the computer processor design.