1. An apparatus comprising: a processing core configured to execute a plurality of threads; and a transactional memory system for executing atomic memory transactions, wherein the processing core is configured to perform operations including: starting, by a first thread, a task by starting to execute a plurality of task instructions; temporarily ceasing the task being executed by the first thread, by not proceeding to execute the task instructions, to initiate an atomic memory transaction; initiating, by the first thread, the atomic memory transaction using the transactional memory system, including: specifying, to the transactional memory system, a plurality of memory addresses for the atomic memory transaction, including executing a load instruction from each memory address of the plurality of memory addresses; accessing, by a second thread, a first memory address of the plurality of memory addresses specified for the atomic memory transaction; receiving, by the first thread, a signal in response to the second thread accessing the first memory address specified for the atomic memory transaction; and as a consequence of receiving the signal in response to the second thread accessing the first memory address specified for the atomic memory transaction, resuming the task, by the first thread, and continuing to execute the task instructions.