1. A method for processing data on a chip with a synchronous data word received by the chip over a double data rate bus in which a first half of the synchronous data word is latched on one edge of a clock signal and the second half of the synchronous data word latched on the next edge of the clock signal, including the steps of: receiving in said first half of the synchronous data word data sufficient to perform a logical function independently of said second half; starting said logical function before said first half and said second half of said synchronous data word are aligned to the same local clock edge.