1. A phase-change-memory peripheral comprising: a peripheral phase-change-memory controller having a central processing unit (CPU) for executing instructions and a random-access memory (RAM) for storing instructions for execution by the CPU; throughput-increasing control routines of instructions executed by the CPU, wherein the throughput-increasing control routines increase a throughput of the phase-change-memory peripheral by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a dual-channel concurrent memory read operation, a dual-channel concurrent memory write operation, a write-cache memory write operation, a multi-channel concurrent multi-bank memory read operation, a multi-channel concurrent multi-bank memory write operation, a multi-channel concurrent multi-bank memory write cache operation; a bus transceiver in the peripheral phase-change-memory controller for receiving peripheral commands and data from a host over a host bus; a phase-change-memory controller in the peripheral phase-change-memory controller; a plurality of phase-change memory (PCM) cells organized as phase-change-memory mass storage devices, coupled to the phase-change-memory controller, for storing non-volatile data for the host, the data in the phase-change-memory mass storage devices being block-addressable and not randomly-addressable; wherein each PCM cell in the plurality of PCM cells has a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase; and a phase-change-memory bus having data lines for transferring data from the phase-change-memory controller to the phase-change-memory mass storage devices, whereby the peripheral phase-change-memory controller controls the phase-change-memory mass storage devices that are block-addressable.