1. A method for executing a target application on a host processor comprising: interpreting each of a sequence of target instructions to produce a sequence of host instructions and executing the sequence of host instructions; translating into host instructions each of a sequence of target instructions to produce translated host instructions, wherein the translating is performed when the number of times a sequence of target instructions is executed exceeds a preset count; storing the translated host instructions wherein a plurality of additional registers are used during execution for holding the official state of a target processor; responding to an exception during execution of a stored translated host instruction by rolling back to a previous point in execution at which correct state of a target processor is known; and interpreting each target instruction in order from the point in execution at which a correct state of a target processor is known.