1. For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, comprising: a key register located within said SEE and coupled to said secure memory to receive a cryptographic key therefrom; and data input and output registers located outside of said SEE and coupled to said key register to allow said cryptographic key to be applied to input data arriving via said data input register to yield output data via said data output register.