1. An apparatus comprising: processing circuitry to process instructions; address translation circuitry to translate a virtual address to a physical address in response to a virtual address request from the processing circuitry; and translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction, wherein said translation measuring circuitry is configured to exclude from the measured latency: a latency of a data access operation using the physical address obtained as a result of translating the virtual address specified in the virtual address request.