1. A processor comprising: a plurality of accelerators; a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction; and an execution unit to: execute the first decoded instruction to, for a thread executing on at least one accelerator of the plurality of accelerators that is to be placed in an inactive state, cause a save of context information for each of the at least one accelerator of the plurality of accelerators for the thread, and a save of a vector identifying the at least one accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine which of the plurality of accelerators have saved context information for the thread, read the saved context information, and restore the saved context information into the at least one accelerator.