1. A processor comprising: a memory; a processing core coupled to the memory; one or more functional units coupled to the memory; and a memory stream component coupled to the memory, the processing core, and the one or more functional units and to: receive a plurality of operations associated with the memory and to be performed by the processing core; receive a plurality of operations to be performed by the one or more functional units, wherein the one or more functional units are external to the processing core; determine a dependency between the plurality of operations to be performed by processing core and the plurality of operations to be performed by the one or more functional units that are external to the processing core, the dependency specifying that at least one read operation of the operations to be performed by processing core is to be executed before at least one of the operations to be performed by the one or more functional units is to be executed; create a first ordering of the plurality of operations to be performed by the processing core; and create a second ordering of the plurality of operations to be performed by the one or more functional units based on the dependency and the first ordering of the plurality of operations to be performed by the processing core, the second ordering to specify when to transmit the operations of the second ordering to the one or more functional units relative to a transmitting of the operations of the first ordering to be performed by processing core.