1. A double-bit non-volatile memory cell structure, comprising: a substrate; a pair of stacked gates above the substrate, wherein each stacked gate includes, from bottom to top, a tunnel layer, a floating gate, an inter-gate dielectric layer and a control gate; a doped region, wherein the doped region is located in the substrate between the two stacked gates; and a pair of source/drain regions, wherein the source/drain regions are in the substrate on each side of the stacked gate pair, and the two source/drain regions and the doped region are identically doped.