1. A processor, comprising: a data cache; instruction execution circuitry configured to execute instructions in two or more redundant threads, wherein the threads include load instructions that cause the instruction execution circuitry to retrieve data from the data cache; and a counter associated with a data block in the data cache, wherein the counter is incremented when the instruction execution circuitry executes a load instruction to retrieve data from the data block for one of the two or more redundant threads (hereafter designated as the leading thread), and wherein the counter is decremented when the instruction execution circuitry executes a load instruction to retrieve data from the data block for a different one of the two or more redundant threads (hereafter designated as a trailing thread).