1. A method for generating a sequence of instructions for design verification of a processor, the method comprising the following steps: (a) receiving a network having a plurality of sites and various paths connecting each site to a plurality of associated destination sites, each site having a plurality of associated processor instructions, and each path available to a given site having an associated weighting; (b) designating an initial site within the network as a current site; (c) selecting one available instruction from the current site and inserting that instruction sequentially in a diagnostic file; (d) selecting one of the paths connected to the current site and designating the destination on that path as the current site; and (e) repeating Steps b thru d until a predetermined number of instructions have been inserted in the diagnostic file.