1. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising: in a pseudo-random phase of operation: providing an initial value; generating from the initial value a set of pseudo-random test patterns; and applying the pseudo-random test patterns to the scan chains in the circuit-under-test; in a deterministic phase of operation: providing a set of compressed deterministic test patterns; decompressing a compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being provided; and applying the decompressed deterministic test patterns to the scan chains in the circuit-under-test.