1. An apparatus comprising: a memory cell having a plurality of available programming states to accommodate multi-level cell (MLC) programming; and a control circuit which stores only a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states, and which subsequently stores only a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.