1. A processor core having an out-of-order pipeline, comprising: an instruction fetch portion of a pipeline that includes a program counter selector that selects addresses used to fetch instructions from a memory, an instruction buffer that stores fetched instructions, and a branch predictor that predicts for a fetched control transfer instruction whether a conditional branch is taken; an instruction execution portion of the pipeline, coupled to the instruction fetch portion of the pipeline, that includes an instruction decoder that decodes instructions read from the instruction buffer, an arithmetic logic unit that executes decoded instructions and, if a decoded instruction is a control transfer instruction, determines whether a prediction made by the branch predictor is correct, and a completion buffer that stores results generated by the arithmetic logic unit during execution of decoded instructions; and pipeline control logic, coupled to the instruction fetch portion of the pipeline and the instruction execution portion of the pipeline, that halts movement of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline in response to a detection of a conditional branch misprediction, invalidates instructions residing within the instruction fetch portion of the pipeline, invalidates instructions residing within the instruction execution portion of the pipeline after a control transfer instruction associated with the conditional branch misprediction reaches a selected stage within the instruction execution portion of the pipeline, and restarts movement of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline.