1. A processor comprising: a plurality of three or more branch predictors, wherein each branch predictor is adapted to provide a prediction and an override signal, each override signal being produced using an independent override logic associated with each branch predictor; and a branch prediction control circuit to generate a branch prediction based on the prediction and override signal from each predictor, the branch prediction control circuit being operable to: determine if a negative override signal has been asserted from one of the plurality of three or more branch predictors; if a negative override signal has been asserted from one of the plurality of three or more branch predictors, then select a branch prediction from a predictor having a highest confidence level that did not assert the negative override; and otherwise, if a negative override signal has not been asserted from one of the plurality of three or more branch predictors, then select a branch prediction from a predictor having a highest confidence level from among the plurality of three or more branch predictors.