1. A microprocessor including a pipelined path for flow of instructions in said microprocessor, which comprises a microcode address multiplexer connected to supply addresses from a plurality of different inputs to a microcode storage means, said microcode storage means being connected to supply microcode, in response to the addresses to a microcode register, said microcode register being connected to supply branch control information to a branch control means, said branch control means being connected to receive branch condition inputs externally of said microprocessor, internally of said microprocessor and from a microcode address programmable logic array, said microcode address programmable logic array being connected to supply microcode addresses to said microcode address multiplexer, said branch control means being connected to control operation of said microcode address multiplexer.