1. A processor comprising: a plurality of processing tiles, wherein each processing tile is configured at runtime to perform a configurable operation, wherein a first subset of processing tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel, and wherein a second subset of processing tiles are configured to perform a second plurality of configurable operations in parallel, wherein each of the plurality of processing tiles comprise: a multiplexer configured to: receive input data from the multi-port memory access module and from another processing tile, wherein at least one of the processing tiles receives data from the multi-port memory access module; send output data to the multi-port memory access module and to another processing tile, wherein at least one of the processing tiles sends data to the multi-port memory access module; and a plurality of operators each operably connected to the multiplexer, wherein each operator is configured to: receive the input data from the multiplexer; perform an operation on the input data to generate the output data; and send the output data to the multiplexer; a first in, first out (FIFO) buffer operably connected to each of the input and output of each respective plurality of operators, wherein each of the plurality of operators is configured to stall when one of the respective FIFO buffers operably connected to the respective operator is full; a multi-port memory access module operably connected to the plurality of processing tiles via data lines, wherein the multi-port memory access module is configured to: control access to a shared memory; provide data to two or more processing tiles simultaneously; and give the plurality of processing tiles direct access to the shared memory; and at least one controller operably connected to the plurality of processing tiles and the multi-port memory access module via a runtime bus, wherein the at least one controller is adapted to configure the plurality of processing tiles and the multi-port memory access module to execute a computation.