1. A method for utilizing fast analysis information during detailed analysis of a circuit design, comprising: electronically analyzing one or more design blocks of the circuit design to determine fast analysis results based upon one or more assumptions of ported signal nets of each one of the design blocks; determining whether hierarchical signal net connectivity of block instances of the design blocks matches the assumptions; if the hierarchical signal net connectivity matches the assumptions, utilizing the fast analysis results to generate detailed analysis results; and if the hierarchical signal net connectivity does not match the assumptions, electronically analyzing the one or more blocks to generate detailed analysis results.