1. A method of transforming a provided virtual processor model to a user virtual processor model to simulate a user target processor, the method comprising: accepting a provided virtual processor model, the provided virtual processor model for simulating a seed target processor, including implementing behavior and timing for a seed set of instructions of seed target processor, such that the simulation is both behavior and timing accurate; accepting one or more user-provided descriptions of the user target processor model; and transforming the accepted provided virtual processor model to the user virtual processor model according to the user-provided descriptions, wherein the user virtual processor model has new and/or modified instructions, and/or modified behavior or timing for instructions, and/or modified processor structure in the form of a new or modified pipeline and/or a new or modified register compared to the seed virtual processor model, wherein the behavior is implemented using binary translation of target code into host code, including caching translated target code for re-use during simulation of the user target processor.