1. An apparatus, comprising: a memory, the memory including a shared ring buffer for storing data, the memory configured to store a set of shared variables configured for use in controlling access to the shared ring buffer, wherein the set of shared variables includes a first variable pointing to a next buffer slot of the shared ring buffer into which data is to be inserted and a second variable pointing to a next buffer slot of the shared ring buffer from which data is to be extracted; a first processor core having a first cache associated therewith, wherein the first cache is configured to store a first set of local variables a third variable pointing to a next buffer slot of the shared ring buffer into which data is to be inserted by the first processor core and a fourth variable providing an estimation by the first processor core as to a current value of the second variable stored in the memory, wherein the first processor core is configured to control insertion of data into the shared ring buffer based on the first set of local variables and the second variable stored in the memory, wherein, to control insertion of data into the shared ring buffer, the first processor core is configured to compare the value of the third variable stored in the first cache with the value of the forth variable stored in the first cache for determining whether the shared ring buffer is potentially full; and a second processor core having a second cache associated therewith, where in second cache is configured to store a second set of local variables including a fifth variable pointing to a next buffer slot of the shared ring buffer from which data is to be extracted by the second processor core and a sixth variable providing an estimation by the second processor core as to a current value of the first variable stored in the memory, wherein the second processor core is figured to control extraction of data from the shared ring buffer based on the second set of local variables and the first variable stored in the memory, wherein, to control extraction of data from the shared ring buffer, the second processor core is configured to compare the value of the fifth variable stored in the second cache with the value of the as sixth variable stored in the second cache for determining whether the shared ring buffer is potentially empty.