1. An apparatus for packet processing in a switching network, the apparatus comprising: processing circuitry coupled to memory arrays and receiving circuitry; the receiving circuitry operable to receive packet header vectors comprising respective packet header words, wherein the packet header vectors are associated with ternary values that are representative of “1”, “0”, and “don't care”; the processing circuitry comprising a plurality of processors, including at least first and second processors coupled to a respective first and second end destinations, the first and second processors operable to modify respective first and second packet header words in response to: at least one packet match operation based on the ternary values; and at least one very long instruction word (VLIW) that provides an instruction to modify the first and second packet header words without specifying the end destination.