1. An apparatus comprising: a hardware processing core in a multi-processing core system, wherein the hardware processing core is configured to execute a sequence of instructions as an atomic memory transaction, wherein the hardware processing core is configured to issue each instruction in the sequence to an execution pipeline, wherein the execution pipeline is configured to validate each instruction of the sequence during a validate stage of the execution pipeline that is prior to an execute stage of the execution pipeline, wherein the execute stage is configured to compute instruction results; wherein the validate stage is configured to determine types of instructions in the sequence based on opcodes of the instructions in the sequence, and wherein the validate stage is configured to allow execution of the sequence of instructions as an atomic memory transaction only if none of the instructions in the sequence of instructions have an opcode indicating an instruction type that permits specification of an access to any memory location for which another processor core in the multi-processing core system includes circuitry configured to execute a type of instruction that permits specification of an access to the memory location.