1. An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture, comprising: a current instruction buffer and a next instruction buffer in a pipeline stage n; an aligned instruction buffer in a pipeline stage n&plus;1; instruction fetch logic for loading instructions into the current instruction buffer from a memory or from the next instruction buffer and for loading instructions into the next instruction buffer from the memory; and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.