1. An apparatus comprising: a first processing unit including a first register file operably coupled to one or more first vector arithmetic logic units; a second processing unit including a second register file operably coupled to one or more second vector arithmetic logic units; wherein the first register file has a plurality of cross-connections to at least one of the second vector arithmetic logic units; and wherein the second register file has a plurality of cross-connections to at least one of the first vector arithmetic logic units.