1. A processor, comprising: a front end unit, including: a branch prediction (BP) pipeline; first selection circuitry that selects an index based on an input program counter, a prior speculative partial target address, and a prior target address; a level 1 branch target buffer (BTB) that generates a first predicted program counter based on the index; a BTB index predictor (BIP) that generates a prediction based on the index and a global history, wherein the prediction includes a second predicted program counter, a first predicted global history shift value, and a way prediction; a level 1 hash perceptron (HP) that generates a second predicted global history shift value and a taken signal based on the index, wherein the taken signal indicates an estimation of whether a branch instruction is taken or not taken; a first comparator that compares the first predicted program counter and the second predicted program counter to generate a first match signal; a second comparator that compares the first predicted global history shift value and the second predicted global history shift value to generate a second match signal, wherein the first match signal and the second match signal are generated in parallel; and a logic gate that generates a BP compare signal by comparing the first match signal and the second match signal, wherein the BP pipeline is selectively flushed based on the BP compare signal; wherein the first predicted program counter, the prediction and the taken signal are generated in parallel during a same branch prediction cycle.