1. A method, in a data processing system, for validating cache coherency within a processor, the method comprising: generating, by a processor, a self-modifying branch test pattern for execution by one or more processors that is under validation testing; selecting, by the processor, an execution pattern from a set of execution patterns thereby forming a selected execution pattern; loading, by the processor, the selected execution pattern into a condition register; for each node in a set of nodes: determining, by the processor, whether a node in a set of nodes is a controlling node; and responsive to the node being a controlling node, performing, by the processor, at least one action on each controlled node mapped to the controlling node; after performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, executing, by the processor, the self-modifying branch test pattern based on the selected execution pattern in the condition register through the set of nodes; responsive to the self-modifying branch test pattern ending, comparing, by the processor, values output during execution of the self-modifying branch test pattern to a set of expected results; responsive to a match of the comparison, repeating, by the processor, the process for each execution pattern in the set of execution patterns; and responsive to a match of the comparison for the execution patterns in the set of execution patterns, validating, by the processor, the cache coherency.