1. A method of identifying layout-versus-schematic errors, comprising: comparing a layout netlist against a schematic netlist to identify one or more layout-versus-schematic errors; generating a graphical representation of the layout netlist; generating a graphical representation of the schematic netlist; displaying on a display an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist; and highlighting the one or more identified layout-versus-schematic errors on the display.