1. A memory switching control apparatus using an open serial interfacing, comprising: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.