1. A simulation processor for performing logic simulation of a logic design including a plurality of logic gates, the simulation processor comprising: an interconnect system; and a plurality of processor units communicatively coupled to each other via the interconnect system, wherein each of at least two of the processor units includes: a processor element configurable to simulate at least one of the logic gates; and a shift register associated with the processor element and including a plurality of entries to store intermediate values during operation of the processor element, the shift register coupled to receive an output of the processor element.