1. A buffered memory module comprising: a downstream driver and a downstream receiver both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem; an upstream driver and an upstream receiver both adapted for connection to an upstream memory bus in the memory subsystem, wherein during a test of the memory module the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver; one or more storage registers; a microprocessor including instructions for executing the test of the memory module including storing results of the test in the storage registers; and a service interface port for receiving service interface signals initiating the execution of the test and for accessing the storage registers to determine the results of the test.