1. A content addressable memory (CAM) device, comprising: a CAM array including a plurality of rows, each row including a plurality of CAM cells coupled to a match line; a data encoder circuit having an input to receive a first data word and configured to encode the first data word using an encoding scheme to generate an encoded data word that comprises a balanced data word having an equal number of logic high bits and logic low bits; and a read/write circuit coupled to the data encoder circuit and the CAM array and configured to store the encoded balanced data word into a selected row of CAM cells, wherein each row includes a number T of quaternary CAM cells, T being an integer greater than 2, wherein the encoded data word includes 2T data bits, and wherein a number S of possible states represented by the balanced data word is expressed as S=(2T)!/(T!) 2 .