1. A computer having a reconfigurable architecture containing a RAM-based primary part (Ht) comprising a structurable RAM unit ( 2 ) comprising a plurality of RAM blocks ( 221 ), a first crossbar switch ( 1 ), where external input data ( 9 ) on the architecture is to be applied to its input, and whose output is connected to the input of the RAM unit ( 2 ) via a first bus system ( 20 ), and a second crossbar switch ( 3 ), whose input is connected to the output of the RAM unit ( 2 ) via a second bus system ( 21 ), and whose output is connected to the input of the first crossbar switch ( 1 ) via a third bus system ( 10 ) in order to feedback output-side data from the second crossbar switch ( 3 ) to the input of the first crossbar switch ( 1 ), where address signals ( 18 and 13 ) produced by the first crossbar switch ( 1 ) are to be input to the RAM unit ( 2 ) and the second crossbar switch ( 3 ) for addressing, and where the output-side data from the second crossbar switch ( 3 ), if necessary after further processing, is also to be input to an output network ( 8 ) for the output of output data ( 17 ) on the architecture, plus means in an additional control part (St) for sequential control of the primary part (Ht), comprising a counter unit ( 4 ), where a common clock signal ( 14 ) is to be input to the counter unit ( 4 ) and to the first crossbar switch ( 1 ), and where counter reading signals ( 12 ) produced by the counter unit ( 4 ) are to be input to the first and second crossbar switches ( 1 and 3 ).