1. A method of operating a non-volatile logic circuit, the method comprising: a step (a) of preparing the non-volatile logic circuit, wherein: the non-volatile logic circuit comprises a control electrode, a ferroelectric layer, a semiconductor layer, and an electrode group, the control electrode, the ferroelectric layer, the semiconductor layer, and the electrode group are stacked in this order, the semiconductor layer is a p-type semiconductor film, the semiconductor film is divided into first to fourth semiconductor portions, the electrode group comprises a power electrode, an output electrode, first to eighth input electrodes, and first to fourth logic configuration electrodes, when X direction, Y-direction, and Z-direction denote a longitudinal direction of the ferroelectric layer, a direction orthogonal to the longitudinal direction, and a layer stack direction, respectively, the first to eighth input electrodes and the first to fourth logic configuration electrodes are interposed between the power electrode and the output electrode along the X-direction, the first to fourth logic configuration electrodes are disposed along the Y-direction, the first to fourth input electrodes are disposed along the Y-direction, the first to fourth input electrodes are disposed along the Y-direction, the first input electrode, the fifth input electrode, and the first logic configuration electrode are disposed along the X-direction on the first semiconductor portion, the second input electrode, the sixth input electrode, and the second logic configuration electrode are disposed along the X-direction on the second semiconductor portion, the third input electrode, the seventh input electrode, and the third logic configuration electrode are disposed along the X-direction on the third semiconductor portion, the fourth input electrode, the eighth input electrode, and the fourth logic configuration electrode are disposed along the X-direction on the fourth semiconductor portion, a first insulation part is interposed between the first semiconductor portion and the second semiconductor portion to insulate the first semiconductor portion from the second semiconductor portion, a second insulation part is interposed between the second semiconductor portion and the third semiconductor portion to insulate the second semiconductor portion from the third semiconductor portion, and a third insulation part is interposed between the third semiconductor portion and the fourth semiconductor portion to insulate the third semiconductor portion from the fourth semiconductor portion; a step (b) of configuring one logic in the nonvolatile logic circuit, the one logic being selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR), wherein: voltages V 1 , VA, VB, VC, and VD are applied to the control electrode, and the first to fourth logic configuration electrodes, respectively, when the logical conjunction (AND) is configured, the voltages which satisfy the following inequality (I) are applied, 
 V1<VA,V1>VB,V1>VC, and V1>VD  (I), when the logical disjunction (OR) is configured, the voltages which satisfy the following inequality (II) are applied, 
 V1<VA,V1<VB,V1<VC, and V1>VD  (II), when the logical non-conjunction (NAND) is configured, the voltages which satisfy the following inequality (III) are applied, 
 V1>VA,V1<VB,V1<VC, and V1<VD  (III), when the logical non-disjunction (NOR) is configured, the voltages which satisfy the following inequality (IV) are applied, 
 V1>VA,V1>VB,V1>VC, and V1<VD  (IV), when the logical exclusive disjunction (XOR) is configured, the voltages which satisfy the following inequality (V) are applied, 
 V1>VA,V1<VB,V1<VC, and V1>VD  (V); a step (c) of writing one state selected from the group consisting of first to fourth states into the non-volatile logic circuit, wherein: voltages Va to Vh are applied to the first to eighth input electrodes, respectively, when the first state is written, voltages which satisfy the following inequality (VI) are applied, 
 V1<Va,V1<Vb,V1>Vc,V1>Vd,V1<Ve,V1>Vf,V1<Vg, and V1>Vh  (VI), when the second state is written, voltages which satisfy the following inequality (VII) are applied, 
 V1>Va,V1>Vb,V1<Vc,V1<Vd,V1<Ve,V1>Vf,V1<Vg, and V1>Vh  (VII), when the third state is written, voltages which satisfy the following inequality (VIII) are applied, 
 V1<Va,V1<Vb,V1>Vc,V1>Vd,V1>Ve,V1<Vf,V1>Vg, and V1<Vh  (VIII), when the fourth state is written, voltages which satisfy the following inequality (IX) are applied, 
 V1>Va,V1>Vb,V1<Vc,V1<Vd,V1>Ve,V1<Vf,V1>Vg, and V1<Vh  (IX); and a step (d) of measuring current generated by applying a potential difference between the power electrode and the output electrode to determine whether the semiconductor layer between the power electrode and the output electrode is a high resistance state or a low resistance state on the basis of the current.