1. A method for processing a compressed-length VLIW instruction on a processor having a very long instruction word architecture, the compressed-length VLIW instruction including a set of control bits and at least one subinstruction, the processor comprising a plurality of clusters, each one cluster of the plurality of clusters comprising a plurality of functional processing units, wherein each one iith functional processing unit in a given cluster has one corresponding functional processing unit and at least one non-corresponding functional processing units in the other clusters of the plurality of clusters, the method comprising the steps of: loading the compressed-length VLIW instruction into a cache; testing the set of control bits of the compressed-length VLIW instruction to determine distribution of the at least one subinstruction, wherein each one functional processing unit of the plurality of functional processing units of each cluster receives one of a no-operation subinstruction or a subinstruction expressly included among the at least one subinstruction; wherein for a first prescribed condition of the set of control bits, at least one expressly included subinstruction is routed to non-corresponding functional processing units as determined by the first prescribed condition; wherein for a second prescribed condition of the set of control bits, at least one expressly included subinstruction is routed to multiple functional processing units as determined by the second prescribed condition, wherein the routing for the second prescribed condition is different than for the first prescribed condition; and executing the compressed-length VLIW instruction as distributed among the plurality of functional units of each cluster by concurrently executing the subinstructions received at the plurality of functional processing units of each cluster.