1. In a system for emulating the execution of source CPU instructions received from a computer external to said system, said system including a memory, a target instruction unit which processes and issues translated target instructions, target functional units for executing target instructions, and an instruction translating unit (translator) for receiving and translating said source instructions to translated target instructions, an improvement for accelerating said translating and issuing, said improvement comprising: signal means in said translator for generating a floating point token signal in response to translation of a source floating point arithmetic instruction; outcome means in said floating point unit for generating completion signals indicative of the outcome of the target floating point arithmetic instruction issued in response to said translation, said completion signals being generated in advance of completing the execution of said issued target floating point arithmetic instruction; a multi-stage wait queue including a wait stage in said translator, said multi-stage wait queue connected to said signal and outcome means for receiving and moving said token signal to said wait stage in response to said translation and for removing said token signal from said wait stage in response to said completion signals; and system means connected to said wait stage, said translator, and said target instruction unit for preventing the translation and issue of instructions until said token is removed from said wait stage.