1. A magnetic memory array that comprises: a plurality of magnetic memory elements arranged in a macro-array of subarrays; a write conductor having a first driver circuit at one end and a second driver circuit at an opposite end, wherein the write conductor is magnetically coupled to memory cells in more than one subarray; and a repeater circuit coupled to the write conductor, wherein the repeater circuit is configured to cooperate with the first and second driver circuits to cause a current flow in a selected subarray.