1. A method to facilitate formal property verification of a design-under-test (DUT), the method comprising: receiving a constrained random test-bench for verifying the DUT, wherein the constrained random test-bench includes a first statement which assigns a random value to a random variable according to a constraint; modifying the constrained random test-bench by replacing the first statement with a second statement which assigns a free input variable's value to the random variable; using one or more computers for generating an assume property which models the constraint on the free input variable; and performing formal property verification on the DUT, wherein the formal property verification uses the assume property to constrain the values for the free input variable.