1. A vector matrix product accelerator circuit for improving multiplication throughput of a processor, the vector matrix product accelerator circuit comprising: an input/output port interfacing with a data memory bus, wherein the data memory bus couples a processor core to a data memory for storing vector input elements of a vector and matrix input elements of a matrix; vector input registers for storage of vector input elements received through the input/output port; matrix input registers for storage of matrix input elements received through the input/output port; multipliers for producing intermediate multiplication values based on input vector elements and matrix input elements; a sequencer for triggering the multipliers to execute successive multiplication cycles for successive subsets of the vector input elements of the vector and successive subsets of the matrix input elements of the matrix; and an adder circuit for summing the intermediate multiplication values computed through respective multiplier cycles to produce a particular result vector element of a result vector representing a result of multiplying the vector and the matrix.