1. A pipelined microprocessor, comprising: instruction decode logic; a program counter configured to indicate a current location in a first instruction sequence; instruction fetch. Logic configured to fetch a first instruction from the current location in the first instruction sequence; and a parameter selector configured to, if the fetched first instruction from the first instruction sequence is a virtual instruction having one or more parameters, select a parameter from the one or more parameters of the first instruction based on control data, and wherein the instruction fetch logic is further configured to: maintain the first program counter at the address of the virtual instruction, select a second instruction sequence based on the virtual instruction, modify the selected parameter, wherein the modification of the selected parameter comprises sign-extending the selected parameter, substitute the modified parameter from the first instruction into a second instruction, the second instruction being from the second instruction sequence, pass each instruction of the second instruction sequence to the instruction decode logic, and after the second instruction sequence has been executed or an exception occurs, advance the program counter and resume the first instruction sequence.