1. A cryptographic processing device configured to perform a cryptographic operation based on a multiplication of a first polynomial with a second polynomial; wherein the cryptographic processing device comprises: a first memory storing a representation of the first polynomial; a controller configured to separate the first polynomial into parts; a second memory storing pre-determined results of the multiplications of the second polynomial with possible forms of the parts of the first polynomial; a third memory for storing the result of the multiplication; an address logic, configured to determine, for each part of the first polynomial, a start address of a memory block of the second memory based on the form of the part and the location of the part within the first polynomial; an adder configured to add, for each determined address of the memory block of the second memory, the content of the memory block of the second memory at least partially to the contents of the third memory, wherein the data element of the third memory to which the content of a data element of the memory block of the second memory is added is the same for a plurality of the parts of the first polynomial.