1. A circuit arrangement, comprising: a vectorizable floating point unit including a plurality of processing lanes; and control logic coupled to the vectorizable floating point unit and configured to selectively operate the vectorizable floating point unit in vector and scalar modes, wherein in the vector mode, the control logic is configured to operate the plurality of processing lanes collectively as a single instruction multiple data (SIMD) execution unit, and in the scalar mode, the control logic is configured to operate the plurality of processing lanes as separate scalar execution units.