1. A Field Programmable Gate Array (FPGA) Integrated Circuit, comprising: a plurality of Programmable Gate Array cell structures; a plurality of dedicated processing cells comprising hardwired Arithmetic Logic Units (ALUs), a function of each of at least some of the dedicated processing cells being individually configurable at runtime; a plurality of dedicated memory cells that support dual-ported access; and a configurable interconnect interconnecting said plurality of dedicated processing cells; wherein: the Integrated Circuit is adapted for forming a sequencer structure, by configurably interconnecting at runtime at least one of the dedicated processing cells and at least one of the memory cells, data input being provided to the sequencer structure via an input port from the interconnect and data output being provided from the sequencer structure via an output port to the interconnect; and the at least one of the memory cells is adapted for: being split into at least two separated data areas; and simultaneously transferring data of the at least two separated areas to the at least one of the dedicated processing cells.