1. A scalable register file for a computer architecture having multiple functional units, the register file comprising: a first instruction register for holding an instruction; a first micro-register file including a first plurality of registers and an output port; a first instruction decoder coupled between the first micro-register file and the first instruction register for selecting one or more of the first plurality of registers during a first pipeline cycle; a first pipeline register coupled to the output port of the first micro-register file for temporarily holding the contents of the first selected registers; a second instruction register coupled to the first instruction register for receiving the instruction held in the first instruction register; a second micro-register file including a second plurality of registers and an output port; a second instruction decoder coupled between the second micro-register file and the second instruction register for selecting one or more of the second plurality of registers during a second pipeline cycle; a second pipeline register coupled to the output port of the second micro-register file for temporarily holding the contents of the second selected registers, the second pipeline register being coupled to the first pipeline register to receive the first selected register contents during the second pipeline cycle; and enable logic to present the contents of the first pipeline register to the second pipeline register, during the second pipeline cycle, if there were contents stored in the first pipeline register during the first pipeline cycle.