1. A cache controller design structure comprising: a tangible, computer readable memory device suitable for encoding circuit design structures; and one or more computer readable design structures encoded by the computer readable memory, the design structures comprising: one or more registers receiving and storing a plurality of unique logical processing partition identifiers, wherein the unique partition identifiers are each associated with a logical processing partition executing on at least one core of the multi-core processor; a position identifier, responsive to translation of an memory cycle address resulting in a shared cache memory miss, identifying a position in a cache directory for data associated with the address, wherein the shared cache memory is at least two way set associative; a line associator, responsive to the position identifier, associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; a directory modifier, responsive to the line associator, modifying the cache directory to reflect the association; and a memory access redirector, responsive to the directory modifier, caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor.