1. A system comprising: trace rules describing a sub-circuit of a larger circuit design; a sub-circuit netlist generation processor configured to generate a sub-circuit netlist, a portion of which is based on at least one of a hardware descriptive language (HDL) netlist of the larger circuit design, a parasitic capacitance database and the trace rules, wherein the sub-circuit netlist contains fewer circuit paths than the HDL netlist of the larger circuit design; and an analog simulation processor configured to generate analog simulation results of the sub-circuit netlist based on dynamic inputs.