1. A method for providing a fill pattern for an integrated circuit design, said method comprising: generating a keepout file from a chip design layout file having chip design layout data, wherein said keepout file includes a map of areas of said integrated circuit design where fill patterns cannot be placed; overlaying said map of areas from said keepout file with a fill pattern to yield a fill-pattern file; removing fill patterns from said fill-pattern file at locations that coincide with locations as defined by said keepout data to yield a final-fill file having fill pattern data; overlaying said fill pattern data from said final-fill file over said design layout data in said chip design layout file to yield a complete design layout file; and verifying design rule integrity and logical to physical correspondence of said complete design layout file.