1. Apparatus for emulating the timing characteristics of a microprocessor, the apparatus comprising: (a) a control signal memory storing data representing a plurality of sets of instructions, each instruction set being stored in a respective region of the said control signal memory and each instruction set comprising a plurality of instructions; (b) a decode memory for receiving a signal specifying a given instruction set to be used for emulating the timing characteristics of a selected microprocessor and for supplying, in response to the instruction set specifying signal, first address signals to the control signal memory to select the region of the control signal memory storing the given instruction set; (c) a sequence control memory for supplying, in response to the instruction set specifying signal, second address signals to select one instruction in the given instruction set; (d) a sequence control latch for supplying the second address signals to the control signal memory; and (e) means for supplying a clock signal to the sequence control latch to actuate the sequence control latch to supply the second address signals to the control signal memory, wherein the control signal memory stores data for producing a WAIT output and wherein the sequence control latch supplies the second address signals to the control signal memory only in response to an external ready input signal, and wherein a change in the ready input signal suspends the supplying of the second address signals by the sequence control latch and causes the control signal memory to produce the WAIT output, so that, in use, the instructions of the instruction set are supplied to emulate the timing characteristics of a microprocessor in a sequence determined by the sequence control memory.