1. A processor, comprising: a plurality of cores; a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a plurality of Advanced Encryption Standard (AES) instructions of an instruction set of the processor that includes a Single Instruction Multiple Data (SIMD) instruction set, wherein the plurality of AES instructions include more than four but less than ten AES instructions including a first AES instruction for a final round of an AES decryption operation, a second AES instruction for a round of the AES decryption operation, a third AES instruction for a round of an AES encryption operation, and a fourth AES instruction for a final round of the AES encryption operation, and wherein the plurality of AES instructions each comprise a different opcode; an L1 data cache; instruction fetch logic to fetch instructions from the L1 instruction cache; decode logic to decode instructions including the first AES instruction; a first 128-bit source register to store a round key to be used for the final round of the AES decryption operation; a second 128-bit source register to store input data to be decrypted by the final round of the AES decryption operation; a plurality of ports each associated with one or more corresponding execution resources to support parallel execution of integer and floating point operations; an execution unit including AES execution logic to execute the first AES instruction to perform the final round of the AES decryption operation, wherein the execution unit is to execute microcode, determined from the decode of the first AES instruction, and obtained from a microcode Read Only Memory (ROM), to execute the first AES instruction, the final round of the AES decryption operation to use the round key from the first 128-bit source register to decrypt the input data from the second 128-bit source register and to store a final decrypted result of the AES decryption operation in a 128-bit destination register, wherein the final round of the AES decryption operation is to include: a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box) lookup; and an inverse Shift Rows operation; and an Add Round Key operation in which an exclusive OR function is to use data from the round key; and a retirement unit.