1. A cache comprising: a plurality of lines addressably organized as a plurality of ways, wherein the plurality of ways addressably organized as at least a first group including a first number of ways and a second group including a second number of ways, and wherein the first number of ways is a different positive integer from the second number of ways; and cache control logic to associate a memory address with one way of the first number of ways and to not associate the memory address with another way of the first number of ways within the first group based on a first portion of a predetermined number of bits in the memory address and to associate the memory address with one way of the second number of ways within the second group based on a second portion of the predetermined number of bits in the memory address.