1. A processor comprising: an issue circuit configured to issue instruction operations for execution in the processor, wherein a first instruction operation in the issue circuit has a plurality of source operands including at least one predicate from a first predicate register and one or more vectors from one or more vector registers, and wherein the issue circuit is configured to issue the first instruction operation responsive to the at least one predicate being a null predicate and wherein the issue circuit is configured to issue the first instruction operation even in the case that at least one of the dependencies on the one or more vectors is unresolved when the first instruction operation is issued.