1. A method for simultaneous multithreading, the method comprising: in response to performing a store instruction for a given thread of threads on a processor core and in response to the processor core having ownership of a cache line in a cache, placing an entry of the store instruction in a given store queue belonging to the given thread, the entry for the store instruction having a starting memory address and an ending memory address on the cache line; comparing, by the processor core, starting memory addresses through ending memory addresses of load queues of the threads on a byte-per-byte basis against the starting memory address through the ending memory address of the store instruction; in response to at least one memory address byte in the starting through ending memory addresses in the load queues of the threads overlapping with a memory address byte in the starting through ending memory address of the store instruction, flushing one or more of the threads having the at least one memory address byte; and in response to no overlap, allowing entries in the load queues of the threads to remain.