1. A method of issuing instructions to be executed by a processing unit, comprising the steps of: receiving a single instruction to be issued that specifies a string of registers including source and destination registers; comparing register IDs in the string of registers with one or more register IDs of registers that have pending writes; generating an aggregate comparison result based on the comparison of the register IDs in the string of registers; issuing the single instruction for execution when the register IDs in the string of registers do not match any of the register IDs of registers that have pending writes; and storing in memory, for a destination register ID of the first destination register in the string of registers, a size indicator that is an integer that reflects only the number of sequential destination registers among the register IDs in the string of registers specified by the single instruction.