1. A neural processing engine comprising: non-transitive electronic storage configured to store instruction code implementing one or more operations; one or more register files configured to electronically and non-transitively store information such that individual ones of the one or more register files comprise: a first packet space into which input packets have been individually transferred by a dispatch unit that is external and independent from the neural processing engine, wherein individual input packets include one or more operands and one or more operator codes, and a second packet space from which output packets are to be individually transferred to the dispatch unit, the output packets including output values; a micro-sequencer configured to, responsive to an individual input packet having been transferred into the first packet space, determine one or more operations to be executed based on the one or more operator codes included in the individual input packet; and an arithmetic logic unit configured to perform the one or more determined operations on the one or more operands included in the individual input packet such that one or more output values are generated by executing the stored instruction code that implements the one or more determined operations, wherein the micro-sequencer is further configured to assemble the one or more output values generated by the arithmetic logic unit as an output packet in the second packet space, wherein the individual input packet includes an operator code of a special instruction that is implemented in a shared processing engine that is external from the neural processing engine, and wherein the micro-sequencer is further configured to transfer one or more special output values, generated by executing the special instruction, from the shared processing engine to assemble in the second packet space.