1. A multi-core processor, comprising: a plurality of processing cores, referred to herein as computing planes, the computing planes being arranged in a hierarchy of levels including a highest level and a lowest level, each of the levels including at least one computing plane, each of the computing planes including a control plane and an associated datapath, each of the control planes including a sequencing instruction memory that is able to store configuration and control information applicable to its associated data path, the configuration information including instructions that control manipulation and routing of data by its associated datapath, each of the control planes being able to receive status information from its associated data path, and being able to provide configuration and control information to its associated data path, each of the datapaths including at least one data input, at least one data output, and at least one element, the element being one of a compute element that is able to manipulate data, an interconnect element that is able to route data, and a storage element that is able to store data, and for at least one of the elements that is in a level above the lowest level, the functionality of the element being provided by a computing plane in a level below the level of the element.