1. A computer-implemented method for electronic design verification comprising: providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages; calculating, using one or more processors, configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design; and storing a seed for each configuration, wherein each seed may be configured to cause a constraint solver to set a defined set of values for one or more random variables in a class associated with the seed wherein the constraint solver is configured to receive a given class with a set of variables and constraints and generate a set of values for the variables that satisfies the constraints.