1. A programmable memory array comprising a plurality of memory sub-arrays programable into a plurality of access modes, at least one of said sub-arrays including: a memory cell for holding data; a first word line that propagates a first select signal; a first bit line; a first selective coupler disposed between said first bit line and said memory cell, selectively coupling said first bit line and said memory cell in accordance with said first select signal for propagating a signal therebetween; an output interface connected to said memory cell for carrying a signal from said memory cell; and an additional data line connected to said memory cell for carrying a signal to said memory cell to enable at least some of said plurality of access modes.