1. A dynamic random access memory device (DRAM), comprising: a storage array to store an N-bit data word, and error checking and correction (ECC) bits associated with the data word; an ECC code store to store a code matrix, the code matrix to include N codes with a first portion of (N/2) codes and a second portion of (N/2) codes, the N codes corresponding to the N bits of the data word, respectively; and ECC circuitry to perform internal ECC in the DRAM with the ECC bits and code matrix in response to a request to access the data word, including circuitry to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively, based on the first and second portions of the code matrix, respectively; wherein a bitwise XOR (exclusive OR) of any two codes in the first portion of the code matrix or a bitwise XOR of any two codes in the second portion of the code matrix is to generate a code that is either not in the code matrix or is in the other portion of the code matrix.