1. In a computer having a processor unit, a memory and a bus for interfacing said processor unit and said memory, said processor unit being operative to fetch instructions and access data stored in said memory, an apparatus for protecting data stored in said memory, comprising means for applying a "read data" instruction to said processor unit, memory access means for detecting a memory access signal generated by said processor unit to access data stored in said memory in response to said instruction, monitoring means for determining whether said instruction was previously fetched from said memory and means responsive to said memory access means and said monitoring means for enabling memory access only if said instruction was previously fetched from said memory.