1. A method of checkpoint acceleration in a simultaneous multithreading (SMT) processor, the method comprising: executing one or more threads in a processing pipeline of a processor core of the SMT processor, the processing pipeline comprising an instruction fetch unit followed by a completion stage followed by a checkpoint stage, the checkpoint stage storing information to establish a recovery state comprising a next instruction address to execute after encountering a fault; storing, in a backlog queue between the completion stage and the checkpoint stage, a list of next-to-complete groups of instructions from the one or more threads anticipated to complete in an upcoming cycle; and driving one or more of the next-to-complete groups of instructions from the backlog queue to the checkpoint stage based on one or more completion indicators identifying which of the one or more groups of instructions actually completed.