1. A hardware element in a Network on Chip (NoC) and/or System on Chip (SoC) comprising: a buffer, configured to store flits of new incoming data as packets for transmission to one or more neighboring hardware elements; and a clock gating circuit that configures the one or more neighboring hardware elements to activate before receiving the new incoming data; and to configure the one or more neighboring hardware elements to sleep after a defined number of cycles, said defined number of cycles are counted from a cycle having non-receipt of incoming data and having a clearance of all data within an input queue of a source hardware element, the defined number of cycles being set based on at least one of a predetermined number of cycles and a calculation based on a self-learning process associated with one or more conditions of the at least one of the SoC and the NoC; wherein the clock gating circuit initiates a hysteresis counter for the one or more neighboring hardware elements being in a sleep state and asserts clock gating based on the hysteresis counter; wherein the clock gating circuit initiates an idle counter for the one or more neighboring hardware elements based on an arrival time of a receipt of the flits of the incoming data corresponding to the one or more neighboring hardware elements.