1. A mathematical operation processing apparatus, comprising: a plurality of computing elements that performs mathematical operations different from one another to produce mathematical operation results, that determines corresponding condition codes of the mathematical operations, and that outputs the mathematical operation results and the corresponding condition codes together; a condition code set register that receives and retains the corresponding condition codes produced simultaneously by said computing elements as a condition code set; a condition code conversion section that performs a predetermined conversion for the condition code set and that outputs a result of the conversion as a conversion condition code set; an operand section that supplies an operand for the mathematical operations in said computing elements and that selects an operand field when a flag selection field is “0” and an output of a flag conversion section when the flag selection field is “1” for the mathematical operations, wherein the output of the flag conversation section is based upon the conversion condition code set.