1. A computer implemented method for modeling an integrated circuit comprising the steps of: establishing by a computer, functional cores of a first software model of an integrated circuit; forming by the computer, high level modules of the first software model by selectively attaching interface code to the functional cores such that the functional cores cooperatively engage to an external environment; creating by the computer, one or more hardware description language modules of the integrated circuit; generating by the computer, the interface code with an interface generator from hardware specification inputs; providing by the computer, the interface code to one or more wrappers, either separately or as an integral part and wherein the one or more wrappers are applied to the same functional cores; refining by the computer, the first software model to provide a second software model, such that designs of the integrated circuit are explored, algorithms of the integrated circuit are appraised and design restrictions of the integrated circuit are reduced; and verifying by the computer, output of the hardware description language modules against output of high level modules of the second software model.