1. An integrated circuit chip, comprising: a processing component configured to process data received via at least one receive queue and to send processed data to at least one transmit queue, wherein respective coalescing latencies associated with the at least one receive queue and the at least one transmit queue are set based on coalescing latency register values respectively associated with the at least one receive queue and the at least one transmit and a base timer register value that is shared by the at least one receive queue and the at least one transmit queue; and a mapping component configured to: set the coalescing latency register values for the at least one receive queue and the at least one transmit queue, and set the base timer register value, wherein the coalescing latency register values and the base timer register values are based on input data, wherein the input data comprises one or more coalescing latency values, and write the coalescing latency register values and the base timer register value to respective hardware registers.