1. A decoder (10) for convolutional self-orthogonal codes comprising a multistage syndrome register (16) for storing a plurality of parity bits (S.sub.47 -S.sub.0); a first majority logic circuit (24) responsive to both a predetermined selection of parity bits from said plurality of parity bits and a plurality of received information bits (X.sub.1 -X.sub.7) for generating a plurality of information correction bits (C.sub.1 -C.sub.7) which correspond in a one-to-one relationship with said plurality of information bits, each information bit comprising a first value (1) when a first threshold level is surpassed and a second value (0) when said first threshold level is not surpassed, said first majority logic circuit producing as an output a plurality of corrected information bits (X.sub.1 -X.sub.7 ; and a second majority logic circuit (26) responsive to the predetermined selection of parity bits from the multistage syndrome register for generating a plurality of syndrome correction bits (S.sub.1 -S.sub.7), each syndrome correction bit comprising a first value (1) when a second threshold level is surpassed and a second value (0) when said second threshold level is not surpassed, said second majority logic circuit producing as an output a plurality of corrected syndrome bits (S') which are subsequently applied as inputs to said multistage syndrome register to replace said predetermined selection of syndrome bits.