1. A processor core for executing a plurality of threads, the processor core comprising: a translation-lookaside buffer (TLB), the TLB comprising: a first TLB portion that includes a first plurality of entries, wherein the first TLB portion is configurable such that the first plurality of entries in the first TLB portion operates in the same mode selected from two modes at any given point in time, and is configurable to switch between the two modes, the two modes comprising: a partitioned mode, wherein respective threads of the plurality of threads are allocated exclusive subsets of the first TLB portion in which to read and write entries of the first plurality of entries, and wherein during translation operations in the partitioned mode, each thread of the plurality of threads is capable of only reading or writing its respective entry from the first plurality of entries in the first TLB portion; and a global mode, wherein the first plurality of entries in the first TLB portion is freely allocated to threads of the plurality of threads, and wherein during translation operations in the global mode, each thread of the plurality of threads is capable of reading or writing to an entry from the first plurality of entries in the first TLB portion; and a second TLB portion including a second plurality of entries, the second TLB portion being configurable to operate in the global mode or the partitioned mode, wherein the second plurality of entries is freely allocated to the plurality of threads in the global mode and the partitioned mode.