1. A processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored in its memory, the processor comprising: instruction type distinguishing means for distinguishing a type of a conditional branch instruction included in the unexecuted instruction sequence, the condition of the conditional branch instruction depending on a prior instruction in the instruction sequence; instruction parallel-issuing means for issuing in parallel for execution by executing units one of a first instruction sequence comprising an instruction sequence logically following the conditional branch instruction if branching does not occur, a second instruction sequence comprising an instruction sequence logically following the conditional branch instruction if branching does occur, and both of said first instruction sequence and said second instruction sequence, said instruction sequences being executed before a decision whether or not to branch is determined, a choice between one of the first, the second and both of said first instruction sequence and said second instruction sequence depending on the type of the conditional branch instruction; a first instruction fetch buffer for temporarily storing the first instruction sequence: a second instruction fetch buffer for temporarily storing the second instruction sequence: instruction fetching means for fetching instructions stored in the memory and selectively writing them into the first instruction fetch buffer and the second instruction fetch buffer; branching determining means for determining whether to branch after the prior instruction has been executed; and execution result managing means for identifying whether the execution results of the instruction sequences are valid based on the results of the branching determining means.