1. A processor for simulating a digital structure comprising: first memory means for storing a description of said digital structure in terms of a list of primitives and interconnections therebetween; second memory means for storing present and previous state data, said second memory means being coupled to said first memory means to receive at least one input state read address therefrom corresponding to a current primitive; primitive evaluator means coupled to said second memory means to receive at least one input state therefrom and to said first memory means to receive a primitive type indicator therefrom, said primitive evaluator means producing a plurality of evaluator outputs; resolver logic means coupled to said primitive evaluator to receive said evaluator outputs therefrom for producing an output state of said current primitive, said resolver logic means being coupled to said second memory means to provide said output state thereto; and program counter means coupled to said first and second memory means for sequentially stepping through said list of primitives and, for each primitive, to provide a primitive number to said first memory means and an output state write address to said second memory means.