1. A dynamic multistreaming processor comprising: a plurality of instruction queues, each instruction queue corresponding to an instruction stream; a plurality of execution units; a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units; a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue; and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full.