1. A pipelined processing device, comprising: a processor configured to receive a request to perform an operation, the processor comprising: a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including error detection logic shared by each of the plurality of processing controllers, the shared error detection logic configured to check each instruction that passes through the pipeline processor, and detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.