1. A domino SRAM memory array, the memory array receiving a plurality of address bits consisting of least-significant bits and most-significant bits, the memory array comprising: a plurality of SRAM cores having wordlines; a wordline decoder receiving the least-significant bits and providing wordline selection signals to all SRAM cores in parallel; a core decoder receiving the most-significant bits and providing first core select signals; input terminals to receive second core select signals; and a read/write multiplexer receiving the first and second core select signals, and providing each of a plurality of third core select signals to a corresponding one of the SRAM cores; wherein the third core select signals are controlled by the first core select signals in correspondence with a read operation, and by the second core select signals in correspondence with a write operation.