1. A CPU employing System Management Mode (SMM), the CPU being capable of initiating transactions between the CPU and an SMRAM when the CPU is in SMM, a transaction having an address and data associated with it, the CPU comprising: a cache having cache entries, each cache entry having associated with it a cache tag entry, a cache data entry, and an SMRAM status bit; means for determining whether an address associated with a given transaction is within a range of addresses defining the addressable location of SMRAM; means for indicating whether the CPU is in SMM; means for writing the data associated with the transaction into a cache data entry, and means responsive to the means for determining and to the means for indicating for setting the SMRAM status bit corresponding to the cache data entry if the CPU is in SMM and the address is within the range of addresses.