1. An apparatus comprising: an execution logic that includes circuitry to execute instructions; and an instruction execution scheduler logic that includes circuitry coupled with the execution logic, the instruction execution scheduler logic to receive an execute at commit state update instruction, the instruction execution scheduler logic including: at commit state update logic to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit, wherein the execution of the execute at commit state update instruction is to update internal state of a processor that is not renamed including at least one of a flag of the processor and a bit in a control register of the processor.