1. A packet buffer random access memory (PBRAM) device, comprising: (a) a memory array; (b) a plurality of input and output ports to be coupled to a network controller device, the memory array for storing packet data received by the plurality of input ports being shared by the plurality of input and output ports; and (c) a plurality of serial registers associated with the input and output ports, the serial registers simultaneously receiving packet data from the input ports and writing packet data to the memory array, the serial registers further being segmented into a plurality of segments, segments of respective serial registers being associated with corresponding portions of the memory array, segments of different serial registers simultaneously transferring packet data to different portions of the memory array.