1. A distributed logic simulator for simulating a circuit, said simulator comprising: a plurality of processors or computing nodes; a plurality of logic simulation program means, executing on respective ones of said processors or computing nodes, for simulating respective parts of the circuit, each of said logic simulation program means executing at its own pace, including means for receiving an input from or supplying an output to another of said processors or computing nodes, and including means for predicting an input when unavailable from another of said processors or computing nodes; host means for broadcasting a breakpoint time to said processors or computing nodes; and a plurality of logic simulation control means, executing on respective ones of said processors or computing nodes, for directing storage of nets and/or states of the simulated logic, receiving the breakpoint time and reporting to said host means when the respective logic simulation program means has advanced to or past said breakpoint time; and wherein said host means determines when all of said processors or computing nodes have reported that the respective logic simulation program means has advanced to or past said breakpoint time.