1. A method of accessing common registers in a register domain in a multi-core processor, comprising: streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain, both the core domain and the register domain being different clock domains in the same multi-core processor; determining if the at least one transaction is addressed to the common registers before staging the at least one transaction for the common registers; and reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.