1. A computer implemented method of circuit equivalence checking, comprising: solving at least a first equivalence checking problem, wherein the act of solving at least the first equivalence checking problem is performed by a processor; storing at least a first solution to at least the first equivalence checking problem; reusing at least part of the first solution to the first equivalence checking problem for a second equivalence checking problem, wherein the first equivalence checking problem includes determining one or more sensitizing simulation vectors and the first solution includes one or more problem signatures, and the one or more problem signatures include logic cones sensitized by the one or more sensitizing simulation vectors; and storing the one or more problem signatures in a memory.