1. An apparatus comprising: a first processor configured to store, at a first memory that is external to and accessible to a second processor, addresses of address translation tables, the addresses stored in configuration blocks of the first memory; and the second processor configured to: store, at a memory of the second processor, a table of pointers to the configuration blocks of the first memory; identify, in the table of pointers, a first pointer to a first configuration block based on an index operand of an instruction; read, from the first configuration block, an address of a first address translation table based on the first pointer; and load the address, from the first configuration block of the first memory, into a register of the second processor, wherein the register of the second processor is configured to be exclusively writeable responsive to execution of the instruction based on a value of a write enable signal received from the first processor, wherein the instruction includes an override operand to indicate whether to override contents of the register of the second processor.