1. Arithmetic logic processing circuitry, comprising: a global carry chain implementing static propagate, kill, and generate circuitry, including, a first stage for generating first propagate, kill, and generate signals for each bit of a pair of multi-bit signal vectors; a second stage for generating second propagate, kill, and generate signals for a first group of the first propagate, kill, and generate signals; a third stage for generating third propagate, kill, and generate signals for a first group of the second propagate, kill, and generate signals; and a fourth stage for generating carry signals and carry complement signals, the fourth stage receiving inputs from each of the second stage and the third stage, the carry signals and the carry complement signals being useful for generating one of a sum result and a subtraction result.