1. A configurable memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP) in a wireless communications system, for generating output vectors from sequential input data vectors, comprising: a rotate-and-distribute unit configured to rotate and distribute input data elements of the input data vectors; a two-dimensional register file configured to receive and store vectors generated by the rotate-and-distribute unit; a write controller configured to control writing of the vectors in the two-dimensional register file by generating write-enable signals for cells of the two-dimensional register file; and a read controller configured to generate the output vectors by reading on a per column basis selected cells of the two-dimensional register file, wherein, the write controller is further configured to control the writing in the two-dimensional register file such that at least two of the input data elements pertaining to a same vector among the input data vectors are stored in cells on different rows and different columns of the two-dimensional register file.