1. An apparatus comprising: a plurality of memory tiles including a first memory tile, each memory tile of the plurality of memory tiles comprising an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors; and selection circuitry including line drivers configured to select a storage component of a memory tile of the plurality of memory tiles based on a corresponding digit line conductor and a corresponding access line conductor to the storage component, wherein the selection circuitry is configured to select two or more storage components of the first memory tile in a consecutive manner before selecting the storage components of a different memory tile of the plurality of memory tiles.