1. An integrated circuit comprising: A. a test data in lead; B. a test data out lead; C. a test clock in lead; D. a test mode select in lead; E. TAP controller circuitry connected to the test clock in lead and the test mode select lead and having control outputs; F. instruction register circuitry coupled between the test data in lead and the test data out lead, the instruction register circuitry having control inputs connected with the control outputs; G. boundary scan circuitry coupled between the test data in lead and the test data out lead, the boundary scan circuitry having control inputs connected with the control outputs and having delay select outputs; and H. clock delay circuitry including separate delay circuits, each having an input connected with the test clock in lead and having a time delay output, the clock delay circuitry including select circuitry having inputs connected to the outputs of the delay circuits, control inputs connected with the delay select outputs, and a delayed clock out lead.