1. A method implemented on a data processing system for circuit design, the method comprising: identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing critical nets; generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions; executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design.