1. An apparatus for non-blocking execution of a static scheduled processor, the apparatus comprising: a processor to process at least one operation using transferred input data; and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor comprises at least one functional unit (FU) to execute the at least one operation, wherein the at least one FU selectively processes the transferred input data using at least one of a regular latency operation and an irregular latency operation.