1. A method of partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level, the method comprising: identifying a desired number of blocks for the second hierarchical level; representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary; identifying transistor networks that extend across block boundaries; assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and reassigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block.