1. A processor comprising: transactional memory circuitry to process a region of transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to initiate the region of transactional memory operations, a transaction end instruction to indicate an end of the region of transactional memory operations, and a transaction abort instruction to abort processing of the transactional memory operations; transaction failure detection circuitry to detect a transaction failure responsive to conflicting load and store operations, wherein a transaction failure is to be generated in response to detecting data loaded by a first transaction being modified by a second transaction; a status circuit to store an indication as to whether a transaction is valid or invalid, the status circuit to set the indication to invalid upon the transaction failure; locking circuitry to allow a transaction to acquire a lock on a critical section of instructions, wherein the transactional memory circuitry is to, upon that the lock is found to be free, attempt to speculatively execute a critical section of instructions as transactions on multiple threads without initially acquiring the lock; the locking circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.