1. An apparatus, comprising: an execution unit configured to execute instructions having up to N possible source operands, wherein N is greater than 1; a register file configured to store a plurality of operands for instructions to be executed by the execution unit; an operand cache configured to store a subset of the plurality of operands stored in the register file; and fetch circuitry configured to retrieve operands specified by instructions to be executed by the execution unit, wherein the fetch circuitry, in response to a particular instruction using fewer than N source operands, is configured to prefetch one or more operands from the register file and store the one or more prefetched operands in the operand cache, and wherein the one or more operands are for an instruction other than the particular instruction.