1. A method comprising: providing a memory array comprising a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.