1. A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a first thread scheduler that outputs a thread selection signal in accordance with a first schedule or a second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads; a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread; and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the first thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the first thread scheduler selects the second schedule.