1. A system comprising: a system memory adapted to hold an address based table, the address based table to hold an entry at a first address, wherein the entry is to be updated to add a representation of a second address associated with a value; and a processing element in a processor, which is coupled to the system memory, the processing element including a cache memory, wherein an annotation field is to be associated with a cache line of the cache memory and the cache line is to be associated with the second address, wherein, in response to the entry being updated to add the representation of the second address associated with the value, a buffered store of the value to the cache line is to be performed, and wherein a cache line is to be transitioned to a buffered coherency state in response to the buffered store of the value to the cache line being performed.