1. A multi-thread content-addressable memory (CAM) device comprising: a first input configured to receive a first virtual address corresponding to a first thread; a second input configured to receive a second virtual address corresponding to a second thread; a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses; a first comparator bank including a first plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration, wherein each of the first plurality of comparators is configured to compare the first virtual address to a binary word stored in a register associated therewith for determining whether a first match is present; and a second comparator bank including a second plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration, wherein each of the second plurality of comparators is configured to compare the second virtual address to a binary word stored in a register associated therewith for determining whether a second match is present.