1. A microprocessor comprising: an instruction device configured to store a loop of instructions including a first instruction; a plurality of decode units coupled to said instruction device and configured to decode said loop of instructions conveyed from said instruction device, wherein the plurality of decode instructions decodes the loop of instructions in a first single clock cycle; a plurality of functional units coupled to said plurality of decode units, wherein the plurality of functional units are configured to execute the decoded loop of instructions conveyed from said decode unit, wherein the plurality of functional units executes the decoded loop of instructions in second single clock cycle subsequent to the first single clock cycle; wherein said first instruction causes said instruction device to repeatedly convey said loop of instructions to said plurality of decode units until a termination condition is detected.