1. Interconnect logic for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed, each transaction comprising an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit, the interconnect logic comprising: a plurality of connection paths operable to provide at least one address channel for carrying address transfers, at least one read data channel for carrying data transfers of read transactions from said slave logic units to said master logic units, and at least one write data channel for carrying data transfers of write transactions from said master logic units to said slave logic units; and control logic operable to control the use of the at least one address channel, the at least one read data channel and the at least one write data channel in order to enable the transactions to be performed; the control logic comprising: address arbiter logic operable for an associated address channel to arbitrate between multiple address transfers seeking to use that associated address channel; read data arbiter logic operable for an associated read data channel to arbitrate between multiple data transfers seeking to use that associated read data channel; and write data arbiter logic operable for an associated write data channel to arbitrate between multiple data transfers seeking to use that associated write data channel; each of the read data arbiter logic and write data arbiter logic being operable independently of the address arbiter logic such that the one or more data transfers of multiple transactions can occur out of order with respect to the corresponding address transfers of those multiple transactions.