1. A timing recovery circuit comprising: an interpolator configured to generate an interpolated signal; an estimator configured to generate a first output signal based on the interpolated signal; a noise prediction filter configured to generate a compensation signal based on interpolated signal and the first output signal; a first mixer configured to mix the interpolated signal with the first output signal and to output the mixed signal to the noise prediction filter; and a second mixer configured to mix the compensation signal with the interpolated signal to generate the timing recovery circuit output signal.