1. A networking application processor, comprising: an input socket configured to receive data packets; a memory for storing instructions; circuitry configured to access data structures associated with a processing stage, the circuitry configured to access data structures enabling a single cycle access an operand from a memory location; an arithmetic logic unit (ALU); and circuitry for aligning operands to be processed by the ALU, the circuitry for aligning operands causing the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.