1. A multithreaded processor comprising: a plurality of hardware thread units each comprising a memory unit; an instruction decoder coupled to the plurality of hardware thread units; a plurality of execution units responsive to the instruction decoder; a first register file including a first plurality of registers, the first register file coupled to the memory unit and coupled to each of the plurality of execution units, the first register file supporting execution of a program instruction of a first program thread, the first register file including a first data operand and a first address operand; and a second register file including a second plurality of registers, the second register file coupled to the memory unit and coupled to each of the plurality of execution units, the second register file supporting execution of a program instruction of a second program thread, the second register file including a second data operand and a second address operand, wherein the first and second register files are accessed based upon a thread identifier and an address of an entry in the register file, wherein the multithreaded processor is configured for controlling an instruction issuance sequence for the first program thread and the second program thread associated with respective ones of the hardware thread units, wherein on a processor clock cycle one of the first program thread and the second program thread is permitted to issue one or more instructions, the thread permitted to issue instructions varying over a plurality of clock cycles in accordance with the instruction issuance sequence; and wherein the instructions are pipelined to permit one of the first program thread and the second program thread to support multiple concurrent instruction pipelines, and wherein the pipelined instructions include an instruction having a pipeline with a computational cycle which is longer than an instruction issue cycle of the multithreaded processor, and wherein results for a first instruction for a program thread are always written to a register file before the results are needed by a second instruction for the program thread without stalling the second instruction and without dependency checking and bypassing hardware.