1. An apparatus for preventing malfunction of pipeline processing associated with a program that modifies an instruction queued for execution, said apparatus comprising: an instruction pipeline which performs overlapped processing of a plurality of executing instructions and aborts processing of selected ones Of said executing instructions; a prefetch buffer, when active said prefetch buffer holding a plurality of instructions queued for possible execution by said pipeline; an address storage holding a first address value that identifies a block of addressee including said plurality of instructions held in said prefetch buffer; a comparator having e first input coupled to receive said first address value from said address storage and a second input coupled to receive a second address value from said pipeline; and a control circuit coupled to said comparator and to said pipeline, said control circuit aborting further processing of said selected ones of said executing instructions when said program includes a store instruction and said pipeline generates said second address for said store instruction and said comparator detects that said second address value corresponds to said first address value, thereby restarting said pipeline when said program modifies an instruction in a block of instructions that includes said queued instructions.