1. A computer-implemented method of designing layouts of integrated circuits, the method comprising: performing a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit; extracting parasitics of the integrated circuit based on the netlist and the layout; performing static timing analysis on the netlist based on the layout and the parasitics, to estimate timing behavior of the netlist and to identify at least one violation by said timing behavior of a corresponding timing requirement at an endpoint of a path in the netlist; performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said timing behavior, and said violation by: (a) identifying a plurality of victim nets located in a fanin cone of said endpoint and identifying a group of aggressor nets, wherein each aggressor net is capacitively coupled to one of said victim nets; (b) forming a set of candidate nets including said group of aggressor nets and said plurality of victim nets; (c) estimating at least one change in timing behavior of each candidate net required to be made to overcome said violation; and (d) choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c); generating an ECO constraint on timing behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation; automatically selecting said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and repairing said layout by applying said ECO repair technique to generate a modified layout corrected for said violation.