1. Graphics data processing logic comprising: a plurality of parallel arithmetic logic units that operate as a vector processor on at least one of pixel data and vertex data; a programmable storage element containing data representing which of the plurality of arithmetic logic units are not to receive data for processing; and parallel ALU data packing logic operatively coupled to the plurality of arithmetic logic units and to the programmable storage element and operative to pack data only for the plurality of arithmetic logic units identified by the data representing which of the plurality of arithmetic logic units that are not to receive data for processing.