1. A scheduling apparatus capable of providing an interface between a memory and at least a first and second device, the scheduling apparatus comprising: a memory request arbiter capable of controlling access to the memory by different devices having different priorities; and at least one counter coupled to the memory request arbiter, wherein the at least one counter is associated with at least the first device of the at least two devices, and wherein the at least one counter enforces a time-period that precludes access by the first device to the memory.