1. An apparatus, comprising: a floating point vector register file containing at least two floating point registers; a permute unit coupled to the floating point vector register file, the permute unit having at least two operand inputs for receiving input operands containing data to be permuted from the at least two floating point registers, and at least one control vector input for receiving a control vector indicating a permutation pattern as a floating point vector; and a result vector register coupled to the permute unit, wherein the permute unit generates a result output, that is stored in the result vector register, based on a permutation operation performed by the permute unit on the input operands according to the control vector.