1. A method for predicting time-varying behavior of signals of a circuit that are referenced by a register transfer level (RTL) description of the circuit, wherein the signals comprise internal signals and other signals, wherein the other signals consist of all circuit input and output signals, and all input and output signals of memory devices described as being included in the circuit, and wherein the RTL description of the circuit indicates that the circuit derives the internal signals from the other signals, the method comprising the steps of: a. processing the RTL description of the circuit to determine logical relationships between the internal signals and the other signals and to identify the memory devices; b. processing the RTL description of the circuit to synthesize a first gate level description of the circuit including the memory devices identified at step a, wherein the first gate level description references the other signals but omits reference to the internal signals; c. processing the first gate level description of the circuit to program a circuit verification system to produce waveform data representing time-varying behavior of the other signals of the circuit; and d. processing the waveform data generated by the circuit verification system to produce additional waveform data representing behavior of the internal signals referenced by the RTL description of the circuit in accordance with the determined logical relationships between the internal signals and the other signals.