1. An apparatus comprising: circuitry to perform at least one of the following subparagraphs (a) and (b): (a) execution, at least in part, of a first list of instructions, the execution resulting, at least in part, from invocation of a first function call, the first list of instructions comprising at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions, the at least one portion and the at least one other portion to be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry, the second list and the third list of instructions being to implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls; and (b) concurrent processing, at least in part, of a first buffer and a second buffer, the concurrent processing involving, at least in part, complementary algorithms.