1. A multi-byte cyclic redundancy check calculation circuit, comprising: a plurality of modules each configured to receive remainder bits in first inputs thereof and different numbers of portions of an input message in second inputs thereof and compute candidate cyclic redundancy check bits based thereon; a storage element configured to receive output bits from one of said plurality of modules and provide said output bits to said first inputs as said remainder bits; and a multiplexer coupled to first outputs of said plurality of modules and configured to select from among said candidate cyclic redundancy check bits to yield a cyclic redundancy check for said input message.