1. A computational unit in an adaptable computing engine, wherein the computational unit includes a clock signal for determining a processor cycle, the computational unit comprising one or more functional units coupled by a bus, wherein the one or more functional units include functional unit inputs; at least one register coupled between the bus and at the input of least one functional unit input; and a control signal for selectively causing the at least one register to hold a data value from the bus for one or more processor cycles.