1. In a field-programmable gate array, a random-access memory block comprising: a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations; at least two programmably invertible enable inputs; hardwired decoding logic coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array; a gate coupled to the output of the random-access memory array and configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.