1. A method for handling a number of exceptions within a processor in a multi-processing system, the method comprising: receiving an exception within the processor, wherein each processor in the multi-processor system shares a same memory; executing a number of instructions at an address within a common interrupt handling vector address space of the same memory, wherein the number of instructions cause the processor to determine an identification of the processor based on a query that is internal to the processor; and modifying execution flow of the exception to execute an interrupt handler located within one of a number of different interrupt handling vector address spaces.