1. Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each for holding a plurality of elements of an ordered set of data; one or more arithmetic or logical functional units each having an input for receiving operands and an output for delivering results, said functional units each including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means responsive to program instructions or selectively connecting individual vector registers for transmitting data as operands to the functional units and for receiving results from the functional units; and, control means connected to control said vector registers in response to program instructions, said control means operative in conjunction with a vector register selected as an operand register in a vector processing operation for causing said selected operand register to successively transmit the elements of the ordered set of data from the vector register to a connected functional unit provided that one or more elements are available in the selected register and for sending a go write signal to said connected functional unit each time an element is transmitted thereto; each of said functional units further including means for receiving and delaying said go write signal a number of clock periods corresponding to the number of clock periods used by the functional unit to perform an operation and for subsequently sending said delayed go write signal back to said control means so that each result produced by the functional unit is signalled by the sending of the go write signal back to said control means; and said control means further operative in conjunction with a vector register selected as a result register in a vector processing operation for causing said selected result register to receive and store a result produced by a connected functional unit as an element of an ordered set of data representing a result vector in response to said delayed go write signal from said connected functional unit so that elements of an ordered set of data are processed under element-by-element control to permit the speed of a stream of vector processing operations to vary according to the availability of elements from the vector registers.