1. An apparatus comprising: circuitry to perform the following subparagraphs (a) and (b): (a) execution, at least in part, of a first list of instructions, the execution resulting, at least in part, from invocation of a first function call, the first list of instructions comprising at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions, the at least one portion and the at least one other portion to be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry, the second list and the third list of instructions being to implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls; and (b) concurrent processing, at least in part, of a first buffer and a second buffer, the concurrent processing involving, at least in part, complementary algorithms; wherein: at least one tool is to select the at least one portion and the at least one other portion so as to permit executing of the at least one portion and the at least one other portion in the first list of instructions by the one or more sets of execution units to exhibit a relatively higher degree of parallel execution in the one or more sets of execution units relative to a relatively lower degree of parallel execution that would occur if the at least one portion and the at least one other portion were to be executed as a result of separately invoking the separate respective function calls, the at least one tool permitting user selection of the at least one portion and the at least one other portion (1) at instruction-level interleaving granularity, and (2) such that the at least one portion and the at least one other portion are to be executed, at least in part, by different respective execution units in a single respective core; and the concurrent processing results, at least in part, from the execution, at least in part, of the first set of instructions.