1. A content addressable memory (CAM) device, comprising: a CAM array including a plurality of rows, each row including a number T of quaternary CAM cells coupled to a match line; and a programmable write circuit coupled to the CAM array and configured to selectively store, within each CAM cell of a selected CAM row, either a single data bit of a first data word or two data bits of an encoded data word, wherein none of the data bits are mask bits, wherein the first data word includes T data bits that represent UP to 2 T possible states, and the encoded data word includes 2T data bits that represent up to S=(2T)!/(T!) 2 possible states, wherein T is an integer greater than 2.