1. A debugger interface unit for identifying accesses to selected exception routines within a data processing apparatus, comprising: a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine; an exception routine catch logic arranged to determine from an instruction address issued with an instruction fetch command which exception routine is indicated by the instruction address and being arranged to receive a first signal indicating that the instruction fetch command is an instruction fetch command for an exception routine issued by a processor core within the data processing apparatus; the catch logic further being arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set; the catch logic being arranged to issue a breakpoint signal if an exception routine is determined from the instruction address, if the first signal is received by the exception routine catch logic, and if the field corresponding to the determined exception routine is set.