1. A suite of generation tools to generate a plurality of design views of a semiconductor chip, each of the generation tools comprising: (a) a manager whose input comprises available physical and logical resources and a desired chip specification; (b) a resource allocation database interfacing with the manager to inventory what physical and logical resources have been used to create design views of the desired chip specification and what physical and logical resources remain available; (c) a resource selector to interact with the manager and resource allocation database to select available physical and logical resources to create the design views; and (d) a composer, interactive with the resource selector, which generates the design views.