1. A memory operable in an active operational mode having an active rate of power consumption and a standby operational mode having a predetermined reduced rate of power consumption lower than said active rate, comprising: a current generating circuit operable to supply a predetermined magnitude of current to a sample power supply input terminal of at least one sample memory cell representative of memory cells of said memory, said predetermined magnitude of current corresponding to said predetermined reduced rate of power consumption; a voltage follower circuit operable to output a standby voltage level equal to a voltage level at said sample power supply input terminal when said predetermined magnitude of current is supplied to said sample power supply input terminal; a memory cell array operable to store data; a switching circuit operable to supply power to a power supply input terminal of said memory cell array at said standby voltage level in said standby operational mode to permit data to remain stored in said memory and to supply power to said power supply input terminal at said active voltage level during said active operational mode to permit data to be stored into said memory cell array and retrieved from said memory cell array.