1. A method of performing a Design Rule Check of an IC design, comprising: partitioning a geometry associated with the IC design; determining distances within various points in the geometry; creating connectivity graphs by a processor between a source and a destination for the various points in an nwell or pwell structure of the geometry, wherein distances associated with the various points in the nwell or pwell structure are measured by traversing a plurality of different paths between the source and the destination of the connectivity graphs; storing the connectivity graphs on a volatile or non-volatile computer usable medium device or displaying the connectivity graphs in a display device; and analyzing the connectivity graphs to determine if a design rule has been violated.