1. A parallel data processor having a plurality of cells for processing digital data signals, comprising: a controller for generating control signals in response to program instructions; and, a plurality of identical interconnected cells each including a full adder having two data input terminals, a carry input terminal, a sum output terminal, and a carry output terminal, and a plurality of memories connected to said full adder and said controller, the memories each being individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of said full adder in response to control signals from the controller, the memories being connected to the full adder and the controller such that both logical and arithmetic operations are performed by the full adder.