1. An integrated circuit chip comprising: a monocrystalline silicon portion on said chip; a polycrystalline portion on said chip; a first plurality of of circuit elements on said monocrystalline silicon portion; a second plurality of circuit elements on said polycrystalline silicon portion; and circuitry for configuring said first and second plurality of circuit elements in a memory cell configuration and for alteratively configuring said first plurality of circuit elements and disabling said second plurality of circuit elements for a logic gate configuration.