1. A processor comprising: an execution resource, said execution resource executing a first instruction, said execution resource being unavailable to receive an additional instruction for execution until completion of execution of said first instruction, said execution resource indicating a number of clock cycles until availability to receive said additional instruction before completion of execution of said first instruction; an instruction storage unit, said instruction storage unit having a plurality of entries that contain instructions to be executed, said entries comprising a field indicating a number of clock cycles until an associated instruction is ready to execute; a scheduler, said scheduler locating a first entry in said instruction storage unit wherein said field indicating a number of clock cycles until said associated instruction is ready to execute that matches said number of clock cycles until availability, said scheduler dispatching said associated instruction from said first entry to said execution resource so as to minimize latency between a time said execution resource completes executing said first instruction and a time said execution resource begins executing said associated instruction from said first entry.