1. A method comprising: in at least one core processor, generating at least one memory access request responsive to a hardware thread, using a first addressing scheme; in a TLB, converting the first addressing scheme to a second addressing scheme; in an L1 cache and/or prefetch unit, accessing cache lines for more than one hardware thread responsive to the second addressing scheme; and converting the second addressing scheme to a third addressing scheme responsive to a hardware thread number; in a second cache, managing memory access requests responsive to the third addressing scheme and a speculation identification number; creating a fourth addressing scheme for accessing main memory; and accessing main memory responsive to the fourth addressing scheme.