1. A multi-voltage domain control circuit for a memory array comprising: multi-voltage domain decoding logic configured to generate a wordline for the memory array; multi-voltage domain mimic logic configured to mimic the multi-voltage domain decoding logic to generate a dummy wordline; the multi-voltage domain decoding logic comprising: low voltage domain decoding logic; high voltage domain decoding logic; and high voltage domain final decoding logic configured to combine and level-shift outputs of the low voltage domain decoding logic and the high voltage domain decoding logic to generate the wordline; and the multi-voltage domain mimic logic comprising: low voltage domain mimic logic configured to mimic the low voltage domain decoding logic; high voltage domain mimic logic configured to mimic the high voltage domain decoding logic; and high voltage domain final mimic logic configured mimic the high voltage domain final decoding logic to combine and level-shift outputs of the low voltage domain mimic logic and the high voltage domain mimic logic to generate the dummy wordline.