1. A processor interface device, comprising: at least one memory port, said at least one memory port adapted to transfer data and signals to and from a storage device; at least one function port, said at least one function port adapted to transfer data and signals to and from a macro function; a data transfer fabric adapted to transfer data and signals between said at least one memory port and said at least one function port, and an arbitration unit adapted to arbitrate access to various portions of said memory by said macro function.