1. A method for chargeback with simultaneous multithreading (SMT) by a computer, the method comprising: managing, by one or more of an operating system and a second-level hypervisor of the computer, a logical core configuration for simultaneous multithreading, the one or more of the operating system and the second-level hypervisor having control over a logical core and control over logical threads on the logical core; configuring, by the one or more of the operating system and the second-level hypervisor of the computer, a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core; running the logical core on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core; and determining a capacity use time for each of the logical threads executing on the physical threads of the single physical core.