1. In a digital processing system including a processor with an internal clock and an external memory, a memory interface connected between the processor and external memory, the memory interface comprising: an information transfer bus operably connected between the processor and the external memory for transferring of information between the processor and the external memory; control means connected to the information transfer bus and the processor for generating at least one control signal for synchronously controlling the transfer of information on the information bus by controlling the time at which the processor reads information from the external memory; flip-flop means having a first logic state and a second logic state for selecting whether to time delay the control signal; and wait circuit connected to said control means and said flip flop means for delaying the control signal by a first time delay when the flip flop means is at the first logic state.