1. A method for analog circuit placement which is executed in a computer to perform a layout for an analog circuit, the method comprising: inputting a plurality of modules, a netlist and a constraint file; creating a QB-tree construction by combining a B*-tree and a quadtree based-on said plurality of modules and said constraint file; performing a node perturbation of said QB-tree; performing a look-ahead constraint checking to check whether meet constraints of said constraint file or not; performing a QB-tree packing when meet constraints of said constraint file; and performing a cost evaluation to guide a simulated annealing process.