1. Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising: at least two memory half-matrices; a bidirectional internal bus for the transmission of data to and from the memory half-matrices, said bidirectional internal bus extending between respective half-matrices; a programming unit for each one of said at least two memory half-matrices; and a data sensing unit; said programming units being adapted to program said at least two memory half-matrices by transferring programming data from said bidirectional internal bus; and said data sensing unit and said programming units communicating with said bidirectional internal bus to reroute, onto said bus, reading data and programming data of said at least two memory half-matrices.