1. A computer-implemented method of managing test transactors, the method comprising: launching, by a processor, a first set of one or more transactors from a plurality of transactors that send stimuli to one or more components of a hardware design, wherein each transactor corresponds with one of the components; receiving, in a memory accessible from the processor, one or more first sets of results from one or more of the first set of transactors indicating resulting data from the stimuli by the hardware design components corresponding to the transactors from which the first sets of results were received; automatically identifying, by the processor, from the plurality of transactors, a second set of one or more transactors, that have been predefined as being dependent upon the one or more first set of transactors from which the first sets of results were received; and automatically launching, by the processor, the identified second set of transactors that send stimuli to one or more of the components of the hardware design.