1. A method for massive parallel testing of resistive type memories, the method comprising: coupling bit lines of a plurality of resistive type memory cells to a current driver, and source lines of the memory cells to a common plane voltage (VCP) pad or external pin; holding the VCP pad or external pin at a test write voltage level for a period of time associated with a test write pulse width while the current driver pulls the bit lines to a ground voltage level; driving, in parallel, a first write test current to flow in a first direction through the memory cells to write first data to the memory cells; holding the VCP pad or external pin at the ground voltage level for the test write pulse width or time while the current driver pulls the bit lines to the test write voltage level; and driving, in parallel, a second write test current to flow in a second direction opposite to the first direction through the memory cells to write second data opposite to the first data to the memory cells.