1. In a computer memory having a plurality of memory banks each containing a plurality of addressable memory cells, the memory being arranged to store vectors such that data elements of each vector are stored in memory cells in different memory banks in an interleaved pattern, each vector having an initial address and spacing data representing a spacing between successive addresses, the improvement comprising, for each memory bank: setup apparatus for receiving the initial address and spacing data for each of a plurality of vectors; cell select apparatus responsive to the memory for accessing a memory cell using a memory cell select associated to a respective one of the initial and successive addresses of each vector; and addressing logic responsive to the setup apparatus and the cell select apparatus for associating a memory cell select to each initial and subsequent address of each of the plurality of vectors.