1. A method of data register allocation in a computer instruction set having tiered instructions whereby corresponding instructions of differing tiers access differing data register sets including differing numbers of data registers comprising the steps of: making a first preliminary attempt to allocate data registers for operand storage using an initially specified data register set for each instruction; if the first preliminary attempt to allocate data registers fails identifying any tiered instruction having an initially specified tier with a corresponding data register set less than all data registers having an input or output variable not data register allocatable, and making a second preliminary attempt to allocate data registers for operand storage using the initially specified data register set for each instruction except using a corresponding instruction of a differing tier having a less restrictive data register set for the identified tiered instructions.