1. A method, comprising: receiving, by a processor, an instruction stream; selecting, by the processor, a group of instructions from the instruction stream; extracting, by the processor, a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits; decoding, by the processor, the sequence of chaining bits; identifying, by the processor, zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits; and outputting, by the processor, control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the selected group of instructions.