1. A data processing device using pipeline control, comprising: an instruction queue in which a plurality of instruction codes are fetched and stored; a fetch address operation circuit that calculates a fetch address, the fetch address being used to fetch and store an instruction code in the instruction queue; a fetch circuit that fetches an instruction code, the instruction code being read out from a memory based on the fetch address and being stored into the instruction queue; and a branch information setting circuit that decodes a branch setting instruction, the branch setting instruction explicitly or implicitly specifying a branch occurring address and a branch target address, a branch to the branch target address occurring when the fetch address is the branch occurring address after a x-th instruction from the branch setting instruction, x being a non-zero positive integer, the branch information setting circuit storing the branch occurring address in a branch occurring address storage register and the branch target address in a branch target address storage register, when the branch setting instruction is decoded, the fetch address operation circuit including a circuit that compares one of a previous fetch address and an expected next fetch address with a value stored in the branch occurring address storage register, and then determines whether or not to output a value stored in the branch target address storage register as a next fetch address, based on the comparison result.