1. An instruction fetch control apparatus having a branch history in which an instruction address of a branch instruction and an address of a branched-to instruction for use when a branch is taken are registered as a set of data for the branch instruction, and a return address stack having a top-of-stack and pushing a returned-to instruction address of a subroutine when a subroutine call instruction is completely executed, and popping the return address stack when a subroutine return instruction is completely executed, comprising: an instruction execution completion notifier reporting completion of instruction execution; and an entry designation unit predicting a return address of a subroutine during an instruction fetching by designating as a predicted return address a designate entry in the return address stack storing return addresses of subroutine calls and fetching a predicted return address of a subroutine using the return address stored in a designate entry of the return address stack, wherein the entry designation unit computes a position of a designate entry in the return address stack relative to a leading entry of the return address stack by: when a subroutine call instruction is predicted during an instruction fetching, changing the designate entry independently of a push or pop operation of the return address stack to indicate a one-step shallower entry of the return address stack relative to the leading entry of the return address stack, when a subroutine return instruction is predicted during an instruction fetching, changing the designate entry independently of a push or pop operation of the return address stack to indicate a one-step deeper entry of the return address stack relative to the leading entry of the return address stack and, and changing the designate entry depending upon a push and pop operation of the return address stack when a subroutine call and a subroutine return instruction is completely executed according to the reporting of completion of instruction execution, thereby keeping a position of the designate entry relative to the leading entry of the return address stack, and wherein the entry designation unit designates an entry in the return address stack as a predicted return address of a subroutine under a condition that an instruction is fetched from a main storage device, the instruction is detected as a hit in the branch history, and the instruction is determined as a return instruction from a subroutine.