1. A method of generating test patterns for testing an integrated circuit, comprising: determining hold probabilities for state elements of a circuit design, the hold probability for a respective state element indicating the probability that the respective state element will output the same logic value during two or more consecutive clock cycles; generating a test cube targeting one or more faults in the circuit design, the test cube initially comprising specified values that target the one or more faults and further comprising unspecified values; modifying the test cube by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities; and storing the modified test cube.