1. A processor, comprising: at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch target address cache that outputs predicted branch target addresses for use as instruction fetch addresses, said branch target address cache including: a branch target buffer having a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address, wherein said branch target address cache accesses the branch target buffer with at least a portion of a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address; and a filter buffer, coupled to the branch target buffer, that buffers one or more candidate branch target address predictions for possible inclusion in the branch target buffer, said filter buffer associating a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction, wherein said branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon the respective confidence indications of the candidate branch target address predictions.