1. A pipelined multiply-scan apparatus comprising: a first input channel, configured to receive a multiply-scan input signal; a second input channel, configured to receive a null-value input signal; a first left-shift hardware module configured to: receive the multiply-scan input signal at a first left-shift input interface, left-shift the multiply-scan input signal, and output a first left-shift output value at a first left-shift output interface; a first adder hardware module configured to: receive the multiply-scan input signal at a first adder input interface, receive the null-value input signal at a second adder input interface, and output a first adder output value at a first adder output interface; a second left-shift hardware module, configured to: receive the first left-shift output value at a second left-shift input interface, left-shift the first left-shift output value, and output a second left-shift output value at a second left-shift output interface; a second adder hardware module configured to: receive the first left-shift output value at a third adder input interface, receive the first adder output value at a fourth adder input interface, and output a second adder output value at a second adder output interface; and a third adder hardware module configured to: receive the second left-shift output value at a fifth adder input interface, receive the second adder output value at a sixth adder input interface, and output a third adder output value at a third adder output interface, wherein the first adder hardware module is configured to output the first adder output value equal to the value received at the second adder input interface if a first enable input received at the first adder hardware module corresponds to a pass value, and the first adder hardware module is configured to output the first adder output value equal to a sum of the values received at the first and second adder inputs if the first enable input received at the first adder hardware module corresponds to an add value, and wherein the first enable input is based on a first preceding output value at the first adder output interface from an immediately preceding cycle, wherein the second adder hardware module is configured to output the second adder output value equal to the value received at the fourth adder input interface if a second enable input received at the second adder hardware module corresponds to a pass value, and the second adder hardware module is configured to output the second adder output value equal to a sum of the values received at the third and fourth adder inputs if the enable input received at the second adder hardware module corresponds to an add value, and wherein the second enable input is based on a second preceding output value at the second adder output interface from an immediately preceding cycle, and wherein the third adder hardware module is configured to output the third adder output value equal to the value received at the sixth adder input interface if a third enable input received at the third adder hardware module corresponds to a pass value, and the third adder hardware module is configured to output the third adder output value equal to a sum of the values received at the fifth and sixth adder inputs if the enable input received at the third adder hardware module corresponds to an add value, and wherein the third enable input is based on a third preceding output value at the third adder output interface from an immediately preceding cycle.