1. An emulating computer device having a first address bus, a second address bus and a data bus, said emulating computer device comprising: memory means for storage of instruction and data, said memory means having a data bus and an address bus, said data bus being coupled to said data bus of said emulating computer device and said address bus being coupled to said first address bus of said emulating computer device; processing means for processing an emulating instruction, said processing means having a data bus, an address bus and a control line, said data bus being coupled to said data bus of said emulating computer device and said address bus being coupled to said first address bus of said emulating computer device; a cache controller having a control line, a no match line, and an address bus, said control line being coupled to said control line of said processing means and said address bus being coupled to said first address bus of said emulating computer device; a memory transfer controller having a no match line, a first address bus and a second address bus, said no match line being coupled to said no match line of said cache controller and said first and second address buses being coupled to said first and second address buses of said emulating computer device; an instruction memory having an address bus and a data bus, said address bus being coupled to said second address bus of said emulating computer device and said data bus being coupled to said data bus of said emulating computer device; an input register having an input and output, said input being coupled to said data bus of said emulating computer device; a decode register having an input and an output, said input being coupled to said output of said input register; a buffer register having an input and an output, said input being coupled to said output of said input register; a decoder array having an input, a control input, a control output, an output and a steering output, said input being coupled to said output of said decode register; a control logic circuit having an input and an output, said input being coupled to said control output of said decoder array and said output being coupled to said control input of said decoder array; a bit steering circuit having a first input, a steering input, a second input, a third input and an output, said first input being coupled to said output of said decoder array, said steering input being coupled to said steering output of said decoder array, said second input being coupled to said output of said decode register and said third input being coupled to said output of said buffer register; an output register having an input and an output, said input being coupled to said output of said bit steering circuit; and a cache random access memory having a first data bus, a second data bus, a first address bus and a second address bus, said first data bus being coupled to said data bus of said emulating computer device, said first address bus being coupled to said first address bus of said emulating computer device, said second data bus being coupled to said output of said output register and said second address bus being coupled to said second address bus of said emulating computer device.