1. An apparatus comprising: a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first memory die includes circuitry associated with operation of the multiple memory cells; a second memory die comprising a second memory core; and a periphery die coupled to the first memory die and to the second memory die, wherein the periphery die comprises: periphery circuitry corresponding to the first 3D memory core and periphery circuitry corresponding to the second memory core; a first error correction coding (ECC) engine; a second ECC engine; and control circuitry configured to perform a first ECC operation at the first ECC engine substantially concurrently with performing a second ECC operation at the second ECC engine, and wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory core and a second memory operation at the second memory core.