1. An emulator comprising: a plurality of design field-programmable gate arrays (FPGAs) configured to collectively emulate a design under test (DUT) and produce a first signal of the DUT, the DUT including a first section; and a system FPGA comprising: a plurality of computational blocks, at least one of the plurality of computational blocks configured to emulate a second section of the DUT and produce a second signal of the DUT based on the first signal, the second section substantially similar to the first section, and a logic analyzer configured to perform logic analysis based on the second signal.