1. A microprocessor that is operable to decrypt encrypted instruction data into plain text instruction data and securely execute the same, preventing observation of the encrypted instruction data outside the microprocessor, the microprocessor comprising: a master key register file comprising a plurality of master keys; selection logic circuitry that selects a combination of at least two of the plurality of master keys; key expansion circuitry that performs at least one mathematical operation on the selected master keys to generate the decryption key; instruction decryption circuitry that performs at least one mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data; and a fetch unit that fetches chunks of encrypted instruction data, wherein each chunk comprises a plurality of fetch quanta of encrypted instruction data, and each fetch quantum comprises a plurality of instruction data bytes, wherein each master key is at least as long as a fetch quantum of the fetch unit.