1. A method for decreasing the latency between an instruction cache and a pipeline processor having a plurality of parallel execution stages, each execution stage having a decode stage and an instruction queue for sequentially processing instructions being processed by said processor, comprising: determining whether said decode stage and said instruction queue contain invalid data; and inserting a group of instructions from said instruction cache through a parallel path into said decode stage while simultaneously inserting the same group of instructions through said parallel path into said instruction queue when said decode stage and said instruction queue contain invalid data.