1. A processor comprising: a register set to store a first operand exponent value, a second operand exponent value and a third operand exponent value; and an underflow prediction circuit comprising: a first logic to determine if the first operand exponent value subtracted from a first value comprising a mathematical equation including a second operand exponent value and a third operand exponent value is less than a first predefined value; a second logic to determine if the first operand exponent value is greater than or equal to a second predefined value; a third logic to assert an output signal indicative of an absence of an underflow condition associated with a floating-point value responsive to the first logic determining that first operand exponent value subtracted from the first value comprising the mathematical equation is less than the first predefined value and the second logic determining that the first operand exponent value is greater than or equal to the second predefined value; a fourth logic to determine if the first operand exponent value subtracted from the first value is no less than a third predefined value and no greater than a fourth predefined value; a fifth logic to determine if that the first value is greater than or equal to a fifth predefined value; and a sixth logic to asset the output signal indicative of the absence of an underflow condition associated with the floating-point value responsive to: the third logic not to assert the output signal indicative of the absence of an underflow condition; the fourth logic determining that the first operand exponent value subtracted from the first value is no less than the third predefined value and no greater than the fourth predefined value; and the fifth logic determining that the first value is greater than or equal to the fifth predefined value.