1. An apparatus, comprising: a plurality of memory die adjacent to and coupled to one another; a logic die coupled to the plurality of memory die, wherein at least one memory die comprises a memory device, the memory device comprising: an array of memory cells; sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component; and timing circuitry coupled to the array and sensing circuitry, the timing circuitry configured to control timing of operations for the sensing circuitry; and wherein the logic die comprises: control logic coupled to the timing circuitry, the control logic configured to execute instructions to cause the sensing circuitry to perform the operations; and switching circuitry configured to: route memory array requests received from a host; and route processing in memory (PIM) requests received from the host to perform a logical operation using the sensing circuitry.