1. A system for pipelined simulated annealing on an FPGA comprising: a Memory Multiplexer; a Main controller communicatively coupled to said Memory Multiplexer; a Copy processor communicatively coupled to said Memory Multiplexer and to said Main controller; an Alter processor communicatively coupled to said Memory Multiplexer and to said Main controller; an Evaluate processor communicatively coupled to said Memory Multiplexer and to said Main controller; an Accept processor communicatively coupled to said Memory Multiplexer and to said Main controller; a plurality of Memory modules communicatively coupled to said Memory Multiplexer; an Adjust Temperature processor communicatively coupled to said Accept processor and to said Main controller; wherein said processors are configured to compute a performance score of an Initial solution, adjust the temperature, compute a new performance score and evaluate said new performance score against previous said performance score.