1. An apparatus for acquiring data of fast fail memory, comprising: a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated corresponding thereto from the pattern generator to a failure analyzer; and the failure analyzer for analyzing the DUT data and the pattern generated corresponding to the DUT data, which are received from the data transmitter, thus producing failure analysis information.