1. A computer-implemented process, the process comprising: receiving, into memory, computer program code including references to one or more libraries; accessing, with a computer processor, information about available hardware libraries; determining, with a computer processor, whether the references in the computer program code can be implemented using one or more of the available hardware libraries; generating a profile of the computer program code to predict functionality suited for execution on a field programmable gate array (FPGA) based at least in part upon the references to one or more libraries and information about the available hardware libraries including code size, power consumption data, resource data, and information about the frequency of calls made to the available hardware libraries; receiving information from a scheduler including each of the computer program code performance requirements, priority of the computer program code execution, availability of a corresponding software library if a particular functional unit is not available within the FPGA, and context switching costs, and receiving data about an execution pattern from a prior execution of the computer program code; and based at least in part upon the generated profile, the information received from the scheduler and the received data, selecting and loading one or more of the one or more of the available hardware libraries into the FPGA for access by an application using the computer program code.