1. An instruction responsive three input arithmetic logic unit comprising: an AND gate having a first input receiving a first multibit input signal, a second input and an output forming the bit wise AND of signals received at said first and second inputs; a first two input Boolean function generator having a first input receiving a second multibit input signal, a second input receiving a third multibit input signal and an output connected to said second input of said AND gate, said output forming a first Boolean combination of signals received at said first and second inputs, said first Boolean combination selected by a current instruction; a second two input Boolean function generator having a first input receiving the second multibit input signal, a second input receiving the third multibit input signal and an output forming a second Boolean combination of signals received at said first and second inputs, said second Boolean combination selected by said current instruction; and an adder having a first input connected to said output of said AND gate, a second input connected to said output of said second two input Boolean function generator and an output forming the addition of signals received at said first and second inputs.