1. In a computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, a computer-implemented method for servicing a data cache miss in parallel with normal instruction execution to thereby reduce or avoid the penalty associated with a data cache miss, comprising the steps of: placing a first instruction that requires a load to a read only register within an instruction stream, wherein said first instruction provides a hint to the data cache memory to prefetch a cache line from a main memory into the data cache memory; decoding and executing said first instruction, wherein said load to said read only register does not alter the contents of said read only register; and processing, substantially simultaneously with said prefetch of said cache line, further instructions that follow said first instruction; whereby said first instruction is placed within said instruction stream such that said cache line is prefetched from said main memory early enough so that subsequent accesses to this data will not result in a data cache miss.