1. A system, comprising: a plurality of input stages, each configured to successively provide bits of a respective code word, starting with a most-significant bit thereof; a plurality of one-shots connected to respective ones of the input stages to successively receive the bits of the respective code words, wherein each one-shot is configured to successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then to provide a second, different bit value; an enable circuit connected to the outputs of the one-shots and configured to provide the enable signal if at least one of the one-shots is providing the first bit value; a controller programmed to sequence through a selected number of bits; and a plurality of successive-approximation analog-to-digital converters (ADCs), wherein each input stage successively receives the bits from a respective one of the ADCs and each ADC comprises: an input terminal; a register connected to the respective input stage to successively provide the bits; a programmable reference that provides a reference electrical signal in response to the value in the register; and a comparator configured to compare an electrical signal at the input terminal to the reference electrical signal and adjust a bit in the register indicated by the controller, wherein the comparator comprises: a domain-wall neuron connected to the input terminal and the programmable reference; and a CMOS latch configured to compare an output of the domain-wall neuron with a selected threshold and store a bit value according to the result of the comparison.