1. A processor, comprising: a storage unit that stores an instruction; a program counter that holds a program counter value specifying an instruction to be executed next; an instruction extension information register that includes a first area and a second area; an instruction decoding unit that decodes a first prefix instruction including a first extension information extending an instruction immediately following the first prefix instruction and writes the first extension information to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including a first extension information extending an instruction that is the first sequential instruction immediately following the second prefix instruction and a second extension information extending an instruction that is the second sequential instruction immediately following the second prefix instruction and writes the first and second extension information of the second prefix instruction to the first and the second area, respectively, when the second prefix instruction is executed; an instruction packing unit that reads out instructions from the storage unit based on the program counter value, and that generates a packed instruction including information from at least one of the first prefix instruction and the second prefix instruction and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes at least one of the first prefix instruction and the second prefix instruction; an instruction execution unit that executes the packed instruction; a register updating unit that increases the program counter value by a number corresponding to a length of two instructions when the instruction execution unit completes the execution of the packed instruction; and an instruction predecoding unit that outputs up to an instruction plus a predetermined number of instructions to the decoding unit when one first prefix instruction is among a plurality of instructions read out from the storage unit, and that outputs up to two instructions plus a predetermined number of instructions to the decoding unit when two or more first prefix instructions or one or more second prefix instructions are among the plurality of instructions read out from the storage unit.