1. In a data processor for processing N bit data words whose bit positions are respectively designated (N-1) through zero starting with the leftmost bit position of a data word and having control means for specifying: a value L defining the number of adjacent bits in a portion of an N bit input data word, a value P1 defining the bit position of said input data word which contains the leftmost one of said L adjacent bits, a value P2 defining a bit position in an N bit output data word, and an option code defining at least one of a plurality of logical operations; a combinational logic arrangement comprising: first combinational logic means connected to and controlled by said control means for selectively performing the logical operations defined by said option code to produce an N bit logical result data word, and second combinational logic means connected to receive said logical result data word from said first logic means and connected to and controlled by said control means for inserting the respective L bits in bit positions P1 through (P1-L+1) of said input data word into bit positions P2 through (P2-L+1) of said logical result data word to produce said output data word, whereby the output word represents the logical result data word as masked by selected bits of the input data word.