1. An apparatus for providing a memory assist function, the apparatus comprising: at least one processing element (PE); at least one memory directly associated with the at least one PE; an instruction decode function which decodes a memory hardware assist instruction that is an instruction in the instruction set architecture of the at least one processing element and causes control signals to he generated to initiate the memory hardware assist function; and a memory hardware assist unit having a memory interface to the at least one memory and a PE interface to the at least one PE, the memory hardware assist unit, after being initiated, iteratively fetches source operands over the memory interface from the at least one memory in parallel with PE operations in the at least one PE and generates at least one result operand that is selectively stored over the memory interface in the at least one memory.