1. A method, in a computing device, of optimizing latch placement in a macro based chip design, comprising: generating a tree graph data structure of the macro based chip design; determining a critical path in the tree graph data structure, wherein the critical path is between a root node of the tree graph data structure and a critical node of the tree graph data structure that does not have a latch placement requirement met; and performing latch placement on the nodes of the critical path in accordance with the latch placement requirement of the critical node and any latch placement requirements of intermediate nodes in the critical path.