1. An apparatus for dispatching instructions to an execution pipeline in a multithreading microprocessor that concurrently executes N threads each having a priority, the priority being one of P priorities, the apparatus comprising: P round-robin vectors, corresponding to the P priorities, each having N bits corresponding to the N threads, each being a 1-bit left-rotated and subsequently sign-extended version of an N-bit input vector, said input vector having a single bit true corresponding to a last one of the N threads selected for dispatching at a corresponding one of the P priorities; N P-input muxes, each coupled to receive a corresponding one of said N bits of each of said P round-robin vectors, each configured to select for output one of said P inputs specified by the corresponding thread priority; and selection logic, coupled to receive an instruction from each of the N threads and to select for dispatching to the execution pipeline one of said N instructions corresponding to one of the N threads having a dispatch value greater than or equal to any of the N threads left thereof in said N-bit input vectors; wherein said dispatch value of each of the N threads comprises a least-significant bit equal to said corresponding P-input mux output, a most-significant bit that is true if said corresponding instruction is dispatchable, and middle bits comprising the priority of the thread.