1. An apparatus, comprising: instruction execution logic circuitry having: input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions; and, masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector routing element circuitry, said masking layer circuitry designed to mask at three different levels of granularity that correspond to said three available bit widths.