1. A method of managing a coherent memory between a central processing unit (CPU) and an accelerated processing device (APD), the APD performing the method comprising: monitoring a flag register to determine whether data stored in a coherent memory is available for processing, wherein the flag register notifies the APD that data is available for processing in the coherent memory; acquiring an address pointer for the data in the coherent memory from an address processing device in response to determining data stored in the coherent memory is available for processing; fencing outstanding read requests associated with the data stored in the coherent memory in response to the determining that data stored in the coherent memory is available for processing by the APD; processing the data stored in the coherent memory using the APD; executing a store release instruction for the data stored in the coherent memory that has been processed by the APD; flushing processed data that is stored in an APD cache and storing the flushed data to the coherent memory; and setting a synchronization variable by the APD to confirm that the data stored in the coherent memory is valid, wherein the synchronization variable is associated with the flag register.