1. A semiconductor memory device, comprising: a memory cell array configured to include a plurality of memory strings; a peripheral circuit configured to perform a program operation on the plurality of memory strings; and a control logic configured to control the peripheral circuit to perform the program operation, wherein the control logic controls the peripheral circuit to adjust potential levels of program permission voltages to be applied to bit lines of respective memory strings according to arrangement positions of the memory strings, wherein the program permission voltage applied to a memory string adjacent in a first direction among the plurality of memory strings has a negative potential level.