1. A processor, comprising: an execution pipeline having one or more execution units to execution the instructions; and a branch prediction unit coupled to the execution units, the branch prediction unit including a branch history table to store prior branch outcomes, a branch predictor, in response to a conditional branch instruction, to predict a branch target address of the conditional branch instruction based on the branch history table, and address match logic to compare the predicted branch target address with an address of a next instruction executed immediately following the conditional branch instruction and to cause the execution pipeline to be flushed if the predicted branch target address does not match the address of the next instruction to be executed.