1. An apparatus comprising: a processing core configured to execute a plurality of threads; and a transactional memory system for executing atomic memory transactions, wherein the processing core is configured to perform operations including: starting, by a first thread, a task by starting to execute a plurality of task instructions; initiating, by the first thread, an atomic memory transaction using the transactional memory system, including: specifying, to the transactional memory system, at least a first memory address for the atomic memory transaction; and temporarily ceasing the task by not proceeding to execute the task instructions; receiving, by the first thread, a signal as a consequence of a second thread accessing the first memory address specified for the atomic memory transaction; and as a consequence of receiving the signal, resuming the task, by the first thread, and continuing to execute the task instructions.