1. An apparatus using an X-canceling multiple-input signature register (MISR) for compacting a test response containing unknowns (X's) in one or more scan cells in a scan-based integrated circuit; the scan cells being connected in series to form M internal scan chains; the X-canceling MISR including one or more selected combination selection bits and being arranged to receive the test response appearing at the scan chain outputs of said M internal scan chains to generate the non-X signature at N external scan outputs for analysis on a tester, where M>N, said apparatus comprising: (a) an M-bit MISR for receiving the test response appearing at the scan chain outputs of said M internal scan chains prior to receiving said test response in said scan-based integrated circuit to generate a signature after a predetermined number of clock cycles; and (b) a selective XOR network connected to said M-bit MISR for canceling out all unknowns (X's) which appear at the scan chain outputs of said M internal scan chains to generate a non-X signature at said N external scan outputs, wherein said XOR network is arranged to determine the values of said selected combination selection bits of the MISR to generate said non-X signature after said predetermined number of clock cycles, by performing a Gauss-Jordan elimination through symbolic simulation.