1. In a multi-processor test system having boundary scan functionality, each processor capable of a streaming data mode of operation, each processor comprising: a test control unit; a register unit including; a 1-bit bypass register for use in a bypass node, and; an n-bit register for use in data exchange mode; wherein the test control unit is responsive to a first instruction for placing the processor in a bypass mode; wherein, in the bypass mode, the test control unit is responsive to logic “1” in the bypass register, the logic “1” in the bypass register maintaining the processor in the bypass mode; and wherein, in the bypass mode, the test control apparatus is responsive to a logic “0” in the bypass register, the logic “0” in the bypass register causing the processor to enter the streaming data mode of operation.