1. A processor comprising: a front end including a fetch/decode unit to prefetch instructions for a first physical thread that includes a set of a first architecture state of the processor and for a second physical thread that includes a set of a second architecture state of the processor, the fetch/decode unit including a first sequencer corresponding to the first physical thread and a second sequencer corresponding to the second physical thread, wherein the processor is a simultaneous multithreading (SMT) processor; the first physical thread to support two or more switch-on-event software threads; the second physical thread to support the two or more switch-on-event software threads; and a thread translation table to maintain mapping information for the first physical thread, the second physical thread, and the software threads, and including a plurality of entries each to store a physical thread identifier associated with one of the physical threads and a virtual thread identifier associated with one of the switch-on-event software threads, wherein the thread translation table is accessed by a physical thread identifier from a first structure of the processor and the corresponding virtual thread identifier is to be output to a second structure that uses the virtual thread identifier to process entries within the second structure, wherein the mapping information is to indicate one of the switch-on-event software threads as an active thread that is executing on the first physical thread and another one of the switch-on-event software threads as an active thread that is executing on the second physical thread.