1. A hybrid survivor memory architecture for a reduced complexity sequence estimator for a channel having a channel memory of length L, comprising: a register exchange architecture (REA) for storing the survivors corresponding to the L past decoding cycles; and a trace-back architecture (TBA) for storing survivors corresponding to later decoding cycles, wherein symbols outputted from said register exchange architecture (REA), before being moved from said register exchange architecture to said trace-back architecture (TBA), are mapped to information bits.