1. A field programmable logic device comprising: a plurality of sources each providing an output; a selector unit to separately select for each part of its output the corresponding part of the output from one of said plurality of sources; and a programmable logic datapath coupled to said selector unit including, a rearrangement circuit coupled to receive said output of said selector unit; a selective field negation circuit coupled to said rearrangement circuit; and a plurality of reduction networks each coupled to receive the outputs of said selective field negation circuit and each including a series of logic levels coupled together to selectively reduce those outputs using XOR, OR, and selective negation circuitry down to one bit.