1. A computerized system for quantitatively identifying electrostatic discharge (ESD) and latch-up sensitivities in an integrated circuit (IC) design, comprising: a pre-processor operable to collect information from a netlist, an elements model, a file of circuit safe operating conditions, and a list of stress simulation conditions, to express the combined program in a specific format modified for ESD and latch-up simulations; a simulator input data file coupled to said pre-processor, operable to store said modified program, including statements used for identifying ESD and latch-up failures, as an ESD netlist expressed in a specific format; a simulator coupled to said simulator input file, operable to apply a simulated, quantified ESD stress event to said modified program of said IC design, and to process said event through said design elements; a post-processor coupled to said simulation program, operable to quantitatively analyze the sensitivities of said design elements relative to ESD and latch-up, to judge critical stress values and to record any element failures; and an output data generator coupled to said post-processor, operable to create a report, expressed in a specific format, of said sensitivities including an element list and a location list of said element failures.