1. An embedded memory having compressed redundancy information on an integrated circuit, comprising: a memory cell array; replacement cells; mapping logic coupled to the memory cell array and the replacement cells for electronically substituting the replacement cells for defective cells at at least one location in the memory cell array; programmable links for storing compressed redundancy information; and decoding logic for decompressing the compressed redundancy information stored in the programmable links and provide decompressed redundancy information for controlling the mapping logic.