1. A processor comprising: a decode unit to decode a plurality of control transfer instructions, the plurality of control transfer instructions including a first control transfer instruction and a second control transfer instruction, the decode unit including a control transfer termination (CTT) instruction tracking state machine, wherein CTT instruction tracking is to be suppressed in response to decoding a first instance of the first control transfer instruction having a target instruction in code not using the plurality of control transfer instructions; an execution unit to execute the plurality of control transfer instructions; and a retirement unit to retire the first control transfer instruction, wherein the retirement unit is to raise a fault in response to a determination that a next instruction to be retired after the first control transfer instruction is not the second control transfer instruction, unless CTT instruction tracking is suppressed.