1. A microprocessor comprising: a memory interface to load or store data envelopes from or to a memory, each data envelope having a first length; a plurality of registers; a buffer; and control logic configured to implement a plurality of instructions to load or store a stream of data elements via a succession of the data envelopes at the memory interface, each data element having a second length in one of the plurality of registers shorter than the first length of the data envelopes at the memory interface, the first length not being an integer multiple of the second length, the plurality of instructions comprising: an initialization instruction configured to initialize the buffer in a load operation in which an initial envelope is loaded into the buffer, the initial envelope comprising a first byte of a first data element of the stream of data elements, or in a store operation in which the buffer is cleared; and a data merge instruction configured to extract or incorporate a respective data element from or into the stream of data elements in the load operation or the store operation, respectively, wherein the data merge instruction is configured to merge current contents of the buffer and the memory interface into a first register of the plurality of registers in the load operation or is configured to merge current contents of the buffer and a second register of the plurality of registers into the memory interface in the store operation, and is further configured to move at least a remainder of the current contents of either the memory interface or the second register into the buffer for use in a successive invocation of the data merge instruction.