1. A processor comprising: a plurality of registers; and an execution core coupled to the plurality of registers, wherein the execution core, responsive to a first instruction, is configured to store a state of the plurality of registers to a memory region specified by the first instruction, and wherein the plurality of registers include one or more registers storing a floating point instruction pointer and a code segment selector, and wherein the execution core, responsive to an operand size of the first instruction being a first operand size, is configured to store the floating point instruction pointer and the code segment selector in a first storage location of the memory region, and wherein the execution core, responsive to the operand size of the first instruction being a second operand size, is configured to store only the floating point instruction pointer in the first storage location.