1. A multi-threaded processor for executing multiple threads comprising: a first shared state structure including a first group of control registers configured to hold control information to be shared by a first private thread and a second private thread, and one or more registers accessible to a user-level instruction, wherein the one or more registers is user-configured using an application programmable bit-vector to select said one or more registers to provide bidirectional read/write communication between the first private thread and the second private thread; a first private state structure including instruction pointer logic configured to hold an instruction pointer for the first private thread and general purpose registers configured to hold general purpose information for the first private thread; a second private state structure including instruction pointer logic configured to hold an instruction pointer for the second private thread and general purpose registers configured to hold general purpose information for the second private thread; thread logic configured to create the second private thread in response to a fork instruction encountered during execution of the first private thread, wherein the fork instruction is part of an Instruction Set Architecture available to users.