1. A computer-implemented method for compiling high-level software programs into instruction level parallel code, comprising: generating a code graph, line by line, wherein a line, p, comprises one or more of nodes that are executed within one clock unit, a node comprising one or more operations; in a first analysis, analyzing a line, by a computer processor, for nodes that may be executed simultaneously, the analysis determining a; content PAR{ }, each term in PAR{ } is process simultaneously; in a second analysis, analyzing, by the processor, a line for nodes that may be sequentially executable from a previous line to yield a content VEC{ }, each term in VEC{ } is processed in succession; and determining the configuration of a next line depending on the first and second analyses, wherein a value of PAR(p), PAR(p) comprising the number of nodes that may be executed simultaneously at a certain stage (p), being less than (p) in a given line determines that the number of nodes in the next line is (p); wherein if (p)is no less than PAR(p), determining that the number of nodes to be executed in the next line the number of node defined by PAR{ }; and wherein a value of VEC being less than 1 determines that a node in the next line not be successive.