1. Data processing apparatus comprising: a plurality of vector registers; a plurality of vector functional units; program instruction initiation means responsive to a first instruction for initiating processing of at least one vector operand of said first instruction in one of said plurality of vector functional units, and said program instruction initiation means responsive to a second instruction for initiating the processing of at least another vector operand of said second instruction in said one vector functional unit dependent upon completion of the first instruction; a first vector control register (VVC) register, corresponding to a first vector register containing said other vector operand, for storing the identity of a second vector register containing said one vector operand; a second VVC register, corresponding to said second vector register for maintaining a busy or a non-busy status of the second vector register; means operating with the second VVC register for releasing the second vector register to a non-busy status when the first instruction is completed; and logic means coupled to the first VVC register and responsive to said non-busy status of said second vector register for beginning processing of the other vector operand in said one functional unit.