1. An input buffer comprising a buffer circuit having an input node and an output node, the buffer circuit being configured to respond to an input signal applied to the input node by generating an output signal at the output node transitioning from a first logic state to a second logic state responsive to the magnitude of the input signal transitioning from one logic state to another, the buffer circuit further being configured to apply a feedback signal corresponding to the output signal to a feedback node of the buffer circuit to strengthen the transition of the output signal during at least some of the time the output signal is transitioning from the first logic state to the second logic state and to discontinue applying the feedback signal to the feedback node at some time between when the output signal has started to transition from the first logic state to the second logic state and when the output signal subsequently transitions to another logic state.