1. A branch processing method for controlling a pipeline operation of a processor, comprising: determining an instruction type of an instruction written into a cache memory and recording the instruction type; when the instruction is a branch instruction, calculating a branch target instruction address of the branch instruction and recording target address information corresponding to the branch target instruction address, wherein the target address information corresponds to one instruction segment containing at least the branch target instruction; and when the branch target instruction is not stored in the cache memory, based on the branch target instruction address, filling the instruction segment containing at least the branch target instruction into the position corresponding to the target address information in the cache memory, such that, before a CPU core executes the branch instruction, a next instruction following the branch instruction in a program sequence and the branch target instruction of the branch instruction are stored in the cache memory.