1. An apparatus comprising: a first circuit configured to receive a plurality of input signals and present one of said plurality of input signals as a data signal in response to a control signal; a second circuit configured to (i) generate said control signal and (ii) generate a trace data stream in response to said data signal; and a third circuit comprising one or more unallocated diffused memory resources and configured to (i) receive and store said trace data stream and (ii) read and present said stored trace data stream, in response to one or more commands.