1. An apparatus for efficiently determining the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set architecture, the apparatus comprising: combinatorial logic associated with each instruction byte of the stream, each configured to receive the associated instruction byte and the next instruction byte of the stream, and configured to generate in response thereto a first length, a second length, and a select control; a multiplexor, associated with each of the combinatorial logic, configured to select and output one of the following inputs based on the select control received from the combinatorial logic: a zero input and the second length received from the combinatorial logic associated with each of the next three instruction bytes of the stream; and an adder, associated with each of the combinatorial logic and multiplexor, configured to add the first length received from the combinatorial logic and the output received from the multiplexor to generate the length of the instruction.