1. An electronic device comprising: a processing unit; a multi-level cell (MLC) flash memory comprising a plurality of multi-level memory cells comprising a plurality of MLC states, the MLC flash memory comprising a critical portion; and a memory controller interfacing the MLC flash with the processing unit, the memory controller responsive to read instructions from the processing unit to read a binary value from an MLC state stored in a given multi-level memory cell in the critical portion.