1. An apparatus, comprising: a first pre-charge line; a second pre-charge line; a first p-channel transistor including a gate coupled to the first pre-charge line, and a first terminal coupled to a first sense line and a second terminal coupled to a first voltage supply node; a first n-channel transistor including a gate coupled to a first control line and a terminal coupled to the first sense line; a first inverter including an input coupled to the first sense line; a second p-channel transistor including a gate coupled to the second pre-charge line, and a first terminal coupled to a second sense line and a second terminal coupled to a second voltage supply node; a second n-channel transistor including a gate coupled to a second control line, a first terminal coupled to an output of the first inverter, and a second terminal coupled to the second sense line; and a second inverter including an input coupled to the second sense line.