1. A method of digital computing, comprising: (a) replicating all target addresses and all branch conditions contained within all branch parcels of an instruction having multiple parcels, some parcels being the branch parcels and some parcels being operational parcels, all parcels capable of independent execution in a processor; (b) loading the instruction having multiple parcels with the replicated target addresses and branch conditions into an instruction cache; (c) selecting the instruction for execution; (d) executing the operational parcels in a plurality of execution units of the processor, each execution unit dedicated to a respective each one of the parcels; (e) simultaneously evaluating all branch conditions of all branch parcels of the instruction to determine a control flow branch taken; (f) simultaneously decoding all target addresses of the instruction with decode logic circuits; (g) correlating one each of the evaluated branch conditions to one each of the decoded target addresses, and to the execution results of the operational parcels, and, as a result, (h) selecting the control flow branch taken for execution; (i) storing the execution results of the control flow branch taken; and (j) selecting a next instruction of the control flow branch taken for execution.