1. A random testing device for logic circuits, particularly microprocessors, comprising: a central unit (1) having an input and an output; a reference microprocessor (MR) and a test microprocessor (MT) to be tested, each said microprocessor having a data (d), an address (a) and a monitoring output (c); a random sequence generator (3) for generating random sequences of instructions and orders, each applied in parallel to both said reference microprocessor and to said test microprocessor; and a comparator (4) having first and second inputs, each of which is connected to one of said data, address and monitoring outputs of each said microprocessor, and an output connected to the input of said central unit; said random sequence generator (3) comprising: (1) a shift register (5) looped as a sequence generator of maximum period by an exclusive OR circuit (6) having inputs, the cells of said shift register corresponding to certain bits defined by a known mathematical property and being connected to said inputs of said exclusive OR circuit (6); (2) a vector sequence generator having an input connected with an output of said shift register for receiving therefrom equiprobable vectors of twenty-eight (28) bits issuing from said shift register, said vector sequence generator comprising for instructions: (a) a first memory (8) for storing data, (b) a second memory (9) for storing operation codes, and (c) a third memory (10) for storing the number of cycles corresponding to the various operation codes; and said vector sequence generator comprising for orders: (d) a fourth memory (11) for storing the types of orders, and (e) a fifth memory (12) for storing the number of cycles corresponding to the various respective orders, means including said shift register (5) for allowing a pseudo-random generation of equiprobable vectors for application to said vector sequence generator; said means including said first memory (8) for storing data, said second memory (9) for storing operation codes, and said third memory (10) for storing the number of cycles corresponding to the various operation codes, to provide instructions; first and second switches (16, 21) for transferring data supplied thereto to said two microprocessors, and first and second busses (14, 15) for connecting the outputs of said first and second memories (8, 9) respectively to said first switch (16); a first bus (A) for data to connect both said reference microprocessor (MR) and said test microprocessor (MT) in parallel and with the outputs of said first switch (16), and a second or order bus (B) for orders connecting both said reference microprocessor (MR) and said test microprocessor (MT) in parallel and with the outputs of said second switch (21); first and second counters (17,20), and a third bus (19) having its input connected with said fifth memory (12) containing the number of cycles corresponding to the respective orders and the output connecting said first and second counters (17, 20) in parallel, a fourth bus (26) connecting said third memory (10) with said first counter (17), and a link (18) connecting said first counter (17) and said first switch (16) for controlling said first switch (16); and a fifth bus connecting said second switch (21) to the output of said fourth memory (11), the output of which is connected to said second or order bus (B); the output of said second counter (20) and said fifth memory (12) being connected to said first counter (17) and through said second counter (20) to said second switch (21) for controlling said second switch (21) to maintain an order for a period of time sufficient for correct execution thereof, and the linking to said first counter makes it possible to send an operation code at the moment when said microprocessors are expecting it after execution of an order; said memories (8, 9, 10, 11, 12) being loaded by subdividing the total field of each said memory into a certain number of areas of different ranges, depending on the probabilities that it is desired to obtain at the output.