1. A programmable logic device, comprising: a sense amp (10); a programmable cells (20a) connected to the sense amp, having: a) a half latch circuit (30), wherein the output (31) from the half latch circuit is used to program various portions of the programmable logic device; and b) a fuse cell circuit (29), coupled to the half latch circuit, for setting the output of the half latch circuit to a high or low signal level. 2. The programmable logic device of claim 1, wherein said half latch circuit comprises: a power rail (Vcc 37); and a first (32) and second (34) P-channel transistor, each having the source electrically coupled to the power rail, and the drains coupled together. 3. The programmable logic device of claim 2, wherein the half latch circuit further comprises: an inverter having electrical inputs from the drains of the first and second P-channel transistors, and having the output electrically coupled to the gate of the second P-channel transistor, the output of the inverter is the output of the half latch circuit for setting a state for various portions of the programmable logic device. 4. The programmable logic device of claim 3, A programmable logic device, comprising: a sense amp; a programmable cell (20a) connected to the sense amp having: a) a half latch circuit (30), wherein the output (31) from the half latch circuit is used to program various portions of the programmable logic device, wherein the said half latch circuit further comprises: a power rail (V.sub.cc 37); a first (32) and second (34) P-channel transistor, each having the source electrically coupled to the power rail, and the drains coupled together; an inverter having electrical inputs from the drains of the first and second P-channel transistors, and having the output electrically coupled to the gate of the second P-channel transistor, the output of the inverter is the output of the half latch circuit for setting a state for various portions of the programmable logic device; and a third P-channel transistor (38) having its source electrically coupled to the drains of the first and second P-channel transistors ; and b) a fuse cell circuit (29), coupled to the half latch circuit, for setting the output of the half latch circuit to a high or low signal level. 5. The programmable logic device of claim 4, wherein said fuse cell circuit comprises: a first N-channel transistor (42) having the drain electrically coupled to the source of the third P-channel transistor; and an anti-fuse cell (44) having: a) an input coupled to a digit line (11) which is coupled to the sense amp; and b) an output electrically coupled to the source of the first N-channel transistor (42). 6. The programmable logic device of claim 5, further comprising: a second N-channel transistor (40) having the source coupled to the first N-channel transistor (42) and the third P-channel transistor (38), and its drain coupled to ground. 7. A PLD programming circuit, comprising: an output line (31); fuse circuit means (29), electrically coupled to the output line, having a low state for pulling the voltage of the first node down, and having a high state for maintaining the voltage on the first node; and latching circuit means (30), coupled to the line, having a first mode for outputting a high signal to the output line while the fuse circuit means is in a low state, and a second mode for outputting a low signal to the output line while the fuse circuit means is in a high state. 8. The PLD of claim 7, A PLD programming circuit, comprising: a first node (35); an output line (31) connected to the first node of the PLD programming circuit; fuse circuit means (29), electrically coupled to the output line, having a low state for pulling the voltage of the first node down, and having a high state for maintaining the voltage on the first node, wherein the fuse circuit means comprises: a the first node (35), coupled between the fuse circuit and the half latch circuit; a digit line (11); and an anti-fuse (44), coupled between the digit line and the first node (35), for enabling the high state on the first node when the anti-fuse is unprogrammed, and enabling the low state on the first node when the anti-fuse is programmed ; and latching circuit means (30) coupled to the output line of the PLD programming circuit, having a first mode for outputting a high signal to the output line while the fuse circuit means is in a low state, and a second mode for outputting a low signal to the output line of the PLD programming circuit while the fuse circuit means is in a high state. 9. The PLD of claim 6 , further comprising: a protection circuit (42), coupled between the first node and the anti-fuse, for inhibiting the anti-fuse from breaking down over time. 10. The PLD of claim 9, further comprising: a program transistor (40) for selectively enabling current through the anti-fuse during programming of the anti-fuse. 11. The programmable logic device of claims 1 , wherein the sense amp uses no power during operating periods of the programmable logic device. 12. The PLD programming circuit of claim 7 , further comprising: a) a programmable cell including the fuse circuit means and the latching circuit means; b) a sense amp electrically coupled to the programmable cell; and c) the sense amp using no power during operating periods of the PLD.