1. A circuit arrangement comprising: a tester that includes a programmable test vector generator for generating test vectors; and an integrated circuit that includes logic circuitry to be tested using the test vectors, a test control block to control testing of the logic circuitry, and a test response and analysis unit configured and arranged to receive test results from the logic circuitry in response to the test vectors, to produce a compact representation of said test results, and to output said compact representation to the tester.