1. A reconfigurable circuit comprising: circuit blocks arranged with a matrix of A rows and B columns, each of the circuit blocks comprising: M row conductive lines; N column conductive lines crossing the row conductive lines; output inverters each having input and output terminals, the input terminal of each output inverter connected to corresponding one of the row conductive lines; input inverters each having input and output terminals, the output terminal of each input inverter connected to corresponding one of the column conductive lines; and resistance change elements between the row conductive lines and the column conductive lines, each of the resistance change elements including a first terminal and a second terminal, the first terminal being connected to corresponding one of the row conductive lines, the second terminal being connected to corresponding one of the column conductive lines, the resistance change element between the m th -row conductive line and the n th -column conductive line in the circuit block located at the a th -row and the b th -column being selected by an address abmn (1≦a≦A, 1≦b≦B, 1≦m≦M, 1≦n≦N); the reconfigurable circuit further comprising: an interconnection connected between the output terminal of the output inverter connected to the row conductive line in one of the circuit blocks and the input terminal of the input inverter connected to the column conductive line in the other one of the circuit blocks; and a row address replacement circuit for replacing address a D b D m D ∀ (1≦a D ≦A, 1≦b D ≦B, 1≦m D ≦M) with address a D b D m S ∀ (1≦m S ≦M) and a column address replacement circuit for replacing address a O b O ∀q D (1≦a O ≦A, 1≦b O ≦B, 1≦q D ≦N) with address a O b O ∀n S (1≦n S ≦N), wherein ∀ stands for an arbitrary number, on condition that the resistance change element selected by address a D b D m D n D is defective, that the output terminal of the output inverter connected to the m Dth -row conductive line in the circuit block located at the a Dth -row and the b Dth -column is connected to the input terminal of the input inverter connected to the q Dth -column conductive line in the circuit block located at the a Oth -row and the b Oth -column, and that the output terminal of the output inverter connected to the m Sth -row conductive line in the circuit block located at the a Dth -row and the b Dth -column is connected to the input terminal of the input inverter connected to the n Sth -column conductive line in the circuit block located at the a Oth -row and the b Oth -column.