1. A memory cell, comprising: two split sub-lithographic charge storage nodes on a semiconductor substrate; two split sub-lithographic first poly gates on the two split sub-lithographic charge storage nodes, wherein the two split sub-lithographic first poly gates are formed by a removal of a portion of a patterned first poly surface between sloping surfaces of two spacers; implanted portions in the semiconductor substrate under the two split sub-lithographic charge storage nodes; a dielectric between the two split sub-lithographic charge storage nodes on the semiconductor substrate, the dielectric comprising a single layer, wherein the two spacers are formed on adjacent side surfaces of the dielectric and on portions of upper surfaces of the patterned first poly surface; a second poly gate between the two split sub-lithographic charge storage nodes; and a third poly gate over the semiconductor substrate.