1. A method comprising: designing an integrated circuit including a plurality of variants, wherein one integrated circuit variant includes a plurality of modular circuits communicatively coupled together and a second integrated circuit variant includes a sub-set of the plurality of modular circuits; laying out the plurality of variants of the integrated circuit for wafer fabrication, wherein the layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant and secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant, and wherein the layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last; fabricating the integrated circuit on a wafer according to the layout up to but not including fabricating the one or more metallization layers to be fabricated last; predicting a demand for each of the integrated circuit variants during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last; selecting one or more of the plurality of variants of the integrated circuit based upon the predicted demand; fabricating the last one or more metallization layers to include a subset of the communicative couplings of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit; and singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit.