1. A method of modification of a semiconductor layout, the layout comprising objects of semiconductor material with corners and edges, the method comprising steps of: receiving ( 61 ) a set of proximities, triggers and design rules, the proximities indicating relations between neighboring edges and/or corners, the triggers defining boundaries for the modification within which boundaries the proximities are valid, the design rules describing physical requirements for the semiconductor layout, generating ( 62 ) a set of constraints, based on the received proximities, triggers and design rules, each constraint in the set of constraints defining a limit within which the semiconductor layout may be modified without changing the proximities, and solving ( 63 ) the set of constraints to obtain a modified semiconductor layout.