1. An information processor comprising: a register file including a plurality of registers; an instruction execution unit utilizing said register file to execute first format instructions as native instructions; and an instruction translation circuit for translating second format instructions into said first format instructions; said information processor having, when a first program described in said second format instructions is executed, a first operation mode in which said first format instructions translated by said instruction translation circuit are executed and a second operation mode in which said first format instructions translated by translation software described in said first format instructions are executed; said information processor comprising a dedicated bus for transferring data between said register file and said instruction translation circuit; said instruction translation circuit including a selection control circuit which selectively outputs plural pieces of internal information onto said dedicated bus in response to execution of instructions by said instruction execution unit to allow to be stored in said register file when the operation mode is switched from said first operation mode to said second operation mode and controls to take in said internal information outputted from said register file onto said dedicated bus in response to execution of instructions by said instruction execution unit when the operation mode is switched from said second operation mode to said first operation mode.