1. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays, comprising: plurality of address latches including a plurality of row address latches for latching a first plurality of bits of individual ones of said plurality of subarray addresses that specify a row address and for latching a second plurality of bits of individual ones of said plurality of subarray addresses that specify a column address, a plurality of data registers, each of said plurality of EEPROM subarrays being coupled to receive data from a corresponding one of said plurality of data registers dedicated thereto, means for storing subarray addresses into selected ones of said plurality of address latches, and for storing data to be written into subarray locations indicated by said subarray addresses, into selected ones of said plurality of data registers in time sequence, one of the selected data registers at a time, wherein said storing means includes means for decoding a third plurality of bits of individual ones of said plurality of subarray addresses to generate a signal to enable the data register coupled to the subarray indicated by said third plurality of bits, and means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches.