1. A method of operating a branch history table (BHT) comprising a plurality of counters in a variable length instruction set processor to execute instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, the method comprising: powering both a first half of the BHT and a second half of the BHT during BHT accesses in the second instruction set execution mode; and powering only the first half of the BHT or only the second half of the BHT during any given BHT access in the first instruction set execution mode.