1. A graphics display system comprising: a. memory circuits for storage of graphics data defining a visual image, the graphics data being formed of pixel codes representing each pixel of the visual image, the pixel codes being arranged in graphics data words and each graphics data word including plural pixels, and the memory circuits for storage of a plurality of program instructions providing for both arithmetic and logic operations and graphics operations on the graphics data, the memory circuits including a multi-bit serial output adapted to be connected to a user viewable display; and b. graphics processor circuits connected to the memory circuits and including: i. a central processing unit that includes a program counter for sequentially addressing the program instructions from the memory circuits, an instruction register for storing each program instruction addressed by the program counter and control circuits connected to and decoding the program instruction stored in the instruction register, the control circuits producing control signals on control bus leads in response to each program instruction stored in the instruction register, the central processing unit being connected to the control bus leads and operating in response to the control signals to perform arithmetic and logic operations on the graphics data, and ii. graphics circuits connected to the control bus leads and operating in conjunction with the central processing unit in response to the control signals to perform graphics operations on the graphics data, and the graphics circuits operating on plural pixels in parallel.