1. A processor comprising: a replay system to replay instructions which have not executed properly; a first processing circuit coupled to the replay system to process instructions including any replayed instructions; a second processing circuit to perform additional processing on an instruction, the second processing circuit having an ability to detect one or more faults occurring therein; and a synchronization circuit coupled between the first processing circuit and the second processing circuit to synchronize faults occurring in the second processing circuit to matching instruction entries in the first processing circuit.