1. A multiprocessor system, comprising: an interface to a background memory; a plurality of processing elements, each comprising a processor core and a cache circuit, coupled between the processor core and the interface for caching background memory data accessed by a program of the processor core; and a write back monitor circuit configured to buffer write addresses used for writing data by at least part of the processor cores, the processor core of at least one of the processing elements being configured to support commands from the program to read write back addresses from the write back monitor circuit and to invalidate cached data in the cache circuit of the at least one processing element for the write back addresses.