1. A processing device comprising: a buffer to store one or more instructions; a decoder configured to decode the one or more instructions and generate one or more decoded instructions; a processor register file to store one or more operands; and a plurality of execution units, each of the plurality of execution units having: a plurality of execution stages configured to execute the one or more decoded instructions using the one or more operands, and a plurality of registers to latch data between the plurality of execution stages, the plurality of registers positioned between the plurality of execution stages to latch data between the plurality of execution stages, wherein a register of the plurality of registers positioned between a pair of execution stages of the plurality of execution stages is configured to provide data directly to a preceding register of the plurality of registers positioned between a different pair of execution stages of the plurality of execution stages.