1. A dynamically configurable multiprocessor that executes coded instructions comprising: a processor creation unit responsive to a processor create command to output signals indicating a current processor configuration; a plurality of processors each processor having a first set of execution resources that are uniquely identified with the processor and a second set of execution resources that are shared amongst the plurality of processors; a plurality of state machines responsive to the processor creation unit, each corresponding to a selected one of the plurality of processors, wherein the state machines maintain processor status information representative of whether the processor is available to receive and execute instructions; status logic analyzing expected latency of instructions on each processor and updating the state machine corresponding to any processor having an instruction with an expected latency greater than a preselected threshold; an instruction fetch unit coupled to the processor creation unit and the plurality of state machines, the instruction fetch unit configured to fetch instructions on a processor-by-processor basis for all processors indicated as active by the corresponding state machine; and a cache subsystem responsive to memory operation instructions from the plurality of processors, wherein the status logic is coupled to the cache subsystem to detect a cache miss that has to be serviced by off-chip cache and the status logic updates the state machine corresponding to the processor creating the cache miss to place the corresponding processor in a nap state in which instruction fetching for the corresponding processor is disabled.