1. A microprocessor comprising: an instruction buffer, wherein said instruction buffer is configured to store a plurality of instructions; a load prediction unit coupled to said instruction buffer, wherein said load prediction unit is configured to: detect a first load instruction of said plurality of instructions; predict a first load address of said first load instruction; and identify a first instruction of a new thread; and a data cache coupled to said load prediction unit, wherein said data cache is configured to: receive said first load address; and fetch data corresponding to said first load address in response to detecting said data is not present in said data cache.