1. A method of designing an analog integrated circuit, comprising: creating a schematic of an analog integrated circuit based on a set of specifications; attaching parasitic constraints to said schematic, the parasitic constraints comprising at least one limit of resistance, capacitance, or inductance applicable to circuit nodes in the schematic, and corresponding to the set of specifications; creating a layout of said analog integrated circuit based on said schematic including said parasitic constraints; extracting parasitic values from parasitic elements of said layout; and operating a computer to compare said extracted parasitic values with said parasitic constraints to verify compliance therewith.