1. In a data processing system including a cache memory and a processor for generating data word address signals and a read signal, the cache memory comprising: storing means for storing data words required by said processor; first means for identifying which data words are stored in said storing means; second means for identifying whether storage locations in said storing means contain valid or invalid data words; control means responsive to said read signal for controlling said first and second identifying means; and hit detection means connected to said first and second identifying means for generating a hit signal if a data word required by said processor is valid and stored in said storing means; characterized in that said control means is responsive to said read signal and said hit signal to control said second identifying means such that the storage location which contained said required data word is identified as containing an invalid data word.