1. An address centrifuge, comprising: a plurality of stages, each one of the plurality of stages having a plurality of boolean gates which realize a sum of products expression for centrifuging input bits into centrifuged address results bits, wherein the input bits include address bits; a first stage having eight one-bit address inputs and generating four sets of two-bit centrifuged results; a second stage coupled to the first stage, the second stage having the four sets of two-bit results as address inputs and two four-bit centrifuged results; and a third stage coupled to the second stage, the third stage having the two four-bit results as address inputs and one 8-bit result.