1. A multiprocessor system comprising: a plurality of processors; a main memory comprising a plurality of sections; a plurality of cache memories provided for said processors; interconnection network means for selectively connecting said cache memories to said sections for the transfer of data therebetween in accordance with address information for said data; shared bus means coupled to said cache memories for transferring said address information to said cache memories; and control means provided for said cache memories for monitoring said address information transferred through said shared bus means to ensure consistency of data stored in said cache memories with data stored in said main memory.