1. A data processing system, comprising: a multi-level cache hierarchy including a lowest level cache; a processor core coupled to the multi-level cache hierarchy; a memory controller coupled to the lowest level cache and to a memory bus of a system memory, the memory controller including: a physical read queue that buffers data read from the system memory via the memory bus; and a physical write queue that buffers data to be written to the system memory via the memory bus; wherein the memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.