1. An on-chip failure analysis circuit for analyzing a memory comprising: a built-in self test unit which tests the memory; a failure detection unit which detects a failure of memory output of the memory; a fail data storage unit in which fail data is stored, the fail data including a location of the failure; an failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure to write fail data including the analysis result in the fail data storage unit; and an analysis result output unit which outputs the analysis result of the failure analysis unit.