1. A circuit arrangement, comprising: (a) execution logic configured to execute a plurality of instructions defined by an instruction set, the instruction set defining at least one conditional branch instruction and at least one switch instruction, wherein the execution logic is configured to execute the conditional branch instruction; (b) instruction fetch logic configured to fetch instructions defined by the instruction set for execution by the execution logic; and (c) switch instruction handling logic configured to process a switch instruction fetched by the instruction fetch logic by generating a plurality of conditional branch instructions for execution by the execution logic to emulate the fetched switch instruction.