1. A compiler device to optimize a program by changing an order of executing instructions, said compiler device comprising: a replaceability determination unit to determine whether or not a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit to generate a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit to insert the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.