1. A process of designing base IC platforms that are customizable into integrated circuits comprising steps of: a) identifying a plurality of macros for placement on an IC platform, each macro representing a sub-circuit for placement on the ASIC, at least some of the macros being defined at least in part by a plurality of elements that perform respective functions of the associated macro; b) identifying identical elements in a plurality of macros; c) placing an identical element as a common element of at least two macros at a location on the platform suitable for inclusion of the at least two macros; and d) placing all other elements of the at least two macros are at locations on the platform relative to the common element as to satisfy macro placement rules for each of the at least two macros.