1. A pre-charging circuit of the output node of an output buffer (BUFFOUT) of an integrated digital system generating at least a first pulse (DLATCHN) for enabling the external visibility of a new datum (DATA) and a second pulse (LOAD) having a shorter duration than the first pulse (DLATCHN) for loading the new datum (DATA) in an output data register (DATABUS_LATCH) whose output is coupled to the input of said output buffer (BUFFOUT), characterized in that said pre-charging circuit comprises a capacitor (INTERNAL_CAPACITOR) connectable in parallel to the load capacitance of the output node (IO_pad) of the buffer by means of a second pass-gate enabled by a pre-charge command (PRECHARGE) corresponding to the logic AND of said second pulse (LOAD) and of the logic XOR of the new datum (DATA) and of the datum (OUT) currently present on the output node (IO_pad); a driver (D), disabled by said enabling first pulse (DLATCHN) charging said capacitor (INTERNAL_CAPACITOR) to a voltage (VC) corresponding to the logic level of a datum belonging to the group composed of said new datum (DATA) and the logic inversion of the current datum (OUT).