1. A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having two or more execution pipelines that begin execution of instructions in a common issue group in a delayed manner relative to each other, the method comprising: receiving an issue group of instructions; determining if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction; and if so, scheduling the first instruction to be executed in a pipeline in which beginning of execution of the first instruction is delayed with respect to beginning of execution of a second instruction in another pipeline in the cascaded delayed execution pipeline unit.