1. A memory device comprising: a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including: a memory controller for control of the DRAM, and repair logic coupled with the memory controller, the repair logic to hold addresses identified as failing addresses for defective areas of the DRAM; wherein the repair logic is configured to receive a memory operation request and to implement redundancy repair for an operation address for the request.