1. A cell array comprising: a logic connection line; a plurality of bit selection lines; a plurality of cells, each cell comprising: a memory element connected to a respective bit selection line; and a logic switching element that selectively connects the memory element to the logic connection line; wherein when logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements.