1. A processor chip that includes a processor core, a store queue (STQ) mechanism with a store queue, and RC dispatch logic, a method for re-ordering store operations from said processor core to said store queue, said method comprising: in response to receiving a new processor-issued store operation from said processor core, allocating a new entry in said store queue; in response to allocating said new entry, determining whether said new entry is dependent on at least one other valid entry in said store queue; and in response to determining said new entry is dependent on at least one other valid entry in said store queue, inhibiting processing of said new entry by said RC dispatch logic until each valid entry which said new entry is dependent has been processed by said RC dispatch logic.