1. A variation aware static timing analysis tool for integrated circuit (IC) design, the tool comprising: one or more parser software modules to receive an integrated circuit netlist, a circuit cell library, and interconnect parasitics associated with the integrated circuit netlist, the circuit cell library including circuit cell sensitivities to one or more semiconductor process variations, the interconnect parasitics including parasitic sensitivities to the one or more semiconductor process variations; a data modeler software module in communication with the one or more parser software modules to receive the integrated circuit netlist, the data modeler software module to add circuit cell netlists of the circuit cell library with their sensitivities into the integrated circuit netlist to generate a data model of the overall integrated circuit design for analysis; a delay calculator software module to receive circuit cell delays with their respective process variation sensitivities and the interconnect parasitics with its respective process variation sensitivities associated with the interconnections, the delay calculator software module to perform a delay calculation for each stage of the data model of the overall integrated circuit design in response thereto; and a path tracing software module in communication with the delay calculator to receive the delay calculation for each stage of the data model of the overall integrated circuit design and the data modeler to receive the data model of the overall integrated circuit design, the path tracing software module to add up the delays of each stage in at least one path of the integrated circuit netlist in response to the data model and the delay calculation for each stage of the data model.