1. A processor having an instruction register for storing an instruction for a ray-box intersection test having a predefined opcode, a predicate register for storing a predicate condition to select an output register for a result of the instruction, a first output register, and a second output register, the processor further comprising: processor circuitry operable to execute the instruction to produce a result; and processor circuitry operable to store the result of the instruction in the first output register if the predicate condition to select the output register is true, and the second output register if the predicate condition to select the output register is false, wherein the processor is operable with a single instruction to produce the result, and to store the result of the instruction, and wherein the predicate condition is based on comparing a value for a component of a ray direction vector to zero.