1. A computing system, comprising: a multi-core processor comprising a plurality of individual processor cores; a cache memory that is configured to be accessible to at least some of the plurality of the individual processor cores; and a cache controller coupled to the multi-core processor, the cache controller configured to allocate a memory space within the cache memory, the cache controller further being configured to facilitate access to the cache memory by at least some of the plurality of the individual processor cores with respective levels of associativity that are different for at least some of the plurality of the individual processor cores.