1. An intra prediction circuit device applied to the H.264 video coding standard, comprising: a first arithmetic operation unit transforming pixel data with rebuilding surrounding sides to bit data; a register storing the bit data; a first multiplexer decoding the bit data stored in the register; a second arithmetic operation unit computing the bit data computed by the first arithmetic operation unit with the bit data of the first multiplexer; a logic right shift unit shifting the bit data computed by the second arithmetic operation unit in a logical right shift manner; a post register storing the bit data shifted by the logic right shift unit with the logical right shift manner; a clipper electrically connected between the logic right shift unit and the post register; a second multiplexer electrically connected between the logic right shift unit and the clipper; and a third multiplexer electrically connected between an output of the first arithmetic operation unit and an output of the second arithmetic operation unit.