1. An apparatus comprising: one or more caches comprising one or more cache lines; a generator that generates memory access operations in response to software; an assignor that assigns a cache line color corresponding to the memory access operations; a receiver that receives and records a color state for each cache line in the one or more caches based upon the cache line color assigned, such that the memory access operations are distinguished by the cache line color and one or more cache lines are also distinguished by the cache line color; and a hardware maintained matrix comprising counters corresponding to cache line colors, the counters comprising: a counter representing a number of times that a specific event happens on a cache line color; and a counter representing the number of times that a cache line color interacts with another cache line color with respect to a specific event; wherein a specific event comprises one or more of a cache hit, a cache miss and a cache line replacement; wherein the behavior of the one or more caches is manipulated based on color information of the memory access operations.