1. A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit having a plurality of logic circuits and a plurality of output drivers, each of said plurality of logic circuits having an output, each of said plurality of output drivers having an input adapted to be selectively coupled to any of the outputs of the plurality of logic circuits, one of said plurality of logic circuits comprising a sequential logic circuit; and a programmable interconnection adapted to selectively couple the input of each of the plurality of output drivers to the output of a selected one of the plurality of logic circuits, whereby any of the logic circuit outputs may be coupled as an input to any one of the output drivers.