1. A solid state memory cell, comprising: an ion source layer comprising unbound conductive ions; an insulator layer that is at least in part permeable to the unbound conductive ions of the ion source layer, wherein the ion source layer is directly adjacent to the insulator layer, and the ion source layer and insulator layer form a resistive switching component having a plurality of resistance states in response to respective bias voltages at a pair of conductive electrodes; a p semiconductor layer; and an n semiconductor layer adjacent to the p semiconductor layer, wherein the p semiconductor layer and the n semiconductor layer are exclusive to the memory cell and form a solid-state p-n diode in series with the resistive switching component, wherein the p-n diode mitigates sneak path current flow through the solid state memory cell.