1. An apparatus comprising: a first processor to execute a plurality of instructions; a first storage to store a first entry representing entire first processor state for each instruction executed by the first processor from the plurality of instructions; a second processor to execute the plurality of instructions; a second storage to store a second entry representing entire second processor state for each instruction executed by the second processor from the plurality of instructions; a controller to synchronize the first processor and the second processor based on at least one entry from the first storage and at least one entry from the second storage.