1. An integrated circuit, comprising: a first processor core, comprising: logic circuitry; a plurality of embedded memories, each associated with at least one repair entity; and built-in self-test circuitry; and built-in self-repair circuitry, comprising: a first decode function, having an input coupled to the first processor core, for decoding test data from each of the embedded memories into fail signature data in a physical-aware format for the associated memory; align and merge circuitry, for reformatting the fail signature data from the first decode function into a unified repair format for all of the plurality of embedded memories of the first processor core; one or more fuse encoders, having an input coupled to the align and merge circuitry, each for generating a fuse pattern in the unified repair format for a repair entity; fuse reconfiguration logic, for reconfiguring the fuse patterns generated by the one or more fuse encoders from the unified repair format into a fuse pattern having an order corresponding to one or more of the repair entities for a selected one of the plurality of embedded memories; and a plurality of shadow fuse registers, each having an input coupled to the fuse reconfiguration logic, each for storing a fuse pattern for the repair entities of an associated embedded memory.