1. A processor, comprising: a pipeline stage including, a first input register; a second input register; a first output register; a second output register; a first selector in communication with the first input register and the second input register; a second selector in communication with the first output register and the second output register; and a controller operable to control switching of the first and second selectors such that data associated with a first processor thread pass through the first input register, the pipeline stage, and the first output register during a time that the first processor thread is being processed, and data associated with a second processor thread pass through the second input register, the pipeline stage, and the second output register during a time that the second processor thread is being processed, wherein the first input register and the first output register are operable to store a state of the first processor thread, and wherein the second input register and the second output register are operable to store a state of the second processor thread.