1. A memory cell including: a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate; a non-volatile n-channel transistor having a source coupled to a second potential, a drain, and a gate; and a stress transistor having a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit.