1. A processor comprising: a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times, the first plurality of compute engines comprising an initial compute engine and a final compute engine, wherein a first subset of the first plurality of compute engines is configured to execute flow instructions and a second subset of the first plurality of compute engines is configured to execute single-instruction-multiple-data (SIMD) instructions.