1. A computer system comprising: A central processor unit, CPU, having at least one execution unit means for executing instructions and producing processor data words, a store into cache for storing data words, means for issuing store into cache commands, and CPU circuit means interconnecting the execution unit means, the store into cache, and the means for issuing store into cache commands, the receipt of a store into cache command by the cache causing the cache to store at least one zone of data bits from a pair of processor data words produced by the execution unit means, each data word consisting of a predetermined number of bits which number is a multiple of the number of bits in a zone; and hierarchical memory system means operatively connected to the CPU for storing in and reading out of said memory system means blocks of system data words at locations of the memory system means having addresses, each block of system data words having a block address, a block address being the address of a block of addressable locations of the memory system means; said execution unit means producing as the result of the execution of an instruction at least one zone of processor data in a pair of processor data words for storage in the store into cache; means connected to the CPU circuit means for producing zone control bits having a predetermined binary value to identify the zones of each pair of processor data words containing processor data produced by said execution unit means for storage in the store into cache; means connected to the CPU circuit means for producing the block address of each pair of processor data words produced by the execution unit means for storage in the store into cache; said store into cache, in response to the receipt by the cache of a store into cache command, of a pair of processor data words, of a block address of the pair of processor data words, and of the zone control bits for said pair of processor data words, storing in said cache the bits of the zones of the processor data words containing processor data identified by zone control bits having said predetermined binary value said bits of the zones of the processor data words being stored in locations corresponding to the block address of said pair of processor data words; register means connected to the CPU circuit means for storing the zone control bits produced by the means for producing zone control bits; means operatively connected to the register means for extracting the zone control bits from the register means upon the receipt of a store to cache command for a block of system data words having the same block address as that of processor data words previously stored in the store into cache, said zone control bits having said predetermined binary value identifying the zones of the data words stored in the cache containing processor data; and means operatively connected to the means for extracting zone control bits and responsive to the zone control bits having said predetermined binary value for inhibiting the cache from storing corresponding zones of system data words of a block of system data words read out of hierarchical memory system means and transmitted from the hierarchical memory system means to the CPU.