1. An integrated circuit (IC) comprising: an arrangement of configurable tiles, each configurable tile comprising configurable circuits for configurably performing operations based on configuration data; and a pipelined network comprising a plurality of M-bit wide segments, each M-bit wide segment defined by a plurality of M-bit wide storage elements, each storage element for providing M-bits of data to one configurable tile in the arrangement in each clock cycle, M being an integer greater than one, wherein the pipelined network allows a plurality of sets of data to traverse the arrangement of configurable tiles simultaneously at different segments of the pipelined network.