1. A cache system, comprising: a cache memory dedicated to service a number of sequencers with sequencer code; a number of cache managers defined to direct placement of sequencer code portions into the cache memory, each of the number of cache managers defined to provide sequencer code from the cache memory to a respectively assigned sequencer; an external memory defined to store a complete version of the sequencer code; and a direct memory access (DMA) engine defined to write sequencer code portions from the external memory to the cache memory in accordance with direction from the number of cache managers.