1. A processor comprising: a plurality of processor cores; a plurality of design blocks coupled to the plurality of processor cores, each design block including a set of registers coupled to gated power, the set of registers to store active context of the design block; logic circuitry coupled to the plurality of cores and the plurality of design blocks, to monitor access to the set of registers of each design block to detect a change in the active context, and to store an indication of one or more of the design blocks that includes the change in the active context, wherein the logic circuitry comprises: a power manager to reduce voltage to the gated power when the processor is in the reduced power state, and wherein the voltage to the ungated power is not substantially reduced when the processor is the reduced power state, logic to save the active context of a design block to the memory according to the stored indication that the design block includes the change in context, and logic to store an indication identifying a subset of registers in the set of registers that have changed from a reset value; and memory coupled to the logic circuitry, the plurality of design blocks, and ungated power, the memory to store the active context while the processor is in a reduced power state.