1. A method of improving performance for a computer processor, said method comprising: receiving in an input/output processor data and a memory access instruction from said computer processor, said memory access instruction identifying a type of memory storage task from a group of more than one different memory storage task; analyzing said memory access instruction in said input/output processor to identify said type of memory storage task; if said type of memory storage task comprises a counter adjustment then updating a value containing recent adjustments to said counter in a higher-speed memory, and updating a full version of said counter in a slower-speed memory if an overflow of said value containing recent adjustments to said counter occurs; and if said type of memory storage task comprises a write to a FIFO queue then storing said data in a queue tail of said FIFO queue in said higher-speed memory, and moving data from said queue tail to a queue body of said FIFO queue in said slower-speed memory if said queue tail is filled.