1. A method for detecting conflicts and managing transaction execution (TX) memory, by a hierarchical cache of a multi-processor system, the hierarchical cache comprising a plurality of local caches, a plurality of intervening caches and a higher level cache, wherein each local cache and each intervening cache is associated with a corresponding single processor, wherein each cache comprises a cache controller, wherein the higher level cache is a shared cache associated with a plurality of processors each processor is any one of a single thread core and a multi-threaded core the method comprising: beginning execution of a first transaction, by a first processor thread, the first transaction comprising memory access instructions; in response to the first transaction requesting a cache line from a higher level cache, searching a cache directory of the higher level cache by a transaction identifier (ID) comprising a processor number and thread number, wherein the transaction ID uniquely identifies each of a plurality of transactions executing on the plurality of processors connected to the higher level cache, for an entry in the congruence class of the first transaction wherein a first read-set indicators or a first write-set indicators are not set for the entry; in response to locating the entry, evicting the located entry and fetching the requested cache line into the higher level cache; setting transaction indicators in the higher level cache based on corresponding cache lines being accessed by memory-operand-access operations of first instructions of the first transaction, the first transaction indicators comprising transaction identifier (ID), the first read-set indicators and the first write-set indicators; and based on determining, by the higher level cache, that a memory conflict has occurred associated with a first cache line of the higher level cache, causing the first transaction to abort and invalidating cache lines of the higher level cache having the transaction ID corresponding to the transaction ID of the first cache line and the first read-set indicators and the first write-set indicators.