1. A memory controller comprising: a read queue; a write queue; wherein the memory controller translates a read-modify-write (RMW) command into a read command on the read queue and a write command on the write queue and controls a sequence of executing the read command and the write command; and wherein the memory controller combines RMW commands that write to a same cacheline into a full cacheline write command and moves the full cacheline write command to the write queue.