1. An apparatus, comprising: a plurality of thread unit circuits to concurrently execute a plurality of threads, each of the plurality of thread unit circuits being capable of executing a checkpoint write instruction to update data stored in a memory storage area after execution of a checkpoint mask instruction; and the memory storage area comprising an active checkpoint storage area and a most recent valid checkpoint storage area, wherein the active checkpoint storage area is to store, in response to the checkpoint write instruction, first data for the checkpoint write instruction encountered during execution of one of the plurality of threads, the first data corresponding to register content data being written by the checkpoint write instruction; wherein the active checkpoint storage area is also to store second data for the checkpoint write instruction, the second data having a state indicative of a validity status of the register content data for the checkpoint write instruction, wherein an active checkpoint pointer, which points to the active checkpoint storage area, is to become a most recent valid checkpoint pointer, which points to the most recent valid checkpoint storage area, in response to a determination that all register contents corresponding to execution of multiple instances of the checkpoint write instruction by any of the plurality of thread unit circuits have been updated and all register contents corresponding to execution of the multiple instances of the checkpoint write instruction are indicated as completely valid by a checkpoint mask stored in the active checkpoint storage area.