1. A method for modeling combinatorial logic at an asynchronous clock domain crossing, the method comprising: employing a simulation value of X in combinatorial logic at an asynchronous clock domain crossing of a circuit being modeled for facilitating modeling of a combinatorial logic glitch, the employing comprising: propagating the simulation value of X through the combinatorial logic at the asynchronous clock domain crossing; and converting the simulation value of X at an output of the combinatorial logic to a random logic value for further propagation within the circuit being modeled.