1. A method of data processing in a data processing system including a processor core having a store-through upper level cache and a store-in lower level cache, a memory controller, a memory-mapped device, and an interconnect fabric communicatively coupling the lower level cache and the memory-mapped device, the method comprising: in response to a first instruction in the processor core, generating a copy-type request and transmitting the copy-type request to the lower level cache, wherein the copy-type request specifies a source real address; in response to a second instruction in the processor core, generating a paste-type request and transmitting the paste-type request to the lower level cache, wherein the paste-type request specifies a destination real address associated with the memory-mapped device; in response to receipt of the copy-type request from the processor core at the lower level cache, the lower level cache copying a data granule from a storage location specified by the source real address into a non-architected buffer; in response to receipt of the paste-type request from the processor core at the lower level cache, the lower level cache issuing on the interconnect fabric a command that writes the data granule from the non-architected buffer to the memory-mapped device associated with the destination real address; and in response to receipt of the command via the interconnect fabric, the memory-mapped device initiating one of a set including a direct memory access (DMA) operation and a computation on a data set.