1. A method of clock cycle synchronized flexible programmable data processing with a processor containing a plurality of different functional computation units, memory units, full access switch units for interconnecting them and control units, that comprises, connecting different functional units to form predetermined control paths and data pipelines in a hierarchical manner; using a common instruction set to program all functional units wherein the instruction set directly codes instruction sequencing (i.e. calculating address for next instruction fetch) and directly or indirectly codes hardware controls; setting up distributed program sequencing with each functional unit having its own program counter, instruction fetch and decode units and its own local memory for program storage; generating control vectors that control the datapath of such functional units, every clock cycle; and configuring multiple memory units to operate in different memory access modes and connecting them to functional computation units through said switch unit to maximize programmability.