1. A secure video content processor having a hardware barrier, the secure video content processor comprising: a first cryptographic unit placed within the hardware barrier, the first cryptographic unit decrypting incoming digital encrypted video information and producing encrypted image frames based on the video information; a frame buffer coupled to the first cryptographic unit and placed within the hardware barrier, the frame buffer receiving the encrypted image frames from the first cryptographic unit; and a second cryptographic unit coupled to the frame buffer and placed within the hardware barrier on a single chip with the first cryptographic unit, the second cryptographic unit retrieving the encrypted image frames stored in the frame buffer, decrypting the encrypted image frames, and converting the decrypted image frames into an analog signal.