1. A circuit arrangement, comprising: a vector execution unit configured to execute a floating point instruction to perform a floating point operation using at least one operand identified by the instruction, wherein at least one operand of the floating point instruction is a denormal value, the vector execution unit comprising: a first processing lane configured to prenormalize the denormal value operand loaded in the first processing lane, and a dot product adder configured to perform the floating point operation using the prenormalized value.