1. A method for stressing an integrated circuit (IC) comprising: providing the IC with a functional unit that includes multiple arrays of memory elements and with memory built-in self test (MBIST) circuitry configured to test the arrays of memory elements; and using the MBIST circuitry to stress the memory elements of the arrays by providing stress data to the arrays to set each memory element of the arrays in a first state and by providing inverse stress data to the arrays to set each memory element of the arrays in a second state that is an inverse of the first state of the respective memory element.