1. A non-volatile memory device, comprising: a plurality of wordlines (WLs); a plurality of local bitlines (LBLs) selectively electrically coupled with a plurality of global bit lines (GBLs); a plurality of re-writable non-volatile two-terminal memory elements, each memory element positioned between a cross-point of one of the plurality of WLs with one of the plurality of LBLs and each memory element directly electrically in series with its respective WL and LBL; and a plurality of amplifiers electrically coupled with the plurality of LBLs and the plurality of GBLs.