1. A memory system comprising: dissimilar memory groups each having at least one memory type; local test controllers each coupled to at least one of said memory types to generate a control signal; interface devices coupled to one of said dissimilar memory group to receive said control signals; a main controller to randomly initialize one of said local test controllers to test each of said dissimilar memory groups; and a serial interface connecting said local test controllers and main controller in a ring configuration for said random initialization.