1. A system for a nano-scale FPGA, comprising: a series of rows of nano-scale gates that are arrayed on a silicon substrate and that are configured into logic array grids; look up tables (LUTs) in memory components on the periphery of a nano-scale device: nano-scale connectors between gates; wherein a routing of logic arrays is done by using nano-scale connectors between the gates; wherein the gates are structured into grids of evolvable logic arrays; wherein the logic array grids access LUTs; wherein the logic array grids access memory on the periphery of the device; wherein the gates reconfigure to a different position when initiated; wherein the device contains between 1,000 and 10,000 gates; wherein the device reconfigures its gates in response to feedback from its environment; wherein the environment is electronic, biological or chemical; and wherein the environment provides feedback to the device.