1. A multi-core computer system, comprising: a first processor core on a die and a second processor core on the die; a first priority register associated with the first processor core and a second priority register associated with the second processor core; and an arbiter circuit operatively coupled to the first processor core and the second processor core, wherein the arbiter circuit allocates access to a shared resource available to the first processor core and the second processor core based on a first value stored in the first priory register and a second value stored in the second priority register.