1. A method of operating a processor, said method comprising: at least one instruction execution unit executing store instructions to obtain store operations; in a queue entry of a store queue coupled to said instruction execution unit, gathering multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory; selecting a store gathering window duration for said queue entry; maintaining a count of a number of consecutive clock cycles for which a store operation is not gathered in said queue entry; comparing the count and said store gathering window duration and responsive thereto, generating a dispatch signal to cause dispatch of a write transaction from said queue entry; and varying a duration of said store gathering window.