1. A processor, comprising: a coprocessor that executes instructions in-program order; an execution unit that executes instructions out-of-program order; a coprocessor interface unit that couples the coprocessor to the execution unit, the coprocessor interface unit including a coprocessor store data queue that is configured to store a result of an instruction executed by the coprocessor; a completion buffer configured to store one or more codes associated with each instruction executed by the co-processor; a graduation unit coupled to the coprocessor and configured to synchronize the coprocessor and the execution unit by graduating instructions in-program order by providing a signal to the coprocessor, based on the one or more codes in the completion buffer, that determines whether the result in the coprocessor store data queue is permitted to alter an architectural state of the processor.