1. A dynamically reconfigurable array logic comprising: a RAM programmable logic array comprising an array of bits, each bit comprising a fuse connection between logic elements; I/O means coupled to the RAM programmable logic array for logical selection of registered output; first register means coupled to the RAM programmable logic array for receiving data and high level commands; sequencer means coupled to the RAM programmable logic array for generating addresses, said sequencer means comprising a pair of up/down counters; timing means coupled to the RAM programmable logic array for issuing READ and WRITE strobes; and second register means coupled to the RAM programmable logic array for monitoring outputs in both a first mode and a second mode.