1. A processor, comprising: a return address prediction circuit configured to: store return addresses for different ones of a plurality of threads executable on the processor, wherein the return address prediction circuit includes a content addressable memory having a plurality of entries, wherein each entry is configured to store a respective one of the return addresses and a thread identifier indicative of one of the plurality of threads, wherein each of the plurality of entries is configured to store a respective age value indicative of an ordering in which return addresses are stored for a respective one of the plurality of threads; store a respective counter value for each thread, wherein each counter value is indicative of a total number of return addresses currently stored for a respective one of the plurality of threads by the return address prediction circuit; receive a first request for a predicted return address for a first thread of the plurality of threads, wherein the first request includes an indication of the first thread; and provide the predicted return address to the first thread in response to the content addressable memory 1) determining that the indication of the first thread corresponds to a thread identifier in an entry that includes the predicted return address and 2) determining that an age value stored in the entry that contains the predicted return address corresponds to the counter value for the first thread.