1. A method of operating a digital processor system of the type containing a microprocessor device and an addressable memory; the microprocessor device including an ALU, addressing means, and control means responsive to instruction words; comprising the steps of: in a first time period, executing an operation in the ALU defined by a first instruction word to produce a first result while the addressing means is sending an address to said memory for a second instruction word, in a second time period, storing said first result in the memory while decoding said second instruction word in said control means, in a third time period, sending an address to the memory for an operand according to the second instruction word, in a fourth time period, executing an operation in the ALU defined by the second instruction word using said operand to produce a second result while sending an address to said memory for a third instruction word, and in a fifth time period, storing said second result in the memory while decoding said third instruction word in said control means.