1. A multi-processor system on a chip, comprising: a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; wherein the bus system is adapted for dynamically establishing and releasing transmission channels between a sending one of the elements and a receiving one of the elements; and wherein the bus system is adapted for forming at least one ring via interconnection elements that include pipeline-registers.