1. A processor supporting concurrent execution of a plurality of threads, said processor comprising: an external control path for receiving commands from an external processor; a thread execution state register containing a dynamic execution state of multiple threads executing within said processor; and a control logic coupled to said external control path and said thread execution state register for receiving thread-execution-state dependent commands from said external control path and selectively performing actions in response to said commands in conformity with said dynamic execution state of at least one of said multiple threads.