1. A neuromorphic network for producing spike-timing dependent plasticity, comprising: a plurality of electronic neurons; and an interconnect circuit comprising a cross-bar array coupled to the plurality of electronic neurons for interconnecting the plurality of electronic neurons, the cross-bar array comprising: multiple axon paths; multiple dendrite paths; multiple membrane paths; a plurality of synaptic devices for interconnecting the plurality of electronic neurons via the multiple axon paths, the multiple dendrite paths and the multiple membrane paths; and a plurality of dendrite drivers corresponding to the multiple dendrite paths and a plurality of axon drivers corresponding to the multiple axon paths, wherein each dendrite driver is coupled to a dendrite path of the multiple dendrite paths at a first side of the interconnect circuit, and each axon driver is coupled to an axon path of the multiple axon paths at a second side of the interconnect circuit; wherein each axon driver and each dendritic driver includes a stochastic signal generator for generating a stochastic signal based on spiking of an associated neuron; wherein each stochastic signal generator comprises: a cyclic counter that is constantly updating its value in every programming phase; a spike dependent counter that is initiated in response to an associated neuron spiking; and a comparator that creates a binary enable pulse in response to determining a value of the spike dependent counter is greater than the value of the cyclic counter; wherein each membrane path is controlled based on a spiking of an electronic neuron connected to the membrane path; and wherein each synaptic device comprises: a variable state resistor with a first terminal and a second terminal; and a transistor device with a gate terminal, a source terminal and a drain terminal; wherein the drain terminal of the transistor device is connected in series with the first terminal of the variable state resistor; wherein the source terminal of the transistor device is connected to an axon path of the multiple axon paths; wherein the gate terminal of the transistor device is connected to a membrane path of the multiple membrane paths; wherein the second terminal of the variable state resistor is connected to a dendrite path of the multiple dendrite paths, such that the synaptic device is coupled between the axon path and the dendrite path, and between the membrane path and the dendrite path; and wherein a state of the variable state resistor changes as a function of time since a last spiking of an electronic neuron connected to the membrane path.