1. A method of designing an integrated circuit, comprising modifying a design—variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit, wherein the modification is performed by a design/synthesis tool implemented in a processor prior to arriving at an initial layout for a design of the integrated circuit; and synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit.