1. A device, comprising: a cache memory; a processor in communication with the cache memory, the processor configured to execute logic operable to: dynamically allocate a portion of the cache memory for use by the processor; modify an index function in accordance with the allocated portion of the cache memory; apply the modified index function to a system memory address to determine an index of a cache line corresponding to the system memory address, the cache line included among a group of cache lines identified with the modified index function as being in the allocated portion of the cache memory; and constrain operation of the cache memory to the group of cache lines identified with the modified index function.