1. A system for supporting efficient packet processing in a network device, comprising: a plurality of packet buffers in a memory on the network device; a direct memory access (DMA) resources pool, wherein said DMA resource pool comprises one or more of DMA resources, wherein each said DMA resource in said DMA resource pool points to a chain of packet buffers in the memory; and wherein each said DMA resource allows a packet processing thread to access a chain of packet buffers in the memory using a thread key pre-assigned to the packet processing thread.