1. A multiprocessor device comprising: a plurality of processors wherein each processor of the plurality of processors includes an interrupt controller having one or more interrupt inputs; and a symmetric interrupt crossbar coupled to the one or more interrupt inputs of the interrupt controllers, the symmetric interrupt crossbar having a plurality of interrupt inputs and a plurality of interrupt outputs, wherein each interrupt input that is not reserved is coupled to a respective interrupt output of an interrupt source of a plurality of interrupt sources, and the plurality of interrupt outputs is coupled to the one or more interrupt inputs of the interrupt controllers in a one-to-one relationship such that one interrupt output is coupled to only one interrupt input of only one interrupt controller, wherein the symmetric interrupt crossbar is programmable to map an interrupt signal from any interrupt source of the plurality of interrupt sources coupled to the symmetric interrupt crossbar to any interrupt input of any interrupt controller coupled to the symmetric interrupt crossbar, wherein programming the symmetric interrupt crossbar to map interrupt signals from the plurality of input sources to interrupt inputs of the interrupt controllers is performed when the multiprocessor device is booted.