1. A computer system with error detection capabilities, comprising: a system bus; a central processing unit being coupled to said system bus and being capable of delivering signals to and receiving signals from said system bus; a memory controller being coupled to said system bus, said memory controller being capable of delivering signals to and receiving signals from said system bus, said memory controller having a non-volatile memory, said non-volatile memory having an area designated for storage of data correlative to detected errors; a main memory being coupled to said memory controller, said main memory being capable of delivering signals to and receiving signals from said memory controller; and error correction circuit means controlled by a program being executed by said central processing unit, said circuit for checking to verify if an error is correctable, and then collecting a detected error and storing data correlative to said detected error as a syndrome in said designated area of said non-volatile memory and said error correction circuit enabling copying said designated area into said main memory at the initiation of each operating session, said error correction circuit including means to use said syndrome to identify an area of said main memory which might have said detected error.