1. A single-chip control device having a central processing unit and a memory interface for interfacing with an external memory, the single-chip control device comprising: at least one function block; a first register for storing operation state information of the function block; a state detection circuit for activating a flag signal when the operation state information of the first register is varied; a storage unit for storing the operation state information of the first register in response to the flag signal; and a control circuit for transmitting the operation state information of the storage unit to an internal bus in response to the flag signal in order to store the operation state information of the storage unit in the external memory through the memory interface.