1. A circuit-design-modifying method executed in a computer system, comprising steps of: performing a first synthesis-with-optimization operation of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis-with-optimization operation of the first and second HDL codes while forcibly preserving specified elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second circuit and the third circuit to generate at least one ECO cone pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic, thereby modifying the post layout circuit into a post layout ECO circuit.