1. A method of forming integrated circuit devices comprising: forming a plurality of patterned device outlines over a semiconductive substrate; forming electrically insulative spacers on at least a portion of the patterned device outlines; and forming a plurality of substantially identically shaped devices relative to the patterned device outlines, at least two individual devices of the plurality being spaced from one another by a distance no greater than a width of an interposed electrically insulative spacer.