1. A memory comprising: a memory cell array on a chip; a built-in self test (BIST) circuit on the chip and coupled to the memory cell array, the BIST circuit configured to perform a write operation to write addresses of failed memory cells in the memory cell array to a failed address sector in the memory cell array; and a first select circuit coupled between the BIST circuit and the memory cell array, the first select circuit configured to selectively couple an output of the BIST circuit and an input to the memory cell array.