1. Apparatus for processing a sequence of instructions, which are stored at different memory addresses in a physical address space, wherein the apparatus is formed to address a logical address space by a predetermined number of logical addresses, and wherein the physical address space is larger than the logical address space, wherein a jump instruction comprises a physical address to address an instruction, which is positioned outside of a physical memory window defined by the logical address space, and wherein a re-jump instruction is provided to terminate a sub-sequence of instructions started by the jump instruction, comprising: a reader for reading in an instruction of the sequence of instructions; an examiner for examining the instruction, wherein the examiner is formed to determine and store re-jump information in the case of the presence of the jump instruction, which refer to the presently current physical memory window, and to retrieve a predetermined amount of the stored re-jump information in the case of a re-jump instruction; and a decoder for decoding the predetermined amount of stored re-jump information to determine whether the predetermined amount comprises a reference to a physical address outside of a current physical memory window, to activate the examiner in such a case, to retrieve another amount of the stored re-jump information to identify the physical address outside of a current physical memory window for a re-jump.