1. An inter-processor-interrupt-generation facility within a processor, the inter-processor-interrupt-generation facility comprising: one or more interrupt memory registers that each specifies a region within a shared-memory address space, one or more target processors, and an interrupt vector; and a combination of one or more of logic circuits, state machines, and firmware that, when a WRITE operation is directed to a shared-memory region specified by an interrupt memory register, generates an inter-processor-interrupt, of an interrupt type specified by the interrupt vector included in the interrupt memory register, that is directed to the one or more target processors specified in the interrupt memory register.