1. A central processor means for processing operands in response to instructions in a data processing system, the data processing system additionally including a memory means for storing the operands and instructions, each operand comprising at least one information bit and each instruction including an operation code having at least one information byte and certain of the instructions including at least one operand specifier, each operand specifier comprising at least one information byte and identifying the location for an operand in the data processing system, said central processor means comprising: A. program counter means for identifying locations in the memory means of operation codes in successive instructions, B. instruction retrieval means connected to said program counter means for normally sequentially retrieving successive bytes of information from the memory means to which said instruction retrieval means connects, C. operation code decoding means connected to said instruction retrieval means for ascertaining, in response to the operation code, the number of operand specifiers that the instruction contains, and D. operand specifier decoding means connected to said instruction retrieval means and to said operation code decoding means for sequentially decoding successive bytes of the information following the operation code to identify a location for each specified operand, said operand specifier decoding means being responsive to information in the operand specifier that identifies the total number of information bytes in that operand specifier, thereby to enable retrieval from the memory means of successive instructions comprising a variable number of information bytes stored in contiguous byte locations in the memory means.