1. A semiconductor memory device comprising: a memory cell array comprising a test cell determined as a worst one among the memory cells passing a first test; a test unit for performing a second test on the test cell in predetermined operation conditions, repeatedly performing the second test after adjusting the operation conditions of the test cell according to the result of the second test and finally outputting the final operation conditions; and a driving unit for driving the memory cell array by using the final operation conditions from the test unit.