1. A parallel processing device, comprising plural operational blocks each comprising: a data storage unit including a plurality of data entries each including a plurality of memory cells arranged as a memory cell array; a plurality of arithmetic/logic processing elements, each of which couples with a corresponding entry and performs a designated operational processing on data stored in the corresponding entry; a plurality of data transfer lines for transferring data between each of the entries and corresponding arithmetic/logic processing element; and a plurality of data transfer circuits, arranged corresponding to said plurality of data transfer lines respectively, for transferring data between the memory cell in the corresponding entry and the corresponding arithmetic/logic processing element, wherein each data transfer circuit transfers data stored in a first memory cell in the corresponding entry to the corresponding arithmetic/logic processing element; each arithmetic/logic processing element executes the designated operational processing for the data transferred from the first memory cell; and each data transfer circuit transfers a result data of the designated operational processing by the corresponding arithmetic/logic processing element to a second memory cell in the corresponding entry, wherein when executing a SIMD operation instruction, the data transfer circuits select the first memory cell in the corresponding entries coupled with a same word line for an operation in the SIMD operation instruction, and wherein when executing a MIMD operation instruction, the data transfer circuits select the first memory cell in the corresponding entries coupled with different word lines for respective operations in the MIMD operation instruction.