1. A method of producing masks for fabricating semiconductor structures, which comprises: generating layout data with information defining a mask layout with individual geometric elements; defining geometric design requirements and an arrangement for the individual structure elements; checking the layout data as to whether the geometric design requirements and the arrangement for the individual structure elements are satisfied; if the design requirements are not satisfied, locating corresponding error locations in the mask layout using the layout data; generating further layout data with information for defining correction figures to correct the respective error locations; and linking the layout data with the further layout data for modifying the layout data.