1. In a computer memory having a plurality of memory banks each containing a plurality of addressable memory cells, the memory being arranged to store vectors such that data elements of each vector are stored in memory cells in different memory banks in an interleaved pattern, each vector having an initial address and spacing data representing a spacing between successive addresses, the improvement comprising, for each memory bank: setup apparatus for receiving the initial address and spacing data for each of a plurality of vectors being accessed; cell select apparatus responsive to the memory bank's position in the interleave pattern and to the transmission of a cell select associated with an initial or subsequent address of a data element of a respective vector to the memory bank for identifying a next cell select to access; and addressing logic responsive to the setup apparatus and the cell select apparatus and to a respective vector's bank select for addressing the memory bank using the cell select from the cell select apparatus.