1. A multiprocessor system that supports multiple cache line invalidations within the same cycle, comprising: a plurality of processors; a lower-level cache that is configured to support multiple concurrent operations; a plurality of higher-level caches coupled to the plurality of processors, wherein the plurality of higher-level caches are configured to perform memory accesses through the lower level-cache; and wherein each of the plurality of higher-level caches is configured to support multiple concurrent invalidations of lines within the higher-level cache.