1. A processor for a multiprocessor system connected to a network, comprising: an instruction processor for executing instructions; a local memory for holding instructions to be executed by the instruction processor and data to be processed thereby, and an access controller for controlling access to said local memory; a main cache for holding part of data held by said local memory and a main cache controller connected to said main cache and instruction processor, and said access controller for controlling said main cache; and a sending unit connected to said main cache for sending data on the network and a receiving unit for receiving data from the network; a receive cache and a receive cache controller connected to said receive cache, said receive unit and said instruction processor and said access controller for controlling the receive cache so that said receive cache temporarily stores data received by the receiving unit which is to be stored in said local memory; said main cache controller responding to a memory write request provided by said instruction processor for first data to be written into the local memory, so as to write said write data into said main cache, said main cache controller not writing said received data into said main cache and said receive cache controller not writing said first data requested by said memory write request into said receive cache; said main cache controller and said receive cache controller both further responding to a common memory read request initiated by said instruction processor unit for second data held in said local memory so as to read the second data requested by the read request from one cache which holds said second data among said main cache and said receive cache; and said main cache controller further responding to a memory read request provided by said sending unit for send data so as to supply the send data from the main cache to the sending unit.