1. A Field Programmable Gate Array integrated circuit comprising: a multi-dimensional configurable cell structure including a plurality of configurable cells; and a configurable interconnect connecting the configurable cells; wherein each of at least one of the cells is a data processing circuit that is hard-wired within the Field Programmable Gate Array and includes: at least two inputs, each being at least 4-bit wide; at least one output being at least 4-bit wide; at least one multiplier; and interconnecting logic operable to couple the at least two inputs and the at least one output to the configurable interconnect.