1. A processor comprising: an instruction fetch unit configured to fetch instructions from a memory; and an instruction decode unit coupled to the instruction fetch unit and configured to decode fetched instructions into micro-operations for execution by an execution unit; wherein the decode unit is configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction; and wherein the processor is further configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed, wherein the single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction.