1. A storage system comprising: a first and a second flash memory group, each group comprising a plurality of flash memory devices; a storage controller including a first processor group, a second processor group and a third processor group, each processor group comprising one or more processors for handling a different stage of a pipelined execution of host storage commands; the first processor group including a host interface circuit coupled to receive a first host command and a second host command from one or more hosts, the first processor group including a first processor and a second processor configured for parallel processing of the first host command and the second host command; the second processor group including a command processing circuit, the command processing circuit including a first processor and a second processor configured for parallel processing of the first host command and the second host command, the command processing circuit configured to provide the first host command to a first processor of the third processor group and the second host command to a second processor of the third processor group; wherein the first processor of the third processor group is associated with the first flash memory group and the second processor of the third processor group is associated with the second flash memory group, each such processor of the third processor group being configured for controlling at least some operations of the flash memory group associated therewith; wherein the storage controller is configured to cause the first and second host commands to be carried out substantially simultaneously.