1. A data processing apparatus comprising a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a particular predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said predetermined values stored in said settable elements form an instruction or decoded instruction.