1. An apparatus for processing an exchange instruction and a load instruction from a memory in parallel in a pipe-lined processor having a first pipe-line, a second pipe-line and a register file of a stack structure, the apparatus comprising: a stack-top updating means for generating a new stack-top signal and a current stack-top signal by updating the stack-top after receiving an information signal about a modification of the stack-top following execution of an instruction by the first pipe-line, the stack-top updating means also receiving a control signal which represents a load instruction executed by one of the second pipe-line and the first pipe-line, and a second pipe-line enable signal; an AND gate for ANDing the second pipe-line enable signal and the control signal to detect execution of the load instruction in the second pipe-line; a decoder for decoding the information signal; a first adder for adding the decoded signal and the current stack-top signal; a subtracter for subtracting 1 from an output signal of the first adder corresponding to an output of the AND gate; a first multiplexer for outputting the new stack-top signal which is that one of the output signal of the first adder and the output signal of the subtracter that corresponds to the output signal of the AND gate; and a register for storing an output signal of the first multiplexer and for outputting the current stack-top signal; a first pipe-line address generating means for generating a first source operand pointer address, a second source operand pointer address and a first destination operand pointer address of instruction which is to be executed in the first pipe-line by receiving the current stack-top signal, a first source operand, a second source operand and a first destination information instruction inputted to the first pipe-line; a second pipe-line address generating means for generating a third source operand pointer address and a fourth operand pointer address of one of the load instruction and the exchange instruction which is to be executed in the second pipe-line, by receiving the source operand of an instruction which comes to the second pipe-line, the new stack-top signal from the stack-top updating means, the first source operand pointer address and the second source operand pointer address from the first pipeline address generating means, and the second pipe-line enable signal and the control signal representing that the load instruction is executed at one of the first pipe-line and the second pipe-line, the second pipe-line address generating means including, an OR gate for ORing the second pipe-line enable signal and the control signal; a second multiplexer for outputting, as the third source operand pointer address of an instruction executed in the second pipe-line, that one of the stack-top signal and the first source operand pointer address that corresponds to an output signal of the OR gate; a second adder for adding the new stack-top signal and the source operand of the instruction which comes to the second pipe-line; and a third multiplexer for outputting, as the fifth source operand pointer address of the instruction executed in the second pipe-line, that one of an output signal of the second adder and the second source operand pointer address that corresponds to the output signal of the OR gate; a pointer register file that has an address of an actual data register file by receiving the address output from both the second pipe-line address generating means and the first pipe-line address generating means; and a physical data register file for outputting a stored operand to an execution unit corresponding to the actual data register file address output from the pointer register file.