1. A method for testing a set of circuitry in an integrated circuit (IC) comprising a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a plurality of configurable routing circuits for configurably passing signals among the circuits of the IC, a plurality of controllable storage elements for controllably storing signals as the signals transit between the configurable circuits, and a debug network that accesses the controllable storage elements, the method comprising: configuring the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria, each test path comprising a set of configurable logic circuits, a set of configurable routing circuits, and at least one controllable storage element; operating the IC in the user mode; and reading values stored in the storage elements along the set of test paths through the debug network to determine whether the set of circuitry is operating within specified performance limits.