1. A floating point multiplier comprising: a circuit for generating a signal indicative of partial products of significands of operands; a carry-save adder for adding the partial products and generating a signal indicative of a sum vector SV1 and a carry vector CV1, wherein each of the vectors SV1, CV1 comprises: 1) one or more digits in one or more first digit positions which are to be included into a significand of a product of the operands; 2) one or more digits in one or more second digit positions comprising a digit position at which a rounding digit is to be added; and 3) one or more digits in one or more third digit positions not to be included into the significand of the product of the operands; a circuit for generating a signal indicative of a carry C3-2 from the third digit positions into the second digit positions; an adder for adding the digits of the sum vector SV1 in the first digit positions to the digits of the carry vector CV1 in the first digit positions and generating a signal indicative of a sum vector SSV1 and a carry vector CCV1; an adder for adding the digits of the sum vector SV1 in the second digit positions to the digits of the carry vector CV1 in the second digit positions and generating a signal indicative of a sum S2 and a carry C2; an adder for adding the sum vector SSV1 to a vector formed by concatenating the carry vector CCV1 and the carry C2, and for generating a signal indicative of conditional sums corresponding to different possible values of a carry C2-1 into the first digit positions wherein the carry C2-1 is caused by an addition, to the sum S2, of the rounding digit and of the carry C3-2; a circuit for generating, for different oossible values of the carry C3-2, a signal indicative of the possible values of the carry C2-1; a first multiplexer for selecting, based on the carry C3-2, one of the possible values of the carry C2-1; and a second multiplexer for selecting from the conditional sums on the basis of the value selected by the first multiplexer.