1. A specialized integrated circuit for a Test and Training Enabling Architecture (TENA) gateway, the specialized integrated circuit comprising: a packet parser logic block configured to parse an incoming MAC layer packet, the incoming MAC layer packet including one more packet headers; a TCP packet handler logic block; and a plurality of TENA packet generator logic blocks, wherein the packet parser logic block is configured to parse an incoming MAC layer packet and to conditionally provide a TCP packet to the TCP packet handler depending on the one or ore packet headers in the incoming MAC layer packet, wherein the TCP packet handler logic block is configured to parse the TCP packet and selectively provide a TENA message to one of the TENA packet generator logic blocks, wherein the selected one of the TENA packet generator logic blocks is configured to construct an outgoing TENA message in response to the provided TENA message, wherein the operation of the packet parser logic block and the TCP packet handler logic block and the TENA packet generator logic blocks is concurrent.