1. A digital baseband processor comprising: at least one main processor for executing instructions in a first instruction sequence; and a timing and event processor coupled to said main processor for executing timing-sensitive instructions in a second instruction sequence, said timing and event processor comprising: two or more instruction sequencers for executing threads of the second instruction sequence; and a time base generator for generating timing signals for initiating execution of instructions on each of the two or more instruction sequencers, wherein said time base generator is configured to use a unified time base derived from a plurality of time bases.