1. An apparatus comprising a processor and a memory storing executable instructions that in response to execution by the processor cause the apparatus to at least perform the following: processing data during a connection between the apparatus and another apparatus, the data being processed in accordance with a predetermined coding scheme; selecting or receiving a selection of feedback code information during the connection, the feedback code information comprising information from which a parity-check matrix is constructable, the feedback code information comprising one of a seed parity-check matrix, an exponent matrix, an index of a parity-check-matrix-related permutation matrix, or an index of an exponent-matrix-related permutation matrix; and switching the processing of data to process the data during at least a portion of the connection in accordance with a parity-check coding technique based upon the feedback code information.