1. A method comprising: setting a number of hypervisor register fields to specify which processor cores are allowed to generate a number of performance events for a particular thread group; configuring a plurality of software threads for an application running in the computing environment into a plurality of thread groups by a plurality of thread group fields in a plurality of control registers; and specifying, by a number of additional hypervisor register fields, a number of counter sets that are allowed to count a number of thread group events originating from one of a shared resource and a shared cache.