1. A multi-graphics command processor chip for use within a computing system, said multi-graphics command processor chip comprising: multiple graphics command processor driven pipeline cores wherein each said graphics command driven pipeline core includes a graphics command processor and generates pixel values of images associated with at least a portion of a digital image to be displayed on said display surface; a routing center for distributing graphics data received from one or more computer command processors to said multiple graphics command processor driven pipeline cores and for collecting rendering results from said multiple graphics command and processor driven pipeline cores; and, a display interface for receiving said rendering results from said routing center wherein said multiple graphics command processor pipeline cores, said routing center, said processing element, and said display interface are implemented on a single semiconductor chip and wherein said multiple graphics command processor pipeline cores are arranged to work in parallel on said single semiconductor chip to receive graphics data from said routing center according to a parallelization mode, wherein the parallelization mode is selected from one of: (a) an object division mode; or (b) an object division mode and a time division mode; or (c) an object division mode and a time division mode and an image division mode; and wherein said command processor chip additionally comprises an auxiliary memory for storing data and wherein the stored data comprises intermediate processing results from one or more of said multiple graphics command processor driver pipeline cores, composition data and processed data for display.