1. A library test circuit for verifying functions of a plurality of standard cell library logic cells, the library test circuit comprising: a core module including a plurality of standard cell library logic cells, each logic cell having a predetermined number of input vector combinations, the core module outputting test result signals according to a standard cell library; a first switch bank for outputting a first input signal to the core module so as to select cell identifiers corresponding to respective logic cells; a second switch bank for outputting a second input signal to the core module so as to select pattern identifiers corresponding to input vector combinations of each logic cell; a first display device; and a second display device; wherein, in an automatic mode where all cell identifiers and all pattern identifiers are sequentially automatically selected, the first display device and the second display device display an identification code of the logic cell in which an error is detected, wherein, in a semi-automatic mode where a cell identifier for the semi-automatic mode is selected and all pattern identifiers corresponding to the cell identifier for the semi-automatic mode are sequentially automatically selected, the second display device displays an identification code of the input vector combination in which an error is detected, wherein, in a manual mode where a cell identifier for the manual mode is selected and a pattern identifier for the manual mode is selected, the first display device and the second display device display a test result signal thereof, and wherein the test result outputted by the core module presents the error detected in the automatic mode, the semi-automatic mode or the manual mode.