1. A logic structure comprising: an array of memory cells arranged in rows and columns; a plurality of decoders, one decoder for each row or each column, each decoder receiving both true and complemented values for each address bit; a pair of logic gates associated with each address bit, wherein said pair of logic gates provide said true and complemented values for each address bit; and a wildcard register providing one enable bit for each address bit, wherein both of said logic gates receive said enable bit from said wildcard register, one of said logic gates receives said address bit, and the other of said logic gates receives the complement of said address bit.