1. A branch target buffer (BTB) method for storing target address, applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture, said method comprising the steps of: determining and setting the part of identical address field of a branch instruction address and a target address; while looking up said BTB, using an instruction address increment unit to increment some part of an arrived instruction address, or an instruction address decrement unit to decrement some part of said arrived instruction address, or neither said instruction address increment unit nor said instruction address decrement unit executing any operation according to determined values of a carry bit and a sub/add bit; after said instruction address increment unit or said instruction address decrement unit executing said increment or said decrement operation, returning computation result to said BTB; and said BTB combining said identical part of said branch instruction address and said target address and said computed part above said variation range of said target address to form a complete target address and outputting said complete target address.