1. A method of synthesis of multiple implementations of an integrated circuit design, comprising: using at least one computer for translating an input model of the design to a first output model compliant with a first set of constraints for constraining implementations of the design; and using said at least one computer for translating the input model to a second output model compliant with a second set of constraints for constraining implementations of the design, wherein the input model specifies functional relationships between operational values of the design, and translating the input model includes translating functional relationships from the input model into corresponding hardware descriptions for the design.