1. An integrated circuit, comprising: a substrate having a back surface extending in an X dimension and a Y dimension; a three-dimensional memory array comprising vertical NAND memory cells extending in a Z direction from the back surface of the substrate; and a control circuit built on the substrate and positioned below at least portions of the three-dimensional memory array, the control circuit comprising: a wordline circuit, divided into at least two subcircuits, to control the memory array; and a bitline circuit, divided into at least two subcircuits, to control the memory array; wherein the wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.