1. A circuit partitioning apparatus for partitioning a target circuit to execute parallel circuit simulation, the apparatus clustering an input target circuit, collecting clusters to create a plurality of subcircuits, and outputting the subcircuits to a simulation execution means, comprising: an initial clustering means for partitioning said target circuit into a plurality of clusters; a min-cut means for collecting clusters generated by said initial clustering means to create the plurality of subcircuits, where each subcircuit comprises a circuit matrix; Lower/Upper decomposition means for decomposing the circuit matrix of each subcircuit composed of clusters generated by the initial clustering section into a product of triangular matrices; an update operation times counting means operative prior to the execution of circuit simulation for counting a number of update operations for said Lower/Upper decomposition using a directed graph, where each update operation is defined as a matrix operation required to generate each elemet of said triangular matrices from the circuit matrix of each subcircuit; and a computation time prediction means using the results of counting by said update operation times counting means to predict a simulation computation time required by said simulation execution means, prior to the execution of circuit simulation, wherein said initial clustering means and said min-cut means feed back the results of the simulation computation time predicted by said computation time prediction means and carry out clustering and min-cut to create subcircuits that require equal computation time for each subcircuit's simulation.