1. A processor having an out-of-order pipeline, comprising: an instruction fetch portion of the pipeline; an instruction execution portion of the pipeline, coupled to the instruction fetch portion of the pipeline; and pipeline control logic, coupled to the instruction fetch portion of the pipeline and the instruction execution portion of the pipeline, wherein the pipeline control logic: halts movement of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline in response to a detection of a control transfer instruction misprediction resulting from a control transfer instruction comprising a control transfer instruction ID checked by a misprediction instruction ID checker; invalidates instructions residing within the instruction fetch portion of the pipeline; continues executing instructions in the instruction execution portion of the pipeline after detection of the control transfer instruction misprediction until the control transfer instruction reaches a selected stage of the instruction execution portion of the pipeline; invalidates instructions residing in the instruction execution portion of the pipeline once the control transfer instruction reaches the selected stage; and restarts transfer of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline.