1. A processor comprising: a plurality of vector registers each having at least 128-bits; a decode stage to decode a first instruction for a single instruction multiple data (SIMD) SM3 hash round slice, the first instruction to specify a round-slice portion of an SM3 hash algorithm, an intermediate hash value input operand, a source data operand set, and a round constant operand set that is to include at least one pre-rotated round constant, wherein at least one of the intermediate hash value input operand, the source data operand set, and the round constant operand set are to be stored in the plurality of vector registers; and one or more execution units coupled with the plurality of vector registers and coupled with the decode stage, the one or more execution units, responsive to the decoded first instruction, to: perform an SM3 hash round-slice set of round iterations upon the source data operand set, including to apply the intermediate hash value input operand and the round constant operand set; and store a result of the first instruction in a destination vector register of the plurality of vector registers.