1. An apparatus for monitoring the performance of a computer system, comprising: one or more processing units; a memory; a connector device connecting the one or more processing units and the memory; one or more hardware probes included in at least one of the processing units and configured to generate probe signals in response to detecting predetermined processing events; and a hardware-based thread trace device connected to the connector device, the thread trace device including (i) an event memory, (ii) an event interlace configured to receive the probe signals from the hardware probes and to store probe event messages for the received probe signals in the event memory, and (iii) an event memory buffer controller configured to send probe event messages from the event memory to the memory.