1. A memory device comprising: a cross-point array of non-volatile memory cells arranged into rows and columns; and a read circuit capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the at least one first resistive random access memory (RRAM) block selection element while programming a second resistive state to at least one second RRAM block selection element, the block selection element respectively connected at least two global selection control lines with a uni-flow device.