1. A method of maintaining cache coherency in a multi-processor computer system having a system memory device and a plurality of processing units, each processing unit having a cache hierarchy including at least first- and second-level caches, the method comprising the steps of: storing a value in a first-level cache of a first processing unit, in response to a write-through store operation executed by the first processing unit, without storing the value in a second-level cache of the first processing unit; writing the value to the system memory device; and providing an indication at the second-level cache that the value is held in a shared state in the first-level cache but is undefined in the second-level cache.