1. An apparatus for branch prediction, comprising: processor means for executing a plurality of instructions concurrently; a branch prediction table which registers entries, each entry including a branching address indicating the plurality of instructions containing a predicted branch instruction, a branch target address of said predicted branch instruction, and an instruction location indicating a location of said predicted branch instruction in said plurality of instructions indicated by said branching address; instruction fetch means for fetching the plurality of instructions to be executed concurrently by said processor means by fetching the plurality of instructions indicated by the branch target address of the predicted branch instruction for a presently fetched plurality of instructions at a next processing timing, where said predicted branch instruction for said presently fetched plurality of instructions is registered in one entry of said branch prediction table having the branching address which coincides with an address of said presently fetched plurality of instructions; prediction judging means for judging said predicted branch instruction for said presently fetched plurality of instructions as correct when said predicted branch instruction is actually encountered during actual execution of said presently fetched plurality of instructions; and predicted instruction invalidation means for invalidating the plurality of instructions indicated by said branch target address of said predicted branch instruction for said presently fetched plurality of instructions which are fetched by said instruction fetch means at the next processing timing, when said prediction judging means does not judge said predicted branch instruction as correct.