1. A processor comprising a) a first number of functional units, for executing respective operations in parallel with each other, the first number being at least three; b) an instruction issue register for holding a second number of operations for executing on the functional units, the second number being at least two and less than the first number, and each operation including a respective operation code associated with a respective one of the functional units; c) a multiport register file for storing operands relating to the operations in the instruction issue register, the multiport register file comprising a third number of read ports for affording parallel access to the operands, the third number of read ports being at least equal to a maximum number of operands required from the register file by any subset of the functional units, which subset consists of the second number of functional units, the third number being smaller than a total number of operands required by the first number of functional units together; and d) operand selecting means for selecting which of the functional units accesses which of the operands from the multiport register file.