1. A computer for reducing the execution time required for branch instructions, said computer comprising a main memory, an instruction fetch unit for fetching instructions from said main memory, an instruction cache for storing instructions for execution, and an execution unit for executing the instructions stored in the instruction cache, said instruction fetch unit comprising first means for storing a first address of a first instruction, second means for storing said first instruction, third means for storing a second instruction sequentially following the first instruction in the main memory, generating means, responsive to the contents of said first, second and third means, for generating a second address of an instruction to be executed following the first instruction, said second address being that of the second instruction if neither the first and second instructions are branch instructions, a branch address specified by the first instruction if the first instruction is a branch instruction, or a branch address specified by the second instruction if the first instruction is a nonbranch instruction and the second instruction is a branch instruction, means for transferring the first instruction and the second address for storage in said instruction cache, and means in the execution unit for addressing the instruction cache at the second address after addressing the first instruction to obtain the next instruction for execution.