1. An associative memory device selectively entering into a registration mode and a retrieval mode, comprising: a) a plurality of addressable associative memory cells each implemented by a series combination of a first electrically erasable and programmable memory transistor and a second electrically erasable and programmable memory transistor, and formed into a plurality of associative memory cell groups; b) a plurality of pairs of data lines selectively provided for said plurality of addressable associative memory cells, the data lines of each pair being coupled to control gate electrodes of said first electrically erasable and programmable memory transistors of the associated addressable associative memory cells and control gate electrodes of said second electrically erasable and programmable memory transistors of said associated addressable associative memory cells; c) a plurality of potential lines selectively associated with said plurality of associative memory cell groups, said series combination of each of the associated addressable associative memory cells being inserted into the associated potential line; d) a variable voltage source connectable with said plurality of potential lines, and operative to supply a current to said plurality of potential lines; e) a data line driver unit coupled to said plurality of pairs of data lines, said data line driver unit being responsive to registration data bits in said registration mode for storing said registration data bits in said plurality of addressable associative memory cells, and operative to selectively energize the data lines of said plurality of pairs for changing one of said first electrically erasable and programmable memory transistor and said second electrically erasable and programmable memory transistor of each addressable associative memory cell to a non-conductive state depending upon the logic level of one of said registration data bits, said data line driver unit keeping both of said first electrically erasable and programmable memory transistor and said second electrically erasable and programmable memory transistor of one of said plurality of addressable associative memory cells in a conductive state when said one registration bit is a don't-care bit, said data line driver unit being responsive to reference data bits in said retrieval mode for selectively energizing said data lines of each pair, and checking said plurality of associative memory cell groups to determine whether or not said reference data bits are matched with said registration data bits stored in one of said plurality of associative memory cell groups, the first electrically erasable and programmable memory transistors and the second electrically erasable and programmable memory transistors of one of said plurality of associative memory cell groups being conductive when the registration data bits stored therein are matched with said reference data bits; and f) a current detecting unit connectable to said plurality of potential lines for detecting said current passing through one of said plurality of associative memory cell groups storing said registration data bits matched with said reference data bits, and operative to produce a hit signal indicative of the match between said reference data bits and said registration data bits.