1. In a microprogrammed data processor having data processor circuitry comprised of an arithmetic unit part, register parts and other processor parts interconnected by data flow bus parts to define a data flow path, all for processing machine macroinstructions having operation codes, the combination comprising: a plurality of control points interspersed at predetermined locations in the data flow path, said control points being adapted and cooperatively coupled therein to enable and disable data flow in predetermined portions of the data flow path; a primary store for storing microwords for defining control actions for predetermined combinations of parts of the data processor circuitry; primary store address circuitry for reading microwords out of said primary store; a first secondary store having stored therein a plurality of mode words for defining additional control actions for predetermined combinations of parts of the data processor circuitry and said control points; a mode register cooperatively coupled between said secondary store and said control points having output lines coupled to said control points of the data processor circuitry for controlling same; circuitry responsive to the current machine macroinstruction operation code for addressing said first secondary store and causing it to supply a selected mode word to said mode register; a second secondary store having stored therein a plurality of starting addresses for different sequences of microwords in said primary store; and circuitry responsive to the current machine macroinstruction operation code for addressing said second secondary store and causing it to supply a selected starting address to said primary store address circuitry for selecting the particular sequence of microwords to be read out of the primary store.