1. A memory array, comprising: a plurality of columns of substantially identical memory cells, wherein all memory cells within each column are commonly connected to a given one of a plurality of bitlines, at least one bitline corresponding to each column; and a ring oscillator circuit comprising a particular memory cell from each of said plurality of columns, wherein said memory cells forming said ring oscillator correspond to a row of said memory array and are connected in a cascade configuration forming a ring, whereby said ring oscillator oscillates at a frequency affected by a loading of said memory cells within other rows of said memory array.