1. A method of redesigning a circuit by reducing a netlist representation of the circuit, wherein the circuit comprises a plurality of nodes including a node, the method comprising: obtaining through use of a computer a plurality of Binary Decision Diagram (BDD) representations associated with said node in the netlist; identifying a reduction in the netlist by synthesizing one of the plurality of BDD representations as a netlist region associated with the node; modifying the netlist representation using the identified netlist region associated with the node to produce a rewritten netlist representation; and redesigning the circuit based on the rewritten netlist representation.