1. A hardware processor comprising: a plurality of execution units in parallel; a switch to: connect inputs of the plurality of execution units to an output of a first buffer and outputs of a plurality of memory banks, and connect inputs of the plurality of memory banks and parallel inputs of a plurality of second buffers to an output of the first buffer, outputs of the plurality of memory banks, and outputs of the plurality of execution units; and an offload engine with inputs connected to outputs of the plurality of second buffers.