1. A superscalar processor in which instructions of the same or different types are dispatched and executed in parallel in multiple execution units, comprising: a decoder unit for decoding fetched complex and specialized multi-cycle execution instructions and for loading them into a instruction queue buffer; a dispatch unit for examining the loaded complex multifunctional and multi-cycle instructions in said instruction queue buffer and grouping them for execution, and dispatching said grouped complex multifunction and multi-cycle instructions via instruction dispatch ports to a fixed point execution unit (FXU) for execution of the dispatched instructions in parallel in multiple execution pipelines of said superscalar processor.