1. A method of reducing a digital circuitry design to build a simplified circuit that preserves assertability, the method comprising: build a simplified netlist from an original netlist of the digital circuitry design; build a composite netlist from the simplified netlist and the original netlist, said composite netlist comprising a plurality of failure targets associated with a respective plurality of implications; check each of said plurality of implications to ensure that for an associated simplified netlist target there is a corresponding original netlist target; verity the simplified netlist by determining whether each of the plurality of failure targets is assertable or is unassertable; report as being validated any unassertable ones of the plurality of failure targets in response to the verifying the simplified netlist; if there are any assertable ones of the plurality of failure targets, attempt to validate said assertable ones of the plurality of failure targets by considering a failure scenario in the simplified netlist and checking for a corresponding failure scenario in the original netlist; and report as being validated any assertable ones of the plurality of failure targets having said failure scenario in the simplified netlist and said corresponding failure scenario in the original netlist.