1. A general purpose, reconfigurable parallel-to-parallel interface system for interfacing a first data bus from a first digital subsystem to a second data bus from a second digital subsystem, the interface system comprising: buffer memory storage means for providing temporary storage of a plurality of data signals transmitted between said first and second subsystems, said buffer memory storage means operating in response to memory storage control signals; programmable bus sizing means for modifying the word size of a plurality of data signals transmitted between said first and second subsystems in response to bus sizing control signals; level translating means connected to said first digital subsystem for translating the electrical levels of a plurality of data signals on said first data bus to electrical levels of said reconfigurable system; reconfigurable state machine means for generating a plurality of interface control signals in accordance with a state table in response to a plurality of external condition signals, said external condition signals including mode control signals, said interface control signals including said memory storage control signals and said bus sizing control signals; means for establishing a data path through said interface system for connecting said first data bus to said second data bus, said data path comprising said buffer memory storage means, said bus sizing means and said level translating means; control signal path means for establishing a control signal path between said state machine means and said first digital subsystem, said control signal path being separate from said data path through the interface system and for carrying handshake control signals between said state machine means and said first digital subsystem, said handshake control signals comprising said external condition signals; host processor means for generating said state table and said mode control signals for said state machine means; and wherein said state machine means operates autonomously from said host processor means upon receiving said state table and said mode control signals until said host processor generates a fresh state table and mode control signals to reconfigure the interface system.