1. A method for the design and manufacturing of a 3D semiconductor device comprising a first circuit stratum and a second circuit stratum, the method comprising: applying a synthesis tool with at least first and second technology libraries; and performing a synthesis that utilizes said at least first and second technology libraries, wherein said first and second technology libraries correspond to two different processes, wherein said first technology library targets said first circuit stratum and said second technology library targets said second circuit stratum, wherein said first circuit stratum is fabricated using a less advanced process node than said second circuit stratum, and wherein said performing a synthesis results in a netlist, said netlist comprises first cells of said first technology library and second cells of said second technology library.