1. A multi-port memory device comprising: a first port; a second port; a first dedicated memory area assigned to the first port; a plurality of shared memory units having shared access by the first and second ports; a first set of I/O lines for the first dedicated memory area; and a second set of I/O lines for the shared memory units, wherein said second set has more I/O lines than said first set, and wherein each of the first set of I/O lines is formed adjacent a respective one of columns or rows of memory cells within the first dedicated memory area, and wherein each of the second set of I/O lines is formed adjacent a respective one of columns or rows of memory cells within the shared memory unit.