1. A method comprising: a processor and a memory for performing the steps of broadcasting data units of packets to a plurality of finite state machine (FSM) comparison units, each of the FSM comparison units implementing a portion of a signature; comparing the data units of the packets to a plurality of signatures, including each FSM comparison unit of the plurality of FSM comparison units independently and concurrently comparing one of the data units to the corresponding portion of a signature implemented by said each of the FSM comparison units; and combining results of the plurality of FSM comparison units independently processing the data units using a logic combinatorial circuit wherein combining results comprises logically ANDing results from a subset of the plurality of FSM comparison units, each FSM in the plurality matching a portion of a first signature from the plurality of signatures, and translating information on the match of the first signature into one or more values.