1. A multiprocessor system including a plurality of processors each with a cache memory, and a main storage shared by said plurality of processors, said system comprising: means for realizing cache coherence control by broadcasting a cache coherence request to each of said processors via a bus; means for setting said bus in a split form so that a broadcasting range in said bus covers a part of said system, not the entirety thereof; a directory for recording, in an associated relationship with respect to said main storage, and for each of data blocks of said main storage, an ID of any one of said processors that registered the data block in its cache memory; and means for conducting cache coherence control between said processors by using the ID information recorded in said directory; wherein cache coherence control based on transmission of the cache coherence request via said bus is conducted between said processors connected by said bus, and cache coherence control using said directory is conducted between said processors disconnected from one another by split setting of said bus.