1. A phase-locked loop circuit comprising: a phase comparison means for detecting a size of a leading phase or a delayed phase of a feedback signal with respect to a reference signal and outputting a leading phase signal having a pulse width corresponding to the size of the leading phase or a delayed phase signal having a pulse width corresponding to the size of the delayed phase; a smoothing means for smoothing the leading phase signal or the delayed phase signal output from the phase comparison means and outputting the result as a control signal; a superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the control signal; and an oscillation circuit for receiving the control signal superposed with other signals by the superposing means and outputting the feedback signal of a frequency corresponding to the control signal to the phase comparison means.