1. A processor comprising: a first instruction cache to store first instructions of essential code that, when the first instructions are executed, determine the logical correctness of a program; a second instruction cache to store second instructions of non-essential code that, when the second instructions are executed, provide hints for the execution of the first instructions; a plurality of triggers to specify a plurality of the nonessential instructions that are to be executed; and a single execution unit to execute both the essential instructions and the non-essential instructions, the processor to process the non-essential instructions in response to the triggers.