1. A method for designing a layout for manufacturing an integrated circuit, the method comprising the steps of: providing a design layout including functional design shapes; discretizing said functional design shapes into a plurality of computational subunits; identifying a geometrical context region around each of said plurality of computational subunits; identifying a representative subunit of said plurality of computational subunits wherein said representative subunit represents a subset of said plurality of computational subunits each having essentially identical geometrical context regions; performing a computation for said representative subunit of said subset; and applying said computation to all occurrences of said representative subunit in said design layout.