1. A method for conducting a parallel analysis on a circuit design represented by a graph comprising: using a computer, creating a global shared queue of ready to process nodes of said graph; creating a plurality of local queues of ready to process nodes of said graph, each of which is owned by a separate computation process; moving nodes from said global shared queue to said local queues of at least two of said separate computation processes; concurrently in said separate computation processes, removing nodes from at least two of said local queues, processing said removed nodes, updating node values in the circuit design, and adding new ready to process nodes to said local queues, wherein said adding said new ready to process nodes is based upon updating predecessor count values; and moving at least one node from one of said local queues to said global shared queue when a number of said nodes in said local queue exceeds an upper threshold value.