1. A method of code optimization in presence of hardware constraints, the method comprising: scheduling instruction codes using virtual registers in a manner that tends to minimize simultaneous active registers while minimizing a number of passes of a processing unit; allocating the virtual registers to physical registers according to a plurality of register allocation orders to produce a corresponding plurality of physical register allocations; determining a conflict value for each register allocation from the plurality of physical register allocations; determining a physical register allocation corresponding to a least conflict value; and rescheduling the instruction codes using the physical register allocation to optimize the code by further reducing a number of conflicts.