1. A non-volatile-memory-transistor based lookup table for an FPGA including: a multiplexer having x address inputs, 2 x data inputs, and an output; a plurality of data-input circuits, each coupled to one of the data inputs of the multiplexer and including: a first non-volatile n-channel MOS transistor having a drain coupled to a power supply potential, a source coupled to the data input of the multiplexer, a floating gate, and a control gate, a second non-volatile n-channel MOS transistor having a drain coupled to the data input of the multiplexer, a source coupled to ground, a floating gate, and a control gate, and a sense amplifier coupled to the output of the multiplexer.