1. A method for verifying equivalent digital circuits ( 10 ) by comparing values of selected outputs ( 16 , 17 ) for equal values of selected inputs ( 12 , 13 ) thereof, the method comprising the steps of: a) analyzing ( 1 ) global clock configurations of said selected inputs and said selected outputs; b) equalizing said global clock configurations by modifying ( 2 ) design representations of said digital circuits (Code A, Code B); and c) determining the equivalency of said digital circuits ( 10 ) by comparing ( 3 ) the modified design representations (Wrapper A, Wrapper B).