1. A node comprising: a memory controller configured to couple to a memory comprising a plurality of coherency blocks, wherein the node permits coherent access to the plurality of coherency blocks by other nodes; a directory configured to track a state, in the other nodes, of at most a first number of the plurality of coherency blocks, the first number less than a total number of the plurality of coherency blocks, wherein the directory includes a plurality of entries, each entry configured to track the state of one coherency block; and a control circuit coupled to the directory, wherein, in response to an access by one of the other nodes to a first coherency block that is a miss in the directory, and wherein the control circuit is configured to select a first entry of the plurality of entries to track the state of the first coherency block, and wherein, if the first entry is currently tracking the state of a second coherency block, the node is configured to cause the second coherency block to be invalidated in the other nodes.