1. A method of designing a charge trapping memory array, the method comprising: designing a floating gate memory array layout, the floating gate memory layout comprising: a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block; modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors; determining an operating voltage difference between the I/O block and the second type of transistors; and modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.