1. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising: a) a first input interface connected to said second core, comprising a first input request connection for asserting a first input request signal to said second core, a first input ready connection for receiving a first input ready signal asserted by said second core, and a first input data connection for receiving a first input token from said second core; b) data processing logic connected to said first input data connection, for generating a first output token from said first input token; c) a first output interface connected to said data processing logic and said third core, comprising a first output request connection for receiving a first output request signal asserted by said third core, a first output ready connection for asserting a first output ready signal to said third core, and a first output data connection connected to said data processing logic, for transmitting said first output token to said third core; d) first input control logic connected to said first input interface, for controlling said first core to receive said first input token if said first input request signal and said first input ready signal are asserted with a predetermined synchronous relationship; and e) first output control logic connected to said first output interface, for controlling said first core to transmit said first output token to said third core if said first output request signal and said first output ready signal are asserted with a predetermined synchronous relationship.