1. A system comprising: a processor having a prefetch unit configured to generate addresses for accessing data from a system memory, the prefetch unit including: a first prediction unit configured to generate a first memory address according to a first prefetch algorithm; a second prediction unit configured to generate a second memory address according to a second prefetch algorithm; and an arbitration unit configured to select either the first or second memory address for use during a given prefetch operation, and wherein the arbitration unit is further configured to inhibit prefetching responsive to determining that power associated with prefetching will be wasted; wherein the arbitration unit is configured to arbitrate between the first and second addresses using a round-robin arbitration scheme for a first arbitration cycle, and further configured to arbitrate using an accuracy-based arbitration scheme for a second arbitration cycle.