1. An apparatus, comprising: a memory configured to store a plurality of entries, wherein each entry of the plurality of entries includes a data portion and a tag portion, wherein the tag portion includes at least an address tag and a type indicator, wherein the type indicator has a value indicative of a type of data stored in the data portion; a control circuit coupled to the memory and to a processor, wherein the control circuit is configured to: receive an instruction request, from the processor, for instruction data at a given address within a storage device; retrieve, in response to a determination that the instruction data corresponding to the given address is omitted from the plurality of entries, the instruction data from a higher-level memory; modify an address value included in the retrieved instruction data for use by the processor; store the retrieved instruction data, including the modified address value, in a given entry; set the address tag in the tag portion of the given entry to correspond to the given address; set the value of the type indicator in the tag portion of the given entry to indicate that instruction-type data is stored in the given entry; receive a non-instruction request to retrieve non-instruction data at the given address where the instruction data is currently stored; determine that the data corresponding to the given address has been stored in the given entry of the plurality of entries dependent upon the address tag in the tag portion of the given entry; and invalidate the given entry in response to a determination that the value of the type indicator in the tag portion of the given entry indicates that instruction-type data is stored in the given entry.