1. A method, comprising: executing a logical reduction instruction in a semiconductor processor, said executing comprising the following: storing a vector having multiple elements into a register; swizzling the elements of the vector with swizzle circuitry to form a first swizzled vector; performing a vector logic operation with vector logic circuitry on the vector and the first swizzled vector to form a first intermediate vector; swizzling said first intermediate vector's elements with swizzle circuitry to form a second swizzled vector; performing said vector logic operation with vector logic circuitry to form a second intermediate vector; and, performing said logic operation on less than all of said second intermediate vector's elements.