1. A stack-gate flash cell structure, comprising: a semiconductor substrate of a first conductivity type; a cell region comprising a gate region being formed over said semiconductor substrate, wherein said gate region being formed between a common-source region and a common-drain region is defined by a first masking photoresist step; said common-source region comprising a common-source diffusion region being formed in a first surface portion of said semiconductor substrate, an etched-back planarized silicon dioxide layer over a first portion of a tunneling dielectric layer being formed over said common-source diffusion region, and a pair of extended floating-gate spacers being formed on side portions of said etched-back planarized silicon dioxide layer; said common-drain region comprising a common-drain diffusion region being formed in a second surface portion of said semiconductor substrate, said etched-back planarized silicon dioxide layer over a second portion of said tunneling dielectric layer being formed over said common-drain diffusion region, and said pair of extended floating-gate spacers being formed on side portions of said etched-back planarized silicon dioxide layer; said gate region comprising a major floating-gate being formed over a third portion of said tunneling dielectric layer, wherein said major floating-gate is integrated with nearby two extended floating-gate spacers to form an integrated floating-gate; a word line on an intergate dielectric layer being formed over said integrated floating-gate and a portion of said etched-back planarized silicon dioxide layers between said pair of extended floating-gate spacers, wherein said word line, said intergate dielectric layer, and said integrated floating-gate are simultaneously patterned and etched by using a second masking photoresist step; and a cell isolation region being formed in each side surface portion of said semiconductor substrate outside of said word line and between said common-source region and said common-drain region.