1. A memory array comprising: a plurality of first electrodes, each having first and second lateral edges over a substrate; a resistance variable material over the plurality of first electrodes; and a plurality of material stacks over the resistance variable material, each material stack located between adjacent first electrodes and comprising at least a conductive material and a second electrode, wherein a first material stack is directly over a first lateral edge of a first electrode to form a first memory element, the first material stack not being directly over a second lateral edge of the first electrode, and a second material stack is directly over the second lateral edge of the first electrode to form a second memory element, the second material stack not being directly over the first lateral edge of the first electrode, the first and second memory elements being electrically connected to the first electrode.