1. A digital circuit design method, comprising: before performing a physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraints file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file according to at least the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.