1. A method for specifying a test sequence for a circuit, the circuit being modelled to have a plurality of external contact nodes, a plurality of internal nets, and at least one sub-circuit having input/output nodes connected to the internal nets, comprising the steps of: modelling possible first faults associated with the external contact nodes, the plurality of internal nets, and the input/output nodes of the at least one sub-circuit; modelling only specified ones of possible second faults associated with at least one of one or more of the internal nets and one or more nets that are internal to the at least one sub-circuit; and generating a specification of a sequence of test pin excitations that are predetermined to detect the presence of the possible first and second faults.