1. A processor comprising: an instruction execution pipeline having: an instruction fetch stage to fetch a single instruction comprising a first input operand specifying multiple target resultant registers and a separate, second input operand comprising a mask vector; an instruction decode stage to decode said single instruction into a decoded single instruction; data dependency logic circuitry to check each of the multiple target resultant registers for data dependencies for the single instruction; a functional unit to execute the decoded single instruction when all of the multiple target resultant registers are cleared for data dependencies to prepare resultant content specific to each of said multiple target resultant registers, and provide said resultant content specific for each of said multiple target resultant registers based on the mask vector; and a write-back stage to write back said resultant content specific to each of said multiple target resultant registers based on the mask vector.