1. A hardware device for delivering inter-processor interrupts, comprising: a memory having a memory space being mapped to a virtual memory space of a first guest process; and a controller coupled to the memory, the controller being configured to detect when interrupt information is recorded in the memory space, the interrupt information being directed to a second guest process associated with a particular CPU core; wherein in response to detecting that the interrupt information is recorded in the memory space, the controller is configured to generate an interrupt based on the interrupt information that causes the second guest process to run on a different CPU core without making an operating system call.