1. A computer-implemented method, performed on at least one computing device, of modeling at least one feature in an integrated circuit (IC) layout for an inter-level effect, the method comprising: building a set of shape measurement regions each connected with an edge of the at least one feature, each shape measurement region increasing in width as it moves away from the edge; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.