1. A method for the logic design verification of a logic unit wherein the logic unit includes at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units include a set of test operations which are carried into execution by the logic unit, said method comprising the steps of: selecting, at said at least one test units a test operation from the set of test operations included therein, wherein said selection of said test operation at each of said at least one test units is performed pseudo-randomly and wherein said selection of said test operation at one of said at least one test units is independent from the selection of a test operation at the others of said at least one test units; and determining the starting times of the test operation for each of said at least one test units, wherein said determination of the starting times of the test operation for each of the at least one test units is performed pseudo-randomly and wherein said determination of a starting time at one of the at least one test units is independent from the determination of the starting times of the test operation at the others of said at least one test units; and providing said selected test operation to said logic unit at said determined start times via said at least one interface means to determine if there are any logical failures associated with the logic unit so as to verify the logical design of the logic unit; wherein the step of selecting the test operations and the step of determining the starting times of the test operations at each of said at least one test units are executed independently of each other.