1. A Field Programmable Gate Array integrated circuit comprising: a multi-dimensional configurable cell structure including a plurality of configurable cells; and a configurable interconnect connecting the configurable cells; wherein each of at least one of the cells is a data processing circuit that is hard-wired within the Field Programmable Gate Array and includes: at least two input ports, each being at least 4-bit wide; at least one output port being at least 4-bit wide; at least one multiplier hardware unit arranged for receiving an input from the at least two input ports and for providing an output to the at least one output port; and circuitry that couples the at least two input ports and the at least one output port to the configurable interconnect.