1. A method of reducing a digital circuitry design to build a simplified circuit that preserves assertability, the method comprising: build a simplified netlist from an original netlist of the digital circuitry design; build a composite netlist from the simplified netlist and the original netlist, said composite netlist comprising a plurality of failure targets associated with a respective plurality of implications including an implication, said implication being associated with a failure target among the plurality of failure targets; check each of said plurality of implications of the composite netlist to ensure that for an associated simplified netlist target there is a corresponding original netlist target, wherein an assertion of said failure target indicates a failure of the implication associated with said failure target; verify, using a computer, the simplified netlist by determining whether each of the plurality of failure targets of the composite netlist is assertable or is unassertable; report as being validated any unassertable ones of the plurality of failure targets in response to the verifying the simplified netlist; determine an assertable failure target among the plurality of failure targets of the composite netlist; validate said assertable failure target by considering a failure scenario of the failure target in the simplified netlist and confirming a corresponding failure scenario in the original netlist; and report as being validated said assertable failure target in response to confirming said failure scenario in the simplified netlist and said corresponding failure scenario in the original netlist.