1. An apparatus for packet processing in a switching network comprising: a memory, the memory comprising: a plurality of words wherein each word in the plurality of words has a plurality of bits wherein each word in the plurality of words is addressed by separate and distinct read address; a logic circuit wherein all bits in the plurality of bits in each word in the plurality of words addressed by a separate and distinct read address are logically ORed together; wherein a result of ORing all bits in the plurality of bits in each word in the plurality of words addressed by a separate and distinct read address is output by the logic circuit; wherein each of the read addresses further comprises: an address ingress/egress bit wherein when the address ingress/egress bit is true the read address is associated with an ingress pipeline; wherein when the address ingress/egress bit is false the read address is associated with an egress pipeline; wherein an ingress wordline is enabled when the address ingress/egress bit is true; and wherein an egress wordline is enabled when the address ingress/egress bit is false.