1. A method of optimizing register transfer level code for an integrated circuit design comprising steps of: (a) receiving as input a first register transfer level code for the integrated circuit design; (b) receiving as input criteria defining a critical multiplex structure; (c) analyzing the first register transfer level code to identify multiplex structures in the first register transfer level code; (d) comparing each of the multiplex structures identified in the first register transfer level code to the criteria defining a critical multiplex structure; (e) including each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure in a list of critical multiplex structures; and (f) generating as output the list of critical multiplex structures.