1. A computer implemented method for storing a data line in one or more caches of a chip multiprocessor, said chip multiprocessor including a plurality of processor cores, each of said plurality of processor cores including at least one first level (L1) cache, each of said plurality of processor cores communicatively coupled to a shared second level (L2) cache, said computer implemented method comprising: receiving an access request from a requesting processor core of said chip multiprocessor, said access request identifying said data line; storing said data line in at least one of said shared second level (L2) cache and said at least one first level (L1) cache based on a sharing of said data line in said chip multiprocessor; generating an enhanced second level (L2) cache directory entry in a shared second level (L2) cache directory of said shared second level (L2) cache, said enhanced second level (L2) cache directory entry indicating a storage state of said data line in said chip multiprocessor; determining whether said access request is a read access request or a write access request; when said access request is a read access request, determining whether said data line is in said first level (L1) cache; when said data line is not in said first level (L1) cache, determining whether said data line is in said shared second level (L2) cache; when said data line is in said shared second level (L2) cache, obtaining said data line from said shared second level (L2) cache; installing said data line in said first level (L1) cache of said requesting processor core; determining whether said data line is in said shared second level (L2) cache only; when said data line is in said shared second level (L2) cache only, determining whether said data line was previously stored in said first level (L1) cache of said requesting processor core only; when said data line was previously stored in said first level (L1) cache of said requesting processor core only, evicting said data line from said shared second level (L2) cache; and generating an enhanced second level (L2) cache directory entry including a cache mask, said cache mask indicating a storage state of said data line in said chip multiprocessor.