1. A microprocessor comprising: a decode unit coupled to receive an instruction and configured to determine a first data transaction type corresponding to said instruction, wherein said first data transaction type is one of a plurality of data transaction types; and a load/store unit coupled to receive said first data transaction type if said instruction includes a memory operation, wherein said load/store unit is configured to determine an access mode for said memory operation in response to said first data transaction type, wherein said access mode comprises: (i) a cacheability mode indicating whether or not data corresponding to said memory operation is cacheable, wherein said cacheability mode indicates non-cacheable for at least one of said plurality of data transaction types; and (ii) a prefetch mode indicating a prefetch strategy corresponding to said memory operation.