1. A processor for video analytics comprising: a plurality of registers each partitioned into at least two fields, each field being configured to store pixel data corresponding to an individual pixel; an instruction decoder configured to decode SIMD instructions from a predetermined SIMD instruction set, the predetermined SIMD instruction set including at least a splice instruction, an averaging instruction and a half subtraction instruction, the splice instruction combining pixels from a single row to generate a pixel matrix having more than one row; an arithmetic-logic unit configured to perform operations corresponding to the decoded SIMD instructions on each of the plurality of registers, each operation being simultaneously performed on each field in a register without causing carry bits to bleed from one field in the register to an adjacent field in the register; an I/O unit configured to interface with at least one external device and configured to receive data from and transmit data to the external device; and a data bus configured to interconnect the plurality of registers, the arithmetic-logic unit and the I/O unit.