1. A logic synthesis device for LSI comprising: a logic description information file for storing, for said LSI having a configuration with a plurality of hierarchical blocks given through hierarchical design, logic description information in a certain design description language describing logic operation contents of said LSI for each of said hierarchical blocks; a block placement information file for storing information about location and area on LSI of the hierarchical blocks constituting said LSI; a library file for storing the correspondence information between the logic operation contents described in said logic description information and the logic gate circuits physically realized on said LSI; and logic synthesis means for making logic synthesis in each of said hierarchical blocks and between said hierarchical blocks based on said logic description information and said correspondence information and adjusting the delay time between said hierarchical blocks based on said block placement information.