1. A processor system, comprising: a first processor chip comprising a first processor, the first processor having a first set of state registers; a second processor chip comprising a second processor, the second processor having a second set of state registers corresponding to the first set of state registers, wherein the first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips, and a mode control circuit to selectively operate the processor system in one of a plurality of operating modes, wherein in a first mode of operation, the first processor is active and the second processor is inactive, and wherein first processor operates at a speed greater than a maximum safe speed of the first processor, and wherein the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor contained in the first set of state registers.