1. A domino CMOS logic circuit, operable on a succession of precharge and evaluation phases of a clock sequence, including a dual gate having first and second logic gate sections which are logic duals of each other, the first and second sections having first and second mutually complementarily interconnected arrays, respectively, of driver transistors that are respectively connected for receiving mutually complementary first and second sets, respectively, of logic input signals, whereby during each evaluation phase the first and second sections generate first and second outputs, respectively, that are the inverse of each other.