1. A system for automatic verification of a test plan for a software model of a semiconductor device, said system comprising: a test plan database for storing test plan items relating to said test plan; a monitor generator for generating monitors for characteristics of said software model, each monitor corresponding to a verification event according to one of said test plan items; a modeling environment for processing said software model and said monitors and generating verification events; and an evaluator for comparing said verification events and said test plan items and updating said test plan database.