1. A data processor with register file indexing comprising: an instruction sequencer and N execution units capable of executing up to N instructions in parallel; a plurality of register files with registers which contain data operands read and written by the N execution units, each register file having read ports to and write ports from the N execution units; and read and write ports associated with each execution unit which have associated control circuitry and register file index (RFI) control registers which control the selection of a first addressing approach and a second indirect addressing approach and allow registers to be addressed using both a the first addressing approach in which fields of an instruction word made available to a particular execution unit directly specify addresses, and a the second indirect addressing approach in which the contents of register file index look ahead registers are utilized in specifying the addresses.