1. A processor, including an arithmetic logic unit and a microinstruction control store, comprising: a first register connected to be loaded solely from said arithmetic logic unit with a first micro-address word segment that forms a base number portion of a microinstruction address; a second register, connected to be loaded solely from said arithmetic logic unit with a second micro-address word segment that forms an offset number portion of a microinstruction address; means for adding said first and second micro-address word segments together to form a microinstruction address; and means responsive to said adding means for addressing said microinstruction control store to access a microinstruction which directly operates the hardward of said processor.