1. An integrated circuit comprising clock input means for receiving a primary clock signal, clock reconfiguring means fed by said clock input means for generating one or more secondary reconfigured clock signals, and utility circuitry fed by said clock reconfiguring means for constituting application utility functions under synchronization by said secondary clock signals, being characterized in that said clock input means comprise clock upscaling means for from said primary clock signal generating an intermediate clock signal with an upscaled frequency for thereby feeding said clock reconfiguring means, said clock reconfiguring means comprising late-programmable and low power memory means driven by said intermediate clock signal for generating said secondary reconfigured clock signals as wave-shape patterns read-out from a plurality of separately and sequentially drivable memory locations.