1. A data processing apparatus comprising a central processing unit formed in a single IC chip for comparing data, arithmetically processing data and branching data, said central processing unit including a memory including a plurality of addressable memory locations, and at least two general register sets, each of said general register sets comprising a plurality of associated general registers for storing a program counter, a program status word, and data, and a general register set pointer for designating any of said general register sets, each of said general registers of each of said general register sets having a first address to be designated when said general register set pointer designates said associated general register set and a second address to designate a memory location used as a work area when said general register set pointer designates the other of said general register sets, said general register sets including at least one common general register for storing data associated with either of said general register sets, and means for addressing said common general register to store data therein.