1. A method for managing instruction buffer resources in a processor of a computer system, comprising: storing a first instruction stream corresponding to a more likely path of a branch instruction in a first portion of an instruction buffer; storing a second instruction stream corresponding to a less likely path of the branch instruction in a second portion of the instruction buffer; within a control circuit responsive to a branch prediction unit of the processor, calculating a measure of branch prediction confidence for a instruction thread; and from a control circuit within the processor that is responsive to the calculated measure of branch prediction confidence, setting a size of the first portion of the instruction buffer and setting a size of the second portion of the instruction buffer in conformity with the measure of branch prediction accuracy.