1. A memory device comprising: a FAMOS (Floating-Gate Avalanche-Injection MOS) memory location having a floating gate overlapping an active surface of a semiconductor substrate with at least two asymmetrical overlap profiles, so as to define at least two electrodes in an active region; and a programming means capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the FAMOS memory location.