1. A programmable processor comprising: (a) an instruction path and a data path; (b) an external interface operable to receive data from an external source and communicate the received data over the data path; (c) a register file comprising a plurality of registers coupled to the data path; and (d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the group data handling instructions comprising a plurality of swap instructions that each operates on variable-size segments of data in an operand register, each segment consisting of a plurality of data elements, each swap instruction reversing the order of the plurality of data elements within each segment within the operand register, to produce a catenated result returned to a register in the register file.