1. A method for fabricating a non-volatile memory cell structure, comprising: providing a substrate having thereon a tunneling oxide layer, a floating gate layer and a dielectric layer; etching the floating gate layer and the dielectric layer in order to define two floating gates; forming a plurality of spacers on sidewalls of the floating gates; oxidizing the substrate to grow a control gate oxide layer between the two floating gates and split gate oxide layer on an outer side of each of the two floating gates; implanting ions into the substrate to form a drain between the two floating gates; depositing a gate layer over the substrate, the gate layer covering the dielectric layer and the spacers; forming a mask on the gate layer, the mask being disposed over the drain; and etching the gate layer to form a control gate over the drain using the mask and simultaneously form a split gate at the outer side of each of the two floating gate in a self-aligned manner, wherein the split gate is opposite to the control gate.