1. A processor comprising: logic configured to cause a software transactional memory access corresponding to a thread to be performed after a preceding hardware transactional memory access corresponding to the thread fails to be performed; a transaction descriptor register configured to store a value corresponding to the software transactional memory access; and a memory configured to store one or more ownership flag bits to identify an ownership status of a corresponding memory entry, wherein the one or more ownership flag bits contains a value copied from the value stored at the transaction descriptor register, and wherein the hardware transactional memory access is to be aborted in response to a determination-that the ownership flag indicates a valid ownership status.