1. A computer-implemented method for electronic design verification comprising: receiving, using a processor, an electronic design at a verification environment; generating a symbolic constant for use with the electronic design and the verification environment, wherein the symbolic constant is assigned an arbitrary value for use throughout a verification process; identifying a plurality of X sources associated with the electronic design and the verification environment; modifying the plurality of X sources based upon, at least in part, the symbolic constant; running a first target node associated with the electronic design and the verification environment; if the first target node is proven, running at least one additional target node until all target nodes are proven; if the first target node is a failure, fetching a symbolic constant value from a counter-example; and generating an integrated circuit after all target nodes are proven.