1. A multi-level non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines; a plurality of word lines insulatively intersecting said bit lines; a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second,. .. , (n−1)th and nth (n≧3) predetermined storage levels; a plurality of programming control circuits coupled to said memory cell array for storing data of first, second,. .. , (n−1)th and nth predetermined logic levels in data storage portions which define write voltages to be applied to respective of said memory cells, for applying said write voltages to said respective of said memory cells according to the data stored in said data storage portions, for determining actual written states of said memory cells, for modifying stored data from said ith (i=2, 3,. .. , n−1, n) predetermined logic level to said first predetermined logic level in the data storage portions storing the data of said ith (respectively, i=2, 3,. .. , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3,. .. , n−1, n) predetermined storage level has been determined, for maintaining said stored data at said ith (i=2, 3,. .. , n−1, n) predetermined logic level in the data storage portions storing the data of said ith (respectively, i=2, 3,. .. , n−1, n) predetermined logic level and corresponding to the memory cells in which it has been determined that said ith (respectively, i=2, 3,. .. , n−1, n) predetermined storage level has not been successfully written, and for maintaining said stored data at said first predetermined logic level in the data storage portions storing the data of said first predetermined logic level.