1. A circuit arrangement, comprising: a vectorizable floating point unit including a plurality of processing lanes; control logic coupled to the vectorizable floating point unit and configured to selectively operate the vectorizable floating point unit in vector and scalar modes, wherein in the vector mode, the control logic is configured to operate the plurality of processing lanes collectively as a single instruction multiple data (SIMD) execution unit, and in the scalar mode, the control logic is configured to operate the plurality of processing lanes as separate scalar execution units; and a register file coupled to the vectorizable floating point unit, wherein in the vector mode, the register file is partitioned into a first plurality of registers, and in the scalar mode, the register file is partitioned into a second plurality of registers that is different from the first plurality of registers, and wherein the control logic is configured to cause the register file to be flushed in response to a mode switch between the vector and scalar modes.