1. A microprocessor including an operator dedicated to a concatenation of variable-length codes to form a sequence of contiguous codes, the operator being associated with a dedicated instruction using two parameters, a first one of which is a word containing a group of bits and the second one of which indicates a length of the group of bits, the operator responding to the dedicated instruction by isolating, in the first parameter, the group of bits having the length indicated by the second parameter and by inserting the bit group so isolated into an active register, in concatenation with a bit group which has been inserted in the active register by a previous execution of the dedicated instruction.