1. A method for performance and power optimization of an instruction class adaptable pipeline processor, the method comprising: programming the instruction class adaptable pipeline processor to create an application program containing class one instructions each executable with a first latency in a class one pipeline and class two instructions each executable with a second latency in a class two pipeline, wherein the first latency is shorter than the second latency; modifying one or more class one instructions by changing, for each class one instruction to be modified, an encoding of the class one instruction to specify the same functionality of the original class one instruction is to be executed with the second latency to minimize power use while still meeting performance requirements and to create a modified application program; and executing the modified application program on the instruction class adaptable pipeline processor.