1. A processor, comprising: fetch logic adapted to fetch a set of instructions from memory, said set comprising a subset of instructions; decode logic coupled to the fetch logic and adapted to process the set of instructions; and a clock coupled to the decode logic; wherein, when processed, an instruction from the set causes the clock to increment a counter external to the processor while the subset is processed; wherein a status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.