1. A video signal processor comprising: (a) first and second storage means for storing plural items of pixel data, (b) an address generator for generating a write address of said first storage means in order that pixel data obtained by sampling a video signal is sequentially written in said first storage means in synchronism with a synchronizing signal, and a read address of said second storage means in order that pixel data is sequentially read out of said second storage means in synchronism with said synchronizing signal, and (c) processing means for reading the pixel data from said first storage means, processing said read pixel data, and writing said processed pixel data in said second storage means, at an operating frequency higher than a sampling rate of said video signal.