1. A scan/bist technique test apparatus for at-speed testing a multi-clock-domain digital integrated circuit including at least a scan chain and combinational logic in each clock domain, configured to use an external automatic test equipment and an automatic test pattern generator software tool of automatic-test-pattern generation in an inter-domain mode for detecting time-related faults, the apparatus comprising a) internal clock generators of different clocks at the frequency of operation of the different clock domains; b) a dedicated clock sourcing logic circuit for each clock domain, adapted to deliver test clock pulses originating from external ATE according to the pattern generated by the automatic test pattern generator tool, and from internal clock generators, to the scan chains of the respective clock domain; c) a controller circuit interfaced with every clock sourcing logic circuit of the different clock domains and adapted to deterministically synchronize the different clock sourcing circuits with said externally generated test clock pulses.