1. A processor, comprising: a cache to store instructions; an instruction decoder to decode the instructions; a set of 128-bit packed data registers to store packed data elements and packed integer data elements; an execution unit comprising: comparison circuitry to execute a packed instruction to: compare a first packed data element and a second packed data element and to responsively set at least one bit in a register to indicate a result of the packed comparison; compare a first packed integer data element and a second packed integer data element and to responsively set the at least one bit in the register to indicate a result of the packed integer comparison; and determine a target code location based on the at least one bit set in the register.