1. A content addressable memory (CAM) device, comprising: a CAM array including a plurality of rows, each row including a number T of quaternary CAM cells coupled to a match line; and a programmable write circuit coupled to the CAM array and configured to selectively store, within each CAM cell of a selected CAM row, either a single data bit of a first data word or two data bits of an encoded data word, wherein none of the data bits are mask bits.