1. An integrated circuit for an interface in which packets are transferred between a network medium and a host bus system, the integrated circuit comprising: a medium access control (MAC) unit through which data is transferred; a port coupled with the host bus system, through which data is transferred to and from the host bus system; buffer memory, coupled to the MAC unit and the port, storing packets in transit between the network medium and the host bus system; and logic, coupled with the buffer memory, to store a rule parameter, to access data fields in packets stored in the buffer memory, and to perform a logic function based on the accessed data fields and on the rule parameter that produces a result used to determine a priority for transfer of corresponding packets out of the buffer memory.