1. A system comprising: a non-volatile memory coupled to a bus through an interface configured to receive memory access addresses to the non-volatile memory from the bus and to output data from the non-volatile memory to the bus; and a low power DRAM (LPDRAM) memory device coupled to the bus; wherein the non-volatile memory is adapted to configure the LPDRAM memory device by, configuring the LPDRAM memory device with a controller of the non-volatile memory; wherein the controller is between a memory array of the non-volatile memory and its interface.