1. A method performed by logic circuitry disposed on a card having a connector to plug into a memory channel that supports near memory cache accesses and far memory accesses, comprising: receiving from said memory channel a first tag component of a target address of a read request transaction being processed by a host that is coupled to said memory channel; receiving a second tag component of an address of a cache line read from a near memory cache in response to said read request transaction; and, comparing said first and second tag components to determine if said cache line corresponds to a cache hit or a cache miss.