1. An integrated circuit (IC) design method, intended for reducing IC power consumption by the efficient identification and implementation of register clock gating in an IC design, comprising: identifying candidate registers to be clock gated; and for each of the candidate registers: determining an output function of the candidate register; determining one gating condition for the candidate register; determining at least one hold expression for the candidate register; and based on the result of the determining of the output function, the gating condition, and the hold expression, clock gating the candidate register.