1. An integrated circuit, comprising: an execution unit capable of executing a program subdivided into phases, each phase having at least one or more cache access operations to fetch data from a cache to process two or more samples; and execution control logic configured to constrain the concurrent execution of cache access operations from different phases in the program while permitting concurrent execution of math operations in different phases of the program, wherein the execution control logic is configured to detect when a boundary between a current phase and a subsequent phase is reached, and to allow operations in the current phase to continue executing while preventing the execution of cache access operations in the subsequent phase until all cache access operations in the current phase have completed.