1. A multi-thread processor that has a plurality of hardware threads for generating a plurality of mutually independent instruction streams, respectively, and a scheduler for specifying the hardware thread that is to be performed next among the hardware threads, wherein the scheduler performs thread scheduling of repeating to specify each hardware thread included in a first group among the hardware threads by the number of times set up in advance for the hardware thread and to specify any one of the hardware threads in a second group by the number of times set up in advance for the second group that includes other hardware threads, and wherein when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs the rescheduling of respecifying the hardware thread in the second group instead of the hardware thread.