1. A coprocessor for use in a computer system having a host processor, a plurality of said coprocessors and a like plurality of data memories wherein each of said plurality of coprocessors is coupled to said host processor for the receipt of instructions, control signals and data and each of said plurality of coprocessors is coupled to a respective one of the data memories, said coprocessor comprising: (a) means, responsive to the control signals, for enabling said coprocessor to respond to instructions and data in one of a plurality of instruction execution modes, said enabling means distinguishing between instruction execution modes wherein said coprocessor responds to instructions and data singularly with respect to others of said coprocessors and wherein said coprocessor responds to instructions and data in parallel with others of said plurality of coprocessor; and (b) means, coupled to said host processor for receiving instructions and data, for executing instructions received with respect to data provided with the instruction and as present in the respective one of the data memories, said executing means including: (i) means for storing data, said executing means being responsive to the data stored by said storing means and the instruction execution mode enabled by said enabling means for qualifying the execution of instructions by said executing means; and (ii) means for communicating interim result information with others of said plurality of coprocessors when executing an instruction in parallel with others of said plurality of coprocessors, said communication means providing a interim result control signal upon reaching a decision point in the execution of an instruction indicative of the interim results of the execution of said instruction and being responsive to a consensus control signal representing the consensus result of said plurality of coprocessors executing said instruction in parallel at said decision point in the execution of said instruction.