1. A method comprising: receiving a design identifying operations to be performed by a programmable logic device (PLD); synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises: identifying a multiplexer in the design, wherein operation of the multiplexer is controlled by select logic over one or more select lines, identifying one or more irrelevant inputs for the multiplexer by, at least in part, decomposing the select logic into one or more select line binary decision diagrams (BDDs) corresponding to the one or more select lines, and generating a reduced multiplexer by eliminating the one or more irrelevant inputs from the multiplexer to reduce the plurality of PLD components; generating configuration data to configure physical components of the PLD in accordance with the reduced multiplexer for the design; and storing the configuration data in a machine-readable memory.