1. A processor system comprising a processing unit with a predetermined instruction set; at least one predicate register, the predicate register comprising a number N of predicate data locations being arranged in a predicate data structure, each predicate data location being adapted to store predicate data; at least one general purpose register, the general purpose register comprising additional predicate data locations, the additional predicate data locations being arranged in a number M−1 of additional predicate data containers, wherein a data structure of each additional predicate data container corresponds to the predicate data structure, wherein each additional predicate data location is adapted to store additional predicate data; a data pathway for transmitting data between the at least one predicate register and the general purpose register, wherein at least one predicate storage location is connected or connectable via the data pathway to at least one corresponding additional predicate data location; wherein the processor system is adapted to carry out a predicate swap instruction of the instruction set to swap, via the data pathway, predicate data in a first predicate data location with data in a corresponding additional predicate data location in a first additional predicate data container and to swap, via the data pathway, predicate data in a second predicate storage location with data in a corresponding additional predicate data location in a second set of additional predicate data.