1. A microprocessor, comprising: a branch unit to process branch instructions and provide a fetch unit with a next instruction address; a load/store unit (LSU) to retrieve data from and stored data to a data memory of the microprocessor; an arithmetic logic unit (ALU) to performing arithmetic operations on scalar, integer data; a vector unit to execute a vector instruction, wherein the vector unit includes a vector register file having a primary vector register and a secondary vector register; a first data bus and a second data bus wherein the first and second data busses both couple the vector unit to the data memory; and a first input multiplexer enabling data on the first data bus to be provided to the primary register file or the secondary register file and a second input multiplexer, independent of the first input multiplexer enabling data on the second data bus to be provided to the second data bus.