1. Apparatus for processing data, said apparatus comprising: a physical set of registers; register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for processing instructions of said instruction set; and available-register identifying circuitry, responsive to a current state of said apparatus, for identifying which physical registers of said physical set of registers are available to be mapped by said register renaming circuitry to a register specifier of an instruction to be processed; wherein said available-register identifying circuitry includes an instruction memory for storing register mapping data indicative of register mappings used by instructions that are issued so as to identify physical registers storing values still required for at least some outcomes of said issued instructions, said register mapping data for one of said issued instruction is kept in said memory if said one of said issued instructions is an unresolved speculative instruction and is kept in said memory if said one of said issued instructions is an instruction which is yet to read one or more registers.