1. A processor comprising: a plurality of program counters; one or a plurality of instruction execution parts; and means for selectively supplying for a plurality of threads instruction flows to said one or a plurality of instruction parts, each of said threads corresponding each of said program counters, wherein said threads can be executed either simultaneously or in time multiplex, wherein said processor has changeable execution priorities among said threads in time multiplex and generates the same result as serial execution according to said priorities would generate.