1. An integrated circuit active memory device comprising: a command engine operable to generate either respective sequences of array control unit commands or respective sequences of memory device control unit commands responsive to respective task commands applied to a task command input of the command engine; an array control unit coupled to receive the array control unit commands from the command engine, the array control unit being operable to generate a respective sequence of processing element instructions responsive to each of the array control unit commands; a memory device control unit coupled to receive the memory device control unit commands from the command engine, the memory device control unit, being operable to generate a respective sequence of memory commands responsive to each of the memory device control unit commands; a decode memory device coupled to receive the processing element instructions from the array control unit, the decode memory device storing a plurality of processing element microinstructions and being addressed by the processing element instructions such that each of the processing element instructions accesses a location in the decode memory device where a respective processing element microinstruction is stored, each of the processing element microinstructions having a number of bits that is greater than the number of bits in the processing element instructions; a memory device having a data bus containing a plurality of data bus bits, the memory device being operable to receive the memory commands and couple write data to and read data from the memory device through the data bus; and an array of processing elements each of which is coupled to a respective group of the data bus bits of the memory device data bus, each of the processing elements having an instruction input coupled to receive the processing element microinstructions from the decode memory for controlling the operation of the processing elements.