1. A demultiplexer for a hybrid nanodevice/CMOS system comprising a layer of parallel nanowires extending to a nanodevice crossbar and a layer of parallel microwires, where each nanowire of the layer of parallel nanowires is configured to overlap each microwire of the parallel microwires, the demultiplexer comprising: a resistor-logic demultiplexer region comprising resistors configured to selectively connect nanowires to microwires; and a pFET array for converting an output of the resistor-logic region to a non-linear input to the nanodevice crossbar, the pFET array comprising one pFET along each of the nanowires.