1. A programmable logic device comprising: a plurality of configuration memory cells; at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells; a plurality of bitlines; a plurality of wordlines; an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines; and a data shift register adapted to provide configuration data to the plurality of configuration memory cells via the bitlines and further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.