1. A method of data processing in a data processing system having a system memory controlled by a memory controller, said method comprising: receiving, by the memory controller, a plurality of data prefetch requests from multiple processor cores in the data processing system, the plurality of data prefetch requests including a data prefetch request issued by a particular processor core among the multiple processor cores, wherein the data prefetch request requests all of multiple data granules within a target line of data; in response to receipt of the data prefetch request by the memory controller, providing, by the memory controller, a coherency response indicating an excess number of data prefetch requests and providing data from the target line of data to the particular processor core, wherein providing data from the target line includes the memory controller providing fewer than all of the multiple data granules of the target line based on scheduling of demand requests by the memory controller, and wherein the coherency response to the data prefetch request is a partial response representing the coherency response of only the memory controller; in response to receipt of the partial response, generating, by coherence management logic within the data processing system, from the partial response and from one or more other partial responses of components of the data processing system, a throttle combined response representing a system-wide coherency response of the data processing system, wherein the throttle combined response is indicative of the excess number of data prefetch requests; and in response to the throttle combined response, reducing, by the particular processor core, a rate of issuance of data prefetch requests.