1. A system on chip (SoC) including a special function register (SFR), wherein the SFR comprising: a first update storage element; a second update storage element; a first update logic corresponding to the first update storage element; and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.