1. A semiconductor memory cell comprising an electrically floating body transistor including: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region and separated therefrom by a gate dielectric; and wherein the memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the gate.