1. A processor for retrieving a data transfer instruction in a cache memory as a combination of instructions comprising: a memory transfer routine detection unit detecting a combination of instructions indicating a memory transfer process in the cache memory from a sequence of instructions by checking instruction codes and operand codes in the sequence of instructions to be executed; and a memory transfer unit executing the data transfer process in the cache memory, wherein the combination of instructions detected by the memory transfer routine detection unit is allocated to the memory transfer unit for execution.