1. A multiprocessor system to facilitate fault isolation test upon one of its processors by another comprising: a first, second, and third memory each having a plurality of memory address locations for storing a plurality of instructions and data; a first and second digital processor, each said processor operative to execute instructions and operate upon data stored in at least one of said memories, each said processor having an input/output port responsive to control signals including halt, initiate, clear and interrupt commands, and at least one port for transferring data and instructions; a transfer switch coupled to each of said memories and processors for transferring instructions and data between said memories and said port of said first and second processors, said transfer switch including means for switching said third memory in place of said first memory in response to a memory switching command signal and for causing said first memory at times when replaced by said third memory to be inaccessible by said first and second digital processors to protect the integrity of the information stored in said first memory; said means for switching includes means for addressing said third memory by an address directed to said third memory and by an address directed to said first memory at times when replaced by said third memory, said transfer switch including means for protecting the information in said second memory in response to a memory protection command signal while permitting information to be read from said second memory; an input/output means coupled to said input/output port of said first and second processors for receiving, decoding and generating initiate, halt, clear and interrupt command signals and for receiving and decoding "who am I" identification request, memory switching and memory protection command signals, said input/output means coupled to a control input of said transfer switch for providing memory switching and memory protection command signals.