1. A system for providing asynchronous dynamic millicode entry prediction in a processor, the system comprising: a branch target buffer (BTB) to hold branch information, wherein the branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction; search logic performing a method comprising: locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine; and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC; and instruction fetch controls (IFC) to fetch instructions of the millicode subroutine asynchronous to the search logic.