1. A hardware processor comprising: a decode unit to decode a vector instruction with a register operand with an elemental offset to: access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset; access a second number of elements in a next register, wherein the second number is the elemental offset; and combine the first number of elements and the second number of elements as a data vector; and an execution unit to execute the vector instruction on the data vector.