1. An integrated circuit comprising: a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than five; said two dimensional pyramid filter architecture of order 2N−1, in operation, capable of producing, on respective clock cycles, at least the following: pyramid filtered output signals corresponding to output signals produced by fourteen one-dimensional pyramid filters of order 2N−1; and pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order &lsqb;2(N−1)−1&rsqb; using signal sample matrices of order &lsqb;2(N−1)−1&rsqb;; wherein the respective output signals in said two dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.