1. A processor comprising: a control circuit configured to assign a first tag to a branch instruction, and wherein the control circuit is configured to assign a second tag to a second instruction in a branch delay slot of the branch instruction, wherein the second tag is equal to either the first tag or a different tag dependent on a type of the branch instruction; and a pipeline coupled to receive the second instruction and the second tag, and further coupled to receive the first tag if the branch instruction is mispredicted, wherein the pipeline is configured to selectively cancel the second instruction responsive to values of the first tag and the second tag.