1. A specialized processing block for a programmable logic device, said specialized processing block comprising: a plurality of fundamental processing units, each of said fundamental processing units including: a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product of said respective pair of inputs; compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; circuitry for shifting said partial products represented by said smaller number of vectors prior to adding them; and circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by no fewer than all of said plurality of partial product generators; wherein: said circuitry for adding outputs only a sum of all partial products of all of said plurality of partial product generators; and each said respective partial product is unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products having said different inputs.