1. A processor comprising: a decoder to decode a load_check instruction; and an execution unit to execute the load_check instruction, wherein execution of the load_check instruction is to cause at least one user-configurable attribute bit stored in a cache line to be read from the cache line and compared with an expected value, wherein if the at least one user-configurable attribute bit does not equal the expected value, the load_check instruction is to cause a light-weight yield to occur and an event handler to be invoked upon detection of an unexpected memory coherency state, wherein the at least one user-configurable attribute bit is to indicate whether a thread of a multi-threaded program may access information stored in the cache line and whether the thread may modify the at least one user-configurable attribute bit.