1. A computer-implemented method comprising: inputting at least one user-supplied assertion; selectively generating and skewing clocks to convert user-supplied unclocked assertions to clocked assertions for each of a plurality of different verification tools, wherein at least one of the verification tools evaluates analog assertions; generating a stimulus; synthesizing a test bench; using different simulators, for each verification tool, simulating the test bench and capturing simulation results; evaluating result differences between the different verification tools with an assertion status difference engine that compensates for output differences in timing and syntax; and identifying and outputting differences indicating an inconsistency between the different verification tools; wherein the inconsistency is from a verification tool implementation error.