1. A test device for generating algorithmic test patterns comprising: an ALU unit with shift-in means for generating and storing algorithmic test patterns by conducting predetermined arithmetic and logic operations on input data to said ALU unit; parity detection means for generating a parity detection bit from selected parity bits of said algorithmic test patterns generated by said ALU unit, said parity detection bit is input into said ALU unit for providing said shift-in means; and selection means for selecting between input reference data and said algorithmic test patterns from said ALU unit, said selecting means provides said input data to said ALU unit.