1. A computer implemented method of instrumentation of an electronic design, comprising: receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, at least one digital portion and at least one analog portion; generating at least one instrumented netlist based at least in part upon said representation of said electronic design; receiving at least one specification of said electronic design; generating at least one set of valid states based on said at least one specification; receiving at least one verification coverage history of said electronic design; correlating said at least one verification coverage history and at least one input vector; and assessing completeness of verification based at least in part upon at least one of said at least one specification, said at least one instrumented netlist, said at least one set of valid states and said at least one verification coverage history.