1. A method for simulating and verifying a design under test (DUT) on a computer comprising a first and second processor, the method comprising: executing a simulation kernel on the first processor, thereby causing the first processor to: notify an assertion engine executing on the second processor that a simulation time slot has begun; simulate changes in signal values of the DUT during the simulation time slot; and wait for the assertion engine executing on the second processor to evaluate assertions corresponding to the DUT on the second processor; and executing an assertion engine on the second processor, thereby causing the second processor to: in response to receiving a notification from the simulation kernel executing on the first processor that the simulation time slot has begun, evaluate the assertions corresponding to the DUT using signal values which were determined during previous simulation time slots; and notify the simulation kernel executing on the first processor that the assertions have been evaluated.