1. A circuit comprising: a first cache configured to store translations between address domains, the cache including first and second logical portions, the first logical portion configured to store translations between a first address domain and a second address domain, the second logical portion configured to store translations between the second address domain and a third address domain; a second cache configured to store translations between the first address domain and the third address domain based on entries in the first cache; a third cache configured to store tags associated with the translations of the first and second cache; and a processor configured to detect a deleted entry in at least one of the first logical portion and the second logical portion and invalidate corresponding entries in the second and third caches.