1. A processor that cyclically executes a plurality of threads, wherein an operation is executed in each of the threads repeatedly, the operation being performed by a predetermined number of operation cells one by one in a sequential order, the predetermined number being different for each thread, and the processor comprising: an operation circuit having a plurality of operation cells whose configurations and connections therebetween are reconfigurable; a reconfiguration unit operable to reconfigure one of the operation cells, based on a piece of configuration information; a configuration information storing unit that stores therein configuration information sets that correspond one-to-one with the threads, and that each include a plurality of pieces of configuration information corresponding one-to-one with the operation cells; a control unit operable to (i) cause the reconfiguration unit to sequentially reconfigure each operation cell that has a configuration for a current thread when the operation cell has completed a last operation thereof in the current thread, based on a piece of configuration information corresponding to the operation cell that has completed the last operation, the piece of configuration information being in the configuration information set for a next thread, and (ii) cause concurrent execution of an operation cell having a configuration for the current thread and an operation cell having a configuration for the next thread.