1. A method of effecting transfers to and from subroutines and interrupt service routines comprising the steps of: A. generating a first microinstruction of a routine from a memory which identifies a branch to subroutine; B. executing a branch to a subroutine; said branch executing step including: a. inhibiting the occurrence of inhibitable interrupts, b. transferring a current address of said first microinstruction in a current address register to an incrementer, c. incrementing said current address to produce an incremented address, d. storing said incremented address, which is a return address, in a first register of a push-down stack, e. transferring previous return addresses into adjacent registers one level down in said push-down stack simultaneous with the storing of said incremented address, f. transferring a next address in said first microinstruction into a next address register if no interrupt is pending or if all pending interrupts are inhibited, g. transferring said next address in said next address register into said current address register, and h. generating a second microinstruction, which is a first microinstruction of a subroutine, from said memory using said next address from said next address register, C. generating an interrupt to an interrupt service routine, said interrupt generating step including: a. generating a vectored interrupt address of a highest priority non-inhibited pending interrupt if a pending non-inhibited interrupt exists, b. transferring said vectored interrupt address into said next address register if interrupts are not inhibited, c. storing a next address from a current microinstruction, which is said return addresss, into said first register of said push-down stack if interrupts are not inhibited, d. transferring previous return addresses into adjacent registers one level down in said push-down stack simultaneous with the storing of said return address, e. transferring said vectored interrupt address in said next address register into said current address register, and f. generating a third microinstruction, which is a first microinstruction of a first interrupt service routine, from said memory using said vectored interrupt address from said next address register, D. generating a microinstruction from said memory which identifies a return from said subroutines or said interrupts; and E. executing a return from said subroutines or interrupts, said return executing step including: a. transferring said return address from said first register in said push-down stack to said next address register if no interrupts are pending or if all pending interrupts are inhibited, b. transferring previous return addresses into said adjacent registers one level up in said push-down stack simultaneous with said transferring said return address to said next address register, c. generating said vectored interrupt address of said highest priority non-inhibited pending interrupt if a pending non-inhibited interrupt if a pending non-inhibited interrupt exists, d. transferring said vectored interrupt address into said next address register if interrupts are not inhibited, and e. generating a fourth microinstruction, which is a subsequent microinstruction to the microinstruction which branches to a subroutine, if no non-inhibited interrupts are pending, or a first microinstruction of a subsequent interrupt service routine if said pending non-inhibited interrupt exists, from said memory using an address from said next address register.