1. A processor whose architecture comprises: an instruction data pipeline comprising multiple data pipeline stages, each data pipeline stage corresponding to a discrete set of processing for a program instruction, the multiple data pipeline stages connected in series to provide start to finish processing data for the program instruction by propagating instruction data corresponding to the program instruction through the multiple data pipeline stages of the instruction data pipeline; a digital signal processor (DSP) configured to sequentially load a first data pipeline stage of the instruction data pipeline with instruction data from program instructions in different programs from a set of multiple interleaved programs such that at any instant in time at least one of the multiple data pipeline stages is loaded with instruction data corresponding to another program instruction from one of the multiple interleaved programs and at least another one of the multiple data pipeline stages is loaded with instruction data corresponding to another program instruction from a different one of the multiple interleaved programs; and a machine state pipeline comprising multiple machine states, each machine state configured to store state data relating to a corresponding one of the multiple data pipeline stages, the machine state pipeline configured to propagate the state data for each of the multiple data pipeline stages sequentially through the multiple machine states in synchronism with the corresponding instruction data as it propagates through the data instruction pipeline such that the propagation of the instruction data and corresponding machine states through the data instruction pipeline and machine state pipeline results in the execution of one of the program instructions of one of the multiple interleaved programs.