1. A processor comprising: a) an instruction decode circuit having an address output, the instruction decode circuit being configured to determine an address specified by an instruction and to provide the specified address at the address output of the instruction decode circuit; b) a rename circuit having 1) an address input coupled to the address output of the instruction decode circuit, and 2) an address output, the rename circuit comprising: i) a counter configured to count a number of times the instruction decode circuit has consecutively decoded the instruction; ii) an arithmetic circuit having 1) a first input coupled to the address input of the rename circuit, 2) a second input coupled to the counter, and 3) a renamed output, wherein the arithmetic circuit is configured to provide at the renamed output a renamed value representing: the specified address received from the address output of the instruction decode circuit via the address input of the rename circuit, added to a value stored in a first register, the value being indicative of a number of vector iterations that have been completed prior to a current vector run, and offset by an amount that is based on a number of times the processor, while operating in a vector mode, has executed the instruction during the current vector run; iii) a switching circuit having 1) a first input coupled to the address input of the rename circuit, 2) a second input coupled to the renamed output of the arithmetic circuit, 3) a control input, and 4) an output coupled to the address output of the rename circuit, wherein the switching circuit is configured to selectively couple a value at the first input of the switching circuit or the renamed value at the second input of the switching circuit to the output of the switching circuit based on a value of the control input; and c) a data access circuit having an address input coupled to the address output of the rename circuit.