1. A method for automatic insertion and correctness verification of level shifters in a design of an integrated circuit (IC), wherein the IC comprises multiple voltage domains, the method comprising: specifying a plurality of voltage constraints, defining at least one pair of voltage domains in the design and at least one level shifter cell; for each pair of voltage domains, checking whether a signal crossing the voltage domains is connected to a level shifter; verifying the correctness in the design of an existing level shifter; generating a level shifter module for the crossing signal, when the crossing signal is not correctly shifted; and inserting the generated level shifter module in the design.