1. A method for optimized buffer placement based on timing and capacitance assertions in a functional chip unit comprising a single source and multiple macros, each having a sink, wherein the placement of the source and the macros with the sinks is pre-designed and the buffers are placed in branches connecting the source with the multiple sinks, the method comprising: calculating, by a processor, an estimated slack for each branch of the branches, arranging the branches according to the calculated slack to evaluate at least one most critical branch of the branches, inserting decoupling buffers in each branch of the branches except for the at least one most critical branch, wherein the inserted decoupling buffers are placed close to the source, globally routing the at least one most critical branch and fixing slew conditions within this branch, subsequently, globally routing at least one next branch of the branches as arranged according to the calculated slack and fixing slew conditions within this at least one next branch, wherein globally routing the at least one next branch comprises: performing an initial routing of the at least one next branch between the source and a sink of the at least one next branch, comparing a slack of the initial routing of the at least one next branch and a slack of the global routing of the at least one most critical branch to determine whether the slack of the initial routing of the at least one next branch is more critical than the slack of the global routing of the at least one most critical branch; based on determining that the slack of the initial routing of the at least one next branch is more critical than the slack of the global routing of the at least one most critical branch, performing re-routing of the at least one next branch between the source and the sink of the at least one next branch, wherein a portion of a replacement routing of the at least one next branch replaces a portion of the global routing of the at least one most critical branch, and wherein re-routing the at least one next branch comprises: identifying a point on the global routing of the at least one most critical branch for which minimum distance estimation, based on a Steiner tree construction, from the sink of the at least one next branch meets the global routing of the at least one most critical branch, removing a portion of the global routing of the at least one most critical branch between the source and the identified point, removing the initial routing of the at least one next branch, and based on a capacitance at the identified point and a capacitance at the sink of the at least one next branch, determining and routing the replacement routing extending between the source and the sink of the at least one next branch, via the identified point, and fixing slew conditions of the replacement routing, and routing at least one remaining branch of the branches.