1. An event alignment control circuit, the circuit comprising: a delay table, wherein the delay table includes at least a first register and a last register, and wherein the delay table is operable to transfer data from the first register to the last register; a flag write controller circuit, wherein the flag write controller circuit is operable to receive an indication of assertion of an event flag and to write information relevant to the event flag to the first register of the delay table; a signal reconstruction circuit, wherein the signal reconstruction circuit is electrically coupled to the last register, and wherein the signal reconstruction circuit is operable to reconstruct the event flag based at least in part on the information relevant to the event flag from the last register; a first processing circuit operable to process a first input derived from a data set based at least in part on the event flag, wherein the event flag is not part of the data set, and wherein the event flag is relevant to a defined portion of the first input; and a second processing circuit operable to process a second input derived from the data set based at least in part on the reconstructed event flag, wherein the reconstructed event flag is relevant to a defined portion of the second input.