1. A processing system operable in various execution environments comprising: plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs; a register coupled to at least one of the processor cores for identifying active execution environments; a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores; and a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.