1. A method for controlling the cycle-by-cycle interleaving of instructions between a number of instruction threads in a simultaneous multithreading processor, the method including the steps of: (a) receiving a first priority signal indicating a first base input processing priority associated with a first instruction thread included in the number of instruction threads; (b) receiving a feedback signal associated with one of the instruction threads; (c) adjusting the first base input processing priority to generate a first adjusted input processing priority in response to the feedback signal; and (d) applying an interleave rule to the first adjusted input processing priority and at least one other thread processing priority to generate a thread selection control signal for controlling the interleaving of instructions from the number of instruction threads.