1. A method of operating a multi-core processor, where each processor core is provided with its own private cache and access to a common memory, the method comprising: executing a processing thread on a selected first processor core for executing a compiled code that was generated from source code, wherein the source code comprises an explicit indication of an amount of second processor cores to process an operation, wherein the processing thread operates in a normal access mode and in a speculative execution mode switchable to override said normal access mode, wherein the processing thread, when in the normal access mode, performs the steps of: allocating sole responsibility for writing data to given blocks of said common memory to respective processor cores; identifying an explicit instruction within the compiled code to switch to said speculative execution mode for executing the operation; based on the identification of the explicit instruction, triggering a switch from said normal access mode to said speculative execution mode; after switching to speculative execution mode: identifying the amount of the second processor cores to execute the operation as indicated by the explicit instruction within the compiled code; transferring responsibility for performing said operation to the identified amount of second processor cores, including copying data from a given block of said common memory to the private cache of each of said second processor cores, wherein each of said second processor cores is allowed to modify the data in its own private cache without making changes visible to other processor cores; determining which of the second processor cores successfully performed said operation based upon a criterion specified in the compiled code derived from an election code segment of the source code; upon completion of said operation at the second processor cores, temporarily allocating sole responsibility for writing data to said given block of said common memory to the one of said second processor cores deemed to have successfully performed said operation; triggering a switch from said speculative execution mode to said normal access mode; and resuming execution of said processing thread at said first processor core in said normal access mode.