1. A processor comprising: an instruction fetch unit configured to fetch instructions of a computer program; a decoder coupled to receive instructions fetched by the fetch unit; and an execution unit coupled to the decoder; wherein the decoder is configured to: detect a received instruction comprises an opcode corresponding to a plurality of functions; and determine the computer program expects a particular one of the plurality of functions to be performed when the opcode is executed; wherein in response to determining hardware support exists to perform said particular one of the plurality of functions responsive to execution of the opcode, the execution unit is configured to execute the received instruction in order to perform said particular one of the plurality of functions.