1. A multiply-accumulate circuit comprising: bit-wise AND gate logic to receive an input operand having a plurality of bits, wherein the bit-wise AND gate logic includes a plurality of AND gates, each AND gate corresponding to a respective bit of the input operand and having a first input to receive the respective bit, a second input to receive a first control signal, and an output, wherein the outputs of the plurality of AND gates collectively form an output of the bit-wise AND gate logic; a partial product generator having a first input to receive, as a first operand, the output of the bit-wise AND gate logic, a second input to receive a second operand, and an output to output a partial product produced by the partial product generator based on the first and second operands; an adder tree having a first input to receive, as a third operand, the partial product supplied at the output of the partial product generator, a second input to receive a fourth operand, and an output to output a sum produced by the adder tree based on the third and fourth operands; an accumulator having an input and an output, wherein the accumulator is configured to store data received at the input and to output the stored data at the output, and wherein the input of the accumulator is coupled to the output of the adder tree, wherein the output of the accumulator is not coupled to the bit-wise AND gate logic; and a multiplexer having a first input to receive the output of the accumulator, a second input to receive external data, and an output, wherein the multiplexer is responsive to a second control signal to output a selected one of the first input or the second input at the output, wherein the output of the multiplexer is coupled to the second input of the adder tree and is supplied thereto as the fourth operand; wherein, when the multiply-accumulate circuit operates in a multiply-accumulate operation mode, the first control signal causes the bit-wise AND gate logic to pass each bit of the input operand unchanged, and the second control signal causes the multiplexer to output the first input as the fourth operand; and wherein, when the multiply-accumulate circuit operates in a load operation mode, the first control signal causes the bit-wise AND gate logic to pass a logic 0 for each bit of the input operand, the second control signal causes the multiplexer to output the second input as the fourth operand, and the sum produced by the adder tree is equal to the fourth operand and is loaded into the accumulator.