1. A semiconductor memory device comprising: a redundant memory cell for use instead of a memory cell when the memory cell has a defect; an electrode applied with a test signal for setting a test condition from outside in testing the redundant memory cell; and an output circuit for outputting data read out of the memory cell and the redundant memory cell, wherein when the test signal is applied to the electrode to set the test condition for the redundant memory cell, the output circuit is configured to output data read out of the redundant memory cell at a level different from a signal level of data read out of the memory cell for output.