1. A dynamic bipolar memory array comprising: a read line, a bit line, a pair of complementary transistors each having a base, a collector and an emitter, one of said pair of transistors being a read transistor having its emitter coupled to said read line, the other of said pair of transistors being a write transistor having its emitter coupled to said write line, the base of the write transistor being connected to the collector of the read transistor and to said bit line, the base of the read transistor being connected to the collector of the write transistor, and a storage node capacitor connected between the base of said read transistor and a fixed potential.