1. An integrated circuit memory comprising: a memory array of floating gate memory cells having control gates, floating gates, sources and drains; a plurality of bitlines, the plurality of bitlines arranged in a plurality of byte-wide sets of bitlines, each bitline coupled to the drains of a column of cells in the memory array; a plurality of wordlines, each coupled to the control gates of a row of cells in the memory array; a plurality of source lines, coupled to the sources of a plurality of cells in the memory array; pre-programming circuits, coupled to the plurality of bitlines and the plurality of wordlines, to apply a gate programming potential to a subset having more than one member of the plurality of wordlines, and a data-in programming potential to at least one of the byte-wide sets of bitlines to program a plurality of bytes of selected cells during a pre-programming interval; and erasing circuits, coupled to the plurality of wordlines and the plurality of source lines, to apply an erasing potential to a plurality of pre-programmed memory cells after the pre-programming interval.