1. A method for input/output (I/O) value determination at a processor core, comprising: generating an I/O instruction comprising at least a physical address; comparing the physical address from the I/O instruction with a database of physical addresses assigned to I/O devices and when the comparing is successful determining the I/O device or a state on the I/O device to receive the I/O instruction in accordance with the physical address; setting a value in a first register to a value identifying the determined I/O device or the state on the I/O device; predicting a value to be set in a second register in accordance with the physical address; and setting a value in a third register.