1. An electrical fuse (eFuse) memory array comprising: a plurality of eFuse bit cells, each eFuse bit cell of the plurality of eFuse bit cells having a program transistor, a read transistor, and an eFuse, one end of the eFuse is connected to the program transistor and the read transistor, and another end of the eFuse is connected to a program bit line and the read transistor is connected to a read bit line, wherein a first eFuse bit cell of the plurality of eFuse bit cells and a second eFuse bit cell of the plurality of eFuse bit cells share a first program bit line, wherein the first program bit line is coupled to an eFuse of the first eFuse bit cell and also coupled to an eFuse of the second eFuse bit cell and is positioned between the first eFuse bit cell and the second eFuse bit cell, a read bit line of the first eFuse bit cell is separate from a read bit line of the second eFuse bit cell, and the first eFuse bit cell is spaced from the second eFuse bit cell in a direction perpendicular to the first program bit line, wherein the program bit line is configured to carry a current sufficient to program the eFuse, and wherein the first eFuse bit cell need not store the logical complement of the data stored in the second eFuse bit cell.