1. An out-of-order execution hardware microprocessor for reducing a likelihood of having to replay a load instruction due to a store collision, the hardware microprocessor comprising: a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies a dependee instruction upon which the store instruction depends for its data; and a register alias table (RAT), coupled to the queue of entries, the RAT configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, wherein in response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction by making an issuing of the load instruction dependent upon the dependee instruction.