1. A processor system comprising: a cache line signature generator, configured to generate a dynamic signature of a cache line of an instruction cache holding instructions of a program; hardware verification logic configured to securely verify a reference signature for a respective cache line content against the dynamic signature and produce a verification signal in dependence thereon; and a hardware instruction processing pipeline comprising a plurality of stages, configured to: load instructions from the cache line, speculatively execute the instructions in the plurality of stages prior to commitment, and in selective dependence on the verification signal, one of: (i) flush the hardware instruction processing pipeline prior to commitment of the instructions, and (ii) permit commitment of the instructions; the hardware instruction processing pipeline comprising: a hardware commit defer unit, configured to allow reversible partial execution of the instructions prior to commitment of the instructions, while preventing irreversible changes to a program state of the program, dependent on the verification signal; a hardware buffer configured to buffer a write resulting from the partial execution of the instructions prior to commitment of the instructions; and hardware control logic configured to write the buffered write to a memory, contingent on the verification signal.