1. A method for performing static timing analysis on an integrated circuit design, said method comprising: performing static timing analysis on a final circuit netlist utilizing a snip file; converting said snip file to a plurality of cutpoints after said final circuit netlist met all timing constraints under said static timing analysis; performing formal verification on said plurality of cutpoints; determining whether or not said plurality of cutpoints pass said formal verification; and in response to a determination that said plurality of cutpoints do not pass said formal verification, issuing a flag to alert a user.