1. A system for executing instructions of a target syste program, said system including a host processor, a main memory and a system control unit coupled to said host processor and to said main memory, said main memory including a plurality of memory areas, a first area storing said instructions of said target system program and a second area storing a plurality of channel commands, said plurality including at least one channel control command coded to specify a number of functions required for initiating the execution of said target system program by said system, said system further including an emulator coupled to said system control unit for fetching said commands and said instructions from said memory, said emulator comprising: a microprogrammed adapter for executing said plurality of said channel commands fetched from said second area, said adapter comprising: an addressable control store for storing a plurality of sequences of microinstructions; branch and test control means for controlling the addressing of said control store during the execution of each said channel command, and for testing the presence of operations coded in the control portion of said one channel control command for establishing next microinstruction sequences to be referenced; decoder circuits coupled to said control store for generating command control signals in response to the read out of said plurality of microinstruction sequences; control logic circuits coupled to said decoder circuits; an input/output processing section coupled to said control store, said decoder circuits, and said system control unit for receiving information from said main memory, including said one channel control command; and a control interface coupled to said decoder circuits and to said control logic circuits; said processing apparatus further including: a processing unit for processing said instructions, said processing unit being coupled to said input/output processing section and to said control interface, said processing unit comprising: control circuits; an arithmetic and logic unit; and a control memory; said control circuits, said arithmetic and logic unit and said control memory being coupled to said control interface, said control store being operative in response to receipt of said one channel command to reference a first one of said microinstruction sequences, said decoder circuits generating a set of said command control signals for conditioning said control logic circuits to apply signals to said control interface for presetting said arithmetic and logic unit, said control memory, and said control circuits to the proper operational states specified by said coded functions within said one channel command for proper execution of sid instructions of said target system program.