1. A state machine circuit switching between multiple states, wherein each state has a state value and a corresponding output value, the state machine circuit comprising: a state patch circuit, configured to generate a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit, configured to output the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit, configured to output the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal, wherein the register stores the current state value.