1. A computer-implemented method for performing a design operation on a circuit design layout, the method comprising: at a computer, receiving a first design layout comprising a first set of shapes and a second design layout comprising a second set of shapes and a plurality of sections; comparing the first design layout with the second design layout to identify an area of the second design layout that differs from a corresponding area of the first design layout in that one of the areas comprises a portion of a shape that the other area does not have; identifying a set of the sections of the second design layout which include the identified area of the second design layout; and performing a design operation only on the identified set of sections of the second design layout.