1. A system for asynchronous hardware acceleration of an untimed software function for use with single-threaded processors, comprising: a host processor; and a hardware accelerator having: a parameter queue, directly coupled to the host processor, for receiving one or more function parameters from the host processor and allowing the queuing of accelerator tasks; a result queue, directly coupled to the host processor, for returning one or more result values to the host processor; a logic block, implementing the software function with hardware circuitry, for: carrying out the software function in hardware, fetching the one or more function parameters from the parameter queue, and pushing the one or more result values onto the result queue; a globals port for directly accessing global variables of the software function from global memory, wherein each global variable is accessed through a global variable access state machine, and providing a first non-arbitrated direct connection from the accelerator to global memory; a globals map comprising the location of required global variables in the global memory; and a host port, allowing the host processor to access the hardware accelerator, and providing a second non-arbitrated direct connection from the host processor to the accelerator.