1. A computer system comprising: a memory controller coupled to a processor and to a DRAM (dynamic random access memory); wherein the computer system is configured to determine the location of a weak cell in a DRAM row that can only hold one reliable logic state during a refresh interval; and wherein the memory controller is configured to: receive data from the processor, encode the data into a bit vector to be written to memory, wherein: for each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell; and the bit vector is longer than the data.