1. A data processing system comprising: an addressable main store having a plurality of word locations for storing information including data and instructions; high speed buffer storage means coupled to said main store for providing immediate access to data and instructions fetched from said main store and stored therein, said buffer storage means having a plurality of addressable locations, and said buffer storage means including control means for fetching said information from said main store in response to memory commands; and, processing means coupled to said high speed buffer storage means, said processing means for processing a normal repertoire of instructions, each instruction including an operation code portion and a plurality of descriptor address portions, said processing means including control means for generating signals including said memory commands required for the execution of said instructions, said control means including decoder circuit means in response to signals indicative of said operation code portion of each type of instruction within said normal repertoire coded to specify an operation involving a plurality of operand data strings specified by said plurality of descriptor address portions which can be processed concurrently, being operation to generate memory command signals accompanied by a set of coded command signals specifying fetching in advance a predetermined segment of data of a first operand string specified by an address developed from a first one of said plurality of instruction descriptor address portions and said buffer storage control means being operative in response to said set of coded command signals to generate signals for forwarding said memory command to said main store to fetch said segment of data when said predetermined segment specified by said memory command is not stored in said buffer storage means for storage in advance in said buffer storage means and enabling signals for conditioning said processing control means to continue to process another one of said plurality of descriptor address portions of said each type of instruction thereby increasing the efficiency of executing said each predetermined type of instruction.