1. An integrated circuit having an array of memory cells, each memory cell capable of storing multiple bits of information, and at least one data terminal, said integrated circuit comprising a plurality of latches connected to said array of memory cells, said latches organized into a first bank and a second bank; control means alternately coupling said first bank to said array of memory cells and said second bank to said one data terminal, and said second bank to said array of memory cells and said first bank to said one data terminal; and whereby data is simultaneously transferred between one bank of latches and said array of memory cells and transferred between another bank of latches and said data terminal for faster read and write operations.