1. A method for executing instructions in a processor, comprising: upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode in the processor, determining if a replay bit is set in a corresponding entry for the returned input data in a miss buffer or another miss data structure; and if the replay bit is set, transitioning to a deferred-execution mode to execute deferred instructions; otherwise, continuing to execute instructions in the execute-ahead mode.