1. A single instruction multiple data processor comprising: a large scale high level language programmable general purpose front end processor for user interfacing, archival storage and scalar task processing; a parallel array processor having a parallel memory module array, a parallel array of arithmetic elements and an alignment network for aligning particular memory modules in said array thereof with particular arithmetic elements in said array thereof for parallel processing of linear vectors; a large high speed secondary storage system having a high speed data channel connected to said front end processor and a high speed data channel connected to said parallel memory array; and a control unit interconnected to said front end processor, said high speed secondary storage system and said parallel array processor for controlling said parallel array processor, said control unit comprising a task memory for storing object program code for use in parallel processing; a scalar processing unit for fetching object program code from said task memory and for issuing instructions in response thereto; an array control unit for controlling said parallel task processor in response to instructions issued by said scalar processor; and a control maintenance unit for providing communications between said front end processor and said control unit, for providing initialization and maintenance control for said control unit, and for gathering error and use data from said control unit, said secondary storage system, and said parallel array processor and for communicating gathered error and use data to said front end processor.