1. A digital data processing system comprising: A. a host for generating host instructions, at least some of said host instructions including an address value; B. a plurality of processing elements each including: i. a host interconnection circuit connected to said host for receiving each host instruction from said host; ii. a memory including a plurality of addressable storage locations, each identified by an address, for storing information, including both processing element instructions and data; iii. offset value storage for storing a value; iv. a processing elements processor including: a. a processing circuit for performing processing operations in connection with data; b. a memory retrieval circuit connected to said processing circuit and said memory for retrieving processing element instructions and data from said memory, for directing data to said processing circuit for processing and for directing processed data from said processing circuit to said memory for storage; c. a memory address generating circuit connected to said offset value storage and said memory retrieval circuit for computing memory addresses for use by said memory retrieval circuit using the address value from said host instruction and the contents of said offset value storage; and d. a control circuit connected to said host interconnection circuit, said processing circuit, and said memory retrieval for enabling execution of host instructions received by said host interconnection circuit, said control circuit obtaining the host instruction from the host interconnection circuit, enabling said memory address generating circuit to generate an address in response to the address value contained in said host instruction, enabling said memory retrieval circuit to retrieve data from said memory and enabling said processing circuit to perform a processing operation on said retrieved data in response to the instruction.