1. A memory device comprising: a source; a string of memory cells; a source select transistor coupled between the string of memory cells and the source; a source select gate bias circuit configured to apply a first bias voltage value to the source select transistor to electrically isolate the string of memory cells from the source during a first pass of programming and to apply a second bias voltage value to the source select transistor during a second pass of programming; and a programming circuit configured to apply a programming voltage to a control gate of a first selected memory cell of the string of memory cells during the first pass of programming; and apply the programming voltage to a control gate of a second selected memory cell of the string of memory cells during the second pass of programming, wherein the first selected memory cell of the string is closer to the source than the second selected memory cell, wherein the programming circuit applies a same programming voltage value during the first pass of programming and the second pass of programming, and wherein first bias voltage value is greater than the second bias voltage value.