1. A real time data sorting adaptive probabilistic neural network system comprising: (a) a plurality of cluster processor circuits, each cluster processor circuit generating an output signal representing a probability density function estimation value, each cluster processor circuit including: (1) an input buffer memory circuit, the input buffer memory circuit having a plurality of serially connected registers for storing input parameter data signals assigned to a respective cluster processor circuit; (2) a plurality of processing elements, each of the processing elements being coupled to a corresponding register of the input buffer memory circuit for receiving assigned input parameter data signals stored in the input buffer memory circuit, each of the processing elements further being responsive to current unassigned input parameter data signals, each processing element providing an output signal; (3) a plurality of exponential function circuits, each of the exponential function circuits being coupled to a corresponding processing element, each exponential function circuit performing an exponential function on the output signal of each processing element and providing an output signal in response thereto; and (4) a summation circuit coupled to each of the exponential function circuits of the respective cluster processor circuit, the summation circuit being responsive to the output signals from the exponential function circuits and performing an addition function thereon and providing an output signal representing a probability density function estimation value; (b) a decision logic circuit, the decision logic circuit being coupled to the summation circuit of each cluster processor circuit, the decision logic circuit comparing the output signal of each summation circuit of the corresponding cluster processor circuit with at least a first threshold value signal, and providing a decision address signal in response thereto; (c) a switching circuit, the switching circuit being coupled to the decision logic circuit and to each of the cluster processor circuits and further being responsive to current unassigned input parameter data signals and assigning the current unassigned input parameter data signals to a respective cluster processor circuit for storage in the input buffer memory circuit of the respective cluster processor circuit in response to the decision address signal from the decision logic circuit; and (d) a storage register circuit, the storage register circuit being coupled to the switching circuit, the switching circuit providing the current unassigned input parameter data signal to the storage register circuit when the output signal of the summation circuit of each cluster processor circuit is less than the first threshold value signal and greater than a second threshold value signal.