1. A low power SHA (secure hash algorithm)-1 hash algorithm apparatus, the apparatus comprising: a data input unit receiving and transferring data to be performed a hash algorithm; a data extension unit generating an intermediate value of each round of the hash algorithm by using one 32-bit register; a message compression unit performing an SHA-1 hash algorithm on the generated intermediate value of the each round for the hash algorithm, by using one adder; a data output unit outputting a result value of the SHA-1 hash algorithm; and a hash algorithm control unit controlling operation sequences of the data extension unit and the message compression unit.