1. A processing device for controlling two hierarchical level data caches, comprising: a processor which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory which is external of aid processing device; a memory interface unit which accesses said main memory; an internal cache controlled as a first level cache; and a cache control function which controls an external cache external of said processing device as a second level cache, wherein said prefetch instruction, when executed causes said processor to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction form said main memory to said external cache and/or said internal cache, prior to executing said subsequent load instruction, and wherein said prefetch instruction includes at least one indication bit for specifying cache levels to which said operand data is to be transferred, said at least one indication bit being included in an operation part of said prefetch instruction.