1. A processor, comprising: a decode unit to decode a multiply-add instruction and a round instruction, wherein the round instruction is to have an input term to specify how many places a mantissa value is to be rounded to; an execution unit to execute the multiply-add instruction, the round instruction, and a plurality of other types of floating point instructions, the execution unit having exponent difference calculation logic, a multiplier and an adder to support the multiply-add instruction, the execution unit also having a rounder to support the round instruction that is to have the input term to specify how many binary places the mantissa value is to be rounded to, the exponent difference calculation logic having a shifter to support execution of the multiply-add instruction and the round instruction.