1. A static random access memory (SRAM) device comprising: a plurality of memory array layers comprising a first memory array layer and a second memory array layer vertically disposed above the first memory array layer, each memory array layer comprising a plurality of memory cells; layer decoder circuitry on each memory array layer comprising a first layer decoder circuit on the first memory array layer and a second layer decoder circuit on the second memory array layer, each of the first layer decoder circuit and the second layer decoder circuit being configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer; a word line driver circuit disposed on each memory array layer, wherein a plurality of word lines are disposed on each memory array layer, each word line driver circuit being configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer; and a plurality of complementary bit line pairs, each complementary bit line pair extending vertically from a memory cell in the first memory array layer to a memory cell in the second memory array layer.