1. A cache memory, comprising: a data array for storing a plurality of data lines; a tag array for storing a plurality of tags associated with the plurality of data lines; and an address decoder in communication with the tag array and the data array, the address decoder including a plurality of line number registers and receiving as input a context identifier and a plurality of index bits from an address supplied to the address decoder, said plurality of line number registers dynamically mapping contents of a memory external to the cache memory to the cache memory, wherein the contents of the plurality of line number registers can be selectively changed during runtime, and wherein the address decoder processes the context identifier and the plurality of index bits to locate a desired data line in the cache memory.