1. A data processing system, the data processing system comprising: a decoder hardware circuit operable to apply a low density parity check algorithm to a decoder input to yield an interim decoded output, wherein the decoder input is a codeword formed of two bit symbols, and wherein the decoder input is encoded to yield a last layer including a plurality of data pairings of a shift value and an entry value, wherein the shift value for all of the plurality of data pairings is the same, and wherein the entry values included in the plurality of data pairings exhibit at least two different entry values; and an inverse mapping hardware circuit operable to remap the interim decoded output to yield an overall decoded output.