1. A machine-implemented method comprising: identifying a request, at a first hardware thread included in a processor, to initiate a second hardware thread; executing software code on the second hardware thread, wherein the executing includes the second hardware thread storing data in one or more hardware registers; invoking a hypervisor in response to identifying that the second hardware thread ceases execution of the software code; extracting, by the hypervisor, the data from one or more of the hardware registers; storing, by the hypervisor, the extracted data in a shared memory area; and executing a debug routine that retrieves the extracted data from the shared memory area.