1. A method of forming an electrically reprogrammable integrated circuit transistor, the method comprising the steps of: forming field-effect transistor (FET) source/drain regions and FET gate regions on a semiconductor substrate; forming a first insulating layer on the semiconductor substrate having the source/drain and gate regions of the FETs; forming a buried contact opening through the first insulating layer and over at least a portion of the gate region, thereby exposing at least a portion of the underlying gate region; forming a conductive bottom plate layer within the buried contact opening and on the first insulating layer, thereby physically and electrically contacting the exposed portion of the underlying gate region; forming a dielectric layer on the conductive bottom plate layer and over the entire substrate; and forming a conductive top plate layer on the dielectric layer.