1. A method for generating a linear address comprising: receiving a plurality (M) of N-bit address components, a first group of said N-bit address components comprising two address components in a format conforming to canonical address format and a second group comprising the other M-2 address components; adding together the lower K bits of each of said M address components to produce the lower K bits of said linear address, wherein K is smaller than N; and adding together the upper N minus K bits of said second group of address components to produce the upper N minus K bits of said linear address, wherein in an address having canonical format each of the upper N-K bits of the address equals the K-th bit of said address.