1. A central processing unit for a computing system, comprising: (a) an integrated execution unit capable of executing both vector and scalar only instructions, including: (i) a single load unit; (ii) a set of pipelined functional units capable of executing either vector or scalar instructions; (iii) a single store unit, coupled to said set of pipelined functional units; and (iv) a set of architected data registers, including both vector and scalar data registers, coupled to both said load unit and said set of pipelined functional units; and (b) a single instruction path, including: (i) a single instruction unit, including means for fetching instructions from storage; (ii) a decoder connected to said instruction unit and identifying instructions fetched from storage as vector or scalar instructions; (iii) address generation means responsive to said decoder for generating an address of a stored operand required by a decoded instruction; and (iv) execution unit control means connected to said decoder for controlling said integrated execution unit to perform a decoded vector or scalar instruction, whereby said integrated execution unit can operate on a scalar only instruction or a vector instruction under the control of said execution unit control means.