1. A computing system comprising: a memory block, representing a volatile memory, including: a memory interface configured to receive a data packet from a host processor separate from the hardware memory computing block, and a hardware memory computing block, coupled to the memory interface, including: a hardware command decoding block configured to identify a partial data computing (PDC) command based on decoding the data packet, a hardware mask decoding block, coupled to the command decoding block, configured to identify a data mask based on decoding the data packet, a hardware data decoding block, coupled to the mask decoding block, configured to identify a partial data based on decoding the data packet, a hardware memory computing sub-block, coupled to the command decoding block, the mask decoding block, and the data decoding block, configured to compute a computation result for identifying a portion of a read data to be modified according to the PDC command, the data mask, and the partial data, a hardware merging block, coupled to the memory computing sub-block, configured to generate a merge result based on modifying the portion of the read data according to the computation result by the hardware memory computing block, wherein the read data is one or more full bit lines of data and the partial data operates on a portion of the read data, and wherein the memory interface is, configured to transmit the merge result.