1. An inter-processor-interrupt-generation facility within a processor, the inter-processor-interrupt-generation facility comprising: one or more interrupt memory registers, each specifying a region within a shared-memory address space, one or more target processors, and an interrupt vector; and logic to, when a WRITE operation issued by the processor is directed to a shared-memory region specified by a particular interrupt memory register, generate an inter-processor-interrupt, of an interrupt type specified by the interrupt vector included in the particular interrupt memory register, directed to the one or more target processors specified in the particular interrupt memory register, wherein the logic is to generate the inter-processor-interrupt after completion of a cache-invalidation cycle related to the shared-memory region specified by the particular interrupt memory register.