1. A method for implementing systematic, variation-aware integrated circuit extraction, the method comprising: inputting a plurality of etch process conditions to an etch model so as to determine a variation in polysilicon conductor to polysilicon conductor (PC to PC) distance for an integrated circuit layout; using variational etch bias computed as a function of the PC-PC distance to modify an effective gate length for devices of the integrated circuit layout; and generating and storing one or more netlist updates attributable to variations in etch bias conditions, wherein the netlist updates are updates with respect to an original netlist extracted from the integrated circuit layout.