1. A computer-implemented method, to generate in memory, goals for functional verification of a design of a circuit, the method comprising: receiving a plurality of constraints on a plurality of signals input to the circuit during simulation of the design; wherein each signal in said plurality of signals is declared as having a random attribute in an object of a class defined in a hardware verification language; automatically applying a predetermined set of rules, to at least one constraint in said plurality of constraints, to identify a template of a goal to be met, by said functional verification during said simulation; and automatically creating said goal in memory by instantiation of said template with information from said at least one constraint; wherein said goal identifies a signal in said plurality of signals and defines a counter for a value of said signal.