1. An information handling system (IHS), comprising: a processor including a hardware prefetch unit, a memory, coupled to the processor, the memory being configured with a prefetch optimizer tool that: receives an instruction sequence of interest including a plurality of instructions with respective software prefetch instructions in advance of particular load instructions; instructs the hardware prefetch circuit in the processor to prefetch instructions from the memory at a selected prefetch depth of a plurality of selectable hardware prefetch depths; cycles through each of the selectable hardware prefetch depths of the plurality of selectable prefetch depths, and that for each hardware prefetch depth cycles through disabling each of the software prefetch instructions to measure respective execution times of the instruction sequence of interest; and stores a plurality of execution times of the instruction sequence of interest at each of the selectable hardware prefetch depths, each of the execution times at each selectable hardware prefetch depths corresponding to a different disabled software prefetch instruction.