1. An apparatus comprising: a group of storage elements including a first storage element and a second storage element; a first bit line coupled to the first storage element; a second bit line coupled to the second storage element; a first bit line charging circuit coupled to the first bit line, the first bit line charging circuit configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state; a second bit line charging circuit coupled to the second bit line, the second bit line charging circuit configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state, the second programming state different than the first programming state; a supply node; and a supply transistor coupled to the supply node and configured to receive multiple supply voltages from the supply node.