1. A method of partitioning a design into smaller components upon receiving the design represented by a hypergraph with a plurality of nodes, the method comprising: by using a computing device, placing the plurality of nodes of the hypergraph into an N-dimensional space, wherein N is an integer that is greater than 2; identifying a set of hyperedges of the hypergraph based on a first set of criteria; for each identified hyperedge, identifying pairs of nodes connected by the hyperedge based on a second set of criteria; adding the identified pairs of nodes into a sorted list, wherein the sorted list is sorted based on a function of locations for each identified pair of nodes; and clustering identified pairs of nodes of the hypergraph; wherein the clustering is used in the generation of an integrated circuit; and wherein the clustering of the identified pairs of nodes of the hypergraph comprises iteratively: selecting a pair of nodes from the sorted list according to a sorted order, and merging the two nodes of the selected pair.