1. A multi-CPU processor comprising: a first multi-core CPU including a first core, a second core and a first cache controller; a second multi-core CPU including a third core, a fourth core and a second cache controller, a first cache including a first portion and a second portion; and a second cache including a third portion and a fourth portion, wherein the first multi-core CPU includes the first portion of the first cache and the third portion of the second cache, the second multi-core CPU includes the first portion and the second portion of the first cache, and the third portion and the fourth portion of the second cache, the first cache controller is configured to control access to the first portion of the first cache and the third portion of the second cache, the second cache controller is configured to control access to the first portion and the second portion of the first cache, and the third portion and the fourth portion of the second cache, and power supplied to each of the first core, the second core, the third core, the fourth core, the first portion of the first cache, the second portion of the first cache, the third portion of the second cache and the fourth portion of the second cache is controlled independently.