1. A heterogeneous, scalable processor, said processor comprising: a first heterogeneous programmable integrated circuit sub-processor configured for 16, 24, 32 and 64-bit processing; and a second heterogeneous programmable integrated circuit sub-processor configured for 8, 4 and 1-bit processing, wherein at least one of the first and second sub-processors include one or more functional units each including a memory and configured for rearrangement of data values to and from the memory, and wherein each of the first and second sub-processors can only execute one function at a time with an internal control block configured to synchronize an order of function execution.