1. A multi-processor circuit, the circuit comprising: plurality of processors, each having an addressing output; a plurality of independently addressable memory banks, each having an addressing input; a connection circuits coupled between the addressing outputs and the addressing inputs, and arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses, the connection circuit providing for a conflict resolution scheme wherein at least one of the processors is associated with an associated one of the memory banks as an associated processor, the connection circuit being arranged to guarantee the associated processor a higher minimum guaranteed access frequency to said associated one of the memory banks than to a further one of the memory banks other than the associated one of the memory banks; a defragmenter, arranged to detect data associated with a task running on the associated processors that is stored on the further one of the memory banks, to move said data to the associated one of the memory banks during execution of the task in response to said detection and to cause addressing of the data by the associated processors to be remapped from said further one of the memory banks to the associated one of the banks after said moving.