1. A programmable logic device comprising: a plurality of complementary metal-oxide-semiconductor (CMOS) logic modules having zero standby current, each having a plurality of inputs and at least one output each one of said plurality of CMOS logic modules providing a logical combination of said plurality of inputs at said at least one output, said plurality of CMOS logic modules being grouped in a plurality of logic array blocks, said logic array blocks being disposed in linear stacks; a plurality of global conductors extending in one direction and interposed between said stacks of logic array blocks, with a subset of said global conductors coupled to a plurality of said at least one output of said plurality of CMOS logic modules; and a first plurality of multiplexers, each having a plurality of inputs coupled to a corresponding subset of said plurality of global conductors, at least one control input, and an output coupled to an input of said plurality of logic array blocks, said first plurality of multiplexers for programmably coupling a global conductor to a logic array block input in response to programming signals on said at least one control input; a second plurality of multiplexers each one having an output coupled to one of said plurality of logic module inputs, at least one control input, and a plurality of inputs coupled to a plurality of logic array block inputs, said second plurality of multiplexers for programmably coupling a plurality of logic array block inputs to said plurality of logic module inputs in response to programming signals on said at least one control input, wherein, a logic array block can communicate with another logic array block only via said plurality of global conductors and said first plurality of multiplexers.