1. A reconfigurable hardware accelerator board comprising: a. an onboard bus terminated in a connector for connecting to a bus of a computer, b. one or more field programmable gate arrays capable of being partially reprogrammed during execution of a program, connected to the bus, c. a memory accessible by said one or more field programmable gate arrays, d. a processor for loading a plurality of program modules in said memory, each for configuring said one or more field programmable gate arrays, and for reconfiguring the programmable gate arrays during the execution of a program to implement in hardware selected program modules stored in memory in which the field programmable gate arrays are configured to provide: e. at least one module for defining a series of correlation references patches each around a reference point and for specifying the locations of candidate patches for correlation with each reference patch, f. at least one module for performing an image correlation computation by comparing each reference patch with candidate patches, and g. at least one module for selecting the candidate patch which best correlates with a reference patch.