1. A reconfigurable interconnect network for coupling a plurality of processing elements to a plurality of memory elements, the reconfigurable interconnect network comprising: a switching element implemented in one or more hardware devices and configured to provide a data path from any processing element of the plurality of processing elements to any memory element of the plurality of memory elements; a plurality of processor interface units implemented in one or more hardware devices, each processor interface unit coupled to one of the processing elements and to the switching element and configured to manage data flow to and from the processing element based on the performance of the processing element; a plurality of memory interface units implemented in one or more hardware devices, each memory interface unit coupled to one of the memory elements and configured to manage data flow to and from the memory element based on the physical configuration of the memory element; and a plurality of application control units implemented in one or more hardware devices, each application control unit coupled to one of the memory interface units and to the switching element and configured to manage the flow of data to and from the memory interface unit based on an application for which the memory element is storing data by coordinating with the memory interface unit to transfer data to and from the memory element in blocks that are sized based upon the application, each one of the plurality of processing elements being configured for a specific application such that each processing element presents a different configuration than the other processing elements to operate on a different application, each one of the plurality of memory elements being a physically separate memory device configured to store data related to a specific application such that each memory element presents a different physical configuration than the other memory elements to store data for a different application.