1. A processor for use in a geometric processing system comprising a plurality of identical function units, each of said function units operating on multiple bit data and comprising a plurality of one bit slice circuits each including arithmetic logic means for operating on a bit of said data with each of one bit slice circuit interconnected with like circuits including at least one lower order circuit for operating on a lower order bit an at least one higher order circuit for operating on a higher order bit of said multiple bit data, each of said one bit slice circuits including a multiple level storage means which cooperatively functions as a dispersed data stack for said function unit, each one bit slice circuit comprising a single bit arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output, a first bus for transferring a data bit to said first ALU input, a second bus for transferring a data bit to said second ALU input, a third bus for transferring a data bit from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive a data bit from a lower order circuit and said first output transferring the data bit to said first bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a higher order circuit, a downshifting register having an input and first and second outputs operably connected to receive a data bit from a higher order circuit and transferring the data bit to said second bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving a data bit from said ALU output and applying said data bit to said first ALU input, an interface register connected to said second bus for transferring a data bit from an input/output bus to said second bus, and a multiple level register interconnected with said second and said third bus for saving and restoring bits for processing, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping and scaling functions.