1. A television signal processing circuit which performs a decoding processing sequentially in micro block units for a HDTV signal with a high resolution and a SDTV signal with a low resolution, comprising: an inverse quantization section which performs inverse quantization processing with respect to coded data; a transform (decoding?) section which performs decoding processing for data which is inversely quantized; and a motion compensation section which performs motion compensation processing on data which is decoded, wherein when processing an HDTV signal, data reduction processing is performed in the inverse quantization section and subsequent processing is performed on reduced data, and pipeline processing, in which processing in different stages is performed in parallel, is executed for two micro blocks, and when processing a SDTV signal, processing in each stage is sequentially executed without performing the data reduction processing and the pipeline processing.