1. A method of parasitic extraction for multi-patterning in an integrated circuit design, the method comprising: determining resistance solutions and capacitance solutions for a netlist of the integrated circuit design using a processor; performing a first parasitic extraction of the resistance solutions and the capacitance solutions to generate a first set of parasitic values comprising mean values for the resistance solutions and the capacitance solutions; modifying at least one geometrical value to a new value for each vector of parameters identified within the integrated circuit design based on a shift in value attributable to multi-patterning for a given layer of the integrated circuit design; performing a second parasitic extraction of the resistance solution and the capacitance solution based on the modified at least one geometrical value, to generate a second set of parasitic values; determining a difference between the first set of parasitic values and the second set of parasitic values to generate sensitivities; and generating as output statistical parasitics in at least one of a vector form and a collapsed reduced vector form.