1. An apparatus, comprising: a memory, wherein the memory comprises a shared ring buffer for storing data units, wherein the memory stores a plurality of shared variables associated with accessing the shared ring buffer; a first processor core running a first thread and having a first cache associated therewith, wherein the first cache stores a first set of local variables associated with the first processor core, wherein the first thread controls insertion of data items into the shared ring buffer using at least one of the shared variables and the first set of local variables; and a second processor core running a second thread and having a second cache associated therewith, wherein the second cache stores a second set of local variables associated with the second processor core, wherein the second thread controls extraction of data items from the shared ring buffer using at least one of the shared variables and the second set of local variables.