1. A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.