1. A method for debugging a system-on-chip (SOC) integrated circuit design including a processor core and a memory array for storing data generated by the processor core, the SOC integrated circuit design being represented by a simulation model, the method comprising: loading initial data values into the memory array associated with the simulation model and simulating the execution of a predefined test program using the initial data values; during the simulated execution, generating a plurality of transaction records identifying write operations during which updated data values are written into the memory array, wherein each transaction record includes an associated timestamp, associated address information, and the updated data values written during the associated write operation; and upon completing the simulated execution, determining instantaneous data values stored in the memory array at a selected point in time during the simulated execution by combining the initial data values and updated data values from one or more transaction records.