1. A write-combining apparatus in a microprocessor coupled to a memory by a bus, the microprocessor having write buffers for buffering data to be written to the memory on the bus, the apparatus comprising: tag allocation logic, for allocating tags to store data associated with store instructions executing in the microprocessor, wherein said tag allocation logic allocates said tags based on a comparison of bus addresses of said store data; a plurality of tag comparators, coupled to said tag allocation logic, for comparing said tags allocated by said tag allocation logic; and write buffer control logic, coupled to said plurality of tag comparators, for determining which of the write buffers to load said store data into based on said comparing of said tags by said plurality of tag comparators.