1. A processor comprising: at least one floating point unit, including: an adder to add a first operand X and a second operand Y to obtain an output operand having a bit length n; a leading change anticipator (LCA) logic, coupled to the adder, to: for each bit position i from n−1 to 1 of the output operand, obtain a set of bit values of the first operand X, and obtain a set of propagation values based on the first operand X and the second operand Y; and generate a LCA mask based on the set of propagation values and the set of bit values; and a shifter, coupled to the adder and the LCA logic, to normalize the output operand based on the LCA mask.