1. A method of run-time operation of a modified Harvard Architecture processor in an Application Specific Integrated Circuit (ASIC) having an on-chip instruction RAM for storing program code instructions, an on-chip data RAM (D-RAM), data buses, and an arbiter, comprising: detecting an available address space in the on-chip instruction RAM; fetching program code instructions from the on-chip instruction RAM during the run-time operation of the modified Harvard Architecture processor; loading data in or accessing data from the on-chip data RAM during the run-time operation of the modified Harvard Architecture processor; loading data in or accessing data from the available address space of the on-chip instruction RAM as an extension of the data RAM during the run-time operation of the modified Harvard Architecture processor; and stalling the fetching of program code instructions from the on-chip instruction RAM during the step of loading data in or accessing data from the on-chip instruction RAM, during the run-time operation of the modified Harvard Architecture processor.