1. A processor comprising: an execution unit having a data path including a plurality of lanes, each of the lanes to execute an operation on at least one channel of a plurality of channels of a single instruction multiple data (SIMD) instruction responsive to the SIMD instruction, the execution unit having a plurality of quadrants and to perform the SIMD instruction in a number of execution cycles; and a decode logic including compaction circuitry to calculate a minimum number of execution cycles to execute the SIMD instruction based on an active lane count, compare the minimum number of execution cycles to an active quadrant value, and based on the comparison, compact the number of execution cycles, including permutation of at least some of the plurality of channels of the SIMD instruction, wherein a number of permutations between the quadrants is minimized by the compaction circuitry, to reduce the number of execution cycles for execution of the SIMD instruction based at least in part on the calculation and an execution mask associated with the SIMD instruction, the execution mask based at least in part on an instruction predicate mask, a dispatch mask and a conditional mask.