1. A matrix router comprising: a combined input stage and output stage (I/O stage) having m matrix switch(es), each matrix switch having: n inputs and n outputs, each input of said n inputs switchable within said matrix switch to any output of said n outputs; k core outputs and k core inputs, each input of said n inputs switchable to any core output of said k core outputs and each core input of said k core inputs switchable to any output of said n outputs; and a core stage having a matrix switch having at least m times k core stage inputs and at least m times k core stage outputs, each core stage input connected to one core output of said I/O stage, and each core stage output connected to one core input of said I/O stage; where m, n and k are integers and m>=1, n>=2, k>=n; and wherein each matrix switch is configured having a minimum of (n+k) times (n+k) switching permutations that enable any of the n inputs of a given matrix switch to be connected to any of the n outputs of the given matrix switch without use of the core stage.