1. A processor comprising: an execution pipeline including a load store unit having a load queue configured to store speculative load instructions that have issued but have not retired, wherein the execution pipeline is configured to execute a wait for event (WEV) instruction; a reorder buffer coupled to the execution pipeline and configured to store instruction operations waiting to retire; wherein in response to the WEV instruction becoming the oldest instruction in the reorder buffer, the reorder buffer is configured to signal the load store unit of a possible redirect in response to determining that an event corresponding to a paired set event (SEV) instruction executed by a different processor has been received; wherein in response to the signal, the load store unit is configured to: check the load queue for speculatively executed load instructions that match an address of a store instruction that has been determined to have been executed by the different processor prior to execution of the paired SEV instruction; retire any speculatively executed load instructions that do not match an address of a store instruction that has been determined to have been executed by the different processor prior to execution of the paired SEV instruction; and signal the reorder buffer to retire the WEV instruction in response to the load store unit completing the check of the load queue.