1. A processor for processing of instruction data including memory access instructions for accessing an external RAM memory comprising: a region stride memory location for storing of a pre-fetch operation stride; a memory region identifier for storing data indicative of a memory region within the external RAM memory within which to apply the stored pre-fetch operation stride; a pre-fetch circuit for pre-fetching of data from the external RAM memory, the pre-fetching circuit responsive to the pre-fetch memory stride when accessing data within the pre-fetch memory region for fetching from said memory using said stride.