1. A method of extracting layout parasitic information comprising: providing a netlist database describing devices and nets of a circuit design; providing a layout database describing geometries of the circuit design; creating from the netlist database and layout database a connectivity-based database where the geometries of the circuit design are organized by nets; providing a predefined structure database comprising a plurality of predefined structures and a plurality of previously extracted parasitic values corresponding to the predefined structures; tracing along a selected net of the connectivity database to find parasitic structures formed by the geometries of the selected net; comparing each of the parasitic structures of the selected net of the connectivity database to the predefined structures in the predefined structure database; and for each parasitic structure of the connectivity-based database that matches one of the predefined structures, using a previously extracted parasitic value from the predefined structure database in determining layout parasitics for the selected net.