1. A processor comprising: a branch information table (BIT); and a return address stack (RAS); wherein the processor is configured to: allocate an entry in the BIT responsive to decoding a branch instruction, wherein the branch instruction has not been previously decoded by the processor; access the RAS at a first location and back-annotate the BIT entry with the first location, responsive to executing the branch instruction; and reposition a RAS pointer to the first location, responsive to re-executing the branch instruction.