1. A method comprising: disabling one or more memory interfaces of a plurality of memory interfaces and enabling the other memory interfaces of the plurality of memory interfaces of a computing device; coupling one or more memory devices to each of the enabled memory interfaces, coupling one or more additional memory devices to a subset of the enabled memory interfaces, and not coupling any memory device to each of the disabled memory interface, wherein a first depth of memory is coupled to a first set of enabled memory interfaces and a second depth of memory is coupled to a second set of enabled memory interfaces, and wherein the first depth is different from the second depth; and mapping each of a plurality of physical address ranges to a corresponding enabled memory interface and a memory space of a corresponding memory device, wherein the physical address ranges of the one or more additional memory devices includes a given offset.