1. A system comprising: a memory controller; and a processor core coupled to the memory controller, the processor core comprising: a first register; a second register; a control register to store an indicator of a default floating point round mode, and a denormals as zeroes indicator; a decoder to receive a round instruction, the round instruction to identify the first register, the register to store a source operand with a plurality of packed double precision floating point values, the round instruction having a round mode override indicator to indicate that the default floating point round mode is to be overridden, the round instruction to identify an override floating point round mode, of a plurality of possible override floating point round modes; and an execution unit coupled to the decoder, and coupled to the first and second registers, the execution unit, responsive to the round instruction, to: convert denormal packed double precision floating point values of the source operand to zero; perform a round operation on the packed double precision floating point values, to generate integral valued double precision floating point values, according to the identified override floating point round mode; and store the integral valued double precision floating point values in the second register.