1. An I/O processor for controlling data transfer between a local bus and an I/O bus comprising: a register file (16); an Execution Unit (10) connected to said register file; said execution unit including a register mapper (24) for establishing a correspondence between logical addresses in instructions and physical addresses of said register file, a local bus sequencer (14) connected to said local bus and to said register file; and, an I/O bus sequencer (12) connected to said I/O bus and to said register file; said register file (16) being shared by said Execution Unit, said local bus sequencer, and said I/O bus sequencer, said register file being comprised of a plurality of register sets; each of said register sets being comprised of a number of local registers addressable by a physical address; said I/O bus sequencer (12), said local bus sequencer (14), and said Execution Unit (10) each having separate data paths for read/write access to said register file (16); said register mapper including a plurality of register set pointers, each register set pointer (FIG. 3) being stored at a location in said register mapper addressable by a logical address, said register set pointers being directly accessed by a logical address in an instruction executed by said execution unit in said I/O processor, each register set pointer having a physical address field for storing the physical address of one of said register sets in said register file such that said logical address presented at an input to said mapper selects a register set pointer, the physical address stored in said register set pointer thereby establishing the correspondence between said logical address and said physical address in said register file (16); said Execution Unit including means for executing instructions that pass a register set pointer from a sending task to a destination task running on said processor by changing the contents of the physical address field of a register set pointer associated with said destination task; said local bus sequencer (14) including first means responsive to said execution unit for sequencing data between said local bus and said register file; said I/O bus sequencer including second means responsive to said execution unit for sequencing data between said I/O bus and said register file.