1. A system comprising: a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions comprising: receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA), the source code configured for a processor and an accelerator; generating aligned assembled code representing the source code, the aligned assembled code being byte-aligned and in accordance with an aligned ISA and comprising aligned processor code for the processor and aligned accelerator code for the accelerator; performing a first linking pass on the aligned assembled code, the first linking pass comprising relocating a first relocation target residing in the aligned accelerator code, wherein the first relocation target is a memory space maintaining an address of a first object outside the aligned accelerator code; generating unaligned assembled code semantically equivalent to the aligned assembled code, in accordance with the unaligned ISA, the unaligned assembled code representing the source code and comprising unaligned processor code for the processor and unaligned accelerator code for the accelerator; wherein at least a portion of the unaligned assembled code semantically equivalent to the aligned assembled code is not byte-aligned, wherein the aligned assembled code comprises padding to achieve byte-alignment, and wherein generating the aligned assembled code representing the source code comprises: generating the unaligned assembled code based on the source code; and padding the unaligned assembled code with blank bits configured to shift instructions in the unaligned assembled code to byte-aligned positions; performing a second linking pass on the unaligned assembled code semantically equivalent to the aligned assembled code, the second linking pass comprising relocating a second relocation target residing outside the unaligned accelerator code, wherein the second relocation target is a memory space maintaining an address of a second object in the unaligned accelerator code; and outputting the executable file for the unaligned ISA based on the first linking pass and the second linking pass.