1. A computing system comprising: a host processor; a host memory, the host memory storing programs for the host processor; a system interface configured to interface with the host processor; and a programmable shader comprising: a) an instruction processing unit configured to convert shader program instructions and output a converted sequence of the program instructions based upon available resources in the programmable shader; b) a fragment selector configured to select fragments, under control of the instruction processing unit, from a total number of fragments; c) a program counter unit configured to compute and output a current program counter under control of the instruction processing unit; and d) a loop count unit configured to compute and output a current loop count under control of the instruction processing unit.