1. An apparatus for executing an arithmetic instruction, said arithmetic instruction including more than three addresses, said apparatus comprising: means for selecting a first source of information from two addresses of said more than three addresses specified within said arithmetic instruction; means for selecting a second source of information from an address of said more than three addresses specified within said arithmetic instruction; means for perforating an operation upon said first source and said second source to generate a result, said operation specified within said arithmetic instruction; means for selecting a destination storage for said result from an address of said more than three addresses specified within said arithmetic instruction; and means for updating a pointer represented as an address of said more than three addresses specified within said arithmetic instruction, said means for updating a pointer and said means for performing an operation occurring in parallel.