1. A method of data processing in a cache coherent data processing system including at least first and second coherency domains, said first coherency domain containing a memory controller and an associated system memory having a target memory block identified by a target address, method comprising: in the first coherency domain, maintaining a domain indicator indicating whether said target memory block is cached outside said first coherency domain; receiving in the first coherency domain a flush operation broadcast to said first and second coherency domains, said flush operation specifying said target address of said target memory block; receiving in the first coherency domain a combined response to said flush operation representing a system-wide response to said flush operation; in response to receipt in said first coherency domain of said combined response, determining if said combined response indicates that a cached copy of said target memory block may remain within the data processing system; and in response to a determination that said combined response indicates that a cached copy of said target memory block may remain in the data processing system, updating said domain indicator to indicate that said target memory block is cached outside of said first coherency domain.