1. A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising: first means for storing a source of operands corresponding to a plurality of instruction operations; second means for concurrently transferring said operands from said first means to a plurality of functional units; third means for performing said instruction operations to generate results using said plurality of functional units; and fourth means for concurrently distributing said results, wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.