1. In a data processor capable of processing data in accordance with a first macroinstruction and a second macroinstruction, improved apparatus for generating at least a first microinstruction and for generating at least a second microinstruction for use in combination with the first microinstruction for executing the second macroinstruction, comprising: microinstruction memory means for storing the first microinstruction at a first address and the second microinstruction at a second address; output means for storing the microinstructions read from the microinstruction memory means and for generating a first output signal in response to the absence of the first microinstruction from the output means and for generating a second output signal in response to the presence of the first microinstruction in the output means; instruction register means for storing during a first time period a first operation code signal corresponding to at least a portion of the first macroinstruction and for storing during a second time period a second operation code signal corresponding to at least a portion of the second macroinstruction; and addressing means responsive during a first time period to the first operation code signal and the first output signal for reading the first microinstruction from the first address into the output means so that the execution of the first macroinstruction is enabled, and responsive during a second time period later than the first time period to the second operation code signal and the first output signal for reading the first microinstruction from the first address into the output means and responsive to the second operation code signal and the second output signal for reading the second microinstruction from the second address into the output means so that the execution of the second macroinstruction is enabled by the first and second microinstructions, whereby the first microinstruction stored at the first address is used to enable the execution of both the first and second macroinstructions.