1. In a computer having a plurality of execution units in which object level instructions are executed singly in a scalar manner and in a group in a parallel, concurrent manner, and in which parallel execution of a group of object level instructions is indicated by compounding control information which is generated prior to fetching said object level instructions for execution, an apparatus for generating microcode that implements and controls execution of said object level instructions, said apparatus comprising: compound processing means for generating said compound control information for said group of object level instructions prior to fetching said group of object level instructions for execution; means for storing said group of object level instructions, including means for storing a first object level instruction, means for storing a second object level instruction, and means for storing said compounding control information indicating parallel execution of said first object level instruction and said second object level instruction; means for storing a plurality of first microcode instruction sequences that includes a sequence of microcode instructions for executing each object level instruction that is executed by said computer singly in a scaler manner; means for storing a second plurality of microcode instruction sequences that includes a sequence of partial microcode instructions for each object level instruction that is executed as a second instruction in a group of object level instructions; means to map said first object level instruction to said means for storing a first microcode instruction sequence to fetch a first microcode instruction; means to map said second instruction to said means for storing a second microcode instruction sequence to fetch a second microcode instruction; means responsive to said first object level instruction, said second object level instruction and said compounding control information to merge said first microcode instruction and said second microcode instruction; means coupling said means to merge said means for storing said first microcode instruction sequence and said means for storing a second microcode instruction sequence; said means to merge including; means to determine an execution resource dependency between said first microcode instruction and said second microcode instruction; means responsive to said means to determine an execution resource dependency to substitute predetermined fields of said second microcode instruction into certain predetermined fields of said first microcode instruction to form a merged microcode instruction; and means for parallel execution of said merged microcode instruction connected to said means to merge.