1. A method of coordinating execution of instructions in a processor that allows the instructions to execute out-of-order, the method comprising: decoding a particular instruction defined in accordance with an instruction set of the processor; and introducing into a stream of executable operations a corresponding helper sequence of instructions corresponding to the particular instruction, wherein the corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.