1. A method for reducing inter-thread communication latency in a multiprocessor system having a cache hierarchy with a write-through level one cache, the method comprising: providing a non-coherent store instruction; scheduling a first thread on a first hardware context associated with the write-through level one cache; scheduling a second thread on a second hardware context sharing the write-through level one cache; and within the first thread, executing the non-coherent store instruction to pass a data value from the first thread to the second thread.