1. A programmable memory, comprising: a matrix of programmable memory cells arranged in rows and columns, each cell for storing first and second logic states with each of said cells normally in the first logic state and programmable to the second logic state, said matrix in an operating mode having output lines coupled to respective groups of said columns; operating means for addressing select ones of said memory cells in the operating mode in accordance with an input operating address and for combining the logic states of said address cells in accordance with a predetermined operating logic function for output from said memory; program enable means for placing the memory in a programming mode to program said memory cells; means for addressing each cell in said matrix in the programming mode to program said memory cells; programming means for changing the logic state of an addressed one of said memory cells from the first logic state to the second logic state, said programming means activated in response to addressing one of said memory cells without raising the voltage on any of said output lines such that each of said memory cells is programmed in the programming mode by addressing thereof.