1. A parallel processor for parallel processing of logic equations and arithmetic operations comprising; a plurality of sequencer means having a common clock for synchronizing operation of each sequencer of said plurality of sequencer means; each sequencer of said plurality of sequencer means having a single bit processor, input multiplexer, data memory for storing data produced by said single bit processor and a machine instruction decoder; common program memory storing machine instructions for processing logic equations; said instruction decoder being responsive to said common program memory and controlling the operation of said input multiplexer, single bit processor and data memory; said single bit processor being responsive to said instruction decoder and input multiplexer and producing output data; said data memory storing the output data under control of said instruction decoder.