1. A read-only memory (ROM) comprising: Q input address lines for supplying an address; P output bit lines for supplying a P-bit data word according to the first address; and N memory cells C 1 to C N , where N>1, and each memory cell C i comprises: W i word lines respectively electrically coupled to B i bit lines according to a dataset to be stored within the ROM, wherein 1<B i <P; and a decoder D i coupled to the Q input lines and adapted to assert one of the W i word lines according to the first address; wherein for at least one of the memory cells C i , the corresponding number of word lines W i is less than 2 Q ; and wherein the P-bit data word is obtained from the bit lines of the memory cells.