1. A processor, comprising: a cache including a plurality of cache banks; a plurality of processor cores, wherein during a first mode of processor operation, each of said plurality of processor cores is configurable to access any of said plurality of cache banks; and core/bank mapping logic coupled to said plurality of cache banks and said plurality of processor cores; wherein during a second mode of processor operation, said core/bank mapping logic is configured to implement a plurality of virtual processors within said processor; wherein a first one of said plurality of virtual processors includes a first subset of said plurality of processor cores and a first subset of said cache banks; wherein a second one of said plurality of virtual processors includes a second subset of said plurality of processor cores and a second subset of said cache banks; wherein processor cores and cache banks included in any one of said virtual processors are distinct from processor cores and cache banks included in any other one of said virtual processors; wherein said processor is operable to store state information indicating which of said plurality of processor cores and which of said plurality of cache banks are included in which ones of said plurality of virtual processors dependent upon programmable processor configuration information; and wherein each of said plurality of virtual processors is configurable by said core/bank mapping logic such that in different configurations of said programmable processor configuration information, a given one of said virtual processors includes different numbers of ones of said plurality of processor cores or different numbers of ones of said plurality of cache banks, and wherein said core/bank mapping logic is configured to prevent processor cores included in said given virtual processor from accessing cache banks included in a different virtual processor.