1. An interrupt controller comprising: a control unit coupled to receive an interrupt acknowledgement from a processor and configured to return an interrupt vector corresponding to an interrupt in response to the interrupt acknowledgement; and a masking circuit configured to mask the interrupt corresponding to the interrupt vector atomically with the interrupt acknowledgement, wherein the interrupt is not masked prior to the control unit returning the interrupt vector in response to the interrupt acknowledgement, and wherein the masking circuit is configured to mask the interrupt responsive to the interrupt acknowledgement, and wherein masking the interrupt prevents a subsequent interrupt acknowledgement from receiving a same interrupt vector until the processor re-enables the interrupt.