1. A processor comprising: a first hardware thread and a second hardware thread; a cache to store cache coherent data in a cache line for a shared memory address accessible by said second hardware thread; a decode stage to decode a first instruction for execution by said first hardware thread, the first instruction specifying a source vector data operand, said shared memory address as a destination operand, and one or more owners of said shared memory address; and one or more execution units, responsive to the decoded first instruction, to: copy data from the source vector data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread in the cache when said one or more owners includes said second hardware thread, wherein corresponding vector elements from the vector source data operand are copied to adjacent sequential element locations starting at the shared memory address until the most significant vector destination element location is filled.