1. An integrated circuit comprising: (A) system address leads; (B) system data leads; (C) an interface having address leads and data leads coupled to the system address leads and the system data leads; (D) control node circuitry having: a control node message queue coupled to the interface, the control node message queue having storage places for data and addresses, a node input buffer separate from the control node message queue and having a control serial message input, and a node output buffer, separate from the control node message queue and the node input buffer, and having a control serial message output, the node output buffer having storage places for data and addresses; and (E) processing circuitry having: a global data input and output buffer having processor data leads; and a node wrapper program queue having: multiple program entries with plural words for eachentry to store information for scheduled programs, in an order of message receipt, and used to schedule execution of the processing circuitry, a processor serial message input coupled with the control serial message output, and a processor serial message output coupled with the control serial message input.