1. Memory circuitry usable as content addressable memory comprising: a plurality of programable memory cells organized as a two-dimensional array of intersecting rows and columns of such memory cells, wherein each memory cell has a storage capacity of one bit of binary data; a plurality of write enable leads, each of which is associated with and extends adjacently along a respective one of the rows, each of the write enable leads being configured to selectively enable writing of data to the memory cells in the associated row; a plurality of read enable leads, each of which is associated with and extends adjacently along a respective one of the rows, each of the read enable leads being configured to selectively enable reading of data from the memory cells in the associated row; a plurality of input signal leads; and connector circuitry configured to selectively connect each of the input signal leads to a respective one of the write enable leads or a respective one of the read enable leads.