1. A processor for executing a plurality of instruction streams, at least one of the instruction streams being a master stream, the processor comprising: an instruction cache for storing instructions for each of the plurality of instruction streams to be executed by the processor; a plurality of functional resources for use by one or more of the plurality of instruction streams; and inter-stream control bitmap, coupled to said functional resources, said inter-stream control bitmap comprising: a plurality of control bits associated with active ones of the plurality of instruction streams, said control bits having a set of editable characteristics for said active ones of the plurality of instruction streams, said editable characteristics being set by at least the master stream.