1. A memory apparatus, comprising: a plurality of memory arrays, each memory array comprising a plurality of memory cells; a plurality of local bit lines (LBLs), each connected to a separate plurality of the memory cells; a plurality of global bit lines, each connected to a separate plurality of the local bit lines; a plurality of global bit line (GBL) latches, each located along a separate global bit line to latch a signal along the respective global bit line; a plurality of first logic gates, each receiving as inputs a separate plurality of the global bit lines; and a plurality of solar bit lines, each configured to connect an output of a separate one of the plurality of first logic gates with a same output latch.