1. A computer-implemented method of generating hardware description language (HDL) code for an executable graphical block diagram model of a hardware system, said method comprising: transforming, using a processor of the computer, a first component of the graphical block diagram model into an intermediate representation, the first component processing frame-based input data and representing a first computational element of the hardware system, wherein a frame is a temporal collection of data samples acquired over a predetermined time period; and serializing at least a portion of the first component, wherein serializing the first component further comprises: generating HDL code for a buffer storing at least a portion of the frame-based input data to the first component; generating HDL code for at least one delay unit delaying processing of the at least a portion of the frame-based input data to the first component; and generating HDL code for at least a portion of the first component, the generated HDL code for the at least a portion of the first component including the generated HDL code for the buffer and the generated HDL code for the at least one delay unit.