1. A memory cell array, comprising: a plurality of memory blocks, each memory block including a plurality of memory strings, wherein each string comprises a plurality of memory cells connected in series between a string selecting transistor (SST) and a ground selecting transistor (GST), the plurality of memory cells comprises at least one memory cell configured to store multi-bit data (“MB cell”) and at least one memory cell configured to store single-bit data (“SB cell”), and the SB cell is positioned in the string at a location exhibiting relatively weak programming characteristics.