1. A semiconductor storage device comprising: a memory cell array including memory cells arranged at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells including a rectifier element and a variable resistance element connected in series; and a control circuit configured to apply a first voltage to a selected one of the first wirings and a second voltage lower than the first voltage to a selected one of the second wirings so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring, and the control circuit being configured to be able to perform a concurrent read operation to perform a read operation from a plurality of the memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently, and being configured to be able to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.