1. A programmable logic device comprising: a JTAG state machine; a JTAG instruction decoder coupled to the JTAG state machine; a JTAG multiplexer coupled to the JTAG instruction decoder and a control circuit; a first non-volatile memory adapted to store a first identification code of the programmable logic device; a second memory adapted to store a second identification code of the programmable logic device; and the control circuit adapted to select between the first identification code stored in the first non-volatile memory and the second identification code stored in the second memory to provide as an identification code for the programmable logic device, wherein the control circuit comprises: a multiplexer coupled to the first non-volatile memory and the second memory; and a third non-volatile memory adapted to control the multiplexer to provide one of the first identification code and the second identification code as a multiplexer output signal to the JTAG multiplexer to provide as the identification code on a test data output path.