1. A computer system including a plurality of processing elements requiring access to a shared memory resource, said computer system comprising: a priority conflict resolution circuit for controlling access to said memory resource among said processing elements, said priority conflict resolution circuit including a predetermined differing initial priority assigned corresponding to each of said plurality of said processing elements and wherein upon a selected one of said plurality of said processing elements being afforded access to said memory resource based upon said initial priority thereof being a highest priority, said initial priority of said selected one of said plurality of said processing elements is changed to a lowest priority and said priority of all others of said plurality of said processing elements is incremented to a next higher priority, the all others of said plurality of said processing elements incrementable to the next higher priority thereof until a common highest priority is reached, and wherein said priority of said subset of said processing elements default to said differing initial priorities thereof.