1. A processor, comprising: a first one of a plurality of processor cores, including: a first cache including circuitry to store one or more translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and circuitry to: execute a translated instruction, the translated instruction translated from an instruction stored in a first memory location; set a first translation indicator in the first cache corresponding to the first memory location to indicate that the first memory location includes translated code to be protected; and request senior store buffer drains of one or more other ones of the plurality of processor cores of the processor based upon the execution of the translated instruction, the senior store buffers including store operations that have been dispatched, executed, or retired, but that have not been committed.