1. A multiprocessor computer system comprising, a cache coherent symmetric (SMP) computer system of symmetric multiple processors having a plurality of processing nodes and caches and a node controller which use processor state information according to mappings provided by supervisor software or firmware of allowable physical processors to an application workload to determine which coherent cache regions in the system are required to examine a coherency transaction produced by a storage request of a single originating processor of said computer system and to change coherency boundaries of one or more of said coherent cache regions directly with coherency mode bits for said coherent cache regions, and wherein a control program for the dispatch of virtual processors for controlling the size and extent of a required coherency domain changes said coherency boundaries directly with said coherency mode bits.