1. A method for enabling high speed floating point exception enabled operation in a multiscalar processor system having a floating point processor unit, a fixed point processor unit and means for simultaneously dispatching instructions to multiple processor units, said method comprising the steps of: simultaneously dispatching an associated dummy instruction having a retained instruction address to said fixed point processor unit in response to each arithmetic instruction dispatched to said floating point processor unit; synchronizing an output of each arithmetic instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit wherein each arithmetic instruction within said floating point processor unit which initiates an occurrence of a floating point exception is accurately identified.