1. A processor, comprising: a front end including circuitry to: determine that an acyclical thread assignment scheme is to be applied to a first block of code received at the processor; determine that a cyclical thread assignment scheme is to be applied to a second block of code received at the processor; based upon applying the acyclical thread assignment scheme, assign the first block of code to a static logical thread; and based upon applying the cyclical thread assignment scheme, assign the second block of code to a rotating logical thread; and a scheduler including circuitry to: assign the static logical thread to a first physical thread; assign the static logical thread to the first physical thread upon each subsequent control flow instruction of the static logical thread; assign the rotating logical thread using a loop of cycle thread assignment iterations, wherein the loop of cyclical thread assignment iterations comprises: assigning the rotating logical thread to a second physical thread; and assigning the rotating logical thread to a third physical thread upon a subsequent execution of the rotating logical thread.