1. An integrated circuit comprising: a first digital signal processing (DSP) block, comprising a first hardwired multiplier coupled to a first hardwired adder; and a second DSP block, comprising a second hardwired multiplier coupled to a second hardwired adder via a programmable multiplexer circuit, wherein the programmable multiplexer circuit is dynamically configurable during operation of the integrated circuit; and wherein the first hardwired adder is coupled to the programmable multiplexer circuit, wherein the programmable multiplexer circuit is controlled by an opmode register that is writable during operation of the integrated circuit, wherein the opmode register is a register within the integrated circuit that is independent of configuration memory of the integrated circuit.