1. A method for providing error detection and correction, the method comprising: receiving an error code correction (ECC) word at a memory assembly in multiple packets via a memory bus, the ECC word including data bits and ECC bits arranged into multiple ECC symbols, each of the ECC symbols associated with one bitlane on the memory bus and including four bits, wherein the ECC word includes an 88/72 ECC code that will detect errors in the symbol, correct errors in the symbol, and detect double symbol errors; and utilizing one of the ECC symbols to perform error detection and correction to bits in the ECC word received via the bitlane associated with the symbol.