1. A processor comprising: a logic to decode a virtual machine control structure (VMCS) identification (ID) having a plurality of portions each to identify a field of the VMCS, wherein data stored within the fields is of varying size and accessibility, into an address of a VMCS field addressed by a virtual machine architecture instruction and an offset value to be added to a base address to identify a location of one of a plurality of micro-operations (uops) to be executed corresponding to a source/destination of the virtual machine architecture instruction wherein if the VMCS field address does not correspond to a valid value, the offset value is to indicate an offset to a uop to signal an invalid VMCS ID.