1. A Field Programmable Gate Array (FPGA) Integrated Circuit comprising: a cell structure including (a) configurable cells in a two-dimensional array and (b) a configurable internal interconnection that interconnects the configurable cells; and at least one dedicated hardwired interface unit that: is separate from the plurality of configurable cells; is connected to the configurable internal interconnection; is adapted for transferring processing data between the configurable cells and an external unit at runtime, while the configurable cells are operational; has at least one state machine controlling said transfer; includes a protocol generator adapted for generating data transfer protocols; and has at least one dedicated line transmitting signals to said external unit and at least one dedicated line receiving signals from said external unit.