1. A computer apparatus suitable for use in the combined compilation and verification of platform neutral bytecode instructions resulting in optimized machine code, comprising: a central processing unit (CPU); a computer memory coupled to said CPU, said computer memory comprised of a computer readable medium; a compilation-verification program embodied on said computer readable medium, said compilation-verification program comprising: a first code segment that receives a bytecode listing; a second code segment that verifies said bytecode listing is free of malicious and improper code and compiles said bytecode listing into machine code; and a third code segment that interprets and executes said machine code.