1. An arithmetic unit, comprising: an operator adapted to receive first and second N-bit operands and produce an N-bit result, the operator including: a preconditioning circuit, a carry generator, and a summing circuit, mounted in cascade, wherein the preconditioning circuit comprises N+1 cells mounted in parallel, the N+1 cells including a selection cell and N preconditioning cells, each of the N preconditioning cells receiving two bits of like rank of the first and second N-bit operands and having means for producing a first and a second logic combination of the two received bits, wherein the carry generator receives the first and second logic combinations from the preconditioning circuit and also receives an incoming carry bit, said carry generator having means for computing N carry bits from the first and second logic combinations and the incoming carry bit, wherein the summing circuit comprises N elementary adders mounted in parallel, each of the N elementary adders receiving the first logic combination from a corresponding preconditioning cell and receiving a corresponding carry bit from the carry generator and wherein each elementary adder produces one bit of the N-bit result by performing an exclusive OR logic operation between the first logic combination and the corresponding carry bit, wherein n and m designate integer numbers such that n+ m=N and the first n bits of the first and second N-bit operands are supplied to corresponding preconditioning cells via a first and second n-bit input register, and the last m bits of the first and second N-bit operands are supplied to corresponding preconditioning cells via a first and second m-bit input register, the first n bits of the N-bit result are addressed to an n-bit output register by the corresponding elementary adders of the summing circuit, and the last m bits of the N-bit result are addressed to an m-bit output register by the corresponding elementary adders of the summing circuit, and wherein the (n+1)th cell of the preconditioning circuit is the selection cell for selectively controlling the operator according to a first and a second working mode, in which in the first working mode the bits of the n-bit and m-bit output registers are the result of an operation performed on a first set of two numbers of N bits, a first number of the first set consisting of a union of bits of the first n-bit input register and the first m-bit input register, and a second number of the first set consisting of a union of bits of the second n-bit input register and the second m-bit input register, and in the second working mode a second set of two numbers, consisting respectively of the bits of the n-bit output register and of the bits of the m-bit output register, is the result of two operations performed in parallel on a third set of two numbers and on a fourth set of two numbers, a first number of the third set consisting of the bits of the first n-bit input register, and a second number of the third set consisting of the bits of the second n-bit input register, and a first number of the fourth set consisting of the bits of the first m-bit input register, and a second number of the fourth set consisting of the bits of the second m-bit input register.