1. An apparatus comprising: a processor having an interrupt input, first and second mask registers controlled by said processor and each having a bit indicating whether an interrupt signal present at said interrupt input is to be enabled or disabled, first means responsive to said interrupt input and said bit in said first mask register for respectively permitting and obstructing recognition of said interrupt signal by said processor when said bit of said first mask register is respectively indicating that said interrupt signal is respectively enabled and disabled, second means responsive to said interrupt input and said bit in said second mask register for respectively permitting and obstructing recognition of said interrupt signal by a further circuit when said bit of said second mask register is respectively indicating that said interrupt signal is respectively enabled and disabled, and means responsive to loading of said first mask register by said processor for conforming said bit of said second mask register to said bit of said first mask register.