1. A method to detect deadlock in a hardware design, comprising: identifying, in a processor, one or more key control signals in the hardware design, each key control signal enabling or blocking an action from happening; generating, in a processor, a state machine for each identified key control signal to track the state of that key control signal; generating, in a processor, one or more assertions for each identified key control signal to detect whether that key control signal is in a deadlock state based on data from the state machine for that key control signal; and determining, in a processor, whether the hardware design can enter a deadlock state by detecting, through formal verification or simulation based verification of the one or more assertions for each identified key control signal in conjunction with said state machines, whether any of the identified key control signals can enter a deadlock state.