1. A microprocessor configured to validate code during runtime, comprising: an instruction pipeline device configured to decode and execute instructions along a control flow path of a block; a signature generator device configured to generate, concurrently with decoding of the respective instructions on the instruction pipeline device, a signature of at least one of: a trace cache storing a plurality of blocks, the control flow path of the block, and the instructions to be executed along the control flow path of the block; a dynamically updatable signature cache system, configured to securely receive and store a set of valid signatures selectively dependent on at least instructions of a block stored in the trace cache, including a signature associated with a content of the instruction pipeline device or trace cache; and a validator, integrated into the instruction pipeline device, configured to validate the generated signature against a signature from the signature cache.