1. A method for verifying a layout of an integrated circuit, which comprises: providing a layout containing a plurality of interconnection networks; selecting one of the plurality of the interconnection networks that are contained in the layout and thereby obtaining a selected interconnection network, the selected interconnection network having dimensions; and calculating a capacitance of the selected interconnection network with respect to others of the plurality of the interconnection networks that are contained in the layout by performing the following steps: determining a filter polygon that surrounds the dimensions of the selected interconnection network; providing the filter polygon with dimensions that are enlarged by a predetermined extent relative to the dimensions of the selected interconnection network; determining portions of others of the plurality of the interconnection networks that overlap the filter polygon; and determining a capacitance between the selected interconnection network and the portions of the others of the interconnection networks that overlap the filter polygon.