1. An apparatus comprising: a plurality of registers; at least one physical processor core coupled with the registers, wherein the at least one physical processor core comprises an operating system visible sequencer and an operating system invisible sequencer; an event counter to count a number of performance-limiting proxy execution events that are to result from execution of a user-level thread of a user-level multi-threaded program, wherein the user-level thread is to be operating system invisible and is to execute on the operating system invisible sequencer; and a component to reduce the number of the performance-limiting proxy execution events by moving the user-level thread from the operating system invisible sequencer to the operating system visible sequencer, wherein the operating system invisible sequencer is to halt processing of instructions pending completion of the user-level thread on the operating system visible sequencer.