1. An apparatus comprising: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have no more than a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has no more than a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.