1. A system comprising: a host controller; an Input/Output (I/O) buffer; and a memory device coupled to the host controller and configured to receive a read command from the host controller, the memory device including an interface control logic in communication with a memory array; wherein the interface control logic includes a latency programming circuit coupled to the memory array and the I/O buffer, the latency programming circuit to store at least one value corresponding to a delay to be provided at the memory array prior to transferring data from the memory array during a read operation, and the latency programming circuit configured to provide the delay by incrementing a counter after a number of clock cycles and by comparing the counter with the value corresponding to the delay.