1. A parity unit circuit operable in a parallel pipelined low density parity check (LDPC) decoder circuit having a plurality of bit nodes and having a plurality of such parity unit circuits controllably coupled with the plurality of bit nodes and having a controller for sequencing operation of the plurality of bit nodes and operation of the plurality of parity unit circuits for exchanging bit messages, the LDPC decoder circuit operable to perform an iterative, message passing, rain-sum algorithm, each parity unit circuit comprising: a memory logic block adapted to store data relating to a parity check computation of said each parity unit circuit, the memory logic block adapted to receive a next bit message (bit_mes) from each of the plurality of bit nodes that participates in the parity check computation of the parity unit circuit; a first computational logic block coupled to the memory logic block adapted to retrieve data from the memory logic block, adapted to compute a parity message (par_mes) and a corresponding sign (par_sign) of the parity message, and adapted to output the parity message and the corresponding sign for application to a bit node under control of the controller; and a second computational logic block coupled to the memory logic block adapted to retrieve data from the memory logic block, adapted to compute new values, and adapted to store the new values in the memory logic block, the second computational logic block further adapted to receive a next bit message (bit_mes) from a bit node, adapted to receive a sign of the bit message (bit_sign) from said each bit node that participates in the parity check computation of the parity unit circuit, and adapted to receive a hard decision value (bit_hard) from said each bit node, wherein said each parity unit circuit comprises the memory logic block corresponding to that parity unit circuit and wherein the memory logic block in said each parity unit circuit is dedicated to storing data pertaining to the that parity unit circuit.