1. A processor comprising: a plurality of address registers; and an instruction decoder decoding an instruction supplied thereto and providing control signals according to results of said decoding; and an execution unit responsive to the control signals and executing said instruction; wherein said instruction can include: 1) a first instruction including an operation code field defining a branch control operation, and an address field used for calculating an address for a branch, and a first register selection field for specifying one of the plurality of address registers in which said address is to be stored after it is calculated; and 2) a second instruction including an operation code field defining a branch operation, and a second register selection field for specifying one of the plurality of address registers that stores said address to be used for the branch operation.