1. An instruction altering system to be used with program and microprogram control systems having instruction storage means and address register means connected with said instruction storage means comprising: first register mean for storing an operation code for an instruction stored in said storage means which is to be altered; second register means for storing a second operation code for an instruction stored in said storage means; input means for providing an operation code of an instruction which is to be executed; comparator means connected with said first register means and said input means for comparing said first operation code and said operation code of the instruction which is about to be executed and for generating a coincidence signal when said codes coincide; and multiplexer means connected with said second register means, said input means, said comparator means and said address register means for transferring said second operation code to said address register instead of the operation code of said instruction which is about to be executed when said coincidence signal is received from said comparator means.