1. A computer system including a plurality of processors and a plurality of memories, the plurality of memories providing for storage of host memory data divided into blocks of host memory data, the processors and the memories being distributed among a plurality of individual nodes, the plurality of individual nodes being connected by an interconnection network; the host memory data being referenced by a host memory address used for locating the blocks of host memory data each stored in a memory data block host location in one or more of the nodes and located using a memory consistency protocol, the memory consistency protocol utilizing an exchange of memory consistency control packets sent between at least two of the plurality of individual nodes, each individual node comprising: A) a multiprocessor group including a plurality of the processors; B) a cache memory containing cached blocks of host memory data; C) local memories within this individual node which are included in the plurality of memories of the computer system; D) a node controller and a memory controller; E) the node controller connected to the multiprocessor group and to the memory controller, the node controller including an imported directory for tracking any block of host memory data imported to any cache memory of this individual node; F) the memory controller connected for controlling the local memories within this individual node, the memory controller including a memory controller directory, the memory controller directory providing, within each storage location of the memory controller directory, storage of a presence vector, each presence vector providing for reference to any number, from one to all, of all possible memory data block host locations; and, G) means for enabling that the memory consistency control packets exchanged between the nodes within the computer system include an item of destination information derived from the presence vector.