1. An electronic circuit, comprising: a test access protocol machine with a core address register to receive and store a core address and a signal routing control circuit to address a selected computational core, of a set of computational cores, as specified by the core address stored in the core address register and to route output test data from the selected computational core, wherein the signal routing control circuit applies control signals to a set of multiplexers and logical gates to address selected computational cores and wherein signal routing control signals control an output multiplexer to route the output test data from the selected computational core.