1. A memory cache comprising: a semi-associative cache array storing a plurality of sets, each one of the plurality of sets further comprising a first tag, a second tag, a data field, and a means for indicating the validity of the one of the plurality of the sets, the semi-associative cache array receiving a first subset and a second subset of an index, the first subset specifying a group of the plurality of sets, the semi-associative cache outputting the second tag and the data field of a selected one of the plurality of sets, the selected one of the plurality of sets being a member of the group, the first tag of the selected one of the plurality of sets being logically equivalent to the second subset, the data field of the selected one output on a plurality of bit lines; a cache reload buffer receiving a data field from an external source and a third tag, the cache reload buffer storing the third tag and the data field; and a cache reload buffer driver coupled to the cache reload buffer and to the semi-associative cache array, the cache reload buffer driver coupling the data field of the cache reload buffer to the plurality of bit lines if the third tag and a third subset of the index are logically equivalent, wherein the cache array sets the means for indicating the validity of the selected one to an invalid state upon an equivalence of the third tag and the third subset.