1. A method for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit comprising the steps of: identifying an interconnection in an integrated circuit; identifying one or more transistors in one or more channel connected regions on a driving side of said identified interconnection; identifying one or more transistors on a receiving side of said identified interconnection; extracting layout layers connected to said identified interconnection from an overall layout of said integrated circuit; extracting parasitic resistance and capacitance values for each of said extracted layout layers; and associating said extracted resistance and capacitance values for each of said extracted layout layers with said identified one or more transistors on said driving side and on said receiving side of said identified interconnection.