1. A microprocessor architecture, comprising: a trusted instruction set execution path; a secure loader that evaluates security information associated with an extension to a microprocessor base instruction set as part of a loading process, the secure loader configures a reconfigurable execution path based on the security and management information, if the security information is evaluated as safe, the reconfigurable execution path corresponding to the extension, if the security information evaluated as safe by the secure loader; a mechanism that determines when a fetched instruction is to be handled by the reconfigurable execution path or the trusted instruction set execution path; and means for dynamically disabling the reconfigurable execution path corresponding to the extension based upon a configuration change.