1. A Soft Register Unit for facilitating register access in a network device, the Soft Register Unit comprising: a Soft Register Engine having an external connection via a PCIe link; a Soft Register CPU connected to the Soft Register Engine; a first memory including an address decode table; the first memory accessible to the Soft Register Engine and the Soft Register CPU; and a plurality of registers implemented in a second memory, the second memory accessible to the Soft Register Engine, wherein, the Soft Register Unit facilitates register access by performing the steps of: receiving a raw address by the Soft Register Engine via the PCIe link; decoding the raw address by using the address decode table to locate a corresponding register; obtaining the characteristics of the register; and accessing the register in response to the characteristics of the register.