1. A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, the method comprising the steps of: input a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagate the constant nets and assign Boolean conditions to the IO arc delays and the interconnection arc delays, evaluate timing path delays and conditions for the integrated circuit design, create the integrated circuit design timing model parameters, and output the integrated circuit design timing model.