1. A computer system, comprising: a peripheral component interconnect bus including a lock signal, a stop signal and a post signal, said peripheral component interconnect bus for performing read and posted read cycles; a posting target coupled to said peripheral component interconnect bus, comprising: means for detecting a read cycle on said peripheral component interconnect bus accessing said posting target; means coupled to said detecting means and said peripheral component interconnect bus for asserting said stop and post signals to convert said read cycle to a posted read cycle; means coupled to said peripheral component interconnect bus for retrieving data requested during said posted read cycle and for providing the data on said peripheral component interconnect bus; and means for monitoring said lock signal, wherein if said lock signal is asserted in response to said assertion of said post signal during said posted read cycle, and if said lock signal is negated and reasserted during a subsequent read cycle, said retrieving and providing means asserts the retrieved data on said peripheral component interconnect bus; and a posting master coupled to said peripheral component interconnect bus; comprising: means for executing read cycles on said peripheral component interconnect bus; and means coupled to said peripheral component interconnect bus for detecting the assertion of said stop and post signals during a read cycle and for asserting said lock signal, wherein if said stop and post signals indicate said posted read cycle, said posting master asserts said lock signal and releases said peripheral component interconnect bus, and wherein said posting master subsequently executes said subsequent read cycle during which said posting master negates and then reasserts said lock signal and retrieves the data from said peripheral component interconnect bus.