1. A processing device, comprising: a store address predictor to predict an address for store operations that store data to a memory hierarchy; a store buffer communicably coupled to the store address predictor, the store buffer to buffer the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations; and a load buffer communicably coupled to the store address predictor, the load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of a respective store operation and to determine whether to speculatively forward data from the respective store operation.