1. A processor comprising: an on-die programmable architecturally-visible storage; a decode unit to receive a data access instruction of an instruction set of the processor, the data access instruction to indicate a data address that is to be associated with data to be stored in the on-die programmable architecturally-visible storage, to indicate a data size associated with the data to be stored in the on-die programmable architecturally-visible storage, and to indicate a destination storage location of the processor; and an execution unit coupled with the decode unit and the on-die programmable architecturally-visible storage, the execution unit on-die with the on-die programmable architecturally-visible storage, the execution unit operable, in response to the data access instruction, to store the data, which is associated with the data address and the data size, in the destination storage location that is to be indicated by the instruction, wherein the destination storage location comprises an architectural register of the processor.