1. An enhanced chip multiprocessor comprising: a plurality of processor cores, each of said plurality of processor cores further comprising: at least one first level (L1) cache; said at least one L1 cache including: at least one enhanced L1 cache directory entry associated with a L1 cache data line stored in said enhanced chip multiprocessor, said enhanced L1 cache directory entry including: a L1 cache owned value indicating whether said L1 cache data line is owned by the at least one L1 cache of a processor core of said plurality of processor cores; a L1 cache valid value indicating whether said L1 cache data line is valid for use by the at least one L1 cache of the processor core of said plurality of processor cores; a L1 cache modified value indicating whether said L1 cache data line has been modified; and a tag value identifying said L1 cache data line; and at least one shared second level (L2) cache, said at least one shared L2 cache communicatively coupled with each of said plurality of processor cores, said shared L2 cache further comprising: at least one enhanced second level (L2) cache directory entry associated with a L2 cache data line stored in said enhanced chip multiprocessor, said enhanced L2 cache directory entry comprising: a first level (L1) cache owned value indicating whether said L2 cache data line is owned by at least one L1 cache of a processor core of said plurality of processor cores, and a first level (L1) cache mask value, said L1 cache mask value indicating a storage state of said L2 cache data line in an L1 cache of each of said plurality of processor cores; a memory coherence protocol value identifying a state of said L2 cache data line in accordance with an associated memory coherence protocol; one or more predictor values used in conjunction with the first level (L1) cache mask value to predict the use of said L2 cache data line by at least one L1 cache of at least one of said plurality of processor cores; and a tag value identifying said L2 cache data line.