1. A processor, comprising: an instruction decode and fetch circuit (IDF) coupled to fetch an instruction stream from an external memory and having circuitry for executing the instruction stream, the IDF fetching the instruction stream by transferring a series of instruction addresses over an address bus and receiving the instruction stream over an internal bus, the IDF executing a data transfer instruction in the instruction stream by transferring a data transfer address over the address bus and transferring a data value over a data bus; cache means receiving the instruction addresses over the address bus and transferring the instruction addresses over an external address bus to the external memory, the cache means receiving the instruction stream from the external memory over the data bus and transferring the instruction stream to the IDF over the internal bus, the cache means storing an instruction from the instruction stream only if the instruction follows the data transfer instruction of the instruction stream, the cache means transferring the instruction that follows the data transfer instruction to the IDF over the internal bus after the IDF executes the data transfer instruction.