1. A method for optimization of a library for use in circuit design, the method comprising: providing an initial circuit netlist; providing one or more sets of existing cells; providing one or more sets of additionally admissible cells; analyzing the initial circuit netlist to find cells that reduce implementation costs considering the initially existing set of cells and the additional set of admissible cells; and outputting one or more new cell library specifications and descriptions comprising a subset of the preexisting cells and a subset of the admissible cells which potentially reduce design costs.