1. An apparatus, comprising: a plurality of thread units to concurrently execute a plurality of threads, each of the plurality of thread units being capable of executing a checkpoint write instruction; and a memory storage area to store a first data for a checkpoint write instruction encountered during execution of one of the plurality of threads, the first data corresponding to content data being written by the checkpoint write instruction; wherein the memory storage area is also to store a second data for the checkpoint write instruction, the second data having a state indicative of the execution status of the checkpoint write instruction responsive to the execution of the checkpoint write instruction.