1. A memory repair system comprising: an integrated circuit configured to receive at least first, second and third signals on first, second and third external pins, respectively, comprising: a memory array; redundant circuit elements coupled to fuses and to the third external pin and configured to enable the fuses to be blown responsive to the third signal being asserted; and a repair controller coupled to the first and second external pins and configured to generate at least one internal repair command responsive to the first and second signals wherein the at least one internal repair command causes at least one memory location in the memory array to be permanently repaired by blowing at least some of the fuses.