1. A device comprising: a first register, a second register, a third register, a fourth register and a fifth register, at least one input terminal to receive binary pieces of data to be stored in these registers, a first multiplication circuit that performs a multiplication operation between two pieces of data stored in the first and third registers, a second multiplication circuit that performs a multiplication operation between two pieces of data stored in the first and fourth registers, a first addition circuit that performs operations of addition between a piece of data stored in the second register and a piece of data produced by the first multiplication circuit, a second addition circuit that performs an operation of addition between a piece of data produced by the first addition circuit and a piece of data given to the second addition circuit by the second multiplication circuit, a delay cell to delay the supply to the second addition circuit of the piece of data given by the second multiplication circuit, multiplexing means that selectively supplies, to inputs of the first addition circuit, the contents of the second register or a permanent logic state, the connection of an input of the second multiplication circuit to an output of the first register, the connection of the output of the first multiplication circuit to one of the registers and the supply to the second addition circuit of a piece of data produced by the first addition circuit or a permanent logic state.