1. A processor that stores, in a bit vector within the processor, results of a comparison between values in a first set of SIMD subregisters and values in a corresponding second set of SIMD subregisters: wherein the first set of SIMD subregisters are contiguous in a first SIMD register; wherein the second set of SIMD subregisters are contiguous in a second SIMD register; wherein the processor is configured to respond to one or more instructions by: setting a bit in the bit vector to “1” for each subregister, in the first set of SIMD subregisters, that stores a value that satisfies a comparative operator with respect to the value stored in a corresponding subregister, of the second set of SIMD subregisters.