1. A processor disposed on a single integrated circuit operable in response to microinstructions, said processor comprising: a microaddress sequencer generating a next microaddress; a read only microinstruction memory circuit coupled to said microaddress sequencer, said microinstruction memory circuit storing a plurality of original microinstructions fixed upon manufacture at corresponding microaddresses and operable to output an original microinstruction stored at a microaddress received from said microaddress sequencer in response to a request signal; a cache memory circuit simultaneously both caching a first type of information different from microinstructions and also storing at least one patch microinstruction, said cache memory circuit coupled to output at least said first type of information and to output a patch microinstruction in response to the request signal; and selection circuitry coupled to said microinstruction memory circuit and said cache memory circuit for selecting for control of the processor for a next cycle between the original microinstruction recalled from said microinstruction memory circuit and the patch microinstruction recalled from said cache memory circuit.