1. A dual modular redundant processor apparatus for assuring data integrity, said apparatus comprising: first and second processor means for respectively producing true and complement operating signals in the absence of any abnormal condition in the dual modular redundant processor apparatus; internal system bus means coupled to the first and second processor means for comunicating the operating signals; means for producing a periodic clock signal; synchronizer means coupled to the internal system bus means for synchronizing leading edges of true and complement pairs of the operating signals produced by said first and second processor means, the synchronizer means including means responsive to the periodic clock signal for cyclically sampling the true and complement pairs of the operating signals, and output means coupled to the sampling means and responsive to the clock signal for producing synchronized operating signals having synchronized leading edges and corresponding to the true and complement pairs of the operating signals; checker means responsive to the synchronized operating signals for determining whether complementation exists therebetween, said checker means generating a dual-railed error signal in the event of absence of such complementation; and error detector means for receiving the error signals from said checker means, said error detector means generating and transmitting to each of said first and second processor means an error detected signal, whereby said first and second processor means can take appropriate action in response to the true and complement operating signals being detected as not having the predetermined logical relationship.