1. A logic circuit comprising: a latch having N bits of a data word in N bit positions including a first and a second group of bit positions; a first comparator circuit comparing data in the first group of bit positions to data in the second group of bit positions and generating a first determination value; a second comparator circuit comparing the data in the second group of bit positions to a result of a first logical operation performed on the data in the first group of bit positions and the data in the second group of bit positions, the second comparator circuit generating a second determination value; a leading zero counting circuit performing a leading zero count on a result of a second logical operation performed on the data in the first group of bit positions and the data in the second group of bit positions, the leading zero counting circuit generating a leading zero count value; and a logic gate operable to receive the first determination value and the second determination value, the logic gate generating a single bit correction value.