1. A zero-flag generator for digital adder with n-bits of input data including a one-bit input carry signal for producing output sum signal and an output carry signal comprising: means for detecting said output sum no later than the production of said sum from said adder, comprising: a plurality of logic combinations of only Exclusive-OR (XOR) gates and AND gates: having individual inputs for each of said bits which are the same as the individual inputs for the corresponding bits of said adder for outputting the logic combination signals XORi and ANDi, where i=0,1,. .. ,n-1, for each of said bits, and a decoder for decoding the outputs of said logic gate combinations with an carry to generate a zero-flag in accordance to the number of combinations of said input carry and said logic combination signals for said zero-flag to be zero.