1. A microprocessor for executing a floating point exchange micro instruction sequence, the floating point exchange micro instruction sequence exchanging contents of a first location and a second location, the microprocessor comprising: register/control logic, for receiving the floating point exchange micro instruction sequence, for determining that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and for providing a signal indicating said dependency; interlock logic, coupled to said register/control logic, for receiving said signal from said register/control logic, and for forwarding a new target location to said preceding floating point micro instruction if said signal indicates said dependency; and target location modification logic, coupled to said interlock logic, for receiving said new target location, and for providing said new target location to said preceding floating point micro instruction; wherein forwarding of said new target location by said interlock logic allows the floating point exchange micro instruction sequence to execute without resolution delay.