1. A computer implemented method for designing an integrated circuit, the method comprising: receiving a netlist; receiving physical layout information related to an integrated circuit based on the netlist; receiving an engineering change order (ECO) that adds at least one logic gate to the physical layout; forming two or more possible solutions to achieve the ECO; ranking the two or more possible solutions based on two or more factors to obtain a highest ranked solution; and selecting the highest ranked solution; wherein ranking includes determining that a tie between solutions exists and the tie is broken based, in order, on scores for routing congestion, timing, placement density and cell density.