1. A method for using a micro-op cache in a processor, the method comprising: performing a tag match in a tag match unit of the micro-op cache for an instruction pointer received in the tag match unit to retrieve a first set of micro-op cache line access tuples having matching tags, each of the first set of micro-op cache line access tuples having a tag and an offset; storing the first set of micro-op cache line access tuples in a match queue to store up to N micro-op cache line access tuples per cycle, wherein N is greater than 1; and concurrently accessing a first plurality of cache lines in a micro-op cache data array responsive to the first set of micro-op cache line access tuples from the match queue to retrieve a second plurality of micro-ops from the micro-op cache data array.