1. A hardware structure for implementing a method for designing public key cryptosystems against fault-based attacks, comprising: a plurality of encoders for encoding input messages into codewords; a plurality of error-checking components for respectively performing error-checking operations to check the respective codewords generated by the respective encoders; a multiplier for performing a multiplication operation on the checked codewords respectively from the error-checking components; an error-checking element for performing an error-checking operation to check the multiplication result; and a decoder for decoding the multiplication result from the multiplier.