1. A non-volatile memory cell array, comprising: a plurality of electrically active regions; a plurality of field oxide layers; a first floating gate sequentially stacked on the plurality of field oxide layers, the first floating gate and the plurality of field oxide layers being formed on the electrically active regions; a second floating gate electrically connected to the first floating gate, the second floating gate having a width that extends to adjacent field oxide layers, slanted side walls that are narrower at an upper surface, and a height from the plurality of field oxide layers to the upper surface that is larger than the width; a dielectric layer formed on the second floating gate; and a continuous control gate formed on the dielectric layer.