1. An anti-fuse magnetic tunnel junction (MTJ) memory, comprising: a pinned layer directly connected to a bit line; a free layer directly connected to a drain of an access transistor, the source of the access transistor being coupled to ground; a tunnel barrier layer coupled between the pinned layer and the free layer; and a programming driver configured to drive the bit line with a programming voltage while the access transistor conducts to drive a magnetization for the free layer and the pinned layer into an anti-parallel state, wherein the programming driver is further configured to drive the anti-fuse MTJ memory cell with the programming voltage so as to break down the tunnel barrier layer after the magnetization switches into the anti-parallel state.