1. An apparatus comprising a block-based processor, the block-based processor comprising: one or more processing cores configured to fetch and execute a plurality of instruction blocks; and a control unit configured, based at least in part on receiving a nullification instruction, to: obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction; nullify the memory access instruction associated with the instruction identification, wherein the memory access instruction is in a first instruction block of the plurality of instruction blocks; and based on the nullified memory access instruction, execute a subsequent memory access instruction from the first instruction block.