1. A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength, characterized by the steps of: detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have the target register address as one of its sources; adding a so-called “extract” instruction into an instruction stream before the smaller bitlength instruction, the extract instruction comprising the following steps of: a. dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station; b. issuing the extract instruction to an Instructional Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme; c. executing the extract instruction by an available IEU; d. setting an indication that the result of said instruction needs to be written into the result field of the instruction following the extract instruction, and; e. writing the extract instruction result into the result field of said first instruction, and into all fields of operands being dependent of said first instruction.