1. A method for implementing coherent accelerator function isolation for virtualization in a hardware input/output (IO) adapter in a computer system, said computer system including a processor; and a hypervisor managing functions associated with the hardware I/O adapter; said method comprising: providing the hardware I/O adapter with a coherent accelerator including an interface services layer providing Partitionable Endpoint (PE) functions and multiple accelerator function units (AFUs); enabling each AFU to operate independently of the other AFUs to perform a computing task; enabling each AFU to access system memory bound to an application and to make one or more copies of said system memory bound to the application within the AFU; enabling each AFU to maintain synchronization between AFU memory-cache and processor memory-cache; enabling individual ones of said AFUs to operate as Peripheral Component Interconnect Express (PCIE) endpoint functions, and using a PCIE root port to associate Memory-mapped IO (MMIO) address ranges, Direct Memory Access (DMA) address ranges, and Message Signaled Interrupt (MSI) address ranges with PCIE requester IDs (RIDs) to associate address ranges with individual said accelerator function unit (AFU).