1. A method for speculatively executing instructions in a microprocessor which commits results of non speculative instructions to at least one architected facility, said method comprising the steps of: determining the occurrence of a stall condition during the execution of said instructions; speculatively executing instructions during said stall condition across multiple pipeline stages; determining the validity of data utilized during said speculative execution; maintaining said data in a non-architected facility when said speculatively executing instructions pass a last of said multiple pipeline stages; and retrieving valid data for use by said non speculative instructions upon removal of said stall condition.