1. An apparatus, comprising: a plurality of memory cells, wherein the plurality of memory cells includes a first subset of memory cells configured to store data and a second subset of memory cells, wherein each memory cell of the second subset of memory cells is configured to generate a respective reference voltage; and circuitry coupled to the plurality of memory cells, wherein the circuitry is configured to: initiate a read of a first memory cell of the first subset of memory cells; initiate a read of a second memory cell of the second subset of memory cells; determine a first voltage dependent upon charge stored in the first memory cell, wherein the first voltage is determined at a first point in time after the initiation of the read of the first memory cell; determine the respective reference voltage of the second memory cell at the first point in time after the initiation of the read of the first memory cell; determine first data dependent upon a comparison of the first voltage and the respective reference voltage; and determine a second voltage dependent upon the charge stored in the first memory cell responsive to a determination that the first data contains an uncorrectable error, wherein the second voltage is determined at a second point in time after the initiation of the read of the first memory cell, wherein the second point in time is after the first point in time.