1. A radix-2 k Montgomery multiplier comprising: an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus, and the sum, and to divide and to output the received previous sum into units of k bits; an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and the sum by summing the partial product, the multiple modulus and the previous sum; and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum.