1. An method to transform a conditional state element, into a logically redundant element in a digital circuit design comprising: coupling a first latency delay unit to a data input of the conditional state element; coupling a second latency delay unit to an enable input of the conditional state element; coupling a first input of a multiplexer to an output of the conditional state element; coupling a second input of the multiplexer to the data input of the conditional state element; and coupling a select line of the multiplexer to the enable input of the conditional state element.