1. An arithmetic logical unit array, comprising: at least two data registers for storing data; a plurality of fixed instruction registers for storing machine code instructions; at least one programmable instruction register configured to store instruction data being representative for a machine code instruction; a selection circuit configured to select one of the machine code instruction from the plurality of fixed instruction registers or the machine code instruction represented by the instruction data; and an arithmetic logical unit configured to apply an operation in accordance with the machine code instruction selected by the selection circuit to the data stored in the data registers.