1. A system for executing a delay instruction in a data processor, comprising: an interface circuit for receiving and decoding the delay instruction, the delay instruction having a first portion for indicating a delay value of the delay instruction; and a central processing unit for executing the delay instruction, the central processing unit, comprising: a register having an input coupled to the interface circuit for receiving the delay value, the register storing the delay value therein; a count detect circuit coupled to the register to receive the delay value, the count detect circuit testing the delay value to provide a tested output signal to indicate whether the delay value is equal to a first predetermined value; and an arithmetic logic unit coupled to the register to receive the delay value, the arithmetic logic unit decrementing the delay value by a second predetermined value to provide a decremented delay signal when the tested output signal indicates that the delay value is not equal to the first predetermined value the central processing unit terminating execution of the delay instruction when the delay value is equal to the first predetermined value.