1. A logic circuit for determining a numerical value representing a number of leading zero count value in a binary input data word, the logic circuit comprising: a latch having a binary input data word, the binary data word includes random bits stored in bit positions of the binary input data word, wherein the bit positions include a least significant bit positions and a most significant bit positions and, wherein, the binary input data word is divided into two halves, one half containing odd numbered bits, while the other half contains even numbered bits; a first comparator circuit for comparing data in the odd numbered bits of the binary input data word to data in the even numbered bits of the binary input data word; a second comparator circuit for comparing the data of the odd numbered bits to a result of a first logical operation performed on the data of the odd numbered bits and the data of the even numbered bits, wherein the comparison is based on a determination of whether the result of the first logical operation is less than the data in the odd numbered bits; a leading zero counting circuit for performing a leading zero count on a result of a second logical operation performed on the data of the even numbered bits and the data of the odd numbered bits, wherein, the leading zero counting circuit generates a number of leading zero count value based on the leading zero count; and a logic gate configured to calculate a single bit value based upon the outputs of the first comparator circuit and the second comparator circuit, wherein, the logic gate generates a single bit correction value, based on the calculated single bit value, the logic gate concatenates the single bit correction value generated by the logic gate to the number of leading zero count value generated by the leading zero counting circuit to provide the numerical value representing the number of leading zero count value in the binary input data word.