1. A microprocessor, comprising: a plurality of dies, each die comprising: a plurality of cores; and a phase-locked loop (PLL), having a frequency ratio input, wherein the PLL is configured to generate a core clock signal for provision to each of the plurality of cores of the die, wherein the core clock signal has a frequency that is a ratio of a frequency of a bus clock signal received by the microprocessor based on a value of the frequency ratio input; wherein each core is configured to generate a first frequency ratio value that indicates the desired frequency ratio of the core and to receive the first frequency ratio value from the other cores of its die and to generate a second frequency ratio value which is the largest of the first frequency ratio values of all the cores of the die; and wherein each core is configured to provide the second frequency ratio value to the PLL if the core is a master core of the die and to provide a zero value to the PLL if the core is not a master core of the die.