1. A processor comprising: event detection logic to detect a raw event; user-programmable event logic coupled to the event detection logic, wherein user-programmable event logic includes a user-programmable event register for storing a user-defined trigger event, the user-defined trigger event to be based on at least the raw event; user-programmable context control logic to specify a weight of a context to be saved; trigger response logic coupled to the user-programmable event logic and the event detection logic to monitor for the user-defined trigger event in response to receiving a user marking instruction; and thread switch logic coupled to the trigger response logic and the user-programmable context control logic, wherein the thread switch logic, in response to the user-defined trigger event being detected by the trigger response logic, to save a portion of a first context based on the weight of a context to be saved that is specified in the user-programmable context control logic and to switch the portion of a helper thread context with the portion of the saved first context without operating system intervention.