1. A flash memory device comprising: a memory cell array configured to store N-bit read data, where N is a positive integer; a page buffer circuit comprising a page buffer configured to receive read data from the memory cell array during a read operation, wherein the page buffer comprises a main register transferring read data to a cache register during the read operation; and a control logic block configured to control operation of the page buffer during the read operation such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.