1. A data processing system comprising a central processor unit for processing address words and data words and one or more memory units for storing address words and data words, said central processor unit including a skew protected quadriport register file having first and second read ports and first and second write ports; an arithmetic-logic unit for performing arithmetic and logical operations on input information supplied thereto and having a pair of inputs, and an outut; a shifter unit for supplying a shifted output therefrom to said register file and having an input and an output; the first read port of said register file connected to one of said pair of inputs of said arithmetic-logic unit; the second read port of said register file connected to the other of said pair of inputs of said arithmetic-logic unit and to the first write port of said register file; and a memory address register separate from said register file for supplying addresses to said one or more memory units; the output of said arithmetic-logic unit being connected to the input of said memory address register and to the input of said shifter unit, the output of said shifter unit being connected to the second write port of said register file for writing the shifted logic unit result into the register file.