1. A processor, comprising: a module configured to collect status data from media access devices connected to a bus, the status data indicating readiness of the media access devices to participate in data transfers, the status data comprising data indicating whether a one of the media access devices has received packet data; one or more processing engines to schedule transfers of packet data; and a push engine to perform unsolicited transfers of the status data to the processing engines in response to the module collecting new status data.