1. An apparatus for extending a microprocessor instruction set, comprising: translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for directing that an architectural extension be employed in the execution of an operation prescribed by said extended instruction; and an extended instruction tag, for indicating said extended instruction prefix, wherein said extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for employing said architectural extension in the execution of said operation.