1. A hardware accelerator comprising: at least one processor; and a non-transitory processor-readable memory device storing instructions that when executed by the at least one processor causes the at least one processor to perform operations including: generating and processing a bitmap data structure, wherein the bitmap data structure comprises information for multiple heterogenous lists including a first list of objects in a first format and a second list of objects in a second format different from the first format, and the bitmap data structure removes the need to maintain and process different bitmap data structures for the multiple heterogenous lists for reducing computational costs; and processing population counts for data and aggregating the population counts; wherein the bitmap data structure comprises a single fixed sized array periodically interleaved with a plurality of aggregated population count fields and a plurality of bitmap fields, a first end of the single fixed sized array appended along a first direction with one or more bit values corresponding to one or more objects of the first list of objects in the first format, a second end of the single fixed sized array opposite to the first end appended along a second direction opposite of the first direction with one or more other bit values corresponding to one or more objects of the second list of objects in the second format, and each aggregated population count field indicative of a number of objects from a start of the bitmap data structure up to the aggregated population count field that are in the first format.