1. An add circuit for adding an addend and an augend and generating a final sum, the addend, augend, and final sum each being binary numbers having a plurality of bits, the bits of the same order in the addend and the augend forming columns, the add circuit comprising: at least one data reduction circuit, each data reduction circuit comprising at least one multi-column adder, the at least one data reduction circuit being for using the columns of addend and augend bits to generate a reduced addend and a reduced augend, the reduced augend having fewer bits than the augend; and a generate/propagate calculation circuit coupled to the at least one data reduction circuit for using the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation circuit having a number of stages, the number of stages being fewer than required to calculate generate and propagate data using the addend and the augend.