1. A processor comprising: an arithmetic unit configured to execute instructions; an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes; an interrupt register configured to receive an interrupt signal; and a sequencer configured to store a series of instructions to be processed by continuous instructions included in the instructions, wherein the sequencer outputs the series of instructions to the instruction decode part in response to the instruction decode part detecting the continuous instructions, wherein the instruction decode part comprises an instruction code map that is configured to store the opcodes in correspondence to instructions and to output the opcodes in accordance with the instructions inputted, and the instruction code map is further configured to store a plurality of opcodes to be output to a second arithmetic unit as switch opcodes corresponding to additional instructions, the additional instructions being a part of the instructions, and to switch the plurality of the switch opcodes in accordance with the interrupt signal.