1. A shared register system for a dual-instruction-set processor, the shared register system comprising: a shared register for storing information to be transferred between a first user program comprised of instructions from a first instruction set and a second user program comprised of instructions from a second instruction set, the first instruction set having a first encoding of operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes; a first decoder, coupled to the shared register, for accessing the shared register from the first instruction set, the first decoder writing information into the shared register responsive to a first subset of instructions from the first instruction set; and a second decoder, coupled to the shared register, for accessing the shared register from the second instruction set, the second decoder reading information from the shared register responsive to a second subset of instructions from the second instruction set, wherein the shared register is in a plurality of general-purpose registers in the dual-instruction-set processor, the source field and the destination field selecting any one register in the plurality of general-purpose registers, the one register selected being the shared register for transferring information between the first user program and the second user program; whereby information is transferred from the first user program to the second user program using the shared register.