1. A processor comprising: a prediction unit to predict whether a load operation to load data from a memory address will conflict with an older pending store operation to store data to the memory address; a watchdog unit to disable the prediction unit if the prediction unit mispredicts whether the load operation will conflict with the older pending store operation based on a ratio of a first counter value and a second counter value reaching a threshold value, wherein the first counter corresponds to a watchdog disambiguation counter to be incremented in a response to correct predictions and the second counter corresponds to a flush counter that is to be decremented in response to misprediction of whether load operations and store operations will conflict with each other.