1. A processor comprising: a storage area to store a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in said first plurality of data elements corresponds to a data element in said second plurality of data elements, in a respective position; a decoder to decode a pack instruction; and a circuit, coupled to said storage area and said decoder, said circuit simultaneously copies a part of each data element in said first and second plurality of data elements into said storage area as a third plurality of separate data elements in a third packed data in response to the pack instruction.