1. A data processing apparatus comprising: instruction fetching circuitry configured to fetch data representing program instructions from memory, each of said program instructions being from one of a plurality of sets of instructions including at least a first set of instructions and a second set of instructions and each program instruction within said fetched data comprising one or more blocks to be pre-decoded, each block of an instruction fetched from memory representing a portion of a program instruction; pre-decoding circuitry configured to pre-decode said blocks to generate pre-decoded instructions; a cache configured to store said pre-decoded instructions; decoding circuitry responsive to said pre-decoded instructions within said cache to generate control signals; and processing circuitry responsive to said control signals to perform processing operations; wherein: said pre-decoding circuitry: speculatively identifies which portion of an instruction a block fetched from memory represents; and performs a pre-decoding operation on said block; and for at least one portion of an instruction from said first set of instructions and at least one portion of an instruction from said second set of instructions, said pre-decoding operation performed on a block fetched from memory is independent of whether said pre-decoding circuitry has speculatively identified said block as representing said at least one portion of an instruction from said first set of instructions or said at least one portion of an instruction from said second set of instructions.