1. A programmable logic device, comprising: an internal three-statable bus; a plurality of driving elements coupled to the internal three-statable bus, each driving element operable to drive the internal three-statable bus; and a plurality of interface logic circuits, each of the plurality of interface logic circuits coupled to a different one of the plurality of driving elements, each interface logic circuit operable to determine whether the internal three-statable bus is being driven, the interface logic circuits collectively operable to prevent contention of signals on the internal three-statable bus.