1. A floating point comparator circuit for comparing a plurality of floating point operands, comprising: a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands; and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands.