1. A non-volatile memory (NVM) device, comprising: a) an interface configured to receive write and read commands from a host; b) a memory array comprising a plurality of NVM cells arranged in a plurality of array planes; and c) a memory controller configured to execute a write operation on a first of the plurality of array planes in response to the write command, and to execute a read operation on a second of the plurality of array planes in response to the read command, wherein the memory controller is configured to suspend the write operation in response to detection of the read command during execution of the write operation, and wherein the memory controller is configured to resume the write operation after the read operation has at least partially been executed.