1. A processor unit for shuffling data comprising: a register file including a plurality of registers to store data; an execution unit operative to receive from the register file a set of source data elements and a set of L control elements being in the form of L shuffle masks, wherein each of said L control elements is associated with a data element position in a resultant and is divided into a plurality of portions: a first portion being a flush field operative to indicate a flush to zero indication, a second portion being a position selection field operative to indicate a position of one of said source data elements, and a third portion being a reserved field for a special use; said execution unit is also operative to: determine whether the flush to zero indication is set for each individual control element, and place a zero into an associated resultant data element position if true, otherwise shuffle data from a data element of the set of source data elements designated by said individual control element to said associated resultant data element position.