1. A method for designing a multi-design integrated circuit die containing multiple designs, the method comprising the steps of: a) generating a netlist for each of the multiple designs; b) generating a pin-pad assignment list for each of the multiple designs; c) consolidating pin-pad assignment lists generated in step b); d) consolidating netlists generated in step a); and e) generating a layout for the multi-design integrated circuit die in which bi-directional I/O buffers are shared by the multiple designs.