1. A method for implementing enhanced scan data testing of a chip using an XOR network comprising: providing a first scan channel and a second scan channel; and said first scan channel and said second scan channel including a plurality of scannable latches providing input data to logic circuits on a chip and receiving output data from logic circuits on the chip; providing the XOR network with a respective first exclusive or (XOR) for hashing output data from the scannable latches on the first scan channel and the second scan channel, and providing a respective second exclusive or (XOR) coupled to respective first exclusive or (XOR) on the first scan channel and the second scan channel to hash output data from the respective first exclusive or (XOR); said respective second exclusive OR (XOR) coupled to respective first exclusive or (XOR) on the first scan channel and the second scan channel for processing hashed output data of said respective first exclusive or (XOR) on the first scan channel and the second scan channel; applying scan data to the first scan channel and the second scan channel using the XOR network and unloading output scan data to output pins; identifying a list of possible faults based on pin state changes, prioritizing the possible faults by a number of occurrences in the list and running diagnostic simulation by prioritized possible faults during diagnostic isolation; and further grading the possible faults to reduce possible faults requiring simulation and running diagnostic simulation by prioritized possible faults by grading during diagnostic isolation.