1. A computer-implemented method comprising: receiving a design identifying operations to be performed by a programmable logic device (PLD); and synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises: detecting an incrementer-multiplier operation in the design, and merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components, wherein the merged incrementer-multiplier operation comprises at least two addition operations configured to operate substantially in parallel.