1. A system comprising: a processor including a memory comprising a line to hold at least a portion of a data item in a buffered state in response to the data item being transactionally written, control logic coupled to the memory to provide a hit response responsive to a local access request to the line in the buffered state and to provide a miss responsive to a non-local access request to the line in the buffered state; and an input/output (I/O) device coupled to the processor, wherein: the control logic is further to transition the line from the buffered state to an invalid state responsive to the non-local access request to the line in the buffered state; and the control logic is further to transition the line from the buffered state to a modified state responsive to perform a commit operation for the line.