1. A method, comprising: designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors; determining a critical current sensitivity parameter for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus; distributing the cell mismatch parameter across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter; and simulating the memory cell based on the individual transistor mismatch parameters to generate a simulation result.