1. A circuit comprising: a decode logic circuit; a buffer coupled to the decode logic circuit; a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, the positive level shifter coupled between a high positive voltage and a reference voltage; a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer, the negative level shifter coupled between a low positive voltage and a negative voltage; and an enable circuit coupled to the negative level shifter, the enable circuit configured to during a first mode of operation, disable the negative level shifter and enable the positive level shifter, and during a second mode of operation, enable the negative level shifter.