1. A configurable computing element selectively realizing a first or second math function, comprising: a semiconductor substrate including transistors thereon; at least first and second three-dimensional printed memory (3D-P) arrays stacked above said semiconductor substrate, wherein said first 3D-P array stores at least a first portion of a first look-up table (LUT) for said first math function, and said second 3D-P array stores at least a second portion of a second LUT for said second math function; at least a configurable interconnect coupling with said first and second 3D-P arrays, wherein said configurable computing element selectively realizes said first or second math function depending upon at least a configuration signal on said configurable interconnect.