1. An apparatus, comprising: a storage array containing a plurality of addressable storage locations; a write pointer coupled to the storage array to point to a first one of the storage locations as an input address; a first read pointer coupled to the storage array to point to a second one of the storage locations as a first output address; a second read pointer coupled to the storage array to point to a third one of the storage locations as a second output address; a first clock coupled to the storage array to clock write data into the storage array at the input address; a second clock coupled to the storage array to clock read data from the storage array at the first output address; and a third clock coupled to the storage array to clock read data from the storage array at the second output address.