1. A processor-implemented method for the synthesis of a hardware description language (HDL) design, comprising: mapping a design into a plurality of interconnected hardware components; identifying a first subset of the hardware components that match a logic pattern; replacing the first subset of the hardware components with a first instance of an inferred hardware component associated with the logic pattern; wherein the inferred hardware component contains hardware to implement the logic pattern and additional un-utilized hardware components; and for each additional hardware component of the plurality of hardware components that is connected to a hardware component in the first subset: determining whether or not the additional un-utilized hardware components are sufficient to implement the additional hardware component within the first instance; and in response to determining the additional un-utilized hardware components are sufficient to implement the additional hardware component in the first instance, transforming, by a processor, the mapped design to implement the additional component by the additional un-utilized hardware components within the first instance.