1. A method of utilizing high level synthesis to automatically configure control logic elements of a hardware design for a pipelined parallel stream processor, the method comprising: obtaining a scheduled graph representing a processing operation in a time domain as a function of clock cycles, the scheduled graph comprising at least one data path to be implemented in hardware as a part of said pipelined parallel stream processor and comprising at least one input, at least one output, a plurality of functional objects and a plurality of parallel branches configured to enable data values to be streamed therethrough from the at least one input to the at least one output as a function of increasing clock cycle; grouping functional objects having a cycle position into groups of functional objects dependent upon common factors; allocating logic control elements which are common to said groups of functional objects; and utilizing, on a computing device, said scheduled graph and said allocated control logic elements to define an optimized hardware design for implementation in hardware as said pipelined parallel stream processor.