1. A method comprising: identifying cells with at least one timing arc from a set of cells, wherein the set of cells are useable in an integrated circuit design; generating a test circuit comprising an input stage sub-circuit for each terminal serving as an input for each of the identified cells, and an output stage sub-circuit for each terminal serving as an output for each of the identified cells, wherein each input stage sub-circuit is independent of each other input stage sub-circuit, and each output stage sub-circuit is independent of each other output stage sub-circuit; and storing the test circuit for use in a timing delay correlation operation between a first timing analysis process and a second timing analysis process; wherein the identifying, generating and storing steps are performed by at least one processing device and at least one memory operatively coupled to the processing device.