1. An apparatus for logic simulation, comprising: storage including a library to define how a net-list is to be synthesized by a synthesis tool; a data-driven logic verification chip comprising a plurality of logic processors, wherein the data-driven logic verification chip comprises a plurality of logic simulation engines, each of the plurality of logic simulation engines comprising: a routing unit, wherein the routing unit is configured to execute a routing algorithm wherein a header of a routed packet includes offsets in an X direction and a Y direction and the packet is determined to reach its destination when both offsets are equal to zero; an instruction memory; a respective one of the plurality of logic processors; and a data memory; and a code generator to adopt one or more heuristics to convert the net-list into data driven logic programs and to allocate hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.