1. A storage array, comprising: a plurality of sub-arrays configured to provide a register for each thread of a plurality of threads, each sub-array configured to store one bit of the register for each thread, and each sub-array comprising: storage cells configured in an array of rows and columns, wherein each storage cell is associated with a different thread of the plurality of threads and stores one bit of data; a read multiplexer coupled to the storage cells and configured to output a global read bit line selected from local read bit lines output by the storage cells; read drivers, each read driver coupled between a read bit line precharge and one of the columns; and write drivers, each write driver coupled between a global write bit line and one of the columns, and configured to write the global write bit line to the storage cells for each thread of the plurality of threads.