1. An apparatus including a configurable demodulation architecture comprising: a tangible, non-transitory computer-readable memory; a plurality of modules comprising processor executable code stored in the memory; a processor connected to the memory and configured to access and execute the following: a control module including a set of control fields including indications of a transmit mode used to transmit a signal to be demodulated and a modulation order, wherein the control module is configured to determine whether Multiple Input Multiple Output (MIMO), Single Input Multiple Output (SIMO), or Space Diversity Multiple Access (SDMA) is utilized; a Fast Fourier Transform (FFT) sample server configured to provide FFT symbol data; and a demodulation engine configured to receive the FFT symbol data, including: a spatial whitening module configured to process the FFT symbol data to provide whitened FFT data; a Minimum Mean Square Estimation (MMSE) module configured to receive the whitened FFT data; at least two Maximal Ratio Combining (MRC) modules configured to receive the whitened FFT data; and at least two multiplexers coupled to the control module and controlled based on the control fields to direct the data flow from the MMSE module and the MRC modules.