1. A system for emulating a circuit design, the system comprising: a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design, wherein the emulation interface is configured to provide timing and control information for at least the verify; and computer readable storage medium comprising instructions, which when executed cause the host workstation to: compile a portion of the circuit design and an associated verification module adapted to configure the FPGA, wherein the compilation is in accordance with a description file.