1. An apparatus, comprising: a pointer memory configured to store a free list that includes a plurality of pointers that each point to an address in a memory that is unallocated; a memory controller configured to manage a linked list using pointers from the plurality of pointers stored in the free list, wherein pointers of the linked list are assigned from the plurality of pointers and reference data of a single network packet stored in the memory, and wherein the memory controller manages a separate linked list for each network packet of a plurality of network packets, wherein the memory controller is configured to, in response to a memory access request for a portion of the single network packet, traverse the linked list using the pointers of the linked list to access the portion that is referenced by at least one of the pointers of the linked list and modify the portion according to the memory access request; a list memory configured to store the linked list; and a descriptor memory configured to store a descriptor of the linked list in a queue that is an on-chip memory of the apparatus, wherein the descriptor includes a head pointer that references a first entry of the linked list, a tail pointer that references a final entry of the linked list and a pointer count that indicates a number of pointers in the linked list for the network packet, and wherein the descriptor memory includes descriptors for network packets that are ingressing and network packets that are egressing the apparatus.