1. A memory system connectable to a host device, the host device including a memory, the memory system comprising: a host interface configured to receive a read command and a write command; a first non-volatile memory configured to store data transmitted by the host device; and a memory controller configured to control the first non-volatile memory, the memory controller being configured to read, from the first non-volatile memory, data that corresponds to the read command, transmit the read data to the host device through the host interface, and write data that corresponds to the write command to the first non-volatile memory, wherein the memory controller includes: a debug unit configured to collect debugging information; and a processor configured to execute firmware to control the memory system, the firmware having a function of receiving a debug command and a function of setting a buffer address to the debug unit, the buffer address indicating a buffer area allocated on the memory in the host device, wherein the debug unit is capable of outputting the debugging information to the buffer area through the host interface when the processor executes the firmware, the debug unit acquires, as a command fetch address, a command that satisfies predetermined conditions among commands output from the processor, and when a change in the command fetch address is greater than a threshold value, the debug unit inserts the command fetch address and a timer value into the debugging information and transmits the debugging information to the host device, the timer value being date and time that the command fetch address had been acquired.