1. A method of processing instructions of multiple instruction streams in a processor core having a plurality of instruction execution slices, the method comprising: by a compiler that generates program code of the multiple instruction streams or a scheduler that pre-processes program code of the multiple instruction streams to allocate resources to hardware threads corresponding to the multiple instruction streams, the compiler or scheduler analyzing the multiple instruction streams and detecting, prior to execution of a first instruction in a first one of the multiple instruction streams, an event indicating that the first instruction requires processing that changes resource availability for execution of a subsequent instruction of the first instruction stream or that the subsequent instruction has execution requirements such that a change in mapping between the instruction execution slices and corresponding ones of the multiple instruction streams is indicated; and responsive to detecting the event, the compiler or the scheduler modifying the first one of the multiple instruction streams by inserting a directive in the first one of the multiple instruction streams, wherein the directive, when executed by another processor core will cause the change in mapping so that at least a portion of the subsequent instruction is dispatched to a selected one of the instruction execution slices that was assigned to a second one of the multiple instruction streams during a previous execution cycle.