1. A memory recessed MOS transistor device, comprising: a resistive switching device; a recessed MOS transistor device comprising: a semiconductor substrate; a gate formed at least in part in a recess in a top surface of the semiconductor substrate and having a feature size in a direction parallel to the top surface of the semiconductor substrate that is less than about 100 nm; a dielectric material between the gate and the semiconductor substrate; and a source region on a first side of the gate and a drain region on an opposing side of the gate, wherein at least one of the source region and drain region is connected to the resistive switching device, and wherein the recessed MOS transistor device and the resistive switching device form a 1T-1R memory device and wherein the recessed MOS transistor device has a channel length, characterized by a length of a conductive path between the source region and the drain region, that is a function of the feature size and a depth of the recess and is less than or equal to about 430 nanometers (nm), and wherein the recessed MOS transistor device is a high voltage transistor device that is configured to maintain a deactivated state in response to a voltage between the source region and the drain region that is greater than three volts.