1. An accelerator circuit comprising: boolean unit to perform a boolean operation on first and second data words to output a result word; and buffer coupled to the boolean unit and having capacity to store at least one block of data, each block being a plurality of words, the circuit being configured to store the first word in the buffer, perform the boolean operation on said first and second words, and store the result word in the buffer overwriting the first word, and further configured to store a first block in the buffer before the boolean unit receives a second block one word at a time.