1. An address translation system for a flash memory device, comprising: a flash memory system writing a data page by allocating a physical address of a physical address space when there is a request for writing the data page from a storage client among storage clients, and performing address translation between the physical address and a logical address of a logical address space, the logical address space being formed between the flash memory system and the storage client to provide the logical address; and the physical address space including a data region writing and extracting data requested from the storage client and storing mapping information and a check point region managing a writing position of mapping information and a sequence number, one or more blocks being allocated to the check point region so that the writing position of the mapping information and the sequence number are written to a page included in the one or more blocks while the page is sequentially circulated at each checkpointing operation, wherein the allocating allocates a new physical address when the storage client requests a writing operation associated with the logical address and the address translation manages a correspondence relationship between the new physical address and the logical address, and wherein the data region includes a log packing block writing one mapping information entry for each page.