1. An apparatus for detecting bugs in a logic-based processing device during post-silicon validation, said apparatus comprising: a test bench having a processor for converting an original test program to a modified test program by dividing instructions of said original test program into multiple blocks of instructions, and by substituting an original register in one of said blocks of instructions with a shadow register, and for executing said modified test program; and a plurality of Proactive Load and Check (PLC) hardware checkers, each inserted within an uncore component of said logic-based processing device to be tested, wherein said PLC hardware checkers perform PLC operations concurrently, wherein one of said PLC hardware checkers includes: a controller for initiating a PLC operation in response to a determination that a predetermined set of criteria has been met; an address generator for generating an address of an original variable in said uncore component with which said PLC hardware checker is associate; a data register for storing a value at said original variable address: and a comparator for comparing said value stored within said data register to a value at a corresponding variable address within said modified test program, and for indicating an existence of a bug within said logic-based processing device to be tested when said value stored within said data register does not match said value from said corresponding variable address within said modified test program.