1. A processor comprising: an execution core configured to execute an instruction having a plurality of operands stored in a plurality of operand registers identified by the instruction, wherein: the plurality of operands of the instruction specify a first one or more addresses and a second one or more addresses; at least the first one or more addresses are contiguous in an address range; the address range begins at a scalar address that is included in the plurality of operands of the instruction; the address range ends at a second address determined from the scalar address and a vector attribute that is stored in one of the plurality of operand registers identified by the instruction, wherein the vector attribute specifies size information of a first vector having vector elements stored in the address range; and the execution core is configured, responsive to executing the instruction, to: detect whether or not a dependency exists between the first one or more addresses specified by the plurality of operand of the instructions and the second one or more addresses specified by the plurality of operands of the instruction; and generate a dependency vector that indicates, for each first element of the first vector stored in the address range that depends on a second element of a second vector having elements stored at the second one or more addresses, which second element that the first element depends on.