1. A data processing interrupt system comprising: first and second arithmetic units for processing emergent tasks and non-emergent tasks respectively with only one arithmetic unit operating at a time; memory means, connected to said first and second arithmetic units for storing data from said first and second arithmetic units; means for requesting an interrupt of a task; and control means, connected to said first and second arithmetic units and said requesting means, for selecting one of either an interrupt task requested by said requesting means and a task being processed by one of said first and second arithmetic units in response to the priority levels of both tasks and for operating the first or second arithmetic unit in dependence upon whether a selected task is an emergent task or a non-emergent task.