1. A multi-processor computer system comprising: a plurality of processor units, each unit including at least one processor and having a plurality of coupler interfaces through which data and addresses may be communicated; at least one random access system memory unit having a plurality of coupler interfaces through which data and addresses may be communicated and through which request signals may be applied to the memory unit; at least one communications unit interfacing with a plurality of input/output devices and having a plurality of coupler interfaces through which data and addresses may be communicated; between each processor unit and each of said system memory units, a respective coupler linking a processor interface to a respective memory interface; between each processor unit and said communications unit, a respective coupler linking a processor interface to a respective communications system interface, each processor unit being freely associable with any of said input/output devices; between each communications unit and each system memory unit, a respective coupler linking a communications interface to a respective memory interface, said couplers providing a distributed switching network permitting data communication between any pair of said processors, system memory, and communication units; and at least one addressable, passive task register associated with one of said units for communication through said couplers for registering a variety of task requests, each task request having a corresponding task priority value which is registered with the request, input/output devices operating to directly register corresponding task requests and values, said register being readable by any one of said processors to obtain the highest priority value registered, whereby a system program incorporating instruction sequences of preselectable length interspersed with instructions effecting reading of said task register will be run by said multi-processor computer system using all available processor units.