1. An apparatus for system design verification, comprising: a stimulus generator for compiling a test case in a scripting language, wherein the test case includes at least one stimulus; a testbench including a design under test (DUT), wherein the testbench simulates behavior of the DUT in response to the at least one stimulus, and wherein the testbench operates using a hardware descriptor language; and an interface gasket connected between the stimulus generator and the testbench for transmitting the at least one stimulus to the design under test, wherein the interface gasket includes a file defining transactions using a hardware description language.