1. An automated system for programming field programmable gate arrays (FPGAs) to implement a desired user-defined algorithm specified in a high level language for processing data vectors with one, two or more dimensions, the system comprising: means for analyzing the user-defined algorithm to determine what logic components are required and their interrelationships, including means for determining how many of such components are required, the relative timing between the required components, and means for determining partial products and the presence of signal delays between selected components; means for mapping the required logic components onto a target FPGA, including means for evaluating alternative interconnection routes between logic components within the target FPGA, and means for producing an optimized placement and routing of the logic components and interconnections on the target FPGA, and means for generating a low level command listing in a file operable to serve as an input file to a low-level conventional FPGA programming tool, whereby the FPGA programming tool from the input file is able to generate a hardware gate programming bitstream to be directed to the target FPGA, thereby programming the FPGA with the desired user-defined algorithm.