1. A Viterbi processor to decode a convolutional code, the processor comprising: a branch metric unit (BMU) comprising a plurality of branch sub-units that receives a first plurality of input bits from a main memory and outputs a first series of branch metrics, wherein the number of active branch sub-units of the plurality of branch sub-units is based on a programmable generator polynomial and a programmable code rate; a path metric unit (PMU) comprising a plurality of add-compare-select (ACS) units that receive the first series of branch metrics through a plurality of interconnects and output a first series of path metrics, wherein the configuration of the interconnects is based on a programmable constraint length; and a number of active path metric registers in a plurality of path metric registers that receive the first series of path metrics and output a second series of path metrics, wherein the number of active path metrics registers from the plurality of path metric registers is based on the programmable constraint length.