1. A system, comprising: a processor comprising: at least a first core; and a local interrupt controller associated with the first core, wherein the first core is operable to store its architectural state to a memory prior to entering a first core sleep state, and wherein the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller, placing the first core in a second core sleep state, and subsequently restoring the saved architectural state of the first core.