1. A computer implemented method for fast remote communication and computation between processors, the computer implemented method comprising: configuring a direct core to core communication unit (DCC) to operate with a first processor in a multiprocessor data processing system, the first processor being a remote processor; receiving in a memory associated with the DCC a set of bytes, wherein the memory occupies a level at least same as a cache level in a cache hierarchy of the first processor, wherein a first area of the memory is configured as a first address space accessible only to the first processor and a second area of the memory is configured as a second address space accessible by any processor in the multiprocessor data processing system, the set of bytes being sent from a second processor, wherein the second processor in the multiprocessor data processing system gains access to the second area of the memory using an address from the second address space, the memory receiving the set of bytes in the second area at the address from the second address space, wherein the set of bytes have an address accessible by the second processor, wherein the memory receiving the set of bytes comprises translating the address accessible by the second processor to an address accessible by the remote processor and the second processor, wherein the set of bytes include information about a context available at the remote processor within which the remote processor has to execute an instruction included in the set of bytes; creating without software intervention a hardware execution context using data specified in the set of bytes at the remote processor; and executing an operation specified in the set of bytes at the remote processor using the created context.