1. A verification method suitable for use with an original model of an integrated circuit, the original model being described by a netlist including a set of gates and a set of edges representing interconnections between the gates, comprising: proposing an equivalence class comprised of a set of candidate gates suspected of exhibiting equivalent behavior; creating a set of equivalence gates, wherein an equivalence gate comprises an XOR or XNOR product of a representative gate and one of the selected candidate gates; creating a speculatively reduced netlist by replacing the representative gate as the source gate for edges sourced by the selected candidate gate; and performing additional verification on the speculatively reduced netlist wherein the additional verification is selected from the group consisting of: verifying formally the equivalence of the gates in the equivalence class including applying a plurality of transformation engines to the speculatively reduced netlist; and performing incomplete search to yield verification coverage data and, for the duration of the incomplete search for which none of the equivalence gates is asserted, applying verification coverage results derived from said duration of the incomplete search to the original model.