1. A method for logic simulation of a connectivity level description of an integrated circuit, where the connectivity level description comprises a plurality of logic elements, the method comprising: in a first processor, clustering logic elements into cluster groups each comprising at least one of the plurality of logic elements, where the cluster groups are sized such that, during a simulation cycle, each cluster group is capable of being simulated on a different processor block of a second processor, wherein the processing units of the second processor are capable of simultaneous operation; and in the second processor, simultaneously simulating a plurality of the cluster groups each being simulated on a different one of the processing units.