1. A star topology serial bus interface system for a multiple-core processor; at least some of said processor cores having the capability to support a plurality of software generated read or write instructions for interfacing with said star topology serial bus interface system; said multiple-core processor having an internal fast messaging network or interface switch interconnect capable of linking the various core processors together; wherein said star topology serial bus interface system is attached to said fast messaging network or interface switch interconnect, and wherein said star topology serial bus interface system is configured to receive memory read or write transmission requests from said core processors; and wherein said star topology serial bus interface system includes a DMA configured to allow said internal fast messaging network or interface switch interconnect memory read or write requests to be implemented as star topology serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.