1. A processor comprising: means for translating a first sequence of instructions in a target instruction set to a second sequence of instructions in an instruction set of said processor, wherein said target instruction set and said instruction set of said processor are different; and means for executing said second sequence of instructions on said processor, wherein said means for executing comprises means for speculative execution of branch operations, wherein said second sequence of instructions is of a bounded length before a commit of said speculative execution occurs, and wherein said translating takes place in advance of executing said first sequence of instructions.