1. A method, comprising: setting a first plurality of direction bits for a first cache line of a first way, wherein data of the first cache line is located in a first bank of a plurality of banks of a non-uniform cache access (NUCA) cache, wherein further sets of the NUCA cache are horizontally distributed across the plurality of banks; setting a second plurality of direction bits for a second cache line of a second way, wherein data of the second cache line is located in a second bank; and moving data of the first cache line to the second bank and data of the second cache line to the first bank to reduce access latency between at least one of the first and second cache lines to at least one processor, wherein the moving is based upon a calculation which uses the first and second plurality of direction bits.