1. A processor comprising: (a) an execution unit having a plurality of execution stages for accessing operands from local registers, performing operations on said operands, and for storing results of said operations; (b) a memory interface unit having a plurality of stages including a memory-request stage for receiving memory address from said execution unit and a memory-access stage for evaluating said memory address to determine if said memory address is available for access and for accessing a memory if said address is available or for issuing an exception control signal if said memory address is not available for access; (c) pipelining means for applying sets of control bits to each of said stages of said execution unit and to each of said memory-request stage and said memory-access stage of said memory interface unit in successive ones of machine cycles of the processor. (d) latch means for holding a set of said control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given one of said machine cycles, and for thereafter re-applying said set of control bits to said memory-access stage in a subsequent one of said machine cycles after said given machine cycle.