1. A semiconductor memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type; said floating body region having a bottom surface bounded by an insulator layer; a first region in electrical contact with said floating body region, said first region exposed at or proximal to a top surface of said floating body region and extending to contact said insulator layer; a second region in electrical contact with said floating body region and spaced apart from said first region, said second region exposed at or proximal to said top surface of said floating body region and extending into said floating body region, wherein said floating body region underlies said second region such that said second region does not extend to contact said insulator layer; a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region exposed at or proximal to said top surface of said floating body region and extending to contact said insulator layer; and a gate positioned between said first and second regions; wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region; and wherein said semiconductor memory cell has only one said gate.