1. An apparatus for acquiring data words which are present on synchronous logic circuitry of a system under test, comprising: (a) detecting means coupled to said data bus for producing an acquisition signal indicative of the occurrence of at least one particular data word on said logic circuitry; (b) data storage means having a plurality of storage locations and addresses corresponding with said locations, said data storage means coupled to said data bus for storing a plurality of successive data words; and (c) addressing means, responsive to said acquisition signal and to the presence of data words on said data bus, for producing the storage addresses of said successive data words in said data storage means such that a predetermined number of successive data words preceding each said particular data word on said logic circuitry are stored in locations in said data storage means corresponding to said storage addresses.