1. An apparatus comprising: fetch circuitry to fetch instructions; decode circuitry to decode the fetched instructions; a plurality of vector registers including a first vector register and a second vector register; and execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to: receive a first decoded instruction to perform wireless security operations; receive a first operand of the first decoded instruction specifying the first vector register that stores a current state of a finite state machine (FSM); receive a second operand of the first decoded instruction specifying the second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM; and execute the first decoded instruction to produce an updated state of the FSM and an output of the FSM in a destination operand of the first decoded instruction.