1. A device comprising: a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal received by said delay lock loop, said delay lock loop comprising: a register configured to provide a signal to control a delay operation; at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state, the at least one delay circuit having at least one delay element operatively coupled to the register and comprising: a first NAND gate to receive an entry point delay signal; a second NAND gate operatively coupled to said first NAND gate, said second NAND gate configured to receive a first input from said first NAND gate and a second input from said register, said second NAND gate configured to provide a delayed output signal; and an AOI gate coupled to a bit associated with said register and to said first NAND gate, said AOI gate configured to receive an input signal and provide an output to said first NAND gate to provide a delay upon said input signal to cause said second NAND gate to generate said output signal.