1. A programmable digital signal processing device for implementing a Viterbi algorithm having a plurality of add-compare-select operations (ACS) operating on a plurality of Viterbi state metrics, the device comprising: a first vector unit comprising a plurality of first registers; a second vector unit comprising a plurality of second registers and connected to the first vector unit via a connection; and a vector pointer unit connected to the first vector unit, the vector pointer unit storing and processing pointers for indirectly addressing the plurality of first registers, wherein the first vector unit and the second vector unit perform concurrent operations for executing a subset of the plurality of add-compare-select operations (ACS).