1. A processor comprising: a cache comprising a plurality of banks, wherein each bank of the plurality of banks can be accessed independently of other banks; wherein the processor is configured to: detect that a first store operation of data conflicts with a first load operation in a first clock cycle in at least one bank of the cache; perform a first partial write of a first portion of the data to the cache in the first clock cycle, wherein the first portion of the data is less than all of the data; perform the first load operation by reading from the cache in the first clock cycle; delay a second partial write of a second portion of the data to the cache until a subsequent clock cycle, wherein the second portion of the data conflicts with the first load operation; maintain a first mask for each portion of a plurality of portions of the first store operation; and update the first mask to indicate the first portion of the first store operation has been written to the cache in the first clock cycle.