1. A method for effecting performance analysis upon a system block, comprising: modeling the system block in both a TLM model and a RTL equivalent model; generating a set of stimuli at a testbench, the testbench being an application that may apply the set of stimuli against the TLM model or the RTL equivalent model to produce a set of timing information; effecting performance analysis on the TLM model using the set of stimuli; and effecting performance analysis on the RTL equivalent model using the set of stimuli.