1. A system for controlling a digital signal processor comprising: a memory having an address space addressable at address words, each of said address words having a front edge word boundary and a back edge boundary, a set of variable length instructions stored in said memory, each of said variable length instructions having a front edge instruction boundary and a back edge boundary, wherein a first portion of said variable length instructions have front edge instruction boundaries which correspond to said front edge word boundaries or have back edge instruction boundaries which correspond to said back edge word boundaries, and a second portion of said variable length instructions have front edge instruction boundaries which are different than said front edge word boundaries and have back edge instruction boundaries which are different than said back edge word boundaries.