1. A processor comprising: a cache including one or more cache lines; a store pipeline to operate on a store, said store pipeline to retrieve a tag associated with one of the cache lines, wherein data stored in a data portion of the cache line is not retrieved and wherein the cache line is to be updated during operation of the store instruction without retrieving data stored in a data portion of the cache line in the cache if, based on the tag, the cache line is determined to be in a modified or exclusive state of a cache coherency protocol.