1. A random non-cyclical binary code generator comprising: a GPS receiver for providing a universal time clock reference used to control events associated with a time-synchronous reading of sub-codes from a pre-defined frame memory within an epoch of sub-codes usable by a signal processing system; a random decimal number generator to create a sequence of random decimal numbers with values of 0.0 to 1.0 inclusive or exclusive of the endpoints upon request; a decimal-to-integer mapper to create a set of random integers with a tailored statistical distribution derived from said sequence of random decimal numbers created by said random number generator; a random integer sequence extender wherein said set of random integers is expanded to longer sequences, which form extended random integers, while maintaining said tailored statistical distribution of said set of random integers; a randomize seed selection algorithm for said random decimal number generator that enables a unique sequence of random decimal numbers to be output from said random decimal number generator and used by said decimal-to-integer mapper to convert random decimal numbers to random integers for use by said random integer sequence extender, wherein said random integer sequence extender is the source of all extended random integers contained in a pre-defined epoch memory of extended random integers; a present and future epoch memory containing said extended random integers, wherein the smallest epoch unit containing extended random integers is a 1-second epoch of extended random integers, wherein the sum of all integer values in said 1-second epoch of extended random integers is 10 million, and wherein there are an even number of extended random integers, wherein each odd index integer represents a logical all ones (1s) binary pulse with bit count equal to an extended random integer value and each even index integer represents a logical all zeros (0s) binary pulse of bit count equal to an extended random integer value, and wherein there are 5 million logical binary ones (1s) and 5 million logical binary zeros (0s) defined by said 1-second epoch of extended random integers; an epoch integer selection controller that copies integers from said 1-second epoch memory of extended random integers to a separate 1-second epoch memory of extended random integers; an integer-to-chip-pulse converter that reads said separate 1-second epoch memory of extended random integers, wherein all integers are indexed from 1 in ascending order, and wherein all odd indexed integers are converted to a binary all ones (1s) pulse, and all even indexed integers are converted to a binary all zeros (0s) pulse, where the pulse widths in bit counts are equal to the values of the extended random integers and concatenated together to form a 1-second epoch of random non-cyclical binary code, and wherein said 1-second epoch of random non-cyclical binary code is parsed into 8 bit parses, wherein each said parse is a code byte represented by two HEX characters, and each 1-second epoch of code bytes is parsed into an integer number of frames, wherein a frame of code bytes contains 5000 code bytes representing 100 orthogonal random non-cyclical binary sub-codes, wherein each said sub-code is defined by 50 code bytes; a clock-shifted memory of said code bytes that is equivalent to said frame of code bytes corresponding to a specific 4-millisecond time of day time period in code bytes in a 1-second epoch of code bytes, wherein said 100 orthogonal random non-cyclical binary sub-codes are bulk loaded in sets of 10 sub-codes in the form of 500 code bytes at a time into a load zone of code bytes in said clock-shifted memory, wherein all sets of 10 sub-codes in said clock-shifted memory are left-shifted in parallel across the clock-shifted memory, wherein the load and shift events are repeated until said clock-shifted memory is filled, after which a time-of-day synchronous 10 MHz chipping clock transfers one or more orthogonal sub-codes from said frame chip by chip out to selected modulators or demodulators during each 40 microsecond code correlation time slot, wherein 100 orthogonal sub-codes are available to 100 modulators or demodulators, wherein sub-codes clocked to each modulator are unique relative to sub-codes clocked to all other active modulators, wherein no modulator or demodulator receives a repeated sub-code during the frame of 100 40 microsecond code correlation time slots in each said 4-millisecond time of day time period, and wherein each said 4-millisecond time of day time period is usable by said signal processing system; and an epoch fill controller for preloading epochs of said extended random integers providing one-time fills of pre-defined memory containing said 1-second epochs of extended random integers, wherein a sequence of random number requests are initiated to said random decimal number generator followed by a delivery of a corresponding sequence of random decimal numbers to said decimal-to-integer mapper, followed by a delivery of a sequence of mapped random integers to said random integer sequence extender, wherein said set of random integers is formed into column-row blocks of random integers according to a column-row selection algorithm, wherein said extended random integers are saved in a memory of said blocks of random integers by said random integer sequence extender, wherein said extended random integers are requested and processed by said epoch fill controller to fill a 0.5 second epoch memory of extended random integers, wherein the last appended extended random integer causes the sum of integer values to be 5000 or greater, and wherein selected random integers in said 0.5 second epoch memory are reduced in value by 1 until said sum of integer values is exactly 5000, which forms an adjusted integer set, and wherein said adjusted integer set is copied in reverse index order to form a reverse integer set, and wherein said adjusted integer set and said reverse integer set are shuffle merged and saved to a memory of said 1-second epoch of extended random integers.