1. A memory array comprising: a first volatile memory cell having first and second inverters cross-coupled between first and second storage nodes, the first storage node being coupled to the first bit line and the second storage node being coupled to the second bit line; a first non-volatile memory cell coupled between the first and second bit lines and having at least one resistive element programmable to have one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes to generate a current for programming the resistive state of the at least one resistive element.