1. A microprocessor configured to process a repeat load string instruction, wherein the repeat load string instruction specifies a string of data bytes in memory to be loaded into an architectural register of the microprocessor, the microprocessor comprising: a memory subsystem, comprising a cache memory; and microcode, wherein the microprocessor is configured to invoke the microcode in response to encountering the repeat load string instruction, wherein the microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into the cache memory a series of cache lines implicated by the string of data bytes specified by the repeat load string instruction; wherein the microcode further includes an instruction to load a last value from the string of data bytes into the architectural register.