1. A memory circuit for maintaining memory access coherency, the memory circuit comprising: a plurality of registers configured to: store a read address, a first write address, and first input data during a first clock cycle; and store a second write address and second input data during a second clock cycle; a memory configured to: read data from a memory location corresponding to the read address during the second clock cycle, wherein the plurality of registers are further configured to store the data read from memory; and write the first input data at a memory location corresponding to the first write address during the second clock cycle; comparator circuitry comprising N×R×W comparators and forwarding paths, wherein N is an integer corresponding to a level of pipelining, R is an integer corresponding to a number of read ports of the memory, and W is an integer corresponding to a number of write ports of the memory, wherein the comparator circuitry is configured to determine whether the read address is the same as the first write address or the second write address; and selection circuitry configured to output, during a third clock cycle: the second data input when the comparator circuitry determines that the read address is the same as the second write address; the first data input when the comparator circuitry determines that the read address is the same as the first write address but not the second write address; and the data read from memory when the comparator circuitry determines that the read address is not the same as the first write address or the second write address.