1. An architecture capable of programming and controlling access of data and instructions, in which a plurality of data transfer levels are preset and a current data transfer level is used for accessing data and instructions, comprising: a first module capable of effecting a burst transfer for continuously outputting a data string having a fixed burst length for access; a second module for storing data and instructions, wherein each data transfer level corresponds to a length of a continuous data transfer via an interface between the first and the second modules; and a burst mode controller programmed by data format accessed by the first module or a result of instruction decoding performed by the first module, so as to adjust the current data transfer level.