1. A microcomputer that can process plural tasks time-divisionally and in parallel, at least one of these tasks being a specific task in which a program looped so that an increment of instruction addresses is fixed is described, wherein one of the plural programs is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction for executing a peripheral function by one instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand, the CPU is designed so that the peripheral function instruction can be executed as one instruction, achieves information needed to execute the instruction concerned by a general-purpose register and stores information concerning an execution result of the instruction concerned into the general-purpose registers.