1. An integrated circuit including a substrate, comprising: a memory array on a first region of the substrate, comprising one-transistor, dielectric charge trapping memory cells arranged in a divided bit line architecture for random access read, erase and program operations; and control circuitry on a second region of the substrate and coupled to the memory array, the control circuitry including logic and bias circuitry having random access read, erase and program modes, wherein the erase mode biases a selected cell to cause hole tunneling to set an erase threshold state in the selected cell, and the program mode biases a selected cell to cause electron tunneling to set a program threshold state in the selected cell.