1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; an access plan cache residing in the memory, the access plan cache including a plurality of entries, each entry including a performance specification for a corresponding query and an access plan for the corresponding query, the performance specification specifying a desired maximum number of bus cycles for the corresponding query that comprises an average of bus cycles over the last N executions of the query, where N is a predetermined positive integer; and a query optimizer residing in the memory and executed by the at least one processor, wherein the query optimizer determines number of bus cycles required to execute a query using an access plan stored in the access plan cache and compares the number of bus cycles required to execute the query with the performance specification corresponding to the query, wherein the query optimizer generates a new access plan if the number of bus cycles required to execute the query using the access plan stored in the access plan cache exceeds the performance specification corresponding to the query, wherein, if the query optimizer generates a new access plan that satisfies the performance specification corresponding to the query, the query optimizer stores the new access plan in an entry in the access plan cache that corresponds to the query and updates the performance specification corresponding to the query with an actual number of bus cycles during execution of the query, and wherein, if the query optimizer cannot generate a new access plan that satisfies the performance specification corresponding to the query, the query optimizer selects a new access plan that had the best number of bus cycles during execution of the query, stores the new access plan in the entry in the access plan cache that corresponds to the query, and stores in the access plan cache the best number of bus cycles as a new stored performance specification corresponding to the query.