1. A method for preserving constraints in a digital design, said method comprising: receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements; identifying a cut of said initial design including one or more cut gates; computing a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs and said one or more state elements; constraining said relation to force one or more constraint gates representing said one or more constraints to evaluate to a forced valuation; identifying one or more dead-end states of said constraints; applying the inverse of said dead-end states as don't cares to simplify said relation; synthesizing said simplified relation to form a first gate set; forming an abstracted design from said first gate set; and performing verification on said abstracted design to generate verification results.