1. A method for verifying a simulated wafer image against an intended design, comprising: receiving a design; generating a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements; computing environments for cell placements based on the skeleton; generating templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement; and generating the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.