1. A method for storing branch address information in an address table of a computer processor, the method comprising: creating in the address table a first entry, the first entry having a base instruction tag for a first instruction and a base address associated with the first instruction; in response to a branch in an entry being predicted taken, creating a new second entry having a second base instruction tag for a second instruction and a second base address associated with the second instruction; and wherein an address associated with an instruction tag may be determined based on the base instruction tag and the base address for an entry associated with the instruction tag.