1. A circuit-design-modifying method executed in a computer system, comprising steps of: performing a first synthesis-with-optimization operation of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis-with-optimization operation of the first and second HDL codes while forcibly preserving specified elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second circuit and the third circuit to generate at least one ECO cone pair; executing Equivalent Check (EC) according to an ECO logic cone belonging to the second circuit to locate an end element to be replaced in the post layout circuit, which is equivalent to an end element of the ECO logic cone; marking the end element to be replaced and an ECO logic cone which belongs to the third circuit with respective effective ECO flags; and executing Equivalent Check (EC) to define a border of equivalence according to the marked end element to be replaced and the marked ECO logic cone, wherein the ECO logic is a set of logic gates including the end element of the marked logic cone and those within the border of equivalence, and then replacing the element to be replaced in the post layout circuit with the ECO logic, thereby modifying the post layout circuit into a post layout ECO circuit.