1. A processing unit comprising: a processor; operating means for dynamically toggling an interrupt mode of said processing unit between enabled and disabled to allow said processor to issue a sequence of instructions that complete a move operation of data from a first memory location to a second memory location without being subject to an external interrupt; wherein said operating means replaces said sequence of instructions with a single combined operation, in response to a determination that said sequence of instructions completes a move operation and said sequence of instructions follows a de-assertion of said external interrupt; and wherein said processing unit completes said move operation from one memory location in a main memory to another memory location with no lock acquisition phase at the processor and without having the data travel to the processor from the first memory location, responsive to said single combined operation.