1. A method performed by a computer system for optimizing a design point for an integrated circuit design, the method comprising: receiving an integrated circuit design, the integrated circuit design comprising a plurality of circuit components; receiving a reference PPA (power, performance, area) metric for the integrated circuit design evaluated at a reference design point; receiving a target PPA metric for the integrated circuit design; and estimating, by the computer system, a trial PPA metric for the integrated circuit design evaluated at a trial design point within a design space, wherein the estimating comprises: accessing a PPA database that contains PPA metrics for multiple test components evaluated at multiple design points; determining scale factors for the circuit components in the integrated circuit design, the scale factors based on: scaling from (a) the reference design point to (b) the trial design point, of equivalent test components to the circuit components; and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point; and iteratively optimizing the trial design point based on the trial PPA metric in relation to the target PPA metric until the trial PPA metric meets or exceeds the target PPA metric, wherein the integrated circuit design is providable for subsequent design and manufacturing of the integrated circuit.