1. A processor comprising: a decoder to decode a load instruction, said load instruction to be memory renamed to use an address of a previous store instruction; a memory ordering buffer to maintain the address for the previous store instruction, wherein the address for the previous store instruction is to be de-allocated from the memory ordering buffer after completion of the previous store instruction; a trailing store buffer to maintain an address for said previous store instruction in response to said previous store instruction being de-allocated from said memory ordering buffer and only if said previous store instruction being a source of memory renaming, said trailing store buffer to maintain the address for said previous store instruction to disambiguate said load instruction.