1. A method for tracking data in a processor comprising: a) providing a plurality of logical registers and a plurality of physical registers; b) decoding an instruction that produces a result, wherein said instruction specifies at least one of the plurality of logical registers; c) mapping the plurality of logical registers to the physical registers, wherein the mapping includes a mapping of the specified at least one of the plurality of logical registers to a corresponding at least one of the plurality of physical registers; d) identifying which of said plurality of physical registers are available to store the result; and e) assigning one of the identified available physical registers to said instruction to store the result until graduation of said instruction; and f) generating a second instruction wherein said second instruction uses the mapped physical registers and the assigned one of the plurality of physical registers.