1. A method to automatically generate a processor architecture for a custom integrated circuit (IC) specified by a user code, the IC having at least one or more timing and hardware constraints, comprising: a. extracting parameters defining the processor architecture from a static profile and a dynamic profile of the user code; b. iteratively optimizing the processor architecture by changing one or more parameters of the processor architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and c. synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.