1. A method of executing a conditional instruction in a pipelined processor, the conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied and to not provide an output if the condition is not satisfied, comprising: receiving one or more operand values; receiving a prior value of the target; evaluating a condition; if the condition is satisfied, performing an operation on the operand values to generate a result value and outputting the result to the target; and if the condition is not satisfied, outputting the prior target value to the target.