1. A programmable logic array integrated circuit comprising: a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks, said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks; a plurality of first conductors adjacent to each of said logic array blocks, the first conductors adjacent to each block being adjacent to the logic modules within said block for selectively applying the outputs of the logic modules in each block to the inputs of any of the logic modules in that block; a plurality of second conductors extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the adjacent row; means for selectively applying the outputs of the logic modules in a row to the second conductors in the group adjacent to said row; means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group; a plurality of third conductors extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the adjacent column; means for selectively applying the outputs of the; logic modules in each column to the third conductors in the group adjacent to said column; and means for selectively connecting said third conductors to said second conductors.