1. A decision feedback circuit comprising: L N-tap decision feedback equalizer (DFE) branches including: K unrolled DFE branches, and Lâˆ’K unfolded DFE branches; each DFE branch including a pre-computation circuit configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value for at least one previous output of the same DFE branch; each unrolled DFE branch including a multiplexer circuit having selection lines for selecting from the set of tap-adjusted inputs for the unrolled DFE branch, the selection lines being connected to outputs of other DFE branches; and each unfolded DFE branch including an unfolded branch multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs, the unfolded branch multiplexer circuit comprising a plurality of multiplexer blocks, each multiplexer block having selection lines corresponding to tap-adjusted inputs from a different one of the other DFE branches.