1. A dynamic logic propagation delay targeting tool that calculates the propagation delay of a signal in a specified block of dynamic logic, comprising: a gate target delay initializer that calculates the initial delay targets for all logic gates in the specified block of dynamic logic; a levelizer that levelizes all the logic gates in the specified block of logic; a backward logic scanner that backward scans the logic gates of the specified block of logic and then calculates for each individual scanned logic gate an output backward surplus of delay at the individual scanned logic gate's output and an input backward surplus of delay at the individual logic gate's input; a forward logic scanner that forward scans the logic gates of the specified block of logic and then calculates for each individual scanned logic gate an input forward surplus of delay at the individual scanned logic gate's input and an output forward surplus of delay at the individual scanned logic gate's output; a gate target delay incrementor that increments delay targets if a positive surplus of delay exists for each individual scanned logic gate of the specified block of logic; and a gate target delay comparator that compares the current delay targets of each individual scanned logic gate of the specified block of logic to the prior delay targets of each individual scanned logic gate of the specified block of logic to further increase the delay targets of all the scanned logic gates of the specified block of logic.