1. A system for vector processor predication in an active memory device, the system comprising: memory in the active memory device; and a processing element in the active memory device, the processing element configured to perform a method comprising: decoding, in the processing element, an instruction comprising a plurality of sub-instructions to execute in parallel; accessing one or more mask bits from a vector mask register in the processing element; and applying the one or more mask bits by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.