1. A method for increasing a manufacturing yield of a programmable logic device (PLD) comprising: forming a PLD in a first section and a second section; forming a first section configuration port and a second section configuration port on the PLD for configuring the first section and second section, respectively; testing each of the first section and second section to determine if one of the sections is defective; configuring, with a processor, the first section with the first section configuration port when the second section is defective; and configuring, with the processor, the second section with the second section configuration port when the first section is defective.