1. A method comprising: identifying, at an instruction pipeline of a processor, a first entry of a stack to be accessed by a first stack access instruction by identifying a first offset from a base of the stack based on the first stack access instruction; identifying, at the instruction pipeline, a second entry of the stack to be accessed by a second stack access instruction by identifying a second offset from the base of the stack based on the second stack access instruction; and identifying a dependency between the first stack access instruction and the second stack access instruction in response to the first offset matching the second offset.