1. A processor comprising: a memory; one or more functional units coupled to the memory; and a memory stream module coupled to the memory and the one or more functional units and to: receive a plurality of operations associated with the memory; receive a plurality of operations associated with the one or more functional units; determine a dependency between the plurality of operations associated with the memory and the plurality of operations associated with the one or more functional units; create a first ordering of the plurality of operations associated with the memory; and create a second ordering of the plurality of operations associated with the one or more functional units based on the dependency and the first ordering of the plurality of operations associated with the memory.