1. A processor comprising: a plurality of processing cores; and a logic to perform a secure enter instruction for a system including a plurality of processors, the plurality of processors including the processor and a plurality of second processors, wherein a node identifier is to be assigned to each of the plurality of processors, and a trusted agent is to be launched on the plurality of processors, including execution of the trusted agent on each of the plurality of processors concurrently to validate a memory configuration of the system, wherein a hash of a secure kernel is to be computed and stored in a master hub agent coupled to the processor.