1. A field programmable gate array (FPGA), comprising: a switching block routing array comprising a plurality of signal inputs and a plurality of signal outputs; a first transistor element coupled to the switching block routing array, wherein the first transistor element comprises a first gate, a first transistor terminal and a second transistor terminal, wherein the first transistor terminal is coupled to a signal input from the plurality of signal inputs, and wherein the second transistor terminal is coupled to a signal output from the plurality of signal outputs, and wherein the first gate is configured to electrically couple or decouple the signal input and the signal output in response to a gate control signal; a latch comprising a first latch terminal and a second latch terminal, wherein the second latch terminal is coupled to the first gate of the first transistor element; a second transistor element comprising a second gate, a third transistor terminal and a fourth transistor terminal; wherein the fourth transistor terminal is coupled to the first latch terminal and the second gate is selectively coupled to an activation voltage; a plurality of resistive elements coupled to the second transistor element, wherein each resistive element from the plurality of resistive elements comprises a first electrode and a second electrode, wherein each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein the plurality of resistive elements includes a first resistive element and a second resistive element, wherein a first electrode of the first resistive element is selectively coupled to a first voltage source, wherein a second electrode of the second resistive element is selectively coupled to a second voltage source; a shared node coupled to a second electrode of the first resistive element, to a first electrode of the second resistive element, and to the third transistor terminal of the second transistor element, wherein the plurality of resistive elements are configured to provide a set signal at the shared node in response at least to a first resistive state of the first resistive element, to a second resistive state of the second resistive element, a relatively high voltage from the first voltage source, and a relatively low or ground voltage from the second voltage source, wherein the second transistor element facilitates controlling propagation of the set signal to the latch in response to the activation voltage, and the first latch terminal of the latch is configured to become set with the set signal in response to activation of the second transistor and propagation of the set signal to the latch, and the first transistor element is configured to electrically couple the signal input to the signal output in response to the first latch terminal becoming set with the set signal; and a programming circuit coupled to the shared node, wherein the programming circuit is configured to facilitate entry to the first resistive state of the first resistive element or is configured to facilitate entry of the second resistive state of the second resistive element in response to an output path voltage applied by the programming circuit to the shared node.