1. A data processing system, comprising: at least two data memories arranged side-by-side along a first direction, each data memory partitioned along a second direction into at least two regions of identical size, wherein the number of regions is a power of two, and wherein the second direction is substantially perpendicular to the first direction; data allocation circuitry adapted to: receive digitally-coded data representing elements of a two-dimensional array; store, into successive adjacent memory locations within a first region of a first data memory, data representing a first sequence of a predetermined number of adjacent elements along a first dimension of the array; and store, into corresponding successive adjacent memory locations of respective adjacent regions of the data memories, data representing adjacent sequences, along the second dimension of the array, of the predetermined number of adjacent elements along the first dimension of the array, wherein the number of adjacent sequences, including the first sequence, represented by data stored in regions of the first data memory is the same as the number of regions in the first data memory, and wherein data stored in the regions of the second data memory represents the same number of adjacent sequences, and wherein sequences represented by data stored in corresponding regions of adjacent data memories are displaced along the second dimension of the array by a number of elements equal to the number of regions in the first data memory; instruction routing circuitry adapted to order execution of identical instructions upon data at corresponding addresses in adjacent data memories, wherein execution of the same instruction is offset by one clock cycle for each adjacent data memory along the first direction; at least two instruction execution units coupled to the respective at least two data memories and adapted to receive from the instruction routing circuitry and execute instructions for operations on the elements represented by the data stored in the respective data memory; and a master processor unit coupled via the instruction routing circuitry to all of the instruction execution units; wherein the master processor unit is adapted to store, fetch and distribute instructions for operations on the elements represented by the data stored in the data memories.