1. A hardware based translation accelerator, comprising: a guest fetch logic component for accessing a plurality of guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block; a plurality of conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block; a native cache coupled to the conversion tables for storing the corresponding native conversion block; a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block; wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache; and in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.