1. A method for generating and simulating test patterns to detect faults in an integrated circuit, comprising: identifying a plurality of nets which can potentially be shorted together as a plurality of potential faults; listing each potential fault in a fault list; categorizing each of the plurality of potential faults into either a feedback fault or a non-feedback fault wherein categorizing each of the plurality of potential faults into either a feedback fault or a non-feedback fault includes: assigning a level to a gate output node equal to the greatest number of intervening gates between the gate output node and a primary input; placing an identification code for each gate output node in a linked list which corresponds to the level of the gate output node; building a dependency list for each gate output node comprising the identification codes for each node on a path between the gate's output node and a primary input; recursively adding the dependency list for each gate which drives an input node to the gate until all dependencies are included; selecting a potential fault from the fault list; inspecting the nodes to determine a high level faulty node and a low level faulty node from the nodes which comprises the potential fault; and inspecting the dependency list associated with the high level faulty node to determine if the potential fault creates a feedback fault; selecting one potential fault from the fault list, having a first faulty node and a second faulty node; generating a test pattern to detect the selected potential fault; and checking the test pattern to ensure that the selected potential fault is detected even if the potential fault is categorized as a feedback fault.