1. A method of error reduction in memristor programming, the method comprising: programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance, the error-corrected target resistance being a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor, where n is a positive integer ranging from one to N, and N is an integer greater than one; wherein the switched memristor array comprises N switched memristors, each switched memristor comprising a switch connected in parallel with a memristor, and wherein programming the n-th switched memristor reduces a total resistance error of a programmed resistance of the switched memristor array.