1. A single channel interlocking system comprising: a plurality of processors for collectively receiving external input information, deriving internal interlocking information from the external input information, and providing external control information based on the external input information and the internal interlocking information, such that each of said plurality of processors is responsive to different information and performs a different function of the interlocking system; a common internal bus connecting said plurality of processors into a single hardware channel, said common internal bus including at least one external input for inputting said external input information and at least one external output for outputting said external control information; first fault-detection means for causing each of the processors to test itself to check whether it is operating correctly and to provide a respective first operation signal dependent on the result of that test; second fault-detection means for causing each of the processors to be tested for correct operation by a respective other of the processors and for causing said respective other processor to provide a respective second operation signal dependent on the result of that test; first logic means for subjecting the first operation signals to a first logical function to provide a first status signal, the first status signal being of a first kind if the first operation signals are such that each of the processors determines it is operating correctly and of a second kind if the first operation signals are such that at least one of the processors determines it is not operating correctly; and second logic means for subjecting the second operation signals to a second logical function to provide a second status signal, the second status signal being of a first kind if the second operation signals are such that each of the processors testing another processor determines that said another processor is operating correctly and of a second kind if the second operation signals are such that at least one of the processors determines that the processor it is testing is not operating correctly, the first logic means and the second logic means being selected from structurally different but functionally interchangeable ones of the group consisting of a gate arrangement including at least one dedicated electronic gate, a software arrangement including at least one software controlled processor, and an electro-mechanical arrangement including a plurality of electromechanical switches, whereby each of the processors is independently tested by two dissimilar test procedures and the results from the two dissimilar test procedures are independently processed by two dissimilar logic means.