1. An apparatus, providing for instruction level control of store checking within a microprocessor, the apparatus comprising: fetch logic, for receiving an extended instruction, wherein said extended instruction comprises: an extended prefix, for specifying that store checking be suppressed for said extended instruction; and an extended prefix tag, wherein said extended prefix tag is an otherwise architectural opcode within an existing instruction set; wherein said fetch logic precludes store checking for pending store events associated with said extended instruction; and translation logic, coupled to said fetch logic, for translating said extended instruction into a micro instruction sequence, said micro instruction sequence directing the microprocessor to exclude store checking during execution of a prescribed operation.