1. A digital processor system comprising: memory means for storing of information; processor means for entering and extracting information from the memory means under the control of a predetermined program sequence; interface means coupled between said processor means and memory means for providing a conduit for information transfer said interface means comprises; control means, responsive to said processor means, for providing at least a first control signal having a first state and a second state; information bus means for transferring of data and program information between said processor means and said memory means under the control of the processor means and memory addressing means including an address register responsive to the control signal when at a first state and a program counter register responsive to the control signal is incremented when the control signal is at a second state, the address register addresses the memory means for the entering or retrieving of data information and the program counter addresses the memory means for the entering and retrieving of program information; and control bus means for transferring of at least the first control signal between said processor means and said memory addressing means.