1. A digital intermediate frequency QAM modulator using parallel processing, comprising: a serial-to-parallel data converter operatively connected to receive serial data, wherein said serial-to-parallel data converter converts a string of serial data to a plurality of parallel data; an I and Q mapper operatively connected to receive said plurality of parallel data and determine its I and Q locations; a plurality of look-up-tables (LUTs) operatively connected to receive and store said I and Q locations, wherein the I LUTs are configured I 1 to I n, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q 1 to Q X, wherein X is the highest number of Q LUTs of said plurality of LUTs; a plurality of adders operatively connected to receive and add said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A 1 to A AN, wherein AN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ 1 to IQ IQN ; a plurality of registers operatively connected to collect and store said output data comprising IQ 1 to IQ IQN ; and a digital to analog converter operatively connected to convert said output data comprising IQ 1 to IQ IQN to analog data.