1. An apparatus for improving write margin of a memory cell, the apparatus comprising: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal, wherein the second circuit is operable to reduce the level of the power supply to the memory cell during write operation of the memory cell.