1. A single chip multithreaded processor comprising: a plurality of processor cores, wherein each core supports processing of a plurality of threads by generating address translation requests for data and instructions related to processing of said plurality of threads; a memory management unit operable to control access to data and instructions for said plurality of threads, said memory management unit being operable to selectively associate a plurality of contexts with each of said plurality of threads; wherein each of said threads is selectively associated with one or more contexts, each of which corresponds either to private memory transfers or shared memory transfers.