1. A decimal arithmetic logic unit comprising: an arithmetic processor having, a first input port for receiving decimal operands, a second input port for receiving decimal operands, a carry-in port for receiving a carry out from a previous decimal arithmetic operation, and an output port for providing a result decimal operand equal to the result of an arithmetic operation performed on decimal operands received at said first and said second input ports; a first multiplexer having an output connected to said first input port, having a first input for receiving a first decimal operand, having a second input for receiving a second decimal operand, and having a select input for receiving a first select signal which determines if said first decimal operand or said second decimal operand is to be connected to the output of said first multiplexer, and a second multiplexer having an output connected to said second input port, having a first input for receiving said second decimal operand, having a second input for receiving a decimal zero operand, and having a select input for receiving a second select signal which determines if said second decimal operand or said decimal zero operand is to be connected to the output of said second multiplexer, whereby said second operand may be applied via said first and said second multiplexers respectively to said first input port and to said second input port of said arithmetic processor so that said second operand may be added to itself when it is desired to convert said second operand in decimal format to binary format, and whereby either said first or said second decimal operands can be applied via said first multiplexer to said first input port of said arithmetic processor while said zero operand is connected via said second multiplexer to said second input port of said arithmetic processor so that they may be subtracted from said zero operand when it is desired to complement either said first or said second operand in decimal format.