1. A processor-implemented method comprising: receiving an instruction operation (OP) code at a processor that includes one or more instruction bits, one or more event type bits, and one or more pipeline trigger stage bits, wherein the one or more event type bits identify a forced event that is unrelated to an instruction corresponding to the one or more instruction bits, and wherein the one or more pipeline trigger stage bits specify one of a plurality of pipeline stages of an execution unit pipeline included in an execution unit of the processor; loading the one or more instruction bits into the execution unit pipeline; and executing the forced event in response to a determination that, during execution of the one or more instruction bits, the one or more instruction bits reaches the specified one of the plurality of pipeline stages in the execution unit pipeline.