1. A multiprocessor data processing system (MP) comprising: a plurality of processors including a first processor and a second processor coupled together by an interconnect, wherein each processor comprises a cache coherency subsystem including a translation look-aside buffer (TLB), at least one execution unit and an associated execution queue, wherein said execution queue holds queue address instructions with real addresses translated from corresponding virtual address by said TLB; a memory coupled to said plurality of processors by said interconnect and which includes a page frame table in which is stored a plurality of page table entries (PTEs) of virtual and real address translation pairs; operating logic associated with each processor for implementing a TLBI response protocol that controls a response by each of said plurality of processors to a receipt of a TLBI; and wherein, responsive to a receipt of the TLBI by said first processor, said TLBI response protocol causes said first processor to first drain queued address instructions from said execution queue of said first processor before issuing said TLBI out on the interconnect.