1. A processor, comprising: a storage unit that stores an instruction; a program counter that holds a program counter value specifying an instruction to be executed next; an instruction extension information register that includes a first area and a second area; an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information written to the first area and a second extension information extending an instruction after two instructions written to the second area, respectively, when the second prefix instruction is executed; an instruction packing unit that reads out instructions from the storage unit based on the program counter value, and that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes at least one of the first prefix instruction and the second prefix instruction; an instruction execution unit that executes the packed instruction generated by the instruction packing unit; and a register updating unit that increases the program counter value by a number corresponding to a length of two instructions when the instruction execution unit completes the execution of the packed instruction.