1. A method of performing a conditional subtract instruction of a first number and a second number, said method comprising: loading said first number in a first register; left-shifting said second number by M-bits to generate a shifted second number, wherein M represents a number of bits in said first number; shifting said first register to the left by one bit to generate a shifted register value; subtracting said shifted second number from said shifted register value to generate a temporary value; adding a 1 to said temporary value and storing a result of said adding in said first register if said temporary value is greater than or equal to zero; and shifting said first register to the left by one bit if said temporary value is less than zero.