1. An integrated circuit comprising: a memory controller configured to couple to one or more memory devices; a flash memory interface unit configured to couple to one or more flash memory devices; a direct memory access (DMA) controller coupled to the memory controller and the flash memory interface unit, wherein the DMA controller is configured to perform DMA operations to move data between the memory controller and the flash memory interface unit; and a processor coupled to the DMA controller, wherein the processor is configured to control the flash memory interface unit using a plurality of commands transmitted by the processor to the flash memory interface unit, and wherein the plurality of commands pass from the processor through the DMA controller to the flash memory interface unit over an interconnect between the DMA controller and the flash memory interface unit, and wherein the interconnect is also used in the DMA operations between the flash memory interface unit and the memory controller; wherein the flash memory interface unit comprises a command queue, and wherein the processor is configured to write the plurality of commands to the command queue to control a transfer between the flash memory interface unit and the one or more flash memory devices, wherein the flash memory interface unit is configured to perform the plurality of commands during the DMA operations between the flash memory interface unit and the memory controller, and wherein the flash memory interface unit comprises a macro memory configured to store a second plurality of commands, wherein the plurality of commands in the command queue are removed from the command queue in response to performing the plurality of commands, and wherein the second plurality of commands remain in the macro memory even when the second plurality of commands have been performed, and wherein the processor is configured to write the second plurality of commands to the macro memory.