1. A process implemented in a processor, comprising: receiving a first store instruction to be executed in a load store unit of the processor; identifying a destination address from the first store instruction; associating a counter with the destination address; and receiving subsequent store instructions, and for each subsequent store instruction, determining whether a respective destination address of that store instruction is within a cache line of the first store instruction, and responsively updating the counter, determining whether the respective destination address of that store instruction is within a cache line subsequent to the cache line of the first store instruction, and if a current value of the counter meets a criteria, then characterizing the store instruction to the subsequent cache line as being a store without ownership and emitting the store to a shared cache level of a memory hierarchy coupled with the processor.