1. A flip-flop comprising: a first AND gate including a first AND gate first input, a first AND gate second input, and a first AND gate output, the first AND gate first input being a delay (d) input of the flip-flop; a first NOR gate including a first NOR gate first input, a first NOR gate second input, and a first NOR gate output, the first AND gate output coupled to the first NOR gate first input; a second NOR gate including a second NOR gate first input, a second NOR gate second input, and a second NOR gate output, the first NOR gate output coupled to the second NOR gate first input, the second NOR gate output coupled to the first NOR gate second input; a first inverter including a first inverter input and a first inverter output, the first inverter input configured to receive a clock signal, the first inverter output configured to output an inverted clock signal, the first inverter output coupled to the first AND gate second input and the second NOR gate second input; a second AND gate including a second AND gate first input, a second AND gate second input, and a second AND gate output, the second AND gate first input coupled to the first inverter output; a third NOR gate including a third NOR gate first input, a third NOR gate second input, and a third NOR gate output, the third NOR gate first input coupled to the second NOR gate output, the third NOR gate second input coupled to the second AND gate output; and a second inverter including a second inverter input and a second inverter output, the second inverter output coupled to the second AND gate second input.