1. A processor implemented in hardware, comprising: a hardware processing core supporting execution of a fixed instruction set and decoding template based user defined instructions specified in a table defining source operands, type of destination register, instruction latency and instruction dependency on private state, wherein decoding includes evaluating the source operands, the type of destination register, the instruction latency and the instruction dependency on private state using a template processing block, wherein the instruction latency is restricted to one of a plurality of pre-defined latencies, and wherein the hardware processing core observes the instruction latency table entries to prevent stall conditions by determining bypass opportunities and operand readiness; and a hardware user execution block connected to the hardware processing core to execute the template based user defined instructions.