1. A processor comprising: a fetch unit to fetch instructions; a decode unit to decode the instructions, the decode unit including a control transfer termination (CTT) logic, responsive to a control transfer instruction, to decode the control transfer instruction into a decoded control transfer instruction, associate second state information with the decoded control transfer instruction to indicate that the CTT logic is in a wait state and provide the decoded control transfer instruction and the second state information to an execution unit, the CTT logic to transition from an idle state to the wait state responsive to the control transfer instruction; the execution unit to execute decoded instructions; and a retirement unit to retire the decoded control transfer instruction, wherein the retirement unit is to raise a fault if a next instruction to be retired after the decoded control transfer instruction is not a CTT instruction.