1. A method of forming a portion of a NAND memory array, comprising: forming a select line coupled to each of a plurality of NAND strings of memory cells of the memory array, wherein the select line comprises a select gate at each intersection of one of the plurality of NAND strings and the select line; wherein forming the select line comprises: connecting first and second conductive layers of the select line that are separated by an interlayer dielectric using a contact that extends from a third conductive layer, formed on the second conductive layer, to the first conductive layer, the contact formed in a hole that passes through the second conductive layer and the interlayer dielectric layer and that terminates at the first conductive layer.