1. A method of emulating a completely connected N neuron structure on a computer system apparatus having a neural synapse processor structure, where N is an integer greater than one, comprising the steps of: switching N communicating adder tress to a communications mode; loading the structure with initial weights, neuron output values, general cell data paths, and command path bits; issuing a multiply instruction to the communicating adder trees; receiving the multiply instruction in synapse processor units; switching the communicating adder trees to a function mode; multiplying neuron values by weight values; summing the products of neuron and weight values in the communicating adder trees; receiving and adding an external input value to the sum of the products of neuron and weight values; generating N neuron output values from neuron activation function units; switching the communicating adder trees to a communications mode; and issuing the neuron output values to the communicating adder trees.