1. A method for resynthesizing a design of an integrated circuit using a parallel processing mode, comprising the steps of: (a) entering a single processing mode by activating a main thread and locking a semaphore associated with the main thread, (b) resynthesizing the design of the integrated circuit using the main thread, (c) identifying tasks to be accomplished in the parallel processing mode, (d) unlocking the semaphore associated with the main thread, (e) ceasing operation of the single processing mode, (f) activating ordinal threads by unlocking a semaphore associated with each ordinal thread, (g) processing the tasks in parallel by assigning the tasks to the ordinal threads and the main thread, (h) upon completion of one of the assigned tasks by one of the ordinal threads, determining whether an additional task remains to be assigned, (i) in the case where the additional task remains, then assigning the additional task to the completed one of the ordinal threads, (j) in the case where the additional task does not remain, then inactivating the completed one of the ordinal threads, and (k) upon inactivation of all of the ordinal threads, returning to the single processing mode, with the ordinal threads remaining inactive unless and until the main thread identifies more tasks to be accomplished in the parallel processing mode.