1. A circuit comprising: a cache configured to store translations between address domains, the cache addressable as a first logical portion and a second logical portion, the first logical portion configured to store translations between a first address domain and a second address domain, the second logical portion configured to store translations between the second address domain and a third address domain; and a processor configured to 1) control a bypass of at least one of the first and second logical portions with respect to an address request and 2) match the address request against a non-bypassed portion of the cache in accordance with the bypass and output a corresponding address result.