1. A data flow machine, comprising at least two processor elements capable of receiving an input data token and operatively interconnected to receive and transmit data tokens between them, each of said processor elements comprising: (a) two processors operatively connected, each of said processors further comprising control logic, data paths operatively connecting at least one execution unit, an input means connected to receive said input data token to a data flow memory in a one-to-one operative connection with said processor and deliver said input data token to said data flow memory, said input means of each of said processors further comprises a first input FIFO register, a second input FIFO register, and a third input FIFO register, said first input FIFO register operatively connected to receive an input data token from the data flow memory in the one-to-one operative connection with that processor, said second input FIFO register operatively connected to receive an input data token from the other processor of the same processor element, and said third input FIFO register operatively connected to receive an input data token from another processor element, a flag checking and updating means, a transmitting means and an output means to output said data token, said output means connected to said execution unit and comprising a first output FIFO register, a second output FIFO register, and a third output FIFO register, (b) said data flow memory having a plurality of storage locations, each storage location having an address and a plurality of storage areas further comprising: a parameter storage area for storing at least one parameter indicator, an operation storage area for storing an operation indicator of an operation to be performed on at least one of said parameter indicators, a flag storage area having a state representative of the presence of parameter indicators required by said operation, and an output target address storage area which provides an output target address to which said output data token is directed; wherein said input means directs an input data token having a target address and a first parameter indicator to one of said storage locations identified by said target address, and in response thereto said flag checking and updating means checks the state of the flag in the flag storage area in the identified storage location to determine if other parameter indicators required by the operation in the identified storage location are present and further updates the state of the flag in the flag storage area in the identified storage location to indicate that said first parameter indicator is present, and in response thereto said transmitting means transmits said operation indicator and those parameter indicators that are present in said identified storage location to said execution unit wherein said operation is performed and a valid output data token is generated only if all parameter indicators required by the operation are present in the identified storage location, said first output FIFO register is operatively connected to transmit an output data token to the data flow memory in the one-to-one operative connection with that processor, said second output FIFO register is operatively connected to transmit an output data token to the other processor of the same processor element, and said third output FIFO register is operatively connected to transmit an output data token to another processor element.