1. A circuit comprising: a first PMOS transistor accepting a first address line; an inverter circuit accepting a second address line; and a pull-up circuit coupled in series to the PMOS transistor and to an output of the inverter circuit, and comprising a second PMOS circuit coupled in series to a first NMOS transistor, the pull-up circuit providing a word line output corresponding to an address provided over the first address line and a second address line, wherein the pull-up circuit is configured to be in a reverse-biased condition when the word line output is in a deselected state.