1. A method for implementing multi-processor memory coherency, comprising: receiving, by a Level-2 (L2) cache of a first cluster, a control signal of the first cluster for reading first data; reading the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, wherein the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and providing the first data read to the first cluster for processing.