1. A circuit configured to cryptographically authenticate itself, comprising: (a) a first plurality of logic cells selected from a first set of supported logic cells; (b) a second plurality of logic cells selected from a second set of supported logic cells; (c) a plurality of interconnections comprising conductive elements, each interconnecting an output of a logic cell in said first plurality of logic cells with an input of at least one logic cell in said second plurality of logic cells, where said interconnections between said first plurality of logic cells and said second plurality of logic cells are selected using a random number source, and where said interconnection selections are configured to comply with (i) wiring limitations, and (ii) circuit area constraints; (d) logic configured to receive inputs to said circuit, use said interconnected first plurality of logic cells and said second plurality of logic cells to cryptographically transform said inputs into result values usable by an external device to authenticate said circuit, and output said result values.