1. Method for analysing a set of original description files for an integrated digital electronic system ( 5 ) in a description language called the HDL language, at the register transfer level, in order to automatically insert instructions in the HDL language into description files to obtain a new set of description files in the HDL language for the integrated digital electronic system including test functions such that during automatic synthesis of the integrated digital electronic system using a new set of files, the integrated digital electronic system obtained builds in at least some of the logical electronic circuits ( 22 , 23 , 24 ) necessary to test the integrated digital electronic system ( 5 ), method characterised in that it includes the following steps: automatic localisation ( 1 ) of HDL instruction sequences that will be at the origin of the memory elements during synthesis of the system ( 3 ), in the original HDL description files; automatic and sequential insertion in at least part of HDL description files, and without relational or functional analysis of the identified memory elements, of so-called SCAN HDL instructions used to obtain at least one so-called “SCAN” chain ( 11 ) connecting the memory elements, during synthesis of the system ( 3 ).