1. A digital PLL frequency synthesizer, comprising: an input receiving a signal having a stable quartz oscillator frequency; a voltage-controlled oscillator outputting a VCO frequency; a first PLL loop connected to an output of said voltage-controlled oscillator and an N/(N&plus;1) frequency divider connected in said first PLL loop for dividing the VCO frequency and generating a divided VCO frequency; a phase-frequency detector having a first input receiving the stable quartz oscillator frequency and a second input receiving the divided VCO frequency, and configured to compare the quartz oscillator frequency with the second frequency, and outputting an output signal connected as a control voltage for said voltage-controlled oscillator; said N/(N&plus;1) frequency divider being configured to be switched over between two adjacent integral divisor factors N and N&plus;1, to divide by N for a duration of M−K cycles, and to divide by N&plus;1 for a duration of K cycles; a phase accumulator connected to said N/(N&plus;1) frequency divider for automatically switching said N/(N&plus;1) frequency divider, wherein a content of said phase accumulator has added thereto the value K with a modulo-M addition with each pulse of the divided VCO frequency and said phase accumulator causing a change in the divisor factor from N to N&plus;1 in a next cycle after each overflow; a PLL phase delay device connected between said N/(N&plus;1) frequency divider and said second input of said phase frequency detector and to said phase accumulator, said phase delay device containing M−1 time-delay elements in a phase delay chain and having first and second control inputs, said first control input for setting a respectively corresponding magnitude of a fundamental delay of each said time-delay element of said phase delay chain, and said second control input for setting a number of the fundamental delays to be active in said phase delay chain, wherein the contents of said phase accumulator are increased with each output pulse of said phase delay device by the adjustable fraction K of the reference frequency modulo-M, and wherein, in event of an overflow, said N/(N&plus;1) frequency divider is switched to N&plus;1 for a next period; said phase accumulator having an output connected to said second control input of said phase delay device; a further phase frequency detector having a first input, a second input connected to said output of said voltage-controlled oscillator without an interposition of a time-delay element, and an output; a further phase delay device for simulating corresponding time-delay conditions, configured identically to said PLL phase delay device, but having a number M series-connected time-delay elements, and connected between said output of said voltage-controlled oscillator and said first input of said further phase-frequency detector; and a further loop low pass filter connected between said output of said further phase frequency detector and said first input of said PLL phase delay device and a control input of said further phase delay device for forming an auxiliary PLL and for setting a respectively corresponding magnitude of the fundamental delays of said time-delay elements of said PLL phase delay device and said further phase delay device.