1. A computer-implemented method performed by a computerized device, comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification; and performing by the computerized apparatus instruction-by-instruction checking by determining for each register value modification in the recorded information whether there is a justification to the register value modification by a completed instruction that was completed prior to the register value modification.