1. A processor, comprising: a physical register file comprising a plurality of physical registers each identified by a corresponding one of a plurality of physical register indexes; a rename table with a plurality of entries, each of said plurality of entries storing an architectural identifier identifying one of a plurality of architectural registers, a larger physical register index and a smaller physical register index; mapping logic that detects a partial write instruction specifying an architectural register already identified by an existing entry within said rename table for a previous write instruction having a write size that is larger than said partial write instruction, wherein said mapping logic allocates a first physical register and updates said smaller physical register index of said existing entry with a first physical register index of said first physical register; size tracking logic that sets a merge indication for said partial write instruction if said write size of said previous write instruction is larger than said partial write instruction; and merge logic that merges a result of said partial write instruction with a second physical register during retirement of said partial write instruction in response to said merge indication, wherein said second physical register is identified by said larger physical register index of said existing entry.