1. A device for communicating with a processor and for caching array data, comprising: a cache memory configured to store a plurality of m-dimensional arrays; array attribute storage hardware configured to store array attributes, to receive an array handle from the processor, and to provide selected array attributes according to the received array handle; and an index mapping hardware configured to communicate with the cache memory and to index the m-dimensional arrays in the cache memory using the selected array attributes, the index mapping hardware configured to support n-dimensional arrays in a single pass.