1. A data processing apparatus comprising: a first input bus register of N bits; a second input bus register of N bits; a multiplier having a first input of L bits connected to receive a first set of L bits of said first input bus register , L being less than N, a second input of L bits connected to receive a second set of L bits of said second input bus register , and a product output of 2L bits producing a product of data that was supplied to said first and second inputs; a left shifter having an input connected to receive the product output of said multiplier , a shift amount input and having an output connected to said output bus , said left shifter left shifting said input by said shift amount, discarding said shift amount of at least one most significant bits bit of said input product output, the left shifter producing a shifted result at said output ; and an output bus register of N bits coupled connected to receive said output of said left shifter, said output bus including register storing a first portion corresponding to a most significant set of L bits of said product output of 2L bits shifted result and a second portion of M bits, where said second portion of M bits does not include a least significant set of is not connected to receive the remaining L bits of said product shifted result , and where N=L+M and M≧L.