1. A data prefetcher in a microprocessor having a cache memory, the data prefetcher comprising: wherein the data prefetcher is configured to receive a plurality of memory accesses each to an address within a memory block, wherein the plurality of memory access addresses are non-monotonically increasing or decreasing as a function of time; a storage element; and control logic, coupled to the storage element, wherein as the plurality of memory accesses are received, the control logic is configured to: maintain within the storage element a largest address and a smallest address of the plurality of accesses and counts of changes to the largest and smallest addresses; maintain a history of recently accessed cache lines implicated by the access addresses within the memory block; determine a predominant access direction based on the counts; determine a predominant access pattern based on the history; and prefetch into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.