1. An apparatus, comprising: a parity check matrix having multiple rows of interconnected exclusive-OR gates; and a control circuit configured for sequential scheduling of message passing to update check-nodes and variable-nodes when decoding codeword data blocks received by said apparatus; said control circuit adapted for performing variable-node updates in a zigzag pattern over said parity check matrix in which generation and propagation of messages is performed in opposite directions through said parity check matrix for even and odd iterations of sequential scheduling.