1. An apparatus in a microprocessor, for accomplishing modular multiplication operations, comprising: translation logic, configured to receive a Montgomery multiplication instruction from a source therefrom, wherein said Montgomery multiplication instruction prescribes generation of a Montgomery product, and configured to translate said Montgomery multiplication instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of said Montgomery product; and execution logic, operatively coupled to said translation logic, configured to receive said sequence of micro instructions, and configured to perform said sub-operations to generate said Montgomery product.