1. Apparatus for mapping logical registers, comprising: a map comprising: means for storing a current set of register numbers which are available for assignment in a current cycle and for storing a previous set of register numbers which were assigned in a previous cycle; means for storing a current set of logical register destination operands and for storing a previous set of logical register destination operands; a plurality of register files corresponding to a number of instructions to be mapped in a cycle, said register files each having a plurality of locations, each register file having a plurality of write ports corresponding to said number of instructions to be mapped in a cycle, with said write ports of each of said register files having a write address port and a write data port, and with a first write port of a first one of said register files having the corresponding write address port fed by a first one of the logical destination register operands of a previous set of instructions and the corresponding write data port fed by a first one of the register numbers of the previous set of instructions, and a last write port of a first one of said register files having the corresponding write address port fed by a last one of the logical destination register operands of the previous set of instructions and the corresponding write data port fed by a last one of the register numbers of the previous set of instructions.