1. A modular reduction module, comprising: a plurality of processing elements arranged in a pipeline configuration, each of the plurality of processing elements including a subtractor and configured to output a quotient bit, for each subtraction performed by the subtractor, and a remainder value, for each subtraction performed by the subtractor that results in a positive value; and a shift register configured to provide input to a first processing element among the plurality of processing elements in the pipeline configuration, wherein each subsequent one of the plurality of processing elements in the pipeline configuration receives the quotient bit of the previous one of the plurality of processing elements in the pipeline configuration as an input after each subtraction by the previous one of the plurality of processing elements in the pipeline configuration, each one of the plurality of processing elements outputs a remainder valid signal after completing processing, each of the plurality of processing elements in the pipeline configuration outputs the respective remainder valid signal based on receiving the remainder valid signal of a respective previous one of the plurality of processing elements in the pipeline configuration, and each of the plurality of processing elements in the pipeline configuration outputs the respective remainder valid signal one clock cycle after receiving the remainder valid signal of the respective previous one of the plurality of processing elements in the pipeline configuration.