1. A logic design support system which supports logic design using an HDL, comprising: RTL analysis means for receiving, as input, an input RTL including a dedicated comment as a comment statement specifying expansion of a generate statement, detecting the dedicated comment from the input RTL, and retrieving a generate statement to be expanded; logic expansion means for expanding the generate statement retrieved by the RTL analysis means; and RTL output means for merging a portion not retrieved by the RTL analysis means from the input RTL with a portion expanded by the logic expansion means, and generating and outputting output RTL.