1. A processor comprising: a decode unit to decode a plurality of control transfer instructions, the plurality of control transfer instructions including a first control transfer instruction and a second control transfer instruction; an execution unit to execute the plurality of control transfer instructions; and a retirement unit to retire the first control transfer instruction, wherein the retirement unit is to raise a fault if a next instruction to be retired after the first control transfer instruction is not the second control transfer instruction and the target instruction is in code using the plurality of control transfer instructions.