1. A computer comprising: a plurality of cells coupled in a communications network, each of said cells comprising: a memory for storing instructions in a plurality of memory packets, wherein each of said memory packets is associated with a linked list, said linked list specifying an order of instruction execution; transmission packet generating means coupled to said memory for generating an outgoing transmission packet containing a first instruction, a first register value, and a first link field for storing a destination cell specifier and a destination memory packet address; output means coupled to said transmission packet generating means for transmitting the outgoing transmission packet to a cell identified by said destination cell specifier in the outgoing transmission packet; input means coupled to said memory for receiving a plurality of incoming transmission packets, one of said plurality of incoming transmission packets containing a second instruction, a second register value, and a second link field for storing a target memory packet address; and processing means coupled to said memory, input means and generating means for processing the one of said plurality of incoming transmission packets by executing the second instruction using a data element contained in one of said plurality of memory packets identified by said target memory packet address as an operand; wherein the first instruction is retrieved from the one of said plurality of memory packets identified by said target memory packet address.