1. A reconfigurable parallel look-up table system comprising: a memory; a plurality of look-up tables stored in said memory; a row index register for holding the values to be looked up in said look-up tables; a column index register for storing a value representing the starting address of each said look-up table stored in said memory; and an address translation circuit responsive to said column index register and said row index register to simultaneously generate an address for each value in said row index register to locate in parallel the functions of those values in each look-up table.