1. A processor, comprising: an instruction supply means for supplying a plurality of instructions, each instruction including information specifying the instruction's operation and execution condition information specifying a condition indicating whether the instruction is executed; a decoding means for decoding the plurality of instructions; an instruction issue control means which references the condition specified by the execution condition information to determine an instruction or a set of instructions whose valid operation is executed; and an execution means for executing one or a plurality of operations based on the information specifying the operation of the instructions; wherein the instruction issue control means has the function to decide, by referencing the condition specified by the execution condition information, whether an instruction is a valid instruction that needs to be executed or an invalid instruction that does not need to be executed, to cause the deletion of an instruction that has been decided to be an invalid instruction before it is issued to the execution means, and to issue a valid instruction following that invalid instruction to the execution means instead of the invalid instruction.