1. A data processing system comprising: a register; a storage circuit; select logic for generating a first select signal and a second select signal, said select logic providing the first select signal to said register and providing the second select signal to said storage circuit, said select logic selectively asserting the first select signal, said select logic selectively asserting the second select signal, said select logic being coupled to said register and to said storage circuit; and a source circuit, coupled to said register and to said storage circuit, so that when a write access is made to said register, if the first select signal is asserted said source circuit transfers a value into said register, if the second select signal is asserted said source circuit transfers the value into said storage circuit, and if both the first and second select signals are asserted said source circuit transfers the value into both said storage circuit and said register.