1. A computer processor configured to generate a design verification environment that simulates testing on an integrated circuit device, the processor being in communication with a user interface and a memory, the processor configured to execute: an environment building program that builds a graphical environment for display on the user interface, the graphical environment comprising at least one verification graphic, each verification graphic associated with source code that simulates a verification module having connection signals that interact with the integrated circuit device upon execution; a signal connector program that assigns connection signals of verification graphics in the graphical environment to corresponding signals of the integrated circuit device, the connection signals associated with source code that simulates a connection between a verification module and the integrated circuit device upon execution; and a code generating program that generates test simulation code that simulates operation of the integrated circuit device upon execution; wherein the memory is configured to maintain an available verification module array that includes at least one verification graphic corresponding to source code representing a verification module, wherein the environment building program displays the available verification module array and the graphical environment via the user interface and adds verification graphics to the graphical environment in response to receiving an add-graphic input signal from the user interface, wherein the signal connector program assigns a connection signal for each verification graphic of the graphical environment to the integrated circuit device, wherein the code generating program generates a test simulation code in response to receiving a generation input signal via the user interface, the test simulation code based at least in part on the source code associated with each verification graphic of the graphical environment and each connection signal assigned by the signal connector program, and wherein the test simulation code is generated in a format for execution on a simulator that simulates testing of the integrated circuit device.