1. A system comprising: a processor configured to: insert an initialization instruction that is used to facilitate detection of runtime incidental atomicity, wherein the initialization instruction is inserted at a safepoint where an execution state of a central processing unit is known, and wherein the initialization instruction comprises an instruction to speculatively execute a particular number of instructions; initiate speculative execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units that immediately follows the inserted initialization instruction, wherein: at least some of the plurality of instruction units correspond to predetermined safepoints associated with known central processing unit execution states, wherein the predetermined safepoints were determined prior to initiation of speculative execution, and wherein thread execution between two consecutive predetermined safepoints is guaranteed to be atomic; at least one of the plurality of instruction units comprises a plurality of machine instructions that emulates one or more virtual instructions; thread execution of each of the plurality of instruction units is guaranteed to be atomic; and the plurality of instruction units is not programmatically specified to be executed atomically together; and in response to a determination that the particular number of instructions are successfully executed atomically without interruption, record information associated with the atomic execution, including establishing an incidentally atomic sequence of instruction units, wherein the incidentally atomic sequence of instruction units comprises a sequence of instruction units that was incidentally atomically executed, and wherein establishing the incidentally atomic sequence of instruction units includes: determining an ending instruction unit, and wherein the incidentally atomic sequence of instruction units corresponds to a sequence of executed instruction units starting at the beginning instruction unit that immediately followed the inserted initialization instruction and ending at the determined ending instruction unit; and a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.