1. A method comprising: receiving, at a register file divided into a plurality of lanes, a set of control bits associated with a current instruction, wherein a scheduler unit is configured to generate the set of control bits; combining the set of control bits with a set of valid bits associated with previously issued instructions, each valid bit in the set of valid bits indicating whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block; and for each thread in the thread block, enabling or disabling one or more bypass paths in a corresponding lane of the register file based on the set of control bits and the set of valid bits.