1. A nonvolatile semiconductor memory device having a plurality of memory cells (1-4) arranged in a matrix of rows and columns and each connected to a row selecting signal line (WL.sub.1) and a bit line (BL.sub.1) in which information can be electrically written and erased, each of said memory cells comprising a memory transistor (101) having a first electrode (102), a second electrode (103) and a third electrode (104), a capacitance (106) connected between the first electrode and the second electrode of said memory transistor, a first row selecting transistor (107) connected between the first electrode of said memory transistor and said bit line, a control gate line (CGL.sub.1) for applying a control gate signal to the second electrode of said memory transistor, and a second row selecting transistor (108) connected between the second electrode of said memory transistor and said control gate line, a control transistor (109) connected to the third electrode of said memory transistor, and means (EER) for rendering said control transistor non-conductive and rendering the third electrode of said memory transistor to be floating.