1. An information processing apparatus having a first and a second arithmetic processors that simultaneously execute same processing, a first control device connected to the first and the second arithmetic processors, and a storing device and a second control device both connected via the first control device, the first control device comprising: a synchronization break detecting unit that detects a synchronization break by detecting abnormality that occurs in any one of the first and the second arithmetic processors; an instruction issue stopping unit that stops issuance of an instruction of the arithmetic processor in which the abnormality is detected; an instruction inhibiting unit that inhibits an instruction issued from a second control device to the first control device; a saving unit that saves inside information held by a normal arithmetic processor of the first and the second arithmetic processor into the storing device; an initializing unit that initializes the first and the second arithmetic processors; a restoring unit that restores the inside information saved in the storing device to the initialized first and second arithmetic processors; and an instruction inhibition canceling unit that cancels the inhibition of the instruction issued from the second control device to the first control device and that resumes synchronous operation of the first and the second arithmetic processors, when the inside information is restored to the first and the second arithmetic processors.