1. An apparatus for receiving a first clock signal and a second clock signal and outputting a digital code, the apparatus comprising: a sampling circuit for using a sampling of the second clock signal by the first clock signal to generate a first intermediate clock signal and a second intermediate clock signal; an asynchronous counter for outputting a first intermediate code for representing a number of clock edges of the first clock signal within a duration defined by the first intermediate clock signal; a TDC (time-to-digital converter) for outputting a second intermediate code to represent a timing relationship between the second intermediate clock signal and the second clock signal; and a processor for generating the digital code based on a weighted sum of the first intermediate code and the second intermediate code.