1. A memory device, comprising: a first array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure comprising: a first signal electrode, a second signal electrode, and a resistive layer positioned between the first signal electrode and the second signal electrode with an amorphous or crystalline conduction channel and lateral composition gradient; and a second array of memory structures disposed in rows and columns and constructed either above or below the first array of memory, each memory structure comprising a first signal electrode, a second signal electrode, and a resistive layer between the first signal electrode and the second signal electrode, wherein the second array increases storage capacity of the memory device.