1. A memory system, comprising: a memory controller and a nonvolatile memory device, the nonvolatile memory device including: a nonvolatile memory cell array including a plurality of memory cell strings, each memory cell string including a string selection transistor, a ground selection transistor, and a plurality of nonvolatile memory cells connected in series between the string selection transistor and the ground selection transistor along a direction that is substantially perpendicular to a substrate, the plurality of nonvolatile memory cells being stacked on or above the substrate in the direction that is substantially perpendicular to the substrate, and control logic configured to detect threshold voltages of the plurality of string selection transistors and to provide information associated with the threshold voltages; wherein, during at least one of a program, read and erase operation, the string selection transistor of each memory cell string is responsive to a first selection voltage to connect the memory cell string to a bit line and a second selection voltage to isolate the memory cell string from the bit line, wherein the threshold voltages are detected when a program operation is performed, when a plurality of program operations are performed, or periodically.