1. A system, comprising: at least one central processing unit; at least one memory unit; and a plurality of integrated circuits that form a switching fabric configured to route data packets between the at least one central processing unit and the at least one memory unit, wherein the switching fabric is constructed using at least two directed acyclic graph (DAG) networks, wherein the at least two DAG networks comprise one selected from a group consisting of a quadrant-DAG and a never-this-direction DAG, and wherein the never-this-direction DAG comprises one selected from the group consisting of a not-south DAG, a not-east DAG, a not-west DAG, and a not-north DAG.