1. A method, comprising: configuring a performance monitor to emulate trapping on a cache line flush type instruction, wherein said configuring comprises configuring a hardware performance counter to trigger an interrupt after a pre-determined number of cache line flush type instructions have been executed; in response to the hardware performance counter triggering an interrupt after the pre-determined number of cache line flush type instructions have been executed: inspecting program instructions of an executing process or application that includes the cache line flush type instructions; determining, dependent at least in part on said inspecting, whether the cache line flush type instructions are being employed within a timing side-channel attack; and in response to determining that the cache line flush type instructions are being employed within a timing side-channel attack, taking action to curtail the timing side-channel attack, wherein said taking action comprises modifying the program instructions or page mapping of the executing process or application that includes the cache line flush type instructions.