1. A processor comprising: a cache comprising a plurality of banks, wherein each bank of the plurality of banks can be accessed independently of other banks; wherein the processor is configured to: detect that a first store operation conflicts with a first load operation in a first clock cycle in at least one bank of the cache; perform a first partial write of a first portion of the first store operation to the cache in the first clock cycle; perform the first load operation by reading from the cache in the first clock cycle; and delay a second partial write of a second portion of the first store operation to the cache until a subsequent clock cycle, wherein the second portion of the first store operation conflicts with the first load operation.