1. A data processing apparatus comprising: a SIMD (single instruction multiple data) array of processing elements, each of which includes an internal memory unit, the processing elements being divided into a plurality of processing blocks, which processing blocks are operable to process respective groups of data items; an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another; and a data transfer controller operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.