1. A data processing system having an instruction processing unit (IPU) and a storage array organized on word boundaries or multi-word boundaries where a word is some number of consecutive bytes representing the basic unit of computation for said instruction processing unit, comprising: said instruction processing unit and said storage array; and hardware accelerator means for cross-boundary storage access to said storage array including a cross boundary buffer means for providing residual read and write data to said instruction processing unit in support of high speed, block concurrent accessing of multi-word operands of said system and for operating on multiple words, with residues from a second and subsequent accesses enabling continuation of the accessing process by said hardware accelerator means beyond two memory words to span more than a word boundary and to allow high speed block-concurrent accesses to and from said storage array for load multiple and store multiple instructions.