1. A matrix of a plurality of processing elements interconnected with each other and wherein each processing element comprises: a memory; an adder; a selectably variable length shift register operatively connected to said adder, said shift register comprising a plurality of individual shift registers having gates interposed therebetween, said gates selectively interconnecting said individual shift registers; and communication means connected to neighboring processing elements within said matrix and further connected to said adder and memory for transferring data between said memory, adder, and neighboring processing elements.