1. A processing core that executes a compare instruction, the processing core comprising: a plurality of general-purpose registers comprising a first input operand register, a second input operand register and an output operand register; a register file comprising the plurality of general-purpose registers; comparison logic coupled to the register file, wherein the comparison logic tests for at least two of the following relationships: less than, equal to, greater than and no valid relationship; decode logic which selects the output operand register from the plurality of general-purpose registers; and a store path between the comparison logic and the selected output operand register.