1. A computer-implemented method for creating in computer memory a representation of interconnections between very large scale integrated (VLSI) circuit design components of a hierarchical circuit design, comprising the steps of: storing in the computer memory a VLSI circuit design component identifying a leaf design entity from the hierarchical circuit design; storing in the computer memory a set of placements in the design where the VLSI circuit design component appears, the placements representing a subset of instances of the leaf design entity; associating with the VLSI circuit design component and the placements a set of links, the links connecting various ones of the placements to one another to further denote placement of the VLSI circuit design component within the hierarchical circuit design; storing the set of links in the computer memory; computing interconnections denoting where placements of instances of VLSI circuit design components are interconnected; and storing the interconnections in the computer memory.