1. A branch control apparatus in a microprocessor, comprising: an instruction cache, for outputting a line of instruction bytes selected by a fetch address; an instruction buffer, coupled to said instruction cache, for buffering said line of instruction bytes; a branch target address cache (BTAC), coupled to said fetch address, for providing offset information relating to a location of a branch instruction within said line of instruction bytes; and selection logic, coupled to said BTAC, for causing a portion of said instruction bytes to not be provided to said instruction buffer, based on said offset information.