1. A computing device, comprising: a processor comprising one or more processing cores and operating in a multi-tenant environment, wherein the one or more processing cores are configured to execute at least a first virtual machine and a second virtual machine simultaneously, and the first virtual machine comprising a first plurality of computer executable instructions for a first tenant and the second virtual machine comprising a second plurality of computer executable instructions for a second tenant; a hardware resource configured to be shared by the first virtual machine and the second virtual machine executing simultaneously on the one or more processing cores; a hardware timer configured to generate a timer value using at least a phase locked loop; and a delay timer module, using hardware logic or microcode, configured to delay accessing the timer value from the hardware timer in response to a request for the timer value, wherein the delay is based on a completion of at least one micro-architectural event introduced before accessing of the timer value from the hardware timer, wherein the at least one micro-architectural event is one or more of a Level 1 cache miss resulting in Level 2 cache read, a Level 2 cache miss resulting in Level 3 cache read, a Level 3 or Level 4 cache miss resulting in system memory read, a Translation Look aside Buffer miss resulting in a page-table walk, a branch mis-prediction resulting in speculative execution of an incorrect instruction, or a pipeline stall.