1. A processor having an instruction set architecture (ISA), the processor comprising: an execution pipeline having a plurality of execution units that execute microinstructions; and an instruction translator that translates architectural instructions defined by the ISA into the microinstructions, the instruction translator comprising: a memory that holds microcode instructions and provides a plurality of microcode instructions per clock cycle in response to an address; a queue that holds microcode instructions provided by the memory; a branch decoder, coupled between the memory and the queue, that decodes the plurality of microcode instructions provided by the memory to detect one or more local branch instructions among the plurality of microcode instructions, causes microcode instructions of the plurality of microcode instructions up to but not including a first-in-program-order local branch instruction of the one or more local branch instructions to be written to the queue, and prevents the first-in-program-order local branch instruction and following microcode instructions of the plurality of microcode instructions from being written to the queue, wherein local branch instructions are resolved by the instruction translator rather than the execution pipeline; and a plurality of microcode translators that translate a plurality of microcode instructions received from the queue per clock cycle into a plurality of microinstructions for provision to the execution pipeline.