1. A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line, said bit line being connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored in the memory cell, said evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, said control loop comprising a differential amplifier having an inverting input operatively connected to the bit line, a non-inverting input supplied from a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and said inverting input, wherein said feedback circuital path is adapted to conduct a measure current corresponding to said cell electric current, and comprises current/voltage conversion means for converting said measure current into a corresponding voltage; wherein said conversion means of the feedback circuital path comprise at least one first transistor arranged so as to conduct said measure current, and biasing means adapted to bias said at least one first transistor so as to emulate the behavior of a resistor.