1. An integrated circuit, comprising: configuration memory cells coupled to a hard macro via configuration registers; the configuration memory cells for storing values for initializing the hard macro; the hard macro initialized to function as an operable circuit selected from a group consisting of a Peripheral Component Interconnect Express (“PCIe”) Endpoint, a PCIe Root Complex, and a PCI Advanced Switching block responsive to output of the values from the configuration memory cells; the configuration registers coupled to be loaded with the values stored by and output from the configuration memory cells; and write management busing coupled to the configuration registers for overwriting at least one of the values loaded into the configuration registers for reconfiguration of the hard macro from the configuration registers without having to overwrite the configuration memory.