1. A zero counter comprising a plurality of hardware logic blocks each arranged to calculate one bit of an output value, the output value corresponding to a number of trailing or leading zeros in an input string, wherein each hardware logic block in the plurality of hardware logic blocks is arranged to calculate a bit of the output value and comprises: a low section hardware logic block comprising inputs arranged to receive bits from a first section of a received string, the first section including a least significant bit in the input string, and one or more logic gates arranged to combine the received bits and generate at least one output; a high section hardware logic block comprising inputs arranged to receive bits from a second section of the received string, the second section including a most significant bit in the received string, and one or more logic gates arranged to combine the received bits and generate at least one output; and combining logic arranged to combine the outputs of the two section hardware logic blocks and generate a bit of the output value.