1. A computer-implemented process, comprising the steps of: (a) loading a first microcode program of a first application program onto memory in an Intel.RTM. i750.TM. Pixel Processor, wherein the first application program runs on a host processor; (b) running the first microcode program on the Intel.RTM. i750.TM. Pixel Processor; (c) unloading the first microcode program from the memory of the Intel.RTM. i750.TM. Pixel Processor; (d) loading a second microcode program of a second application program onto the memory in the Intel.RTM. i750.TM. Pixel Processor, wherein the second application program runs on the host processor; (e) running the second microcode program on the Intel.RTM. i750.TM. Pixel Processor; (f) unloading the second microcode program from the memory of the Intel.RTM. i750.TM. Pixel Processor; (g) repeating steps (a) through (f), wherein the first and second application programs run concurrently on the host processor.