1. An apparatus comprising: a decoder to decode three different instructions having an immediate operand into three different decoded instructions; instruction execution circuitry comprising: input vector element routing circuitry to perform the following for each of the three different decoded instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source an output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions; and masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector element routing circuitry, said masking layer circuitry to mask at three different levels of granularity as specified by the immediate operands.