1. An over-programming condition detector for use with an array of multistate memory cells, each cell programmable to store an amount of electric charge representative of a desired state selected from at least four sequential data states, the detector comprising: a first logic gate for detecting a first one of the sequential data states in data intended to be written to the array; a second logic gate for detecting a second one of the sequential data states in data intended to be written to the array; a third logic gate for detecting a third one of the sequential data states in data intended to be written to the array; and a fourth logic gate for receiving data written to the array.