1. An arithmetic and logic device for use in a processing unit, said processing unit comprising a register file capable of providing at least a first source operand, a second source operand, a third source operand, and a destination operand, said processing unit capable of proving a first immediate value, said arithmetic and logic device comprising: an arithmetic and logic unit having a first input, a second input, and an output; a first auxiliary computing unit, a second auxiliary computing unit, a third auxiliary computing unit, each of which has a first, a second, and a third inputs and an output; a control unit controlling the operation of said first, second, and third auxiliary computing units; wherein the outputs of said the first and the second auxiliary computing units are connected to said the first and the second inputs of said arithmetic and logic unit respectively, said output of said the arithmetic and logic unit is connected to said the first input of said the third auxiliary computing unit; said the first immediate value and said the third source operand are connected to said the second and the third inputs of all said auxiliary computing units; said the first source operand is fed to said the first input of said first auxiliary computing unit, said the second source operand is fed to said the first input of said the second auxiliary computing unit, said output of said the third auxiliary computing unit is fed to said the destination operand.