1. A test apparatus for testing a device under test, comprising: an instruction storing section that stores thereon a test instruction sequence; a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction; a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test; and a result register that stores thereon a value having a predetermined number of bits, wherein the instruction storing section stores thereon the test instruction sequence including therein a result register update instruction to update a value of a designated bit position in the result register with a predetermined value, and when executing the result register update instruction, the pattern generating section updates, with the predetermined value, the value of the bit position in the result register which is designated by the result register update instruction.