1. An apparatus comprising: a first memory having a first read latency, wherein a first portion of a sequence of instructions and a size of the first portion is stored at the first memory; and a second memory having a second read latency larger than the first read latency, wherein a second portion of the sequence of instructions is stored at the second memory and the size of the first portion and a size of the second portion are periodically adjusted by a memory controller based, at least in part, on the size of the first portion stored in the first memory, wherein the sequence of instructions follows a branch instruction stored at the second memory, wherein a request for each of the first portion of the sequence of instructions and the second portion of the sequence of instructions is sent without delay responsive to a branch of the branch instruction being taken, wherein the size of the first portion of the sequence of instructions is based, at least in part, on a ratio between latency in accessing the second memory and a latency in accessing the first memory, wherein the first and second portions of the sequence of instructions are written to the first and second memory, respectively, in an interleaving manner based on a write latency of the first memory.