1. A segmented digital to analog converter comprising first, second and third segments, wherein: the first segment (DAC1) comprises a plurality of impedances ( 52. 1 to 52 .S 1 ) arranged in series; the second segment (DAC2) comprises a plurality of current sources ( 62. 1 to 62 .S 3 ) or a current divider; the third segment (DAC3) comprises a current divider ( 72 ); and a controller ( 20 ) arranged to receive an input digital word and to provide first, second and third control words to the first, second and third segments, respectively, such that the first second and third segments cooperate to provide an analog representation of the input digital word.