1. A field programmable gate array (FPGA) for processing received financial orders, comprising: a page manager configured to: receive a message including a financial order, an order identifier, and an action to take with respect to the financial order, segment the order identifier into a first identifier segment and a second identifier segment, and access a first tier of memory to identify a page index corresponding to the first identifier segment; and a main order manager configured to: combine the page index and the second identifier segment into a second tier memory address, and access a second tier memory address in a page in the second tier of memory corresponding to the page index to perform the action with respect to the financial order.