1. A non-volatile semiconductor memory comprising: a first memory device comprising a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments; a memory controller comprising a microprocessor for executing access commands received from a host; interface circuitry operable to generate control signals that enable the microprocessor to communicate with the first memory device; and power fail circuitry operable to transmit a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment.