1. A multiplier circuit comprising: a fused Booth encoder multiplexer unit which uses two input operands to produce a plurality of partial product bits for a multiplication operation, wherein said fused Booth encoder multiplexer unit includes a plurality of encoder-selector cells each having a logic tree which produces a partial product bit according to a Booth encoding and selection algorithm in a single clock phase, said logic tree contains a plurality of logic transistors, each logic transistor in said logic tree has a gate connected to one of a respective plurality of operand bit inputs, said logic transistors are interconnected to carry out a Boolean function according to the Booth encoding and selection algorithm to produce the partial product bit for the multiplication operation at a dynamic node, and a latch is connected to said dynamic node which maintains the value of the partial product bit at an output node, and wherein at least one of said logic trees includes a first transistor stack with a first logic transistor having a source connected to a drain of a power transistor and to said dynamic node and controlled by a first multiplicand bit, a second logic transistor having a source connected to a drain of said first logic transistor and controlled by a complement of a first multiplier bit, a third logic transistor having a source connected to a drain of said second logic transistor and controlled by a complement of a second multiplier bit, and a fourth logic transistor having a source connected to a drain of said third logic transistor and having a drain connected to a source of a foot transistor, and controlled by a third multiplier bit, a second transistor stack with a fifth logic transistor having a source connected to a drain of said power transistor and to said dynamic node and controlled by a complement of the first multiplicand bit, a sixth logic transistor having a source connected to a drain of said fifth logic transistor and controlled by the first multiplier bit, a seventh logic transistor having a source connected to a drain of said sixth logic transistor and controlled by the second multiplier bit, and an eighth logic transistor having a source connected to a drain of said seventh logic transistor and having a drain connected to said source of said foot transistor, and controlled by a complement of the third multiplier bit, a third transistor stack with a ninth logic transistor having a source connected to a drain of said power transistor and to said dynamic node and controlled by a second multiplicand bit, a tenth logic transistor having a source connected to a drain of said ninth logic transistor and controlled by the complement of the first multiplier bit, an eleventh logic transistor having a source connected to a drain of said tenth logic transistor and controlled by the second multiplier bit, and a twelfth logic transistor having a source connected to a drain of said eleventh logic transistor and having a drain connected to said source of said foot transistor, and controlled by the third multiplier bit, and a fourth transistor stack with a thirteenth logic transistor having a source connected to a drain of said power transistor and to said dynamic node and controlled by a complement of the second multiplicand bit, a fourteenth logic transistor having a source connected to a drain of said thirteenth logic transistor and controlled by the first multiplier bit, a fifteenth logic transistor having a source connected to a drain of said fourteenth logic transistor and controlled by the complement of the second multiplier bit, and a sixteenth logic transistor having a source connected to a drain of said fifteenth logic transistor and having a drain connected to said source of said foot transistor, and controlled by the complement of the third multiplier bit; a tree unit which uses the partial product bits to generate a plurality of partial products; and an adder unit which uses the partial products to generate intermediate sum and carry results for the multiplication operation.