1. A computer-implemented method for designing an emulation chip using a selectable fastpath topology, comprising: determining, from a circuit design for the emulation chip, an initial fastpath topology comprising a plurality of processors connected in series such that each of the plurality of processors is one of N levels of the initial fastpath topology, N being an integer greater than one; and reducing, using a computer to process the circuit design, the initial fastpath topology from the N-levels to M-levels, where M is an integer greater than zero and less than N, by changing at least one connection among the plurality of processors such that M processors of the plurality of processors are connected in series and N−M processors of the plurality processors are connected in parallel.