1. An apparatus, comprising: an address swap cache; and a memory segment swap logic to detect a reproducible fault at a first physical address targeting a first physical memory segment in one of a plurality of memory devices; in response to the detection of the reproducible fault, remap the first physical address to a second physical address, the second physical address targeting a second physical memory segment in one of the plurality of memory devices; store the first and second physical addresses in an entry in the address swap cache; receive a memory transaction targeting the first physical address; perform a lookup to identify the entry in the address swap cache storing the first physical address; in response to the identification, swap the second physical address into the memory transaction for the first physical address.