1. A method of invalidating translation entries without deadlock in a multithreaded data processing system including a plurality of processor cores, the method comprising: receiving, in a shared queue, storage-modifying and synchronization requests of a plurality of concurrently executing hardware threads of an initiating processor core among the plurality of processor cores, wherein the plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread among the plurality of hardware threads and the synchronization requests includes a synchronization request of the initiating hardware thread that follows the translation invalidation request; broadcasting the translation invalidation request such that the translation invalidation request is received and processed by the plurality of processor cores to invalidate any translation entry that translates a target address of the translation invalidation request; and in response to receiving the synchronization request in the shared queue, removing the synchronization request from the shared queue, buffering the synchronization request in sidecar logic, iteratively broadcasting the synchronization request buffered in the sidecar logic until all of the plurality of processor cores have completed processing the translation invalidation request, and thereafter removing the synchronization request from the sidecar logic; and while the synchronization request is buffered in the sidecar logic, permitting one or more store requests of the initiating hardware thread that follow the invalidation request to be issued from the shared queue to a memory subsystem of the data processing system, such that deadlock is avoided, wherein at most one synchronization request per hardware thread can be active in the sidecar logic at a time.