1. A processor, comprising: an instruction prefetch buffer storing an instruction code and its instruction address; an instruction pipeline storing said instruction code and its instruction address input from said instruction prefetch buffer, and pipeline-processing said instruction code; a comparison unit to which an instruction address in said instruction pipeline and an instruction address in said instruction prefetch buffer are input, that compares the input instruction address and an instruction address of an instruction code to be read next from an instruction cache memory or from a main memory, to judge whether or not the instruction addresses are identical with each other; and a control unit whose control, when the instruction addresses are identical with each other, is to read the instruction code neither from said instruction cache memory nor from said main memory but to process the instruction code stored in said instruction pipeline or in the instruction prefetch buffer again in said instruction pipeline or in the instruction prefetch buffer.