1. A computer processor comprising: an instruction decoder having a plurality of random access memory elements and a fixed instruction decoding portion, the fixed instruction decoding portion having an input for receiving program instructions and an output coupled to a back-end processing engine configured to function according to a target instruction set architecture, the instruction decoder being internal to the computer processor and operable to: store a first set of logical values for decoding a first set of program instructions in the plurality of random access memory elements, the first set of program instructions being associated with a first instruction set architecture, the first set of logical values generated from: a first set of operational codes generated from the first set of program instructions; and a first set of micro-operations generated from the first set of operational codes; receive a first program instruction associated with the first instruction set architecture from an instruction memory; decode the first program instruction by logically combining a particular one of the first set of logical values with the first program instruction to form a first decoded logic value associated with the target instruction set architecture, the first decoded logic value indicating a decoded output of the first program instruction; transmit the first decoded logic value to the back-end processing engine; store a second set of logical values for decoding a second set of program instructions in the plurality of random access memory elements, the second set of program instructions being associated with a second instruction set architecture, the second instruction set architecture being different from the first instruction set architecture, the second set of logical values generated from: a second set of operational codes generated from the second set of program instructions; and a second set of micro-operations generated from the second set of operational codes; receive a second program instruction associated with the second instruction set architecture from an instruction memory; decode the second program instruction by logically combining a particular one of the second set of logical values with the second program instruction to form a second decoded logic value associated with the target instruction set architecture, the second decoded logic value indicating a decoded output of the second program instruction; and transmit the second decoded logic value to the back-end processing engine; wherein the first and second sets of logical values are generated before execution of the computer processor by a reconfiguration engine that is separate from the computer processor; wherein the first and second sets of logical values are operable to allow the instruction decoder to alternatively decode the first program instruction from the first instruction set architecture and the second program instruction from the second instruction set architecture using a single physical path in the computer processor; and wherein the first and second sets of logical values are generated by: determining a plurality of opcodes from the first and second sets of program instructions; determining bit-locations of the determined plurality of opcodes; determining bit-lengths of the determined plurality of opcodes; composing a plurality of pseudo opcodes; determining a plurality of extended opcodes from the first and second sets of program instructions; determining extended opcode fields from the first and second sets of program instructions; determining bit-locations of the determined plurality of extended opcodes; determining bit-lengths of the determined plurality of extended opcodes; generating aligned opcodes using the plurality of pseudo opcodes, the determined bit-locations, and the determined bit-lengths; and generating the first and second sets of logical values using the determined extended opcodes and the aligned opcodes.