1. In a computer system having a processor for performing memory access by specifying an address in a main memory, and a cache memory comprising cache lines, a cache access controller comprising: a control circuit for producing a plurality of access values in response to said address, each access value associated with a corresponding one of said cache lines and having a true or a false state; and an access logic circuit for permitting caching of information associated with said address at one of said cache lines if its corresponding access value is true.