1. An apparatus comprising: a processor having an execution unit including a plurality of logic units to execute instructions, the execution unit including: a first selector to select a first portion or a second portion of an input operand based on whether an instruction is to perform a reciprocal operation or a square root reciprocal operation; a lookup table coupled to the first selector and including a plurality of entries, wherein the output of the first selector is to access a given one of the plurality of entries, each of the entries including a first term, a second term, and a legacy portion, wherein the first and second terms are set at a midpoint of an interval; and a reciprocal logic unit to receive the accessed entry and a portion of the input operand and to generate a reciprocal result for the input operand responsive to the instruction.