1. An information processing apparatus comprising: a main memory that stores data; a plurality of processors each provided with a primary cache memory; a secondary cache memory that is provided between the main memory and the processors, the secondary cache memory having larger capacity than one or more of the primary cache memories; and a cache controller that performs cache search on the secondary cache memory based on a second index uniquely generated by joining: 1) a bit string having a predetermined bit length; and 2) a first index that is included in a data access command transmitted from any one of the processors, the first index being used for performing cache search on the one or more of the primary cache memories, wherein the cache controller generates the bit string by performing a logical operation on a flag and a candidate number, the flag being included in the data access command, and the candidate number being updated when the cache controller performs a cache miss determination.