1. A multi-processor system comprising: a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests; and a log that retains executed load instruction entries associated with executed program instructions, the executed load instruction entries being retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.