1. An apparatus for FPGA configuration protection comprising: watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured; watchdog circuitry configured to receive the watchdog signal, to initiate reconfiguration of the FPGA with a reset signal if the watchdog signal is not received for or within a predetermined time, and to repeat until a successful configuration occurs; circuitry in the FPGA configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received; and a multiplexer which transfers watchdog signal responsibilities to the processor after the processor is released from reset.