1. A vector processor comprising: a register file containing vector registers; a decoder which during decoding of an instruction identifies a selected vector register from the register file and identifies a size for data elements to be processed during execution of the instruction; and processing circuitry coupled to the vector register, wherein the processing circuitry when executing the instruction performs a number of parallel operations on data elements from the selected vector register, the number of parallel operations being controlled by the size for the data elements.