1. A microprocessor comprising: a memory; an instruction bus; instruction prefetch means, coupled to said memory, for prefetching instruction codes from said memory and for transferring prefetched instruction codes onto said instruction bus, said prefetched instruction codes including a conditional branch instruction code, said instruction prefetch means further performing, in response to a branch target instruction prefetch request, a branch target instruction prefetch operation for prefetching a branch target instruction code from a branch address of said memory and transferring said branch target instruction code onto said instruction bus, said branch target instruction code including first instruction data belonging to a branch target instruction and second instruction data belonging to an instruction other than said branch target instruction; decoding means, coupled to said instruction prefetch means, for receiving said prefetched instruction codes, for producing decoded instruction information in response to said prefetched instruction codes, for receiving said conditional branch instruction code and for producing address information indicative of said branch address and branch condition information indicative of a branch condition of said conditional branch instruction; execution means, coupled to said instruction prefetch means and said decoding means, for executing an instruction in response to said decoded instruction information, for responding to said branch condition information to determine whether said branch condition is satisfied and for producing a branch execution signal when said branch condition is satisfied; and generating means, coupled to said decoding means and responsive to said address information, for generating and supplying said branch target instruction prefetch request to said instruction prefetch means, and for generating less significant bit data of said branch address in response to said address information; said instruction prefetch means comprising: a first buffer coupled to said instruction bus; a second buffer coupled to said instruction bus; means for controlling said first buffer to temporarily store said prefetched instruction codes; means for controlling said second buffer to temporarily store said branch target instruction code; aligner means, coupled to said second buffer and said generating means and responsive to said less significant bit data generated by said generating means, for outputting said first instruction data and for preventing said second instruction data from being output when said branch condition is satisfied; gate means coupled between said aligner means and said decoding means; and means, coupled to said decoding means and said execution means and responsive to said branch execution signal, for altering a state of said gate means from a closed state to an open state for immediately transferring said first instruction data from said aligner means to said decoding means when said branch condition is satisfied, said gate means being maintained in said closed state when said branch execution signal is not generated.