1. A processing unit for a multiprocessor data processing system, said processing unit comprising: a processor core including: a store-through upper level cache; an instruction sequencing unit that fetches instructions for execution; a data register; at least one instruction execution unit coupled to said instruction sequencing unit that concurrently executes multiple threads of instructions; and wherein the processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of said first thread to a store target address matching the load target address to fail if said store-conditional operation of said second thread succeeds.