1. A system for selecting processor states on a platform, comprising: a processor having a circuitry for providing hardware feedback related to current processor frequency, processor state, and percentage of time the processor is busy; means for adjusting the hardware feedback based on processor stall time information and for updating the processor state based on the adjusted hardware feedback, the adjusting and updating being performed before an effective processor state is read by logic to update the processor state; the means for adjusting and updating further comprises, logic to modify a value for a first machine state register before allowing one or more actors to use the results of a calculation of a ratio of the first machine state register and a second machine state register, wherein the modification applies processor stall time information.