1. A method for improving performance of a synchronous logic circuit having logic stages, comprising: dynamically generating a main clock signal associated with the synchronous logic circuit; generating at least one backup register clock signal, the backup register clock signal at the same frequency as the main clock signal and phase shifted from the main clock signal to thereby provide additional time for one or more of the logic stages to execute; and driving the at least one backup register of the synchronous logic circuit with one of the at least one backup register clock signal.