1. An apparatus comprising: a functional unit of an instruction execution pipeline comprising a plurality of compare-and-exchange circuits in parallel and coupled to network circuitry to execute a single vector sorting instruction to sort an input operand of one or more vectors into numerical order, each of said compare-and-exchange circuits having a respective comparison circuit that compares a pair of inputs, each of said compare-and-exchange circuits having a first output for presenting a higher of the pair of inputs and a second output for presenting a lower of the pair of inputs; and a memory circuit containing microcode that provides control signals to said network circuitry to loopback each output of the plurality of compare-and-exchange circuits into the plurality of compare-and-exchange circuits until each vector of an input operand of a plurality of vectors is sorted.