1. A data processing apparatus, comprising: a plurality of registers operable to store items of architectural state; a plurality of functional units, each functional unit being operable to perform a processing operation with reference to one or more of said items of architectural state; at least one of said functional units having a register cache associated therewith having one or more cache entries, each cache entry being operable to store a copy of one of said items of architectural state and a register identifier identifying the register containing that item of architectural state; and control logic operable to determine a subset of said items of architectural state to be copied in said register cache in dependence on the processing operation of the functional unit with which said register cache is associated.