1. A thread arbitration system for use in a processor, the system comprising: an array comprising a plurality of first entries each corresponding to an element of the array, wherein the array is shared by a plurality of threads, and wherein each entry of the plurality of first entries is configured for use by any thread of the plurality of threads; control circuitry, wherein in response to determining a given thread has not deallocated any entry of the plurality of first entries for a predetermined first amount of time, the circuitry is further configured to store an indication that the given thread has been identified as a thread hog; a thread arbitration table comprising a plurality of second entries, wherein each entry of the second entries is configured to indicate a high threshold value and a low threshold value; and a thread history shift register (HSR) corresponding to the given thread, wherein the thread HSR is used for indexing into the thread arbitration table to select a corresponding second entry, wherein each bit of the thread HSR indicates whether the given thread was identified as a thread hog over a previous predetermined second amount of time.