1. An electronic logic circuit comprising: a plurality of areal capacitive coupling devices coupled to process a set of data inputs; each areal capacitive coupling device being configured such that a floating gate potential of such device can be altered in response to receiving an input signal from said set of data inputs; wherein said floating gate potential can be adjusted to place said areal capacitive coupling device into a first state or a second state through areal capacitive coupling to a potential associated with a first active region receiving said input signal; said plurality of areal capacitive coupling devices being interconnected to generate a first logic output which is a first logical function associated with the set of data inputs.