1. A tag memory having an automating tag comparison mechanism, comprising: a memory cell array, configured to store a plurality of cache tags, wherein the memory cell array receives an index related to a memory address and outputs a plurality of row tags in the cache tags based on the index; a plurality of sensing amplifiers coupled to the memory cell array to receive the row tags and performing a signal amplification process on the row tags to serve as a plurality of comparison tags; and a tag comparison circuit, configured to receive a target tag related to the memory address and coupled to the sensing amplifiers to receive the comparison tags, wherein the tag comparison circuit compares the target tag with each of the comparison tags parallelly, when one of the comparison tags matches the target tag, the tag comparison circuit outputs a location of the matched comparison tag to serve as a first column address, and the first column address is a column address where the memory address corresponds to a first data memory.