1. An apparatus used for testing an embedded memory in an integrated circuit, comprising: a clocked element that inputs data from a data-input path and outputs data along a data-output path; a primary multiplexer having a primary output coupled to the data-input path and two or more primary inputs coupled to at least a system-data path and a secondary-multiplexer path, respectively, the primary multiplexer being operable to selectively output at least system data or secondary-multiplexer data on the data-input path; and a secondary multiplexer having a secondary output coupled to the secondary-multiplexer path and secondary inputs coupled to at least a scan-chain-data path and a memory-test-data path, the secondary multiplexer being operable to selectively output at least scan-chain data or memory-test data on the secondary-multiplexer path, wherein the data-output path comprises input logic and is coupled to an input of an embedded memory that is not part of a scan chain path, and wherein the memory-test-data path comprises compensatory logic and is coupled to an output of a memory built-in self-test (MBIST) controller, the compensatory input logic being configured to perform an inverse function of the input logic.