1. A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device, comprising: a unit configured to assume as a virtual wiring line a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit configured to calculate a parallel wiring length along which said virtual wiring line and said intra-macro wiring line run; and a unit configured to output information concerning said virtual wiring line when said parallel wiring length exceeds a reference value defined as a design rule.