1. An accumulating multiplication circuit comprising: a multiplication part for executing an operation for first and second input data, including "n" bits, respectively, and for outputting a first 2n-bit data; an arithmetical operation part for executing an operation for said first 2n-bit data and a second 2n-bit data and for outputting a third 2n-bit data; a shifter receiving said third 2n-bit data, for shifting said third 2n-bit data rightward by "n" bits so as to output the shifted third 2n-bit data; and a selector receiving said second 2n-bit data and said shifted third 2n-bit data, for selectively supplying said second 2n-bit data as it is to said arithmetical operation part or supplying said shifted third 2n-bit data as said second 2n-bit data inputted to said arithmetical operation part; said multiplication part comprising: first through fourth registers for holding most significant "n" bits of a multiplier, where "n" is a positive integer, least significant "n" bits of said multiplier, most significant "n" bits of a multiplicand, and least significant "n" bits of said multiplicand, respectively; a first multiplexor for selecting either an output data of said first register or an output data of said second register, so as to supply a selected output data; and a Booth's decoder receiving said selected output data outputted from said first multiplexor.