1. A method comprising: calculating simulated contours of one or more structures representing an IC design layout; calculating evaluation cutlines along the simulated contours, each cutline corresponding to an evaluation site; extracting one or more image parameters for the evaluation cutlines;□inter-structure coarse selection followed by intra-structure fine selection of evaluation sites; calibrating an optical proximity correction (OPC) model for the IC design layout based on measurements at the selected evaluation sites; and manufacturing an IC based on the calibrated OPC model.