1. A system comprising: a device controller apparatus including a transfer buffer, and a non-volatile memory (NVM) communicatively coupled to the device controller apparatus, the NVM including a set of multi-level NVM cells and a chip controller apparatus that includes a substrate and logic, implemented in fixed-functionality hardware and coupled to the substrate, the logic to: read a lower page from the set of multi-level NVM cells, read one or more intermediate pages from the set of multi-level NVM cells, and read a last page from the set of multi-level NVM cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is to be substantially similar to an intermediate read time associated with the one or more intermediate pages.