1. An integrated circuit comprising: a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies; an instruction scheduler adapted to: evaluate a received plurality of instructions to detect data dependencies between individual instructions in the received plurality of instructions; generate, in response to the data dependencies, a control signal that indicates whether data dependency was identified between a set of instructions of the plurality of received instructions; assign the set of instructions to the first data processing unit and the at least one second data processing unit for parallel execution in response to the control signal indicating a lack of data dependency between the set of instructions; and monitor, for instructions received over a period of time, data dependencies indicated by the control signal to determine a level of data dependencies over the period of time; and wherein the integrated circuit is operable in a first power mode and a second power mode, the second power mode being a reduced power mode compared to the first power mode, and is adapted to adjust an operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the level of data dependencies.