1. A microprocessor that supports an instruction set architecture that specifies a plurality of processor modes and that specifies architectural registers associated with each of the plurality of processor modes and that specifies a load multiple instruction that instructs the microprocessor to load data from memory into one or more of the architectural registers specified by the load multiple instruction, the microprocessor comprising: direct storage, that holds data associated with a first portion of the architectural registers and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; indirect storage, that holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit; wherein which of the architectural registers are in the first and second portions varies dynamically based upon the current processor mode of the plurality of processor modes; and wherein for each of the architectural registers specified by the load multiple instruction: if the architectural register is currently in the first portion, the microprocessor loads data from memory into the direct storage; and if the architectural register is currently in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.