1. A method for performing functional verification of a first netlist ( 50 ) of logic circuits ( 10 ) with the steps of: creating a second netlist of logic circuits ( 15 ) equivalent to a subset ( 13 ) of said first netlist; creating a third netlist of logic circuits by replacing ( 51 ) said subset of said first netlist by said second netlist; performing functional formal verification ( 52 ) of said third netlist and identifying errors from at least one produced counterexample ( 53 ); determining ( 54 ) input signal values ( 65 ) for said second netlist from said counterexample of said third netlist; generating ( 55 ) a test case ( 56 ) including said input signal values; and using said test case to functionally verify said first netlist.