1. In a digital computer system having a central processing unit (CPU), at least one memory device that includes several contiguous memory locations individually definable by discrete addresses, and at least one bus forming at least part of a path for the parallel transmission of information between the CPU and memory device, a security device for preventing unauthorized access to preselected memory locations within the memory device, comprising: logic device means external to said CPU and said memory device for recognizing a group of signals present on said bus associated with accessing at least one memory location which has been predefined as a memory location which will not intentionally be accessed during the execution of authorized programs by the CPU, and generating in response thereto a first signal; latch means for generating and maintaining a second signal whenever the first signal has been received from said logic device means; and switching device means, connected to the memory device, for preventing further access to at least the preselected memory locations within the memory device when the second signal is received from said latch means.