1. A computer implemented method for testing a plurality of electronic devices under test (DUTs), the method comprising: generating one or more of a design test pattern, command or instruction with an electronic design automation related (EDA) tool in a native format thereof; sending the generated design test pattern, command or instruction to an automated test equipment related (ATE) apparatus over a communication pipeline wherein the ATE apparatus is operable for the testing the plurality of DUTs; upon receipt, converting the sent design test pattern, command or instruction to an instance of the test pattern, command or instruction in a format that is directly executable by the ATE apparatus; inputting one or more of test signals to each of the plurality of electronic DUTs based on the executable test pattern; receiving from each of the plurality of electronic DUTs test results based on the input test signals; and returning one or more of the received test results to the EDA tool and a report of an action of the ATE apparatus responsive to the sent command or instruction.