1. An apparatus, for accessing extended registers within a microprocessor, the apparatus comprising: translation logic, for translating an extended instruction into corresponding micro instructions for execution by the microprocessor, wherein said extended instruction comprises: an extended prefix, for specifying register address extensions, said register address extensions indicating the extended registers, wherein the extended registers cannot be specified by an existing instruction set; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified opcode within said existing instruction set; and extended register logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for accessing the extended registers.