1. Pipelined data processing apparatus for obeying a sequence of instructions, comprising: (a) a memory, (b) clock means for producing first clock signal defining a clock beat and at least one further clock signal which divides each clock beat into a write sub-beat and at least one read sub-beat, (c) means responsive to the first clock signal for advancing each instruction through a read phase, an execute phase, and a write phase during successive clock beats, (d) execution means connected to the memory and operative during each clock beat to perform a function specified by the instruction currently in its execute phase, thereby producing a result for the instruction, (e) write means operative during the write sub-beat of each clock beat to write to the memory the result of the instruction currently in its write phase, (f) read means operative during the read sub-beat of each clock beat to read an operand from the memory for the instruction currently in its read phase, (g) detection means connected to said write means and to said read means for detecting a read/write clash in which the instruction currently in its read phase requires to read from the memory an operand which is about to be written by the instruction currently in its execute phase, and (h) means connected to said execution means and to said detection means and operative upon detection of said read/write clash, for making the result of the instruction currently in its execute phase directly available as an operand for the instruction currently in its read phase.