1. A semiconductor design support device for designing a semiconductor integrated circuit, the device comprising: a behavioral description configured to describe an algorithm of processing performed by hardware in a motion level; an RTL description generated by reading the behavioral description, the RTL description configured to recognize a concept including register and clock synchronism particular to the hardware; a latency analyzer configured to analyze a result of a logic simulation performed on the RTL description to calculate a latency in each block representing an operation in a predetermined unit in the behavioral description; a correspondence table in which each block in the behavioral description corresponds to a state in the RTL description; and a correspondence table generator configured to generate the correspondence table.