1. A circuit comprising: M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format; a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products; and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.