1. A data processor comprising: an instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing one of a plurality of execution steps associated with a pending instruction being executed by said instruction execution pipeline; a data cache capable of storing data values used by said pending instruction; a plurality of registers capable of receiving said data values from said data cache; a load store unit capable of transferring a first one of said data values from said data cache to a target one of said plurality of registers during execution of a load operation; a shifter circuit associated with said load store unit capable of one of a) shifting, b) sign extending, and c) zero extending said first data value prior to loading said first data value into said target register; and bypass circuitry associated with said load store unit capable of transferring said first data value from said data cache directly to said target register without processing said first data value in said shifter circuit.