1. A NAND gate comprising: a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode; a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node; a first resistor having a first terminal coupled to the control electrode of the first NPN transistor and a second terminal coupled to the second current electrode of the first NPN transistor; a second P channel transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving a second input signal, and a second current electrode; a second NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node; a second resistor having a first terminal coupled to the control electrode of the second NPN transistor and a second terminal coupled to the second current electrode of the second NPN transistor; a third P channel transistor having a first current coupled to the first power supply terminal, a control electrode for receiving a third input signal, and a second current electrode; a third NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the third P channel transistor, and a second current electrode coupled to the output node; a third resistor having a first terminal coupled to the control electrode of the third NPN transistor and a second terminal coupled to the second current electrode of the third NPN transistor; and pull-down means, coupled between the output node and a second power supply terminal, for providing a current path between the output node and the second power supply terminal only if the first, second, and third input signals are a logic high and blocking said current path if one or a more of the first, second, and third input signals are a logic low; said pull-down means comprising first, second and third N channel transistors connected in series between the output node and the second power supply terminal, said first N channel transistor having a control electrode for receiving the first input signal, said second N channel transistor having a control electrode for receiving the second input signal, and said third N channel resistor having a control electrode for receiving the third input signal.