1. An apparatus implementing an Advanced Encryption Standard (AES) S-box encryption process on a 128-bit block including a first 16 byte values each byte having a polynomial representation in GF(256), the apparatus comprising: a polynomial-powers generating circuit to compute for each of the first 16 byte values, respectively, a plurality of second byte values having polynomial representations in GF(256) corresponding to a plurality of powers of the polynomial representation of their respective byte value of the first 16 byte values; a multiplier circuit to multiply together in GF(256) the plurality of second byte values for each of the first 16 byte values, respectively, to produce a third 16 byte values each having a polynomial representation in GF(256) corresponding to the multiplicative inverse of their respective byte value of the first 16 byte values; and an affine transform circuit to apply an affine transformation to the multiplicative inverses of the 16 byte values to generate, respectively, a fourth 16 byte values each having a polynomial representation in GF(256) wherein applying the affine transformation to generate a fourth 16 byte values having polynomial representation in GF(256) is performed by a multiplication of each corresponding multiplicative inverse polynomial representation with an 8-bit by 8-bit product matrix and a subsequent XOR with a constant byte value.