1. A system comprising: a processor including a plurality of processing cores, a cache memory, and an integrated voltage regulator to be a dedicated power plane to enable the cache memory to store a context of the processor when the processor is in a connected standby sleep state; a platform control hub coupled to the processor; an external voltage regulator; and an embedded controller; wherein the processor is to enter the connected standby sleep state upon: powering of the cache memory with the dedicated power plane, the dedicated power plane separate from a sustain power plane that powers the cache memory in a deep sleep state; powering down of remaining components powered by the sustain power plane and powering down of the sustain power plane; redirection of wakeup sources for handling processor wakeup and context restore to the platform control hub; and transference of at least one architectural function of the processor to the platform control hub.