1. A method of preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements in Hardware Design Language source code containing multiple wait statements into equivalent register transfer code target file with the target file being in lower to upper correct dependency order, comprising the steps of: a) creating a process statement that is sensitive to the current state and creating a case statement whose selection expression is the current state; b) initialize a wait state; c) locating a wait statement corresponding in position to the initialized wait state; d) creating an entry in a case statement in the code that corresponds to a behavioral model when a register transfer level wait state is in the initialized wait state; and e) incrementing the wait state number.