1. A Digital Signal Processing (DSP) block comprising: a first input register block coupled to a multiplier, wherein the first input register block receives either a first data input or an input from a second input register block; a third input register block coupled to the multiplier, wherein the input third register block receives either a second data input or an input from a fourth input register block; and a multiplexer of a plurality of multiplexers coupled to the multiplier, the plurality of multiplexers controlled by an opcode, wherein the multiplexer of the plurality of multiplexers is coupled to the first input register block and the third input register block.