1. A cache memory, comprising: a data array; a store queue configured to buffer synchronization operations and store operations; a pollution vector control configured to create respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory; and a store queue controller configured to set dependencies in a dependency data structure of the store queue based on the pollution vectors to reduce unnecessary ordering effects and dispatch store operations from the store queue in accordance with the dependencies indicated by the dependency data structure; wherein the cache memory is a lower level cache memory and the cache memory is further configured to: compare a load target address of a load operation that hits in an upper level cache memory that is associated with the lower level cache memory to active store target addresses in the lower level cache memory; and in response to a match of the load target address with one or more of the active store target addresses in the lower level cache memory, set an associated one of the respective pollution vectors to indicate that a thread that issued the load operation is polluted by a given store operation active in the lower level cache memory.