1. An integrated circuit device having a semiconductor substrate, comprising: a memory cell array comprising a plurality of volatile memory cells; and a metal oxide semiconductor field effect transistor (MOSFET) configured as a non-volatile electrically erasable programmable read only memory (EEPROM) device having a floating gate and a control gate, and adapted to store status information associated with the memory cell array, wherein the MOSFET has a single polysilicon film for the floating gate, and the control gate is disposed within a well in the semiconductor substrate.