1. An integrated circuit with an active-level configurable pin, comprising: a bonding pad for receiving an input signal; latching means coupled to said bonding pad, for latching a logic state of said input signal in response to an inactivation of a reset signal, and for providing a first signal indicative of said latched logic state; input pin configuration means coupled to said latching means, for providing an internal input signal as a selected one of said input signal or a complement of said input signal selected in response to said first signal; and an internal circuit for receiving said selected one of said input signal or said complement of said input signal.