1. A vector processing apparatus, comprising: an instruction memory storing a multiple instruction group including one or more instructions; an instruction fetch unit reading the multiple instruction group from the instruction memory; and a plurality of instruction processing units, each instruction processing unit including a multiple instruction selecting unit and an arithmetic unit, the multiple instruction selecting unit receiving the multiple instruction group through the instruction fetch unit, and selecting a single instruction from the multiple instruction group according to a comparison using a previous arithmetic result of the arithmetic unit and predicate information contained in each of the one or more instructions, and the arithmetic unit performing an arithmetic operation according to the selected single instruction.