1. A non-transitory computer-readable medium having computer-readable code embodied therein, the computer-readable code to cause a computer system, in response to execution of the computer-readable code, to: receive or retrieve a sequence of instructions targeted for execution on an execution processor, wherein the execution processor includes a plurality of alias registers and circuitry to check entries in an alias register for memory aliasing; after the sequence of instructions is received or retrieved, perform one or more optimizations on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions, the one or more optimizations including a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions; and after the one or more optimizations, construct a graph, with the optimized sequence of instructions represented as nodes of the graph and edges of the graph; and insert one or more move instructions in the optimized sequence of instructions to move one or more entries among the plurality of alias registers during execution, to expedite alias checking at execution time, wherein the edges of the graph include checking edges and anti-checking edges; wherein a checking edge connects two nodes representing two memory instructions that require execution time memory aliasing checking, and an anti-checking edge connects two nodes representing two instructions that do not require execution time memory aliasing checking.