1. A method for determining an optimal voltage pulse for programming a NOR-type flash memory cell comprising a floating gate, a control gate and a drain, said optimal voltage pulse, to be applied to the control gate of the memory cell, being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, the method comprising the following steps: providing a set of parameters including a programming window target value and a drain current target value of the memory cell; dynamically measuring the drain current of the memory cell when a rectangular-shaped voltage pulse is applied to the control gate; providing a transistor equivalent to the memory cell and comprising a gate electrode and a drain electrode, such that a drain current of the transistor is equal to a drain current of the memory cell when the gate electrode of the transistor is brought to a potential equal to a potential of the floating gate of the memory cell; dynamically measuring the drain current of the transistor as a function of the potential of the gate electrode of the transistor; determining the potential of the floating gate during the rectangular-shaped voltage pulse, from the measurement of the drain current of the memory cell and the measurement of the drain current of the transistor; determining, respectively from the drain current target value, the potential of the floating gate during the rectangular-shaped voltage pulse and from the programming window target value, the initial voltage level, a slope of the voltage ramp and the programming duration, such that the drain current of the memory cell during the optimal voltage pulse is substantially equal to the drain current target value; and wherein the drain (D) is brought, during the measurement of the drain current of the memory cell, to a constant potential identical to that of the drain electrode during the measurement of the drain current of the transistor.