1. A method of configuring a plurality of memory elements having selectable dimensions, said method comprising: selecting a width of a data word to be output by a circuit having said plurality of memory elements; selecting a width for memory locations of said plurality of memory elements, said width for memory locations being less than said width of a data word; configuring said plurality of memory elements to have said selected width; and concatenating the outputs of each memory element of said plurality of memory elements to generate a concatenated output having said width of said data word.