1. A digital data processing circuit having therein a precharge node and having a plurality of inputs comprising: circuit means coupled to said input responsive to a signal applied at said input; look-ahead precharge circuit means coupled between plurality of said inputs to said digital data circuit and said precharge node and also coupled to said circuit means for detecting a change in a logic level of any of said inputs and precharging said precharge node in response to said change in said logic level; and wherein said digital data processing circuit is a read only memory including address buffer circuits, row and column decode circuits, and a digital storage array and wherein said precharge node is a sense bus in said data storage array.