1. A method for programming a cluster-based field programmable gate array (FPGA) device comprising: providing a netlist and cluster size information; translating the netlist into a hypergraph; recursively partitioning the hypergraph into multiple partitions; translating the partitions into clusters; placing the clusters on the FPGA device; routing interconnects using a pre-fabricated routing resource on the FPGA device; generating a programming bitstream in response to the placing and routing; and providing the programming bitstream to the FPGA device to realize the user design.