1. A memory device, comprising: a semiconductor stack comprising multiple layers arranged in sequence substantially along a first dimension; and a memory cell formed within a subset of the semiconductor stack, and comprising a patterned top electrode, a resistive switching layer and a patterned bottom electrode formed of respective ones of the multiple layers of the semiconductor stack and arranged in sequence along a direction, wherein the direction forms a forty five degree or larger angle to the first dimension at least near the subset of the semiconductor stack.