1. A digital system with a processing engine for executing instructions in parallel, the processing engine comprising: an instruction buffer for holding at least two instructions with a first instruction in a first position and a second instruction in a second position; a first decoder for decoding the first instruction and generating first control signals; a second decoder for decoding the second instruction and generating second control signals; and arbitration logic for arbitrating between the first and second control signals for controlling parallel execution of the instructions in accordance with a set of parallelism rules.