1. An integrated circuit device comprising: a bit line having a plurality of memory cells coupled thereto wherein each memory cell includes an electrically floating body transistor comprising: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region; and wherein each memory cell includes a plurality of data states including a first data state which corresponds to a first charge in the body region of the transistor and a second data state which corresponds to a second charge in the body region of the transistor; data sense circuitry, coupled to the bit line, the data sense circuitry including: a sense amplifier including at least one input node having a capacitance, wherein the sense amplifier includes at least one transistor coupled to the bit line to receive a signal on the at least one input node wherein the signal is representative of a data state of a selected memory cell, wherein the selected memory cell is one of the plurality of memory cells which are coupled to the bit line; and circuitry, coupled to the bit line, to (a) write the data state of the selected memory cell or (b) write (i) the data state back into the selected memory cell or (ii) a different data state into the selected memory cell; and wherein, in operation, the sense amplifier determines the data state of the selected memory cell based on the voltage developed on the at least one input node.