1. A method for determining an effect of noise on a digital integrated circuit having at least one logic gate, comprising: performing a timing analysis on the at least one logic gate; performing a noise analysis on the at least one logic gate; dynamically synthesizing a waveform propagation model as a function of the timing analysis, wherein the waveform propagation model is representative of the effect of noise on the timing analysis of the at least one logic gate; applying an arbitrary voltage waveform derived from the noise analysis to the dynamically synthesized waveform propagation model; and determining an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.