1. An apparatus, comprising: an address generator operative to receive a current state vector and a current input value, wherein the address generator is operative to generate a memory address corresponding to a transition rule in response to the current state vector and the current input value; a transition rule memory comprising a plurality of memory addresses, wherein the memory address is a location in the transition rule memory; wherein the transition rule is a transition rule vector comprising a short state tag field; and wherein the short state tag field comprises fewer bits than the current state vector.