1. A system comprising: a single instruction, multiple data (SIMD) processor, the SIMD processor comprising an instruction memory for storing a set of instructions and a plurality of processing elements configured to concurrently execute an instruction from the set of instructions on a corresponding plurality of pixels from a row in at least one prediction error and a corresponding plurality of pixels from a row in at least one block of prediction pixels; and a data access circuitry for providing the at least one prediction error and the at least one block of prediction pixels; and a circuit for determining whether two or more prediction errors and two or more prediction pixels can be concurrently processed by the SIMD processor.