1. An apparatus for offloading execution of a function from a CPU to an accelerator engine, comprising: a CPU that determines a function to be offloaded, and locates a data related to the function, wherein the data is stored on a secondary storage device; and an accelerator engine prepared by a controller using at least partial reconfiguration coupled to the CPU, wherein the accelerator engine is programmed to receive the data related to the function from the secondary storage device through a direct memory access (DMA) engine, execute the function using the data related to the function received by the accelerator engine, construct output data via computing the data related to the function during the executing the function, and move the output data through the DMA engine from the accelerator engine to the CPU, wherein the CPU initiates a programmed input/output (I/O) operation to move the output data and the controller communicates data formats that are to be used for the function execution to the accelerator engine.