1. A method for using a system-on-chip (SoC) memory manager to optimize off-chip memory modules, comprising: receiving a request for a first data block at a memory controller, subsequent to shutting a first memory module down; determining that the first data block is stored in the first memory module; translating a first data block address in the first memory module to a second data block address in a second memory module via a memory map; if the first data block is present in a cache, supplying the first data block on a SoC data bus from the cache; and loading the cache with a plurality of data blocks from a corresponding plurality of addresses in the second memory module, associated with the first data block address, wherein the loading the cache further comprises setting a limit value equal to n and a counter value equal to 0; determining if a next address in the cache; if so, incrementing the counter and determining if the next address is in the cache until the counter is equal to n.