1. A method for tracking uncertain signals in a simulation of a chip design, comprising: generating a directed graph which contains sequential logic devices and input/output (IO) devices from a netlist of the chip design, wherein the directed graph illustrates a signal association among the sequential logic devices and IO devices, the sequential logic device being devices wherein the output of the devices are dependent on the current input to the devices and the previous state of the devices; obtaining signals related to the sequential logic devices and IO devices from simulation results, wherein the signals contain a plurality of uncertain signals; and back tracing, using a processor, at least a part of the plurality of uncertain signals along the directed graph to determine the device which firstly generates an uncertain signal.