1. In an integrated circuit, an electrically programmable interconnect architecture, comprising: a plurality of logic modules placed in an array on a substrate, the modules having at least one RAM cell and having connection nodes; a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wire segments and wherein at least one of said wire segments is connected to at least one of said connection nodes; a plurality of reconfigurable elements, each of said reconfigurable elements having two main terminals, said main terminals connected between selected ones of said wiring segments comprising one of said channels, each of said reconfigurable elements further including a control terminal; series-pass transistors connected between selected adjacent ones of said segments, each of said series-pass transistors having a control element, and selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.