1. A flag logic circuit for use in a multi-queue memory device having a plurality of queues, the flag logic circuit comprising: a first stage storage element having a capacity to store a flag value for each of the queues in the multi-queue memory device; a flag status bus having a capacity to provide N flag values; a status bus control circuit configured to receive a signal that identifies a first number M of one or more queues used in the multi-queue memory device, and in response, generate a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1; and a selector circuit coupled to receive the flag values stored in the first stage storage element and the repeating pattern of X control values, wherein the selector circuit is configured to route X sets of N flag values from the first stage storage element to the flag status bus in response to the repeating pattern of X control values.