1. A processor system comprising: a processor including: a set of internal registers comprising at least one program counter; and an instruction decoder for sending a control signal responsive to execution of a predetermined instruction; and a communication interface coupled between the processor and an external device, the communication interface receiving data from the external device, and having at least one internal data path to at least one of the internal registers for inputting data into the at least one internal register responsive to receiving the control signal from the instruction decoder, wherein the internal data path is for directly inputting into the at least one program counter an address to a service routine by bypassing a branch prediction circuit.