1. A signed multiplier circuit, comprising: a two-dimensional array of instances of a logic block, adjacent instances of the logic block being coupled one to another; a plurality of pairs of configuration memory cells, each pair of configuration memory cells coupled to one of the instances of the logic block, respectively, wherein: each instance of the logic block is programmable to implement a first multiply function of first and second inputs, wherein the first and second inputs are both signed; each instance of the logic block is programmable to implement a second multiply function of the first and second inputs, wherein the first and second inputs are both unsigned; each instance of the logic block is programmable to implement a third multiply function of the first and second inputs, wherein the first input is signed and the second input is unsigned; each instance of the logic block is programmable to implement a fourth multiply function of the first and second inputs, wherein the first input is unsigned and the second input is signed; and each instance of the logic block is responsive to the respective pair of configuration memory cells, and in each pair a first configuration memory cell indicates whether the first input to the instance of the logic block is signed or unsigned, and a second configuration memory cell indicates whether the second input to the instance of the logic block is signed or unsigned.