1. A graphics processing apparatus comprising: a plurality of arithmetic logic units (ALUs) receive instructions and associated data configured for processing in parallel; pre-processing logic configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs; post-processing logic configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.