1. A memory alignment system for use in a digital data memory storage system having a central processor capable of operating on data words of at least one defined width, a memory having a plurality of locations having defined addresses, the widths of said locations corresponding to the defined widths of said data words, and the addresses further grouped into lines, each line having at least two data locations, and a memory writing means responsive to write instructions from the processor for transmitting data words from said processor to said memory, the writing means being capable of transmitting into said memory of at least two data words together when destined for the same line, the improvement wherein the memory alignment system comprises: A. a write buffer means connected to the processor and the writing means, the buffer means having a plurality of rows, each row having a plurality of locations for receiving and storing data words destined for alignable locations in said memory, in association with their memory addresses, B. comparator means for comparing a first address of a data word previously stored in said buffer means with a second address contained in a write instruction, and C. routing means responsive to said comparator means for routing said data word associated with said write instruction to the same row of said write buffer as said previously stored data word when said first and second addresses are located in the line of memory, thereby enabling the writing means to transfer in a single memory write cycle at least two data words to the same line of memory.