1. A processor, comprising: a hierarchy of memories comprising a first memory structure comprising one or more entries to store an instruction address and one or more instructions starting from the instruction address; one or more registers; and a processing logic, operably coupled to the hierarchy of memories and the one or more registers, to: responsive to writing one or more instruction addresses starting from the instruction address to the one or more registers, pre-fetch, based on the one or more instruction addresses starting from the instruction address, one or more instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories.