1. A memory device comprising: a mode register decoder that receives an address signal and programming operation modes of the memory device; and an antifuse circuit unit comprising at least one antifuse that programs a defective characteristic code according to the operation modes of the memory device to the at least one antifuse and outputs the defective characteristic code to an external source; wherein the antifuse circuit unit stores the defective characteristic code, which is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device.