1. A processor, comprising: a prefetch buffer to store a plurality of macro instructions; a clock circuit to provide an oscillating clock signal for at least a plurality of units in the processor; macro instruction decode logic to determine a class of each macro instruction retrieved from the prefetch buffer; in response to the determination of the class of a first macro instruction of the plurality of macro instructions, a clock management unit to cause the oscillating clock signal to remain in a steady state for at least one clock cycle entering at least one of the plurality of units in the processor that are not utilized to operate on the first macro instruction; and a first instruction decoder unit of the plurality of units to decode the first macro instruction into one or more opcodes.