1. A cache comprising: a cache memory; and a cache control unit coupled to the cache memory; and error correction code (ECC) bits associated with data stored in the cache memory; wherein the control unit is configured to: allocate a cache line storage location in the cache memory for a first write request that misses the cache and updates less than a full cache line; store data from the first write request at the cache line storage location without reading a corresponding cache line from memory; and in response to the first write request, redefine ECC bits associated with the cache line storage location from being ECC bits usable to correct detected errors in the associated data to valid bits that indicate which portions of data stored in the cache line storage location are valid.