1. A memory controller, comprising: a memory bus port to be coupled to a plurality of memory slots that are configured to receive memory banks to form a memory associated with the memory controller; a first interface to transmit and receive packets for the memory, each of the packets comprising a header, the header containing a mutable address and a packet opcode specifying an operation to be performed in accordance with a network protocol; a second interface to be coupled to a plurality of processing engines to provide the plurality of processing engines direct access to the memory; and a controller core configured to: decode a packet received at the first interface; and perform an operation specified in the received packet.