1. An integrated circuit comprising: a plurality of ways of cache, wherein the plurality of ways comprises a quantity that is a multiple of three and not a power of two, and wherein the plurality of ways are organized into a plurality of pairs; a single bit for each of the plurality of pairs, wherein each single bit is to operate as an intermediate level decision node representing the associated pair of ways; a root level decision node comprised of exactly two individual bits to point to one of the single bits to operate as the intermediate level decision node representing an associated pair of ways; and wherein a total number of bits of the decision nodes is N−1, wherein N is a total number of ways in the plurality of ways and the decision nodes to determine which of the plurality of ways of cache to use.