1. A method used in producing an integrated circuit design, said circuit design having cells and interconnects, said circuit having a representation that is hierarchically decomposed into a top-level and a plurality of blocks, at least some of the plurality of said blocks being capable of being further hierarchically decomposed and of having a parent block associated therewith, said method comprising: processing at least one of said blocks such that an abstraction is created that includes physical interconnect information relating to interconnects between components within said at least one block, said physical interconnect information modeling parasitic electrical and physical effects of interconnects upon an estimated behavior of said integrated circuit; and utilizing said abstraction in another development phase performed said parent block.