1. A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a first thread scheduler that outputs a thread selection signal in accordance with a first schedule pattern or a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads; a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads; and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the first thread scheduler selects the first schedule pattern, and when the multi-thread processor is in a second state, the first thread scheduler selects the second schedule pattern, wherein the first thread scheduler comprises: an interrupt control unit that, when a state of the multi-thread processor is changed from the first state to the second state, outputs a control signal according to an input interrupt signal; and a selection unit that selects the first schedule pattern or the second schedule pattern according to the control signal from the interrupt control unit, and wherein the first state comprising when the multi-thread processor performs a normal operation and the second state comprising the multi-thread processor performing an interrupt processing.