1. A system for processing instructions with an instruction processor, comprising compounding decoding means for decoding a series of base instructions of a scalar machine and for generating a series of instructions including compound instructions and single scalar instructions, said compound instructions each comprising a plurality of scaler instructions as member instruction units of such compound instruction and having an instruction format text having appended control bits in the instruction format text enabling execution of the compound instruction format text in said instruction processor, wherein said control bits indicate which scalar instructions are grouped in a given compound instruction; fetch means for fetching said compound instructions; decoding means for decoding fetched compound and single instructions; execution means for executing member instruction units of compound instructions in parallel in response to and in accordance with said control bits and for executing single scalar instructions; and wherein said system provides a compound instruction program to said execution means which preserves intact the scalar execution of said base instructions of a scalar machine.