1. An apparatus, comprising: a processing unit configured to receive a first command from a host to read data from a memory, wherein the memory includes a plurality of planes; and an interface coupled to the memory, wherein the interface is configured to: send a second command to the memory to read data from a first plane of the plurality of planes responsive to the processing unit receiving the first command; and receive data from the first plane of the plurality of planes; wherein the processing unit is further configured to decode an Error Correction Code (ECC) of the data read from the first plane of the plurality of planes; wherein the interface is further configured to send, in parallel to the processing unit decoding the ECC of the data read from the first plane, a third command to the memory to read data from a second plane of the plurality of planes.