1. A processor comprising: a plurality of physical registers, each identified by a physical register identifier (ID) of a plurality of physical register IDs; a plurality of architectural registers, each identified by an architectural register ID of a plurality of architectural register IDs; a register free list comprising a plurality of entries, wherein the register free list is partitioned into a plurality of banks and wherein each entry is configured to store an indication indicating whether a corresponding physical register ID is available to be assigned; and a register rename unit comprising circuitry configured to: assign physical register IDs to architectural register IDs based at least in part on a number of physical register IDs indicated as being available for assignment within each bank of the plurality of banks; receive a returning physical register ID that is currently indicated by the register free list as not available for assignment; and assign the returning physical register ID to a given architectural register ID without updating the register free list to indicate the returning physical register ID is available for assignment, in response to determining at least one bank of the plurality of banks has a number of available physical register identifiers that differs by at least a threshold amount from a number of available physical register identifiers within one or more other banks of the plurality of banks.