1. A non-volatile-memory-transistor based lookup table for an FPGA including: a multiplexer having x address inputs, 2 x data inputs, and an output; a plurality of data-input circuits, each coupled to one of the data inputs of the multiplexer and including: a first n-channel MOS transistor having a drain coupled to a power supply potential, a source coupled to the data input of the multiplexer, and a gate, a second n-channel MOS transistor having a drain coupled to the data input of the multiplexer, a source coupled to ground, and a gate, a first non-volatile memory cell having an output coupled to the gate of the first n-channel MOS transistor; and a second non-volatile memory cell having an output coupled to the gate of the second n-channel MOS transistor; and a sense amplifier is coupled to the output of the multiplexer.