1. A semiconductor storage device, comprising: N word lines, N being an integer of four or greater; M bit lines that intersect with the word lines, M being an integer of two or greater; multiple memory cells placed at positions where the word lines and the bit lines intersect, the memory cell storing binary data; and a read circuit connected to the M bit lines, the read circuit detecting levels of a multi-ary signal, wherein the read circuit detects levels of a quarternary signal on a bit line selected from the M bit lines, and the semiconductor storage device performs an error operation if data based on the detection results for signal levels is determined to be incorrect.