1. A method for issuing instructions in a processor, the method comprising: dispatching a first instruction of a plurality of instructions in an issue queue, the issue queue having a plurality of queue positions configured to store each of the plurality of instructions in a corresponding queue position, the issue queue storing the first instruction in a first queue position, the plurality of instructions including at least a second instruction including a target instruction tag, the first instruction including a target instruction tag and a source instruction tag, the source instruction tag specifying a logical register that stores source operand data; at dispatch of the first instruction, comparing, by an issue unit of the processor, the source instruction tag of the first instruction with each of a plurality of target instruction tags in a table, the table configured to store the target instruction tag associated with the first instruction, wherein the table is further configured to store the plurality of target instruction tags, each target instruction tag in the plurality of target instruction tags being associated with a corresponding one of the plurality of instructions, each stored target instruction tag specifying a logical register that stores a target operand; at dispatch of the first instruction, associating, by the issue unit, the second instruction with a pointer to the first instruction in the first queue position upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with the second instruction, that the first instruction is dependent on the second instruction, and further based on determining that the second instruction is younger than all other instructions in the issue queue upon which the first instruction is dependent; and using, by the issue unit, the pointer to wake up the first instruction upon issue of the second instruction.