1. A processor comprising: a first number of hardware processing elements to execute a second number of software threads; a consolidation module adapted to determine during runtime if consolidation of the second number of software threads to a subset of the first number of hardware processing elements is energy efficient in response to the second number being smaller than the first number, and including; an activity module adapted to determine a current activity metric for the first number of hardware processing elements during runtime; a utilization module adapted to determine if the current activity metric consolidated to the subset of the first number of hardware processing elements would increase power consumption; and a control module adapted to determine that the consolidation is energy efficient in response to determination that the consolidated current activity metric would not increase power consumption, and to determine that the consolidation is not energy efficient in response to determination that the consolidated current activity metric would increase power consumption; and a migration module adapted to migrate the second number of software threads to the subset of the first number of hardware processing elements in response to determination that the consolidation of the second number of software threads to the subset of the first number of hardware processing elements is energy efficient.