1. A method for designing a digital circuit using a hardware description language (HDL), the method comprising the steps of: defining a signal to be of a clock data type, the clock data type distinct from a plurality of other data types provided by the HDL, the plurality of other data types including data types for defining level-sampled signals; and specifying one or more modules with the HDL, each of the one or more modules accepting the signal of the clock data type as a condition for execution to render the module synchronous with the signal.