1. A system for low density parity code decoding, the system comprising: a plurality of variable node (vnode) logic modules for processing different groups of vnode values associated with a codeword, the groups being processed sequentially over multiple clock cycles, the vnode logic modules outputting updated vnode values; a vnode memory for storing the vnode values and updated vnode values; a plurality of check node (cnode) logic modules for sequentially processing groups of cnode values and outputting updated cnode values; a cnode memory for storing the cnode values and updated cnode values; and logic for checking the codeword using the updated vnode values and the updated cnode values, wherein a number of the vnode logic modules is a fraction of a number of vnodes used by the system in low density parity code decoding, the fraction being less than 1/1.