1. A processor system, comprising: a general partition having a central processing unit (CPU), the general partition including a load monitor to receive an instruction; an embedded partition having a second CPU; an inter-partition bridge (IPB) in communication with the general partition and the embedded partition to pass an instruction from the general partition to the embedded partition; a thread scheduler to create a raw thread context (RTC) frame from the instruction and to translate the RTC frame into a bytecode-oriented thread context (BTC) for transmission to the embedded partition via the IPB; a managed runtime environment filter to evaluate the instruction and pass the instruction via the IPB when the embedded partition can process the instruction; and an operating system executing on the general partition to determine whether an acceleration application is enabled on the embedded partition, to invoke the embedded partition to compile the instruction when the acceleration application is enabled on the embedded partition, and to initiate execution of the instruction on the general partition when the acceleration application is not enabled.