1. A computer-implemented method for use with an electronic design, the method comprising: identifying, using one or more processors, a plurality of sibling nets associated with the electronic design; determining if the plurality of sibling nets have a same input slew rate; if the plurality of sibling nets do not have a same input slew rate, determining a delay calculation (DC) for each of the plurality of sibling nets; and if the plurality of sibling nets do have a same input slew rate, sharing a stored DC with the plurality of sibling nets.