1. A data processing apparatus comprising: execution circuitry configured to execute a sequence of program instructions; checkpoint circuitry configured to identify an instance of a predetermined type of instruction in said sequence of program instructions and to store checkpoint information associated with said instance of said predetermined type of instruction, said checkpoint information identifying a state of said data processing apparatus prior to execution of said instance of said predetermined type of instruction, wherein said predetermined type of instruction has an expected long completion latency, and wherein if said execution circuitry does not complete execution of said instance of said predetermined type of instruction due to occurrence of a predetermined event, said data processing apparatus is arranged to reinstate said state of said data processing apparatus with reference to said checkpoint information, such that said execution circuitry is configured to recommence execution of said sequence of program instructions at said instance of said predetermined type of instruction.