1. A system for controlling a processor element (PE) structure comprising: a PE structure comprising two or more PEs in communication with each other to form a floating point unit (FPU)-processing element; a floating point-reconfigurable array (FP-RA) control circuit in communication with the PE structure to control the PE structure to perform FP arithmetic; and a configuration cache in communication with the FP-RA control circuit to store a context word used by the PE structure to perform the FP arithmetic operations, wherein when the FP arithmetic requires a multi-cycle operation, the configuration cache inputs an entry point to the FP-RA control circuit and the FP-RA control circuit generates the context word for each cycle of the multi-cycle operation.