1. A vector processing apparatus comprising: a main storage for storing scalar instructions, vector instructins and data; a scalar processor connected to said main storage for executing the scalar instructins; a vector processor connected to said main storage and said scalar processor for executing the vector instructions; memory means having a plurality of memory locations for indicating status of completion of vector operations; said scalar processor including first requestor and decode means for fetching the scalar instruction from said main storage and decoding the scalar instruction for execution, said scalar instructions each having an order assurance instruction to assure an order of execution of the scalar, and said order assurance instruction having a field for designating a memory locaton of said memory means; said vector processor including second requestor and decoder means for fetching the vector instruction from said main storage and decoding the vector instruction for execution, said vector instructins each having a field for designating a memory location of said memory means; and first and second wait managing means for controlling execution of scalar instructions and vector instructions, respectively, each of said first and second wait managing means causing a respective one of said first and second requestor and decode menas to assume a wait status or an enable status in accordance with a set or reset status of the memory location of said memory means designated by a respective one of said order assurance instruction and said vector instruction, and effecting setting or resetting of the memory location of said memory means designated by said field in response to termination of operation on a respective one of said order assurance instruction and said vector instruction.