1. A circuit arrangement, comprising: a first processing core disposed on an integrated circuit device and including a first execution unit that includes a first non-pipelined execution logic circuit, the first non-pipelined execution logic circuit configured to execute at least one non-pipelined instruction; a second processing core disposed on the integrated circuit device and including a second execution unit that includes a second non-pipelined execution logic circuit, the second non-pipelined execution logic circuit configured to execute the at least one non-pipelined instruction; and a multiplexing logic circuit coupling together the first and second execution units to receive a plurality of non-pipelined instructions issued to each of the first and second execution units and route the plurality of non-pipelined instructions to the first non-pipelined execution logic circuit for execution thereby, wherein the second processing core is configured to selectively issue a first non-pipelined instruction to the first non-pipelined execution logic circuit using the multiplexing logic circuit and to selectively issue a second non-pipelined instruction to the second non-pipelined execution logic circuit.