1. A data processing apparatus, comprising: a memory access pipeline accessing memory; an arithmetic operation pipeline executing arithmetic operations; and an instruction decoder, located in a preceding stage of the memory access pipeline and the arithmetic operation pipeline, issuing an instruction, wherein the memory access pipeline exclusively analyzes and develops a memory access instruction and when the memory access pipeline issues the memory access instruction to the arithmetic operation pipeline, a timing and a priority level between the memory access instruction and the instruction issued from the instruction decoder to the arithmetic operation pipeline are determined.