1. A cache memory comprising: a data array that stores a cached block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, in response to the address stored in the second address array resulting in a cache hit during a period before a second block that has caused the cache miss to be read from a memory and written into the data array, wherein the cache memory is configured to wait for the second block to be read from memory when it is determined that an entry in the second address array corresponding to the first block is not vacant.