1. A parallel processor, comprising: a cache configured to receive data pertaining to an operation; and a parallel execution unit associated with said cache and configured to execute parallel counterparts of said operation such that, when executed in parallel, said parallel counterparts is configured to create in said cache multiple aliases for said data, each of said multiple aliases corresponding to a different copy of said data, wherein each of said parallel counterparts is operable to invalidate only one of said different copies of said data.