1. A memory system, comprising: a location addressable high-dimensional store having data identified by location; a plurality of content addressable stores each having content words, each content word being associated with a reference to data in the location addressable high-dimensional store; a mapping unit that maps the location addressable high-dimensional store to a sparse distributed memory space; search word register for searching a content addressable store level for a desired content word using at least one temporal attribute; sparse memory retrieval unit that uses the desired content word to retrieve data from the sparse distributed memory space via the location addressable high-dimensional store which has been mapped; comparison unit to execute instructions to analyze the data which has been retrieved from the sparse distributed memory space by a hashing logic, wherein the hashing logic executes instructions to convert the data which has been retrieved from the sparse distributed memory space into a first logical address and payload data, wherein the first logical address describes metadata about the payload data; a hardware translation unit, wherein the hardware translation unit executes instructions to translate the first logical address into a first physical address on a storage device; a hardware load/storage unit, wherein the hardware load/storage unit stores the first logical address and the payload data at the first physical address on the storage device; a hardware exclusive OR (XOR) unit, wherein the hardware XOR unit compares two logical address vectors to derive a Hamming distance between the two logical address vectors; a hardware retrieval unit, wherein the hardware retrieval unit retrieves other payload data that is stored at a second physical address whose second logical address is within a predefined Hamming distance from the first logical address, and wherein a Hamming distance between the first logical address and the second logical address is derived by the hardware XOR unit; an address vector converter, wherein the address vector converter is hardware that converts each “zero” bit in an address vector to a “negative one” bit to generate a converted address vector; an address vector summer, wherein the address vector summer is hardware that sums each bit position from two or more address vectors to generate a summation address vector; and a threshold logic, wherein the threshold logic compares the summation address vector to the first logical address, wherein a group of logical addresses whose summation address vector matches the first logical address is determined to address a storage location of a same class of payload data.