1. Apparatus for enabling an instruction to control data flow bypassing hardware within a processor of a programmable processing engine, the apparatus comprising: a pipeline of the processor, the pipeline having a plurality of stages including instruction decode, writeback and execution stages, the execution stage having a plurality of parallel execution units; and an instruction set of the processor, the instruction set defining a register decode value that specifies one of source operand bypassing and result bypassing from a previous instruction executing in pipeline stages of the processor.