1. A system wherein a processor having a general cache memory is connected to an auxiliary cache module for enhancing cache storage of said general cache memory to expand the storage capability of frequently used words from main memory and which words have a main memory address, said processor generating commands for reading data words or instruction code words, said system comprising: (a) said auxiliary cache module including: (a1) steering block means for routing the addresses of a block of four words, to an internal address register means and for transferring said block of four words to a data queue means for storage during such time when said processor is executing processing instructions; (a2) said data queue means for storing said block of four words from main memory, said words including data words and instruction code words: (a3) said internal address register means for holding the said main memory address of each of said block of four words; (a4) means to compare a single word requested address from said processor with the addresses stored in said internal address register means and to generate a hit signal if a match occurs, for enabling a word transfer to said processor; (b) bus interface means connecting to said main memory via a system bus means including: (b1) means for transferring a four-word block of data words or instruction code words to said steering block means; (c) internal maintenance means for receiving control signals to configure the storage capability of said general cache memory and said auxiliary cache module so as to enable said auxiliary cache module to expand the storage capacity of said general cache memory, or to disable said auxiliary cache module from expanding the storage capacity of said general cache memory, and including: (c1) means to enable said data queue means to respond only to Read data word commands only; (c2) means to enable said data queue means to respond only to Read instruction code word commands.