1. A processor, comprising: a physical register file comprising a plurality of physical registers; a decoder to decode first and second load instructions, each naming a destination logical register; and a register allocation table to map each of said destination logical registers to a physical register within said plurality of physical registers, wherein if said first and second load instructions are detected to load from a same memory location into first and second destination logical registers, respectively, then said register allocation table maps said first and second destination logical registers to one of said physical registers.