1. A cache memory system, comprising: multiple upper level caches, wherein each upper level cache comprises multiple cache lines; and a current level cache comprising an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM), wherein the Exclusive Tag RAM is configured to preferentially store an index address of a first cache line that is in each upper level cache and whose status is unique dirty (UD), wherein the Inclusive Tag RAM is configured to store an index address of a second cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD), and wherein data of the second cache line is backed up and stored in the current level cache.