1. A method for performing an analysis of at least one logic stage in a netlist, said logic stage having at least one driver, the method comprising: a) generating at least one look-up table for an output transient current, based on values of input and output voltages, using data available from a cell library; b) synthesizing analytically at least one current source model including a DC component and a plurality of parasitic capacitances, using said look-up table; c) simulating said logic stage using said current source model to model said driver; and d) obtaining characteristics of said simulated logic stage.