1. A computer-implemented method for performing multiply-add operations, the method comprising: receiving a plurality of input operands; detecting that at least one input operand has an elementary value; gating off one or more portions of a math processing circuit based on the at least one operand having the elementary value; after gating off one or more portions of the math processing circuit, performing one or more abbreviated math operations via the math processing circuit to generate a result; and if the result does not have a zero value or an effective value of zero, then forwarding the result to a final output register; or if the result has a zero value or an effective value of zero, then enabling an all-zero bit associated with the final output register to be set.