1. A microprocessor employing speculative execution comprising: a shared memory; logic to execute a software implemented lockout mechanism for preventing, when invoked, access to designated lines of the shared memory during execution of a pending transaction; a transaction buffer for storing addresses associated with lines of data in the shared memory, the buffer tracking accesses to the shared memory during execution of the pending transaction; and logic for invoking the software implemented lockout mechanism upon detection of a predetermined number of executions of the transaction.