1. An apparatus comprising: a translation lookaside buffer (TLB) in a processor; one or more control words associated with the TLB; and a hardware-managed stack to hold one or more values for at least one of the control words; the TLB having a plurality of TLB entries, each TLB entry being associated with a virtual machine extension (VMX) tag word; wherein each VMX tag word includes one or more bits to indicate if the associated TLB entry is to be invalidated, according to a processor mode, when an invalidation operation is performed; the processor mode being one of execution in a virtual machine (VM) and execution not in a virtual machine; the invalidation operation belonging to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries; wherein invalidation of a TLB entry by an invalidation operation is further conditioned upon a value of one or more of the control words; wherein the one or more control words associated with the TLB are located in a Virtual Machine Control Structure (VMCS) in memory; wherein the control words associated with the TLB include a TLBVMX word and a mask word; and the stack is to hold values for the mask word.