1. A processor system, comprising: a plurality of arithmetic units capable of performing arithmetic processings in parallel; a storage which stores data that said plurality of arithmetic units use for arithmetic processings; a plurality of DMA controllers which perform data transfer between said plurality of arithmetic units, and between said plurality of arithmetic units and said storage in parallel with processings of a host processor; and a DMA control circuit which controls start-up of said plurality of arithmetic units and said plurality of DMA controllers in parallel with processings of said host processor.