1. A processor, comprising: a hardware instruction processing pipeline configured to decode and execute instructions along a control flow path of a block of instructions; a signature generator configured to generate a signature of instructions entering or within the hardware instruction processing pipeline; a communication port configured to receive encrypted information representing at least one valid signature; a memory configured to securely receive and store a secret key adapted to decrypt the at least one valid signature; and a hardware commit defer unit configured to allow reversible partial execution of the block of instructions while preventing irreversible changes to a program state until at least the generated signature is validated against the at least one valid signature.