1. An on-chip information processing system comprising: a first input port configured to receive packets of a first packet-type at a first data rate that each include an address of a first address-type; a packet dicer module configured to dice the received packets of the first packet-type into one or more packets of a second packet-type that each include an address of a second address-type in a packet header; one or more second input ports configured to receive packets of the second packet-type at a second data rate; one or more second output ports configured to transmit packets of the second packet-type off the on-chip system at the second data rate, wherein the first data rate is faster than the second data rate; and a router module configured to receive packets of the second packet-type from a set of packet sources and transmit packets of the second packet-type to a set of packet destinations, wherein the set of packet sources includes the packet dicer module and the one or more second input ports, wherein the set of packet destinations includes the one or more output ports.