1. A processor having one or more processing cores, each of said one or more processing cores comprising: a front end unit to fetch respective instructions of threads and decode said instructions into respective decoded instructions and input operand and resultant addresses of said instructions; and a plurality of processing units, each of said processing units to be assigned a plurality of said threads, each processing unit coupled to said front end unit and having a respective buffer to receive and store decoded instructions of its assigned plurality of said threads, each of said plurality of processing units comprising: i) a plurality of functional units comprising at least one integer functional unit and at least one floating point functional unit, said plurality of functional units to simultaneously execute its respective processing unit's received, decoded instructions for two or more of its assigned plurality of said threads, ii) registers coupled to said plurality of functional units to store operands and resultants of said received, decoded instructions of its assigned plurality of said threads, iii) data fetch circuitry to fetch input data operands for said plurality of functional units' execution of said received, decoded instructions of its assigned plurality of said threads, and iv) register allocation circuitry to allocate a respective register partition of the registers for each assigned thread of its assigned plurality of said threads.