1. A method performed in a circuit synthesis process, comprising the steps performed by a data processing system of: scanning at least one node of a hierarchical description of a finite state machine stored in a memory of the data processing system; assigning, for each node of the hierarchical description scanned, a metric determined from a reachability function of the finite state machine; and selecting, according to the metric, certain nodes of the hierarchical description as defining a partition of the finite state machine for optimization.