1. An apparatus, comprising: a memory device, comprising: an array of memory cells; sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to: store debugging code in the array of memory cells; execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is stored within the instructions to perform the logical operations.