1. A method comprising: determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized, the determining comprising, defining variables for the logic gate to be resized, that is within the electronic circuit; defining nets influenced by the logic gate to be resized; determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized; formulating objective function to be solved by the electronic circuit; solving the objective function using a linear programming solver based on the defined variables and the determined constraints; and outputting solving of the objective function obtained by linear programming solver for further processing; and selecting gate configuration from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.