1. Interconnect circuitry for connecting a plurality of data source circuits and a plurality of data destination circuits, said interconnect circuitry comprising: a plurality of input paths each configured to connect to a respective one of said plurality of data sources; a plurality of output paths each configured to connect to a respective one of said plurality of data destinations and selectively to connect to one of said plurality of input paths; and an arbitration circuit associated with one of said plurality of output paths and configured to arbitrate between overlapping connection requests to said one of said plurality of output paths received from said plurality of input paths; wherein said arbitration circuit stores a matrix of priority bits having a plurality of rows of priority bits and a plurality of columns of priority bits, each intersecting pair of a given row of said plurality of rows of priority bits and a given column of said plurality of columns of priority bits representing priority information for a given input path as: (i) which of said plurality of input paths have a lower priority than said given input path; and (ii) which of said plurality of input paths have a higher priority than said given input path; and said arbitration circuit is configured to perform a priority update upon said matrix by performing one or more update operations each acting upon one of: (i) a selected row of said plurality of rows of priority bits; and (ii) a selected column of said plurality of columns of priority bits.