1. Apparatus for processing data, said apparatus comprising: a physical set of registers; register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; prediction circuitry responsive to at least one instruction of said instruction set to be subject to mapping by said register renaming circuitry to generate a prediction for said instruction as one of: (i) an executed prediction being a prediction that said instruction will be executed; (ii) a not-executed prediction being a prediction that said instruction will not be executed; renaming control circuitry responsive to a not-executed prediction for an instruction to suppress said register renaming circuitry performing a mapping for said instruction; prediction resolving circuitry responsive to an execution outcome for said instruction to determine if said prediction is correct or is incorrect; and recovery circuitry responsive to said not-executed prediction for said instruction being incorrect to control said register renaming circuitry to perform said mapping for said instruction and to reverse any incorrect changes of architectural state consequent upon said not-executed prediction for said instruction being incorrect.