1. A clockless return to state domino logic gate, comprising: a plurality of nodes each configured to switch between a first state and a second state, including a plurality of input nodes, a preset node, an output node, an enable node, and first and second reset nodes, wherein each of said plurality of input nodes comprises a return to state node which returns to said second state after being asserted to said first state according to return to state operation; a domino circuit having a preset state and a latch state, wherein said domino circuit asserts said preset node and said enable node to said first state and asserts said output node and said first reset node to said second state when said domino circuit is in said preset state, wherein said domino circuit switches to said latch state when said preset node is pulled to said second state in which said domino circuit pulls said output node to said first state and pulls said enable node to said second state, and wherein said domino circuit resets back to said preset state when said first reset node is pulled to said first state; an evaluation circuit which pulls said preset node to said second state when said plurality of input nodes are in any one of at least one evaluation state, and which otherwise releases said preset node; an enable circuit which pulls said second reset node to said first state when said enable node is in said second state, and which otherwise releases said second reset node; and a reset circuit which couples said first reset node to said second reset node when said plurality of input nodes are not in any one of said at least one evaluation state, and which otherwise isolates said first and second reset nodes.