1. A digital signal processing system comprising: at least one C-programmable processor configured to execute an instruction set that includes at least one of multiply instructions and multiply-accumulate instructions that generate a result in carry-save format or redundant binary format, wherein the instruction set is executed at a single instruction, multiple data (SIMD) level, wherein the at least one C-programmable processor further includes a final adder in communication with a carry and sum pipeline, the at least one C-programmable processor further configured to disable the final adder to conserve power.