1. A processor comprising: a processor pipeline to output branch instruction addresses; a branch target buffer responsive to the branch instruction addresses, wherein the branch target buffer comprises branch target buffer records to map branch instruction addresses to branch target addresses associated with an entry location of a first code region, wherein the branch target buffer records comprise confidence counters to track a number of times branches associated with the branch target addresses are taken; and a presbyopic target buffer responsive to the branch target buffer, wherein the presbyopic target buffer comprises presbyopic target buffer records to map the entry location of the first code region to an entry location of a second code region; a cache memory to retrieve the instructions at the branch target addresses and the instructions at the subsequent branch target addresses; a fetch buffer to receive the instructions at the branch target addresses; a prefetch stream buffer to receive the instructions at the subsequent branch target addresses.