1. A single chip digital signal processor (DSP), comprising: a multiplicity of memory mapped resources, said memory mapped resources including: memory locations in a data memory for storing DSP data, memory locations in a program memory for storing DSP instructions, and a plurality of on-chip peripheral interfaces for interfacing the DSP with peripheral devices external to said DSP; a DSP core coupled to said data memory and program memory for executing said stored DSP instructions; a direct memory access (DMA) controller, said DMA controller including a host processor interface for coupling the DSP to a host processor; said DMA controller coupled to said data memory, program memory, DSP core and on-chip peripheral interfaces for performing local data transfers between specified ones of said memory mapped resources and for performing host data transfers between said host processor and said memory mapped resources; and a plurality of data and address bus pairs coupled to said data memory, program memory, DSP core and DMA controller, a first of said data and address bus pairs being dedicated to data transfers controlled by said DMA controller for transferring data between the host processor, said memory mapped resources and said peripheral devices, and a second of said data and address bus pairs dedicated to data transfers controlled by said DSP core for transferring data to and from said DSP core; said DMA controller including a first set of registers for local data transfers between said memory mapped resources and a second set of registers in said host processor interface for host data transfers; said first set of registers including a data transfer register, an address source register and an address destination register; said second set of registers including a host input register for receiving data from said host processor, a host output register for holding data to be sent to said host processor, a host command register for storing commands received from said host processor, a host pointer register for receiving an address from said host processor wherein said received address specifies one of said memory mapped resources; said host processor interface including a host address bus and host data bus interface for enabling said host processor to directly access said second set of registers at predefined host address bus addresses; and said DMA controller including a controller for executing said command stored in said host command register, wherein said command stored in said host command register is selected from a predefined set of host commands that include commands for reading and writing any specified one of said memory mapped resources, commands for initiating burst data transfers between said host processor and a set of said memory mapped resources at a sequence of addresses, and commands for initiating cycle stealing data transfers between said host processor and a set of said memory mapped resources at a sequence of addresses wherein each cycle stealing data transfer is interleaved with any local data transfer that said DMA controller is performing.