1. A method for masking co-processor power usage on a field-programmable gate array (FPGA), the method comprising: determining a power usage of a co-processor to be loaded on the FPGA, wherein the co-processor is a hardware accelerator for a virtual machine; generating at least one moat brick circuit based on the determined power usage; loading the co-processor on the FPGA; loading the at least one moat brick circuit on the FPGA such that the at least one moat brick circuit is physically adjacent to the co-processor and at least partially masks the power usage of the co-processor; forming a composite co-processor including the co-processor and the at least one moat brick circuit; and employing negative feedback to adjust a voltage variation on an FPGA power distribution trace through the at least one moat brick circuit to mask the power usage.