1. A circuit arrangement, comprising: first decode logic associated with a first type of execution unit and configured to receive an instruction and decode the instruction; and second decode logic associated with a second type of execution unit and configured to receive the instruction and decode the instruction, wherein the instruction is concurrently forwarded to the first and second decode logic; wherein the first decode logic has a higher priority than the second decode logic such that if the first and second decode logic respectively decode the instruction as a valid instruction for the first and second types of execution unit, the instruction is executed by a first execution unit of the first type of execution unit rather a second execution unit of the second type of execution unit.