1. A coprocessor interface for establishing instruction, data, and control communication between a central processing unit (CPU) and a coprocessor, the interface providing for coprocessor evaluation of CPU conditional instructions, the interface comprising: an instruction transfer group for providing the CPU conditional instructions to the coprocessor; and a condition code check signal group, coupled to said instruction transfer group, for transferring condition code checkss from the coprocessor to the CPU upon evaluation of the CPU conditional instructions by the coprocessor.