1. A computer-implemented method for assuring a reliability of a chip comprising: retrieving a design netlist with a processor; identifying, via the processor, a logic structure in the design netlist; generating, via the processor, a driver based on the logic structure, wherein generating the driver based on the logic structure comprises: verifying a parity; traversing a netlist back from a plurality of netlist outputs; identifying one or more parity protected structures and one or more gates, wherein protected parity structures comprises a duplication protection; and generating an assertion indicative of a parity validity; applying, via the processor, a simulation and a formal model based on the driver; and testing, via the processor, an output of the simulation and the formal model.