1. A hybrid programmable logic device, comprising: programmable logic elements, at least some of which provide at least one hardware acceleration function; processors interleaved with the programmable logic elements and physically sized such that one physical dimension of each of the processors is equal to a multiple of a same physical dimension of the programmable logic elements; and first intersecting horizontal and vertical connectors that provide data to and from the programmable logic elements, the processors or any combination therein; wherein the vertical pitch of the intersecting horizontal and vertical connectors is a multiple of a vertical pitch of at least one of the programmable logic elements of the processors.