1. A processor, comprising: a branch prediction unit configured to predict directions and target addresses of control transfer instructions in a sequence of instructions to be issued by the processor for execution; a pattern detection unit configured to detect a pattern based on the directions and the target addresses; a replay unit configured to store target addresses of the sequence of instructions, wherein the replay unit is configured to provide, in response to the pattern detection unit detecting the pattern, the stored target addresses to an instruction fetch unit to cause the instruction fetch unit to re-fetch instructions of the sequence of instructions until a misprediction of a control transfer instruction is detected.