1. A hybrid programmable logic device comprising: a processor comprising fixed logic elements, wherein in the processor is disposed in a first layer; a programmable logic element disposed in the first layer; interface circuitry that delivers signal from the programmable logic element to the processor, wherein the interface circuitry is coupled to the programmable logic element using an input circuitry that multiplexes the signal, and wherein the interface circuitry comprises an interface buffer that buffers the signal from the input circuitry; and an interface port coupled to the processor that receives the signal from the interface buffer; and scheduling circuitry comprising a program instruction memory, wherein the scheduling circuitry is configured to: detect a new mode of operation for the processor; halt operation of the processor, in response to the detection of a new mode of operation; receive the signal from the programmable logic elements, wherein the signal comprises a processor instruction; and store the processor instruction in the program instruction memory.