1. An apparatus comprising: a first set of hardware processors of a first instruction set architecture to execute a primary hypervisor, the primary hypervisor to schedule first virtual processor tasks for execution on the first set of hardware processors; a second set of hardware processors of a second instruction set architecture to execute a secondary hypervisor, the secondary hypervisor to schedule second virtual processor tasks for execution on the second set of hardware processors, wherein the second instruction set architecture is different from the first instruction set architecture; and a storage device to store memory address translation mapping data that is accessible to the primary hypervisor and to the secondary hypervisor, wherein the primary hypervisor is configured to program the memory address translation mapping data, and wherein the secondary hypervisor is configured to use the memory address translation mapping data.