1. An apparatus comprising: a plurality of processors, each processor having the capability of executing a plurality of threads; a memory coupled to the plurality of processors; and a thread dispatch mechanism residing in the memory and executed by at least one of the plurality of processors, the thread dispatch mechanism determining which of the plurality of processors are idle, which of the plurality of processors can accept an additional thread, and which of the plurality of processors cannot accept an additional thread, the thread dispatch mechanism dispatching a new thread to an idle processor, if one exists.