1. A method comprising the steps of: (a) measuring a gate leakage current of a plurality of transistors; (b) applying a single stress bias voltage to the plurality of transistors, the stress bias voltage causing a 10% degradation in a drive current of each transistor within a respective stress period t; (c) determining one or more relationships between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively; (d) estimating a negative bias temperature instability (NBTI) lifetime τ of the plurality of transistors based on the measured gate leakage current and the one or more relationships determined in step (c).