1. A processor architecture, comprising: at least one in-order pipeline to receive data prefetch instructions and other instructions; a translation lookaside buffer (TLB) with a number of ports for mapping virtual addresses to physical addresses; a data prefetch queue to receive data prefetch instructions when a respective virtual address associated with a respective data prefetch instruction is not found in the TLB; and a hardware page walker to access page tables in memory when respective data prefetch instructions are not found in the TLB.