1. A computer system, comprising: a control unit, an interconnection system and a processing array for parallel processing having nodes which are interconnected with the distribution system to other processing nodes, wherein: the control unit is programmable and has means for enabling the processing array having an array of processing elements to operate in coordination and which also enables a system control program to operate subsets of the parallel array with each subset dedicated to different applications or different phases of a single application program's processing, wherein the interconnection system provides physical connections between the control unit and the elements of the parallel array of processing elements enabling data and control transfers which are completely independent of the transfer of data between elements of the processing array, the interconnection system distributes functions associated with data transfer between elements of the processing array and distributed functions embedded in processing node software, and the processing array provides non-shared memory and compute services and which are partitioned and the processing array is scalable wherein the control unit and interconnection system provide means, including a broadcast bus path, for broadcasting data and instructions to the parallel array, for accumulating data and status information from the elements of the array, for generating and accepting status information which represents the union of the status derived from the elements of the array, and for controlling how elements of the parallel array interact with the broadcast bus path, means for continuously and unobtrusively accumulating status from individual processing elements to facilitate programmer testing and tuning, means for partitioning the elements of the array into subgroups that are controlled by interleaved commands and data transfers where: subgroup size is specified by the application and/or system operating program and ranges from a single processing unit to the assembly of all processing units, subgroups may be assembled from any particular set of elements of the parallel array irregardless of the particular address information associated with the specific elements, means for generating program specified cross sections of the parallel array for assembly into partitions, means for associating with each command or data, tag information to control which partition should receive the data, means for writing to registers within the processor elements of the parallel array data specifying which partition code will be used to address the individual element, means for writing commands and data to the elements of the parallel array which are passed to the units irrespective of the current status of the partition data within any particular element of the parallel array, means for providing to elements of the parallel array a broadcast facility to all or subsets of the parallel array data specified by the application and/or system operating program, and such operations comprise sequential action of: means for permitting all or a subset of the elements in the parallel array to signal the need for the broadcast, means for accumulating and prioritizing broadcast requests, means for causing the performance of a broadcast operation sequence, means for initializing parallel processor system operations and for providing additional program loads when directed by an application and/or system operating program.