1. A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising: at runtime, receiving instructions for detecting conflicts between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, wherein a given predicate value indicates elements in at least the portion of the vectors that can be processed in parallel, wherein the conflicts between the memory addresses are data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime, and wherein the instructions are inserted in program code prior to runtime; wherein while executing the program code, executing the instructions causes a processor to detect the conflict between the memory addresses and generate the one or more predicate values.