1. A multiprocessor electronic circuit comprising: a plurality of processors; a single cryptographic processing unit comprising a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and further comprising two cryptographic engines, a cipher engine and a hash engine, wherein an assignment of one of the two cryptographic engines to one of the plurality of processors is performed independently from an assignment of the other of the two cryptographic engines; and control logic for connecting the cryptographic processing unit to the plurality of processors and for temporarily assigning one of the two cryptographic engines to one of the plurality of processors.