1. A computer-implemented method, comprising: for each of a plurality of memory access routines having different access timing characteristic, executing, by a redundant array of independent disk (RAID) stack, the memory access routine to load predetermined data from a main memory to a register of a processor of a data processing system; determining, by the RAID stack, an amount of cache misses for the execution of the memory access routine; and selecting, by the RAID stack, one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.