1. A computer system, comprising: an electrical device; a cache memory coupled to said electrical device; and bridge logic containing a processor interface having a prefetch buffer, said bridge logic coupled to said memory; wherein said electrical device issues a read request to said bridge logic to retrieve data from a first cache line, said bridge logic retrieves said first cache line and also retrieves a second cache line before the second cache line is requested by said electrical device and stores said second cache line in said prefetch buffer pending its request by said electrical device.