1. A processor-implemented method, comprising: obtaining, via one or more hardware processors, one or more parameters and one or more corresponding values pertaining to at least one application under test (AUT); generating, via the one or more hardware processors, a first set of arrays based on an analysis being performed on said one or more parameters and said one or more corresponding values, wherein two or more arrays in said first set of arrays comprises elements that are unique from each other; identifying, via the one or more hardware processors, two or more arrays from said first set of arrays to obtain a second set of arrays, wherein two or more arrays from said second set of arrays comprises pairwise interacting elements that are unique from each other; interchanging, via the one or more hardware processors, said pairwise interacting elements across said two or more arrays in said second set of arrays to obtain a third set of arrays; and combining, via the one or more hardware processors, two or more arrays from said third set of arrays to form an optimized covering array.