1. A method for generating test vectors for an integrated circuit, the method comprising the following steps: (a) generating input test vectors and output test vectors for non-core cell portions of the integrated circuit; (b) generating, input test vectors and output test vectors for core cell partitions of the integrated circuit; and, (c) combining the input test vectors for the non-core cell portions and the input test vectors for the core cell partitions into a single combined input test vector, so that at least a subset of values for the output test vectors generated in step (a) and step (b) are not included in the single combined input test vector.