1. A method for reducing inter-thread communication latency in a multiprocessor system having a cache hierarchy with a write-through level one cache, the method comprising: providing a non-coherent store instruction; scheduling a first thread on a first hardware context associated with the write-through level one cache; scheduling a second thread on a second hardware context sharing the write-through level one cache; within the first thread, executing the non-coherent store instruction to pass a data value from the first thread to the second thread; and updating the shared write-through level one cache prior to updating a cache level at which a cache coherency policy is enforced such that the data value is passed from the first thread to the second thread before the data value is updated in the cache level at which the cache coherency policy is enforced.