1. A state machine engine, comprising: a state machine lattice comprising a plurality of configurable elements each comprising a plurality of memory cells, wherein the plurality of configurable elements are configured to analyze data and to output a result of the analysis, wherein the state machine engine is configured to halt the analysis upon receipt of an interrupt indication for interruption of operation of the state machine engine; an instruction buffer configured to provide the instruction associated with the operation of the state machine lattice; and an instruction insertion register configured to transmit an initialization instruction to indicate that an instruction associated with the operation of the state machine engine inclusive of the analysis is forthcoming subsequent to halting of the analysis, wherein the instruction buffer is distinct from the instruction insertion register.