1. A high-speed computer memory subsystem implemented within a network device, said high-speed computer memory subsystem for providing memory services to a network processor, said computer memory subsystem comprising: a high-speed interface comprising a Peripheral Component Interconnect (PCI) express bus; wherein a first end-point of the PCI express bus is connected to the network processor, and a second end-point of the PCI express bus is connected to a network memory unit, said network processor being separate from said network memory unit; a memory services protocol for said high-speed interface, said network processor using said memory services protocol to make memory service requests for more than one type of memory operation to said network memory unit, said memory operations including counter operations and First-In First-Out queue operations wherein the memory services protocol is carried by the PCI express bus; and a memory logic coupled to said high-speed interface, said memory logic processing and responding to memory service requests specified in said memory services protocol.