1. A computer program product for facilitating address translation in a computing environment, said computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: obtaining, by a processor, an address to be translated from the address to another address; translating the address from the address to the another address, wherein the translating comprises: determining an attribute of the address to be translated to the another address using a segment lookaside buffer (SLB), wherein the attribute indicates the address is to be translated as part of an instruction fetch or a data access; selecting first information of a first segment lookaside buffer entry as selected information to be used in translating the address to the another address in response to both the attribute being a first attribute and the attribute matching a corresponding attribute in the first segment lookaside buffer entry, wherein the first attribute comprises the address is to be translated for an instruction fetch; selecting second information of a second segment lookaside buffer entry as selected information to be used in translating the address to the another address in response to both the attribute being a second attribute and the attribute matching a corresponding attribute in the second segment lookaside buffer entry, wherein the second attribute comprises the address is to be translated for a data access; wherein the first and second information are concurrently available for selection; using the selected information to translate the address from the address to the another address, wherein the another address indicates one memory location based on the selected information comprising the selected first information and another memory location different from the one memory location based on the selected information comprising the selected second information, and wherein the one memory location and the another memory location are in a common address space interspersed with memory locations addressed by addresses translated using the selected first information and the selected second information, wherein a corresponding attribute is specified for each segment in conjunction with each segment lookaside buffer entry, enabling memory regions of the address to be translated to a common segment address for instruction accesses and data accesses.