1. A processor, comprising: a virtualization technique selector, configured to select a memory virtualization technique from among a plurality of memory virtualization techniques dependent, at least in part, on a prediction of a distribution of virtual memory locations to be accessed; and an address translator configured to: translate, on behalf of a first plurality of program instructions, a first virtual memory address to a first physical memory address according to a first selected memory virtualization technique; translate, on behalf of a second plurality of program instructions, a second virtual memory address to a second physical memory address according to a second selected memory virtualization technique, wherein said first selected memory virtualization technique is distinct from said second selected memory virtualization technique.