1. An apparatus, comprising: a level one cache; a level two memory, wherein in a first mode a first portion of the level two memory is configured as an extension of the level one cache, and in a second mode the first portion of the level two memory is configured as a portion of the level two memory and is excluded from operating as an extension of the level one cache; and control logic operable to route a memory access request to the first portion of the level two memory in parallel with the level one cache conditioned upon an indication that the first mode is enabled.