1. A high speed parallel digital adder for adding two digital operands comprising: input logic means including a plurality of stages to which said operand digits are applied, each stage receiving a different one or more corresponding pairs of operand digits and being operative in response thereto to produce first and second conditional sum signals for each stage along with corresponding carry output signals for each stage derived solely from the corresponding operand digits applied thereto, said first conditional sum signal being produced assuming the presence of a carry-in to the respective stage and each second condition sum signal being produced assuming the absence of a carry-in to the respective stage; carry look-ahead logic means responsive to said carry output signals for producing stage look-ahead carry and carry-not signals; and selection means to which said stage look-ahead carry and carry-not signals are applied along with said first and second conditional sums for selecting particular ones of said conditional sums representing the sum of said operands.