1. A programmable CPU multiplier responsive to instructions dedicated to polynomial operations, comprising: an array unit responsive to instructions dedicated to polynomial operations, the array unit having: a first array that is used to perform arithmetic multiplication, the first array having a first result output and a second result output; and a second array that is used to perform binary polynomial multiplication, the second array having a third result output; and a carry propagation adder having a first input, a second input, and an output, wherein the first input of the carry propagation adder is selectively coupled to the first result output of the first array, the second input of the carry propagation adder is selectively coupled to the second result output of the first array and the third result output of the second array, and the output of the carry propagation adder is stored in a register to provide an output of the polynomial operations.