1. An apparatus for performing a partial write operation of at least one byte of partial write data to an address of a word in a main memory wherein data is stored in words of multiple bytes, comprising: cache means for storing cache data in addressable words containing a plurality of bytes capable of being individually enabled for reading and writing, for determining in accordance with the main memory address whether the main memory address causes a cache hit, for selectively generating a cache hit signal in accordance with the determined result, for outputting at least one byte of cache data from a byte enabled for reading and designated by the main memory address in accordance with negation of a first control instruction input thereto, and for inputting and storing the partial write data at all bytes enabled for writing of a word at a cache address corresponding to the main memory address in accordance with said first control instruction; address and data output means for receiving the main memory address and the partial write data, for outputting the main memory address to said cache means, for combining the outputted cache data and the partial write data in accordance with a second control instruction input thereto, and for outputting the partial write data to said cache means in accordance with said second control instruction such that said combining and said outputting the partial write data to cache are simultaneously performed; and control means for selectively generating the first and second control instructions from the main memory address, for generating an input access control data indicating a byte width of the partial write data in accordance with the hit signal, and for outputting said first control instruction to said cache means wherein negation of said first control instruction enables at least one byte in a word of said cache means for reading, and wherein said first control instruction enables for all other bytes in said word for writing, and for outputting said second control instruction to said address and data output means.