1. A processor comprising a thread processor and a cache memory having a plurality of WAY, comprising: a supervising address register provided for each thread processor to hold a cache WAY number and a cache line address to designate a particular block of the cache memory, and a comparator provided for each thread processor to compare a cache WAY number and a line address of a cache memory held by a supervising address register with a cache WAY number and line address of a cache memory accessed from the other thread processor.