1. In a computer system executing a Pascal P-Code program, where P-Code includes instructions of 1, 2, 3 and 4 bytes in length, the system including a memory storing the program as a sequence of two byte words irrespective of the length of each individual instruction, a processing subsystem comprising: instruction processing logic means for generating a fetch request signal to obtain the next byte of an instruction in the program sequence and, upon receiving the first byte of a P-Code instruction, for generating 0, 1, 2, or 3 additional fetch requests as required to obtain the remaining bytes of the entire instruction; an instruction register for storing a two byte word retrieved from memory; a translation state register for storing a state code specifying the actions to be taken to obtain and transfer the next byte in the program sequence to the instruction processing logic means; and control logic means, responsive to a fetch request signal from the instruction processing logic means and responsive to the state code stored in the translation state register, (1) for retrieving from the memory the next word in sequence of the program and storing it in the instruction register if the state code specifies that the instruction register does not contain the next byte to be transferred to the instruction processing logic means, (2) for transferring from the instruction register to the instruction processing logic the next byte in the program sequence as specified by the state code, and (3) for setting the state code to specify the actions to be taken upon receiving the next fetch request, the processing subsystem, thereby accomplishing program instruction fetch control independently of the number of bytes in each instruction.