1. A method for verifying timing of a circuit including an interconnect part with RLC inputs and RLC outputs, the method comprising: expressing the interconnect part in terms of an admittance matrix for the RLC inputs and a voltage transfer from the RLC inputs to the RLC outputs; pre-characterizing the admittance matrix and voltage transfer without initial condition; integrating the interconnect with a driver part in the time domain with both the admittance matrix and the voltage transfer in the frequency domain with initial conditions.