1. A field programmable gate array (FPGA) comprising: a plurality of tiles, each tile of the plurality of tiles operable to be programmed at different times to perform only a logic function or only a routing function, wherein the plurality of tiles comprise a first tile comprising a first look-up table that is programmed to perform the logic function; and a set of second tiles that are separated from the first tile by one or more third tiles, wherein an output of the first tile is directly connected to at least one of the second tiles via at least one of the third tiles that comprises the look-up table that is programmed as a routing multiplexer coupled to a driver to perform the routing function.