1. An integrated non-volatile memory (NVM) system, comprising: an array of non-volatile memory (NVM) cells; bias voltage generator circuitry configured to generate bias voltages for the NVM cells; controller circuitry configured to determine performance degradation for the NVM system based upon performance information relating to at least one of a program operation or an erase operation and to adjust at least one voltage level for the bias voltages generated by the bias voltage generator circuitry based upon the performance degradation determination; wherein the controller circuitry is further configured to conduct at least one of a program operation or an erase operation for the NVM system using the at least one adjusted voltage level.