1. A method at a processing system having at least a master processor for simulation of an electrical circuit, the method comprising: mapping connectivity of the electrical circuit at the master processor, utilizing nonlinear differential algebraic equations (NDAEs): partitioning the electrical circuit into a plurality of sub-circuits at the master processor, the partitioning using is Companion Form representation of the electrical circuits and node tearing; representing coupling between the plurality of sub-circuits as binary vectors at the master processor; and obtaining interface results for each sub-circuit, the obtaining comprising: sending each of the plurality of sub-circuits, including binary interface vectors from the master processor to a plurality of slave processors; and receiving the interface results back at the master processor.