1. A method comprising: executing a logical reduction instruction in a semiconductor processor, said executing comprising: storing a vector having multiple elements into a register; swizzling the elements of the vector with swizzle circuitry to form a first swizzled vector; performing a vector logic operation with vector circuitry on the vector and the first swizzled vector to form a first intermediate vector; swizzling all elements of said first intermediate vector with swizzle circuitry to form a second swizzled vector; performing said vector logic operation with vector circuitry on said first intermediate vector and said second swizzled vector to form a second intermediate vector; and performing a logic operation on less than all elements of said second intermediate vector.