1. A method for sorting elements in hardware structures, said method comprising: selecting a plurality of elements to order from an unordered input queue (UIQ) within a range in response to finding a match between at least one most significant bit of said range and corresponding bits of a respective identifier operable to tag each of said plurality of elements, wherein said UIQ comprises a plurality of out of order elements; presenting each of said plurality of elements to a respective multiplexer; and generating a select signal for an enabled multiplexer corresponding to each element in said plurality of elements in response to finding a match between at least one least significant bit of a respective identifier operable to tag each of said plurality of elements and a port number of an ordered retirement queue.