1. A microprocessor, comprising: a hardware instruction translator, that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are encoded in a distinct manner from the manner in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded; and an execution pipeline, coupled to the hardware instruction translator, wherein the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; wherein the hardware instruction translator directly provides the microinstructions to the execution pipeline for execution to generate the results defined by the x86 ISA and ARM ISA instructions.