1. Circuitry for use with a field programmable gate array (FPGA), the circuitry comprising: an array of signal processing accelerators (SPAs) that is separate from the FPGA, wherein the array of SPAs is configured to receive input signals from the FPGA, and wherein each SPA in the array of SPAs has a same architecture that is configurable to implement different functions, wherein each of the different functions perform operations on data in the input signals to manipulate the data; and an array of network nodes that controllably route the input signals to the array of SPAs.