1. A logic simulation system for simulating a simulation target logic circuit, comprising: a host computer having data of the simulation target divided into a plurality of sections defining different simulation phases to be executed sequentially in time division; an emulator for emulating the simulation target, including: a plurality of programmable emulation chip means for mapping the simulation target, each emulation chip means having memory means with a plurality of memory banks provided in correspondence to said plurality of sections for registering mapping data specifying a function to be realized by said each emulation chip means in emulating each of said plurality of sections; programmable network means for interconnecting said plurality of emulation chip means; and emulation control means for controlling said plurality of emulation chip means and the network means by sequentially switching the memory banks of the memory means of said each emulation chip means and changing connections among said plurality of emulation chip means provided by the network means in emulating each of said plurality of sections; and interface means for interfacing the host computer and the emulator.