1. A graphics processing unit, comprising: a first set of registers, wherein the first set of registers includes architecturally-defined registers; a second set of registers configured to mirror the first set of registers; and an execution pipeline configured to: implement predication for an instruction sequence having opcodes that indicate whether the instruction sequence is to be conditionally executed based on a predicate value generated by a predicate writer instruction; store the predicate value in the second set of registers; and update the first set of registers with the predicate value in the second set of registers; and control logic configured to: perform evaluation of the predicate value in the second set of registers; and based on the evaluation, cause the execution pipeline to discontinue execution of the instruction sequence by clock gating one or more stages of the execution pipeline.