1. A computing system for simulating a design of a hardware system, the computing system comprising: a processor; and memory storing the design, wherein the design comprises: a system level simulation wrapper, comprising: a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication; a Cycle Accurate HDL model of an intellectual property (IP) block; a system level model of the IP block; and a switch coupled to the plurality of port interfaces, wherein the switch is selectively configured to communicate with the Cycle Accurate HDL model or the system level model.