1. A digital logic circuit comprising: a programmable logic device configured to include a pipeline that comprises a matching stage and a downstream ungapped extension prefilter stage, the matching stage being configured to receive a data stream comprising a plurality of possible matches between a plurality of data strings and a plurality of substrings of a query string, the ungapped extension prefilter stage being configured to (1) shift through pattern matches between the data strings and the plurality of substrings of a query string and (2) provide a score so that only pattern matches that exceed a user defined score will pass downstream from the ungapped extension prefilter stage.