1. An in-order multi-threading processor, comprising: a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread; an execution unit to execute said first thread and said second thread in parallel; a multi-thread scheduler coupled to said first instruction fetch unit, said second instruction fetch unit, and said execution unit, wherein said multi-thread scheduler is to determine the width of said execution unit; wherein said multi-thread scheduler unit determines whether said execution unit is to execute said first thread and said second thread in parallel depending on the width of said execution unit; and wherein said first thread and said second thread are compiled to have instruction level parallelism.