1. A receiver comprising: one or more signal-processing blocks adapted to generate a processed signal from a received signal; and a hardware-based matrix co-processor comprising: two or more different matrix-computation engines, each adapted to perform a different matrix computation; and one or more shared hardware-computation units, each adapted to perform a mathematical operation, wherein: at least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor; and each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.