1. A data processing system comprising: a cache memory for storing operands and instructions, each of said instructions including an operation code portion and also including descriptor information for describing characteristics of said operands; an execution control unit for storing microwords for executing operations specified by said instructions; a control unit coupled to said cache and to said execution control unit, said cache and said control unit being responsive to said microwords for transferring one of said instructions and said descriptor information specifying a decimal numeric operation to said control unit from said cache, said control unit being responsive to said microwords for transferring said operation code portion of said one of said instructions to said execution control unit for selecting a series of said microwords for executing said decimal numeric operation; a decimal unit coupled to said control unit and said cache including control means for receiving said descriptor information and operand processing means for receiving said operands in response to said series of said microwords for stripping decimal digits from said operands and packing said decimal digits into a plurality of words in accordance with said descriptor information, said decimal unit including adder means responsive to said descriptor information for indicating if said operands are short operands by shifting decimal digits from said long and short operands and packing said decimal digits into words; an execution unit coupled to said decimal unit for receiving said words in response to said series of microwords and performing said decimal numeric operation; wherein said control means being responsive to said descriptor information and a plurality of status flag signals generated in response to a selected field of said series of said microwords further generates a plurality of vector branch signals indicative of the number of words of said short operands and of the number of cache memory cycles between a first word of said short operands being requested by said microwords, and a first word of said plurality of words being received by said execution unit in advance of said decimal unit receiving said short operands from said cache; said execution control unit being further coupled to said decimal unit, and being responsive to said plurality of vector branch signals for branching to a subroutine of said series of said microwords, for processing said short operands.