1. Apparatus for simulating a circuit comprising: a hardware model of at least a portion of the circuit in a reconfigurable hardware logic using timing insensitive glitch-free (TIGF) logic; a software model of the circuit stored in a memory; and switch logic, coupled to the software model and the hardware model, for selectively switching between the software model and the hardware model while performing simulation over a plurality of simulation cycles; wherein the TIGF logic is configured to receive a global trigger signal comprising an evaluation period followed by a trigger period for each of the plurality of simulation cycles, the evaluation period configured to allow signals in the circuit to reach steady-state before the trigger period for each of a plurality of simulation cycles.