1. An integrated circuit (“IC”) comprising: N sets of configurable circuits for jointly processing a set of data signals at a first data rate, wherein each set of configurable circuits processes the set of data signals at a second data rate that is a fraction of the first data rate, wherein each set of the configurable circuits reconfigure at each reconfiguration clock cycle, and wherein the N sets of configurable circuits comprise respective rescaled portions configured at different clock phases; and a set of configuration data storage for iteratively supplying one of M sets of configuration data at each reconfiguration clock cycle to each set of configurable circuits.