1. A data processing device having a pipeline mechanism to execute an instruction by pipeline processing, comprising: a bypass to pass an operation result of a preceding instruction to a succeeding instruction as a source operand before writing the operation result to a register, wherein the succeeding instruction has a bypass specification field to indicate whether the source operand is to be received from the bypass or the register; and a source operand selector to select the source operand from the register or the bypass according to the bypass specification field.