1. A cache memory, comprising: a data array; a store queue configured to buffer synchronization operations and store operations; a pollution vector control configured to create respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory; and a store queue controller configured to set dependencies in a dependency data structure of the store queue based on the pollution vectors to reduce unnecessary ordering effects and dispatch store operations from the store queue in accordance with the dependencies indicated by the dependency data structure.