1. A circuit device for producing an output according to a sum of its input signals comprising, an FET circuit having a gate electrode, and a multi-stage capacitor structure for summing the inputs at the gate of the FET, comprising an input stage having multiple sets (V1 to V4, V5 to V8) of input electrodes for receiving the input signals, and a larger electrode (33 or 34) for each set and electrostatically coupled to the input electrodes of the corresponding set for summing input signals at each larger electrode, a last capacitor stage comprising a pair of electrodes (36, 37), and electrodes (39, 40) formed as a unitary structure coupled to the pair of electrodes for summing their signal voltage, and means coupling the pair of electrodes of the last stage to the larger electrodes of the input stage.