1. A multiprocessor electronic circuit comprising: a plurality of processors; a single cryptographic processing unit that comprises a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and that further comprises two cryptographic engines, a cipher engine and a hash engine, wherein the functional steps performed in either the cipher engine or the hash engine are performed independently from each other; and a control logic that connects the cryptographic processing unit and the plurality of processors and that implements the functionality of temporarily assigning the cryptographic processing unit to one of the plurality of processors.