1. A test system for non-volatile memory devices, the test system comprising: a controller circuit for executing test instructions and generating control signals; a non-volatile memory array comprising a plurality of memory blocks; test circuitry coupled to the controller circuit and adapted to determine voltage ranges of the memory array in response to the control signals; and a scratch control array of non-volatile memory cells, separate from and having a quantity of cells that is different than the non-volatile memory array, to store the instructions for execution by the controller circuit, the instructions forming a test sequence executed by the controller circuit when a quantity of defective cells of the at least one array block exceeds a predetermined threshold of defective cells.