1. A system for determining criticality in an electrical circuit comprising: a. a netlist input for receiving a circuit netlist, the netlist representing a topology of the electrical circuit; b. an assertion input for receiving one or more assertions representing boundary timing conditions; c. a delay variability input for receiving a list of one or more sources of delay variation that contain variability information of one or more of the sources of delay variation; d. a model input for receiving a parameterized delay model, the parameterized delay model containing a model for the delay of each component of the electrical circuit, each model being a function of one or more of the sources of variation; and e. a process that determines and outputs timing criticality information of the electrical circuit.