1. In combination: an instruction register for sequentially storing digital instructions during execution in a digital processor, each of said digital instructions corresponding to a sequence of microinstructions to be executed; an addressable memory for storing digital microinstructions constituting said sequences of microinstructions; a microinstruction register connected to the output of said addressable memory for sequentially storing said digital microinstructions after being read out of said memory and during execution; means coupled to said instruction and microinstruction registers for providing digital addresses to said addressable memory for reading said sequences of microinstructions out of said memory and sequentially into said microinstruction register for execution; said providing means comprising means for selecting a contiguous set of bits from the digital instruction resident in said instruction register for inclusion in one of said digital addresses wherein the number of bits in said selected set is determined by a first field of bits of the microinstruction resident in said microinstruction register and wherein the position in said resident instruction from which said set is selected is determined by a second field of bits of said resident microinstruction; and said providing means further comprising means for selecting bits from a third bit field of said resident microinstruction for inclusion in said one digital address.