1. A processor comprising: a branch resolution unit configured to detect a mispredicted branch operation, wherein the branch resolution unit is configured to transmit a redirect address for fetching instructions from a correct target of the branch operation responsive to detecting the mispredicted branch operation; and a redirect recovery cache comprising a plurality of cache entries, each cache entry configured to store operations corresponding to instructions fetched in response to respective mispredicted branch operations, wherein the redirect recovery cache is coupled to receive the redirect address and, if the redirect address is a hit in the redirect recovery cache, the redirect recovery cache is configured to supply operations from the hit cache entry to a pipeline of the processor, bypassing at least one initial pipeline stage.