1. In a stored program data processing system including a processor nucleus and input/output (I/O) devices, said processor nucleus including control storage containing microinstructions and data, said microinstructions having control bits and address bits, a microinstruction register connected to receive microinstructions from said control storage, microinstruction fetch means for accessing said control storage and transferring a selected microinstruction to said microinstruction register, a data local store, addressing means for addressing said data local store, internal address generation means selectively connectable by said control bits to receive said address bits from a microinstruction in said microinstruction register and connected to provide addresses to said addressing means, first and second operand registers having inputs from said data local store, from said microinstruction register and from sources external to said processor nucleus, an arithmetic and logic unit (ALU) connected to said operand registers, a data register connected to receive data from said ALU, clock timing control means connected to be controlled by said control bits and operable to provide timing control signals, the improvement comprising: external address register means selectively connectable under control of said control bits to receive said address bits from said mircoinstruction, external registers having logic means integral therewith to perform logical operations on data entered into said external registers for either said processor nucleus or said I/O devices means connecting said logic means integral with said external registers to said I/O devices, first gating means connected to control entry of data into said external registers, said first gating means connected to receive data from said data register under control of said external address register means and said clock timing control means, said data entered into said external registers including control data for said logic means integral with said external registers, and second gating means connected to said logic means integral with said external registers to receive output data therefrom and pass said output data to said operand registers in said processor nucleus, said second gating means being connected under control of said external address register means and said clock timing control means.