1. A system comprising: a processor; a pattern-recognition processor; and a plurality of registers, wherein the plurality of registers includes a first set of registers directly accessible by the processor via a first address map and a second set of registers not directly accessible by the processor via the first address map, wherein the first set and the second set of registers are directly accessible by the pattern-recognition processor via a second address map, and wherein the system is configured such that the second set of registers is indirectly accessible by the processor via the first set of registers.