1. A processor comprising: a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and one or more execution units, responsive to the decoded first instruction, to: perform one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set if a first indicator of said one or more substitution function indicators indicates a first substitution function; perform one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set if a second indicator of said one or more substitution function indicators indicates a second substitution function; and store a result of the first instruction in a SIMD destination register.