1. A computer processor comprising: first and second multi-stage instruction processing components that are configured to access and process in parallel instructions belonging to the distinct first and second instruction streams that have a predefined timed semantic relationship, wherein at least one of the first and second instruction streams includes variable-length instructions having a bit bundle bounded by a head end and a tail end with an alignment hole within the bit bundle, wherein the alignment hole includes bits that specify a count of implicit nop operations that follows the timed semantic relationship between the first and second instruction streams; wherein first and second multi-stage instruction processing components each include an instruction buffer coupled to a decode stage, wherein the instruction buffer for a particular one of the first and second multi-stage instruction processing components is configured to store at least one variable-length instruction, and the decode stage for the particular one of the first and second multi-stage instruction processing components is configured to i) decode operations encoded by the variable-length instruction stored by the instruction buffer for the particular one of the first and second multi-stage instruction processing components, ii) isolate and interpret the bits of the alignment hole of the variable length instruction, and iii) initiate a number of nop operations as represented by the count of implicit nop operations specified by the bits of the alignment hole in order to follow the timed semantic relationship between the first and second instruction streams.