1. A logic processor for processing two-state and four-state simulation data, comprising: an instruction fetch unit configured to retrieve and buffer a plurality of simulation instructions; an instruction decode unit configured to receive and decode instructions from the instruction fetch unit; a four-state register file comprising a plurality of pairs of registers to load data in accordance with the decoded instructions, each register of a pair corresponding to a Verilog data structure; and an arithmetic logic unit configured to use hardware device language semantic arithmetic, logical, and comparison operations on data in the pairs of registers.