1. In a computing device, a method for optimizing the timing-driven placement of one or more movable gates of a circuit in a physical synthesis flow using a non-linear delay model, the method comprising: identifying at least one movable gate based on at least one selection criteria; generating a set of legalized candidate locations corresponding to at least one identified movable gate; generating a disjunctive timing graph based on the generated set of legalized candidate locations; determining an optimal location of at least one movable gate using a recursive branch-and-bound search; and storing the optimal location in the computing device.