1. A data processing system for providing access to a memory unit by a plurality of central processor units, said system comprising a plurality of central processor units; a memory unit comprising a plurality of memory modules; an address bus for transferring addresses from said central processor units to said memory unit; a data bus for transferring data between said central processor units and said memory unit; multiprocessor control means comprising means for providing a processor word cycle having a plurality of time phases; means for controllably providing access to said address and data buses by different groups of said central processor units during different ones of said plurality of time phases during each instruction word cycle.