1. An apparatus, comprising: a multi-level cache memory including a lower-level cache and at least one higher-level cache, said lower-level cache located closer to a processor and having lower access latency than said higher-level cache; a set control logic to identify a first replacement candidate within said higher-level cache responsive to a first cache miss to said higher-level cache, to invalidate a cache line corresponding to the first replacement candidate in the lower-level cache, and to evict said first replacement candidate only if there is a second cache miss to said first replacement candidate within said higher-level cache prior to an intervening cache hit to said first replacement candidate within said higher-level cache; and a cache control logic to forward requests to system memory on a cache miss.