1. An apparatus, comprising: a plurality of processors capable of being operatively coupled to a main memory, each processor including an associated local memory and being operable to request at least some data from the main memory for use in the local memory; and at least one main processor operable to control access by the processors to data within the main memory and within the processors, wherein: at least one of the processors is operable to enter a secure mode of operation in which no requests initiated by others of the processors for data transfers into or out of the at least one processor are serviced, but such transfers initiated by the at least one processor are serviced subject to the access controlled by the main processing unit, and the main processing unit is operable to exclude access to data associated with at least one further processor by others of the processors except for the at least one processor.