1. A processor that executes coded instructions, the processor comprising: a fetch unit operative to fetch selected ones of the coded instructions; a marker unit within the fetch unit for marking the fetched instructions with instruction metadata; a floodgate unit having a first state in which marked instructions are passed to the fetch unit output and a second state in which marked instructions are held back; a plurality of downstream functional units coupled to receive and execute instructions from the floodgate unit, each of the functional units having a preselected number of resources available and the instruction metadata indicating the number of the resources required by each instruction; and a resource monitor unit having stored a count of the preselected number of resources available for the plurality of downstream functional units, the resource monitor being responsive to the instruction metadata to decrement the count of resources available based upon the number of resources required by each instruction, and the resource monitor being coupled to select the state of the floodgate unit.