1. An integrated circuit for implementing a secure hash algorithm, comprising: a data path configured to process an input message by performing rounds of the secure hash algorithm, the data path comprising hardware components that are reconfigurable; and a controller configured to control operation of the data path in performing the rounds of the secure hash algorithm, the controller comprising hardware components including an address control module and a finite state machine that cooperate with each other to provide control bits and physical memory addresses during each round of the secure hash algorithm; wherein at least some of the hardware components of the data path are reconfigured during each round of the secure hash algorithm in response to the control bits provided during each round of the secure hash algorithm; and wherein variable values stored in a variable memory are provided to the data path for processing during each round of the secure hash algorithm in response to the physical memory addresses provided during each round of the secure hash algorithm.