1. A microprocessor comprising fetch logic operative to: fetch an instruction; generate a hash index from one or more portions of an address for the instruction; generate a disambiguation tag from at least one other portion of the address for the instruction; determine whether an alternate version exists for the instruction based on the hash index and the disambiguation tag, including: referencing a translation address index in a translation address cache of the microprocessor according to the hash index, comparing a current context for the microprocessor with an assumed context, the current context describing a current working state of the microprocessor, the assumed context describing a state of the microprocessor for which the alternate version is valid, and determining that an alternative version of the instruction exists when the current context agrees with the assumed context, wherein the alternate version is a translation of the instruction, and the alternative version comprises a set of two or more micro-operations; and in response to a determination that the alternative version exists, abort the fetch of the instruction; and retrieve the alternate version for execution by the microprocessor, including retrieving a physical address for the alternate version from the translation address cache.