1. A processor that performs pipeline processing on an instruction, the processor comprising: a plurality of registers configured to store a result obtained by executing an instruction; an acquisition unit configured to acquire an instruction; a calculation unit configured to acquire a calculated value by performing calculation, wherein the calculation is designated by an operation code designating a type of processing, which operation code is included in the instruction acquired by the acquisition unit, and wherein the calculation uses an operand acquired in accordance with source register information designating a register that stores the operand used for calculation, which source register information is included in the instruction acquired by the acquisition unit, and that designates; a pipeline register that stores the calculated value obtained by the calculation unit; and a storage unit that stores, in accordance with destination register information designating a register that is to store the calculated value, which destination register information is included in the instruction acquired by the acquisition unit, the calculated value stored in the pipeline register in the designated register, wherein in a case in which a first instruction including the destination register information that designates a register that is to store the calculated value, and a second instruction that does not include the destination register information, are input to the processor, and a calculated value obtained in accordance with the first instruction is stored in the pipeline register when the calculation unit performs calculation in accordance with the second instruction, if a register indicated by the source register information included in the second instruction and a register indicated by the destination register information included in the first instruction match, the calculation unit acquires the calculated value stored in the pipeline register as an operand used for the second instruction, and in a case in which the register indicated by the source register information included in the second instruction and the register indicated by the destination register information included in the first instruction match, and the second instruction or an instruction that precedes to the second instruction designates the second instruction as the last instruction that uses the calculated value obtained in accordance with the first instruction, the storage unit does not store the calculated value stored in the pipeline register in the register indicated by the destination register information included in the first instruction, and stores, in other cases, the calculated value stored in the pipeline register in the register indicated by the destination register information included in the first instruction.