1. A method of designing a layout for an integrated circuit comprising: receiving a logic description in a high-level description language for the integrated circuit, the logic description having a plurality of circuit objects interconnected to form a plurality of nets, by executing first instructions in a computer system; identifying a plurality of placeable objects in the circuit description, by executing second instructions in the computer system; assigning physical design attributes including locations to a selected subset of the placeable objects, by executing third instructions in the computer system; visually displaying a layout abstract which shows the selected subset of the placeable objects at their assigned locations, by executing fourth instructions in the computer system; and saving the circuit description with the assigned physical design attributes as a synthesis input file, by executing fifth instructions in the computer system.