1. A processor for retrieving a data transfer instruction in a cache memory as a combination of instructions, said processor comprising: a memory transfer routine detection unit detecting an existence of a combination of instructions indicating a memory transfer process in the cache memory by confirming an existence of a loop in a sequence of instructions fetched from an instruction cache, said detection unit detecting the existence of the combination of instructions by checking instruction codes and operand codes in the sequence of instructions to be executed; and a memory transfer unit exclusively executing a data transfer process in the cache memory, wherein the combination of instructions detected by the memory transfer routine detection unit is assigned to the memory transfer unit for execution.