1. A method of high level synthesis of an integrated circuit including execution units for partial scan testing from a control data flow graph (CDFG) description of the integrated circuit comprising the steps of: allocating a quantity of execution units based upon resource allocation; selecting scan variables assignable to scan registers for breaking all loops in said CDFG such that the number of scan registers is minimized, by calculating a loop cutting effectiveness (LCE) measure for estimating the quantity of loops broken by selecting a scan variable and by calculating a highest hardware sharing effectiveness (HSE) value for scan variables and selecting those scan variables with the highest calculated loop cutting effectiveness measure and hardware sharing effectiveness value; scheduling and assigning operations to execution units for substantially minimal cost; and synthesizing the integrated circuit according to said allocating, said selecting and said scheduling and assigning.