1. A parallel processor, comprising: a Processing Element (PE) array having a plurality of PEs; a local memory directly connected to the PE array; a separate floating-point accumulator array having a plurality of accumulators for performing a floating-point addition operation, wherein the floating-point accumulator array includes the same number of accumulators as PEs included in an uppermost row of the PE array and each of the accumulators communicates with a PE of the same column in the uppermost row to perform a floating-point addition operation; and a control unit for reading an instruction from an external memory, broadcasting the instruction to the PEs of the PE array, and addressing the local memory when a PE communicates with the local memory.