1. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising: a plurality of reprogrammable logic devices, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said reprogrammable logic devices also having programmable input/output terminals which can be reprogrammably connected to selected ones of said functional elements configured into said reprogrammable logic devices, said reprogrammable logic devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection; a plurality of reprogrammable interconnect devices, each of said reprogrammable interconnect devices having input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected ones of said input/output terminals, said plurality of reprogrammable interconnect devices also having an input demultiplexer and an output multiplexer implemented at at least one input/output terminal. said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection; and a set of fixed electrical conductors connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.