1. A microprogrammed multi-core processor, the microprogrammed processor being microcode controlled and comprising: at least two processor cores, each of said processor cores having at least one internal execution unit and an associated microinstruction register; a common internal microprogram control store connected to said microinstruction registers of said at least two processor cores, said common internal microprogram control store including microcode instructions for controlling at least the internal standard operation of said at least two processor cores, said microcode instructions controlling operation of said internal execution units; means for providing time-shared access to said microprogram control store by said at least two processor cores, wherein the microcode instructions from said common control store are loaded directly into said microinstruction registers of said at least two processor cores, contents of each of said microinstruction register directly controlling the associated said execution unit, thereby sharing resources of said control store of the microprogrammed processor, and wherein said at least two processor cores are separate and configured to execute different microprogram tasks independently of each other according to respective execution threads, said execution unit of each of said at least two processor cores determining a next microprogram address.