1. In a computer system including a first processor and a second processor, said computer system having a programmable interrupt controller for receiving a processor-associated vector and for correspondingly generating an interrupt request, a combined multiprocessor interrupt controller and interprocessor communication system comprising: a system bus; an input/output bridge element coupled to said system bus, said input/output bridge element comprising interrupt circuitry for receiving said interrupt request and for obtaining said processor-associated vector from said programmable interrupt controller, and circuitry for packaging said processor-associated vector into an interprocessor communication message and for providing said interprocessor communication message onto said system bus; and a system controller coupled to said system bus, said system controller comprising bus interface circuitry for receiving said interprocessor communication message from said input/output bridge element through said system bus, and decode circuitry for decoding said interprocessor communication message and retrieving said processor-associated vector, wherein said bus interface circuitry further provides said processor-associated vector to one of said first and second processors.