1. A data processor, comprising: instruction cache memory having a plurality of memory; a branch prediction data storage unit for storing prediction data of a conditional branch of a branch instruction being taken or not taken, and in a case of the conditional branch being taken, prediction data of memory storing data of the branch instruction from among the plurality of memory; and a read active control unit for, when an instruction is to be executed in a branch instruction, outputting a read active control signal to the plurality of memories by using the prediction data of the conditional branch being taken or not taken obtained from the branch prediction data storage unit by an index corresponding to the branch instruction, and the prediction data of the memory.