1. A computer-implemented method for simulating a circuit design, the method comprising: initializing one or more initial simulated logic elements to an unknown Boolean state; feeding the unknown Boolean state to one or more first simulated logic elements; simulating one or more first results resulting from the first simulated logic elements, the first results including at least one negative unknown Boolean state, wherein the negative unknown Boolean state is the opposite of the unknown Boolean state; feeding the negative unknown Boolean state to one or more second simulated logic elements; and simulating one or more second results resulting from the second simulated logic elements.