1. A processor address translation apparatus for translating an instruction operand address to a different operand address, the processor address translation apparatus comprising: a memory with an address input for selecting a data element from a plurality of data elements; an instruction register for receiving an instruction encoded with an operand address in an operand address bit field of the instruction and control information indicating the operand address is to be translated as part of the instruction's execution; and an address translation unit for accessing the memory in a translation pattern, having the operand address bit field as input and, in response to the instruction received in the instruction register, directly translating the operand address bit field received as input to form the different operand address in accordance with the translation pattern, the different operand address accessing a data element from the memory through the address input.