1. A store data buffer control for a system in which data to be stored from a processor to a memory is temporarily and sequentially stored in a plurality of store data buffers and the stored data is then stored sequentially in said memory from said store data buffers, comprising: indication means provided for each of said store data buffers to indicate the presence or absence of data for each store data buffer; first designation means responsive to a store request signal from said processor for designating sequentially that one of said store data buffers into which data from the processor is to be next stored, said first designation means including means for causing the indication means corresponding to the designated store data buffer to indicate the presence of data; second designation means for designating sequentially one of said store data buffers from which data is to be transferred into said memory; first control means responsive to an indication of the presence of data by at least one of said indication means for instructing data transfer from the store data buffer designated by said second designation means to the memory, and simultaneously for causing the indication means corresponding to the store data buffer designated by the second designation means to indicate the absence of data for that store data buffer; store request hold means for storing successive request signals from said processor and for holding the store request signals for a predetermined period of time; and indication changing means connected to said first designation means and said store request hold means and responsive to occurrence of a fault in the processor which may result in the storing of invalid data in at least one of said store data buffers in response to the indication of the presence of data by at least one of said indication means for causing said indication means to indicate the absence of data for those store data buffers which have received data on the basis of the request signals held in said store request hold means, whereby said first control means will not recognize the presence of data in those store data buffers and therefore will not instruct a data transfer of any data stored therein, thereby to prevent the transfer of invalid data to said memory.