1. Apparatus for processing data comprising: pre-decoding circuitry responsive to program instructions fetched from a memory to perform pre-decoding operations upon said program instructions to form pre-decoded instructions; a cache memory coupled to said pre-decoding circuitry to store said pre-decoded instructions; decoding circuitry responsive to pre-decoded instructions read from said cache memory to generate control signals; and processing circuitry responsive to said control signals to perform processing operations specified by said pre-decoded instructions; wherein said program instructions are from a plurality of different instruction sets; said pre-decoding circuitry maps program instructions from a first instruction set and program instructions from a second instruction set to pre-decoded instructions having a shared format to represent shared functionality; and a shared portion of said decoding circuitry generates said control signals to control said processing circuitry with respect to said shared functionality.