1. An apparatus for reducing replays in an out-of-order processor, the apparatus comprising: a first reservation station, coupled to a hold bus, configured to dispatch a first load micro instruction, and configured to detect and indicate on the hold bus if said first load micro instruction is one of a plurality of specified load instructions directed to one of a plurality of non-core resources, wherein said plurality of non-core resources are shared by a plurality of cores of the out-of-order processor; replay reducer circuitry configured to detect said specified load micro instruction directed to non-core resources, wherein the replay reducer circuitry is further configured to evaluate an opcode portion of a load micro instruction that implicates a noncore resource; replay reducer circuitry configured to evaluate an unmodified opcode portion of a load micro instruction that implicates a non-core resource, in order to detect said specified load micro instruction directed to non-core resources; a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if it is indicated, in response to the detection by the replay reducer circuit, on said hold bus that said first load micro instruction is said one of said plurality of specified load instructions, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved an operand; load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction, and configured to enter a power savings state if no micro instructions are received for execution, wherein, if said first load micro instruction is not said specified load micro instruction, said load execution logic indicates on a miss bus if said first load micro instruction fails to successfully execute in said first number of clock cycles, thus initiating a replay of said one or more younger micro instructions, and wherein, if said first load micro instruction is said specified load micro instruction, said load execution logic does not indicate that said first load micro instruction fails to successfully execute if more than said first number of clock cycles are required to successfully execute, thus precluding a replay of said one or more younger micro instructions; and said plurality of non-core resources which are located outside of said plurality of cores, comprising: a random access memory, configured to store microcode patches corresponding to the out-of-order processor which, upon initialization, accesses said random access memory to retrieve said microcode patches.