1. A processor comprising: a first branch predictor configured to: provide an indication whether a given branch instruction has hysteresis, wherein the hysteresis indicates the given branch instruction has a frequently alternating pattern for its branch direction; and generate first branch prediction data for the given branch instruction; a second branch predictor configured to generate second branch prediction data for the given branch instruction; and control logic configured to train the first branch predictor by updating stored values in the first branch predictor used to predict a branch direction; wherein in response to detecting a mismatch between the first branch prediction data and the second branch prediction data, the control logic is configured to: train the first branch predictor for the given branch instruction, responsive to detecting the indication does not indicate hysteresis; and prevent training of the first branch predictor for the given branch instruction responsive to detecting the indication does indicate hysteresis.