1. An array of field programmable gate array (FPGA) devices configured for execution of a source code, the array comprising: two or more FPGA devices that are configured to execute a parallelized portion of the source code that is partitioned among the FPGA devices, wherein: the source code is partitioned based on data rates of computing elements of the source code, computational performance of the FPGA devices, and input/output (I/O) bandwidth of the FPGA devices, two or more of the FPGA devices include a memory bank that is addressable by a global memory address space for the array and includes an array interconnect configured to enable the computing elements that are executed by each of the FPGA devices to be programmed with a uniform address space of a global memory of the array and to enable utilization of the global memory by each of the FPGA devices, at least one of the FPGA devices includes a slave synchronization kernel that is configured to synchronize intermediate results between two or more of the computing elements, and one of the FPGA devices includes a master synchronization kernel that is configured with synchronization information that pertains to the slave synchronization kernel and to further synchronize the slave synchronization kernel with the other computing elements of the array; a host processor; and a host interface logic configure to connect the host processor with at least one of the FPGA devices.