1. A method, comprising: ceasing to determine path metrics for an encoded signal using add compare select logic in a hardware Viterbi decoder; determining a best state using the add compare select logic in ceil((K−1)/r) clock cycles, K equal to code constraint length of the hardware Viterbi decoder processing r trellis-sections per cycle, where r=log 2 R and R is Radix-R add compare select unit (ACSU) data-path; and resuming determination of path metrics of the encoded signal using the add compare select logic.