1. A processor comprising: a two-dimensional array of processing elements; and multiple shift-register planes, each shift-register plane comprising a separate two-dimensional shift-register array, wherein each shift register of each shift-register array is dedicated to one of the processing elements, wherein the processor is configured to execute instructions to perform a matrix multiplication operation on a first matrix stored in a first shift-register plane and a second matrix stored in a second shift-register plane to generate a result of the matrix multiplication operation stored in a third shift-register plane, wherein the first matrix comprises N columns, and wherein the instructions cause each processing element to perform, for N iterations, operations on shift registers dedicated to the processing element, the operations comprising: performing a multiplication operation between a first value stored in a first shift register of the first shift-register plane and a second value stored in a second shift register of the second shift-register plane, performing an addition operation between a result of the multiplication operation and a summation value stored in a third shift register of the third shift-register plane, updating the summation value stored in the third shift register of the third shift-register plane using a result of the addition operation, and based on determining that a current iteration is not a last iteration: shifting data in the first shift-register plane one unit in a first dimension corresponding to rows of the first matrix, and shifting data in the second shift-register plane one unit in a second dimension corresponding to columns of the second matrix.