1. A system for generating a specification error signal in response to a predetermined type of instruction in at least one preselected format containing: (i) an operation code of at least two binary bits of information, the binary state of at least one bit indicating said instruction is of said predetermined type, and (ii) at least one field of at least two binary bits of information the binary states of said two bits determining whether a specification exception exists in said instruction, said system comprising, in combination: discriminator means for generating a first enabling signal in response to said instruction when said instruction is in said preselected format, said discriminator means comprising: (1) means for detecting and discriminating between instructions in said preselected format and instructions in other formats, and (2) means for generating said first enabling signal when said instructions are in said preselected format; means for generating a second enabling signal in response to the binary state of said one bit of said operation code indicating said instruction is of said predetermined type; and means for generating said specification exception signal in response to (a) said first enabling signal, (b) said second enabling signal, and (c) a predetermined binary state of each of said bits of said field of said instruction.