1. In a target processor, a trace apparatus comprising: a trigger unit responsive to user and target processor state input signals, the trigger unit generating control signals in response to the input signals; timing trace apparatus, the timing trace apparatus responsive to control signals for selectively providing timing trace streams during secondary code execution; program counter/data trace apparatus, the program counter/data trace apparatus responsive to signals from the control apparatus for selectively providing program counter/data trace streams during secondary code execution when the timing trace unit is providing signal during the secondary code execution.