1. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of processor cores, the method comprising: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a respective function associated with executing instructions of the same program to be executed on the integrated circuit, where at least a first set includes one or more processor cores assigned to a first function associated with preparing the instructions for execution, at least a second set includes one or more processor cores assigned to a second function, performed in parallel with the first function, associated with executing the prepared instructions, and the number of processor cores assigned to the first set is larger than the number of processor cores assigned to the second set at startup of the program; speculatively performing, by the first set of one or more processor cores, the first function on at least some instructions before it is determined that those instructions will be executed; storing the results of performing the first function as the prepared instructions; determining, by the second set of one or more processor cores, when reaching a portion of the program not previously executed, whether the first function has been speculatively performed on instructions for that portion of the program and the results of performing the first function have been stored as prepared instructions, with the second set of one or more processor cores retrieving the stored prepared instructions if prepared instructions were stored, and stalling to wait for the first set of one or more processor cores to perform the first function on instructions for that portion of the program if prepared instructions were not stored; and reconfiguring the number of processor cores assigned to at least one of the sets during execution of the program based on characteristics associated with executing the instructions including detecting a portion of the program associated with increased resource demand for performing the second function and reassigning at least some of the processor cores from the first set to the second set.