1. A method of creating a test pattern for use in testing a semiconductor chip having a built-in self-test (BIST) module configured to generate a plurality of vectors from a set of pseudo-random pattern generator (PRPG) values, the method comprising the steps of: simulating a plurality of pseudo-random vectors to be generated by the set of PRPG values; selecting a plurality of IDDQ vectors compatible with an IDDQ test from the plurality of pseudo-random vectors; and identifying the IDDQ vectors in the test pattern to thereby facilitate IDDQ testing of the semiconductor chip using the vectors applied by the BIST module.