1. A memory device, comprising: an array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure comprising a first signal electrode, a second signal electrode, and a resistive layer coupled to the first signal electrode and the second signal electrode; a plurality of word lines connected to the first signal electrodes of a row of memory cells; and a plurality of bit lines connected to the second signal electrodes of a column of memory cells and wherein the resistive layer comprises two resistive elements that in combination have a zero temperature coefficient.