1. In a data processor having an instruction pipeline, wherein the instruction pipeline has a plurality of instruction pipeline stages, and wherein the plurality of pipeline stages comprise a first instruction pipeline stage and a second instruction pipelines stage, a method, comprising: providing a data processor instruction to the instruction pipeline that causes the data processor to perform a first set of computational operations during execution of the data processor instruction; performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, wherein the first mode comprises a parity protected mode of a memory coupled to the data processor; and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected, wherein the second mode comprises an error correction code (ECC) protected mode of the memory.