1. A semiconductor device comprising: a controller configured to generate a data retention path control signal in response to a power condition change signal; a plurality of data retention paths configured to sequentially couple a plurality of global input/output (I/O) lines coupled to a volatile memory to a dummy I/O line in response to the data retention path control signal; a dummy I/O pad coupled to the dummy I/O line; and a non-volatile memory device coupled to the dummy I/O pad, configured to retain a plurality of storage data segments received from the volatile memory when powered off, or provide data retained in the non-volatile memory to the volatile memory as recovery data when power is recovered.