1. A graphics processing appartus comprising: shader execution circuitry configured to execute a plurality of shader routines in order to perform a predetermined sequence of shader operations; rendering circuitry configured to perform at least one rendering operation on data output by the shader execution circuitry; control circuitry configured to allocate to the shader execution circuitry individual shader routines from a set of shader routines, in order to cause the predetermined sequence of shader operations to be performed; the predetermined sequence of shader operations including a tessellation setup operation, the tessellation setup operation receiving as an input an initial list of initial data for N initial vertices, and generating as output an input list of input data for M input vertices and tessellation control data; the predetermined sequence of shader operations further including a tessellation operation, the tessellation operation receiving as inputs said tessellation control data and said input list of input data for M input vertices, and generating at least output data for P output vertices; the control circuitry is configured to cause the tessellation operation to be performed by allocating to the shader execution circuitry, for each output vertex of the P output vertices, a tessellation shader routine from said set of shader routines; the shader execution circuitry configured, each time the tessellation shader routine is executed for an associated output vertex, to: (i) compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and to (ii) compute from the input data for the M input vertices, and the tessellation coordinate data, the output data for the associated output vertex.