1. A system for automatically alleviating processor race conditions, the system comprising: a sub-phase clocking mechanism for dividing a circuit clock into a plurality of sub-phases; and a translator for (i) translating program elements from a coding language into an electronic data interchange format, (ii) classifying each program element according to specified ranges of time required for the program element to perform its tasks, and (iii) assigning program elements within each range of time to a corresponding clock subphase.