1. A memory system for a computational circuit having a pipeline including at least one functional unit, comprising: a. an address generator that generates a memory address; b. a coherent cache memory that is addressed by the memory address, a cache directory being associated with the cache memory, the cache memory capable of generating a cache memory output; c. a non-coherent directory-less associative memory that is addressed by the memory address and that receives input data from the cache memory, the associative memory capable of generating an associative memory output that is delivered to the functional unit; and d. a comparison circuit that compares the associative memory output to the cache memory output and that asserts a miscompare signal when the associative memory output is not equal to the cache memory output.