1. A computer implemented method for verifying connectivity for a hierarchical configuration of shapes representing an integrated circuit design, comprising: using at least one processor that is configured or programmed for performing a process, the process comprising: identifying one or more lists of connected shapes for a net in a hierarchical physical electronic design having a plurality of hierarchical levels, wherein the one or more lists of connected shapes are identified without requiring the hierarchical physical electronic design to be unfolded, and a hierarchical level of the plurality of hierarchical levels is considered as unfolded when an action of hierarchy flattening is performed on at least the hierarchical level; determining a number of lists of connected shapes that result from the act of identifying the one or more lists of connected shapes for the net; and identifying an open circuit if the number of lists from the act of determining the number of lists is greater than one.