1. A system comprising: a memory device having a n-bit multi-purpose register (MPR); and a memory controller coupled with the memory device, the memory controller to, for at least N combinations of N bits, write a bit combination to the MPR over a non-swizzled bus, read the bit combination from the MPR over a swizzled bus, and generate a mapping of bit ordering between the memory device and the memory controller corresponding to the swizzled bus, the memory controller to write data to a memory location in the memory device by using the mapping and applying an error correcting code to the data.