1. A method comprising: receiving descriptions of a design circuitry including at least one known and at least one unknown logic module; selecting a portion of the design circuitry; and replicating, by a digital processing system, the selected portion of the design circuitry, the replicating omitting replication of at least one unknown logic module of the selected portion of the design circuitry, the replicating further providing outputs of the at least one unknown logic module as a delayed an input to a corresponding logic module within the replicated circuitry; wherein the replicated circuitry preserves the functionality and includes fewer logic modules than the selected portion of the design circuitry for facilitating debugging of the design circuitry.