1. A digital arithmetic combiner, comprising: respective overflow input and output terminals; respective operand input terminals; a tristate device having a data input terminal coupled to said overflow input terminal, a data output terminal coupled to said overflow output terminal, and a tristate control terminal, and including first and second controlled switches having control electrodes coupled to said tristate control terminal and having primary conduction paths serially coupled between a source of operating potential and a source of reference potential; an overflow generator having respective input terminals coupled to said operand input terminals, and an output terminal coupled to said overflow output terminal, for generating a signal indicating overflow conditions when the signals at said operand input terminals have the same logic states; and logic circuitry coupled between said operand input terminals and said tristate control terminal for enabling said tristate device to generate a signal at said data output terminal when the signals at said operand input terminals have different logic states.