1. A process of transforming an original netlist for an integrated circuit to a final netlist employing only universal gates having four inputs and two outputs, the universal gate being arranged to perform at least two logic functions, the process comprising steps of: a) input an original netlist in basic form of two-input gates and inverters, each gate and inverter having an output; b) creating a negation net for each net coupled to an input or output of each gate and to an input of each inverter; c) removing each gate of the original netlist and inserting a universal gate in its stead such that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement; and d) removing each inverter of the original netlist and negating the net previously coupled to the input of the inverter.