1. A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N, comprising: a) N functional units, each of the N functional units comprising logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation; and, a floating point multiply add instruction said logic circuitry comprising a multiplier, an adder and a shift register to support said first and second integer multiply add instructions and said floating point multiply add instruction, said shift register inserted before said adder to align a C term and said multiplier's AB term in support of said first and second integer multiply add instructions and said floating point multiply add instruction, wherein, a different shift strategy is used for said shift register for said floating point instruction than for said integer multiply add instructions, said shift strategy comprising, for said floating point multiply add instruction, shifting one of the AB term and the C term to be aligned with the other of the AB term and the C term, said shift strategy also comprising, for said first and second integer multiply add instructions, shifting said C term to effectively pad said C term with zeros, wherein said shifting of said floating point multiply add instruction is in an opposite direction that said shifting of said first and second integer multiply add instructions; b) masking circuitry to enable presentation of output results from selected ones of said N functional units.