1. A microprocessor that supports the Advanced RISC Machines (ARM) instruction set architecture (ISA), which specifies a plurality of processor modes, including a User mode, an FIQ exception mode, and a plurality of non-FIQ exception modes, and which specifies architectural registers associated with each of the plurality of processor modes and which specifies a load multiple instruction that instructs the microprocessor to load data from memory into one or more of the architectural registers specified by the load multiple instruction, the microprocessor comprising: direct storage, that holds data associated with a first portion of the architectural registers and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; indirect storage, that holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit; wherein the indirect storage is a private random access memory (PRAM) not within the instruction set architecture system memory space; wherein which of the architectural registers are in the first and second portions varies dynamically based upon a current processor mode of the plurality of processor modes; wherein for each of the architectural registers specified by the load multiple instruction: when the architectural register is currently in the first portion, the microprocessor loads data from memory into the direct storage; and when the architectural register is currently in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage; wherein when the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R 13 -R 14 architectural registers of the ARM ISA exception modes and the R 8 -R 12 architectural registers of the ARM ISA FIQ exception mode; wherein when the current processor mode is the ARM ISA FIQ exception mode then the direct storage holds data associated with the FIQ exception mode architectural registers, and the indirect storage holds data associated with the R 13 -R 14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R 8 -R 12 architectural registers of the ARM ISA processor mode previous to the current processor mode; and wherein when the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R 13 -R 14 architectural registers of the ARM ISA User mode and exception modes other than the current non-FIQ exception modes and also holds the R 8 -R 12 architectural registers of the ARM ISA FIQ exception mode.