1. A data processing system including a microprogrammable data processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different phases of operation to completion, said data processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to said multibit operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a multibit control sequence code having less bits than said operation code and an address, said control sequence code specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences; a cycled addressable second control store including a plurality of locations for storing at least one microinstruction of a different one of said plurality of execution sequences; an address register connected to receive said address from said first control store and connected to said second control store for read out of the microinstruction contents of a location during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation; hardwired control state sequencing means coupled to said first control store including sequence decoder circuit means for decoding said control sequence codes, said hardwired control sequencing means for generating different sequences of control signals for defining the different operations to be performed during a first one of said phases of operation for each instruction, said hardwired control sequencing means, being conditioned by each control sequence code within a certain class read out in response to the operation code of an instruction being processed, for generating a predetermined one of said different sequences of control signals, for performing said operations during said first one of said phases of said instruction, for transferring said address into said address register, for continued processing of said instruction under the control of the specified one of said plurality of execution sequences, and for placing said sequencing means in a predetermined state, said specified execution sequence including a microinstruction containing a restart code bit pattern; and, decoder circuit means coupled to said hardwired control state sequencing means and to said output register, said decoder circuit means being operative upon the read out of said microinstruction restart code pattern from said second control store into said output register to generate signals for switching said hardwired control state sequencing means from said predetermined state to another state to continue instruction processing in said pipelined fashion.