1. A memory device comprising: an array of data memory cells arranged in data rows and data columns; a plurality of gates for transmitting respective row selection outputs of a row decoder to respective rows; a dummy column of dummy memory cells substantially identical to the data memory cells; precharge means for precharging the data columns and the dummy column at a precharge potential when no data row is selected; programming means for setting selected data columns at respective programming potentials; dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no data row is selected; dummy column programming means for setting the dummy column to a second logic state opposite to the first logic state; and first detector means for detecting that the dummy column has discharged from the precharge potential to the second logic state and for consequently enabling the plurality of gates, wherein each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state.