1. An apparatus, comprising: an instruction cache; and control circuitry configured to: detect a pattern of execution of instructions, wherein the instructions are a set of instructions executed by an instruction processing pipeline, based on execution of at least a portion of the instructions in the set of instructions multiple times, wherein the pattern includes multiple forward control transfer instructions within a loop; wherein at least one of the multiple forward control transfer instructions, during a time interval between detecting the pattern and exiting the pattern, transfers control in one iteration of the pattern and does not transfer control in another iteration of the pattern; and wherein at least one cache line between at least one of the multiple forward control transfer instructions and its target is not included in the pattern; and store the set of instructions in the instruction cache, wherein the apparatus is configured to store at most one copy of each instruction in the pattern in the stored set of instructions; wherein the apparatus is configured to fetch and execute the instructions from the instruction cache.