1. A computing system comprising: a plurality of processors; a cache configured to be accessed by at least two of the plurality of processors; a cache controller coupled to the cache; a persistent memory coupled to the cache controller; wherein a first thread of a plurality of threads executed by a first processor of the plurality of processors is configured to send a given data block to the persistent memory for storage via the cache controller; and wherein the cache controller is configured to: in response to receiving the given data block and determining a coherence state corresponding to the given data block does not already prevent read access, increment a respective per-thread count for the first thread; prevent any read access of a copy of the given data block in said cache, in response to detecting the given data block is to be sent to be stored in the persistent memory; and in response to receiving a corresponding acknowledgment that the given data block is stored in the persistent memory, decrement the respective per-thread count for the first thread.