1. A method of operating a multi-transistor, scalable SRAM cell having a single floating body transistor, said method comprising: providing the floating body transistor in which ground is applied to a source of the floating body transistor, and wherein said source comprises a first conductivity type selected from p-type and n-type conductivity types, and in which a drain of the floating body transistor comprising a second conductivity type selected from said p-type and n-type conductivity types and different from said first conductivity type is connected to a write access transistor and a read sense device, wherein said floating body transistor comprises a floating body region configured to be charged to a level indicative of a state of the memory cell; a buried layer having a different conductivity type from a conductivity type of said floating body region; biasing said buried layer to ensure bistable operation of the floating body transistor; and applying pure logic levels on a bit line connected to said write access transistor and a read access transistor in combination with operation of a write word line and a read word line connected to said write access transistor and said read access transistor, respectively.