1. In a device comprising a programmable processor with an associated physical memory space which stores native functions in a format determined by a hardware architecture of the processor, the improvement comprising a virtual machine concurrently emulated by the processor which executes virtual functions in a standardized format determined irrespective of the hardware architecture of the processor, wherein the execution of a selected virtual function by the virtual machine causes the processor to execute a corresponding native function, and wherein the corresponding native function is executed to evaluate concurrent execution of at least one other native function.