1. A very high-density complex programmable logic device (CPLD) having a plurality of hierarchical signal paths, said CPLD comprising: a first hierarchical level circuit having first hierarchical level resources wherein a first hierarchical level signal path within said first hierarchical level circuit utilizes only said first hierarchical level resources; and a second hierarchical level circuit having second hierarchical level resources connected to said first hierarchical level resources wherein a second hierarchical level signal path utilizes only second and first hierarchical level resources.