1. A processor, comprising: an instruction decoder to decode instructions; an execution unit coupled to the instruction decoder to execute instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit; a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit; and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics.