1. An apparatus comprising: a digital signal processor (DSP) with a hardware stack configured and arranged to be used by program code for call subroutines for which the hardware stack is invisible to a software program language used to program the DSP; a first circuit configured and arranged to provide a set of DSP instructions including a primary set of instruction codes via the software program language and including inline assembly instruction codes; the DSP being configured and arranged with the first circuit to execute the inline assembly instruction codes, and therein to store a respective return address of a first task by saving a program counter for the digital signal processor, branch to a different portion of the primary set of instruction codes for carrying out a blocking function, including maintaining the hardware stack so contents of the stack remain unmodified; determine if a blocking condition for said blocking function is present; store shared resources of the processor, if a blocking condition is determined; switch to at least a second task; and use the saved program counter to return to the first task.