1. A method for testing an electronic memory while the electronic memory is in use, comprising: initializing a write error detection code in response to a write access to the electronic memory at a location at a beginning address of an address range under test; initializing a read error detection code in response to a read access to the electronic memory at the location at the beginning address of the address range under test; updating the write error detection code in response to each write access to the electronic memory at a location within the address range under test, such that a final value of the write error detection code is a cyclic redundancy check (CRC) value of data written to the electronic memory at each location within the address range under test; updating the read error detection code in response to each read access to the electronic memory at a location within the address range under test, such that a final value of the read error detection code is a CRC value of data read from the electronic memory at each location within the address range under test; comparing the final value of the write error detection code to the final value of the read error detection code to determine if the electronic memory has a fault; and generating an error signal if the electronic memory has a fault.