1. An apparatus, comprising: one or more processors supporting a system management mode, system management memory, and software controllable caching of memory; one or more memory modules; a memory controller; a communication bus to couple the one or more memory modules to the memory controller; and logic to: detect whether a system management memory module is in a visible state; in response to a determination that system management memory is in a visible state, direct system management memory input/output operations to the system management memory module; and in response to a determination that system management memory is in an invisible state, direct system management memory cache write back operations to the system management memory module and directing other system management memory input/output operations to another location in system memory.