1. A method of functionally testing a memory having a plurality of addressable cells, comprising the steps of: (a) writing a pseudorandom sequence of bits into a predetermined number of consecutively-addressed memory cells to provide a reference block; (b) replicating said reference block by iteratively reading said pseudorandom sequence of bits and writing said bits into next successive blocks in a first direction until all of the memory cells are written. (c) complementing the contents of said reference block; (d) again replicating said reference block by iteratively reading complemented bits of said pseudorandom sequence and writing said complemented bits into next successive blocks in said first direction until all of the memory cells are written; (e) sequentially reading each cell in a second direction opposite said first direction, complementing the data therein, and writing said complemented data back into said cell; (f) again reading each cell in said first direction and comparing said complemented data with said pseudorandom sequence of bits to detect differences, and, in response, (g) identifying any memory faults.