1. A method for performing a built-in and at-speed test in a system-on-chip comprising following steps: (a) receiving a statistic timing analysis report of the system-on-chip; (b) determining a plurality of critical paths for an at-speed test in the system-on-chip according to the statistic timing analysis report; (c) analyzing signals at observe control points and capture control points of each of the critical paths for generating a plurality of test states; and (d) transmitting the test states to a virtual instrumentation software architecture wrapper.