1. A device to generate n-valued symbols, each n-valued symbol having one of n values with n=2 p and p>1 and being represented by a signal, comprising: an n-valued shift register with feedback, including a plurality of shift register elements and a memory implementing an n-valued logic feedback function; the memory having a first input and a second input, the memory storing a single non-commutative n-valued truth table implementing the n-valued logic feedback function, which is an addition over an n-valued finite field that is modified by an n-valued inverter, the memory being connected to the n-valued shift register with feedback, wherein the first input and the second input each are enabled to receive an n-valued symbol provided by a shift register element of the n-valued shift register that determine a symbol in the single non-commutative n-valued truth table as an output symbol of the n-valued logic feedback function; an output of the shift register with feedback to provide an n-valued symbol, wherein the device is selected from the group consisting of: scrambler, descrambler, sequence generator, generator of symbols of an error correction code, and a Cyclic Redundancy Check (CRC) coder.