1. A method of managing a memory array within a processing system, said method comprising: counting accesses to each page of data locations of said memory array from a memory controller managing said accesses, wherein said memory array is a common level of system memory comprising multiple memory device ranks; determining whether or not pages stored in a first portion of said memory array are accessed less frequently than pages stored in a second portion of said memory array, wherein said first portion and said second portion of said memory array correspond to separate sets of physical memory devices that are independently power-managed; responsive to said determining, relocating data stored in less frequently accessed locations of a first portion of said memory array to a second portion of said memory array; further responsive to said determining, relocating data stored in more frequently accessed locations of a second portion of said memory array to a first portion of said memory array; and setting power management states of said first portion of said memory array and said second portion of said memory array in conformity with a frequency of accesses to said corresponding portion of said memory array.