1. An apparatus, comprising: a plurality of cores, each core including at least one respective core memory location, wherein the plurality of cores is configured to process a plurality of instructions while running in a normal operating mode in which access to the respective core memory locations of other cores of the plurality of cores is prevented; an inter-processor bus coupled to the plurality of cores; and circuitry coupled to the plurality of cores, wherein the circuitry is configured to: detect that a first core of the plurality of cores has stopped committing a subset of the plurality of instructions; and send an indication to a second core of the plurality of cores that the first core has stopped committing the subset of the plurality of instructions; wherein the second core is configured to: switch from the normal operating mode to a privileged operating mode in response to receiving the indication, wherein the privileged operating mode allows the second core to access the at least one respective core memory location in the first core using the inter-processor bus; disable the first core from further processing instructions of the subset of the plurality of instructions in response to the switch to the privileged operating mode; and copy data, via the inter-processor bus, from the at least one respective core memory location in the first core to the at least one respective core memory location in a third core of the plurality of cores in response to disabling the first core; and wherein the third core is configured to resume processing the subset of the plurality of instructions dependent upon the data.