1. A pattern generator, comprising: an address generator adapted to provide a first address having a plurality of address bits; an address topology generator including a first plurality of programmable logic gates, each programmable logic gate of the first plurality coupled to receive at least a subset of the plurality of address bits, the first plurality of programmable logic gates generating a second address having a plurality of modified address bits; and a data topology generator adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits.