1. An integrated circuit comprising a multiplication function configured to execute a multiplication of at least two binary words x and y in a plurality of basic multiplication steps of components xi of word x by components yj of word y, i and j being iteration variables, wherein in at least some of the multiplication steps i does not equal j, and wherein the multiplication function is further configured to execute two successive multiplications of binary words x and y by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed.