1. An electrostatic discharge (ESD) protection optimizer for an integrated circuit (IC), comprising: a circuit analyzer configured to identify ESD cells and circuitry of said IC by comparing component information of said IC with predefined ESD protection elements and predefined circuit topologies; and an ESD resistance determiner configured to calculate a resistance value to couple in series with said circuitry, said resistance value based on protection cell physical attributes associated with said identified ESD cells and circuitry physical attributes associated with said identified circuitry.