1. A device comprising: a processor operable to execute a shader compiler, wherein the shader compiler comprises: a decoder operable to translate a vector instruction to an instruction having a unified instruction representation; one or more components operable to process the instruction having the unified instruction representation using the unified instruction representation to generate a processed instruction, the processed instruction having the unified instruction representation; and an encoder operable to translate the processed instruction having the unified instruction representation to a processor executable instruction, wherein the unified instruction representation includes both vector and scalar attributes wherein the attributes of the unified instruction representation include at least one attribute common to both the vector instructions and scalar instructions.