1. A tool for designing checker circuitry, the tool comprising: an assertion unit for entering assertions corresponding to an expected behavior of at least a portion of a circuit, the assertion unit relying on Boolean expressions; an automata unit for generating automata, each automaton corresponding to at least a portion of one of the assertions, the automata unit using a symbolic alphabet to represent the assertions, the automata unit adapting automata algorithms to support the symbolic alphabet in the generated automata; and a checker generator for designing checker circuitry corresponding to each of the automata for the at least one portion of the circuit.