1. In a microprocessor system comprising a processor, a cache memory, and a main memory, a method for obtaining and processing an instruction comprising the steps of: said processor coupling a request for an instruction to said cache memory; said cache memory responsively coupling a cache word and cache tag to said processor; said processor pre-decoding said cache word, while concurrently, determining whether said request to said cache memory has resulted in a cache hit or miss wherein said cache tag is utilized to make this determination; said processor decoding said cache word; if said request to said cache memory has resulted in a cache hit, said processor executing said cache word as a valid instruction; if said request to said cache memory has resulted in a cache miss, said processor canceling the execution of said cache word as an invalid instruction and coupling a request for said instruction to said main memory.