1. A computer-implemented method performed by a processor, the method comprising: obtaining an arbiter design to be formally verified, wherein the arbiter design is based on an original arbiter design comprising a fairness logic and an arbitration logic, wherein the arbiter design comprising the arbitration logic and a portion of the fairness logic; generating, using the portion of the fairness logic, values to be provided as input to the arbitration logic; monitoring the values generated using the portion of the fairness logic and provided as input to the arbitration logic to allow detection of a multi-dimensional Complete Random Sequence (CRS) having two or more dimensions, wherein each dimension corresponds to a different sequence of the values being monitored; and, performing formal verification of the arbiter design, wherein the formal verification is performed to verify a property is held by the arbiter design with respect to a bounded or unbounded fairness condition which is based on the multi-dimensional CRS, whereby the arbitration logic is formally verified independently of the fairness logic.