1. A microprocessor, operatively coupled via a bus to a memory, the microprocessor comprising: a cache memory; and a grabline instruction, that specifies a memory address that implicates a cache line of the memory, wherein the grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line; wherein the microprocessor is configured to forego initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception.