1. A computer system comprising a main memory, means for providing an LDA macrocode instruction, and a CPU having a plurality of accumulators and microinstruction logic for generating a microcode control word for causing the transfer of a word in main memory to an accumulator of the CPU, said microinstruction logic generating one of a plurality of address words from portions of said LDA macrocode instructions, said logic having a microcode control word generator comprising a plurality of banks of control memories, and said logic having means for applying portions of the bits of said address words to the input of said banks of said memories and said logic having means responsive to at least one bit of said generated address words for selectively enabling one bank of said plurality of banks of said memories to produce a microcode control word.