1. A device comprising: a nonvolatile memory, wherein the nonvolatile memory is configured to store a set of bits; and a controller coupled to the nonvolatile memory, the controller comprising a decoder to perform a decoding operation based on the set of bits and based on a parity check matrix that includes a block row having a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix by at least a threshold number of null sub-matrices, the decoder comprising: a first check node unit (CNU) stage; a variable node unit (VNU) stage coupled to an output of the first CNU stage; a first shifter coupled to an output of the VNU stage; a second shifter coupled to a first memory and to an input of the VNU stage, the first memory configured to store log-likelihood ratio (LLR) information; and a second CNU stage coupled to an output of the first shifter and coupled to a second memory configured to store check node message information.