1. A method comprising: compiling a representation of a circuit, the circuit including a replicated portion and delay logic to delay inputs into the replicated portion; selecting one or more triggering signals; setting one or more states for each selected triggering signal to setup a trigger condition; and generating, by one or more processors, a test based on recorded data that includes one or more states of one or more registers in the replicated portion of the circuit and a sequence of inputs that led to the trigger condition when the trigger condition occurs, the test including the recorded states of the registers and the sequence of inputs that led to the trigger condition.