1. A computer implemented method for implementing multi-power domain digital or mixed-signal verification and low power simulation of an electronic circuit design, comprising: using a computer system to perform a process, the process comprising: identifying one or more schematics of the electronic circuit design; generating one or more net or terminal sets or one or more overriding net or terminal sets for the one or more schematics of the electronic circuit design by at least referencing a power data file for the electronic circuit design, wherein the power data file for the electronic circuit design includes a specification of one or more power-saving techniques and data or information for power intent for at least a portion of the electronic circuit design to provide portability of the power intent across multiple electronic circuit design tools; and performing verification or simulation of the electronic circuit design by using at least the one or more net or terminal sets or the one or more overriding net or terminal sets.