1. Conditional control apparatus for a digital computer capable of executing a plurality of instructions, said computer operating in computer cycles during which instruction fetching is overlapped with instruction execution without wasting computer cycles in effecting the overlapped operation, comprising storage means for storing a plurality of instruction words each having first and second next address control fields and first and second function control fields, fetching means for fetching an instruction word from said storage means during each computer cycle, decision logic means for providing first and second decision signals in accordance with conditions generated within said computer, said fetching means being responsive to said first and second next address control fields of an instruction word fetched in a computer cycle previous to the current computer cycle and to said first decision signal for selecting said first or second next address control field in accordance with said first decision signal and fetching, in said current computer cycle, the next instruction word from said storage means in accordance with the next address control field selected by said first decision signal, and processor means for executing operations designated by said function control fields, said processor means being responsive to said first and second function control fields of said instruction word fetched in said previous computer cycle and to said second decision signal for selecting said first or second function control field in accordance with said second decision signal and executing, in said current computer cycle, the operation designated by the function control field selected by said second decision signal, said decision logic means providing said first and second decision signals for use in said current computer cycle in accordance with conditions generated within said computer in response to execution by said computer, in said previous computer cycle, of an instruction word fetched during a computer cycle occurring before said previous computer cycle, whereby said fetching of said next instruction word is overlapped with said execution of said operation without wasting computer cycles in effecting said overlapped operation.