1. A computer-implemented method for reducing logic and delay within a logic structure, the method comprising: searching logic structures to be analyzed; finding a plurality of latches within a logic structure to be analyzed; determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed; determining if there is at least one remaining latch to be analyzed; determining whether inverters are disposed within an input path and an output path of the at least one remaining latch; obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found; modifying the logic functions using DeMorgan's Theorems; determining whether timing violations exist with the modified logic functions; and annotating hardware description language based on the modified logic functions when no timing violations exist.