1. A processor comprising: a destination register to store a plurality of data elements; a source register to store a plurality of index values, each of which corresponds to one of the plurality of data elements; a base address register to store a base address; a mask register to store mask values, each mask value corresponding to one of the plurality of data elements; a decoder to decode a vector gather instruction, the vector gather instruction having a scale field to specify a common scaling factor to be applied to the index values; and execution circuitry coupled to the decoder, the execution circuitry to perform operations associated with the vector gather instruction, the operations comprising conditionally accessing, based on corresponding mask values, one or more of the plurality of data elements and storing the one or more of the plurality of data elements in the destination register; wherein the execution circuitry is to scale the index values in accordance with the scale field to generate a corresponding plurality of scaled index values, and add the base address to each of the scaled index values to generate a corresponding plurality of non-contiguous system memory addresses for the data elements to be accessed and stored in the destination register.