1. A processor comprising: one or more vector registers each comprising a first plurality of data fields to store values of vector elements; a decode stage to decode a first instruction specifying: a first operand of the one or more vector registers, a size of the vector elements, a portion of the first plurality of data fields, a second operand of the one or more vector registers, and a third operand; and an execution unit, responsive to the decoded first instruction and for each data field of the portion of the first plurality of data fields, to: read a first, a second and a third value respectively from corresponding data fields of the size of vector elements in the first, the second and the third operand; and compute in parallel an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.