1. An integrated semiconductor memory comprising: a plurality of memory cells; first lines and second lines that can be used to actuate the memory cells; and a plurality of devices, each device within a path of one of the first lines, the devices permitting exclusive actuation of memory cells in a region of just a first subsection of the first line and electrically decouples a second subsection of the respective first line, wherein the devices can be set in a state permitting, without intervening switching or other manipulating of the device, memory cells to be actuated either within a respective first, relatively short access time exclusively in the region of the first subsection of the first lines; or alternatively within a respective second, relatively long access time in the region of the first subsections and also of the second subsections of the first lines, depending on the respective access time chosen.