1. A computer-implemented method for analyzing electrical power in a circuit, wherein the circuit comprises a plurality of circuit cells and a plurality of circuit wires, wherein a source netlist includes a plurality of circuit nodes and a plurality circuit edges, wherein each circuit node included in the source netlist corresponds to a circuit cell included in the circuit, wherein each circuit edge included in the source netlist corresponds to a wire included in the circuit, and wherein the method comprises: forming a compressed circuit node that combines a first circuit node and at least one second circuit node, wherein the first circuit node and the at least one second circuit node are included in the plurality of circuit nodes included in the source netlist, and wherein the forming the compressed circuit node is based, at least in part, on the first circuit node and the at least one second circuit node having a node equivalence; forming a first compressed circuit edge that combines a first circuit edge and at least one second circuit edge, wherein the first circuit edge and the at least one second circuit edge are included in the plurality of circuit edges included in the source netlist, and wherein the forming the first compressed circuit edge is based, at least in part, on the first circuit edge and the at least one second circuit edge having an edge equivalence; forming a reduced netlist, wherein the reduced netlist includes a first subset of the plurality of circuit nodes included in the source netlist and a second subset of the plurality of circuit edges included in the source netlist, wherein the reduced netlist includes the compressed circuit node in substitution for the first circuit node and the at least one second circuit node, and wherein the reduced netlist includes the first compressed circuit edge in substitution for the first circuit edge and the at least one second circuit edge; associating with the compressed circuit node, in the reduced netlist, a lumped node metric that combines a node metric associated with each of the first circuit node and the at least one second circuit node; associating with the first compressed circuit edge, in the reduced netlist, a first lumped edge metric that combines a first edge metric associated with each of the first circuit edge and the at least one second circuit edge; and fabricating, based upon an improvement to the circuit due to a power analysis using the reduced netlist, a semiconductor circuit.