1. A computer-implemented method for legalizing a portion of a circuit layout, the method comprising: receiving a set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes; receiving a selection input from a user which identifies the portion of the circuit layout which is to be legalized; receiving a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints; and modifying the portion of the circuit layout to obtain a modified portion of the circuit layout which satisfies the set of design constraints and at least a subset of the set of technology constraints.