1. A hardware processor comprising: a decode circuit to decode an instruction comprising a state operand, a source vector operand, a destination vector operand, and a control operand; and an execution circuit to execute the instruction to: convert elements from the source vector operand in a first encoding format to a second encoding format, store the elements in the second encoding format in the destination vector operand, store a total length of the elements in the second encoding format in the state operand, and set a stream completion indication in the control operand when the elements from the source vector operand are last elements in a data stream.