1. An apparatus comprising: a first field conversion circuit to convert each of a plurality of 16 byte values of a block, respectively, from a first corresponding polynomial representation in GF(256) to a second corresponding polynomial representation in GF((2 2 ) 4 ); a multiplicative inverse circuit to compute for each of the second corresponding polynomial representations in GF((2 2 ) 4 ) of the 16 byte values, respectively, a corresponding multiplicative inverse polynomial representation in GF((2 2 ) 4 ); and a second field conversion circuit to convert each corresponding multiplicative inverse polynomial representation in GF((2 2 ) 4 ) and to apply an affine transformation by performing a multiplication of each corresponding multiplicative inverse polynomial representation with an 8-bit by 8-bit product matrix and a subsequent XOR with a constant byte value to generate, respectively, a third corresponding polynomial representation in GF(256) wherein the multiplication of each corresponding multiplicative inverse polynomial representation with an 8-bit by 8-bit product matrix and a subsequent XOR with a constant byte value is implemented by a series of XORs.