1. A computer-implemented method of testing a design for an instruction fetch unit (IFU) of a microprocessor, comprising: supplying a sequence of instruction addresses to an IFU model which represents the IFU design, wherein the instruction addresses correspond to program instructions provided by a memory hierarchy which is external to the IFU model; fetching one or more of the program instructions according to the instruction address sequence from the external memory hierarchy to the IFU model; detecting that a current state of the IFU model is a predetermined state of interest; automatically modifying the instruction address sequence responsive to said detecting to force a selected address to be fetched next by the IFU model s wherein the selected address is specifically based on the predetermined state of interest; and fetching a program instruction corresponding to the selected address from the external memory hierarchy to the IFU model.