1. A method of testing an integrated circuit comprising a core and a plurality of memory cells having outputs and inputs which are alternately connected to inputs and outputs of the core, said core being provided with a clock input intended to receive a first clock signal in a standard mode of operation, each memory cell being identified by an address and provided with a clock input intended to receive a second clock signal in a test mode, said clock input of the core being subjected to a conditional inhibition in the test mode, which method comprises the following steps: configuration of the circuit in the test mode, selection of a so-called virtual address, which does not correspond to any memory cell, canceling the inhibition of the clock input of the core for a predetermined period of time following said selection.