1. A method, comprising: generating, using a processor, a register transfer level description of a first kernel of a heterogeneous, multiprocessor design; integrating the register transfer level description of the first kernel with a base platform circuit design providing a static region within a programmable integrated circuit that provides an interface to a host of the heterogeneous, multiprocessor design; generating, from the register transfer level description of the first kernel and using the processor, a first configuration bitstream specifying a hardware implementation of the first kernel and supporting data for the configuration bitstream; and including the first configuration bitstream and the supporting data within a binary container.