1. A fault tolerant computer system comprising: a meta processor running an algorithm; a plurality of slave processors; a slave processor switch in communication with the meta processor and controlled by the algorithm to selectively assign operating systems, and application processes and threads to the slave processors; a plurality of memory devices; a memory switch in communication with the meta processor and controlled by the algorithm to provide data communication between selected slave processors and selected memory devices over selected memory ranges; an I/O switch in communication with the meta processor and controlled by the algorithm to provide data communication between selected slave processors and selected I/O devices; and all system and I/O interrupts being communicated to the meta processor and handled by the algorithm.