1. A processor arrangement, comprising: a first processor; a plurality of second processors, each second processor comprising a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor comprises a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor, wherein the first processor comprises a bit-mask generator, wherein the bit-mask generator comprises a plurality of shift registers configured to generate the processor-specific bit-mask sequences of the second processors; wherein one shift register of the plurality of shift registers is configured to generate a processor-specific bit-mask sequence specific to one second processor of the plurality of second processors.