1. A method of reducing interconnection delays associated with a Viterbi-decoder, the method comprising the steps of: providing a plurality of branch metric computation units (BMCUs) and at least one add-compare-select unit (ACSU) having a plurality of cells; connecting a first BMCU selected from the plurality of BMCUs to a first group of ACSU cells selected from the plurality of ACSU cells; and connecting a second BMCU selected from the plurality of BMCUs to a second group of ACSU cells selected from the plurality of ACSU cells.