1. An apparatus comprising: (a) H hardware contexts, each of which is capable of storing the execution state of one thread in a multi-threaded processor; and (b) a context controller for: (i) activating each of A hardware contexts, wherein each of said A active hardware contexts has a priority, (ii) maintaining the E highest priority of said A active hardware contexts as executing hardware contexts, wherein E equals the lesser of A and C, and wherein C equals the maximum number of concurrently executing hardware contexts in said multi-threaded processor, and (iii) initiating a context switch in said multi-threaded processor among said E executing hardware contexts on a time-sequenced basis; wherein C and H are positive integers and 2<C<H; and wherein A and E are non-negative integers and and E≦A≦H.