1. A computer-implemented method for performing formal verification of a circuit in view of low power design specification, the method comprising: receiving, by a computer processor, a request to perform formal verification of connectivity of a circuit representing an input/output ring of a system on chip, the circuit represented by a circuit design, the circuit comprising components and connections between components; receiving, by the computer processor, low power design specification for the circuit, the low power design specification describing power states for one or more power domains of the circuit; modifying, by the computer processor, the circuit design by introducing one or more isolation cells based on the low power design specification; generating, by the computer processor, combinational constraints based on the low power design specification, the combinational constraints representing valid power states of power domains of the circuit based on the low power design specification; receiving, by the computer processor, a set of assertions representing connectivity between components of the circuit, wherein a result of evaluation of an assertion is based on whether a component is connected to another component; performing, by the computer processor, formal verification of the modified circuit design based on the set of assertions representing connectivity between components of the circuit and the combinational constraints based on low power design specification; and determining, by the computer processor, whether the circuit has valid connectivity in view of the low power design specification based on the result of the formal verification, the result of the formal verification based on values of the assertions representing connectivity between components of the circuit.