1. A processing system comprising: a first interconnect of a first data processor to communicate information between a portion of the first data processor and a first memory; a first debug module, of the first data processor, coupled to the first interconnect, the first debug module comprising: a first trace buffer to store data trace information of the first memory that meets a first data trace criteria of the first debug module; a first data trace filter module coupled to the first trace buffer to filter out data trace information stored at the first trace buffer that does not meet a second data trace criteria; a second interconnect of a second data processor to communicate information between portions of the second data processor a second memory; and a second debug module, of the second data processor, coupled to the second interconnect, the second debug module comprising: a second trace buffer to store data trace information of the second memory that meets a third data trace criteria of the second debug module; and a second data trace filter module coupled to the second trace buffer to filter out data trace information stored at the second trace buffer that does not meet a fourth data trace criteria.