1. An electronic device comprising: a processor having an execution pipeline and capable of executing at a plurality of performance states; a processing circuit independent of the processor; and machine readable instructions executable on the processing circuit to: monitor at least one metric relating to events of the execution pipeline of the processor, wherein the at least one metric is derived from a count of events of the execution pipeline, the events including instructions that have been retired by the execution pipeline in a given time interval; determine a current utilization of the processor based on the monitored at least one metric; and according to the determined utilization, cause the processor to transition from a first of the plurality of performance states to a second of the plurality of performance states.