1. A processor, comprising: an instruction cache to store instructions; a plurality of processing cores in a single chip package; wherein each processing core, of the plurality of processing cores, is to support simultaneous multithreading, and wherein each processing core further comprises: an instruction fetch logic to fetch one or more instructions; an instruction decode logic to decode the one or more instructions; a first logic to cause the plurality of processing cores to appear as multiple logical processors, and to identify a set of the multiple logical processors to execute each instruction; and a second logic to transfer the processing of a thread of instructions from a first set of the logical processors to a second set of the logical processors.