1. A memory cell, comprising: a programmable solid state electrolyte layer configured to represent a logical state according to a resistance of the programmable solid state electrolyte layer; a writing line; a selecting line; and a controllable switch arranged between the solid state electrolyte layer and the writing line, and connected to the selecting line; wherein the controllable switch is controlled, at least in part, by application of a voltage on the selected line; wherein the switch comprises a limiting element that limits a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.