1. A structure of processor having a plurality of main processors and sub processors comprising: a plurality of main processors which process programs by receiving instructions and data from an external memory, each of said main processors comprises: an instruction cache/memory management unit which stores instructions which are inputted from said external memory, an instruction fetching/checking unit which fetches instructions from said instruction cache/memory management unit and checks whether said instructions are for a main processor or a sub processor, an instruction decoding unit which converts said instruction to a form of internal informality, a main processor instruction issue unit which allocates registers and execution units so that said instructions converted into a form of internal information are executed, a register file which stores data necessary for execution of said instructions, a plurality of execution units which execute operations according to information received from said main processor instruction issue unit, and a storing/fetching unit which stores or fetches external data; a plurality of sub processors which process said instructions received from said main processors in parallel with said main processors, each of said processor comprises: an instruction queue which stores temporarily instructions fetched from said main processor for a sub processor, a sub processor issuing unit which selects instructions that can be processed simultaneously by checking said instruction queue, a plurality of register files which stores data necessary for said instructions, a plurality of said register files which is equal in number to the number of said main processors, and a plurality of sub processor execution units which execute operations according to information of said instructions; and an internal connecting network which connects said main processors and said sub processors.