1. A programmable logic element, comprising a P-type ferroelectric transistor element having a first gate terminal and first and second channel terminals; and an N-type ferroelectric transistor element having a second gate terminal and third and fourth channel terminals, wherein said first gate terminal, said first channel terminal and said second channel terminal of said P-type ferroelectric transistor are electrically connected in parallel with said second gate terminal, said third channel terminal and said fourth channel terminal of said N-type ferroelectric transistor element, respectively, and wherein a first threshold voltage of said P-type ferroelectric transistor element and a second threshold voltage of said N-type ferroelectric transistor element are substantially symmetric to each other in a non-polarized state.