1. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising: a floating body memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with said floating body region; said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type; a second transistor connected to said second region of said floating body memory cell; and a third transistor connected to said second transistor.