1. A method for analyzing a timing design of an integrated circuit and operable by a computing processor, the method comprising: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability by a computer processor for the timing path based on a joint probability distribution of at least one statistically independent parameter analyzing the timing design based on the integrated slack path variability; and determining a sensitivity of the timing path to each of the at least one statistically independent parameter, the sensitivity being determined based on a probability distribution of the statistically independent parameter wherein the sensitivity to the statistically independent parameter is determined approximately using formula: 
 S= ( P b −P w )/(σ b −σ w ), where S indicates the sensitivity, P b indicates a slack under a best corner of the statistically independent parameter, and P w indicates a slack under a worst corner of the statistically independent parameter, and σ b and σ w indicate numbers of sigma points of distribution limits at the best and worst corners of the statistically independent parameter, respectively.