1. A decoder comprising: a memory configured to store an input value having an integer part and a fractional part; and mapping circuitry coupled to the memory and configured to calculate a floating point number having an exponent value mapped from the integer part by inserting the inter part into an exponent field of the floating point number to generate the exponent value and further having a significand value mapped from the fractional part by inserting the fractional part into a significand field of the floating point number to generate the significand value.