1. A logic circuit for delaying a signal input thereto specified number of clock cycles X, wherein X is between 1 and 2 N, the logic circuit comprising: a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2 N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each the M inputs is connected to one of the clocked registers.