1. A host controller for controlling a device connected to a host, comprising: a first bus interface coupled to a system bus; a processor which determines whether data received from a system memory via the first bus interface are descriptor data; and a descriptor tracer which receives and stores the descriptor data transmitted to the processor, wherein the host comprises the system bus and the system memory, wherein the descriptor tracer comprises: a memory which stores the descriptor data; and a second bus interface which allows a central processing unit (CPU) to directly access the memory without passing through the system bus so that the CPU can determine whether the host controller operates normally, wherein the descriptor data is directly transmitted to the descriptor tracer from the system bus without passing through the first bus interface.