1. A high-speed processor system, comprising: a CPU having a primary cache memory; a secondary cache memory arranged on a hierarchical level lower than that of said CPU, said secondary cache memory having a first MPU; and a plurality of main memories connected to said secondary cache memory and arranged in parallel with one another, each of said main memories having a tertiary cache memory provided with a second MPU; wherein each of said first MPU and said second MPUs has both a cache logic function and a processor function, thereby enabling distributed concurrent processing.