1. A processor comprising: a cache hierarchy including at least a first level-1 cache and a higher-level cache; wherein the processor is configured to: map a first portion of a physical memory space to a first portion of the higher-level cache; execute instructions, at least some of which comprise microcode; decode a first instruction of the instructions; wherein if a microcode access signal is detected responsive to said decode of the first instruction, determine the first instruction represents microcode and allow the first instruction to access the first portion of the higher-level cache; and wherein if a microcode access signal is not detected responsive to said decode of the first instruction, determine the first instruction does not represent microcode and prevent the first instruction from accessing the first portion of the higher-level cache.