1. A computer system, comprising a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory comprising a plurality of portions each of which is associated with one of the processing nodes, each processing node comprising a processor, a memory controller for controlling access to the associated portion of the system memory, and a host bridge for facilitating communication with a plurality of I/O devices, the first point-to-point architecture being operable to facilitate first transactions between the processors and the system memory, the computer system further comprising at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges, wherein the at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.