1. A memory control apparatus comprising: reception means for receiving a memory access request from a plurality of request sources for requesting an access to a memory; division means for dividing the received memory access request into a plurality of commands, wherein a unit of data transfer of each of the plurality of commands is smaller than a unit of data transfer of the memory access request, and wherein the number of commands of the plurality of commands is determined in accordance with the unit of data transfer of the plurality of commands and the unit of data transfer of the memory access request; issue means for issuing each command of the plurality of commands obtained by the division means in alternate order for each of the plurality of request sources, wherein one command of a first plurality of commands obtained from said division means in response to a first memory access request from a first one of the plurality of request source is issued to the memory between issuance of two commands of a second plurality of commands obtained by said division means in response to a second memory access request from a second one of the plurality of request sources, in a case where plural memory access read requests are received from the plurality of request sources; and return means for returning one piece of data obtained from the memory to the first one of the plurality of request sources in response to the one command of the first plurality of commands obtained by said division means in response to the first memory access request, wherein the one piece of data is returned between returning of two pieces of data obtained from the memory in response to each of the two commands of the second plurality of commands obtained by said division means in response to the second memory access request, wherein the plurality of memory access requests are processed by time division and concurrently.