1. A microprocessor, comprising: a register set, defined by an instruction set architecture of the microprocessor; a cache memory; a superscalar pipelined architecture including a plurality of execution units; and a store unit, coupled to the cache memory, wherein the store unit is distinct from the other execution units of the microprocessor and includes an arithmetic/logic unit (ALU) in which the store unit and the ALU are not separated by a register; wherein the store unit is configured to receive a single instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result; wherein the store unit is configured to read the source operand from the source register and to provide the source operand directly to the ALU without sending the source operand to any of the other execution units of the microprocessor and without registering the source operand before being provided to the ALU; wherein the ALU is configured to perform the operation on the source operand to generate the result; and wherein the store unit is further configured to operatively write the result to the cache memory.