1. A circuit arrangement for an electronic system for time-delayed outputting of a switching signal, comprising: a first timer, adapted to convert an input signal to a first time-delayed output signal; a second timer, adapted to convert the input signal to a second time-delayed output signal, wherein the second timer is redundant with respect to the first timer; a common actuating element for the input signal for both the first and the second timers; and a control unit, for each timer, for computational and measurement determination of the time delay, which is predetermined by use of the actuating element, and for processing of a time delay which is relevant for the outputting of the switching signal.