1. A memory device, comprising: a bit line; a source line; a resistive memory element having a number of resistance states; a switching device coupled in series with the resistive memory element between the bit line and the source line; a word line arranged to control the switching device; and a write pulse generator and read sensing logic coupled between the bit line and source line, wherein the source line is selectably coupled to an intermediate potential of a voltage source powering at least one of the write pulse generator and read sensing logic.