1. A multi-core microprocessor that supports a plurality of operating states representing different levels of performance and power consumption, the microprocessor comprising: a plurality of cores; a control unit configured to put selected cores into selected operating states at selected times; and for each core, a synchronization register external to that core, specific to that core, and readable by the control unit; wherein each core is configured to respond to an instruction to target an operating state by writing a value identifying the target operating state to its synchronization register; wherein the control unit is configured to help the cores work cooperatively to cause a power saving action that affects a shared resource provided that the action does not reduce performance of any core sharing that resource below its target operating state; wherein the control unit is configured to refrain from performing a power-saving action that affects a shared resource until all of the cores sharing that resource have written values identifying a consistent target operating state to their synchronization registers, wherein a core's target operating state is consistent with the power saving action if the power saving action would not reduce performance of the core below its target operating state; wherein the control unit is configured to cause individual cores to enter a sleep state while waiting for other cores sharing the resource to write values identifying target operating states that are consistent with the power-saving action; wherein the control unit is configured to wake only a selected one of the cores sharing the shared resource, when all cores sharing that resource have written values identifying target operating states that are consistent with the power-saving action; and wherein in response to being awaken, the selected core communicates with a chipset to disable the shared resource.