1. A processor for executing operations in a pipeline system, comprising: a plurality of operand registers, each identified by a register number; a pipelined arithmetic unit having inputs and a plurality of operational stages; a plurality of data buses connected between outputs of said operational stages of said arithmetic unit and said inputs of said arithmetic unit, said data buses transferring operand inputs to said arithmetic unit; a selector for selecting either an output from said plurality of operand registers or said outputs of said operational stages as operand inputs to the arithmetic unit; a generator for generating an operand determination signal indicating that an output from said plurality of operational stages of the arithmetic unit has been determined as write-in data for an operand register corresponding to a stage of the arithmetic unit; a circuit for transmitting and circulating a register number given for said operand register whose renewal is specified by a given instruction and a command to renew the operand register corresponding to said stage of the arithmetic unit; and a control circuit responsive to at least said register number and said operand determination signal for controlling said selector so as to select at least one of said operand registers when at least one operand for the instruction is held in said at least one operand register, to select said arithmetic unit when said operand for the instruction has already been determined in said arithmetic unit, and to select said arithmetic unit after said operand for the instruction has been determined unless said operand for the instruction is determined, so that said operand for the instruction is supplied to the arithmetic unit.