1. An apparatus comprising: a microprocessor core; a hardware accelerator including a configuration register and configurable by contents of the configuration register to apply a predetermined signal processing function upon input operand data; and a configuration controller comprising a predetermined data-structure specification and a configuration model, the predetermined data-structure specification including one or more data structures, the configuration model including one or more structural details of the configuration register, and the configuration controller being responsive to a notification from the microprocessor core to configure the contents of the configuration register of the hardware accelerator by a translation of configuration data from a first format associated with the predetermined data-structure specification to a second format associated with the configuration model.