1. A collector for a synchronous central processing unit (CPU) of a data processing system having program addressable registers, a memory, said CPU having a repertoire of instructions and a plurality of execution units, wherein each of said execution unit executes a different subset of the repertoire of instructions independently of and in parallel with the other execution units and each executes the instructions in the order in which instructions are received by each such execution unit, said CPU having means for issuing in program order instructions to the collector and to the execution unit capable of executing the issued instruction; each execution unit that executes any instructions that requires more than one clock period having associated with it an input stack for storing instructions awaiting execution by its associated execution unit in the order received, the number of clock periods required to execute each instruction differing such that the results of the execution of instructions of a given program by the instruction execution units are not produced in program order; the collector comprising: means for storing in program order instructions issued by the means for issuing instructions to the collector; result means associated with each of said execution units for storing a plurality of results of the execution of instructions by its associated execution unit in the order executed; a master safe store and a store stack for storing the results in program order of the execution of each instruction executed by the execution units; and collector control means responsive to the order in which instructions are stored in the means for storing in program order instructions for causing results stored in the result means associated with each execution unit to be stored in program order in the master safe store if the results change the contents of an addressable register and to be stored in the store stack in program order if the results are to be written into memory.