1. A data processing apparatus, comprising: main processing logic operable to execute a sequence of instructions in order to perform a process; subsidiary processing logic operable to perform at least part of said process on behalf of the main processing logic; a memory accessible by the main processing logic when performing said process, the main processing logic being operable to define a portion of said memory to be allocated memory accessible to the subsidiary processing logic when performing said at least part of said process; a memory management unit programmable by the main processing logic and operable to control access to the allocated memory by the subsidiary processing logic, the main processing logic being operable to program the memory management unit such that for an access request issued by the subsidiary processing logic relating to the allocated memory, the memory management unit is operable to produce a memory address and one or more associated memory attributes identifying one or more properties of the allocated memory at that memory address.