1. A translation-lookaside buffer (TLB), comprising: a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector; wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID); an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries; and logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector.