1. In a systolic array system utilizing a plurality of semiconductor chips, a semiconductor chip comprising: a plurality of processing elements each including a floating-point serial processor and a plurality of data storage registers; global bus means coupled to the serial processor of each of said plurality of processing elements for inputing and outputing data to and from each chip and for programming each serial processor; a plurality of data buses coupled to each of the plurality of data storage registers of each of said plurality of processing elements; and said global bus means being coupled to said plurality of data storage registers for programming said data storage registers.