1. A computer system comprising: a microprocessor including a reorder buffer coupled to receive a first source operand specifier corresponding to a dispatchable instruction, and wherein said reorder buffer is configured to detect a dependency between said dispatchable instruction and a first instruction represented within said reorder buffer by a first destination operand specifier and a corresponding first last in buffer indication responsive to: (i) a match between said first source operand specifier and said first destination operand specifier corresponding to said first instruction, and (ii) said first last in buffer indication indicating that said first instruction is last, in program order, among the instructions represented within said reorder buffer to update a storage location defined by said first destination operand specifier; a bus bridge coupled to said microprocessor; and an input/output (I/O) device coupled to said bus bridge, wherein said I/O device is configured to communicate between said computer system and another computer system coupled to said I/O device.