1. A signal processor for processing an analog input signal, the processor comprising: a signal sampling circuit configured to produce a sample set of analog data values corresponding to the amplitude of the analog input signal at various times; a filter coefficient array including plural filter coefficients, the plural filter coefficients being divided into at least two different filter coefficient subsets, each subset having a predetermined number N of filter coefficients, wherein said predetermined number N is selected based upon a desired output rate; a total of N multipliers operatively connected to the signal sampling circuit and the filter coefficient array and configured to: 1) mulitply N analog data values from the sample set by respective N values from a selected one of the filter coefficient subsets to generate a first set of N intermediate values; and 2) multiply N analog data values from the sample set by respective filter coefficients from a different selected one of the filter coefficient subsets to generate a second set of N intermediate values; and a summer circuit configured to sum the intermediate values for each selected filter coefficient subset, thereby providing output at said desired rate.