1. An apparatus, comprising: an execution unit; a fetch unit configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields; and a plurality of address generator units; wherein a first address generator unit of the plurality of address generator units is configured to perform a first arithmetic operation for a first thread of sub-instructions dependent upon a first field of the plurality of fields and store a result of the first arithmetic operation in a register; wherein a second address generator unit is configured to generate at least one address of a plurality of addresses, wherein each address of the plurality of addresses is dependent upon a respective field of the plurality of fields, wherein the apparatus is configured to use the at least one address to access one or more input operands for the execution unit for a second thread of sub-instructions; and wherein the apparatus is configured to use the result of the first arithmetic operation stored in the register to access one or more input operands for the execution unit for a sub-instruction in the first thread of sub-instructions in a subsequent multi-part instruction.