1. A system for executing instructions, the system comprising: a plurality of virtual cores of a processor coupled to receive instruction threads allocated by a scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein resources of each partitionable engine are operable to be partitioned to instantiate a virtual core with partitioned resources of other partitionable engines, wherein the instruction threads are executed using the partitionable engines in accordance with a virtual core execution mode; and a plurality of memory fragments coupled to the plurality of partitionable engines for providing data storage, wherein each of the plurality of memory fragments comprises an L1 cache and a load store buffer, wherein a global interconnect links each of the plurality of memory fragments to each of the plurality of partitionable engines and wherein each memory fragment comprises: a first arbiter operable to interface between a first plurality of ports and a second plurality of ports, wherein the first plurality of ports is operable to allow the global interconnect to access the first arbiter and wherein the second plurality of ports is operable to allow the first arbiter to access an associated load store buffer.