1. A method of developing a clock distribution network for an integrated circuit, the steps comprising: capturing sources of clock skew including timing mismatches between clock sinks; synthesizing a higher level behavioral description of the integrated circuit and said sources of clock skew to generate a 2D layout comprising a clock distribution network and combinational logic; separating said clock distribution network from said combinational logic and locating said clock distribution network to a first area of the integrated circuit; and floorplanning said combinational logic of said first area.