1. An instruction fetch control device supplying instructions to an instruction execution unit, comprising: a plurality of instruction buffers each storing an instruction string to be supplied to the instruction execution unit; a designation unit designating a first instruction buffer from which the instruction string is currently supplied to the instruction execution unit, and designating a second instruction buffer storing a subsequent instruction string of the instruction buffer, as the instruction string to be supplied next, an instruction fetch request unit searching for one nullified instruction buffer; and an instruction fetch control unit making the searched for one nullified instruction buffer valid, wherein after an instruction string stored in an instruction buffer corresponding to a first identifier has been supplied to the instruction execution unit, the instruction fetch control unit nullifies the instruction buffer, the instruction string is a sequence of one or more instructions which are stored at sequential addresses of an instruction storage unit from which the instruction string is fetched and stored in the instruction buffer; the subsequent instruction string of the instruction string in the first instruction buffer is fetched from an address of the instruction storage unit immediately following an address from which the instruction string in the first instruction buffer is fetched, and the instruction fetch control device dynamically configuring the instruction buffers to be used regardless of a frequency of branch predictions.