1. A neuromorphic integrated circuit comprising: an array of analog computational cells fabricated on an integrated-circuit-substrate, the analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells; and one or more nanowire-interconnect layers above the array of analog computational cells, each nanowire-interconnect layer including: a first sublayer of approximately parallel nanowires, each nanowire of the first sublayer connected to a single computational-cell pin of the first type, a memristive sublayer, and a second sublayer of approximately parallel nanowires, each nanowire of the second sublayer connected to a single computational-cell pin of the second type, the nanowires of the second sublayer oriented in a direction non-parallel to the direction of the nanowires of the first sublayer.