1. An integrated circuit including a memory module comprising: an even number of at least four memory banks, each memory bank having a plurality of memory cells, each two of the memory banks being alternately connected to a m-bit data bus, the memory banks being classified into two groups, each group comprising a memory bank of each memory bank region; and a selection device the selection device selecting one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups, m being equal to an integer multiple of i.