1. A method of waiving verification failures, comprising the steps of: (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, said circuit error files containing a plurality of circuit errors of said circuit designs; (B) generating a system error file by performing an additional physical verification on a system design, said system error file containing a plurality of system errors of said system design, said system design incorporating said circuit designs; (C) generating a valid error file by removing said circuit errors from said system error file, said valid error file containing a plurality of valid errors comprising a subset of said system errors; and (D) storing said valid error file in a recording medium.