1. A memory controller system for controlling access to a memory device having a plurality of integrated circuit (IC) chips disposed in a non-uniform stack configuration within a three-dimensional stacked (3DS) structure, the memory controller system comprising: a memory profiling portion configured to determine the non-uniform stack configuration of the memory device, the non-uniform stack configuration being defined by a plurality of selectable stacks each having at least one selectable chip, with at least one of the stacks being formed by less chips than another of the stacks formed by a maximum number of chips, the non-uniform stack configuration occupying a subset of chip locations within a uniform stack configuration virtually defined by at least all stacks of the plurality of selectable stacks being formed by the maximum number of chips; a virtual rank mapping portion configured to assign a subset of virtual ranks allocated for the uniform stack configuration virtually defined for the memory device to the subset of chip locations actually defined by the non-uniform stack configuration; and an address conversion portion coupled to said virtual rank mapping portion, said address conversion portion configured to convert an unoptimized address definable with reference to the uniform stack configuration by an unoptimized set of bits to an optimized address defined with reference to the non-uniform stack configuration by an optimized set of bits shorter in bit length than said unoptimized set of bits, wherein addressing overhead during monitoring of data access operations to the memory device is optimized.