1. A processor for managing a pool of available physical registers, the processor comprising: an instruction fetcher, an instruction decoder and at least one execution unit, the processor configured to perform a method comprising; performing, by a processor, operations that activate and deactivate selected architected registers of a set of architected registers, wherein a selected architected register is deactivated after a last-use of a value of the selected architected register; and based on an instruction being executed requesting a read of a first value from an architected register of a set of architected registers, performing a)-c) comprising: a) determining whether the architected register is activated; and b) based on the determining the architected register being read is deactivated, returning an architecture defined default value; and c) based on the determining the architected register being a read is activated, returning the first value, wherein the first value is a previously stored value in said architected register.