1. A method of reducing total power dissipation for logic cells of an integrated circuit, comprising: selecting, by a processor, a distribution of logic cells corresponding to at least one path; computing a dynamic to static power ratio for each logic cell in the distribution of logic cells; ranking the logic cells within the distribution of cells into a lower group, a middle group and an upper group of logic cells according to the dynamic to static power ratio for each logic cell, wherein the middle group is user defined according to a minimum and a maximum allowable dynamic to static power ratio; swapping cells from among the lower group of logic cells and the upper group of logic cells with cells of different transistor threshold voltage or different transistor size until all cells have a dynamic to static power ratio between the minimum and maximum allowable dynamic to static power ratio resulting in a reconfigured middle group of logic cells; and verifying path timing for the reconfigured middle group of logic cells.