1. A central processor for controlling the operation of subsystems which are interconnected on a common data bus of a telephone exchange to establish requested service between telephone subscribers, wherein the exchange includes a program memory also connected to the common data bus and containing a plurality of addressable multiple bit operational codes to be utilized by the central processor, said central processor comprising: a program address register including means for providing and storing the address in the program memory which contains an operational code to be utilized by the central processor; an arithmetic logic unit having an input coupled to said program address register for receiving the program memory address from said program address register, said arithmetic logic unit additionally having an output; a bus address register having an input coupled to said arithmetic logic unit output and having an output coupled to the common data bus for receiving the program memory address from said arithmetic logic unit and for addressing the program memory at the program memory address over the common data bus to cause the program memory to transmit the operational code over the common data bus; an instruction register having an input and an output for storing the operational code and for providing subsystem address signals responsive to the operational code; said arithmetic logic unit input also being coupled to said common data bus for receiving the operational code and said arithmetic logic unit output being coupled to said instruction register input for transferring the operational code to said instruction register, said arithmetic logic unit also having another input coupled to said instruction register output for receiving said subsystem address signals therefrom and for transferring said subsystem address signals at said arithmetic logic unit output to said bus address register for causing said bus address register to address the subsystems corresponding to said subsystem address signals for obtaining subsystem data therefrom, and said arithmetic logic unit also including means for performing logic and arithmetic functions responsive to function control signals to provide subsystem data and control signals; a bit time counter for providing sequential operational timing signals; and a control word generator coupled to said instruction register for providing said function control signals responsive to the operational code stored in said instruction register and coupled to said bit time counter for coacting therewith to provide said function control signals in proper time sequence.