1. A vector processor for performing a vector operation on two vectors each having a plurality of vector elements comprising: operation indicating means for providing respective information of an operation to be performed for each vector element of at least one of said two vectors; an arithmetic unit for performing a designated type of operation on each of said vector elements of each vector inputted thereto; first means for simultaneously supplying to said arithmetic unit said vector elements of said two vectors, respectively, said elements being supplied one at a time from each vector; and second means responsive to said operation indication means for designating to said arithmetic unit, each time a vector element is supplied thereto from said one of said two vectors, the type of operation to be effected by said arithmetic unit.