1. A processor comprising: a core to execute instructions, the instructions comprising memory operations, the core comprising: a register file having a plurality of registers to store data for use in execution of the instructions; a binary translator executed within the core to: determine a relative order of memory operations, detect when a first memory operation has been reordered prior to a second memory operation with respect to an original order of memory operations, identify a reordering problem of the first memory operation with respect to the second memory operation, by access to an alias tracking table that tracks at least two sequence numbers for each index, the at least two sequence numbers comprising a Maximum Load Sequence Number (MLSN) and a Last Store Sequence Number (LSSN), and communicate the relative order of memory operations to the core; and an alias hardware module to verify whether the memory operations are executed to distinct addresses.