1. A system, comprising: an interconnect to couple to one or more processor cores; and an atomic processing engine (APE), coupled to the interconnect, to receive a plurality of commands from the one or more processor cores through the interconnect and, in response to a first command of the plurality of commands, perform a first plurality of operations associated with the first command, the first plurality of operations referencing multiple memory locations; wherein at least one of the multiple memory locations is shared between a plurality of threads to be executed by the one or more processor cores.