1. A method of optimizing speed and predicted power consumption of a design for an integrated circuit, the design for an integrated circuit comprising at least one path further comprising at least one gate, the method comprising the steps of: creating an initial parent state representing devices of the integrated circuit design, where for each device in a path of the integrated circuit the state further comprises device size information and device type information, where the device type information further comprises selection between at least one fast-but-leaky type and at least one slow-but-not-leaky type; and performing multiple iterations of global optimization wherein at each iteration at least one daughter state is created from at least one parent state and evaluated for both power and speed.