1. A microprocessor comprising: a data bus means for transferring digital information; an interrupt request input conductor for conducting an interrupt request input signal representative of an interrupt request; instruction register means coupled to said data bus means for temporarily storing any one of a plurality of software instructions, including a first instruction having a fixed code, received by said data bus means; gating means for operatively coupling said data bus means to said instruction register means; instruction decode means responsive to the contents of said instruction register means for controlling execution of said instruction; interrupt means responsive to both said interrupt request input signal and to said first instruction coupled to said gating means for producing a signal for inhibiting loading of the next instruction to be executed in response to either said interrupt request input signal or said first instruction; and said gating means including means responsive to said signal coupled to said instruction register means for forcing a second code having a plurality of bits which are the same as corresponding bits of said first code into said instruction register means in response to said interrupt request input signal.