1. A processor comprising: a gather logic module comprising a first gather logic unit to identify locality of data elements in response to a first gather instruction; a first memory comprising a plurality of memory rows including a first memory row associated with the first gather instruction, the first memory row including a first portion to store data obtained in response to the first gather instruction and a second portion to store a snoop indication; and a second memory to store one or more data element addresses accessed in response to the first gather instruction, the second memory to store a pointer to denote that the first gather instruction accessed the one or more data element addresses, wherein if a snoop hits a valid entry in the second memory corresponding to the one or more data element addresses, the snoop indication is stored in the first memory row.