1. An apparatus comprising: a first sub-arbiter circuit configured to determine a first winning channel from a plurality of channel requests based on a first criteria; and a second sub-arbiter circuit configured to determine a second winning channel received from said plurality of channel requests based on a second criteria, wherein (a) said second sub-arbiter is configured to further prioritize the order of said first winning channel when determining said second winning channel by overriding said first winning channel if said second criteria creates a more efficient data transfer and (b) said second criteria of said second sub-arbiter circuit is different than said first criteria of said first sub-arbiter circuit to maintain consecutive read or write operations in a particular bank of a plurality of banks of a memory.