1. A fuzzy logic controller, comprising: a regulating memory for fuzzification connected to a regulating decoder and a minimum/maximum circuit for inference formation and a defuzzification circuit connected downstream of the minimum/maximum circuit; the regulating memory having f input memories and an output memory, for each input memory an input signal being fed via a respective buffer/decoding circuit to a respective input of a respective input memory; each input signal having an input resolution e and each buffer/decoding circuit forming 2.sup.e addresses for the respective input memory; a respective input memory of the f input memories having stored numbers for linguistic values of a respective input signal and function values of a first and h-1 further input relevance functions, h representing a degree of overlap of input assignment functions; for each input memory a number for a first relevant linguistic value of a respective input signal being fed directly and numbers for further relevant linguistic values of the respective input signal being fed via a respective incrementing device to inputs of a respective number multiplexer and being successively switched through by the respective number multiplexer in dependence on a respective multiplexer control signal to a respective input of the regulating decoder; the function values of a first and of h-1 further input relevance functions being successively fed in dependence on the respective multiplexer control signal via a respective relevance function multiplexer to a minimum operation element of the minimum/maximum circuit; and numbers for linguistic values of an output signal being assigned by rules stored in the regulating decoder from numbers for the relevant linguistic values of the respective input signal and these numbers for linguistic values of an output signal serving as addresses for a downstream output memory that is connected to the regulating decoder, said downstream memory containing values for relevance functions of the output signal and said downstream memory having an output connected via an output multiplexer to the minimum operation element of the minimum/maximum circuit.