1. A programmable logic array in which a desired logic function may be erasably programmed comprising: a plurality of input terminals; an AND plane including a plurality of AND gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of input terminals; and an OR plane including a plurality of OR gates each of which is operatively connected to receive a signal from the corresponding one of said plurality of AND gates in said AND plane and to supply a logic output, wherein at least one of said AND and OR planes includes: a matrix of conductors including first and second conductors which run in different directions thereby defining intersections therebetween and which are electrically isolated from one another; and a plurality of reprogrammable memory elements each disposed at each of the intersections between said first and second conductors, each of said reprogrammable memory elements having a first electrode connected to the corresponding one of said first conductors, a second electrode connected to the corresponding one of said second conductors and a third electrode connected to a reference voltage.