1. A multi-channel SPI interface memory controller, disposed between a CPU and a multi-channel SPI interface memory, comprising: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; and a register bank disposed between the main controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface.