1. A method of performing cache injection in a processor system, comprising: detecting, by a cache, a specific instruction sequence that includes multiple instructions, wherein one of the multiple instructions is a load instruction to a first address and another one of the multiple instructions is a compare instruction; monitoring, by the cache, addresses on a bus in response to detecting the specific instruction sequence multiple times; requesting, from a remote node via a network controller, input/output data associated with the first address of a data block stored in the cache; and acquiring, by the cache, ownership of the input/output data when an address on the bus that is associated with the input/output data corresponds to the first address of the data block stored in the cache.