1. An adaptive processor array comprising a plurality of identical processing cells arranged in parallel columns and rows to form a two dimensional matrix, each of said cells in said array having logic means and a memory for storing a memory state, the first row of said cells in the array forming a parallel input to the array, the last row of said cells in the array forming a parallel output from the array, each given cell (except for end row cells) in intermediate rows of said cells between said first and last rows having inputs each representing a data value coupled from two cells in a previous cell row positioned diagonally relative to said given cell, said logic means in each cell to compute a new data value based upon said diagonal inputs and its present memory state, said given cell (except for end row cells) coupled to two cells in the subsequent row positioned diagonally relative to said given cell, said new data value provided as an output to said diagonally coupled subsequent row cells, said logic means in each cell to evaluate the new data values received from said diagonally connected previous row cells and accordingly update its memory state by changing said new data values to a modified data value either toward or away from said new data values possessing respectively the same value or a greater separation in value and provide said modified value as a cell output, said updating of said memory state accomplished within a set range of values, said logic means further including means to classify said inputs as falling within one of two possible states based upon evaluation relative to said updated memory states, one of said states being interpretative of said inputs inside a designated field of inputs and the other of said states being interpretative of said inputs being outside a designated field of inputs.