1. A method of re-implementing a memory module, or a part of a memory module, that has been implemented on an FPGA device, the method comprising: performing a physical timing analysis on an initial implementation of the memory module or the part of a memory module; re-implementing the memory module or the part of a memory module, the re-implementation of the memory module or the part of a memory module comprising two or more logic blocks; placing the two or more logic blocks on the FPGA device, and re-connecting the two or more logic blocks, based at least in part on the physical timing analysis, so as to reduce circuit delay.