1. A method, comprising: sending a first command from a first assist thread bound to a first processor to a second processor and a memory, where the first command comprises a processor core argument that identifies the second processor and an instruction to pre-fetch a cache line; responsive to the first command, sending a first reply from the second processor, the first reply comprising an indication of an ability to receive the cache line; responsive to the first command, sending a second reply from the memory, the second reply comprising an indication of an ability to provide the cache line; responsive to receiving the first reply and the second reply, sending a combined response from the first processor to the second processor and the memory, the combined response comprising an indication to continue the instruction to pre-fetch the cache line; and responsive to the combined response, sending the cache line from the memory to the second processor and into a first cache of the second processor.