1. A neuron comprising: an adder circuit responsive to a plurality of gated inputs and generating an output, said adder circuit including: means for adding said gated inputs together to produce a sum; and means for adding said sum to a predetermined weight to generate said output; and a latch/counter for generating said gated inputs from a plurality of inputs to said neuron, said latch/counter means transmitting a given input x.sub.i to said adder circuit during g.sub.i addition cycles of said adder circuit, wherein g.sub.i represents a non-negative integer, said given input x.sub.i being added during each of said g.sub.i addition cycles resulting in a gated input having a form g.sub.i * x.sub.i.