1. A method comprising the steps of: receiving a single macro instruction specifying at least two logical registers, wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements; and independently performing an operation specified by the single macro instruction on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements, wherein the first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.