1. An integrated circuit comprising: an instruction cache comprising a plurality of fetch blocks, each fetch block of the plurality of fetch blocks associated with a location in the instruction cache and a cache tag identifying a location of the fetch block in memory; a branch prediction module, configured to generate a way prediction identifying a location in the instruction cache associated with a predicted fetch block and a cache tag associated with the predicted fetch block; and an instruction fetch unit configured to: retrieve, based on the way prediction, a first fetch block from the instruction cache located at the location identified by the way prediction; compare the cache tag associated with the retrieved first fetch block with the cache tag associated with the predicted fetch block; and validate, based on the comparison, that the retrieved first fetch block is the predicted fetch block predicted by the way prediction.