1. Circuitry for stochastic computation, said circuitry comprising: a plurality of processing nodes, including a first processing node and a second processing node, each of said processing nodes configured to process an outcome stream having a plurality of outcomes, each of said outcomes in said outcome stream being in one of a plurality of states, wherein an outcome from said outcome stream is in a particular state with a particular probability; communication links configured to transmit outcome streams between pairs of said processing nodes; and a delay module on each of said communication links, said delay module configured to delay outcome streams traversing said communication link by an assigned delay; wherein said first and second processing nodes are connected by a plurality of data paths, at least one of which comprises a plurality of communication links, each of said data paths causing an aggregate delay to an outcome stream traversing said data path; wherein no two aggregate delays impose the same delay on an outcome stream.