1. A pipeline processor including a first stage to read data from a general purpose register unit, a second stage to execute instruction, and a third stage to write back data into the general purpose register unit, the pipeline processor comprising: a first pipeline register to retain data obtained by the execution in the second stage and to allow the data to be written back into the general purpose register unit, the first pipeline register being provided between the second stage and the third stage, the first pipeline register including a first area to store a data validity flag indicating validity of the retained data and a second area to store a WRITE control flag to control writing the retained data into the general purpose register unit, and, the data retained in the first pipeline register being allowed to be written back into the general purpose register unit when the WRITE control flag indicates “valid”; and a bypass circuit to supply the data retained in the first pipeline register to the second stage when the data validity flag indicates “valid,” wherein the data validity flag and the WRITE control flag become “valid” when each of preceding and subsequent instructions for rewriting the general purpose register reaches the third stage, the WRITE control flag becomes “invalid” when the data retained in the first pipeline register is written into the general purpose register unit, and the data validity flag becomes “invalid” when a subsequent instruction is provided to the third stage that invalidates the data retained in the first pipeline register, and wherein the first pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit, and the first pipeline register provides the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.