1. A circuit for generating a multiplicative inverse of a finite field element, comprising: a plurality of parallel exponentiation circuits, each of the parallel exponentiation circuits comprising combinatory logic circuits configured to receive input digits of a multi-digit field element β of a finite field, the combinatory logic circuits being further configured to map the input digits to output digits of an output multi-digit field element β 2 m , where m is an integer greater than zero and m has a different value for each of the parallel exponentiation circuits; and a plurality of multiplier circuits configured to multiply together outputs of the parallel exponentiation circuits to generate the multiplicative inverse of the field element β.