1. A multicore processor, comprising: a plurality of cache memories at a first level; a plurality of processor cores, with each one of the plurality of processor cores associated with a corresponding one of the plurality of cache memories at the first level, and each processor core comprising: a processor; and a switch, with the switch having ports that provide a network among the plurality of processor cores; a cache at a second, different level, storing data and directory entries, and with for each cache line of data associated with a given cache line address stored in the cache at the second, different level on the multicore processor is stored a corresponding directory entry, with a common directory entry used for at least some cache lines in a given page or a given larger region of memory, with respect to a size of a cache line to provide compression of directory state information; a shim coupled via the network between one or more of peripheral ones of the processor cores that are processor cores at a periphery of the multicore processor, and corresponding one or more memory controllers, with at least some of the ports on the switch that is associated with the one or more of the processor cores passing though the shim to a corresponding main memory controller, and with the shim coupled to the cache at the second, different level, with the shim configured to: receive memory requests; and in response, query the cache at the second level using the stored directory entries before sending the received request to a main memory module.