1. A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprising: a controllable first FIFO clocked by a WDQS signal and storing write data on the basis of one or more successive write commands; and a controllable second FIFO clocked by an internal clock signal and storing, for a write operation, only addresses associated with valid write data of said write data stored in said first FIFO.