1. A memory controller comprising: (a) a first register; (b) a second register; and (c) control circuitry configured to (i) store, in the first register, first address data specifying a memory region from among a plurality of memory regions in a memory associated with the memory controller, wherein the memory has an associated memory space and supports random access to addresses of the memory space, wherein each of the memory regions spans a plurality of addresses of the memory space, and wherein the first address data comprises a value of base memory address of the specified memory region; (ii) store, in the second register, second address data corresponding to a current memory address of the specified memory region, the current memory address being contiguous with a previously written memory address of the specified memory region; (iii) receive, from a first computing resource, first write data to be written in the specified memory region; (iv) write the first write data at the current memory address based on the value of the base memory address of the specified memory region and the second address data corresponding to the current memory address; and (v) increment the second address data in the second register to update the current memory address based on a size of the first write data written at the current memory address.