1. A semiconductor memory system having a loop forward architecture, a command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to a first memory chip, to a second memory chip, to a third memory chip and to a fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller, the semiconductor memory system comprising: wherein each memory chip includes a rank select switching section; and with each command one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of command/address/write data stream stream and read data stream stream; and a rank select signal not embedded in the frame from the memory controller, transferred to each memory chip at the rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a command/address/write data stream signal stream is to be sent to an own memory core and processed or re-driven to a next memory chip.