1. A system comprising: a central processing unit; a clock source; a set of peripheral units being accessible by the central processing unit, each peripheral unit in the set of peripherals having at least one data sequential logic element having a clock input coupled to the clock source and an output coupled to a data output node; a delay path including at least one programmable delay line coupled between the clock source and the clock input of the at least one data sequential logic element in at least one of the peripheral units, the at least one programmable delay line having a delay selection input, wherein; the at least one programmable delay line is formed having a plurality of unit delay elements, each unit delay element having a send input, a send output, a return input, a return output, an inverter coupled between the send input and the send output, a multiplexer having a first data input coupled to the send output, a second data input coupled to the return input, an inverting output coupled to the return output, and a select input, each successive unit delay element having its send input coupled to the send output of the preceding unit delay element and having its return output coupled to the return input of the preceding unit delay element; and the delay selection input includes one bit position for each select input of each multiplexer in each unit delay element.