1. A method comprising: identifying a number of branches (N b ) and a number of iterations (N i ) in a loop in an instruction stream of a processor; generating a number of forward branches until the number of forward branches equals N b ; generating a non-branch instruction in between each of the number of forward branch instruction; recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch; determining whether a loop iterator number (i) is less than N i −1; generating a backward branch with an associated target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than N i ; generating a forward branch with an associated target address which is greater than the current address responsive to determining that loop iterator number (i) is equal to Ni−1; and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.