1. A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the further processing does not have to be repeated on multiple occurrences of the node instance in the layout.