1. A tag memory having an automating tag comparison mechanism, comprising: and the first column address is a column address where the memory address corresponds to a first data memory; wherein the tag comparison circuit further receives the index, the index comprises an upper level auxiliary tag, and each of the comparison tags comprises a lower level tag, a rest tag and an upper level flag, wherein the tag comparison circuit performs a parallel comparison between the target tag and the lower level tag of each of the comparison tags, if the lower level tag of one of the comparison tags matches the target tag, the tag comparison circuit further determines whether the rest tag in the matched comparison tag matches the upper level auxiliary tag in the index, and if the rest tag in the matched comparison tag does not match the upper level auxiliary tag in the index, the tag comparison circuit outputs the location of the matched comparison tag as the first column address, wherein the first data memory is a level of cache of a plurality of levels of cache, if the rest tag in the matched comparison tag matches the upper level auxiliary tag in the index, the tag comparison circuit further determines whether the upper level flag in the matched comparison tag is set, and if the upper level flag in the matched comparison tag is not set, the tag comparison circuit outputs the location of the matched comparison tag to serve as the first column address.