1. A method of determining a quality parameter for a verification environment for a hardware design language description of a hardware design, the method comprising: generating a netlist from the hardware design language description; generating a list of hardware design outputs; generating logical paths in the netlist based on the list of hardware design outputs; generating a modified netlist involving logical paths, wherein the generating the modified netlist comprises: determining for each gate in each of the logical paths in the netlist whether the gate is selected as an insertion point; and selecting a fault type for the selected gate in the netlist and inserting a mutant and associated activation and monitoring logic in the netlist, wherein the fault type, the mutant and monitoring logic of the associated activation and monitoring logic are each selected from a mutant database, wherein the modified netlist is generated; performing a fault simulation based on the modified netlist and collecting simulation result data using the monitoring logic; and determining the quality parameter for the verification environment from the fault simulation and the simulation result data.