1. An array-type processor in which a multiplicity of processor elements, which individually execute data processing in accordance with instruction codes for which data are individually set and for which connection relations between the processor elements are switch-controlled, are arranged in rows and columns; and in which said instruction codes of this multiplicity of processor elements are successively switched by a state control unit; wherein: said state control unit is composed of a plurality of units; the multiplicity of said processor elements is divided into the number of element areas that corresponds to the number of said state control units; a plurality of said state control units is connected to a plurality of said processor elements according to a plurality of said element areas; and each of the plurality of said state control units is arranged in a respective element area of the plurality of said element areas.