1. Reconfigurable processing unit ( 1 ) comprising: data flow controlling elements ( 10 ), data manipulating elements ( 20 ), a configuration memory unit ( 30 ) comprising a plurality of memory cells ( 31 a ,-. .. ) for storing settings of the data flow controlling elements ( 10 ), an addres decoder ( 40 ) for converting an address into selection signals for the memory cells ( 31 a ,. .. ), characterized in that the address decoder ( 40 ) is shared between the configuration memory unit ( 30 ) and a further memory unit ( 20 ).