1. An integrated circuit including a first number of memory interface partitions, each partition including a second-level cache, each second-level cache comprising: a tag ram configured to receive read requests for data and to determine whether data requested by a read request is stored in the second-level cache; a frame buffer interface configured to receive read requests from the tag ram; a first-in-first-out memory configured to receive read requests from the tag ram; a first auxiliary memory configured to receive read requests from the first-in-first-out memory; and a second-level cache memory configured to receive read requests from the first auxiliary memory and the first-in-first-out memory.