1. A computer-implemented method for race logic analysis on an integrated circuit (IC) design, to aid IC chip designers to detect and correct errors in their circuits and hence produce reliable IC products, the race logic analysis method comprising—using a processor to perform one or more of the following steps (a) detecting concurrent invocation of HDL-defined system functions/tasks that may cause one or more static or global signals/registers in the IC to be concurrently assigned or concurrently assigned and referenced, and render indeterminate values for those signals/registers; (b) detecting concurrently execution of “un-related” process blocks in the IC design that may cause one or more signals/registers to be concurrently assigned with different values, and hence render indeterminate values for those signals/registers; (c) detecting concurrently execution of “un-related” process blocks in the IC design that may cause one or more signals/registers to be concurrently assigned and being referenced by different process blocks, and render indeterminate values being read by driven process blocks; (d) detecting, dynamically via an event-driven logic simulation, circular functions/tasks invocation that may cause operation of the IC design to hang (deadlock); (e) detecting user-defined functions/tasks that invoke themselves recursively without termination, and hence render the IC design operation to hang (deadlock); (f) detecting concurrent invocation of HDL-defined functions/tasks that are built-in to HDL-defined inter-process communication (IPC) objects by “un-related” processes, that may render execution order of said “un-related” processes indeterminate, and/or that may process data that are of indeterminate values.