1. A processor core comprising: a plurality of dispatch queues, wherein the plurality of dispatch queues are configured to receive instructions associated with a plurality of threads; an even plurality of parallel execution slices, wherein each of the even plurality of execution slices includes a register file; a routing network configured to direct an output of the plurality of dispatch queues to the even plurality of parallel execution slice, wherein the even plurality of execution slices are configured to independently execute a plurality of threads; and a plurality of read busses coupling the even plurality of parallel execution slices to corresponding ones of the register files included in the even plurality of parallel execution slices, wherein the even plurality of parallel execution slices are organized in pairs, wherein a first read bus coupling a first one of a pair of the even plurality of parallel execution slices to a corresponding first one of the register files provides read access to the first execution slice and is also coupled to a second one of the pair of the even plurality of parallel execution slices to provide read access to the second execution slice so that the first register file is shared by the first execution slice and the second execution slice, and wherein a second read bus coupling the second execution slice to a corresponding second one of the register files provides read access only to the second execution slice and is not coupled to the first execution slice so that the second register file is not shared with the first execution slice.