1. A decoder for a quasi-cyclical low-density parity check code, comprising: a plurality of node processors each configured to perform a combined check node and variable node calculation on a variable node likelihood value at an input of the node processor using a check to variable node message to produce an updated variable node likelihood value at an output of the node processor a plurality of variable node memories providing storage for a plurality of variable node likelihood values, wherein the plurality of variable node memories comprise shift registers, each of the shift registers having a fixed time delay and connecting an output of one of the node processors to an input of one of the node processors; and a plurality of message memories coupled to the node processors, each message memory being associated with one of the node processors and having storage for a plurality of the check to variable node messages.