1. A semiconductor structure comprising: a device configured to receive at least one input data-word, the device comprising: a logic structure configured to: receive at least one key-word, wherein each key-word is configured to instruct the logic structure on a different predefined number and combination of one or more encrypting operations that are to be performed on each respective input data-word, wherein each key-word is derived as a function of a selected eFuse row address where each respective input data-word is to be stored after encryption; receive at least one code-word, wherein each code-word is a data pattern configured to combine with each respective input data-word using the one or more encrypting operations instructed by each respective key-word, and wherein each code-word is different for each respective input data-word; and generate at least one encrypted data-word by encrypting each input data-word using the data pattern of each respective code-word and the predefined number and combination of one or more encrypting operations instructed by each respective key-word; and an eFuse storage device configured to store each encrypted data-word as eFuse data at each respective selected eFuse row address by blowing fuses in accordance with each respective encrypted data-word, wherein a physical eFuse data pattern stored at each row is different based on each respective key-word and code-word.