1. A circuit comprising: a multiplier circuit for multiplying first and second n bit operands, wherein the multiplier circuit is configured to generate a result operand which represents a multiplication of the first and second n bit operands and further configured to generate first and second 2n bit partial product operands, and; an overflow detection circuit coupled to the multiplier circuit and configured to generate an overflow signal indicating the multiplication of the first and second n bit operands result in an overflow condition, wherein the overflow detection circuit generates the overflow signal in parallel with the generation of the result operand by the multiplier circuit and wherein the overflow detection circuit is configured to receive the most significant (n+1) bits of the first and second 2n bit partial product operands from the multiplier circuit.