1. In a computer having an arithmetic logic unit capable of processing at least one predetermined number of operands in tandem, said computer further adapted to process sparse vectors, said sparse vectors having corresponding order vectors having bits of two types, a first type indicative of the location of sparse vector operands in an expanded vector, a second type indicative of the location of operands of a preselected value; for each sparse vector to be coprocessed by said arithmetic logic unit, the improvement comprising: means for fetching said order vector bits group by group until all order vector bits have been fetched; the numbers of bits in each group being equal to said predetermined number of operands said arithmetic logic unit is capable of processing in tandem; means responsive to said means for fetching order vector bits for developing a population count of the number of bits of said first type in a group of order vector bits; means responsive to said means for developing a population count for forwarding a first plurality of operands from said sparse vector equal in number to said population count; means for aligning and ordering said first plurality of operands into an expanded group according to the alignment and order of said first type bits in said group of order vector bits; means for generating operands of a preselected value; means for inserting said operands of a preselected value into said expanded group according to the alignment and order of said second type bits in said group of order vector bits; and means for forwarding said expanded group of aligned and ordered operands in tandem to said arithmetic logic unit.