1. A memory cell, comprising: two split sub-lithographic charge storage nodes on a semiconductor substrate; two split sub-lithographic first poly gates on the two split sub-lithographic charge storage nodes; implanted portions in the semiconductor substrate under the two split sub-lithographic charge storage nodes; a dielectric between the two split sub-lithographic charge storage nodes on the semiconductor substrate, the dielectric comprising a single layer; a second poly gate between the two split sub-lithographic charge storage nodes; and a third poly gate over the semiconductor substrate.