1. Device ( 10 ) for processing digital data, in particular of the system on electronic chip type, using distributed execution of multiple data processing operations (T 1 , T 2 ) on multiple calculation nodes ( 16 , 18 , 20 , 24 , 26 , 28 , 30 , 34 , 36 , 38 , 44 , 48 ) using a data-flow processing model in which each data processing operation destined to be carried out on the device is modelled by a directed graph which is made up of calculation nodes, buffer memory nodes and directed links for the transfer of data between these nodes from at least one input buffer memory node ( 14 , 42 ) to at least one output buffer memory node ( 40 , 52 ), where two different processing operations may include at least one common calculation node ( 16 , 20 , 26 , 28 , 30 , 34 , 36 , 38 ), characterised in that it includes means ( 12 ; 60 ) for identifying, from a valued directed multi-graph made up of the union of several distinct processing graphs divided into several valued directed sub-multi-graphs ( 54 , 56 , 58 ) called chunks and whose input and output nodes are buffer memory nodes of the multi-graph, a coordination module ( 16 , 26 , 34 ) for each chunk, and in that each identified coordination module is designed to synchronise portions of processing operations destined to be executed in the chunk with which it is associated independently of portions of processing operations destined to be executed in other chunks.