1. A pipelined system for generating instructions in a digital computer comprising: means for producing first and second clock signals; CLK 1 and CLK 2, respectively; a sequencer operating at the rate of the first clock signal to generate sequential instruction addresses; a memory connected to receive the addresses from the sequencer and to produce instructions corresponding thereto; a pipeline register connected to the memory to load the instructions for execution at the rate of the second clock signal; the first and second clock signals normally being synchronous and at the same rate whereby the register loads a given instruction for execution while the sequencer generates the address of the sequentially following instruction; and decoder means responsive to the loading of a branch instruction into the register to cause the sequencer to generate a nonsequential address and to inhibit the second clock signal to prevent the register from loading the sequentially following instruction whereby, upon the next common occurrence of the first and second clock signals an instruction corresponding to the nonsequential address is loaded into the register and the sequencer generates the address of the instruction which follows the nonsequential address in a new sequence.