1. A data addressing system for addressing data storage means comprising: processor means which provides control signals and address signals, said control signals manifesting a data movement operation to be performed and said address signals defining addresses within a confined address space, addressable memory means for being addressed within said confined addressable space, said memory means including both read only memory addressable in a first portion of said confined addressable space and random access memory addressable in a second portion of said confined addressable space, said read only memory and random access memory being divided into an unpaged part and a plurality of paged parts, such that the address signals directly address said unpaged parts and page signals enable one of said paged parts to be addressed by said address signals; a plurality of selectable page register means, each for storing a code, one of said page register means being selected at any time to provide said page signals as manifesting said stored code; and page register selection means responsive to said control signals and selected address signals defining said address space portions for selecting one of said page register means wherein said page register means includes first, second and third page register means, said first page register being selected to provide said page signals whenever a read data operation occurs with respect to said read only memory, said second page register being selected to provide said page signals whenever a read data operation occurs with respect to said random access memory, and said third page register being selected to provide said page signals whenever a write data operation occurs with respect to said random access memory.