1. A trim circuit for tuning a current level of a reference cell in a flash memory including a sense amplifier for comparing a cell current from a memory cell having a gate for receiving a word line signal voltage with a reference current from the reference cell having a gate for receiving a bias voltage to produce a sense signal, the trim circuit comprising: a first and second units connected in series for producing the bias voltage by dividing the word line signal voltage with at least one of the first and second units having a programmable flash cell to serve as a variable resistor having a programmable resistance; and a programming circuit connected to the memory cell and flash cell for programming the programmable flash cell to thereby determine a value of the programmable resistance.