1. A method of using logic design computing equipment to design a logic circuit for implementing on a target device that is separate from the logic design computing equipment, the method comprising: with an emulation engine on the logic design computing equipment, receiving a computer program language description of the logic circuit, modeling performance of the target device when loaded to implement the logic circuit identified by the computer program language description prior to implementing the logic design on the target device, and generating statistics based on the modeled performance of the target device when loaded to implement the logic circuit; with a first compiler on the logic design computing equipment, generating an optimized hardware description language (HDL) description of the logic circuit based on the generated statistics; with a second compiler on the logic design computing equipment, generating an optimized configuration data bit stream for the target device by compiling the optimized HDL description of the logic circuit; and with a configuration device, loading the optimized configuration data bit stream onto the target device, wherein the target device implements the logic circuit as identified by the optimized HDL description when loaded with the optimized configuration data bit stream.