1. A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may cause a break in an instruction flow and non-exception instructions being instructions that execute in a statically determinable way, said data processing apparatus comprising: at least two processing blocks for processing instructions from said stream of instructions; a first processing block having a set of physical registers associated with it for storing data values being processed by said first processing block, and renaming circuitry associated with said first processing block for mapping architectural registers specified in instructions to be processed by said first processing block to physical registers within said set of physical registers; a second processing block having a set of physical registers associated with it for storing data values being processed by said second processing block, said second processing block registers not supporting renaming; control circuitry configured to identify exception instructions in said instruction stream and to detect when said exception instructions have been committed; said second processing block being configured to receive signals from said control circuitry and to suspend processing of an instruction in said second processing block until all preceding exception instructions have been committed, wherein said control circuitry comprises a global counter and is configured to analyse said instruction stream prior to said instructions being issued to said processing blocks and to update said global counter in response to detection of one of said exception instructions and for each instruction to be processed by said second processing block to update an instruction counter associated with said instruction with a value of said global counter, such that said instruction counter indicates a number of unresolved exception instructions preceding said instruction in said instruction stream; said control circuitry being responsive to detection of an oldest unresolved exception instruction being committed to generate a committed signal; and said control circuitry being responsive to said committed signal to update said global counter and instruction counters, said second processing block suspending processing of instructions in dependence upon said instruction counter values.