1. A memory system having a number of memory chips arranged in a matrix of N rows and M columns for storing X data words per roll having M bit positions, X being greater than N, said system comprising: addressing means for reading said data words from said matrix, an error checking system for identifying and locating error in any bit of each said data word read from said matrix, control means for establishing a range Y of memory addresses, Y being a fraction of X but greater than N, counter means associated with respective bits of each said data word read from said matrix, logic means connected to said control means, said error checking system, said addressing means and said counter means and operative to increment one of said counter means each time that error is identified in a respective bit of a data word having an address within said range, an additional counter connected to said logic means, said additional counter being incremented each time a data word is read from said matrix within said range Y of memory addresses irrespective of whether error is identified in any bit thereof, and means connected to said counter means and said additional counter to determine the ratio of the counts in each said counter means relative to the count in said additional counter.