1. A method of mapping an integral into a computational thread of a processing unit having a parallel architecture, the method comprising: mapping the integral into a summation of products, each of the products being a product of a respective coefficient value and a respective summation value; generating data elements that define a directed graph in a memory structure for computing the summation of products, the directed graph comprising: a plurality of input nodes, each corresponding to one of the coefficient values or to one of the summation values, being connected to an input of a first edge, and being adapted for giving the respective coefficient or summation value, as an intermediate value, to the input of the first edge connected thereto, one or more intermediate nodes, each corresponding to an operation of the summation of products and being connected to outputs of two of the first edges and to an input of a second edge, each intermediate node being adapted for performing the operation on the intermediate values of the two of the first edges, and for giving a result of the operation as another intermediate value to the input of the second edge connected thereto, and an output node being connected to an output of a second edge, and being adapted for receiving the intermediate value of the second edge; assigning a level of a traversal sequence to each node of the directed graph that defines a sequence in which operations corresponding to the nodes are executed in the computational thread of the processing unit; and specifying, for each level of the traversal sequence as the traversal is being performed according to the traversal sequence, a storage location in the memory structure for the intermediate value corresponding to each first or second edge having its input connected to the node assigned to the respective level of the traversal sequence, the specifying including determining a fastest memory location in a memory that includes register, local, and global storage locations by: storing the intermediate value in the register storage if: the register storage has free storage space, or there is another intermediate value that has been assigned a storage location in the register storage that has an intermediate level parameter with a value that is larger than the value of the intermediate level parameter of the intermediate value currently being assigned the storage location, in which case the storage location of the intermediate value with the highest intermediate parameter value is changed to the local storage or the global storage, otherwise storing the intermediate value in the local storage if: the local storage has free storage space, or if there is another intermediate value that has been assigned a storage location in the local storage that has an intermediate level parameter with a value that is larger than the value of the intermediate level parameter of the intermediate value currently being assigned the storage location, in which case the storage location of the intermediate value with the highest intermediate parameter value is changed to the global storage, otherwise storing the intermediate value in the in the global storage, wherein the arrangement and levels of the nodes defined by the memory structure maps the integral into the computational thread of the processing unit.