1. A partial scan system for sequential circuits comprising: an input unit, that receives a description of the sequential circuits; a peripheral partitioning unit, that peripherally partitions the sequential circuits received by the input unit; a tree decomposition unit, that performs tree decomposition on the sequential circuits received by the input unit; a circuit redesign unit, that redesigns the sequential circuits based on outputs of the peripheral partitioning unit and tree decomposition unit; and an output unit, that outputs a redesigned circuit.