1. A context switching unit for switching a plurality of contexts, the context switching unit comprising: a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a read port, a write port, a context-switching read port, and a context-switching write port; a context cache for caching a context, the context cache comprising a read port and a write port, being connected directly to the register file, and being contained in a central processing unit in a on-chip manner; a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit, wherein the thread control unit receives a context switch instruction for executing a save operation and a restore operation concurrently and the identifier of a new thread to be interchanged, when a context switch which executes both a context save operation and a context restore operation in parallel occurs; the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and the save register identifier indicating the location where the current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier; the thread control unit sends the obtained address to the context cache and sends the register identifier to the register file concurrently; the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port and, concurrently writes the data of the context to be restored, sent from the read port of the context cache to the context-switching write port through the restore bus, in the register corresponding to the register identifier; the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port and, concurrently writes the data of the context to be saved sent from the context-switching read port of the register file to the write port via the save bus; and the context switching unit switches contexts by executing an operation for restoring a context from the context cache to the register file and an operation for saving a context from the register file to the context cache concurrently.