1. A device, comprising: a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (LBAs); a secondary memory implemented as a cache for the primary host memory; a hybrid controller configured to: receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the secondary memory; receive the incoming memory access requests from the host processor, the incoming memory access requests including a range of LBAs; route the incoming memory access requests to a set of incoming queues by implementing a priority scheme, the set of incoming queues comprising an incoming execute queue, the priority scheme comprising: routing invalidate requests in an invalidate ready queue to the execute queue as a highest priority; routing read requests in a read ready queue to the execute queue as a second highest priority; and routing promotion requests in a promotion ready queue as a third highest priority; directly map clusters of host LBAs to clusters of secondary memory, the secondary memory clusters corresponding to a memory space of the cache, the mapping of the host LBA clusters to the secondary memory clusters being fully associative wherein any host LBA cluster can be mapped to any secondary memory cluster; responsive to a promotion request that specifies a cluster aligned host LBA range, use the mapping of the host LBA clusters to the cache clusters to determine if the host LBA range corresponds to one or more overlapped cache clusters present in the secondary memory; if the host LBA range corresponds to the one or more overlapped cache clusters, create a bitmap of the overlapped cache clusters; and implement a write operation to the secondary memory using the bitmap to skip writing the overlapped cache clusters to the secondary memory.