1. A processor comprising: a main controller (CTR 11 ); a plurality of processing units ( 1 - 9 ), each processing unit comprising a local controller (CTR 1 -CTR 9 ) and at least one functional unit (FU 1 -FU 9 ) controllable by the local controller (CTR 1 -CTR 9 ), the local controller (CTR 1 -CTR 9 ) being coupled ( 15 ) to the main controller (CTR 11 ); an instruction set having at least one instruction for increasing the activity of at least one processing unit ( 1 - 9 ); characterized in that the main controller (CTR 11 ) is arranged to process the at least one instruction.