1. An electronic power management system comprising: plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output; a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs; and a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.