1. A microprocessor comprising: a cache memory; a prefetch unit coupled to the cache memory and configured to monitor memory accesses and to determine whether to prefetch one or more blocks of memory from a system memory based upon previous memory accesses, wherein the prefetch unit is further configured to use addresses of the memory accesses to calculate each next memory block to prefetch; detection logic configured to provide a notification in response to detecting a memory access instruction including a particular hint; wherein in response to receiving the notification, the prefetch unit is configured to inhibit using an address associated with the memory access instruction including the particular hint, to calculate subsequent memory blocks to prefetch.