1. A processor, comprising: a hierarchical interrupt register structure, comprising: a plurality of lower level registers, and a first root-level register configured to indicate an interrupt occurring at a first lower level register of the plurality of lower level registers; one or more error handlers, each error handler of the one or more error handlers assigned to a respective set of registers of the interrupt register structure; and a system interrupt handler configured to determine, based on a determined amount of time required to complete a prescribed recovery action for an interrupt, whether to directly handle the interrupt or to invoke an error handler of the one or more error handlers to handle the interrupt.