1. For use in a processor, a branch architecture for limiting branch penalty without branch prediction comprising: a fetch-branch unit operating in parallel with a decode unit and controlling retrieval of instructions for the decode unit, wherein the fetch-branch unit, upon detecting a branch instruction during one cycle, initiates retrieval of at least one sequential instruction from a location immediately following a location of a last retrieved instruction during one of a first cycle immediately following the one cycle and a second cycle immediately following the first cycle, and initiates retrieval of at least one target instruction from a target location for the branch instruction during the other of the first cycle immediately following the one cycle and the second cycle immediately following the first cycle.