1. A system comprising: a first circuit including a multiplier array configured to receive a first operand and a second operand and generate a plurality of outputs; an adder array configured to receive the plurality of outputs and generate a partial product of the first operand and the second operand, wherein the partial product of the first operand and the second operand includes partial sums and carry bits; and a plurality of register arrays configured to store the partial sums and carry bits; and a second circuit is configured to generate the product of the first operand and the second operand by implementing a two-stage reduction of the partial product of the first operand and the second operand including a first stage and a second stage; the first stage including rearranging the partial sums and carry bits as two multi-bit integers; and the second stage including generating a plurality of multi-bit integers based on the two multi-bit integers, and generating the product of the first operand and the second operand based on the plurality of multi-bit integers.