1. A content-addressable-memory device comprising: a plurality of content-addressable-memory sub-arrays that simultaneously performs a parallel comparison between a plurality of data sequences arranged in a row direction of memory cells storing three values of “1”, “0”, and ”X” and a search data sequence input from outside, and outputs a result of the comparison for each of the data sequences; a first input pin to which the search data sequence is input; and a second input pin to which a search data sequence arbitrarily designating a content-addressable-memory sub-array is input, wherein each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence input from the second input pin.