1. An SDIO controller having a single-chip semiconductor device connecting a SDIO-compliant SDIO host device with a plurality of applications via an SD bus, comprising: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.