1. A processor chip comprising: a plurality of processor cores, including at least one processor having a plurality of ALUs; a plurality of local memories comprising copies of main memory areas; a cache controller controlling the local memories; a prefetching arrangement for prefetching data from the main memory areas into the local memories; wherein: at least some of the local memories operate as first level cache; the processor chip has multi-thread capabilities; and the prefetching arrangement is adapted to receive prefetch commands during execution of a first thread and prefetching data during the execution of a second thread.