1. A computer processor based method comprising: executing, by an architectural thread, instructions in a dynamic instruction stream; spawning a speculative thread at a specified location in the dynamic instruction stream during the executing by the architectural thread; and executing, by the speculative thread, instructions in the dynamic instruction stream subsequent to the specified location so that instructions in the dynamic instruction stream are fetched and issued out of sequential order with respect to the executing by the architectural thread, wherein the specified location is at least more than two-hundred instructions beyond the oldest instruction that is awaiting completion of execution for the architectural thread.