1. A method operating in a computer system for analyzing an integrated circuit design having a hierarchical structure, the method comprising: using the computer system to traverse nodes of the hierarchical structure, wherein the nodes represent cells of the integrated circuit design; finding candidate cells to receive corrections for optical proximity distortion, wherein the candidate cells are selected based on at least one of a size of the cells and a frequency of occurrence of the cells; tagging the candidate cells; extracting overlap regions between overlapping cells of the integrated circuit design; and collecting the overlap regions into a different cell, other than the overlapping cells.