1. A multi-processor system operating in a selected one of a plurality of modes comprising: a plurality of processors, each processor having a data port and an instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port; a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors; a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, one of said operational modes of said switch matrix being a single instruction multiple data mode, said switch matrix connecting processors to memory in said single instruction multiple data mode whereby a predetermined one of said processors accesses instructions via said instruction port and switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of each of said processors, and each of said processors accesses data via said data port and said switch matrix within any of said plurality of memories except said instruction memory corresponding to said predetermined one of said processors; and an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.