1. A computer implemented method comprising: receiving a transaction level model description of an integrated circuit; generating a synthesizable subset of the transaction level model description from the transaction level model description, the synthesizable subset including a communication portion and a behavioral portion, the communication portion independently synthesizable; automatically converting function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description; automatically generating interface logic in the synthesizable subset of the register transfer level description, the interface logic comprising an interface between a bus interface and the signal accesses, the interface logic including combinational logic of a signal generator and buffer registers; and storing in a computer readable medium the register transfer level description including said signal accesses and the interface logic between the bus interface and said signal accesses.