1. An asynchronous register comprising: an input receiving a plurality of asynchronous data signals; an input receiving a control signal; a plurality of asynchronous storage elements, each asynchronous storage element generating an output signal in response to at least one of the plurality of asynchronous data signals and the control signal; wherein each asynchronous storage element is characterized by asserting a meaningful output when the asynchronous data signal and the control signal are meaningful, and holding the meaningful output until both the asynchronous data signal and the control signal are non-meaningful; and wherein each asynchronous storage element is further characterized by switching its output to a non-meaningful signal when the asynchronous data signal and the control signal are non-meaningful, and holding the non-meaningful output until both the asynchronous data signal and the control signal are meaningful.