1. A semiconductor memory device having a memory cell array comprising memory cells which need refresh and receiving asynchronously a write request and write data together with an access address, wherein the semiconductor memory device comprises: an access means for executing a refresh of said memory cell array subsequently to a write cycle to the access address; a write control means for rendering said access means perform a late write operation, using said access address and said write data given in said memory cycle, after a memory cycle in which said write request has been given; and a read inhibit control means for inhibiting a read operation based in an output enable signal in said write cycle having said execution of said late write operation.