1. A system on a chip (SoC) comprising: memory to store a set of instructions; and a processor core coupled to the memory and comprising a configuration bit register to store configuration bits, wherein the processor core is to: identify a region of code in the set of instructions demarcated by a first instruction of the set of instructions; determine a first metric resulting from execution of the region of code with the configuration bits set to a first value; determine a second metric resulting from execution of the region of code with the configuration bits set to a second value; and set the configuration bits to a third value to increase a performance of the processor core, decrease power consumption of the processor core, or both for subsequent execution of the region of code, wherein the third value comprises a first portion of the configuration bits for the first value and a second portion of the configuration bits for the second value, wherein each of the configuration bits indicates whether a tunable parameter for a system configuration of the processor core is enabled or disabled.