1. A method of building a multi-layer graph for greater than two dimensional integrated circuit routing, the method comprising: generating a plurality of subgraphs, each of the plurality of subgraphs corresponding to each of a plurality of layers of circuitry, each of the plurality of subgraphs including a plurality of segments based on information from other layers of circuitry; and combining all of the plurality of subgraphs into a single, multi-layer graph.