1. A microprocessor, comprising: scheduler logic for issuing one or more instructions for execution; execution logic for executing the one or more instructions as issued by the scheduler logic; a queue for holding one or more instructions for re-dispatch to the execution logic; and runahead control logic for managing runahead operation of the microprocessor, the runahead control logic configured to: detect a runahead-triggering event, responsive to detection of the runahead-triggering event, (i) cause the microprocessor to operate in runahead, and (ii) insert a runahead-triggering instruction associated with the runahead-triggering event into the queue along with one or more additional instructions, resume non-runahead operation upon resolution of the runahead-triggering event, and upon resuming non-runahead operation, re-dispatch the runahead-triggering instruction and the one or more additional instructions from the queue to the execution logic.