1. A processor comprising: instruction logic to receive a first state management instruction, a second state management instruction, and a third state management instruction, the first state management instruction having a parameter to program a bit vector to identify a subset of a plurality of features supported by the processor, the second state management instruction to read the bit vector, and the third state management instruction to specify a state management operation; and state management logic to perform the state management operation specified by the third state management instruction for the subset of the plurality of features.