1. A readdressing circuit for providing data communications over a data line and a clock line between at least one master device and multiple slave devices, comprising: a data input node for receiving a data signal transferred over the data line and including an address word produced by the master device, a data output node coupled to the multiple slave devices, an address generator for storing a multi-bit fixed offset value, the address generator being responsive to the address word at the data input node for generating multiple unique addresses for the multiple slave devices and providing the translated address immediately to the data output node without requiring extra clock cycles, and an address transmit detection circuit for allowing the multiple unique addresses to be provided at the data output node when the address word is detected at the data input node, and for preventing an output signal of the address generator from being supplied to the data output node when the address word is not detected at the data input node.