1. A computer system for simulating the operation of an embedded system using a software application residing in the memory of a computer, comprising: a design application configured to form a hardware specification of an embedded system, the design application including: a design language having at least one graphical symbol adapted to form a finite state machine (FSM) representation of electronic hardware, each graphical symbol of the design language having a graphical portion and a user-definable textual portion defining the behavior of the graphical symbol, a library including at least one instruction set accurate simulator for simulating the behavior of a target processor core having at least one memory read pin, at least one write memory pin, and at least one interrupt pin, a graphical user interface adapted to permit a user to select an instruction set accurate simulator of a target processor core and to form a FSM representation of a hardware component in the design language, and a configuration interface for coupling memory read/write signals and interrupt signals of the instruction set accurate simulator to corresponding signals of a the hardware component; a test bench builder for generating a graphical representation of at least one interactive test bench and for selecting signals or variables to be coupled to a graphical representation of a user interface for each interactive test bench; a software debugger including a debugging interface for associating a breakpoint of execution a graphical symbol of the finite state machine representation of the hardware component; a graphical database and a behavioral database coupling data associated with the hardware description to a code generator; a compiler for compiling the output of the code generator into an object file of the hardware description; a discrete event simulation engine configured to execute the object file of the hardware description; a first API interface adapted to couple the discrete event simulation engine to each of the interactive test benches; at least one API interface adapted to couple the discrete event simulation engine to the instruction set accurate simulator of the hardware description; and at least one API interface adapted to couple the instruction set accurate simulator to a software debugger, the software debugger configured to load at least one binary program code compiled for the target processor.