1. A subranging analog-to-digital (A/D) converter for converting a sampled analog input signal into corresponding n-bit digital words representative thereof comprising: an arithmetic unit for generating a series of error signals for each analog input signal sample, said error signals of a series being representative of the differences between a signal representative of the corresponding analog input signal sample and a respectively corresponding series of feedback signals associated therewith; a plurality of parallel network branches for operating on each error signal simultaneously, each network branch i of said plurality including: means for gain adjusting each error signal with a gain G.sub.i ; and an m.sub.i -bit quantizer cascaded therewith for converting each gain adjusted error signal of the branch i into an m.sub.i -bit digital word representative thereof, the m.sub.i bits of said digital word output of each quantizer i being assigned predeterminately to a portion of the bits of an intermediate n-bit digital word which has a greater bit capacity than any of the m.sub.i -bit digital words; said gain G.sub.i increasing progressively from one branch i to another branch i+1 in accordance with a predetermined range of quanta of the corresponding quantizers associated therewith; means for selecting at least one digital word conversion from the plurality of simultaneous conversions for each error signal based on the digital codes thereof to form said intermediate n-bit digital word corresponding to each error signal: said selecting means including: a digital date for each network branch except the branch having the lowest gain, each digital gate disposed in cacade with its corresponding branch quantizer and governed by a gate command signal to select the digital word conversion of its corresponding quantizer as a constituent in the formation of said intermediate n-bit digital words in accordance with the bit assignment thereof; and means for generating the gate command signals by generating the gate command signal for said digital gate of branch i+1 based on the conversion digital code of the quantizer output of branch i; means for accumulating each series of formed intermediate n-bit digital words by generating an intermediate accumulated n-bit digital word corresponding to each formed intermediate n-bit digital word of said series, each generated series of intermediate accumulated n-bit digital words being respectively representative of said series of feedback signals in accordance with their accumulating sequence; and means for storing the final accumulated n-bit digital word for each accumulating series of formed intermediate n-bit digital words as the n-bit digital word conversion of its corresponding analog input signal sample.