1. A method comprising: disabling one or more of a plurality of memory interfaces and enabling the other of the plurality of memory interfaces of a computing device; coupling one or more memory devices to each of the enabled memory interfaces and one or more additional memory devices to a subset of the enabled memory devices, wherein a first depth of memory is coupled to one or more memory interfaces and a second depth of memory is coupled to one or more other memory interfaces; and mapping each of a plurality of physical address ranges to a corresponding memory interface and a memory space of a corresponding memory device, wherein the physical address ranges of the additional memory devices includes a given offset.