1. A digital signal processor, said digital signal processor having an instruction decoder coupled to an instruction memory for decoding a plurality of instructions fetched from said instruction memory, said digital signal processor being responsive to a short-immediate instruction word, said digital signal processor comprising an accumulator register coupled to an output of an arithmetic processing unit; a rounding value coupled to said accumulator register; means for loading said rounding value into said accumulator register substantially contemporaneously with starting an arithmetic operation of said arithmetic processing unit; means in said instruction decoder for selecting an arithmetic operation to be performed responsive to an opcode field in said short immediate instruction word; means in said instruction decoder for selecting an immediate constant as an operand for said arithmetic operation to be performed, said immediate constant being responsive only to an immediate field in said short-immediate instruction work, said immediate constant being substantially different from a binary value represented by said immediate field.