1. A parallel rendering architecture in computer graphics, comprising: a sequencer which decodes rendering commands for a plurality of pixels and generates fragment-processing commands therefrom; a SIMD processor operatively connected to said sequencer, the processor comprising a plurality of processing elements that are configured to receive and operate on said fragment-processing commands and also separately connected to send and receive pixel data, and automatically jump to rendering another pixel when rendering on any one pixel stalls; and a buffer operatively interposed between said sequencer and said processor, into which the sequencer deposits said fragment-processing commands and from which said processor receives said fragment-processing commands, that decouples operations between the sequencer and the processor; wherein said sequencer is logically asynchronous to said processing elements and does not have to work on the same instructions at the same time as said processing elements, and wherein said sequencer and said processing elements are physically synchronous, and said sequencer and said processing elements operate at different rates, whereby the likelihood of stalling in said processor is reduced.