1. A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, comprising: polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree; mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree; estimating a shared array BIST completion time corresponding to a maximum total memory address size under test; reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST latency/completion time; and testing the plurality of memories sharing the first comparison tree.