1. A processor-implemented method comprising: receiving an instruction operation (OP) code at a processor, wherein the instruction OP code includes one or more instruction bits and one or more forced event bits; identifying, by bit decode logic included in the processor, a forced event based upon the one or more forced event bits, wherein the forced event is unrelated to an instruction that corresponds to the one or more instruction bits; and executing the forced event by an execution unit included in the processor.