1. A system comprising: a plurality of registers, wherein the plurality of registers comprises: a first set of registers directly accessible by a device; and a second set of registers indirectly accessible by the device via the first set of registers; wherein the first set of registers includes a first subset of registers that enable indirect access to the second set of registers by the device, and a second subset of registers different from the first subset; and a pattern-recognition processor, comprising: a row decoder having an input configured to receive a data stream to be searched; and a plurality of feature cells coupled to the row decoder, wherein each of the plurality of feature cells comprise a plurality of memory cells each addressable by a conductor coupled to an output of the row decoder.