1. A signal processor simulator for simulating parallel execution of instructions on a dual processor circuit, the signal processor simulator comprising: a first processor simulator for simulating execution of instructions to a first processor of the dual processor circuit; a second processor simulator for simulating execution of instructions to a second processor of the dual processor circuit; a shared memory to store values, said shared memory visible to said first processor simulator and said second processor simulator; a first clock simulator to simulate a clock for the first processor; a second clock simulator to simulate a clock for the second processor; and a synchronizer that compares the first clock simulator against the second clock simulator and processes an instruction to the processor simulator corresponding to the clock simulator that is furthest behind.