1. A simulation system for verifying logic behavior of a semiconductor integrated circuit, comprising: a reprogrammable semiconductor device comprising an interface circuit and a logic circuit; and an analyzing unit configured to divide a logic behavior of the semiconductor integrated circuit into a software-based first logic behavior and a hardware-based second logic behavior and to generate circuit data of the interface circuit included in the first logic behavior that exhibits an input/output behavior and circuit data of the logic circuit that exhibits the second logic behavior; wherein the analyzing unit verifies the logic behavior of the semiconductor integrated circuit including the logic circuit, the interface circuit, and an untimed behavior model exhibiting the first logic behavior in which time related information is unspecified.