1. An apparatus comprising: one or more precharge paths comprising one or more respectively corresponding first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more respectively corresponding first junction nodes, the one or more precharge paths lacking a keeper circuitry; and one or more second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more respectively corresponding second junction nodes, and second terminals coupled to a second power rail.