1. A Network On a Chip (NOC), the NOC comprising: a first processing node; at least one execution unit within the first processing node; a Compressed Direct Inter-thread Communications Buffer (CDICB) coupled to the processing node, wherein the CDICB is populated with operands from an Uncompressed Direct Inter-thread Communication Buffer (UDICB) that comprises at least one empty buffer cell between at least two operands that are stored in the UDICB, and wherein the UDICB and the CDICB contain multiple different operand aggregates; a multiplexer (MUX) Special Purpose Register (SPR) coupled to the CDICB and the first processing node, wherein the MUX SPR stores MUX control data; and a MUX controller coupled to the MUX SPR and a first set of MUXs within the first processing node, wherein the MUX controller utilizes MUX control data from the MUX SPR and the first set of MUXs to realign original operands retrieved from the CDICB by the first processing node, wherein realigned original operands are organized by data rows in an organization format that is required by an execution unit architecture for supplying operands to the execution unit.