1. A computer-readable memory storing a plurality of instructions for causing a processor to perform operations, the plurality of instructions comprising: instructions that cause the processor to split a continuous event processing (CEP) query into a plurality of separate operators; instructions that cause the processor to determine a separate constraint for each particular operator within the plurality of separate operators; instructions that cause the processor to determine a constraint for the CEP query based at least in part on the constraints that the processor determined for the plurality of separate operators; and instructions that cause the processor to determine, based on the constraint for the CEP query, whether at least a part of the CEP query can be executed in a concurrent manner; and instructions that cause the processor to spawn multiple threads of execution that concurrently process events from an event stream in response to determining that at least part of the CEP query can be executed in a concurrent manner.