1. An apparatus for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system, comprising: means for identifying a class of instructions; means for sampling path-identifying state information of a currently processed instruction when the currently processed instruction belongs to the identified class of instructions; a shift register to store a predetermined number of entries storing selected state information; and means for simultaneously sampling the shift register and additional state information about the instruction being executed at the time of sampling.