1. A very long instruction word (VLIW) processor comprising: a VLIW fetch unit for fetching an instruction bundle which comprises a plurality of instructions to be executed in parallel and a single value indicating predicated execution of each of the plurality of instructions in the bundle; a decoder for decoding the instruction bundle; and a VLIW execution unit for executing, in parallel, the instructions included in the instruction bundle, according to the single value indicating predicated execution.