1. An integrated circuit chip comprising programmable intelligent search memory for content search wherein said programmable intelligent search memory performs regular expression based search and wherein said regular expression comprises an interval symbol, said interval symbol comprises a symbol and further comprising a) a lower limit; b) an upper limit; or c) a combination thereof; the programmable intelligent search memory using one or more regular expressions, said one or more regular expressions comprising one or more symbols or characters, said one or more regular expressions further comprising one or more of said interval symbols, said one or more regular expressions converted into one or more finite state automata representing the functionality of said one or more regular expressions for programming in said programmable intelligent search memory, said one or more finite state automata comprising a plurality of states, said plurality of states derived from said one or more symbols or characters or said one or more interval symbols of said one or more regular expressions, said content comprising one or more input symbols provided as input to said programmable intelligent search memory, said programmable intelligent search memory comprising at least one of each of: a. a symbol memory circuit to store said one or more symbols; b. an interval symbol memory circuit to store said one or more interval symbols; c. an interval symbol evaluation circuit coupled to said interval symbol memory circuit to evaluate a match of said one or more interval symbols stored in said interval symbol memory circuit with said one or more symbols of said content; d. a symbol evaluation circuit coupled to said symbol memory circuit to evaluate a match of said one or more symbols stored in said symbol memory circuit with said one or more symbols of said content; e. a state dependent vector (SDV) memory circuit to store state transition controls for said one or more finite state automata; f. a current state vector memory (CSV) circuit to store said plurality of states; and g. a state transition circuit coupled to said symbol evaluation circuit, said interval symbol evaluation circuit, said current state vector memory circuit and said state dependent vector memory circuit to perform state transition from one or more first states to one or more second states of said plurality of states of said one or more finite state automata.