1. An integrated circuit device comprising: an embedded memory comprising a plurality of memory macros, each memory macro comprising a plurality of memory cells, each memory macro having a data input and a data output; a built-in-self-test (BIST) circuit coupled to said plurality of memory macros for simultaneous operation of said memory macros; and a plurality of latch gates coupled between the data outputs of said macros and the BIST circuit, wherein said latch gates are responsive to enable control signals from said BIST circuit to latch data from the data output of an individual memory macro selected by said BIST circuit to said BIST circuit for analysis, wherein said BIST circuit is configured to select from said memory macros' data outputs an individual memory macro's data output for analysis while said memory macros are simultaneously operated.