1. A computer-implemented method for performing a formal verification of a circuit description, the method comprising: receiving a hardware description for at least a portion of a circuit design, wherein the hardware description includes a clock specification of two or more clocks; capturing phase clock states from the hardware description based in part upon a master clock and a phase counter, wherein the master clock and the phase counter are used to model the two or more clocks; capturing edge clock states from the hardware description in response to a transition of a one or the two or more clocks; and implementing, on a computer, a formal verification process based in part upon the captured phase clock states and the captured edge clock states.