1. A memory device comprising: a semiconductor including a source region, a drain region, and a channel region between the source region and the drain region; a first gate structure overlying the channel region, wherein the first gate structure comprises: a first memristive portion overlying the channel region; and a first conductive portion overlying the first memristive portion; and a second gate structure underlying the channel region, wherein the second gate structure comprises: a second memristive portion underlying the channel region; and a second conductive portion underlying the second memristive portion.