1. A method for implementing two types of architectures on a chip, comprising: receiving an instruction from a fetch engine, determining whether the instruction is a macroinstruction or a microinstruction, if the instruction is a macroinstruction, sending the macroinstruction to an emulation engine, decomposing the macroinstruction into one or more microinstructions, formatting, by a bundler, the microinstructions into bundles as preferred by the native microarchitecture, dispatching a bundle in parallel to an execution engine, if the instruction is microinstruction, dispatching the microinstruction to the execution engine; and dispatching additional information to the execution engine, wherein the additional information is contained in bits of the bundle otherwise not required for emulation of the macroinstruction.