1. An integrated circuit (IC) for pattern detection comprising; an arithmetic logic unit coupled to a comparison circuit, the arithmetic logic unit programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, the first multiplexer coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern, wherein the first multiplexer is coupled to another register, wherein inputs of the first multiplexer are a pattern of the plurality of patterns and also a predetermined pattern of the plurality of patterns.