1. An apparatus comprising: a memory configured to store a program including a description of loop processing of iterating a plurality of instructions; and a processor coupled to the memory, configured to: rearrange an execution sequence of the plurality of instructions in the program such that the loop processing is pipelined by software pipeline, set a first register as a load destination of data in a load instruction of the plurality of instructions, and insert a shift instruction to shift a data row in a storage area to left, into the description of the loop processing in the program, the data row being acquired by combining the first register with a right side of a second register for single instruction multiple data (SIMD) extension instruction, wherein, for each of a plurality of iterations of the pipelined loop processing, the processor loads data into the first register according to the load instruction, and shifts the data row in the storage area acquired by combining the first register with the right side of the second register to left according to the shift instruction, and wherein after each of the plurality of iterations of the pipelined loop processing is performed, the processor refers to data at a head of the second register.