1. An apparatus comprising: a processor; a memory comprising a first buffer, a second buffer, and a third buffer; and a member of the group consisting of (1) a graphics processor unit (GPU), (2) a multi-core processor, (3) a cell processor, and (4) a reconfigurable logic device; wherein the processor is configured to (1) receive a plurality of incoming records, the incoming records comprising a plurality of fields, (2) write the incoming records to the first buffer, (3) identify which of the fields of the incoming records are to be processed by the member, and (4) write the identified fields to the second buffer; wherein the member is configured to (1) read the fields in the second buffer, (2) perform a data processing operation on the read fields to generate a plurality of processed fields, and (3) write the processed fields to the third buffer; and wherein the processor is further configured to (1) read the processed fields in the third buffer, (2) read the fields for the incoming records in the first buffer, and (3) merge the processed fields with the fields from the incoming records to generate a plurality of outgoing records such that the outgoing records include the processed fields in place of their corresponding fields of the incoming records.