1. In a computer architecture for executing computer instructions, a method to reduce the occurrence of instruction execution pipeline stalls due to branch instructions and jump instructions, said method comprising: providing an instruction transfer bandwidth associated with a trace cache of said computer architecture that is greater than an instruction execution bandwidth of said computer architecture; and feeding back branch results of executed branch instructions and using said instruction transfer bandwidth in order to transfer only correct next instructions into an instruction execution pipeline based on said branch results of said executed branch instructions such that the occurrence of instruction execution stalls within said instruction execution pipeline is reduced.