1. A multi-port memory device comprising: one or more memory banks; a clock distribution network for distributing a clock signal; and a plurality of ports connected to the clock distribution network and providing access to the one or more memory banks, wherein at least some of the plurality of ports include an associated clock divider circuit that receives the clock signal and modifies the clock signal in order to generate a local clock signal, the local clock signal utilized by the associated port to operate at a port speed.