1. A method of designing a layout for an integrated circuit comprising: receiving a logic description in a high-level description language for the integrated circuit, the logic description having a plurality of circuit objects interconnected to form a plurality of nets, by executing first instructions in a computer system; identifying a plurality of placeable objects in the circuit description, by executing second instructions in the computer system; assigning physical design attributes including locations to a selected subset of the placeable objects, by executing third instructions in the computer system; visually displaying a layout abstract which shows the selected subset of the placeable objects at their assigned locations, by executing fourth instructions in the computer system; saving the circuit description with the assigned physical design attributes as a synthesis input file, by executing fifth instructions in the computer system; carrying out multiple concurrent optimizations for the circuit objects in a physical synthesis process for the integrated circuit using the synthesis input file, the logic description in the high-level description language, an input boundary, and input boundary timing assertions while maintaining fixed locations for the selected subset of placeable objects according to the assigned physical design attributes to generate a placement-optimized layout for the integrated circuit, by executing sixth instructions in the computer system; and routing interconnections between the circuit objects in the placement-optimized layout according to the logic description to generate a final layout for the integrated circuit, by executing seventh instructions in the computer system.