1. A method of making, including layout functions for, an integrated circuit, comprising: providing an integrated circuit design, said design including a plurality of cells and a plurality of interconnections between the cells, each cell having a one or more connection points; providing an integrated circuit die size and shape and defining within the die size and shape a layout area; globally optimizing a placement of all of the cells within the layout area based upon an objective function, wherein said step of optimizing assigns a location to each cell within the layout area and yields inter-cell physical distances for each pair of cells; defining each cell as a single-cell cluster; identifying neighboring clusters according to the placement; grouping pairs of neighboring clusters into larger multi-cell clusters having internal connections, external connections and a total number of included cells, by: selecting a pair of neighboring clusters which, if merged, would form a larger cluster with a relatively high degree of internal connectivity and a relatively low degree of external connectivity according to a single figure-of-merit for the larger clusters, selecting from multiple pairs of clusters which have the same figure-of-merit only that pair of clusters which has a least inter-cluster physical distance, whereby said least inter-cluster physical distance serves as a tie-breaker for selecting between the multiple pairs of clusters having the same figure of merit, and merging the selected pair of neighboring clusters into a larger multi-cell cluster and eliminating the pair of neighboring clusters, if the larger cluster has a total number of included cells which is less than a pre-defined number; repeatedly grouping pairs of clusters into larger clusters until a termination condition is met; completing a layout process based upon the integrated circuit design, the integrated circuit die size and shape, and die area partitioning and placement of the clusters of cells, said layout process resulting in an integrated circuit layout.