1. For use with an Instruction Unit of the type which receives macroinstructions over a memory bus from a main memory, interprets said macroinstructions, and issues memory-access types of microinstructions and arithmetic types of microinstructions; and for use with said main memory by transmitting and receiving data and addresses over said memory bus, an Execution Unit comprising: A. an access sequencer for sequencing a state machine through operations necessary to execute said memory-access types of microinstructions; a reference-generation unit connected to and controlled by said access sequencer, said reference-generation unit containing an arithmetic unit capable of generating and checking addresses in a main-memory address space for developing physical-memory addresses from logical-memory addresses contained in a memory-access microinstruction, for use in accessing said main memory over said memory bus, and for transfer to said instruction unit; a first state machine; means in said access sequencer for decoding a memory access microinstruction issued by said instruction unit; means in said access sequencer connected to said first state machine and to said means for decoding a memory access microinstruction for sequencing said first state machine through the cycles necessary for said reference generation unit to execute a function specified by said memory access microinstruction; B. a math sequencer for decoding an arithmetic type of microinstruction including means for sequencing a state machine through operations necessary to execute said microinstruction; a data-manipulation unit connected to and controlled by said math sequencer for performing arithmetic operations called for by said arithmetic-type of microinstruction issued by said instruction unit; said data manipulation unit containing registers and an arithmetic unit capable of performing arithmetic operations; a second state machine; means in said math sequencer for decoding an arithmetic microinstruction issued by said instruction unit; means connected to said second state machine and to said means for decoding an arithmetic microinstruction for sequencing said second state machine through the cycles necessary for said data-manipulation unit to execute a function specified by said arithmetic microinstruction; means in said math sequencer for signaling the instruction unit when the execution is complete; and, C. means connected to said access sequencer and to said math sequencer for distributing said microinstructions issued by said instruction unit to said means in said access sequencer for decoding a memory access microinstruction and to said means in said math sequencer for decoding an arithmetic microinstruction, to thereby enable an arithmetic microinstruction executable by said math sequencer to be separately decoded by said decoding means in said math sequencer to thereby provide for the commencing of immediate execution by said data manipulation unit, and to enable a memory-access microinstruction executable by said access sequencer to be separately decoded by said decoding means in said access sequencer to thereby provide for the commencing of immediate execution by said reference-generation unit.