1. A tile-based graphics processing pipeline in which a render output is divided into plural rendering tiles for rendering purposes, comprising: a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data; a tile buffer configured to store rendered fragment data for only part of the render output locally to the graphics processing pipeline prior to that data being written out to an external memory, the tile buffer storing data values for an array of sample positions of a rendering tile, with respective sets of the sample positions corresponding to and being associated with respective pixels of a rendering tile of an output data array that the rendered fragment data relates to; write out stage circuitry configured to write data stored in the tile buffer to an external memory; and programmable processing stage circuitry operable under the control of graphics program instructions to, for respective pixel positions of a rendering tile that rendered fragment data stored in the tile buffer represents, read rendered fragment data stored in the tile buffer for one or more sampling positions that are not associated with the pixel position in question, perform a processing operation using the rendered fragment data of the rendering tile read from the tile buffer to generate per-tile metadata that describes an aspect of the rendered fragment data of the rendering tile read from the tile buffer, and write the per-tile metadata that describes an aspect of the rendered fragment data of the rendering tile read from the tile buffer into the tile buffer or to an external memory.