1. A hardware stack, comprising: an instruction decoder generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a plurality of stack operations; a stack storage comprising a plurality of storage locations, each of the plurality of storage location being classified into one of at least two banks; and a stack pointer circuit for pointing to at least one of the stack banks of the stack storage in response to at least one decoding signal to thereby cause a stack operation.