1. A processor comprising: a first plurality of threads, each of said first plurality of threads comprising one of a second plurality of processing units; each of said first plurality of threads receiving a respective one of a third plurality of issue groups, wherein each of said respective one of said third plurality of issue groups belongs to a respective one of a fourth plurality of instruction packets; said processor executing said third plurality of issue groups in a single clock cycle, wherein each of said third plurality of issue groups is executed in a respective one of said second plurality of processing units.