1. A method for generating a biased layout for making an integrated circuit, comprising: (a) identifying a nominal layout defined by one or more cells, each cell having one or more transistors having transistor gate features with a nominal gate length; (b) identifying an annotated layout, the annotated layout itself provides information for identifying gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout; and (c) producing a biased layout by modifying the nominal layout using the information provided by the annotated layout, such that the biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout, the method implemented by a processor executing a program.