1. A computing machine comprising: a memory; a first computational node embodied in a first integrated circuit and a second computational node embodied in a second integrated circuit, each computational node configured to make requests for memory accesses for selected data to the memory via a stride parameter, the first and second computational nodes being heterogeneous from each other; a network coupled to the memory and the first and second computational nodes; and a memory controller node coupled to the memory and the network and configured to receive requests for memory accesses by the computational nodes to the memory for selected data stored in the memory and generate row and column memory addresses corresponding to stored data and use the stride parameter to access the requested data selected from some of the data stored at the row and column memory addresses from the requests.