1. A circuit for determining the number of Logic 1 bits in a group of N data bits comprising: an input stage of 4:3 carry-save adders, each of said 4:3 carry-save adders receiving four of said N data bits on four input lines and generating three sum bits (S 2, S 1, S 0 ) equal to a total number of Logic 1 bits on said four input lines, wherein said three sum bits have bit weights of S 2 &equals;4, S 1 &equals;2 and S 0 &equals;1, respectively; a first intermediate stage of 4:2 carry-save adders, each of said first intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said S 2 sum bits, said S 1 sum bits, and said S 0 sum bits and generating therefrom a carryout (COUT) bit, a carry (C) bit and a sum (S) bit; and a carry-propagate adder having a first input channel and a second input channel coupled to said first intermediate stage 4:2 carry-save adders and capable of generating a binary result equal to a total number of Logic 1 bits in said group of N data bits.