1. An analog pulse delay circuit comprising: an input line; a first flip flop (FF) having a set input, a reset input, and an output, the set input connected to the input line; a first field effect transistor (FET) having a gate, a source, and a drain, the gate connected to the output of the first flip flop; a first resistor capacitor circuit coupled to the drain and source of the first FET, and between a voltage and a ground; a first comparator connected to an output of the first resistor capacitor circuit and to a first voltage reference for comparing the output of the first resistor capacitor circuit and the first voltage reference, the first comparator having an output; an AND gate having a first input connected to the output of the first comparator and having a second input, and an output; an OR gate having a first input connected to the input line, a second input connected to an inverted output of the first FF, and an output; a second flip flop (FF) having a set input, a reset input, and an output, the reset input connected to the output of the OR gate, and the set input connected to an inverted output of the OR gate; a second field effect transistor (FET) having a gate, a source, and a drain, the gate connected to the output of the second flip flop; a second resistor capacitor circuit coupled to the drain and source of the second FET, and between the voltage and the ground; a second comparator connected to an output of the second resistor capacitor circuit and to the first voltage reference for comparing the output of the second resistor capacitor circuit and the first voltage reference, the second comparator having an output; and the output of the second comparator connected to the reset input of the first flip flop and an inverted output of the second comparator connected to the second input of the AND gate.