1. An input/output system for controlling input/output data transfer operations of a plurality of peripheral devices, said system comprising: a memory means; processor means, said processor means including means for generating commands during said data transfer operations involving said plurality of peripheral devices; multiplexer means; means interconnecting said memory means, said processor means and said multiplexer means for communiction on a priority basis; said multiplexer means including at least one adapter port coupled to said plurality of peripheral devices, said multiplexer means comprising: a plurality of registers arranged for storing interrupt control information transferred by said commands pertinent to the processing of said input/output operations by said multiplexer means; a first one of said registers containing coded signals specifying a numerical value used for identifying one of a plurality of interrupt routines executed by said processor means to process interrupt event signals received from said devices and a second one of said registers containing coded signals specifying numerical values for identifying a plurality of levels of priority to be given by said multiplexer means to said plurality of interrupt event signals received from said device; interrupt logic means coupled to receive said event signals from said adapter port; priority network means coupled to said logic means and to said second register, said priority means being operative to generate signals indicating the request having highest priority in accordance with interrupt event signals received from said logic means, said highest priority being defined in accordance with said values stored in said second register; and, output register means being operatively coupled to said priority network means and to said plurality of registers, said priority network means generating signals causing signals representative of the contents of said first register and one of said values stored in said second register corresponding to the event signal having the highest priority to be applied to said output register means for transfer to said interconnecting means as a part of an interrupt request.