1. An apparatus for coupling a memory device being addressable by means of an address space to a processing unit, the apparatus comprising: a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory device by said received memory address; a second memory access unit being adapted for receiving content data from said processing unit and for controlling a search for said received content data in said memory device; and an allocation unit for allocating a first part of said address space of said memory device to said first memory access unit and allocating a second part of said address space of said memory device to said second memory access unit.