1. A processor comprising: a prefetch unit configured to concurrently maintain a plurality of separate, active prefetch streams, wherein each of the plurality of prefetch streams is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations; and a data cache coupled to the prefetch unit, wherein the prefetch unit is configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.