1. A computer system, comprising: means for resolving a first target address for a first type of program branch instruction in a first stage of a multi-stage pipeline processor; means for resolving a second target address for a second type of program branch instruction in a later, second stage of said multi-stage pipeline processor, and such that more instructions will be put in the pipeline by an instruction fetch unit before said second target address was resolved compared to a resolution of said first target address; and means for inserting and filling a variable number of branch delay slots just after each program branch with useful instructions, wherein the number of branch delay slots for each case depends on it being a said first or second type of program branch instruction; wherein, processor performance is improving by using the number of branch delay slots that are really necessary for each type of program branch instruction.