1. In a computer system that includes decode logic responsive to encountered instructions having addresses, a branch prediction device comprising: a first level branch prediction cache (BPC) having a first number N1 of lines storing prediction information on up to N1 previously encountered branch instructions, each line in said first level BPC being configured to store an entry providing prediction information, said first level BPC being responsive to a first set of address bits of an encountered instruction, and enabling a given first level BPC entry to be output in the event that said first set of address bits and the given first level BPC entry satisfy a predetermined condition; and a second level BPC having a second number N2 of lines storing prediction information on up to N2 previously encountered branch instructions, each line in said second level BPC being configured to store an entry providing prediction information, said second level BPC being responsive to a second set of address bits of the encountered instruction and enabling a second level BPC entry to be output for use in the event that said predetermined condition is not met.