1. A data processing apparatus including a data processing unit having a given memory address space identified by an address field having a plurality of bits, a control memory connected to said data processing unit for receiving said plurality of bits and having registers addressable within a portion of said address space, a read/write memory connected to said data processing unit for receiving said plurality of bits and having registers addressable in a second portion of said address space, said read/write memory being divided into address zones requiring switching action by the data processing unit to address memory registers in various zones and a plurality of input/output registers connected to said data processing unit to be addressed thereby by said plurality of bits for being addressable in said memory address space common to predetermined ones of said address zones.