1. A signal processing apparatus, comprising: a channel pooling signal processor, including: a plurality of computation units; a test interface for testing the function of said plurality of computation units; a general purpose microprocessor for managing data flow into and out of said channel pooling signal processor; and an interconnect mechanism for connecting said plurality of computation units, said test interface, and said general purpose microprocessor; and a digital signal processor connected to said channel pooling signal processor; wherein said channel pooling signal processor performs more computationally intensive signal processing operations and said digital signal processor performs less computationally intensive signal processing operations.