1. A method, comprising: receiving a scan operation instruction; and in response to the scan operation instruction, performing a scan operation on a sequence of single-bit values using a parallel processor architecture with a plurality of processing elements; wherein each of the plurality of processing elements hold a single-bit value of the sequence of single-bit values; wherein the plurality of processing elements includes a first set of processing elements, a second set of processing elements, and a tree of adders that receives input from the first set of processing elements and delivers results to the second set of processing elements.