1. A computer system for instruction execution, the system comprising: a processor having a pipeline, wherein the system is configured to perform a method, comprising: fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions; for each of the plurality of branch instructions, assigning a branch uncertainty to each of the plurality of branch instructions; for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches; and balancing the instructions, based on a current summation of instruction uncertainty, in the pipeline.