1. In a microprogram-controlled processor which carries out macroinstructions by either execution of a series of microinstructions which are routed to the operation decoder or by direct routing of said macroinstruction to said operation decoder from the macroinstruction operation register, comprising: a control storage for storing a hardware control word which controls said direct routing of a macroinstruction, said hardware control word comprising a mode control bit and a plurality of direct control bits; a microinstruction operation register connected to said control storage for reading said hardware control word from said control storage and for generating control signals from said plurality of direct control bits contained in said hardware control word; first gating means coupled to said microinstruction operation register for outputting said generated control signals; and second gating means coupled to said macroinstruction operation register for directly routing said macroinstruction to said operation decoder; a mode latch connected to said microinstruction operation register, said mode latch being activated by said mode control bit having a preselected value indicating that a macroinstruction is to be directly routed to said operation decoder, said mode latch controlling said first and second gating means, whereby the execution of said macroinstruction is controlled by said control signals.