1. In a modular computer system including a plurality of individual processors, each having essentially the same structure and functional characteristics but capable of operating under different control programs, wherein each processor has its own instruction processing means, an arithmetic logic unit, storage means, and necessary address and data 1/0 registers the improvement which comprises error detecting means for indicating that any processor has a hard failure and means for transmitting a failure signal to a control means, bussing means including gating operable under control of said control means for selectively interconnecting the address and data registers of the storage means of each processor so that any processor may be functionally substituted for the storage means of its own or any other processor in the system; control means operative in response to a failure indicating signal from said error detection means to stop operation of the defective processor, interrupt the operation of a predetermined one of the non-defective processors and reconfigure said bussing means to connect the storage means of the defective processor to said predetermined non-defective processor and concurrently disconnect the storage means of the predetermined nondefective processor from said processor.