1. A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving bits of a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses, commencing with the start write address, which are applied to the decoder; and a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer.