1. A method of synthesis of a model representing a design of an integrated circuit, the method comprising: associating a test environment with a first model representing a design of an integrated circuit; wherein the first model includes a first signal; translating the first model of the design to a second model of the design; wherein the second model includes multiple signal parts that correspond to the first signal; generating an adaptor that creates the first signal from the multiple signal parts so as to adapt the second model to the test environment.