1. An apparatus for implementing processor verification testing with random content of program loops in random test generation for processor pre-silicon functional verification comprising: a processor, a constrained random test generator tangibly embodied in a non-transitory machine readable medium used in the processor verification testing; said processor implementing said constrained random test generator performing processor verification testing and generating random instructions in a program loop and implementing random content of program loops for the processor verification testing, said processor implementing said constrained random test generator performing the pre-silicon functional processor verification testing steps of: converging all random conditional branches to a main program loop using a converged branch instruction stream; enabling program interrupts to converge to the main program loop using a built in exception handling mechanism being provided in said constrained random test generator; allowing register based storage addresses to maintain a value using mandatory read only registers applied to said constrained random test generator; avoiding inherently problematic operations for the program loops using global class restriction mechanism applied to said constrained random test generator; and preserving storage addressability using machine state detection and restoration mechanisms; applying a functional result to a test case definition with each of said converged branch instruction stream, said built in exception handling mechanism, said mandatory read only registers; said global class restriction mechanism and said machine state detection and restoration mechanisms, and each in combination in said constrained random test generator, said predefined test definition including a memory logical address of the random conditional branch, and a target logical address of the random conditional branch; said processor performing the processor verification testing using said predefined test definition, generating random instructions for a processor execution path ending with an unconditional branch to the same memory logical address of the random conditional branch; and said processor using said predefined test definition ensures reliable generation of constrained random tests involving multiple iterations of the program loop for the processor verification testing.