1. A method of improving pre-route and post-route correlation for a design of an integrated circuit, the method comprising: performing an initial placement, a virtual routing, and a lower-effort actual routing for the design, the lower-effort actual routing providing more aggressive optimizations than the virtual routing; comparing results of the virtual routing and the lower-effort actual routing to identify nets having miscorrelation; defining patterns based on the nets having at least a predetermined miscorrelation; assigning net routing constraints to nets matching defined patterns; applying the net routing constraints to nets of the design with the defined patterns; using a computer, optimizing placement and performing a higher-effort actual routing of the design including nets with applied net routing constraints; and outputting a routed design.