1. A decoder comprising: means for performing a multi-input combinational logic NAND function; one or more 2-to-1 multiplexers; one or more inverters; and means for writing configuration bits into the select lines of said multiplexers; wherein one or more of the inputs of said means for performing a multi-input combinational logic NAND function is coupled to the output of one of said 2-to-1 multiplexers to which a single connection is coupled to inputs of said multiplexer, wherein one pathway is coupled to one of said multiplexer inputs and the other is coupled to one of said inverters to the other of said multiplexer inputs.