1. A data processing apparatus comprising: a register data store for storing data elements; an instruction decoder for decoding a constant generating, single instruction multiple data (SIMD) instruction, said SIMD instruction having an associated data value with a data portion and a control portion, said associated data value being encoded within said SIMD instruction; and a data processor for: performing SIMD data processing operations within parallel processing lanes on at least one source operand including multiple data elements corresponding to said multiple parallel processing lanes in response to a SIMD data processing instruction decoded by said instruction decoder such that a data processing operation specified by said decoded SIMD instruction is performed on each of the multiple data elements in the corresponding parallel processing lane; in response to said decoded constant generating SIMD instruction, expanding at least the data portion of said associated data value; and depending on a selected function, generating a constant forming said at least one source operand, wherein said data processor is configured depending on said selected function to replicate said data portion at different places within said constant, said control portion specifying at least one position within said constant where said data portion is to be replicated, and wherein replication of said data portion forms multiple constants with one of those constants for use in a SIMD data processing operation performed on each data element in multiple ones of the multiple processing lanes.