1. A processor comprising: a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine; a first microcode alias storage comprising a first plurality of microcode alias locations; a second microcode alias storage comprising a second plurality of microcode alias locations; a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is to: select a first one of a) the first microcode alias storage for storage of a first parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the first parameter location in one of the second plurality of microcode alias locations; and a first inheritance logic, coupled to an input of the second microcode alias storage, the first inheritance logic to determine whether to inherit the first parameter location from the first microcode alias location of the first microcode alias storage.