1. A cache memory control method in a multiprocessor system, formed by a plurality of processors respectively having cache memories, for executing a plurality of threads whose execution sequence is defined, wherein when a processor executing a thread writes data, said processor writes said data in a cache memory of said processor; when there is a cache line corresponding to a writing target address of said data, in said cache memory of said processor executing a thread positioned posterior to said thread in the execution sequence, said processor updates said cache memory; and when there is a cache line corresponding to the writing target address of said data, in said cache memory of said processor executing a thread prior to said thread in the execution sequence, said processor records that said processor executing said thread has written data into the cache line.