1. A memory device, comprising: at least one bank of memory cells; an addressing circuit coupled between external terminals and the at least one bank of memory cells; a data path coupled between external terminals and the at least one bank of memory cells; a command decoder coupled to external terminals, the command decoder being operable to generate control signals to control the operation of the memory device; and a processing system coupled to the at least one bank of memory cells, the processing system being operable to perform a processing function on data read from the at least one bank of memory cells to provide results data and to write the results data to the at least one bank of memory cells.