1. A processor having a datapath width for processing data received from a memory, the processor comprising: an instruction decoder for decoding an instruction and generating control signals therefrom; a plurality of datapath instances, each having a datapath width less than the processor datapath width and coupled to the instruction decoder and the memory, for retrieving data from, storing data to, and operating on data from the memory responsive to control signals received from the instruction decoder; a data transfer unit coupled to the plurality of datapath instances and the instruction decoder for transferring data among the plurality of datapath instances responsive to control signals received from the instruction decoder; and a register readable by an instruction decoded by the instruction decoder for indicating how many datapath instances are in the processor.