1. A sigma-delta circuit with a time sharing architecture comprising: a coefficient generation element used for generating coefficients for sigma-delta operations; a sigma-delta processing element used for executing sigma-delta operations according to the coefficients generated by the coefficient generation element; and a storage element used for storing results of the sigma-delta operations executed by the sigma-delta processing element; wherein the sigma-delta circuit is used for executing a plurality of orders of sigma-delta operations through the coefficient generation element, the sigma-delta processing element and the storage element.