1. An arithmetic processing apparatus comprising: a plurality of processors in which each of the plurality of processors has an arithmetic unit and a cache memory; at least one of the plurality of processors further including: an instruction port that holds a plurality of instructions accessing data of the cache memory, the plurality of instructions being executed out of order and being released in order; a first determination unit that receives an invalidation request for data in the cache memory in a state in which a load instruction held in the instruction port is completed and is not released, and validates a first flag when a cache index of a target address and a way ID of the received invalidation request match with a cache index of a designated address and a way ID of the load instruction; a second determination unit that validates a second flag when target data is transmitted due to a cache miss after a load instruction held in the instruction port undergoes the cache miss; and an instruction re-execution determination unit that instructs re-execution of an instruction subsequent to the load instruction held in the instruction port when both the first flag and the second flag are validated at the time of completion of an instruction held in the instruction port.