1. A processor, comprising: circuit to receive a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively; and one or more execution units to split the macro instruction into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand, and to execute the first micro instruction, and to execute the second micro instruction.