1. A computer system for a hardware transactional memory (HTM), the system comprising: a processor core configured to: set a mode register of the processor core of a computer to indicate a HTM mode; execute a plurality of transactions by the processor core in the HTM mode based on the mode register; determine whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode; and based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transition the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.