1. An integrated circuit comprising: a plurality of computational elements including a plurality of arithmetic nodes, a plurality of bit-manipulation nodes, a plurality of finite state machine nodes, and a plurality of input/output nodes; a first and a second processing node each having a core processor based on a common architecture; a first memory associated with said first processing node; a second memory associated with said second processing node; a first node wrapper for coupling said core processor of said first processing node to said first memory and to said computational elements; a second node wrapper for coupling said core processor of said second processing node to said second memory and to said computational elements; and means for interconnecting said computational elements and said first and second processing nodes to define a selected task to achieve a desired functionality.