1. An input/output bus bridge and command queuing system, comprising: an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responding with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands; said interrupt router including a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands; a first in first out (FIFO) command queue for ordering bus memory mapped input output (MMIO) commands; means for directing said EOI commands from said first command queue to the input of said FIFO command queue; first means for directing said EOI commands and MMIO commands from said command queue to an input output bus; second means for directing said INR and IRR commands from said second command queue to said input output bus; whereby strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.