1. A matrix-vector multiplication device comprising: a runtime programmable decoder for transforming processor-centric sparse matrix data directly into field-programmable gate array (FPGA)-centric matrix data without utilizing an intermediate representation of the matrix data by: determining that the processor-centric sparse matrix data is encoded in a sparse format; identifying which sparse format of a plurality of sparse formats that the processor-centric sparse matrix data is encoded in based on metadata associated with the matrix data; and transforming the processor-centric sparse matrix data directly into the FPGA-centric matrix data based on the identified sparse format; a plurality of data stream-first-in-first-out (FIFO) queues for managing a plurality of data streams for processing; a plurality of processing pipes for receiving the plurality of data streams from the plurality of data stream FIFO queues and processing data streams from among the plurality of data streams; and a vector memory for multiplexing the processed plurality of data streams into output data.