1. A system for implementing multi standard programmable low-density parity check decoder in a receiver, said system comprising: a control signal generation unit, generate pre computed control signals associated with a h-matrix; and a hardware decoder unit, wherein said hardware decoder unit comprises: a control signal storage unit, stores said pre computed control signals associated with said h-matrix; a LLR memory fetch & data align unit, obtains LLR bytes from a LLR memory unit, wherein a number of LLR bytes that are fetched from said LLR memory unit based on number of rows in a layer of said h-matrix; a rotation and aligning unit, performs a rotation on said LLR bytes to obtain aligned valid LLR bytes, wherein said aligned LLR bytes is communicated to a processing elements unit; said processing element unit, processes said aligned valid LLR bytes to obtain an output data, wherein said output data is an intermediate LLR value, wherein a number of processing elements are enabled based on at least one of (i) a number of rows in a layer, and (ii) a location of an active elements of said H-matrix within a current layer; a de rotation unit, de-aligns said output data of said processing element unit, wherein said LLR bytes are shifted in a reverse direction based on said rotation; and an output processing unit, generates an output LLR bytes based on a feedback from at least one diagonals and a input LLR values.