1. A digital computer system including processor means for processing digital data; microinstruction logic means for providing sequences of microinstructions for controlling said processor means; memory means for storing at least macroinstructions employed in controlling said system; and memory output bus means for conducting said at least macroinstructions from said memory means to said microinstruction logic means; said microinstruction logic means comprising: means for receiving and storing first certain ones of said macroinstructions for selecting operations to be performed by said processor means, each one of said first certain ones of said macroinstructions corresponding to an associated one of said sequences of microinstructions for controlling said processor means; microinstruction memory means for segmentally storing each microinstruction of each one of said sequence of microinstructions, wherein each said microinstruction is divided into a plurality of segments and each one of said segments is stored in a separate location in said microinstruction memory means, decoding means responsive to each one of said first certain ones of said macroinstructions for sequentially selecting each one of said segments of said each one of said microinstructions of said corresponding sequences of microinstructions; and means connected from said microinstruction memory means and responsive to operation of said decoding and selecting means for (1) sequentially receiving and storing said each one of said segments of said corresponding each one of said microinstructions, and (2) providing said corresponding sequences of microinstructions for controlling said processor means.