1. A data processing apparatus comprising: a processor operable to execute instructions, each instruction having micro-architectural state information associated therewith; comparator logic operable to compare said micro-architectural state information with predetermined micro-architectural state information associated with a problematic event and to issue a match signal if a match is detected; and trigger logic responsive to said match signal to provide one of a plurality of output signals, said trigger logic being programmable to determine which of said output signals is provided upon receipt of said match signal, each output signal being arranged to activate a corresponding mechanism to handle said problematic event.