1. A data processing circuit comprising: an execution circuit comprising a plurality of functional units; an instruction decoder coupled to the execution circuit for controlling the execution circuit according to successively executed instructions, the instruction decoder being operable in at least a first instruction mode and second instruction mode, instructions for execution in the first instruction mode including an instruction with respective fields for controlling each of the respective functional units, instructions for execution in the second instruction mode each containing no more than a field or fields for controlling a subset of the plurality of functional units; and a mode control circuit coupled to the instruction decoder, the mode control circuit being configured to control a selection between the first and second instruction modes for instructions executed following a jump command in an instruction in response to instruction mode selection information provided by the execution of the jump command.