1. A method for writing test data into a tag array and an instruction array of an instruction cache in a microprocessor, the method comprising: initiating an instruction fetch from a dummy address comprising: pushing the dummy address and a first state bit onto a stack used to hold procedure return addresses, the first state bit indicating a test mode; and executing a procedure return operation to initiate the instruction fetch from the dummy address; causing an instruction cache miss in response to the first state bit indicating the test mode, regardless of whether the dummy address hits the tag array; writing a dummy tag field of the dummy address into the tag array in response to the cache miss and a dummy instruction into the instruction array; and suppressing execution of the dummy instruction in response to the first state bit indicating the test mode.