1. A static random access memory, comprising: means for reading and writing a logic state in each of a plurality of groups of memory cells, said groups of memory cells having first and second pluralities of memory cell columns, each of said columns including at least one memory cell; means for retrieving data from each of said groups coupled between said first and second pluralities of memory cell columns; means for selecting one of said memory cell columns in each of said groups; and global decoder means for selecting any individual row of said memory cells in any of said groups of memory cells according to an address instruction executed by said global decoder means, wherein said global decoder means is centrally coupled to said groups of memory cells, and wherein said row contains at least one said memory cell.