1. A processor comprising: a mask register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the mask register corresponds to an element location in a vector; a decode stage to decode a first instruction specifying a vector source operand, the mask register, a vector destination operand and a vector destination offset location; and one or more execution units, responsive to the decoded first instruction, to: read a plurality of values in the first plurality of data fields of the mask register, the plurality of values being unmasked values; for a first value in the first plurality of data fields in the mask register, copy a corresponding first vector element from the vector source operand to a first adjacent sequential element location in the vector destination, the first vector element being at the vector destination offset location; wherein upon copying the corresponding first vector element from the vector source operand to an adjacent sequential element location in the vector destination, change the first value in the mask register from a first unmasked value to a-first masked value; for a second value in the first plurality of data fields in the mask register, copy a corresponding second vector element from the vector source operand to a second adjacent sequential element location in the vector destination; and upon copying the corresponding second vector element from the vector source operand to an adjacent sequential element location in the vector destination: change the second value in the mask register from a second unmasked value to a second masked value, the first masked value and the second masked value being used to track progress of a completion of the decoded first instruction; determine that the vector destination is full and store the vector destination to a memory; set the vector destination offset location to zero; and re-execute the first instruction using the first masked value, the second masked value, and the vector destination offset location to compress a third vector element.