1. A circuit to compare a first set of analog signals to a second set of analog signals, comprising: an analog difference computing array including N columns of analog differencing circuits, N+1 rows of analog differencing circuits with each row including a set of --N-- analog differencing circuits connected by a common integration line, said set of analog differencing circuits comparing said first set of analog signals and a subset of said second set of analog signals to generate analog difference signals that are applied to said common integration line, said rows of analog difference circuits thereby including a set of common integration lines each carrying analog difference signals; and a distance integration array comprising a set of distance integration circuits connected to said set of common integration lines to receive said analog difference signals and generate summation signals, each of said summation signals corresponding to the sum of differences of said analog difference signals applied to one of said common integration lines.