1. An apparatus comprising: a first group of memory cells coupled to a first access line and configured to store a plurality of first elements; a second group of memory cells coupled to a second access line and configured to store a plurality of second elements; and a controller configured to cause: the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line; and the plurality of first elements and the plurality of second elements to be compared in parallel.