1. A computer-implemented method comprising: receiving, by a processor, a design layout of an integrated circuit, the integrated circuit comprising at least one wafer; identifying, by a user through a graphical user interface, a critical pitch of the design layout; identifying, by the user through the graphical user interface, a set of design rules forming a design arc that is limited by the critical pitch; extracting, by the processor, a process variation and a plurality of failure mechanisms of the design layout, wherein the extracting is based at least in part on the critical pitch and based at least in part on the set of design rules, wherein a failure mechanism is a factor behind a design rule to reduce manufacturing defects and reduce wafer failure risks; performing, by the processor, a ground rule calculation based at least in part on the process variation and the plurality of failure mechanisms; assessing, by the processor, wafer failure risks by performing a simulation based at least in part on the ground rule calculation; revising the design layout as a revised design layout based at least in part on a type of the wafer failure risks, wherein the revised design layout reduces and minimizes the plurality of failure mechanisms instead of minimizing design rule violations; and manufacturing the integrated circuit using the revised design layout.