1. A processor comprising: one or more model specific registers (MSRs) to be configured in a first execution state to specify support of a user-level thread synchronization architecture for the processor; a plurality of execution cores having corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request; and a cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of a MONITOR request for an address from an execution thread of the user-level, to store the address and record an associated state of the monitored address state storage for a first execution core of the plurality of execution cores associated with the execution thread when said one or more MSRs is configured in the first execution state; and further responsive to receipt of an MWAIT request from the execution thread for the address, to record an associated wait-to-trigger state of the monitored address state for said first execution core associated with the execution thread; and wherein the first execution core is to transition the execution thread to an optimized sleep state responsive to the receipt of said MWAIT request from the execution thread when said one or more MSRs is configured in the first execution state.