1. A computer system, comprising: a program memory configured to store a program including a plurality of instructions, wherein each instruction includes at least two instruction portions and each instruction portion includes an associated identification bit; a decode unit configured to: decode instructions from said program memory, and transmit a first instruction portion to a first execution channel and a second instruction portion to a second execution channel, wherein said first execution channel and said second execution channel each includes at least one respective load/store unit, wherein each said respective load/store unit is directly coupled to a shared load/store memory and is configured to simultaneously compare at least two requested addresses of at least two data objects with two or more addresses held in said shared load/store memory; and a data cache, directly coupled to each said first and second execution channels, and configured to hold one or more data objects.