1. A multi-level flash memory device including an embedded micro-controller for executing algorithm codes stored in a read only memory, a plurality of digital to analog converters for programmably producing regulated biasing or control voltages required during various phases of operation of the non-volatile multi-level memory, a plurality of addressable configuration fuses to be permanently conditioned (burned) during a phase of testing of the device being fabricated, characterized by further comprising an ancillary random access memory for storing processed configuration data produced by the embedded microprocessor through the execution of a specific power-on algorithm at every powering on of the device or a repeatable test-mode power-on algorithm, processing configuration bits corresponding to a logic state of said configuration fuses.