1. An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies; an instruction scheduler adapted to: evaluate data dependencies between individual instructions in a received plurality of instructions; and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies; wherein the integrated circuit is operable in a first power mode and a second power mode, the second power mode being a reduced power mode compared to the first power mode, and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.