1. An apparatus for reducing replays in an out-of-order processor, the apparatus comprising: a first reservation station, coupled to a hold bus, configured to dispatch a first load micro instruction, and configured to detect and indicate on the hold bus if said first load micro instruction is a specified load micro instruction directed to retrieve an operand from one of a plurality of prescribed resources other than on-core cache memory, wherein said plurality of prescribed resources are shared by a plurality of cores of said out-of-order processor; replay reducer circuitry configured to evaluate an unmodified opcode portion of a load micro instruction that implicates a non-core resource, in order to detect said specified load micro instruction directed to non-core resources; a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if on said hold bus, in response to the detection by the replay reducer circuit, the first reservation station indicates that said first load micro instruction is said specified load micro instruction, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved said operand; load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction, wherein said load execution logic is also configured to enter a power savings state if no micro instructions are received for execution, and wherein, if said first load micro instruction is not said specified load micro instruction, said load execution logic indicates on a miss bus that said first load micro instruction fails to successfully execute when more than said first number of clock cycles are required to retrieve said operand, thus initiating a replay of said one or more younger micro instructions, and wherein, if said first load micro instruction is said specified load micro instruction, said load execution logic does not indicate that said first load micro instruction fails to successfully execute when more than said first number of clock cycles are required to retrieve said operand, thus precluding a replay of said one or more younger micro instructions; and said plurality of prescribed resources which are disposed outside of said plurality of cores, comprising: system memory, coupled to the out-of-order processor via a memory bus.