1. A data processing apparatus, the apparatus comprising: an input port for receiving a communication signal that contains temporally successive bits; an output port for outputting a data word formed from respective ones of the temporally successive bits; a programmable processor circuit coupled to the input port, the processor executing a plurality of series of programmed instructions in support of said receiving or said outputting, each at a time of reception of a respective one of the temporally successive bits, the processor circuit suspending operation each time after executing a respective one of the series of instructions; a synchronization circuit coupled to the processor circuit to trigger execution of respective ones of the series of instructions, each time at the time of reception of the respective one of the temporally successive bits, and, except for a last one of the series of instructions, prior to reception of one or more later bits that contribute to the data word.