1. An apparatus for instruction-level parallelism in a processing element, comprising: an instruction control unit; The apparatus of claim 7, wherein the instruction buffer comprises : a first instruction buffer coupled to said instruction control unit, the first instruction buffer configured to hold a the first instruction including a dependency indicator and being associated with a first thread; , and a second instruction buffer coupled to said instruction control unit, the second instruction buffer configured to hold a the second instruction including a dependency indicator and being associated with a second thread; a dependency counter coupled to said instruction control unit; ; and wherein an the execution switch is coupled to said instruction control unit, said first instruction buffer , and said second instruction buffer ; and an execution unit coupled to said execution switch; said instruction control unit configured to detect the dependency indicators and change the value of said dependency counter in response to detecting the dependency indicators and configured to disallow execution of the first instruction if said dependency counter includes a value less than a threshold value .