1. A data processing device comprising: a plurality of CPUs; and a plurality of memories corresponding to the CPUs, wherein when the CPUs issue requests for fetching instruction codes of different addresses from the corresponding memories, the instruction codes are supplied from the corresponding memories to the corresponding CPUs, wherein when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, the instruction code read from one of the memories by one access to the same address is supplied, in parallel, to the CPUs, and wherein when among the CPUs, M CPUs issue requests for fetching an instruction code of a same address and the other N CPUs issue requests for fetching instruction codes of addresses different from the address (M and N are positive integers), the instruction code read from one of M memories corresponding to the M CPUs by one access to the same address is supplied, in parallel, to the M CPUs, and from N memories corresponding to the N CPUs, the corresponding instruction codes are supplied to the corresponding CPUs.