1. A flash-memory sub-system comprising: a flash-memory array of physical blocks of flash memory identified by a physical-block address (PBA), a physical block having a plurality of pages, a page having a data sector that can be written with arbitrary data only once before requiring an erase of the physical block; wherein the data sector is block-addressable and not randomly-addressable, wherein all bytes of the data sector are accessible together as a block and not accessible as individual bytes; a data area formed from physical blocks of flash memory in the flash-memory array; wherein each page in the physical blocks stores host data from a host in the data sector for the page; a logical-sector address (LSA) received from the host, the LSA from the host being a host address for the host data from the host; a first-level volatile lookup table having a plurality of mapping entries, wherein each mapping entry in the plurality of mapping entries is for storing a PBA mapping to a physical block for a logical block address (LBA); a second-level volatile lookup table having a plurality of rows, wherein each row in the plurality of entries is for storing a plurality of page-valid bits that indicate when pages in a physical block contain valid data; and a modulo generator, receiving the LSA from the host, for performing a modulo operation on the LSA to generate a modulo remainder that identifies a selected page-valid bit in a selected row of the second-level volatile lookup table, the modulo generator also generating a quotient that is a LBA that is applied to the first-level volatile lookup table to select a selected mapping entry; the selected mapping entry for storing a PBA mapping indicating a selected physical block for storing host data identified by the LSA; wherein the PBA mapping from the selected mapping entry of the first-level volatile lookup table is applied to the second-level volatile lookup table to select the selected row in the plurality of rows, whereby the first-level volatile lookup table stores PBA mappings that select rows of page-valid bits in the second-level volatile lookup table.