1. A digital processor operating to decode and execute instructions, including compare and branch instructions, the digital processor comprising: a first storage for holding a target instruction; a second storage for holding a next in-line instruction; a multiplexer having inputs to receive the first and second storage; an execution unit to receive and decode the compare instruction to compare at least two values identified by the compare instruction to produce a true condition if the compare is successful and then to receive the branch instruction to assert a bypass control signal that is coupled to the multiplexer to select the target instruction for input to the pipeline when the condition is true.