1. A method for generating transition fault test patterns for a circuit design, comprising: obtaining a first circuit model corresponding to the circuit design; replicating the first circuit model to obtain a second circuit model; selecting a storage device within the first circuit model; disconnecting a data input of the storage device in the first circuit model; disconnecting a data output of a corresponding storage device in the second circuit model; coupling a driver of the storage device in the first circuit model to a portion of the second circuit model that was driven by the data output of the corresponding storage device in the second circuit model, wherein the first and second circuit models form a transformed circuit model; and using the transformed circuit model to generate transition fault test patterns for the circuit design.