1. A programmable chip, comprising; memory; a custom logic block operable to perform one or more custom instructions; a processor core coupled to memory, the processor core configured to receive an instruction sequence including supported and custom instructions, the processor core operable to call the custom logic block when a custom trigger instruction is identified while processing supported instructions simultaneously, wherein the processor core is an address generation unit and the custom logic block is a custom address generation unit configured to calculate zigzag scanning addresses for MPEG encoding; wherein the processor core distinguishes supported instruction from custom instructions by snooping a program counter address, wherein an address identifying a custom instruction to be detected is provided by a linker when a software program is compiled for execution on the processor core.