1. A processor for floating point underflow detection, comprising: circuitry to decode a first instruction, the first instruction when executed by the processor is to perform a fused multiply-add (FMA) operation; and a floating point unit including circuitry to: determine a non-normalized result of the first instruction based on a first input, a second input, and a third input; and determine whether underflow exists in the non-normalized result based on a first exponent of the first input, a second exponent of the second input, and a third exponent of the third input.