1. A semiconductor memory device that comprises a plurality of memory rows, where a said memory row comprises a plurality of memory cells and one row decoder, where a said row decoder comprises a plurality of MOS transistors and a plurality of row-select binary input signals, where the row decoder supports logic functions: when all the row-select binary input signals of the row decoder are turned on, the row decoder turns on its output signal to enable part of or all of the memory cells in the memory row to be available for memory read or memory write operations, when any one of the row-select binary input signals of the row decoder is turned off, the row decoder turns off its output signal, and when all the row-select binary input signals of the row decoder are turned off, the row decoder is placed into a power saving mode where the steady-state drain-to source voltage difference of every MOS transistor in the row decoder is set to zero, except for small voltage differences caused by none-ideal conditions.