1. A method to automatically synthesize a custom integrated circuit, comprising: a. receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; b. encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; c. receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; d. automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and e. synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication.