1. A quantum processor, comprising: a plurality of quantum devices arranged in a lattice; a first plurality of coupling devices, wherein a coupling device in the first plurality of coupling devices couples a first quantum device and a second quantum device in the plurality of quantum devices, wherein the first quantum device and the second quantum device are nearest neighbors in the lattice; and a second plurality of coupling devices, wherein a coupling device in the second plurality of coupling devices couples a third quantum device and a fourth quantum device in the plurality of quantum devices, wherein the third quantum device and the fourth quantum device are next nearest neighbors in the lattice.