1. A semiconductor device having a memory device, comprising: a substrate; a first plurality of memory cells disposed upon the substrate comprising: a first plurality of top electrodes comprising a first metal layer, wherein the first plurality of top electrodes spatially extend in a first direction; a first plurality of bottom electrodes comprising a second metal layer, wherein the first plurality of bottom electrodes spatially extending in a second direction, wherein the first direction and the second direction are different; a first barrier material layer disposed in intersection regions between the first plurality of top electrodes and the first plurality of bottom electrodes, wherein the first barrier material layer contacts the first plurality of bottom electrodes within the intersection regions; a resistive switching material layer disposed in the intersection regions, wherein the resistive switching material layer contacts the first barrier material layer within a first contact region; an active metal layer disposed in the intersection regions, wherein the active metal layer contacts the resistive switching material layer within a second contact region; and a second barrier material layer disposed in the intersection regions, wherein the second barrier layer contacts the active metal layer and contacts the first plurality of top electrodes within the intersection regions; a dielectric material layer disposed overlying the first plurality of memory cells; and a second plurality of memory cells disposed upon the dielectric material layer; wherein a size of the first contact region and a size of the second contact region are different.