1. An information processing apparatus comprising: one or more processors operable to: repetitively execute a plurality of execution processes corresponding to a plurality of instructions in parallel; control an issue timing of each of the plurality of instructions so that each of the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency; and transform an operand register address of each of the plurality of instructions in accordance with a predetermined increment value upon each repetition of the execution, wherein the operand register address is renamed when a value of an offset value register associated with an operand register is updated in accordance with the predetermined latency, and wherein the predetermined increment value is stored in an offset increment register to be added to the value of the offset value register upon each repetition of the execution.