1. In a field-programmable gate array, a random-access memory block comprising: a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations; at least two programmably invertible block-enable inputs; hardwired decoding logic having inputs coupled to the at least two programmably invertible block-enable inputs to selectively enable the random-access memory array by generating a block-enable signal at an output in response to a preselected combination of data signals presented to the at least two programmably invertible block-enable inputs; a gate having a first input coupled to the data output of the random-access memory array and a second input coupled to the output of the hardwired decoding logic and configured to pass the output of the random-access memory array only if the block-enable signal is present on the second input and if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.