1. A processor, comprising: a front end including a decoder, the decoder including circuitry to identify an end-of-live-range (EOLR) indicator, the EOLR indicator specifying an architectural register previously used in code and a location in the code at which the architectural register is no longer used; an allocator including: a finite state machine to scan a data structure for a mapping of the architectural register to a physical register in response to identification of the EOLR indicator by the decoder, the bounds of the scan being based upon information specified by the EOLR indicator; and circuitry to issue a reclamation request to disassociate the architectural register from the physical register in response to finding a mapping of the architectural register to the physical register; and a retirement unit including circuitry to disassociate the architectural register from the physical register, in response to the reclamation request.