1. An integrated circuit for a smart card comprising: at least one data terminal for providing communications with a host device over a system bus; and a processor configured to provide an attachment signal on the at least one data terminal for recognition by the host device, cooperate with the host device to perform an enumeration based upon at least one default descriptor, receive information from the host device regarding an allocation of system bus bandwidth to other devices communicating with the host device over the system bus, remove the attachment signal from the at least one data terminal and thereafter again provide the attachment signal on said at least one data terminal based upon the information regarding the allocation of system bus bandwidth to other devices, and cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor.