1. A circuit design synthesis method comprising: associating a first block of a circuit design with a first cell library; associating a second block of the circuit design with a second cell library; specifying at least one constraint upon the circuit design in its entirety; synthesizing the circuit design, including synthesizing both the first block and the second block, in the course of synthesizing the first block, mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and in the course of synthesizing the second block, mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.