1. A data processor comprising: an instruction decoding means which decodes an instruction and generates a branch displacement value and instruction length of a conditional branch instruction, an instruction execution means for executing instructions, including said conditional branch instruction, a displacement value bus which transfers the branch displacement value of said conditional branch instruction generated by said instruction decoding means, a program counter value calculation means having a first adder which adds a program counter value of said conditional branch instruction and the branch displacement value of said conditional branch instruction transferred from said instruction decoding means through said displacement value bus in order to calculate the program counter value for the branch target instruction of said conditional branch instruction, an address bus, which transfers the program counter value of said conditional branch instruction, a correction value bus, different from said displacement value bus, which transfers the instruction length generated in said instruction decoding means by decoding said conditional branch instruction, and an address calculation means coupled to said instruction execution means, said instruction execution means being different from said program counter value calculation means, said address calculation means having a second adder different from said first adder; said displacement value bus being coupled to said instruction decoding means and said program counter value calculation means, said address bus being coupled to said program counter value calculation means and said address calculation means and said correction value bus being coupled to said instruction decoding means and said address calculation means; wherein said address calculation means calculates the address of the next instruction after said conditional branch instruction by adding the program counter value for the conditional branch instruction transferred through said address bus from said program counter value calculation means and the instruction length of said conditional branch instruction transferred through said correction value bus from said instruction decoding means; wherein said branch displacement value is transferred to said program counter value calculation means at substantially the same time as said instruction length is transferred to said address calculation means; and wherein said address calculation means is coupled to a register file having one or more registers for holding operands.