1. A branch control apparatus in a microprocessor having an instruction cache, coupled to an address bus, for providing cache lines to an instruction buffer, the apparatus comprising: a target address of a branch instruction, said target address provided by a branch target address cache (BTAC); a wrap signal, provided by said BTAC, for indicating whether said branch instruction wraps across first and second cache lines; and an address register, coupled to said BTAC, for storing said target address; wherein if said wrap signal indicates said branch instruction wraps across said first and second cache lines, said address register provides said target address on the address bus to the instruction cache to select a third cache line, said third cache line containing a target instruction of said branch instruction.