1. An apparatus for storing configuration data in a programmable logic device having an array of memory cells arranged in rows and columns, the apparatus comprising: a means for addressing a selected column of memory cells, the addressing means being coupled to the array of memory cells; a first shift register having an input and a plurality of outputs for storing and shifting data, each output of the first shift register coupled respectively to a different row of memory cells of the array; a second shift register having an input and a plurality of outputs for storing and shifting data, each output of the second shift register coupled respectively to a different row of cells of the array; and parallel input means having a first data input, a second data input, a first data output and a second data output, the first and second data inputs coupled to receive data to be loaded in the memory cells, the first data output of the parallel input means coupled to the input of the first shift register and the second data output of the parallel input means coupled to the input of the second shift register.