1. An apparatus for testing an embedded memory in an integrated circuit, comprising: input logic comprising one or more memory-input paths coupled to respective memory inputs of the embedded memory; a memory built-in self-test (MBIST) controller; and at least one scan cell coupled between the input logic and the MBIST controller, and being selectively operable in a memory-test mode and a system mode, wherein the at least one scan cell inputs memory-test data from the MBIST controller and outputs the memory-test data through the input logic along at least one of the memory-input paths while operating in the memory-test mode.