1. A method of forming an integrated circuit (IC), comprising: providing a substrate comprising a logic region and a memory region including a select transistor region and an adjacent control transistor region; forming a charge trapping layer over the substrate within the control transistor region; forming oxide layers, a high-k gate dielectric layer and a polysilicon layer over the substrate; patterning the polysilicon layer, the high-k gate dielectric layer and the oxide layers to form a logic sacrificial gate stack within the logic region, a select gate stack within the select transistor region and a control gate stack within the control transistor region; and replacing the polysilicon layer within the logic sacrificial gate stack with a metal layer to form a metal gate electrode within the logic region; wherein forming the oxide layers comprises: forming and patterning a first oxide layer so that it remains within a first area of the logic region and so that it is removed from remaining areas of the logic region and the memory region; and forming and patterning a second oxide layer so that it is removed from a second area of the logic region and so that it remains within remaining areas of the logic region and the memory region.