1. A processor, comprising: a matrix of execution units including a first row of execution units and a second row of execution units, wherein the first row of execution units operate in parallel and the second row of execution units operate in parallel and in dependency upon the first row of execution units; a register file with multiple register segments to store instruction matrices results for subsequent processing by the matrix of execution units, wherein each instruction matrix of the instruction matrices includes a first row of instructions executed in parallel by a sub-set of execution units of the first row of execution units and a second row of instructions executed by a sub-set of execution units of the second row of execution units, wherein the register file is configurable for different execution modes, including: the multiple register segments forming a single register file where each register segment stores the sources and results of a Multiple Instructions Multiple Data (MIMD) super instruction matrix issuing four simultaneous instruction matrices where each individual instruction within each of the four simultaneous instruction matrices is a scalar or Single Instruction Multiple Data (SIMD); the multiple register segments forming individual independent register files with individual register state to support simultaneous processing of separate threads, wherein each instruction matrix is associated with a separate thread and a separate register file segment; and the multiple register segments forming a single thread register file, wherein register segments are duplicated in multiple segments of the register file to store the results of simultaneously executed non-dependent instruction matrices that are dynamically issued from a single thread instruction sequence.