1. An embedded system, comprising: a processing unit, simultaneously executing at least one first thread having a flag for performing a data acquisition operation and one second thread for performing a data process and output operation for acquired data in the data acquisition operation, wherein the flag is used for indicating that a state of the first thread is in one of an execution state and a sleep state; a memory coupled to the processing unit, providing a shared buffer for the at least one first thread and the second thread; a bus; and an integrated circuit for buffer management coupled to the memory and the processing unit through the bus, accessing the shared buffer, acquiring data from the shared buffer and writing the acquired data in the data acquisition operation to an external storage unit, and acquiring data from the external storage unit and writing the data acquired from the external storage unit to the shared buffer, wherein, the processing unit checks the flag before executing the second thread, wherein the second thread is executed when the flag indicates the sleep state while execution of the second thread is suspended when the flag indicates the execution state, wherein the integrated circuit for buffer management further comprises: a direct memory access (DMA) controller, generating an operation signal according to a usage status of the shared buffer and performing a DMA operation on the shared buffer through the bus; and a microcontroller coupled to the DMA controller and the external storage unit, accessing the external storage unit according to the operation signal; wherein the DMA operation is for acquiring data from the shared buffer and the microcontroller writes the data acquired from the shared buffer to the external storage unit when the operation signal is a data acquisition signal; and the DMA operation is for acquiring data from the external storage unit and the microcontroller writes the data acquired from the external storage unit to the shared buffer when the operation signal is a data storing signal, and wherein the shared buffer is further divided into a first buffer regarding as a buffer of the first thread and a second buffer regarding as a buffer of the second thread and when the usage status of the shared buffer indicates that the usage of the first buffer has exceeded a dedicated ratio for the first buffer, the DMA controller generates the data acquisition signal and acquires the data of the first buffer and the microcontroller writes the acquired data of the first buffer to the external storage unit; and when the usage status of the shared buffer indicates that the usage of the second buffer has lower than a dedicated ratio for the second buffer, the DMA controller generates the data storing signal and the microcontroller acquires data from the external storage unit, and the DMA controller writes the data acquired from the external storage unit to the second buffer.