1. A memory device, comprising: a first string of memory cells; a second string of memory cells; a data line coupled to a first end of the first string of memory cells and to a first end of the second string of memory cells; a source coupled to a second end of the first string of memory cells and to a second end of the second string of memory cells; a select gate coupled between the first end of the second string of memory cells and the data line; and a controller; wherein the controller is configured to cause the memory device to bias the data line to a first potential; wherein the controller is configured to cause the memory device to bias the source to a second potential, where the first potential is greater than the second potential; wherein the controller is configured to cause the memory device to deactivate the select gate by causing the memory device to bias a control gate of the select gate to a third potential, where the first potential is greater than the third potential; and wherein the controller is configured to cause the memory device to perform a programming operation on a selected memory cell of the first string of memory cells to increase a threshold voltage of the selected memory cell by causing the memory device to apply a programming potential to a control gate of the selected memory cell concurrently with causing the memory device to bias the data line to the first potential and concurrently with causing the memory device to bias the source to the second potential while the select gate is deactivated.