1. A computer system comprising: a processor with at least one load/store unit for loading and storing data objects, a decode unit for decoding instructions supplied to the decode unit from a program memory, wherein each instruction has at least one bit sequence defining a register address; a register file having a plurality of registers each having the same bit capacity and addressable via at least two register address ports, one of said ports being associated with a first execution channel of the computer system and the other of said ports being associated with a second execution channel of the computer system; a first register address supply path for supplying said at least one bit sequence to said one register address port; and at least one cache memory associated to the processor holding data objects accessed by the processor; said processor's load/store unit containing a high speed memory directly interfacing said load/store unit to the cache.