1. A multiple bit per cell memory device comprising: a command and address decode block connected to a command bus and an address bus; a data input/output (I/O) block connected to said command and address decode block and connected to a data bus; and a memory array of multiple bit memory cells connected to said command and address decode block and said data I/O block, wherein information states of said multiple 10 bit memory cells are mapped to a plurality of data bits and remaining information states of said memory cells are configured as invalid data states.