1. A cache memory system including a small-capacity cache memory which enables high-speed access and is provided between a processor and a main memory, comprising: a software cache controller which performs software control for controlling data transfer to the cache memory in accordance with a preliminarily programmed software; and a hardware cache controller which performs hardware control for controlling data transfer to the cache memory by using a predetermined hardware; wherein the processor causes the software cache controller to perform the software control but causes the hardware cache controller to perform the hardware control when it becomes impossible to perform the software control.