1. A method of optimizing a computer model of a digital circuit, said model including a data flow graph (DFG), comprising the steps of: determining a minimum bitwidth required for at least a portion of a directed path of said DFG responsively to a width of an output port of at least one operator, where said portion is in a fan-out direction relative to said output port; determining information content of inputs of an operator of said DFG; determining information content of an output port of said operator responsively to said information content of said inputs; reducing a bitwidth of a portion of said DFG responsively to said second and third steps of determining.