1. A memory control device that controls a memory from/to which data are read/written by a processor, the memory control device comprising: a clock switcher configured to receive a first clock and a second clock of which clock frequency is higher than that of the first clock, supply the first clock to the memory until the second clock becomes stable, and supply the second clock after the second clock has become stable; and a control signal switcher configured to start supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supply, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.