1. A computer system, comprising: a central processing unit with an internal memory controller; an external cache; a primary memory device; and a unified memory bus connecting said central processing unit, said external cache, and said primary memory device; wherein said internal memory controller controls said external cache and said primary memory device; and wherein said internal memory controller generates a memory address signal and a memory control signal for directly controlling said external cache and said primary memory device, said memory address signal and said memory control signal being applied to said unified memory bus during a memory access operation to simultaneously access said external cache and said primary memory device.