1. A processor, comprising: a front end to receive an instruction; a decoder to decode the instruction; a core to execute the instruction, including circuitry to: determine that the instruction will require strided data converted from source data in memory, the strided data to include corresponding indexed elements from a plurality of structures in the source data to be loaded into a same register to be used to execute the instruction; load source data into a plurality of preliminary vector registers, the source data to be unaligned as resident in the vector registers; apply blend instructions to contents of the preliminary vector registers to cause corresponding indexed elements from the plurality of structures to be loaded into respective interim vector registers; and apply further blend instructions to contents of the interim vector registers to cause further corresponding indexed elements from the plurality of structures to be loaded into respective source vector registers; and a retirement unit to retire the instruction.