1. A data decoder circuit, the data decoder circuit comprising: a plurality of variable nodes; a plurality of check nodes; a plurality of serial connections between the plurality of variable nodes and the plurality of check nodes; wherein the plurality of variable nodes and the plurality of check nodes are operable to send variable node to check node messages and check node to variable node messages as stochastic bit streams, wherein the plurality of variable nodes and the plurality of check nodes are operable to perform floating point operations based on the stochastic bit streams, and wherein the variable node to check node messages and the check node to variable node messages are passed iteratively between the plurality of variable nodes and the plurality of check nodes.