1. A cache control apparatus which controls a set-associative cache memory shared by a plurality of processors, wherein the cache memory includes a plurality of ways, and the ways are divided into groups each of which includes one or more of the ways, said cache control apparatus comprising a cache allocation control unit configured to perform a cache allocation process of allocating each of the ways to one or more of tasks which are executed by the processors, wherein in the case where one of the groups includes an unallocated way which is included in the ways and is not yet allocated to any of the tasks and a way which is included in the ways and is already allocated to one or more of the tasks each of which is executed by a corresponding one of the processors, said cache allocation control unit is configured to allocate the unallocated way included in the one of the groups to a corresponding one or more of the tasks each of which is executed by the corresponding one of the processors.