1. An apparatus comprising: a first integrated circuit and a second integrated circuit each comprising: a first phase-locked loop (PLL) formed on an integrated circuit die; a reference clock signal pin coupled to the first PLL by a first path of electrical length L1; a first PLL driver coupled to the first PLL; and a first PLL feedback pin coupled to the first PLL by a second path of electrical length L2, wherein L1.apprxeq.L2; wherein the first PLL driver of the first integrated circuit is coupled to the reference clock signal pin of the second integrated circuit by a first propagation path of electrical length L3.