1. An arithmetic processing device comprising: an arithmetic core, wherein the arithmetic core comprises: an instruction controller configured to request processing corresponding to an instruction; a memory configured to store lock information indicating that a locking target address is locked, the locking target address, and priority information of the instruction; and a cache controller configured to: receive, when executing a first instruction including locking of a first address in a cache memory from the instruction controller, a second instruction including moving data corresponding to the first address to the cache memory; determine whether the lock information is stored in the memory and whether a count value that is counted based on a clock signal from when locking of the first address in the cache memory reaches a threshold value; update the lock information in the memory when the count value reaches the threshold value; compare a first priority information in the memory and a second priority information corresponding to the second instruction when the lock information is stored in the memory and the count value does not reach the threshold value; and update the lock information in the memory when a second priority of the second priority information is higher than a first priority of the first priority information and not-update the lock information in the memory when the second priority is not higher than the first priority.