1. A method of a processor performing template-based classification of a circuit design, the method comprising: the processor reading a template file that defines a plurality of channel-connected-region (CCR) templates and super-CCR templates; the processor formatting a graph for each of the CCR templates and super-CCR templates; the processor identifying a plurality of CCRs based on a partitioned netlist file that defines a given circuit design; the processor generating a graph for each of the identified CCRs; the processor identifying a matching CCR template graph for each generated CCR graph; and the processor determining in an interative manner, for each formatted super-CCR template graph, all possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph.