1. A scan isolation and bypass architecture comprising core logic having a core logic input and a core logic output; an input isolation multiplexer having a first input, a second input, a selection input and an output, the input isolation multiplexer selectively providing one of the first and second inputs of the input isolation multiplexer to the output of the input isolation multiplexer based on the selection input of the input isolation multiplexer, the first input of the input isolation multiplexer being coupled to a functional input, the second input of the input isolation multiplexer being coupled to a functional output, the output of the input isolation multiplexer being coupled to the core logic input, and the selection input of the input isolation multiplexer being coupled to a first test select signal; an output isolation multiplexer having a first input, a second input, a selection input and an output, the output isolation multiplexer selectively providing one of the first and second inputs of the output isolation multiplexer to the output of the output isolation multiplexer based on the selection input of the output isolation multiplexer, the first input of the output isolation multiplexer being coupled to the core logic output, the second input of the output isolation multiplexer being coupled to the output of the input isolation multiplexer, the output of the output isolation multiplexer providing the functional output, and the selection input of the output isolation multiplexer being coupled to a second test select signal; wherein when the first and second test select signals indicate a core feedback test, the output isolation multiplexer passes the core logic output from the first input of the output isolation multiplexer to the output of the output isolation multiplexer as the functional output, and the input isolation multiplexer passes the core logic output from the second input of the input isolation multiplexer to the output of the input isolation multiplexer and the core logic input.