1. A data encoding circuit, the data encoding circuit comprising: a first stage data encoder circuit including a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value, and wherein the first stage data encoder circuit is operable to provide a first stage output; and a second stage encoder circuit including a second vector multiplier circuit operable to multiply a third interim value by a second sparse matrix to yield a second interim value, and wherein the second stage encoder circuit further includes a third vector multiplier circuit operable to multiply the data input by a third sparse matrix to yield the third interim value.