1. An apparatus for performing floating-point arithmetic operations comprising: a near processing path; a far processing path in parallel with the first path; an input data bus for providing first and second floating point operands to the near processing path and the far processing path substantially simultaneously, wherein each of the first and second floating point operands include a sign-bit, a mantissa, and an exponent, wherein the near processing path generates a plurality of exponent difference signals as a function of a pattern of exponents in the first and second floating point operands, wherein the near processing path generates a near path subtraction result based on the exponent difference signals, wherein the near processing path computes an exponent difference of the first and second floating point operands, and wherein the near processing path generates an exponent difference signal based on the computed exponent difference, and wherein the far processing path computes a mantissa difference of the first and second floating point operands, and wherein the far processing path generates a far path subtraction result based on the computed mantissa difference, if the computed exponent difference is not equal to 0, 1, or −1; and a final result multiplexer coupled to the near processing path and the far processing path that selects and outputs either the far path subtraction result, the near path subtraction result, or a standard result based on the generated exponent difference signal, wherein the standard result is selected based on a status of the near path or the far path subtraction result.