1. A synchronization unit with race avoidance capability in a system including multiple-slice, redundant loosely-coupled processors and memory, the synchronization unit comprising: a logical gateway that performs voted-write operations as a delegate for the processors which mutually compares data from the processors and resolves data discrepancies in write data among the processors in favor of a majority of the processors that agree and receives data and memory address information from the processors and writes resolved data to addressed memory as a delegate for the processors; and a logic that performs a delegated write action that delegates a write operation to the logical gateway, the logical gateway inserting the delegated write into a Direct Memory Access (DMA) stream at a time consistent for all processor slices whereby order of all delegated writes to each of a plurality of memories is identical.