1. A system for locating faulty logic on a semiconductor chip comprising: a scan channel having a plurality of logic elements that receive a test vector, generate a test vector result, and output the test vector result; a mask coupled to the scan channel and configured to control the test vector result based on a masking pattern; and a tester configured to: transmit the test vector to the scan channel; receive the test vector result from the scan channel; determine the masking pattern as a function of a failure rate of one or more faulty logic elements of the plurality of logic elements; implement the masking pattern using the mask; and compare the test vector result to a reference result based on a good chip.