1. A processor comprising: a hardware decoder to decode a user-level key generation assist instruction; and a hardware execution unit, responsive to the user-level key generation assist instruction, to modify a data operand including to: overwrite a second portion and a fourth portion in the data operand by copying a first portion to the second portion and copying a third portion to the fourth portion; concurrently perform a byte substitution on all bytes of each of the plurality of portions in the data operand; concurrently perform a rotate word on the first portion and the fourth portion; and concurrently perform an exclusive OR operation on the first portion and an immediate data and an exclusive OR operation on the fourth portion and the immediate data.