1. An encryption engine using two-way parity fault detection, the encryption engine including: a) an S-box/invert S-box (SBISB) processor implemented by at least one hardware device, having an input and an output; b) a first one-bit parity computer having an input and an output, the input coupled to the input of the SBISB processor, the first one-bit parity computer configured to compute the one-bit parity of the output of the SBISB processor based on the input to the SBISB processor; c) a first parity comparator implemented by at least one hardware device, having a first and second input and an output, the first input coupled to the output of the first one-bit parity computer and the second input coupled to the output of the SBISB processor, the first parity comparator configured to compare the output of the first one-bit parity computer to the actual parity of the output of the SBISB processor; d) a second one-bit parity computer having an input and an output, the input coupled to the output of the SBISB processor, the second one-bit parity computer configured to compute the one-bit parity of the input to the SBISB processor based on the output of the SBISB processor; and e) a second parity comparator implemented by at least one hardware device, having a first and second input, the first input coupled to the output of the second one-bit parity computer and the second input coupled to the input of the SBISB processor, the second parity comparator configured to compare the output of the second one-bit parity computer to the actual parity of the input of the SBISB; the encryption engine, further including, f) a shift rows/invert shift rows (SRISR) processor having an input coupled to the output of the SBISB processor and having an output; g) an encrypt/decrypt processor having an input coupled to the output of the SRISR processor and having an output; h) a mix column/invert mix column MCIMC processor having an input coupled to the output of the encrypt/decrypt processor and having an output; i) a third one-bit parity computer having an input and an output, the input coupled to the input of the MCIMC processor, the third one-bit parity computer configured to compute the one-bit parity of the output of the MCIMC processor based on the input to the MCIMC processor; j) a third parity comparator having a first and second input and an output, the first input coupled to the output of the third one-bit parity computer and the second input coupled to the output of the MCIMC processor, the third parity comparator configured to compare the output of the third one-bit parity computer to the actual parity of the output of the MCIMC processor; k) a fourth one-bit parity computer having an input and an output, the input coupled to the output of the MCIMC processor, the fourth one-bit parity computer configured to compute the one-bit parity of the input to the MCIMC processor based on the output of the MCIMC processor; and l) a fourth parity comparator having a first and second input, the first input coupled to the output of the fourth one-bit parity computer and the second input coupled to the input of the MCIMC processor, the fourth parity comparator configured to compare the output of the fourth one-bit parity computer to the actual parity of the input of the MCIMC processor.