1. A method of accommodating an interdependency between a first instruction and a second instruction within a pipelined instruction processor having a plurality of pipeline stages wherein said first instruction has a first index register field and said second instruction has a second index register field and wherein interdependency between said first instruction and said second instruction means that said first index register field and said second index register field are equal and non-zero, said first instruction and said second instruction being sequentially placed within a computer program for sequential execution by said pipelined instruction processor such that said first instruction is executed by a second stage of said pipelined instruction processor simultaneously with the execution of said second instruction by a first stage of said pipelined instruction processor, comprising: a. determining whether said first instruction is a skip instruction wherein the skip instruction is an instruction that conditionally prevents the execution of the second instruction when the second instruction is positioned in a pipeline stage directly following the pipeline stage of the first instruction such that the second instruction is the next sequential instruction for execution following the first instruction enabling said skip instruction to provide a program branch without requiring a second operand to specify a branch address; b. comparing said first index register field of said first instruction to said second index register field of said second instruction, the second instruction being positioned in a pipeline stage directly following the pipeline stage of the first instruction such that the second instruction is the next sequential instruction for execution following the first instruction; c. delaying said second instruction by a predetermined number of pipeline stages if said determining step determines that said first instruction is a skip instruction and said first index register field of said first instruction and said second index register field of said second instruction indicate an interdependence therebetween; and d. executing said second instruction without delay if said determining step determines that said first index register field of said first instruction and said second index register field of said second instruction do not indicate an interdependence therebetween.