1. A field programmable gate array, comprising: a programmable interconnect structure; and a plurality of logic cells, each said logic cell comprising: a first multiplexer comprising a first data input, a second data input, a select input and an output; a second multiplexer comprising a first data input, a second data input a select input and an output; a third multiplexer comprising a first data input connected to said output of said first multiplexer, a second data input connected to said output of said second multiplexer, a select input and an output; a first logic gate comprising a first input and a second input and an output, said output of said first logic gate connected to said select input of said first multiplexer; a second logic gate comprising a first input, a second input and an output, said output of said second logic gate connected to said select input of said third multiplexer; a third logic gate having a first input a second input and an output, said output of said third logic gate being coupled to said first data input of said first multiplexer; and a sequential logic element having a set input, a reset input and a data input, said data input being coupled to said output of said third multiplexer, wherein said first multiplexer, said second multiplexer, said third multiplexer, said first logic gate, said second logic gate, said third logic gate and said sequential logic element are all part of said logic cell.