1. A processor, comprising: an instruction decoder to decode an instruction, the instruction having a first operand, a second operand, a third operand, and a fourth operand, the first operand to specify a first storage location to store an accumulated value, the second operand to specify a second storage location to store a first value and a second value, the third operand to specify a third storage location to store a third value; and execution circuitry coupled to the instruction decoder to execute the decoded instruction to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of the third value to the accumulated value based on the fourth operand.