1. A non-transitory computer readable medium having instructions stored thereon that when executed by a computer performs a method of developing a clock distribution network for an integrated circuit, the method comprising: capturing sources of clock skew including timing mismatches between clock sinks; moving the clock sinks to a clock distribution network; synthesizing a behavioral description of the integrated circuit and said sources of clock skew to generate a 2D layout comprising the clock distribution network and combinational logic; separating said clock distribution network from said combinational logic and locating said clock distribution network to a first area of the integrated circuit; determining vias to provide via connections between the clock distribution network and the combinational logic, where the via connections are where the clock sinks were located before the step of moving the clock sinks; and floorplanning said combinational logic of said first area.