1. An apparatus comprising: a plurality of processor cores; comparison circuitry configured to compare data output from the plurality of processor cores; and an encoding module configured to encode received data by initially assigning a plurality of binary bit values to the plurality of processor cores, and based on at least one of a number of the plurality of processor cores and a first binary bit value of the plurality of binary bit values, adding a first additional binary bit to the first binary bit value, wherein the first binary bit value is assigned to a first processor core of the plurality of processor cores.