1. An arithmetic logic unit for use in a processor comprising, a memory having an address input accepting information bits which include two groups of bits each representing an operand and a bitindicating a mathematical function to be performed using the two operands, said memory having an output from which are read computation result bits from said memory indicating the result of the indicated mathematical operation involving the two operands, and including a first invalid computation result bit indicating if the result of the indicated mathematical operation read from said memory is invalid because the input information bits representing one or both of the operands do not represent a valid numerical digit, first means for selecting the ones of the information bits representing a first operand to be applied to the address input of said memory, second means for selecting the ones of the information bits representing a second operand to be applied to the address input of said memory, and storage means for storing the first invalid computation result bit read out onto the output of said memory, said first invalid computation result bit indicating to said processor that the result of the mathematical operation output from said memory is invalid because the information bits on the address input of said memory and indicating one or both of said operands do not represent a valid numerical digit.