1. A memory system comprising: a plurality of nonvolatile memory chips each having a plurality of memory banks which can perform a memory operation independent of each other; and a memory controller which can control to individually access each of said nonvolatile memory chips, wherein in the case of giving a write instruction designating an address to a nonvolatile memory chip and, after that, giving a write instruction designating another address to said nonvolatile memory chip, said memory controller can selectively instruct a simultaneous writing operation or an interleave writing operation, and wherein after giving a write instruction designating said another address to one of said plurality of nonvolatile memory chips, said memory controller can give a write instruction designating further another address to another nonvolatile memory chip in said plurality of nonvolatile memory chips.