1. A memory device comprising: first and second digit lines; first and second programmable resistance memory elements associated with a single memory cell for respectively storing complementary digit values of a data digit as different resistance values and determining the value stored in at least one of the first or second programmable resistance memory elements by discharging respective voltages through the first and second programmable resistance memory elements; first and second access devices for respectively coupling first and second programmable resistance memory elements to the first and second digit lines; and sense circuitry, respectively coupled to the first and second digit lines, for reading the data digit stored as a resistance value in one of the memory elements.