1. An apparatus, comprising: a memory; and first circuitry coupled to or comprised in the memory and configured to: receive a sequence of memory access requests for the memory, wherein the sequence of memory access requests is configured to access locations associated with entries in a matrix, wherein the first circuitry is configured with memory access constraints for the sequence of memory access requests; and grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.