1. A decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus comprising: a hard-decision decoder configured to perform hard-decision decoding, utilizing a processor, on a received word using a hard-decision decoding algorithm and output a hard-decision decoded word signal and, when a hard-decision decoding process fails, a hard-decision decoding failure signal; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding on a received word for which said hard-decision decoder has failed in the hard-decision decoding, indicated by the hard-decision decoding failure signal being inputted into the soft-decision decoder, a hard-decision decoder buffer configured to receive the hard-decision decoded word signal and delay the hard-decision decoded signal by a first delay time corresponding to the decoding time of one word by the soft-decision decoder; and a soft-decision decoder buffer configured to delay the received word by a second delay time corresponding to the decoding time of one word by the hard-decision decoder and output the delayed received word to the soft-decision decoder so that when the hard-decision decoder outputs a hard-decision decoded word signal corresponding to a first received word, the soft-decision decoder starts to receive the same first received word, wherein when the soft-decision decoder performs a soft-decision decoding, both the hard-decision decoder buffer and the soft-decision decoder output a decoded signal corresponding to a same received word substantially at the same time, wherein the soft-decision decoder receives a soft-decision received value signal and, when the hard-decision decoding process fails, the hard-decision decoding failure signal, and wherein, when the soft-decision decoder receives both, the soft-decision received value signal and the hard-decision decoding failure signal, the soft-decision decoder performs soft-decision decoding.