1. A processor comprising: instruction fetch circuitry to fetch CLFLUSH, LFENCE, and SFENCE instructions; instruction decoder circuitry to decode the CLFLUSH, LFENCE, and SFENCE instructions; a cache to store a cache line that is flushed from said cache in response to execution of the CLFLUSH instruction; and memory ordering unit circuitry to: prevent load instructions that follow the LFENCE instruction in program order from being dispatched until load instructions previous to the LFENCE instruction in program order have been performed; prevent store instructions that follow the SFENCE instruction in program order from being dispatched until store instructions previous to the SFENCE instruction in program order have been performed; and permit an LFENCE instruction that follows a previous SFENCE instruction in program order to pass the previous SFENCE instruction.