1. A multi-slice processor comprising: an instruction sequencing unit, a plurality of execution slices, and a plurality of load/store slices, wherein the multi-slice processor is configured to carry out: receiving, at a load/store slice from the instruction sequencing unit, an instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.