1. A method for maintaining inclusion of a processor pipeline, the method comprising: recording, for a first micro-op cache line, an instruction-cache way storing a first instruction corresponding to one or more micro-ops, generated by decoding the first instruction, and stored in the first micro-op cache line; updating, responsive to a micro-op cache hit at the first micro-op cache line, an instruction-cache in-use indication associated with the first instruction, said instruction-cache in-use indication associated with the first instruction being located at least in part through use of the instruction-cache way recorded for the first micro-op cache line; evicting the first micro-op cache line corresponding to the recorded instruction-cache way, and initiating a micro-op cache miss synchronization responsive to an eviction of the first instruction from the instruction-cache; and enqueuing a victim-cache deallocation micro-op following the micro-op cache miss synchronization.