1. A pixel clock generation device comprising: a high-frequency clock generation circuit generating a high-frequency clock; a transition detection circuit detecting a transition of a state of a pixel clock, and outputting a detection signal according to a timing of the detected transition; a control signal generation circuit generating a control signal according to said detection signal and phase data indicating a transition timing of said pixel clock; and a pixel clock control circuit causing the state of said pixel clock to transit according to said control signal.