1. A method comprising: selecting an operation to be performed by a circuit; representing, through a data flow graph having edges and nodes, a plurality of hardware components for performing the operation; simulating a plurality of solutions for performing the operation, each solution corresponding to a hardware component combination represented as a path on the data flow graph; determining a cost for each solution of the plurality of solutions, the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost; and selecting a solution from among the plurality of solutions, the selected solution having a lowest determined.