1. A co-processor for complex arithmetic processing, comprising: a complex arithmetic circuit that executes a complex arithmetic operation for complex data in accordance with an instruction from a primary processor, the complex arithmetic operation being required for radio communication; and a memory controller that operates in parallel with the complex arithmetic circuit, and accesses a memory, wherein the complex arithmetic circuit includes a trace circuit that monitors arithmetic result data for first complex data series sequentially read from the memory, and that detects a normalization coefficient for normalizing the arithmetic result data.