1. An integrated circuit memory device, comprising: a data latch having a data input, a control input and a clock input; and a strobe signal input buffer that is responsive to a data strobe signal and an indication signal and selectively passes an inactive-to-active transition of the data strobe signal to the control input of said data latch when the indication signal is active, but blocks passage of the inactive-to-active transition of the data strobe signal to the control input when the indication signal is inactive.