1. A Boundary Scan test apparatus for integrated circuits comprising, a plurality of Boundary Scan cells connected to functional pins of an integrated circuit chip, a test access port controller connected to dedicated Boundary Scan pins including TMS and TCK pins, an instruction register communicating with the test access port controller and connected to dedicated Boundary Scan pins including TDI and TDO pins, a boundary register, a bypass register, a plurality of test data registers and an address register all connected in parallel between the TDI and TDO pins, all of said registers communicating with the instruction register, said address register being loaded with an address that points to a specific one of the test registers, a software instruction set adapted for decoding by the instruction register, said instruction set having first instructions dependent on an address of a target test data register and second instructions which are independent of addresses and directed to specific registers not among the addressable test data registers, said first instructions including an additional instruction for the instruction register wherein the additional instruction augments a standard instruction set and accesses the address register, and wherein one of the test registers is selected to be accessed, the selected test register being determined by the address loaded in the address register when the additional instruction is executed.