1. A signal processor designed to execute variable-sized instructions that may comprise up to N elementary instruction codes, the processor comprising: a memory program comprising I individually addressable, parallel-connected memory banks, I being at least equal to N, wherein the codes of a program are recorded in interlaced fashion at the rate of one code per bank and per address applied to the bank, means for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction, a cycle for reading an instruction in the program memory comprising the reading of a sequence of codes that comprises the instruction code or codes to be read and can also, when the number of codes of the instruction read is smaller than I, comprise codes belonging to a following instruction.