1. A cache system, comprising: a processor chip receiving a processing unit address; a comparing device comparing the processing unit address to at least a portion of an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the portion of the address information, a mapping device mapping the portion of the address information of an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory of the processor chip; a stacking loop searched in groups of allocated tags, in which each tag in each group of allocated tags is ordered in the stacking loop based at least in part on a most recently used tag in the group of allocated tags when the processing unit address matches the portion of the address information; and a data memory address generator generating a data memory address corresponding to an allocated location in the data memory temporarily storing the external memory data when the processing unit address matches the portion of the address information, the tag memory updating at least the portion of the address information and a data memory address corresponding to the allocated data memory subset and the corresponding data memory set when new external memory data is fetched from an external memory.