1. An apparatus for fast remote communication and computation between processors, comprising: a first processor in a multiprocessor data processing system, the first processor being a remote processor; a direct core to core communication unit (DCC) configured to operate with the remote processor; and a memory associated with the DCC, wherein the memory operates at a hierarchical level of one of (i) level-1 of a processor-cache and (ii) level-2 of the processor-cache in a cache hierarchy of the remote processor, wherein a first area of the memory is configured as a first address space accessible only to the remote processor and a second area of the memory is configured as a second address space accessible by a second processor in the multiprocessor data processing system, wherein the second processor gains access to the second area of the memory using an address from the second address space, the memory receiving from the second processor a set of bytes in the second area at the address from the second address space, the set of bytes comprising (i) an operation to be performed at the remote processor and (ii) a context for the operation, wherein the context comprises an encoded reference to an address space of the second processor wherein the reference is used in executing the operation at the remote processor, and wherein the remote processor executes an operation using the context.