1. A data sensing apparatus, being configured to sense read-out data of a memory apparatus, comprising: a sensing reference voltage generator, receiving a reference voltage, generating a reference current according to the reference voltage and a control signal, and generating a sensing reference voltage according to the reference current; a sensing reference current generator, coupled to the sensing reference voltage generator, receiving the sensing reference voltage, and generating a sensing reference current according to the sensing reference voltage and the control signal; and a sense amplifier, having a first input end being coupled to the sensing reference current generator and a second input end being coupled to a selected memory cell of the memory apparatus, receiving the sensing reference current and a read-out current from the selected memory cell, and sensing a current difference between the sensing reference current and the read-out current to generate the read-out data,. wherein the sensing reference voltage generator comprises: an operation amplifier, having a first input end receiving the reference voltage; a first transistor, having a first end receiving a power voltage, a control end coupled to an output end of the operation amplifier; a diode, having an anode being coupled to a second end of the first transistor, a cathode coupled to a second end of the operation amplifier, wherein the sensing reference voltage is generated at the anode of the diode; and a first variable resistor, coupled between the cathode of the diode and a reference ground, wherein a resistance of the first variable resistor is determined by the control signal, wherein the first variable resistor comprises: a plurality of switches and a plurality of resistors, wherein the switches are coupled in series between the cathode of the diode and the reference ground, the resistors are coupled in series between the cathode of the diode and the reference ground, and the switches are respectively coupled to the resistors in parallel, wherein, the switches are respectively controlled by a plurality of bits of the control signal.