1. A processor comprising: one or more vector registers each comprising a plurality of data fields to store values of vector elements; a decode stage to decode a first instruction specifying: a first operand specifying a first vector register of the one or more vector registers, a second operand specifying a second vector register of the one or more vector registers, a third operand, and a size of the vector elements associated with the one or more vector registers; and an execution unit, responsive to the decoded first instruction and for each data field of the plurality of data fields, to: read a first, a second and a third value respectively from corresponding data fields of the vector registers, based on the size of the vector elements, in the first, the second and the third operand; compute a first interpolated value for the vector elements as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value; read a fourth, a fifth and a sixth value respectively from corresponding data fields of the vector registers, based on the size value of the vector elements, in the first, the second and the third operand; and compute a second interpolated value for the vector elements, in parallel with computing the first value multiplied, as the fourth value multiplied by the fifth value minus the fifth value multiplied by the sixth value plus the sixth value.