1. A decode unit for a processor, comprising: an input for an element of machine code representing an instruction; and circuitry configured to determine whether an opcode identifier portion of the element of machine code identifies a virtually encoded instruction, responsive to the opcode identifier portion identifying a virtually-encoded instruction, using both the opcode identifier portion and at least part of a remaining portion of the element of machine code to decode the element of machine code into data defining an executable operation for execution on an execution unit coupled with the decode unit, and otherwise decoding the element of machine code into data defining an executable operation using the opcode identifier portion of the element of machine code.