1. An energy-efficient nonvolatile microprocessor, comprising: a processing core having a plurality of system states divided into programmer visible states and programmer invisible states; a nonvolatile flip-flop array for storing data, wherein the stored data is maintained after a power source is off; and a set of nonvolatile interconnections connected between the processing core and the nonvolatile flip-flop array, wherein the processing core only stores the programmer visible states into the nonvolatile flip-flop array through the nonvolatile interconnections when the power source is unstable.