1. A method for full integrated circuit (IC) mask pattern generation, comprising: generating, by a processor, an initial mask image from target polygons; performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels; determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization; generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information; and generating optimized mask patterns based on a localized polygon optimization of the mask.