1. A processor having a modular organization, comprising: at least one local store operable to store data and instructions for execution; at least one functional unit operable to execute instructions on data provided from said at least one local store; and at least one issue logic unit operable to convert the instructions provided from said at least one local store into operations of said at least one functional unit for executing the instructions, each of said at least one issue logic unit being operable to control execution of the instruction by one or more of said at least one functional unit according to a common instruction set, such that when said processor includes a plurality of said functional units, said at least one issue logic unit is operable to decode a unitary instruction of the instructions provided from said at least one local store to simultaneously operate all of said plurality of functional units according to said unitary instruction, and to decode multiple instructions to separately operate first and second subsets of said plurality of functional units, each said subset being operated according to a respective one of said multiple instructions.