1. A method for performing a trimmed verification analysis in an integrated circuit (IC), the method comprising: selecting IC layer definitions of interest and additional device structure descriptions of interest; creating a rundeck including the selections; analyzing the created rundeck, wherein the analyzing comprises: selecting a geometric design system file from the created rundeck; extracting a layout netlist from the geometric design system file; selecting a schematic netlist from the created rundeck; and comparing the schematic netlist with the layout netlist; and generating an error report based on a result of the analysis.