1. A method of implementing an integrated circuit using one of a plurality of configuration bitstreams for a design implemented in the integrated circuit, the method comprising: generating, by a computer, a plurality of implementations of the design; analyzing the plurality of implementations of the design to determine initial variations in timing among the implementations; modifying at least one implementation of the plurality of implementations to reduce the variations in timing among the plurality of implementations; and outputting a plurality of configuration bitstreams for the plurality of implementations having variations in timing that are reduced relative to the initial variations in timing.