1. An integrated circuit, comprising: a plurality of tiles, each tile comprising a processor; a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and the plural data paths to couple switches of the plurality of tiles; a plurality of memory interface modules including circuitry to access copious external memory, each memory interface module coupled to a switch of at least one tile with a processor on at least one of the tiles configured to flush data resident in caches on that tile to copious memory and a processor of at least one of the plurality of tiles is further configured to: execute a ping operation that sends a ping packet over an network interconnection to one or more copious memory controllers to determine status of previous memory transactions, with the ping operation comprising a memory ping synchronization primitive to determine the status of the previous memory transactions.