1. In a data processing system having a pipeline mechanism, said pipeline mechanism comprising: instruction fetch means for fetching a predetermined number of units of instruction data, including variable length instructions to be executed by said data processing system, from a storage means; instruction decoding means for decoding the instruction data fetched by said instruction fetch means to generate control information for instruction execution; an instruction bus, having first and second portions and connecting said instruction fetch means and said instruction decoding means, for transferring first and second parts of said predetermined number of units of fetched instruction data to said decoding means; and instruction execution means, which includes plural operation units comprising an ALU and a sub-ALU, for executing the instruction according to said control information; wherein said instruction decoding mean comprises: first decoding means, coupled to the first portion of said instruction bus, for issuing a first signal indicating whether a preceding instruction is transmitted on said first portion and a part of a following instruction is transmitted on said second portion of said instruction bus and for generating first control information, including first operand register identification information identifying a first operand register and first operand register rewrite information indicating whether said first operand register is rewritten when said preceding instruction is executed, said first control information for controlling the execution of said preceding instruction in said instruction execution means; second decoding means, coupled to the second portion of said instruction bus, for generating second control information, including second operand register number information identifying second operand registers and second operand register referral information indicating whether said second operand registers are referred to during the execution of said following instruction, said second control information for the execution of said following instruction in said instruction execution means and for issuing a valid signal indicating that the following instruction can be executed utilizing the sub-ALU; and judging means, coupled to said first and second decoding means to receive said first and second control information and said first and valid signals, for generating a validity signal when each operand register referred to by said following instruction is not rewritten by the preceding instruction, and each of said preceding and following instructions is able to be executed by a different operation unit among said plural operation units; whereby said instruction execution means executes in parallel said preceding and said following instructions only when said validity signal is generated and executes each instruction successively otherwise.