1. A microprogrammable CPU for a computer capable of performing a repertoire of macro instructions, said computer including main memory mains for storing macro instruction words corresponding to macro instructions to be performed by said computer, each macro instruction being executable by a plurality of micro operations, comprising main memory addressing means for addressing said main memory means to fetch macro instruction words therefrom for execution by said computer, macro instruction register means for receiving macro instruction words fetched from said main memory means by said main memory addressing means, control storage addressing means coupled to said macro instruction register means for providing micro routine addressing signals in accordance with the contents of the macro instruction word fetched into said macro instruction register means, control storage means for storing a plurality of micro routines for performing said macro instructions of said repertoire, respectively, each said micro routine comprising micro instruction words capable of controlling a plurality of said micro operations, said control storage means being responsive to said micro routine addressing signals for addressing the micro routine corresponding to said macro instruction word fetched into said macro instruction register means and for simultaneously providing a plurality of said micro instruction words of said micro routine addressed by said micro routine addressing signals, and a plurality of processor means coupled to said control storage means, each said processor means including arithmetic and logic unit means and local memory means intercoupled in said processor means for performing said plurality of micro operations, said plurality of processor means being responsive, respectively, to said plurality of micro instruction words simultaneously provided by said control storage means in response to said micro routine addressing signals for controlling said plurality of processor means to simultaneously perform a respective plurality of said micro operations in response to the contents of said respective micro instruction words simultaneously applied thereto in execution of said macro instruction word fetched into said macro instruction register means, said macro instruction words fetched into said macro instruction register means from said main memory means comprising, in operation of said computer, a stream of macro instructions flowing through said macro instruction register means, said plurality of micro instruction words applied simultaneously from said control storage means to said plurality of processor means, respectively, comprising a plurality of micro instruction streams flowing simultaneously through said plurality of processor means, respectively, said main memory means, main memory addressing means, macro instruction register means, control storage means and plurality of processor means in combination, in response to said main memory addressing means fetching said macro instruction words into said macro instruction register means, being operative for executing said stream of macro instructions flowing through said macro instruction register means by decomposing said stream of macro instruction into said plurality of micro instruction streams flowing simultaneously through said plurality of processor means, respectively.