1. An instruction fetch control apparatus controlling instruction fetch in an instruction control device having a cache memory unit, a lower memory unit, and an execution unit speculatively executing an instruction sequence stored in the cache memory unit, comprising: an instruction fetch unit issuing an instruction fetch request to the cache memory unit; and an instruction prefetch unit prefetching an instruction by preliminarily transferring a predetermined instruction sequence from said lower memory unit to said cache memory unit when the instruction sequence which is to issue a fetch request is not contained in said cache memory unit.