1. A programmable logic device (PLD), comprising: (a) input/output (I/O) circuitry; (b) programmable core logic; (c) memory; (d) one or more standard-cell logic blocks (SLBs); (e) general routing resources providing programmable connections between the I/O circuitry, the programmable core logic, and the memory; and (f) SLB routing resources providing programmable connections between (1) each SLB and (2) any of the I/O circuitry, the programmable core logic, and the memory, such that the SLB routing resources can be programmed to insert each SLB into a signal transfer path between (A) any of (i) the I/O circuitry, (ii) the programmable logic core, and (iii) the memory and (B) any of (i) the I/O circuitry, (ii) the programmable logic core, and (iii) the memory.