1. A branch prediction apparatus in a processor including address selection logic for providing a fetch address to an instruction cache, the fetch address used to select lines of the instruction cache, the apparatus comprising: first and second branch predictors, for providing first and second target address predictions of a branch instruction to the address selection logic; instruction decode logic, configured to receive and decode said branch instruction and to generate a type thereof; and branch control logic, configured to control the address selection logic to select said first prediction as the fetch address, said first prediction selecting a first line of the instruction cache; wherein said branch control logic is further configured to subsequently selectively control the address selection logic, based on said branch instruction type, to select said second prediction as the fetch address, said second prediction selecting a second line of the instruction cache.