1. A processor architecture comprising: a systolic matrix including a plurality of rows and a plurality of columns, wherein each of the plurality of columns includes a Very Long Instruction Word (VLIW) computational part providing control signals and instruction flow management, and a plurality of processing elements as a vertical structure, the plurality of rows being formed by replicating the plurality of processing elements associated with each of the plurality of columns in a horizontal direction according to either a vectorial type or a multiple scalar instruction type operation approach, wherein each processing element includes a number of associated arithmetic-logic units including configuration according to a Simple Instruction Multiple Data (SIMD) paradigm that receives the same input signals; a first set of multiplexers selects either a vectorial instruction propagation or a scalar instruction to be packed into a current cycle, and a second set of multiplexers recycles the scalar instructions; and a power-management unit to power a selective number of said processing elements and to selectively control power consumed by each processing element in said matrix and wherein said power-management unit is to scale relative frequency of operation of each processing element so as to render uniform processing time of each of the plurality of columns and balance computational burden on powered processing elements; wherein the VLIW computational part comprises a configuration of Reduced Instruction Set Computer (RISC) type processor by setting instruction parallelism to one.