1. A system comprising: write circuitry configured to implement a write finite state machine selected from a plurality of write finite state machines; read circuitry configured to implement a read finite state machine selected from a plurality of read finite state machines; and a multi-port memory coupled to the write circuitry and the read circuitry, wherein the multi-port memory is a bit-addressable memory comprising a write port controlled by the write circuitry and a read port controlled by the read circuitry, wherein the write circuitry and the read circuitry are configured to implement the selected write finite state machine and the selected read finite state machine to perform one of a plurality of different data transformations using the multi-port memory, and wherein the write port is controlled by a first clock signal and the read port is controlled by a second clock signal that is different from the first clock signal.