1. A processor capable of executing a multifunction instruction comprising: a plurality of registers; and a multifunction instruction execution circuit, wherein: the multifunction instruction execution circuit moves a plurality of operands in a corresponding plurality of formats into a corresponding plurality of registers from a common location in response to a single execution of the multifunction instruction; wherein: a first one of the corresponding plurality of formats is an integer encoded in memory in an unsigned byte format, a second one of the corresponding plurality of formats is an integer encoded in memory in a signed byte format, and a third one of the corresponding plurality of formats is generated by the processor by inserting a fixed number of bits from the common location into a fixed location in a third one of the corresponding plurality of registers.