1. A system to perform an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design, the system comprising: a memory device configured to store instructions and information; and a processor configured to execute the instructions to execute a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, determine a quality measure associated with each of the two or more scenarios, and perform the intra-run decision to eliminate one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.