1. A processor system having an interstream control arrangement, comprising: a plurality of hardware streams for streaming one or more instruction threads; a supervisory thread configured to run in an active stream of the plurality of hardware streams; and a subservient thread configured to run in an available stream of the plurality of hardware streams in parallel with the supervisory thread, wherein the system is configured to enable the supervisory thread, during execution, to set-up and start the subservient thread in the available stream.