1. An omni-protocol data packet processing engine for managing communication of data packets between a computer processor and a high speed network fabric having a line speed of at least 10 Gb/second, the omni-protocol data packet processing engine comprising: an ingress portion of the data packet processing engine, including: a first plurality of bit-stream stage processors, each bit-stream stage processor having a programmable control memory unique to that bit-stream stage processor; an ingress processor-interface to the computer processor; an ingress network-interface to the network fabric; and a first multi-port data flow packet memory operably coupled to the first plurality of bit-stream stage processors, the ingress processor-interface, and the ingress network-interface; and an egress portion of the data packet processing engine including: a second plurality of bit-stream stage processors, each second bit-stream stage processor having a programmable control memory unique to that bit-stream stage processor; an egress processor-interface to the computer processor; an egress network-interface to the network fabric; and a second multi-port data flow packet memory operably coupled to the second plurality of bit-stream stage processors, the egress processor-interface, and the egress network-interface; wherein the control memory of each of the bit-stream stage-processors is individually selectively dynamically programmable based on one of a plurality of protocols determined for a given data flow of one or more data packets and the bit-stream stage-processors process the given data flow as a flow of bit stream data through the multi-port data flow packet memory such that processing of the given data flow by the plurality of bit-stream stage processors is timed according to the flow of bit stream data and the flow of bit stream data is established at a rate that enables continuous operation of the data packet processing engine for all of the plurality of protocols substantially at a speed that is at least equal to the line speed of the high speed network fabric, and wherein each of the bit-stream stage processors is configured to programmed to deliver a bit-stream functionality and interconnect with other bit-stream stage processors, such that the bit-stream functionality of a single stage is deliverable within a dwell time that does not exceed a time interval elapsing between the arrival of two consecutive data packets from the high speed network fabric.