1. A memory device comprising: a plurality of memory cells, memory cells in the plurality of memory cells comprising a bottom electrode, a memory element over the bottom electrode, the memory element having a top surface, a dielectric fill over the top surface of the memory element, and a top electrode extending through a via in the dielectric fill and including a stem portion, wherein a base of the stem portion of the top electrode is in electrical contact with a contact area on the top surface of the memory element; and wherein the vias of the memory cells have via widths adjacent the top surfaces of the memory elements, the via widths having a first variation in magnitude across the plurality of memory cells, and the bases of the stem portions of the top electrodes of the memory cells have base widths less than the via widths, the base widths having a second variation in magnitudes across the plurality of memory cells, the second variation being smaller than the first variation.