1. A processor comprising: a plurality of cores; a level 1 instruction cache to cache instructions; a level 1 data cache; a bus interface unit; a plurality of 128-bit registers; a decode unit to decode the instructions from the level 1 instruction cache including four Advanced Encryption Standard (AES) instructions of an instruction set of the processor, wherein each of the four AES instructions has a unique opcode, the four AES instructions to be decoded by the decode unit including: a first AES decryption instruction that is to use a 128-bit source and destination register of the plurality of 128-bit registers and a 128-bit source register of the plurality of 128-bit registers, and a second AES decryption instruction that is to use a 128-bit source register of the plurality of 128-bit registers and a 128-bit destination register of the plurality of 128-bit registers; and an execution unit coupled to the decode unit, wherein: the first AES decryption instruction is to cause the execution unit to receive data from the 128-bit source and destination register and the 128-bit source register that is to be used by the first AES decryption instruction, perform operations for an AES single decryption round including an inverse byte substitution, an inverse shift rows, and an exclusive OR, but omitting an inverse mix columns, and store a first result in the 128-bit source and destination register; and the second AES decryption instruction is to cause the execution unit to receive data from the 128-bit source register that is to be used by the second AES decryption instruction, perform operations including an inverse mix columns, and store a second result in the 128-bit destination register that is to be used by the second AES decryption instruction.