1. A microprocessor having an architecture register that is modifiable by an instruction, the microprocessor comprising: an execution core, for receiving the instruction and for modifying the architecture register upon execution of the instruction, wherein the instruction comprises: a first operand that is an immediate value to specify a particular bit field within the architecture register to be modified upon execution of the instruction; a second operand to identify the architecture register to be modified; and a third operand to specify whether the particular bit field is to be set or cleared; and whereby the architecture register is modified atomically when the instruction executes.