1. An apparatus for executing an MMX PSADBW instruction, comprising: subtractors, for generating packed differences of packed operands of the instruction and for generating carry bits associated with each of the packed differences; inverters, coupled to said subtraction logic, for generating an inverse of each of said packed differences; multiplexers, coupled to said inverters and said subtraction logic, each for selecting as an output said packed difference if said associated carry bit indicates the packed difference is positive, and for selecting as said output said inverse if said associated carry bit indicates the packed difference is negative; and adders, coupled to said multiplexers, for adding said carry bits and said outputs of said multiplexers to generate a result of the instruction.