1. A computer-implemented method for formal verification of an integrated circuit comprising: receiving, via a computing device, an electronic design associated with the integrated circuit; generating one or more faults in a cone of influence of an assertion; placing a constraint configured to model an original design for the one or more faults; initiating formal verification on the electronic design while ignoring all electronic design constraints; determining whether the assertion is passing, wherein the determining includes activating an original design for a subset of faults; if the assertion is passing, activating a single fault from the subset; determining if the assertion is passing; and if the assertion does pass, deleting the single fault from the subset.