1. An apparatus for increasing fault tolerance of an FPGA circuit, comprising: a computer configured for designing an FPGA circuit; and programming executable on said computer for: describing a logic circuit for implementation on the FPGA circuit and routing of circuits through a synthesis process which arrives at a physical design; performing a circuit analysis on said logic circuit; performing in-place iterations of reconfiguring, don't care X filling, and/or inversion of look-up table (LUT) bits toward increasing overall reliability of said logic circuit; and updating said FPGA circuit in response to said in-place iterations; wherein said in-place iterations are performed after placement and routing to preserve physical design while optimizing the logic circuit to mask faults originating upstream.