1. A circuit arrangement, comprising: a processing core including an issue unit and at least one execution unit, wherein the issue unit is configured to issue instructions from an instruction stream to the at least one execution unit for execution thereby; and a programmable microcode unit coupled to the issue unit and configured to issue an instruction sequence to the at least one execution unit in response to a microcode instruction in the instruction stream, wherein the programmable microcode unit is programmable in response to software executed by the processing core.