1. Device for data rate regulation of at least two digital video signal components, comprising a correlation reduction circuit which receives the digital signal components representing a certain number of points of an image divided into blocks, a scanning conversion circuit which converts two-dimensional succession of values of output coefficients F.sub.i (u,v) of the correlation reduction circuit into a one-dimensional succession, a normalization circuit, a circuit for quantification by conversion into an integral value, a circuit for encoding the quantified values, and a data rate regulation circuit which receives the encoded values in accordance with a variable data rate and sends an average norm value associated with the said data rate to the normalization circuit, and delivers values at a constant data rate to the output of the regulation device, characterized in that said normalization circuit comprises: (a) a circuit for computing a ratio rap(acti) between an activity of a first component and an activity of a second component, the activity being a quantity which, proceeding from the coefficients obtained in the one-dimensional succession for each component, reflects the greater or lesser significance of high spatial frequencies in the spectral content of each one of said image blocks, and this quantity being computed for each component by connection of the input of said circuit for computing rap(acti) to the output of the scanning conversion circuit; (b) a circuit for computing a ratio rap(norm) between a data rate regulation norm relating to the second component and that relating to the first component; (c) a circuit for computing specific norms relating, respectively, to the first component and to the second component, receiving said value of rap(norm) and a global norm value delivered by a circuit for computing a global norm; (d) a divider for dividing an output of the scanning conversion circuit by an output of said global norm computing circuit; (e) a counter for counting a number of binary elements present in the data rate regulation circuit for the current block in the course of processing; (f) an auxiliary memory for temporary storage of said number of binary elements; (g) a subtractor for determining, by its sign, a difference of the number of binary elements between the input and the output of said auxiliary memory; (h) the global norm computing circuit, receiving an output of said subtractor and an output of the couner and delivering a global norm value intended for one of the inputs of the circuit for computing said specific norms.