1. A computer-implemented method of scheduling processing in a hardware threaded circuit, comprising: in a processor, receiving inputs corresponding to unthreaded processing of an application; receiving and storing in a memory information including processing element resources, a number of processing elements, and a window size corresponding to a number of downstream processing states to be examined; generating a hardware threaded schedule for processing the application with at least first and second one of the processing elements being interconnected to enable dynamic resource sharing; synthesizing the hardware threaded schedule to an Application Specific Circuit (ASC); and synthesizing the hardware schedule to maximize throughput, wherein the first and second processing elements each include a first type of resource and a second type of resource and a multiplexer such that the interconnection includes at least one input signal being provided to the first type of resource in the first and second processing elements.