1. A method of controlling a memory element, comprising: generating, at a host, a first instruction for a managed portion of a memory element; associating the first instruction with a logical address of the memory element; transmitting the first instruction to the managed portion of the memory element through a communication bus using a bus protocol; generating, at the host, a second instruction for an unmanaged portion of the memory element; associating the second instruction with a physical address of the memory element; and transmitting the second instruction to the unmanaged portion of the memory element through the communication bus using the bus protocol.