1. A method of fabricating a reconfigurable processor for running moderately complex programming applications comprising: (a) providing source code for a programming application, (b) entering the source code in a control flow graph generating compiler to produce a control data flow graph of data flow control flow and branch points, (c) extracting from the control flow graph basic blocks of code lying between branch points, (d) from the code lying between the branch points generating intermediate data flow graphs, (e) identifying clusters shared among dfgs at the highest level of granularity, (f) from the identified clusters determine the largest common subgraph shared among the dfgs, (g) scheduling the largest common subgraph for fast accomplishment of operations in the lcsg, (h) applying the scheduled lcsg to the intermediate flow graphs replacing the unscheduled lcsg therein, (i) scheduling the intermediate flow graphs containing the lcsg's for fast accomplishment of operations in the intermediate flow graphs to derive data patches having operations and timings of each intermediate flow graph, (j) combining the data patches to include operations and timing of the lcsg with operations and timings of each intermediate subgraph that are outside the lcsg, (k) from the combined data patches scheduling for process time reduction multiple uses of the lcsg operations and timings necessary to accomplish operations and timings of all intermediate subgraph employing the lcsg, and (l) implementing in hardware having mixed granularities the operations and timing of the lcsg including: (i) partitioning, (ii) placing, and (iii) interconnection routing.