1. A memory system having three mutually intersecting directions defined as a first direction, a second direction, and a third direction, comprising; a semiconductor substrate having a principal plane extending in the first direction and the second direction; and a cell array including plural first lines extending in the third direction, plural second lines extending in the first direction, plural third lines extending in the second direction and provided between said semiconductor substrate and a formation region of said plural first lines, and plural cells formed at intersections of said plural first lines and said plural second lines and having three or more settable physical quantity levels, wherein said cell array includes plural transistor layers stacked in the third direction and provided between said plural first lines and said plural third lines, said plural transistor layers include plural transistors operative to electrically connect said plural first lines selectively to one of said plural third lines, said plural transistors each include a conduction channel composed of polysilicon or an oxide semiconductor and have a gate length extending in the third direction, said cell array includes a logic circuit containing plural transistors and operative to connect between said first lines and said third lines, and said plural transistors contained in said logic circuit are formed dispersedly in a first and a second transistor layer adjacent in the third direction of the plural transistor layers.