1. A system to handle exceptions comprising: a plurality of processors; a plurality of dissimilar operating systems, wherein each of the plurality of processors executes one of the plurality of dissimilar operating systems; a memory, wherein the memory is to store a common exception handling vector address space and a plurality of separate interrupt handlers for each of the plurality of dissimilar operating systems; and a memory controller coupled to the memory and the plurality of processors, wherein upon receiving an exception by one of the plurality of processors, the one of the plurality of processors determines a type of the exception, executes instructions within the common exception handling vector address space, determines an identification of the one of the plurality of processors based on a value stored in an internal register of the one of the plurality of processors, and selects one of a plurality of separate interrupt handlers for the operating system of the identified processor.