1. A non-volatile memory cell, comprising: a) first and second semiconductor islands at a same horizontal level on a substrate and spaced a predetermined distance apart, the first semiconductor island comprising a control gate of said non-volatile memory cell and the second semiconductor island comprising source and drain terminals of said non-volatile memory cell; b) a gate dielectric layer on at least part of said first semiconductor island; c) a tunneling dielectric layer on at least part of said second semiconductor island; d) a floating gate on at least part of said gate dielectric layer and said tunneling dielectric layer; and e) a metal layer in electrical contact with said control gate and said source and drain terminals.