1. A data processor for executing, instructions realized by wired logic, in a pipeline system, comprising: a program counter for indicating an address of an instruction to be read; m(m&equals;2, 3,... ) instruction registers for storing a sequency of m instructions of which the first address is pointed by said program counter, at a time in one machine cycle; a register file formed of a plurality of registers in which data are stored; and m arithmetic operation units which read corresponding data from said register file and make arithmetic operations thereof in parallel in accordance of instructions read from said instruction registers; whereby the contents of said program counter is increased by m at a time, sequential m instructions are read from the addresses pointed by said program counter and written in said instruction registers, and said m instructions are processed in parallel by said m arithmetic operation units.