1. A data processing apparatus, comprising: a plurality of processing units operable to perform data processing operations requiring access to data in shared memory; each processing unit having a cache associated therewith operable to store a subset of said data for access by that processing unit; cache coherency logic employing a cache coherency protocol to ensure data accessed by each processing unit is up-to-date; each processing unit being operable to issue a write access request when outputting a data value for storing in said shared memory, when the write access request is of a type requiring both the associated cache and the shared memory to be updated, a coherency operation being initiated within the cache coherency logic; the cache coherency logic being operable to perform the coherency operation in respect of the caches associated with the plurality of processing units, including the cache associated with the processing unit issuing the write access request, in order to ensure that the data in those caches is kept coherent; and the cache coherency logic further being operable to issue an update request to said shared memory in respect of the data value the subject of the write access request.