1. A floating point unit capable of issuing multiple instructions in a single clock cycle comprising: a plurality of physical registers configured to be accessed as a stack, wherein the contents of said plurality of physical registers define the current state of said floating point unit; a plurality of parallel instruction decoders, wherein each instruction decoder is configured to decode one instruction during a first clock cycle; and a plurality of top of stack calculation units, wherein said plurality of top of stack calculation units are connected in a series, wherein each of said plurality of top of stack calculation units is coupled to receive a particular decoded instruction from one of said plurality of parallel instruction decoders, wherein each of said top of stack calculation units is configured to calculate a new top of stack pointer by adjusting a starting pointer as directed by a particular one of said decoded instructions, wherein each top of stack calculation unit is also configured to provide said starting pointer to the next top of stack calculation unit in said series.