1. A method of designing an integrated circuit, comprising: providing a physical layout group, comprising: a first layout corresponding to a first die having a first function; and a second layout corresponding to an interposer configured for the first die connected thereon; partitioning the first physical layout group into a first physical layout partition according to the first function; performing a first automatic place-and-route (APR) process to obtain a first hierarchical layout according to the first physical layout partition; and performing a first verification on the first hierarchical layout.