1. A digital error detection and correction apparatus comprising: data source means for providing n-bit error correction-coded code words including data and redundant binary bits, n being an integer, each code word comprising a plurality of sub-words having b bits each, b being an integer, one or more bits of a code word being possibly provided by a faulty element in said data source; error correcting means responsive to n-bit code words from said data source means for correcting up to a predetermined number of errors within a code word, said error correcting means providing a corrected code word in the presence of a correctable number and distribution of errors and providing an uncorrectable error output signal in the presence of an uncorrectable number and distribution of errors; fault-identifying means for identifying at least one b-bit sub-word of each said code word from said data source means, which sub-word was provided by a faulty element in said data source means; sub-word generating means for generating up to 2.sup.b unique combinations of said b-bit sub-word; and control means responsive to said error correcting means output signal and to said fault-identifying means for substituting a sub-word generated by said sub-word generating means for at least one sub-word of said n-bit code word identified by said fault-identifying means to form a modified code word and for applying said modified code word to said error correcting means, said control means operating cyclically to substitute a different generated sub-word up to 2.sup.b times in response to the output signal of said error correcting means.