1. A graphics processing apparatus comprising: a memory having regions of memory, each region of memory associated with a control bit to mark the region of memory in a clear state or a data state; and a processor coupled to the memory and configured to implement: render logic to set a first control bit associated with a first region of memory, the first region of memory to receive a request to write a color value, the first control bit referencing a clear color value stored in a register for the clear state, and clear color detection logic to detect the color value from compressed pixel data for the write request to the first region of memory and cause the render logic to set the first control bit to indicate the clear state and write to the first region of memory with the clear color value stored in the register if the detected color value for the write request to the first region of memory matches the clear color value.