1. An integrated circuit device comprising: at least one field programmable gate array region and at least one mask programmable gate array region; an I/O system including I/O pads and associated driver circuits; a user-programmable interconnect architecture for selectively making connections between said at least one field programmable gate array region, said at least one mask-programmable gate array region and said I/O system; and at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region, wherein the at least one circuit interface region is user programmable.