1. In a reduced instruction set computer (RISC) processor having a multi-stage pipelined datapath, a unified integer and floating-point datapath comprising: a register file combining a plurality of general purpose registers and a plurality of floating-point registers; an integer/mantissa execution unit, coupled to said register file, said integer/mantissa execution unit comprising: an adder, a shifter, a Boolean logic functional unit, a normalization logic unit, and a multiplexing network selectively routing operands to said adder, shifter, Boolean logic functional unit and normalization logic unit, an exponent execution unit coupled to said register file; and a unified control unit incorporating a superset of integer and floating-point instructions, said unified control unit coupled to said integer/mantissa execution unit and said exponent execution unit for controlling the operation and flow of operands through said integer/mantissa and exponent execution units, wherein said multiplexing network in said integer/mantissa execution unit comprises: a plurality of shift multiplexers having inputs coupled to receive operands, and having control inputs coupled to said unified control unit; a booth multiplexer having inputs coupled to outputs of said shift multiplexers, and an output coupled to a first input of said adder; an add multiplexer having inputs coupled to outputs of said shift multiplexers, and an output coupled to second input of said adder; a first multiplexer having inputs coupled to an output of said shifter and an output of said Boolean logic functional unit, respectively, a control input coupled to said unified control unit, and an output; a result multiplexer having a first input coupled to an output of said adder, a second input coupled to an output of said first multiplexer, and a control input coupled to said unified control unit; and a sum register for temporarily storing an output of said result multiplexer, and for feeding back said output of said result multiplexer to said shift multiplexers.