1. A processor comprising: a decoder to decode an instruction that is to indicate a first operand and a second operand, each of the first and second operands to have a plurality of packed data elements that are to correspond in respective positions, in which a first subset of the packed data elements of the first operand which are adjacent to one another and a first subset of the packed data elements of the second operand which are adjacent to one another are each to correspond to a first lane, and in which a second subset of the packed data elements of the first operand which are adjacent to one another and a second subset of the packed data elements of the second operand which are adjacent to one another are each to correspond to a second lane; an execution unit coupled with the decoder, the execution unit to store a result in response to the instruction being decoded by the decoder, in which the result that is to be stored is to include: (1) in a portion of the result that is to correspond to the first lane, only all adjacent highest order data elements from the first subset of the first operand interleaved with all corresponding adjacent highest order data elements from the first subset of the second operand; and (2) in a portion of the result that is to correspond to the second lane, only all adjacent lowest order data elements from the second subset of the first operand interleaved with all corresponding adjacent lowest order data elements from the second subset of the second operand.