1. A programmable memory test interface for testing a memory device, comprising: a plurality of programmable input pins and output pins; logic component means for interfacing the plurality of programmable input pins and output pins to the memory device, the logic component means is capable of being configured in accordance with one or more memory testing methodologies, and the configuring is accomplished by interconnecting selected ones of the plurality of programmable input pins and output pins; and a plurality of memory interfacing pins that connect the logic component means to the memory device.