1. A multi-bit non-volatile random access memory device, comprising: a first node; a first multi-bit storage circuit that includes a first transistor and a first programmable resistive device, a first terminal of the first transistor coupled to a second node, a control terminal of the first transistor coupled to a first write line, and a second terminal of the first transistor coupled to a third node, the first programmable resistive device coupled between the third node and a first bit line; a second multi-bit storage circuit that includes a second transistor and a second programmable resistive device, a first terminal of the second transistor coupled to the second node, a control terminal of the second transistor coupled to a second write line, and a second terminal of the second transistor coupled to a fourth node, the second programmable resistive device coupled between the fourth node and the first bit line; a reference circuit that includes a third transistor, a first terminal of the third transistor coupled to a second bit line and a second terminal of the third transistor coupled to the first node, and a control terminal of the third transistor coupled to a common write line; and a write enable circuit that includes a fourth transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a write enable line, wherein the write enable circuit is configured to activate in response to a write enable signal on the write enable line such that current flows either from the first bit line to the second bit line, or from the second bit line to the first bit line, to store a logic high state or a logic low state in one or more of the first multi-bit storage circuit or the second multi-bit storage circuit.