1. A trace and debug system for a processor, the processor having a processor core, a cache, a bus interface unit (BIU) and a timer, the processor core having a normal mode, a debug mode and a program counter (PC) to record a subsequent instruction address, the cache being coupled to the processor core through an address bus and a data bus, the BIU being coupled with the cache and a main memory, the timer being connected to the processor core to offer a timer function to an operating system for performing a context switch, the system comprising: a trace monitor, which is connected to the program counter (PC) in order to monitor address data of the program counter; a hardware break device, which is connected to the address bus and the data bus in order to produce a hardware break event in accordance with a predetermined hardware break point for halting the processor core; a debug controller, which is connected to the trace monitor in order to control an operation of the trace monitor; and a debug communication link, which is comprised of an interface and a memory controller and coupled between the hardware break device and a host in order to send the value of the PC and the state of the processor core to the host for forming a trace and debug message with respect to the processor core; wherein the trace monitor determines whether the processor core executes a non-successive instruction in accordance with the address data of the program counter; if the processor core executes the non-successive instruction, the trace monitor generates a trace break event in order to set the processor core from the normal mode to the debug mode and then the hardware break device fetches a value of the program counter (PC) and a state of the processor core; and wherein the interface is connected to the host in order to send and receive data, and the memory controller is connected to the interface, the BIU, and the hardware break device in order to map internal registers of the hardware break device and the debug controller to a memory space of the host, such that the host is capable of conveniently configuring relative settings, and accessing data of the main memory or peripherals connected to the BIU through the memory controller and the BIU.