1. An accelerated processor structure on a programmable integrated circuit device, the accelerated processor structure comprising: a processor; a plurality of configurable digital signal processors (DSPs), each configurable DSP comprising a circuit block, wherein the circuit block comprises a plurality of multipliers, wherein each configurable DSP is configured to use or bypass the plurality of multipliers by configuring at least one data connection between the plurality of multipliers; a first bus configured to transfer instructions from the processor to the configurable DSPs; a second bus configured to transfer processing data from the configurable DSPs to the processor; and data rotate circuitry coupled to the plurality of configurable DSPs and the second bus, wherein the data rotate circuitry is configured to align memory addresses of the processing data for the processing data to be accessed in aligned chunks.