1. A logic device comprising: field programmable apparatus having a plurality of inputs, a plurality of intermediate conductors, a plurality of outputs, means for coupling a field programmable subset of the inputs to a field programmable subset of the intermediate conductors and means for generating signals on the outputs at least partly in response to signals on the intermediate conductors; a first register and a second register, said first register and said second register having first input means and second input means, respectively, coupled to outputs of said field programmable apparatus, said first register and said second register further having first output means and second output means, respectively; and register selection means for selectively coupling one of said first output means and said second output means to a shared port.