1. A hardware-software counter comprising a hardware counter for counting lower significant bits, a carry-borrow circuit responsive to a higher order bit position of said counter and including cancel means responsive to successively received carry and borrow signals to cancel a respectively represented carry and borrow, memory means in the carry-borrow circuit separately memorizing a received carry or borrow, means responsive to said memory means to deactivate said cancel means, and a microprocessor including an adder for counting higher significant bits and means in said microprocessor for sensing said memory means in said carry-borrow circuit for determining whether a "1" is to be added to said higher significant bits.