1. A method for synthesis of an adaptable logic function consisting of a first class logic sub-function with a first worst case timing path length meeting a first maximum clock frequency and a second class logic sub-function with a second worst case timing path length meeting a second maximum clock frequency where the first worst case timing path length is less than the second worst case timing path length, the method comprising: creating a non-inverting hardware description language (HDL) module (Module 1 ) with a small propagation delay parameter and its associated model for the first class logic sub-function; creating a non-inverting HDL module (Module 2 ) with a small propagation delay parameter and its associated model for the second class logic sub-function; replacing the small propagation delay parameter of Module 1 with a propagation delay equal to the difference between the first worst case timing path length of the first class logic sub-function and the second worst case timing path length of the second class logic sub-function and accounting for the small propagation delay parameter of Module 2 ; instantiating Module 1 in the first class logic sub-function execution path; instantiating Module 2 in the second class logic sub-function execution path; and synthesizing the adaptable logic function for a plurality of timing paths with the period of the clock set to the second worst case timing path length of the second class logic sub-function and accounting for the small propagation delay parameter of Module 2 .