1. An apparatus comprising: a multi-threading processor including: an instruction fetch unit to receive a first thread and a second thread fetched from memory; an execution unit to execute said first thread and said second thread; a multi-thread scheduler coupled to said execution unit, wherein said multi-thread scheduler is to determine the width of said execution unit; and an instruction decode unit coupled between the instruction fetch unit and the multi-thread scheduler, wherein said decode unit is to decode said first thread and said second thread; wherein the width of the first thread and the second thread are examined during each cycle and then the combined width of the first and second thread is compared to the width of the execution unit; wherein said execution unit is to execute said first thread and said second thread in parallel if said execution unit is wide enough and to execute said first thread and said second thread in series if said execution unit is not wide enough.