1. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to map to at least a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising: receiving a first write data stream, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units; selecting a first physical programming unit from the plurality of physical programming units; determining whether the first write data stream associates with a pattern; if the first write data stream does not associate with the pattern, setting identification information corresponding to the first logical access address as a default value, programming the first write data stream into the first logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and storing the identification information corresponding to the first logical access address in a predetermined area; if the first write data stream associates with the pattern, setting the identification information corresponding to the first logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit; and mapping the first logical programming unit to the first physical programming unit, wherein a step of storing the identification information corresponding to the first logical access address to the predetermined area comprises: programming the identification information corresponding to the first logical access address into the redundancy bit area of the first physical access address.