1. A method of predicting a logic soft error rate for a circuit of a given technology using a processor that executes an estimating function to perform the method comprising: determining, by the processor, a charge stored on at least one logic node in the circuit; estimating a logic soft error rate for at least one logic node in the circuit using the processor operatively coupled to a database of logic soft error rate data points, wherein the data points in the database give a soft error rate as a function, at least in part, of a technology of the circuit, a type of product, and a charge of the logic node; and calculating, using the processor, the logic soft error rate of the circuit, wherein the logic soft error rate of the circuit is a function of the logic soft error rate of each logic node.