1. A data processor with an address translation buffer comprising: an execution unit generating an address; an address translation buffer coupled to the execution unit, the address translation buffer comprising a plurality of entries, each one of the plurality of entries comprising: a set of N translation mapping fields, where N is an integer, a differing one of the set of N translation mapping fields storing a differing one of a set of N translation mappings and a corresponding one of a set of N tags, the set of N translation mapping fields indexed by a first subset of the address, the set of N translation mapping fields operable to output a selected one of the set of N translation mapping fields if a second subset of the address is logically equivalent to the corresponding one of the set of N tags; a replacement pointer field storing a pointer, the pointer indicating one of the set of N translation mapping fields to receive a new translation mapping; and a replacement pointer control unit coupled to the address translation buffer, the replacement pointer control unit operable to overwrite a first value to the replacement pointer field responsive to a first state of a user-accessible control register during normal replacement operation of the address translation buffer, the replacement pointer field operable to overwrite a second value to the replacement pointer field responsive to a second state of the user-accessible control register.