1. A non-volatile memory device, comprising: an array of memory cells arranged by rows of word lines and columns of bit lines, wherein at least a portion of control gates of the memory cells are coupled to a same word line (WL), and wherein one or more sources and one or more drains of at least some of the memory cells are coupled to a same bit line (BL); a controller operatively coupled to the array of memory cells, wherein the controller is configured to: cause a signal level to ramp between a first value and a second value over clock cycles, wherein the signal level is applied to the memory cells in a selected WL; receive, at a same clock cycle, data for a plurality of individual memory cells in the selected WL, wherein the received data is associated with current values for the plurality of individual memory cells; and determine digital values for the plurality of individual memory cells based, at least in part, on the received data over the clock cycles, wherein to determine the digital values, the controller is configured to compare memory cell timing data to reference cell data; a sense circuit operatively coupled to the array of memory cells and to the controller; and a shift register operatively coupled to an output terminal of the sense circuit, wherein the shift register is configured to output the data to the controller, wherein the controller is configured to decode the received data by use of one or more of hard decoding or soft decoding, wherein thresholds are defined between digital states of the memory cells, and wherein the controller is further configured to adjust the thresholds according to a data retention model of the memory cells and according to a cell to cell interference model of the memory cells.