1. A computer processor for processing multiple threads of execution in parallel, the processor having a dedicated portion in which units of the processor are assigned to a single thread of execution, and having a shared portion in which units of the processor are shared among a plurality of threads of execution, the processor comprising: a shared memory; the dedicated portion of the processor having units dedicated to a thread of execution on a thread-by-thread basis, the dedicated portion of the processor including: a first access unit dedicated to process a first thread of execution, the first access unit including (i) a first access instruction fetch queue unit for fetching instructions from the shared memory, and (ii) a first access functional unit operable (a) to compute program control flow by performing arithmetic and branch instructions, and (b) to access memory by performing load and store instructions; and a second access unit, operating simultaneously with the first access unit, the second access unit dedicated to process a second thread of execution, the second access unit including (i) a second access instruction fetch queue unit for fetching instructions from the shared memory, and (ii) second access functional unit operable (a) to compute program control flow by performing arithmetic and branch instructions, and (b) to access memory by performing load and store instructions; a first execution queue unit coupled to the shared memory and storing instructions and data for the first thread of execution; a second execution queue unit coupled to the shared memory and storing instructions and data for the second thread of execution; the shared portion of the processor having units shared by at least two of the multiple threads of execution, the shared portion of the processor including: a plurality of execution functional units collectively operable to perform instructions not performed by the access units; and an arbitration unit coupled to the plurality of execution functional units and to the first execution queue unit and the second execution queue unit, the arbitration unit operable on an instruction-by-instruction basis to assign instructions from the first thread of execution and the second thread of execution among the plurality of execution functional units based upon the type of instruction being executed, wherein an execution functional unit may perform instructions from either the first thread of execution or the second thread of execution based upon the operation of the arbitration unit.