1. An apparatus comprising: a first processing element including a destination address storage element to hold a destination address, wherein at least a portion of an architectural state associated with the first processing element is to be written to the destination address in response to a save architectural state event; a second processing element including a restore storage element to hold the destination address as a restore address, wherein the at least the portion of the architectural state associated with the first processing element is to be restored to the second processing element from the restore address after the at least the portion of the architectural state associated with the first processor is written to the destination address in response to the save architectural state event.