1. A method for performing a butterfly operation for implementing a decoder in a processor having a memory and arithmetic logic unit (ALU) associated therewith, comprising: disposing old path metrics in said memory; disposing a set of gamma metrics in a local storage device associated with said ALU; providing at least one butterfly update instruction within the instruction set of said processor, providing said old path metrics as inputs to said ALU; providing said set of gamma metrics as inputs to said ALU; and providing at least one addressing mode for said memory, the execution of the at least one addressing mode causing a set of new path metrics to be reordered and written back to memory subsequent to execution of said at least one butterfly update instruction.