1. A logic circuit for delaying a signal input thereto by a number of clock cycles X, the logic circuit comprising: a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.