1. An information processing apparatus connected to an emulator to arrange a logic circuit of a verification target, comprising: a compile unit configured to create a logic circuit of a first data transfer unit arranged in a computer to transfer input data from the computer to the emulator, from the first data transfer unit based on a description of a verification program concerning input data; and a generation unit configured to generate a second data transfer unit that receives the data from the first data transfer unit and transfers the received data to the verification target based on the description of the verification program concerning the input data.