1. A processor having non-hierarchical security enhancements for context states, said processor comprising: at least one register; and a context control unit using context identifier tags associated with corresponding contexts to control access by said contexts to said at least one register, said context control unit receiving, from a first context, an access request for a specific register and further performing the following: determining whether said specific register is tagged with a first context identifier tag associated with said first context; and when said specific register is tagged with said first context identifier tag, providing said first context with read and write access to said specific register.