1. A processor comprising: a base register including a base field to indicate a starting address of a first memory region corresponding only to a first software program to access information from a first address; a limit register including a limit field to indicate the ending address of the first memory region; a translation register including a translation field to indicate a redirected address to where the first software program is to access the information, the redirected address being different than the first address; and a v bit storage area to store a v bit to indicate whether the base register is enabled.