1. A single instruction multiple data (SIMD) architecture including multiple interconnected processing elements, each of said processing elements comprising: memory means for storing data; function means for performing computational and/or Input/Output (I/O) operations; multi-operation instruction register means for storing an instruction for normally causing said function means to simultaneously perform multiple operations; mask register means for storing a plurality of mask bits, said mask register means including a mask context bit register holding a mask context bit, said mask context bit being logically combined with at least one of the plurality of mask bits for masking one of the operations; means for setting a condition mask bit, said condition mask bit being one of the plurality of mask bits, wherein the condition mask bit selectively prevents certain operations from being performed; and stack means for storing the contents of the mask register means during a subroutine call so as to save a context of the processing element during the subroutine call, wherein a state of the mask context bit prior to the subroutine call is stored in the stack means, and wherein a state of the condition mask bit is stored in the mask context bit register during the subroutine call, said stack means stacking multiple contents of the mask register means in sequence for multiple nested subroutine calls.