1. A data memory unit, comprising: a substrate including a source region and a drain region; a first insulating layer over the substrate; a second insulating layer over the substrate and between the source region and drain region; a solid electrolyte layer between the first insulating layer and second insulating layer, the solid electrolyte layer has a capacitance that is controllable between at least two states; an anode electrically coupled to a first side of the solid electrolyte layer, the anode electrically coupled to a voltage source; and a cathode electrically coupled to a second side of the solid electrolyte layer, the cathode electrically coupled to the voltage source and the second side opposing the first side.