1. A vector processor, comprising: (a) a memory for holding data; (b) at least one vector register including means for holding a set of vector elements and means for reading out said vector elements sequentially in groups in response to a store compression instruction, wherein each group comprises m (m&gt;1) vector elements which are read out in parallel; (c) at least one vector mask register including means for holding a set of mask bits each corresponding to one vector element of the set of vector elements, each mask bit comprising a valid mask bit or an invalid mask bit, and means for reading out the set of mask bits sequentially in groups in response to said store compression instruction, wherein each group comprises m mask bits corresponding to a respective group of m vector elements, wherein a respective group of m mask bits are read out in parallel and in synchronism with read out of a corresponding group of vector elements; (d) store means connected to said memory, said vector register and said vector mask register and responsive to said store compression instruction for selectively writing vector elements, within a set of vector elements currently read out of said vector register and corresponding to valid mask bits within the corresponding set of mask bits, into regularly spaced storage locations of said memory; (d1) wherein said store means comprises first to m-th parallelly operable access means, wherein an i-th (1.ltoreq.i.ltoreq.m) access means includes means for writing into said memory an i-th vector element of a respective group of vector elements currently read out from said vector register, in response to an i-th mask bit of a group of corresponding mask bits currently read out from the mask register when said i-th mask bit is a valid mask bit; (d2) wherein said first access means includes means for generating an address of a storage location of said memory into which a first vector element of the read out group of vector elements is to be written when a first mask bit of the read out mask bits is a valid mask bit included in all groups of m mask bits read out before the currently read out group of m mask bits; (d3) wherein each j-th (2.ltoreq.j.ltoreq.m) access means includes means for generating an address of a storage location of said memory into which a j-th vector element of the currently read out group of vector elements is to be written when a j-th mask bit of the currently read out group of m mask bits is a valid mask bit, depending upon said total number of valid mask bits in all previously read out groups of mask bits and upon a total number of valid or invalid mask bits included in the first to (j-1)th mask bits included in the currently read out m mask bits.