1. An apparatus, comprising: an array of memory cells; and sensing circuitry coupled to the array, and comprising: a plurality of sense amplifiers coupled to respective pairs of complementary sense lines; a plurality of compute components coupled to the sense amplifiers via respective pairs of pass gates coupled to the respective pairs of complementary sense lines; and logical operation selection logic configured to control the respective pairs of pass gates based on: a selected logical operation; and respective data values stored in at least one of: the compute components; and the sense amplifiers; and wherein the plurality of compute components comprise respective stages of a shift register into which data values on the respective pairs of complementary sense lines are loaded by enabling the respective pairs of pass gates.