1. A system for providing a floating point product, comprising: an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively; wherein the analyzer circuit comprises: a first group of comparators that generate asserted signals responsive to bits in an exponent field of the first and second floating point operands; a second group of comparators that generate asserted signals responsive to bits of a first portion of a fraction field of the first and second floating point operands; and a third group of comparators that generate asserted signals responsive to bits of a second portion of the fraction field of the first and second floating point operands; and a results circuit coupled to the analyzer circuit and configured to assert a resulting floating point operand containing the product of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand, wherein each of the first floating point operand, second floating point operand and resulting floating point operand comprises a sign bit, an exponent field and a fraction field, and wherein at least one of the five lowest order bits of the fraction field of one of the first floating point operand, second floating point operand and resulting floating point operand comprises at least one status flag.