1. A computer-implemented method for multi-patterning technology violation detection and visualization within an integrated circuit design layout, the computer-implemented method comprising: mapping a plurality of violations of a design rule in the integrated circuit design layout into a plurality of edges in a graph; generating, at one or more modules including a coloring module, a color graph corresponding to the graph at least by reducing a plurality of nodes in the graph into a plurality of colored nodes that reduces a graph size and by coloring the plurality of colored nodes in the color graph; detecting at least one multi-patterning violation from the color graph using at least a pattern recognition or detection technique without utilizing odd loop detection techniques, wherein the at least one multi-patterning violation is detected when neighboring nodes of the plurality of colored nodes have a same color; and visualizing the at least one multi-patterning violation on a layout canvas to enable selection of a corresponding fix to the at least one multi-patterning violation.