1. A method for operating a microprocessor to natively translate and execute instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA, the method comprising: extracting distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formatting them; extracting distinct x86 instruction bytes from a stream of instruction bytes received from an instruction cache and formatting them; using an ARM instruction length decoder to decode ARM instruction bytes and determine instruction lengths of ARM instructions; using an x86 instruction length decoder to decode x86 instruction bytes and determine instruction lengths of x86 instructions; determining start and end bytes of the x86 ISA and ARM ISA instructions; translating the x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture native to an execution pipeline of the microprocessor; and executing the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.