1. A processor comprising: at least one lower processing capability and lower power consumption physical compute element on a die, the at least one lower processing capability and lower power consumption physical compute element to be visible to first software that is to schedule workloads on the at least one lower processing capability and lower power consumption physical compute element and that is selected from an operating system, a virtual machine monitor, and a micro-kernel; at least one higher processing capability and higher power consumption physical compute element on the die, the at least one higher processing capability and higher power consumption physical compute element to be invisible to all software including the first software; migration performance benefit evaluation logic on the die and comprising at least one of a circuit and firmware to evaluate a performance benefit of a migration of a first workload from the at least one lower processing capability and lower power consumption physical compute element to the at least one higher processing capability and higher power consumption physical compute element based on receipt of a request for higher performance that is to be received from the first software, and to determine whether or not to allow the migration based on the evaluated performance benefit; available energy and thermal budget evaluation logic on the die and comprising at least one of a circuit and firmware to evaluate available energy and thermal budgets of the processor and to determine to allow the migration if the migration fits within the available energy and thermal budgets of the processor or not allow the migration if the migration does not fit within the available energy and thermal budgets of the processor, wherein the available energy and thermal budgets of the processor are shared by the at least one lower processing capability and lower power consumption physical compute element on the die and the at least one higher processing capability and higher power consumption physical compute element on the die; and workload migration logic on the die and comprising at least one of a circuit and firmware to perform the migration of the first workload when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.