1. A computer based test bench generator for verifying integrated circuits specified by models in a Hardware Description Language, comprising: a repository storing a general set of self-checking tests applicable to integrated circuits; means for entering behavior data of an integrated circuit model; means for entering configuration data of the integrated circuit model; means for automatically generating test benches in said Hardware Description Language, said means being configured to make a selection and setup of suitable tests from said repository according to the specified integrated circuit model, configuration and behavior data.