1. A rectangular digital processing array comprising: a plurality of processor cells each including a multi-bit memory having an input and an output, a first, input, single bit accumulator, a processing element having two inputs, one connected to receive the output of the multibit memory and the other connected to receive the output of the single bit accumulator; a second accumulator; first interconnections between the first accumulator of each cell and the first accumulators of two neighboring cells; second interconnections between the second accumulator of each cell and two neighboring cells which are different from the neighboring cells to which the first accumulator of each such cell is interconnected; and a controller connected to all of the cells in the array operative to control the transfer of data within each cell and through the interconnections between the cells.