1. An instruction transform apparatus for transforming an instruction to a new form, the instruction transform apparatus comprising: an instruction cache storing instructions from which a sequence of instructions are fetched to form a very long instruction word (VLIW); a first instruction register for receiving the fetched sequence of instructions, the fetched sequence beginning with a decode and load instruction followed by a second instruction, wherein the decode and load instruction causes the second instruction to be transformed into a partially decoded form, wherein the second instruction is comprised of a first bit field, a second bit field, and other instruction bits, wherein a bit field represents specified bits in a preselected bit field; a first decode unit connected to the first instruction register selectively determining to decode the first bit field of the second instruction to a first decoded full machine level format set of bits, selectively determining to decode the second bit field of the second instruction to a second decoded full machine level format set of bits, wherein the selectively determining to decode or to not decode is in response to a specification encoded in the second instruction and wherein a transformed partially decoded form of the second instruction is created to include the other instruction bits which are not decoded, the first decoded full machine level format set of bits, and the second decoded full machine level format set of bits; and a transform storage unit for storing the transformed partially decoded form of the second instruction in an instruction slot of the VLIW at an address generated in response to the decode and load instruction, wherein the bit width of the transformed partially decoded form of the second instruction depends upon the selectively determining to decode or to not decode.