1. A microprocessor, comprising: a plurality of processing cores, each processing core comprising a fetch unit, a decompression unit, and execution units; wherein each processing core comprises a core microcode memory configured to hold microcode instructions in the form of M-bit wide words of microcode instructions; and a secondary microcode memory, distinct from said core microcode memories, configured to provide N-bit wide words of microcode instructions, wherein M and N are integers greater than zero and N is different from M; wherein either the M-bit wide words or the N-bit wide words of microcode instructions, but not both, are compressed, and either the N-bit wide words or the M-bit wide words of microcode instructions, but not both, are uncompressed; wherein the decompression unit is configured to decompress the compressed microcode instructions after being fetched from one of the memories and before being executed.