1. A computer-implemented method for instruction execution, the method comprising: detecting, by an error detection unit included in a computer, an error in a first execution unit among a plurality of execution units of a processing circuit, wherein the first execution unit includes at least a first execution sub-unit and a second execution sub-unit, and the error detection unit installed remotely from the plurality of execution units; receiving instructions that are executable by at least one execution unit among the plurality of execution units; identifying at least one characteristic of the instructions, matching the at least one characteristic to an execution unit capable of executing a given instruction, and dispatching the given instruction to a corresponding execution unit based on an instruction dispatch rule that controls routing of the given instruction; in response to determining the corresponding execution unit is the first execution unit including the error, adjusting, by the computer, at least one of the instruction dispatch rules of an instruction issue unit based on detecting the error in the first execution unit to generate a replacement dispatch rule, the replacement dispatch rule re-routing the given instruction so as to restrict access to the first execution unit while leaving un-restricted access to the remaining execution units of the plurality of execution units; determining that the error is associated with the first execution sub-unit and the error is not associated with the second execution sub-unit; and adjusting the instruction dispatch rules of the instruction issue unit to prevent routing of instructions to the first execution sub-unit and to allow routing of instructions to the second execution sub-unit.