1. A two-dimensional information processing apparatus comprising: a plurality of unit cell circuits arranged in a tow-dimensional matrix and each including a detector for detecting information as predetermined part of two-dimensional information, a storage circuit for storing information detected by the detector, and a signal processing circuit for generating a pulse width modulation signal which has a pulse width corresponding to the information detected or stored; a plurality of address lines extending in a direction of columns of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the columns; a plurality of bus lines extending in a direction of rows of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the rows; means for selecting at least one of the address lines and supplying those unit cell circuits which are included in the selected address line, with a control signal for causing those unit cell circuits to generate pulse width modulation signals; and means for selecting at least one of the bus lines and reading, through the selected bus line, at least one of the pulse width modulation signals.