1. In a processor, an apparatus for issuing instructions, comprising: a classification logic adapted for prioritizing instructions in relation to one another and sorting said instructions in a number of priority categories; a plurality of instruction queues, wherein said plurality of said queues matches said number of said priority categories, and wherein each of said queues adapted to receive only one of said priority categories of said instructions from said classification logic, whereby said queues having same priority categories as said instructions; and an issue logic operably coupled to said plurality of instruction queues and selecting from which of said queues to dispatch said instructions for execution, wherein said issue logic has been designed to be cognizant of said priority categories of said queues.