1. A logic circuit having an output terminal and at least one input terminal, which comprises: a first electron transmission protein film made of a first electron transmission protein; a second electron transmission protein film made of a second electron transmission protein having a redox potential different from that of said first electron transmission protein and joined on top of said first electron transmission protein film; a third electron transmission protein film made of a third electron transmission protein having a redox potential different from that of said second electron transmission protein and joined on top of said second electron transmission protein film; a source electrode connected to said first electron transmission protein film; a gate electrode having an electrical influence on said second electron transmission protein film; a drain electrode connected to said third electron transmission protein film; said first, second, and third electron transmission films being coupled so as to form a driving transistor network in which a series connection of at least one circuit group consisting of at least one transistor with its drain and source connected in parallel to a pair of common drain and source terminals; said common drain terminal of the first circuit group in said series connection being connected to said output terminal; said common source terminal of the last circuit group in said series connection being connected to a second power supply having a potential lower than that of said first power supply; the gate of said transistor in said circuit group being connected to said input terminal; said load transistor and said driving transistor network being of the same type; and threshold voltages of said load and driving transistor network being substantially the same.