1. A computer system comprising: a central processor; a memory arrangement comprising: a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, a first charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of switching circuits each coupled to receive the first positive voltage provided by the first charge pump and for transferring that first positive voltage to selected subgroups of a plurality of subgroups of bitlines of the array, and logic circuitry coupled to the plurality of switching circuits for enabling the plurality of switching circuits in a selected order, such that a switching circuit of the plurality of switching circuits is enabled to couple the first positive voltage to a selected subgroup of the plurality of subgroups of bitlines until the floating gate field effect transistor devices coupled to the bitlines to be programmed are programmed; and a system bus for transferring data and addresses between the central processor and the memory arrangement.