1. A method, comprising: receiving a layout design for an integrated circuit (IC) device; performing a lithography pattern check (LPC) simulation on a first layer of the layout design, the LPC simulation including a topography-aware simulation model, the topography aware simulation model using data indicating topography variation of a second layer underlying the first layer to determine defocus values for areas of the layout design; and using the defocus values determined by the LPC simulation, identifying areas of the layout design that have defocus values that are outside a defined depth of focus tolerance range as potential hot spots of the layout design.