1. A computer implemented method for monitoring instruction execution in an instruction pipeline, the computer implemented method comprising: counting, by a performance monitor in a processor, a number of stall cycles for a group of instructions that are being executed by execution units in the processor, wherein the stall cycles are cycles of the processor during which the execution units are executing the group of instructions but none of the group of instructions completes execution; retrieving a deterministic latency pattern corresponding to the group of instructions; comparing the number of stall cycles to the deterministic execution latency pattern; and responsive to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed, identifying the instruction as a dependent instruction.