1. A processor comprising: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit associated with the second core, the prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, each prefetch request entry associated with at least one triggering event including an invalidate command, the prefetch circuit to detect the invalidate command for the first cache line, the invalidate command detected from the first core, and to issue a prefetch request associated with the invalidate request in the prefetch circuit to cause the first cache line to be prefetched from the first cache to the second cache.