1. An apparatus, comprising: an array of memory cells; and a controller configured to: apply a particular programming pulse of a programming operation for a plurality of memory cells of the array of memory cells to a respective control gate of each memory cell of the plurality of memory cells, wherein the plurality of memory cells comprises a first subset of memory cells having respective desired data states of a plurality of data states of the programming operation that are lower than a particular data state of the plurality of data states, and a second subset of memory cells having respective desired data states of the plurality of data states that are higher than or equal to the particular data state; while applying the particular programming pulse to the respective control gate of each memory cell of the plurality of memory cells, at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming; and after applying the particular programming pulse to the respective control gate of each memory cell of the plurality of memory cells, apply a subsequent programming pulse to the respective control gate of each memory cell of the plurality of memory cells while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state of the plurality of data states, and while not inhibiting any memory cell of the second subset of memory cells from programming; wherein the plurality of data states comprises more than two different data states.