1. An integrated circuit, comprising: a bit error test controller that provides a bit pattern; and a physical interface having a plurality of byte lanes, wherein said physical interface converts digital signals from the bit error test controller into waveforms for one or more memory devices, wherein at least a first byte lane is connected by a loopback path to a second byte lane and wherein said bit error test controller provides said bit pattern using a write operation that is then obtained using said loopback path to evaluate said physical interface based on said bit pattern.