1. A system, comprising: a data processor configured to check an arrival time of data training patterns corresponding to a data loading signal and address information for a read training, and advance or delay a phase of a system clock; and a semiconductor memory device configured to generate the data training patterns by distributing the data loading signal and the address information input through a plurality of address pads, and output the data training patterns through a plurality of data input/output pads, wherein the address information comprises: a data type address information for constructing the data training patterns; and a control signal type address information for selecting data input/output pads to output the data type address information.