1. A logic circuit comprising: a first vertical transport field effect transistor and a second vertical transport field effect transistor, each having source/drain regions on vertically opposing sides of a gate structure and a vertical fin extending vertically upwards with respect to a supporting substrate of a vertical inverter, from a bottom source/drain region to a top drain/source region; one or more gate structures; wherein components of the logic circuit are present in at least three different and distinct vertical levels, a Level FET comprising a horizontal plane passing through the fins of the first and second vertical transport field effect transistors, Circuit Level M 1 , and Circuit Level M 2 ; wherein Circuit Level M 1 comprises at least one horizontal plane through at least one conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit; and wherein Circuit Level M 2 comprises a horizontal plane through at least one conductive element that forms a conductive bridge from N output to P output of the field effect transistors.