1. A mixed-radix carry-lookahead adder, comprising the following: an initial carry-lookahead stage having one or more elements configured to receive a plurality of sets of input bits, to create initial propagate and generate output signals for each bit position in the sets of input bits, and to compute an XOR of the sets of input bits that is forwarded to a final carry-lookahead stage; a first intermediate carry-lookahead stage having one or more elements of a first radix, and that is configured to receive the initial propagate and generate output signals from the initial carry-lookahead stage, and to calculate first propagate and generate output signals based thereon; a second intermediate carry-lookahead stage having one or more elements of a second radix that is different than the first radix, and that is configured to receive the first propagate and generate output signals from the first intermediate carry-lookahead stage and calculate second propagate and generate output signals based thereon; a third intermediate carry-lookahead stage having one or more elements of the first radix and one or more elements of the second radix, and that is configured to receive the second propagate and generate output signals from the second intermediate carry-lookahead stage and calculate at least a third generate output signal based thereon, wherein the elements of the initial carry-lookahead stage, the elements of the first intermediate carry-lookahead stage, the elements of the second intermediate carry-lookahead stage, and the elements of the third intermediate carry-lookahead stage are arranged such that each of the propagate and generate output signals passes through no more than a single passive transmission line; and the final carry-lookahead stage comprising an XOR logic gate configured to receive a final generate output signal from an intermediate carry-lookahead stage, and to XOR the final generate output signal with the computed XOR signal forwarded from the initial carry-lookahead stage in order to produce a sum of the plurality of sets of input bits.