1. A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, parallel busses for interconnecting the arithmetic/logic unit and the registers, an instruction register, and control means having an input coupled to the instruction register, said control means generating control outputs coupled to the arithmetic/logic unit and the busses and registers for controlling operation thereof in response to instruction words temporarily stored in the instruction register, all within the integrated circuit, and wherein the control means includes a read-only-array having an address input and a command output and includes addressing means receiving said input coupled to said instruction register and having an output for applying a sequence of addresses to said address input to define an operation selected by an instruction word, said sequence including a first address derived from said instruction word in said instruction register, and said sequence including a second address subsequently derived from the same said instruction word still in said instruction register.