1. A phase locked loop (PLL) circuit comprising: a phase detector comparing an input signal to a feed back signal, the phase detector providing an error signal, a low pass filter defining a filter output, a voltage controlled oscillator accepting the output from the low pass filter and output the feedback signal, at least two charge pumps that each output a driving signal to the low pass filter, wherein the driving signal is responsive to the error signal, a lock detector that accepts the error output and in response outputs at least one lock signal, wherein the one lock signal represents an indication of a coarse lock, a reference generator that accepts the first lock signal and in response outputs one reference signal to one charge pump, wherein the reference signal controls the charge pump, and wherein when the at least two charge pumps provide a signal to the low pass filter the PLL loop bandwidth is higher than when one of the at least two charge pump is inactive.