1. In a system having a memory array that is arranged as an X-Y matrix of memory cells, and comprising: means providing coded address signals for selecting memory cells for evaluation of the logic state of the signals stored therein, an X decoder for decoding the coded address signals corresponding to the X coordinate of the selected memory cell and for applying an X coordinate signal to the memory array to enable evaluation of the memory cells located along the corresponding X coordinate, and a Y decoder for decoding the coded address signals corresponding to the Y coordinates of the selected memory cell and for enabling the read-out between the memory cells located along the corresponding Y coordinate and an output terminal of the Y decoder, to enable evaluation of the selected memory cell; an improved Y decoder comprising: a plurality of signal selectors, each of said selectors signal having a plurality of input lines with at least two of said input lines corresponding respectively to different ones of said Y coordinates, each of said signal selectors having an output terminal to which one of said input lines is connected in response to at least one of said decoder address signals, a plurality of gate-controlled switches, each of said switches having a gate electrode, a source electrode and a drain electrode, the source electrodes of said switches connected respectively to the output terminals of said signal selectors, the drain electrodes of said switches connected to each other and to said Y decoder output terminal; and at least one AND/OR circuit for generating a gate signal in response to a particular set of coded address signals and for applying said gate signal to a gate electrode of a gate controlled switch whereby said read-out path includes only one of said signal selectors and only one of said gate controlled switches.