1. An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor, where the instruction processing circuit comprises: a decoder circuit operable to receive at least one sequence of instructions and to decode the at least one sequence of instructions into a sequence of operations of a first type; a basic block builder circuit operable to receive a portion of the sequence of operations of the first type and to generate therefrom a sequence of operations of a second type; a multi-block builder circuit separate from the basic block builder circuit and operable to receive a portion of the sequence of operations of the second type and to generate therefrom a sequence of operations of a third type; a branch predictor circuit operable to generate a branch operation prediction from the sequence of operations of the first type, the sequence of operations of the second type, and the sequence of operations of the third type, wherein the branch predictor circuit comprises a first predictor circuit corresponding to branch operations of a first type and a second predictor circuit corresponding to branch operations of a second type; and a sequencer circuit operable to select a next sequence of operations from among the sequence of operations of the first type, the sequence of operations of the second type, the sequence of operations of the third type, and the branch operation prediction for providing to the execution circuit, wherein the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction of the branch operations of the first type concurrently with the second predictor circuit generating a prediction of the branch operations of the second type, wherein the sequencer circuit is operable, in a second environment, to cause the first predictor circuit to generate the prediction of the branch operations of the first type sequentially with the second predictor circuit generating the prediction of the branch operations of the second type.