1. An integrated circuit having a plurality of input pins receiving input signals and a plurality of output pins, comprising: first programmable array means, coupled to the plurality of input pins, for receiving a plurality of first input terms and generating a plurality of first output terms including a first AND-array receiving the first input terms and generating first product terms, and a first OR-array receiving the first product terms and generating first sum-of-product terms for supply as the first output terms; second programmable array means, coupled to the plurality of output pins and to the first programmable array means, for receiving the plurality of first output terms and generating a plurality of second output terms for supply to the plurality of output pins including a second AND-array receiving the first output terms and generating second product terms and a second OR-array receiving the second product terms and generating second sum-of-product terms for supply as the second output terms.