1. A low density parity check decoder comprising: a plurality of message processing blocks arranged in a logical array; a plurality of information bit processors, one for each column of said message processing blocks (“MPBs”) in said logical array; a plurality of lookup table memories, one for each column of said message processing blocks in said logical array; and a plurality of check message processors, one for each row of said message processing blocks in said logical array, wherein said decoder iteratively operates to decode a data signal, and wherein the array of message processing blocks provides distributed storage of parity check message memory and distributed computation of check-node and bit-node messages, so as to facilitate highly parallel access of message storage and message computation for high-throughput LDPC processing.