1. A method of processing instructions of multiple instruction streams in a processor core having a plurality of instruction execution slices, the method comprising: detecting an event corresponding to dispatch of a first instruction of a first one of the instruction streams that indicates that mapping between the instruction execution slices and corresponding ones of the instruction streams should be changed due to a change in resource availability or requirements for execution of a subsequent instruction of the first instruction stream; and responsive to detecting the event, dispatching at least a portion of the subsequent instruction to a selected one of the instruction execution slices that was assigned to a second one of the instruction streams during a previous execution cycle.