1. A method of generating a stream processor, the method comprising: generating a graph of nodes representing the stream processor to be implemented in hardware; identifying nodes within the graph that affect external flow control of the stream processor; retaining the identified nodes and removing or replacing all nodes that do not affect external flow control of the stream processor in a modified graph; simulating, by a processor, the modified graph or building a corresponding circuit of the retained nodes; traversing the graph in reverse order from outputs to inputs and, for each node, determining in sequence if it affects external flow control; and once the graph has been simulated or a corresponding circuit built of nodes that do affect external flow control, debugging any identified flow control bugs independent of the data flow through the stream processor.