1. Command queuing circuitry comprising: a primary queue for holding a first command, the first command being an erase block command specifying a first flash memory block to be erased; a secondary queue for holding a second command, received subsequent to the first command, the second command being either a second erase block command specifying a second flash memory block to be erased or a first program word command specifying a first flash memory word to be programmed; snooping circuitry for examining the second command, without servicing the second command, prior to completion of service of the first command: prioritization circuitry for determining the priority of the snooped second command, if the second command is the first program word command and the first flash memory word is not part of the first flash memory block, the second command having a higher priority than the first command; switching circuitry for suspending service of the first command and permitting service of the second command if the second command has a higher priority; and command absorption circuitry to incorporate service of the second command into service of the first command and then purge the second command from the secondary queue if the second command is the second erase flash block command.