1. A method comprising: forming, by a computing system, multiple circuit design entities, each including a different set of gates in a gate-level implementation of an electronic system; determining, by the computing system, a physical layout for the circuit design entities based, at least in part, on characteristics of the sets of gates in the circuit design entities; and generating, by the computing system, a physical design implementation for the electronic system based, at least in part, on the physical layout for the circuit design entities.