1. A method comprising: setting a bit line, coupled to a resistive element of a memory cell, to a first voltage level, wherein the resistive element is configured to have a first resistance in a first state of the memory cell and a second resistance in a second state of the memory cell; setting a source line to a second voltage level, wherein the source line is selectively coupled to the memory cell by an access transistor; asserting a word line signal to apply a first bias voltage across the resistive element, wherein the applied first bias voltage initiates a first write operation at the memory cell; and deasserting the word line signal after a variable time duration based on a detection, during said first write operation, of a current through the resistive element.