1. Apparatus for processing data comprising: A cache memory coupled to a main memory; a processing pipeline, coupled to said cache memory, configured to process a stream of program instructions and having a plurality of processing stages including a main query stage, responsive to a program instruction at said main query stage, configured to generate a main query request to said cache memory, said cache memory, responsive to said main query request, configured to generate a main query response signal indicative of whether or not said cache memory is ready to service an access request by said program instruction at said main query stage; a buffer configured to store said program instruction from said main query stage if said main query response signal indicates said cache memory is not ready to service said access request by said program instruction at said main query stage; a buffer query stage, separate from said main query stage and responsive to a program instruction stored within said buffer, configured to generate a buffer query request to said cache memory, said cache memory, responsive to said buffer query request, configured to generate a buffer query response signal indicative of whether or not said cache memory is ready to service an access request by said program instruction stored within said buffer; and a fetch stage, responsive to said main query response signal and said buffer query response signal, configured to access said cache memory to service one of said access request by said program instruction at said main query stage and said access request by said program instruction stored within said buffer, wherein a clock signal defines boundaries between processing cycles of said apparatus and a fetch, said main query request and said buffer query request take place in a same processing cycle.