1. A memory device, comprising: at least one main memory block comprising a plurality of erase blocks; a control circuit configured to control erasing of the main memory block, the control circuit being configured, in response to an erasing of a first erase block of the main block, to set a count associated with the first erase block to a particular value and change a count associated with another erase block of the main block; and refresh the other erase block in response to the count associated with the other erase block reaching a threshold, wherein the refresh of the other erase block comprises: moving user data contained in the other erase block to a new location, if the other erase block contains user data when the other erase block is refreshed; and refreshing system data contained in the other erase block in place.