1. A processor comprising: a plurality of registers; an instruction generation logic to generate at least one instruction to read information from at least one register of the plurality of registers in order to detect whether the at least one register of the plurality of registers contains erroneous information; and detection logic to detect at least one register of the plurality registers that is to store information that will not be accessed for longer than a threshold period based, at least in part, on at least a portion of a code being translated by a binary translator.