1. A semiconductor device comprising: a memory for storing a plurality of instructions therein; an instruction queue which temporarily stores instructions fetched from the memory; a central processing unit which executes instructions supplied from the instruction queue; an instruction cache which stores instructions which have been executed in the past by the central processing unit; and a control circuit which controls fetching of instructions, wherein: when the central processing unit executes a branch instruction, and an instruction of a branch destination is stored in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes: the instruction queue to fetch the instruction of the branch destination from the instruction cache; and the instruction queue not to fetch the instruction following the instruction of the branch destination.