1. A processor comprising: an instruction set that defines a plurality of instructions that are executable by the processor, the instruction set comprising: a regular store instruction that is used in first regions of computer programs where memory aliasing cannot occur; and a special store instruction that is used in second regions of the computer programs that are different than the first regions; hardware that detects memory aliasing and assures proper operation of code that includes the regular store instruction and the special store instruction even when memory aliasing occurs, wherein the hardware that detects memory aliasing tracks data destination addresses of store instructions using address tag fields, and sends address but not data of the special store instruction to at least one load/store queue.