1. A design structure embodied in a hardware-description language and stored on a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: a multi-threaded system, comprising: a multi-threaded processor that maps identifying fields of each of a plurality of source registers and a plurality of destination registers to different respective identifying fields of each of a plurality of threads of instruction; wherein a first of the source registers and a first of the destination registers are mapped to a first thread; wherein a second of the source registers and a second of the destination registers are mapped to a second thread; and wherein the first thread is different from the second thread, and each of the first and second source registers and the first and second destination registers are different from each other of the first and second source registers and the first and second destination registers; and wherein the processor executes an instruction of the first thread when the second thread is inactive by: providing access by the first thread to the mapping of the second thread to the second source register and the second destination register if the second thread is inactive; using the mapping of the second thread to the second source register and the second destination register to execute the instruction of the first thread by reading from the second source register and writing to the second destination register; using the mapping of the first thread to the first source register and the first destination register to execute the instruction of the first thread by reading from the first source register and writing to the first destination register; and mitigating any attempt by the second thread to read from the second source register or write to the second destination register still mapped to the second thread while the first thread is using said second source register to execute the instruction of the first thread.