1. An image processing circuit comprising: a plurality of line buffers, each line buffer storing pixel data of a plurality of pixels as line data, said plurality of pixels configuring a single image line of an image; a first image processing part performing a first image processing task on original image data provided from the exterior by using the line data stored in at least one of said plurality of line buffers, and providing processed image data; a second image processing part performing a second image processing task on the processed image data provided from said first image processing part by using the line data stored in at least one of said plurality of line buffers, and providing processed image data; a line buffer selector that selectively connects said first image processing part to a first subset of said plurality of line buffers and selectively connects said second image processing part to a second subset of said plurality of line buffers, said first subset of said plurality of line buffers not overlapping with said second subset of said plurality of line buffers; and an output path selector that selects one of an output path that skips the second image processing task and an output path that performs the second image processing task, wherein said output path selector selects said output path that skips the second image processing task when said line buffer selector connects said first image processing part to all of said plurality of line buffers provided in the image processing circuit, and said output path selector selects said output path that performs the second image processing task when said line buffer selector connects said second image processing part to a predetermined number of line buffers that are necessary for the second image processing tasks, wherein the first image processing part and the second image processing part are identical in structure.