1. A processor comprising: a memory management unit (MMU) comprising a queue configured to store pending hardware-generated page table entry (PTE) updates; and an interface unit coupled to the MMU and to an interface of the processor, wherein the interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory; and wherein the MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface.