1. In a programmable logic device, a structure comprising: a plurality of programmable logic blocks; a routing resource for interconnecting said programmable logic blocks, said routing resource receiving signals from a plurality of interconnection lines and routing said signals to said programmable logic blocks; a first pin configured to receive a first input signal; a second pin configured to receive a second input signal; and means, receiving said first and second input signals from said first and second pins, for multiplexing each of said first and second input signals to more than one of said interconnection lines.