1. In a programmed manipulator having a manipulating portion, a device for driving the manipulating portion in a plurality of different axes, a device for generating digital signals representing an actual position of the manipulating portion, a device for memorizing said digital signals thereby to produce digital instruction signals representing an objective position of the manipulating portion, a comparator comparing said instruction signals with said actual positional signals thereby to produce error signals, a device for controlling said driving device based on said error signals, said error signals are thereby reduced, and a device for controlling manually said driving device without depending on said error signals; the improvement comprising: a memory revising region setting means for shifting the content of one region to another region in said memory device, when a step is defined to be an information group corresponding to a unit of operation, or for exchanging the contents of two regions between each other, sets the numbers A and B for leading step and the last step within a first region and also the numbers C and D for the leading step and the last step within a second region of memory in said memorizing device; a plurality of up-down preset counters for storing signals indicative of said step numbers A and C delivered from said revising region setting means, and adding or subtracting "1" from the thus stored contents of the counters each time a pulse is received; a plurality of buffer registers for holding the signals indicative of said step numbers B and D also delivered from said revising region setting means; a first step number comparator which compares the output from one of said up-down preset counters with the output from one of said buffer register thereby to produce a difference signal and sends to the up-down preset counter an instruction for addition or subtraction depending on the sign of said difference signal; a second step number comparator which compares the output of the other said up-down present counters with the output of the other of said buffer registers to produce a difference signal, and sends to the other of said up-down present counters an instruction for addition or subtraction depending on the sign of said difference signal; a subtraction preset counter which stores the output of said first step number comparator, subtracts "1" from the thus stored content each time when a pulse is received, and when the content is found to be a predetermined state, produces an output indicative of said state; a plurality of address calculating means for calculating actual addresses in the memory based on the outputs of both of said up-down preset counters; a plurality of addition preset counters to store the address outputs from both of said address calculating means, respectively, and add "1" to the contents each time when a pulse is received therein until the additions are carried out in a number of times equal to the number of addresses included in said unit of operation constituting a step; first means for selecting either one of the outputs from said addition preset counters twice for each pulse received and sending the selected output to said memory; a plurality of buffer registers for holding respectively the contents of memorized addresses selected by said selecting means and sequentially delivered from said memory, and delivering the thus held contents into the memorizing addresses selected by said selecting means; second means for selecting either one of the outputs from said buffer registers once for each pulse added to said addition preset counters and sends the thus selected output to said memory; and timing pulse generating means for delivering a first train of pulses to said subtraction preset counter and said up-down preset counters until the same pulse train is stopped by the output signal from the subtraction preset counter, said timing pulse generating means delivering a number of second train of pulses equal to the number of addresses for the memory unit constituting said step each time when one of said first train of pulses is received to said addition preset counters, said timing pulse generating means further delivering for each of said second train of pulses a number of pulses required for making it possible to read out of said memory the contents in the addresses in said two regions in said memory, for the purpose of exchanging the contents between each other or of shifting one content to the address corresponding to the other content, and for making it possible to write the same into said memory.