1. A cache memory system comprising: a first cache memory and a second cache memory, said first and second cache memories comprising direct mapped cache memories, wherein said second cache memory has a memory capacity smaller than that of said first cache memory, each of said first and second cache memories including a data memory section for storing data, a tag memory section for storing an address tag for locating data stored in said data memory section, a comparator for comparing an output of said tag memory section with an address tag of a given address, and a hit generator for generating a hit signal when said comparator determines said output of said tag memory section coincides with said given address; and means for controlling said first cache memory and said second cache memory such that, in response to a reading access from an external device, said first cache memory is accessed first, and if the hit signal is not generated from said reading access of said first cache memory, said second cache memory is accessed, and if the hit signal is not generated from said reading access of said second cache memory, an external memory is accessed, wherein the smaller second cache memory and the larger first cache memory maintains or improves the hit/miss ratio of the overall cache memory system.