1. A programmable logic device comprising: programmable logic circuitry; scheduling circuitry that receives user-defined configuration data; and a plurality of resolution engines coupled to the scheduling circuitry, wherein the plurality of resolution engines receives the user-defined configuration data from the scheduling circuitry, generates hardware-defined configuration data based on the user-defined configuration data and a set of pre-determined constraints, and loads the hardware-defined configuration data and the user-defined configuration data onto the programmable logic circuitry to implement a logic design for the programmable logic device, wherein the plurality of resolution engines generate a configuration data bitstream that includes the user-defined configuration data and the hardware-defined configuration data, and wherein the plurality of resolution engines loads the configuration data bitstream onto the programmable logic circuitry.