1. A method for testing bit failures in memory array elements of an electronic circuit, said method comprising the steps of: using a computer, modifying a representation of said electronic circuit such that errors can be injected into said memory array elements via input signals of read, write, or both read and write logic of said memory array elements; building an emulator model from said modified representation; injecting errors into said memory array elements during an emulation of said emulator model; and wherein said representation of said electronic circuit is a hierarchical netlist and said modifying of said representation of said electronic circuit includes: identifying a desired array memory signal by type or attribute from said hierarchical netlist; identifying an assignment of said desired array memory signal to a data output signal in said hierarchical netlist; and inserting an equivalent of error injection behavioral between said data output signal and said memory signal.