1. An SR latch circuit having an enable input and an SR latch circuit output, the SR latch circuit comprising: a first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage configured to receive an enable input in advance of set an reset inputs becoming valid, the enable input causing the first input stage to become transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage; a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage configured to receive the enable input in advance of set and reset inputs becoming valid, the enable input causing the second input stage to become transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.