1. An apparatus comprising: N memory banks addressable by N intermediate signals, wherein N is at least two and each of said memory banks (i) receives a respective one of said intermediate signals and (ii) has a plurality of memory locations; an address switch configured to (i) generate said intermediate signals by routing N addresses signals in response to a control signal, each of said address signals conveying a respective one of a plurality of address values, each of said address values corresponding to a respective one of said memory locations and (ii) generate said control signal in response to all of said address signals; and a data switch configured to route N data signals between N data ports and said memory banks in response to said control signal.