1. A nonvolatile semiconductor memory comprising: plural nonvolatile memory cells arranged in matrix form; plural word lines connected to gates of said nonvolatile memory cells; plural bit lines connected to drains of said nonvolatile memory cells; plural source lines connected to sources of said nonvolatile memory cells; and a word decoder which activates a word line according to an address signal, and which, when different word lines are accessed sequentially, overlaps a part of activation periods of said word lines to perform access operations in parallel, wherein all combinations of bit lines and source lines that are connected to the drains and the sources of nonvolatile memory cells are different from each other.