1. An apparatus, comprising: a first fuse array; a second fuse array; circuitry configured to: read a first set bit values from the first fuse array; read a set of redundancy bit values from the first fuse array; check the first set of bit values for errors dependent upon the set of redundancy bit values; and read at least one bit value from the second fuse array in response to a determination that at least one error is present in the first set of bit values.