1. A method to detect deadlock in a hardware design using assertion-based verification, the method comprising: tracking the state of one or more control signals in the hardware design; generating one or more assertions for each of the one or more control signals to detect whether that control signal is in a deadlock state based on said tracking, wherein the one or more assertions for the one or more control signals are defined in an assertion language; determining whether the hardware design can enter a deadlock state by detecting, through formal verification or simulation based verification of the one or more assertions, whether any of the one or more control signals can enter a deadlock state; and in response to determining that the hardware design can enter a deadlock state, outputting a deadlock indication, wherein the hardware design is updated based on the outputted deadlock indication.