1. A device, comprising: a pattern-recognition processor, comprising: a plurality of logical groups, wherein each group comprises one or more feature cells, wherein the one or more feature cells of each group are coupled to first route lines by first connections; a plurality of logical rows, wherein each row comprises one or more of the plurality of groups wherein the one or more groups of each row are coupled to second route lines by second connections; and a plurality of logical blocks, wherein each block comprises one or more of the plurality of rows, wherein the one or more rows of each block are coupled to third route lines by third connections; wherein the plurality of blocks are coupled to fourth route lines by fourth connections.