1. An integrated circuit with a processor ( 603 ), a non-volatile memory ( 602 ) and an interface ( 605 ) connecting said processor ( 603 ) to said non-volatile memory ( 602 ), wherein said interface ( 605 ) contains a first cache memory ( 601. 1 ) and a second cache memory ( 601. 2 ), said first and/or said second cache memory ( 601. 1 , 601. 2 ) being equipped for storing data corresponding to determined addresses of the non-volatile memory ( 602 ), and said interface ( 605 ) providing said processor ( 603 ) selectively with data from said first cache memory ( 601. 1 ) or from said second cache memory ( 601. 2 ) and fetching data from said non-volatile memory ( 602 ) corresponding to a next determined address.