1. A processor, comprising: a mapping module that maps virtual processor identifiers and process context identifiers to global and local identifiers, respectively, so that the global and local identifiers uniquely identify entries in one or more data structures from which the virtual processor identifiers and process context identifiers can be retrieved; and a translation-lookaside buffer (TLB) having a plurality of address translations, wherein for each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the local identifiers to which the mapping module has mapped one of the process context identifiers.