1. A processor core comprising: a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core; an instruction address register for storing an instruction address corresponding to each of a plurality of aborted transactions from the plurality of transactions; a data address register for storing a data address corresponding to each of the plurality of aborted transactions, wherein the processor core is configured for: retrieving the instruction and data addresses corresponding to each of the plurality of aborted transactions from the instruction address register and the data address register, respectively; and generating profiling information of the plurality of aborted transactions based on the retrieved instruction and data addresses.