1. A data processing system, comprising: processor means for processing data, memory means for storing at least one sequence of instructions to be performed by said data processing means, microprogram means for providing sequences of micro-instructions to said processor means for performing said instructions, said instructions including at least one no-op instruction to be performed by at least one of said sequence of micro-instructions selected from an extended set of micro-instructions, and memory bus means connected from an output of said memory means and to an input of said micro-program means for conducting memory output signals representing said instructions to said microprogram means, said processor means including a quadriport register file having dual read ports and dual write ports, an arithmetic-logic unit for performing arithmetic and logical operations on input information supplied thereto and having a pair of inputs and output, a shifter unit for providing a shifted output therefrom to said register file and having an input and an output connected to an input of said register file, means for connecting said dual read ports of said register file to said inputs of said arithmetic-logic unit means for connecting at least one of said read ports of said register file to at least one of said write ports of said register file, memory address register means for providing addresses to said memory means, and means for connecting said output of said arithmetic-logic unit to an input of said memory address register means, to an input of said shifter unit, and to at least one of said write ports of said register file, and said microprogram means including micro-instruction control store means having first and second memory spaces for respectively storing and providing to said processor means a non-extended set of said micro-instructions and said extended set of micro-instructions, and instruction decoding means having an input connected from said memory bus means and an output connected to an addressing input of said micro-instruction control store means and responsive to said instructions for decoding said instructions and providing address signals to said micro-instruction control store means for selecting each of said micro-instructions, including means responsive to first certain portions of said instructions for selecting said at least one sequence of micro-instructions from said extended set of micro-instructions when a present instruction is a said at least one no-op instruction, each one of said first certain portions of said instructions containing information for identifying whether each one of said instruction is said a said at least one no-op instruction, whereby said micro-instruction control store means is responsive to said address signals provided by said instruction decoding means as a result of said decoding by said instruction decoding means of said first certain portions of said instructions to provide said at least one sequence of micro-instructions from said extended set of micro-instructions stored in said second memory space to said processor means when a said instruction present on said memory bus means is a said at least one no-op instruction.