1. A system comprising: means for providing an indication whether a first memory address to be written stores a target instruction for a first instruction set architecture which has been translated to at least one host instruction for a second instruction set architecture, the at least one host instruction stored at a second memory address, the means for providing comprising: a look-aside buffer including a plurality of storage locations for virtual addresses and associated physical addresses including a first storage location for the first memory address, and a storage position corresponding to the first storage location for storing the indication; and means for responding to the indication and for assuring that the at least one host instruction will not be utilized once the first memory address has been written, in which case the means for responding removes the at least one host instruction from the second memory address.