1. A method for verifying functionality of an integrated circuit system-on-chip (SoC), the method comprising: transforming a first stimulus transaction into a first response transaction, using a first model, at a first level; transforming a copy of the first stimulus transaction into a second response transaction, using a second model, at a second level lower than the first level; at a first testbench at the first level, storing the first and second response transactions in first and second response queues, respectively; and using a computer processor, verifying functionality of the SoC at the first and second levels based on the first and second response transactions retrieved from the first and second response queues, respectively.