1. A digital system having a hierarchical memory system comprising: a level 0 cache; a level 1 cache connected to the level 0 cache; a level 2 memory connected to the level 1 cache; a fill buffer connected to receive a line of data from the level 2 memory and to allocate the line of data to the level 0 cache and to the level 1 cache simultaneously; and streaming circuitry connected to the level 0 cache, the streaming circuitry operable to, when both a first data request from the CPU and a second data request from the CPU are contained within the line of data, provide the second requested data to a requester prior to allocating the line of data.