1. A processor circuit, the processor circuit comprising: a program address circuit, wherein the program address circuit includes: a branch target buffer, wherein the branch target buffer includes a plurality of entries each associated with a respective change of flow instruction, and wherein each entry includes an indication of an entry source and a next program address corresponding to the respective change of flow instruction; and a branch prediction replacement circuit, wherein the branch prediction replacement circuit is operable to determine replacement priorities of the plurality of entries, and wherein the replacement priorities are based at least in part on the entry source for each of the plurality of entries; and an execution pipeline, wherein the execution pipeline receives an executable instruction corresponding to one of the next program addresses.