1. An apparatus, comprising: an instruction-grouping circuit configured to organize a plurality of instructions for a computer processor into a plurality of instruction groups prior to execution; a plurality of execution units configured to execute the plurality of instruction groups based upon cycles of a clock signal; a delay-identification circuit including: a delay counter that is configured to count a number of cycles occurring in a time period for a first group of instructions of the plurality of instruction groups, wherein the time period is an amount of time between when a group of instructions is ready to be dispatched to one or more execution units of the plurality of execution units and when the group of instructions has been completely executed by the one or more execution units; a threshold register that is configured to store a threshold number of cycles that represents an undesired amount of delay within the time period; a delay register that is configured to store at least one effective address of at least one instruction in the first group of instructions; a delay detector circuit that is configured to: detect when the first group of instructions is delayed in the time period; in response to detecting that the first group of instructions is delayed, start the delay counter to count the number of cycles in the time period; in response to detecting that the first group of instructions is no longer delayed, stop the delay counter; compare the number of cycles counted with the threshold number of cycles; and in response to determining the number of cycles counted is greater than the threshold number of cycles, store at least one effective address of at least one instruction of the first group of instructions; and a group completion table that is configured to store data regarding the first group of instructions when the first group of instructions has been dispatched to the one or more execution units but has not been at least one of: completely executed by the one or more execution units and flushed from the apparatus; wherein the delay detector circuit is further configured to: detect when the first group of instructions is delayed from being dispatched to the one or more execution units; and detect when the group completion table is empty for one or more cycles; and wherein the delay-identification circuit communicates a frequency, from among at least a first frequency and a second frequency, for processing the first group of instructions via the one or more execution units in response to anticipating a delay in the first group of instructions.