1. Method of characterizing a CMOS logic cell to be produced in a technology of the partially depleted silicon-on-insulator type, comprising a modeling of the cell and a phase of determining the internal potentials (Vb) of the transistors of the cell in a dynamic equilibrium state, which phase is based on a functional simulation of the modeled cell using a binary stimulation signal (ST 0 ), having an initial logic value, and on a cancellation, to within a precision error, of the sum of the squares of the variations in the quantities of charge in the floating substrates (BN) of the transistors of the cell over a period (P) that encompasses two successive transitions (TRn, TRn&plus;1) of the stimulation signal.