1. A reconfigurable processor comprising: a first processor core including a plurality of first functional units which execute a portion of instructions of a first instruction set; a second processor core including a plurality of second functional units which execute a portion of instructions of a second instruction set; and a coarse grained array including a plurality of third functional units which execute another portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core, wherein the plurality of third functional units executes the other portion of instructions of the first instruction set and/or the second instruction set in parallel with the plurality of first functional units and/or the plurality of second functional units executing the portion of instructions of the first instruction set and/or the second instruction set, wherein an instruction of the first instruction set is capable of being executed by at least one third functional unit and at least one first functional unit, and wherein an instruction of the second instruction set is capable of being executed by at least one third functional unit and at least one second functional unit.