1. A method for modeling power of a pipelined processor, comprising: breaking at least one design block of the processor into a plurality of sub-blocks; determining a plurality of categories of power dissipation of each sub-block; constructing a power simulation equation for each category of power dissipation of each sub-block; determining coefficients of each power simulation equation; applying a power simulation program to each power simulation equation to calculate the power of each sub-block, and summing the power of each sub-block to calculate the power of the processor.