1. A method for scheduling instructions in an out-of-order microprocessor pipeline, said method comprising: identifying a first set of instructions awaiting scheduling to a set of execution units, the set of execution units including a first execution unit that can execute a first type of instruction and a second type of instruction and the set of execution units further including a second execution unit that cannot execute the first type of instruction; identifying a second set of instructions that is a subset of the first set of instructions, where all instructions in the second set of instructions are of the second type; identifying a third set of instructions that is a subset of the first set of instructions, where all instructions in the third set of instructions are not in the second set of instructions; and assigning the second set of instructions to the second execution unit for execution and the third set of instructions to the first execution unit for execution.