1. A method for computing, with computing equipment, a write margin for a dual-port memory array cell comprising: with computing equipment, modifying the dual-port memory array cell to include a differential noise source; with computing equipment, systematically varying a voltage setting for the differential noise source while performing write operation transient simulations for the modified dual-port memory array cell; and using results from the write operation transient simulations to determine the write margin for the dual-port memory array cell.