1. A multithreaded processor system comprising: a register file having N hardware threads, where N is an integer greater than one; an offline storage structure having M hardware threads, where M is an integer greater than or equal to one; and a thread control that inactivates a first one of the N hardware threads in the register file and activates a second one of the N hardware threads in the register file and, in response to the inactivation of the first one of the N hardware threads and the activation of the second one of the N hardware threads, unloads register values associated with a first architected state of the processor system from the inactivated thread to registers of one of the M hardware threads and loads register values from one of the M hardware threads associated with a second architected state of the processor system to the inactivated thread in the register file; wherein the register file is arranged as columns of registers with each column having N register portions, such that each of the N register portions is associated with a different hardware thread of the register file; wherein the offline storage structure is an offline register file arranged as columns of registers with each column having M register portions, such that each of the M register portions is associated with a different hardware thread of the offline register file; and wherein the M register portions and the N register portions are shift registers and a given column of M register portions associated with a respective register in the offline register file is aligned with a given column of N register portions associated with a substantially similar register in the register file, such that a shift register ring is formed that allows for the shifting register values from the one of the M hardware threads in the offline register file to the first one of the N hardware threads in the register file concurrently with the shifting of register values from the first one of the N hardware threads in the register file to the one of the M hardware threads in the offline register file.