1. A field programmable gate array, comprising: a plurality of programming conductors extending parallel to one another in a first dimension; a plurality of logic modules disposed in a row extending in said first dimension parallel to said plurality of programming conductors; a plurality of first routing wire segments extending parallel to one another in a second dimension perpendicular to said first dimension, some of said first routing wire segments I being coupled to inputs of one of said logic modules, the others of said first routing wire segments O being coupled to outputs of said one of said logic modules; a plurality of second routing wire segments extending parallel to one another in said first dimension and crossing said plurality of first routing wire segments; a plurality of antifuses disposed to programmably couple selected ones of said first and second routing wires segments together; and a plurality of programming transistors, each of said programming transistors having a first electrode coupled to a respective one of said first routing wire segments, each of said programming transistors having a second electrode coupled to one of said plurality of programming conductors, each of said programming transistors having a control electrode, wherein none of the control electrodes of the programming transistors coupled to the routing wire segments O is permanently connected to the control electrode of any programming transistor coupled to a routing wire segment I.