1. A programmable transistor array, comprising: a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other; wherein the arrangement of the BTUs is subject to restricted design rules such that the NTUs are adjacent other NTUs and DTUs but not PTUs across the rows, and the PTUs are adjacent other PTUs and DTUs but not DTUs across the rows.