1. A circuit design placement retiming method comprising: using a computer system to run a process to perform the steps of: determining at least first and second placement register placement alternatives; determining for the first register placement alternative, a first value indicative of a proportionality of delay to number of registers for a structural cycle of the first register placement alternative having a largest proportionality of delay to number of registers in the first register alternative; determining for the second register placement alternative, a second value indicative of a proportionality of delay to number of registers for a structural cycle of the second register placement alternative having a largest proportionality of delay to number of registers in the second register alternative; using the determined first and second values to evaluate the first and second register placement alternatives; selecting one of the first and second register placement alternatives based upon the evaluation; and incorporating the selected placement alternative into the circuit design.