1. An integrated memory management device comprising: an acquiring unit acquiring a read destination logical address from a first processor of one or more processors; an address conversion unit converting the read destination logical address acquired by the acquiring unit into a read destination physical address of a non-volatile main memory; an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size of the non-volatile main memory or an integer multiple of the page size of the non-volatile main memory; and a transmission unit transferring the read data to a cache memory of the first processor having a cache size that depends on the block size of the non-volatile main memory or the integer multiple of the page size of the non-volatile main memory.