1. A method of encrypting a data segment, the data segment comprising a plurality of data blocks, each data block comprising a plurality of data bits, the method comprising: encrypting a first plurality of data blocks of the data segment by (1) generating a first plurality of bit vectors, (2) reversibly combining each of the first plurality of data blocks with a corresponding one of the first plurality of bit vectors to thereby generate a first plurality of data block-bit vector combinations, and (3) performing an encryption operation on the first plurality of data block-bit vector combinations, wherein the first plurality of bit vectors have values that are independent of the encryption operations performed on the first plurality of data blocks; and encrypting a second plurality of data blocks of the data segment by (1) generating a second plurality of bit vectors based at least in part upon a value of one of the first plurality of encrypted data block-bit vector combinations, (2) reversibly combining each of the second plurality of data blocks with a corresponding one of the second plurality of bit vectors to thereby generate a second plurality of data block-bit vector combinations, and (3) performing an encryption operation on the second plurality of data block-bit vector combinations; and wherein the method steps are performed by a circuit, wherein the circuit comprises a block cipher circuit and a sequence generator circuit, the block cipher circuit comprising a plurality m of pipelined stages, the block cipher circuit pipelined stages simultaneously performing, in a pipelined fashion, a portion of the encrypting steps on a plurality m of different data block-bit vector combinations corresponding to m data blocks of the data segment, the sequence generator circuit performing the steps of generating the first and second plurality of bit vectors, the sequence generator circuit comprising counter control logic, the method further comprising the counter control logic (1) generating a count value indicative of how many data blocks of the same data segment have been processed by the block cipher circuit, (2) determining whether a condition corresponding to a feedback stride has been met such that the counter control logic determines that the feedback stride condition has been met in response to at least m data blocks of the same data segment having been processed by the block cipher circuit, (3) in response to a determination that the condition corresponding to the feedback stride has not been met, selectively controlling the generating step to generate the first plurality of bit vectors, and (4) in response to a determination that the condition corresponding to the feedback stride has been met, selectively controlling the generating step to generate the second plurality of bit vectors.