1. A pipelined microprocessor configured for long operand instructions, the microprocessor comprising: a memory unit; a load-store unit coupled to the memory unit, the load-store unit including: a data formatter, the data formatter receiving information from the memory unit and including an operand selector and a shift register portion; and an execution unit coupled to the load-store unit and receiving operand information there from, the execution unit including output latches coupled to a storage location within the execution unit for storing output information from the execution unit.