1. A memory circuit for storing and providing streams of data, said memory circuit accommodating both serial access and random access, and said memory circuit comprising: a random access memory array having an address input and a data port; a data buffer having a data port coupled to said memory array data port, said data buffer synchronizing operation of said memory array to the streams of data; an address sequencer having a data input and having an output coupled to said memory array address input, said address sequencer generating a sequence of memory addresses to be successively applied to said memory array; and an address buffer register having an output coupled to said address sequencer data input, said address buffer register supplying a random access address that initializes the sequence of memory addresses generated by said address sequencer.