1. A computer processor comprising: a plurality of functional units that perform operations over multiple machine cycles, wherein the operations produce result operands; circuitry that generates result tags dynamically according to a number of result operands produced by the plurality of functional units in a given machine cycle; a bypass network that provides data paths for transfer of result operands between the plurality of functional units, wherein result tags and corresponding result operands are broadcast together over the data paths of the bypass network; and a plurality of selector circuits associated with the plurality of functional units, wherein each selector circuit is configured to selectively route a result operand carried on a given data path of the bypass network as an input to an associated functional unit based on operation of a result tag comparator that compares a result tag carried on the given data path of the bypass network to a dynamically selected result tag; wherein the plurality of selector circuits is controlled by tag valid signals that are part of the result tags generated dynamically according to the number of result operands and carried on the data paths of the bypass network.