1. A method, comprising: receiving defect information obtained from a test wafer, wherein the test wafer was fabricated according to an Integrated Circuit (IC) design layout; receiving a plurality of first regions of interest (ROIs) based on the defect information, wherein the first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred; performing a frequency domain analysis for the first ROIs; and forecasting a wafer defect probability for the IC design layout based at least in part on the frequency domain analysis.