1. A processor comprising: a branch resolution unit configured to detect a mispredicted branch operation, wherein the branch resolution unit is configured to transmit a redirect address for fetching instructions from a correct target of the branch operation responsive to detecting the mispredicted branch operation; a redirect recovery cache comprising a plurality of cache entries, each cache entry configured to store operations corresponding to instructions fetched in response to respective mispredicted branch operations, wherein the redirect recovery cache is coupled to receive the redirect address and, responsive to the redirect address hitting in the redirect recovery cache, the redirect recovery cache is configured to supply operations from the hit cache entry to a pipeline of the processor, bypassing at least one initial pipeline stage, and wherein each cache entry is further configured to store at least one address corresponding to an instruction that is subsequent to instructions represented in the cache entry, and wherein the redirect recovery cache is configured to transmit the address from the hit cache entry; a fetch control unit coupled to receive the address from the hit cache entry; and an instruction cache coupled to the fetch control unit, wherein the fetch control unit is configured to fetch instructions from the instruction cache, and wherein the fetch control unit is configured to fetch instructions from the address received from the redirect recovery cache in response to the redirect address hitting in the redirect recovery cache.