1. A processor, comprising: at least two cores, each of the at least two cores having a first level cache memory, each of the at least two cores being multi-threaded; a crossbar; a plurality of cache bank memories in communication with the at least two cores through the crossbar, each of the plurality of cache bank memories in communication with a main memory interface; a plurality of input/output (I/O) interface modules in communication with the main memory interface and providing a link to the at least two cores, the link bypassing the plurality of cache bank memories and the crossbar; and threading hardware configured to enable each of the at least two cores to switch from a first thread to a second thread on a cycle-by-cycle basis using storage that includes a plurality of pipeline registers for each thread and a register file for each thread, wherein the first and second threads are not continuously stored, wherein the switch from the first thread to the second thread depends at least in part on a round robin scheduling of any threads that are not blocked, wherein the threading hardware further includes (a) duplicated register files associated with each of the at least two cores, wherein each duplicated register file has a second nonstandard write port, and (b) a first set of duplicated pipeline registers downstream from instruction fetch stage logic and a second set of duplicated pipeline registers downstream from decode/branch stage logic.