1. A vector processing apparatus, comprising: a main storage, transfer means connected to said main storage for fetching vector data elements from said main storage and for storing vector data elements into said main storage; at least one operation means for performing an operation on inputs provided to said operation means and providing outputs corresponding to results to results of the operation; a plurality of vector registers connected to said transfer means and said operation means, each for holding at least a set of vector data elements; a plurality of access means each connected to a corresponding addresses for storage locations within a corresponding vector register to write or read vector data elements in or from said corresponding vector register connect means responsive to program instructions for selectively connecting said vector registers to said transfer means and to said operation means, so that vector data elements read out from said corresponding vector register are provided to said operation means as the inputs thereto or to said transfer means as the vector data elements to be stored into said main storage, or so that the outputs of said operation means or vector data elements fetched by said transfer means are written into said corresponding vector register; and means for setting an initial address which may differ from a start address of said storage locations of said one vector register in one of said plurality of access means for a vector register so as to enable said access means for that vector register to effect generation of sequential addresses starting from an initial storage location designated by the initial address.