1. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates; a service processor unit configured to perform one or more debug operations on one or more of said logic blocks, the service processor unit comprising: a control unit, a buffer memory, an analysis engine, and a bus interface; and a multiplicity of probe lines configured to capture and propagate one or more of said one or more system operation signals from said logic blocks to said service processor unit during normal system operation; wherein said analysis engine is configured to align signals received from said probe lines during normal system operation.