1. A vector processing system comprising: a circuit for receiving an instruction identifying a plurality of operands and specifying an operation, wherein each of the plurality of operands comprises a plurality of bits; a plurality of parallel processing units corresponding to each of said plurality of bits of said plurality of operands, each arranged to generate a result according to the operation on particular one bits of the each of the plurality of operands, wherein a parallel processing unit in the plurality of parallel processing units comprises an accumulator that is selectively operable to accumulate sequential results; and a scalar processing unit for generating a composite result according to the accumulated sequential results and/or the results from a selected number of parallel processing units.