1. A low-density parity check (LDPC) decoder comprising: a computational memory array having at least a variable node section comprising at least one block of variable nodes and a check node section comprising at least one block of check nodes associated with said least one block of variable nodes, said block of variable nodes and said associated block of check nodes comprising a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on said bit and a group of cells implementing one node; and a controller to instruct said computational memory to: perform said operations inside said computational memory on said block of variable nodes and write results of computations associated with said variable node operations into said associated block of check nodes; and perform said operations in said computational memory on said associated block of check nodes and write results of computations associated with said check node operations into said associated block of variable nodes, wherein said results of said computations associated with said variable node operations and said check node operations are transferred between said block of variable nodes and said block of associated check nodes through bit lines in said computational memory.