1. A data processing apparatus comprising: processing logic operable to execute a plurality of program threads; a cache operable to store data values for access by the processing logic, the processing logic being operable when access to a data value is required whilst executing a first program thread to issue an access request specifying an address in memory associated with that data value, and the cache being operable in response to the address to perform a lookup procedure to determine whether the data value is stored in the cache; indication logic operable in response to an address portion of the address to provide an indication as to whether the data value is stored in the cache, said indication being produced before a result of the lookup procedure is available, and the indication logic being operable to only issue an indication that the data value is not stored in the cache if that indication is guaranteed to be correct; and control logic operable, if the indication indicates that the data value is not stored in the cache, to use said indication to control a process having an effect on a program thread other than the first program thread; the processing logic comprising a plurality of processors each sharing access to the cache, and each being operable when access to a data value is required to issue an access request specifying an address in memory associated with that data value; the plurality of program threads being distributed across the plurality of processors; the indication logic being operable in response to at least some of the access requests to provide said indication; and the control logic comprising arbitration logic operable to perform an arbitration process to arbitrate access to the cache between the plurality of processors, the process controlled by said indication being the arbitration process, and the arbitration logic being arranged to use the indications provided by the indication logic when performing said arbitration process, wherein the indication logic comprises: counter logic having a plurality of counter entries, each counter entry containing a count value; vector logic having a vector entry for each counter entry in the counter logic, each vector entry containing a value which is set when the count value in the corresponding counter entry changes from a zero value to a non-zero value, and which is cleared when the count value in the corresponding counter entry changes from a non-zero value to a zero value; index generation logic operable to generate from an address portion of an address at least one index, each index identifying a counter entry and associated vector entry; the index generation logic being operable whenever a data value is stored in, or removed from, the cache to generate from the address portion of the associated address said at least one index, and to cause the count value in each identified counter entry to be incremented if the data value is being stored in the cache or decremented if the data value is being removed from the cache: the index generation logic further being operable for at least some access requests to generate from the address portion of the associated address said at least one index, and to cause the vector logic to generate an output signal based on the value in each identified vector entry, the output signal indicating if the data value of the access request is not stored in the cache, wherein: a memory hierarchy exists within the data processing apparatus having a number of memory levels, the cache being provided at one of said memory levels, and when processing access requests memory levels higher in the hierarchy being accessed before memory levels lower in the hierarchy; and whilst the vector logic and the counter logic are both associated with the cache, the vector logic is accessible separately to the counter logic and from a different level in the memory hierarchy to that memory level from which the counter logic is accessible.