1. A non-volatile memory, comprising: an array of multi-state non-volatile memory cells connected along word lines and bit lines; row control circuits including word line driving circuitry connectable to the word line along which a plurality of selected memory cells from the array are connected whereby a plurality of word line voltage levels are applicable thereto; and source control circuitry connectable to a common source line of the selected memory cells for applying a first voltage level greater than ground thereto; column control and data input/output circuitry connectable to the bit lines of the selected memory cells, including sensing circuitry connectable to a corresponding one or more sensing nodes of the one or more selected memory cells, whereby the memory can determine the state of the selected memory cells in a process comprising: discharging the memory cells to ground through the corresponding bit lines; subsequently applying the first voltage level to the common source line; subsequently applying a first of said word line voltage levels to the word line while continuing to apply the first voltage level to the common source line; in response to applying the first word line voltage level to the word line, determining whether the data content of each of the selected memory cells corresponds to one of a first subset of said multi-states; subsequently applying a second of said word line voltage levels to the word line while continuing to apply the first voltage level to the common source line, wherein the second word line voltage level differs from the first word line voltage level; and in response to applying the second word line voltage level to the word line, determining whether the data content of each of the selected memory cells corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.