1. A processor comprising: a general purpose processor core; a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores, the 3D integrated circuit stack coupled to the general purpose processor core; and interconnect logic having at least one data channel, to interconnect the graphics processor cores of the 3D integrated circuit stack and couple the graphics processor cores with a shared resource, the interconnect logic further to enable data distribution between the graphics processor cores and the shared resource over a virtual channel including multiple programmatically pre-assigned traffic classifications.