1. A central processing unit (CPU) comprising: an interrupt unit for interrupting execution of instructions; a plurality context defining register sets, wherein each set of registers having the same number of CPU registers; a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of said plurality of context defining register sets upon occurrence of an exception; and a control register configured to control selection of a register set of said plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.