1. A digital processing unit for executing program instructions stored in at least two memories and comprising at least one first register of temporary storage of an operator of a current instruction to be executed and at least one second register of temporary storage of at least one argument or operand of said current instruction, comprising a protection circuit for submitting, upstream of said first register, said operator to a deciphering function if this operator originates from one of the memories or from an area of these memories, identified from the address provided by a program counter, said argument or operand being not submitted to said deciphering function.