1. A method of automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues comprising: identifying a set of target regions and a set of reference regions from a design layout; utilizing a processor to generate a reference baseline of layout patterns from the set of reference regions; utilizing the processor to compare a frequency profile of layout patterns in the set of target regions to a frequency profile of layout patterns in the reference baseline; and based on the comparison, utilizing the processor to identify candidate layout patterns from the set of target regions for further analysis.