1. A compression circuit in a processor-based system, the compression circuit configured to, in response to eviction of a cache entry in a cache memory: receive uncompressed cache data and a virtual address associated with the evicted cache entry in the cache memory; compress the uncompressed cache data into compressed data of a compression size; read first metadata from a metadata cache associated with the virtual address associated with the evicted cache entry, the metadata cache comprising a plurality of metadata cache entries each indexed by a virtual address, each metadata cache entry among the plurality of metadata cache entries comprising metadata associated with a physical address in a compressed system memory; read second metadata from a metadata circuit in the compressed system memory associated with the virtual address associated with the evicted cache entry into the metadata cache, the metadata circuit comprising a plurality of metadata entries each indexed by a virtual address, each metadata entry among the plurality of metadata entries comprising metadata associated with a physical address in the compressed system memory; in response to the first metadata associated with the virtual address associated with the evicted cache entry not being available from the metadata cache after compressing the uncompressed cache data into the compressed data of the compression size, the compression circuit is further configured to: obtain an index to a new memory block in a memory entry associated with a new physical address from a free list; and store the compressed data in the new memory block at the memory entry at the new physical address in the compressed system memory based on the obtained index; store new metadata associated with the new physical address of the new memory block in a metadata buffer; and store the new metadata from the metadata buffer in the metadata entry associated with the virtual address associated with the evicted cache entry in the metadata circuit in the compressed system memory.