1. A method for detecting a timing channel in a hardware design, the method comprising: receiving a hardware design; synthesizing at least one portion of the hardware design with gate level primitives; adding tracking logic to the gate level primitives to monitor information flow through the gate level primitives; simulating sets of inputs to the gate level primitives including added taint inputs to identify information flows by generating outputs from the gate level primitives for every clock tick while changing only taint inputs; isolating timing flows from information flows by conducting input-to-output deterministic traces to isolate functional flows in the information flows.