1. A cache controller for use with a processor, comprising: a plurality of mappers for receiving instructions of a first instruction set, each mapper for mapping an instruction of said first instruction set to a predetermined instruction width format (PIWF) configuration; and a multiplexor for receiving said PIWF configurations from said plurality of mappers and selecting, in response to a selector signal, a desired one of said PIWF configurations for decoding and execution by the processor.