1. A system comprising multiple memory blocks spanning a plurality of power domains, said system comprising: a Shared Fuse Wrapper architecture for storing the repair data of the memory blocks on a centralized fuse macro cell operatively coupled therewith; at least one repair data register operatively coupled with a corresponding memory block, for storing memory repair data thereon and for transmitting the memory repair data thereto to effect repairs of the corresponding memory block; and a plurality of parallel links connecting the memory blocks of the plurality of power domains to the Shared Fuse Wrapper architecture, wherein the capacity of said fuse macro cell is given by a function of a number of redundancy memories in a power domain, a length of total repair data in a power domain, a minimum number of memories to be repaired, a number of bypass flops corresponding to logical addresses, and a largest repair data length corresponding to the minimum number of memories to be repaired across power domains.