1. A semiconductor memory device comprising: a memory cell array comprising memory cells in a matrix arrangement; a data inverter configured to invert data in the memory cells and to write the inverted data in the memory cells; an address counter configured to increment or decrement an internal address when the data inverter writes the inverted data; and a decoder configured to select a first memory cell comprising data to be inverted by the data inverter based on the internal address designated by the address counter.