1. A system for providing processor-based security, comprising: a processor having a processor core, a cache memory, a plurality of registers for storing at least one hash value, and a memory interface; and at least one on-chip instruction for performing a secure launch of a hypervisor program, the instruction causing the processor to: compute a first storage hash value over a current state of a first hypervisor program; compare the first storage hash value to a second storage hash value stored in the plurality of registers; if the first storage hash value matches the second storage hash value, allow the first hypervisor program corresponding to the first storage hash value to access contents of a secure storage area in a non-volatile memory previously stored by a second hypervisor program corresponding to the second storage hash value; and if the first storage hash value does not match the second storage hash value, preventing access to the contents stored in the secure storage area and allocating a new secure storage area for the first hypervisor, and copying the first storage hash value into a register containing the second storage hash value, wherein the processor encrypts and hashes data written to, and decrypts and verifies hashes of data read from, the secure storage area using a first on-chip encryption key and a first on-chip storage hash value, wherein the processor encrypts and hashes data written to, and decrypts and verifies hashes of data read from, a secure storage area corresponding to a first trusted software module using a second encryption key and a second storage hash value, and wherein the secure storage area corresponding to the first trusted software module program is defined by a module identity, an encryption key, and a pre-defined storage hash value.