1. A system on a chip (SoC) comprising: memory to store a set of instructions; and a processor core coupled to the memory and comprising a configuration bit register to store configuration bits, wherein the processor core is to: identify a region of code in the set of instructions demarcated by a first instruction of the set of instructions; determine whether a first metric, resulting from execution of the region of code with the configuration bits set to a first value, is lower than a second metric, resulting from execution of the region of code with the configuration bits set to a second value; and set the configuration bits to the first value to increase a performance of the processor core, decrease power consumption of the processor core, or both for subsequent execution of the region of code.