1. A multiprocessor system comprising: a plurality of data processing units, each of the data processing units: (a) being programmable; and (b) being adaptable for sequentially processing data in a clocked manner; and including (c1) at least one Arithmetic Logic Unit (ALU), and (c2) at least one data register set for storing intermediate results in sequential data processing; at least one bus system for at least interconnecting at least some of the data processing units, each being provided a supply voltage by a voltage supply; wherein for at least some of the data processing units, the clock frequency is adjustable at runtime without affecting the clock frequency of at least one of: one other of the data processing units, and the bus system; and wherein the voltage supply is adapted to supply higher supply voltages for data processing at higher clock frequencies.