1. A memory device comprising: a memory integrated circuit chip including at least: a non-volatile memory array including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip, the non-volatile memory array further including at least one memory segment configured to store data in a binary symmetric form wherein single data bits are stored in redundant pairs; and control logic including one or more logic layers integrated in combination with the one or more layers of discrete storage cells and distributed extending laterally over the non-volatile memory array, the control logic operable to maintain a plurality of copies of data in the non-volatile memory array and detect one or more errors by comparison of selected one or more of the plurality of copies, the control logic further operable to detect bit-errors by comparison of selected ones of the plurality of copies wherein a difference in a redundant pair is indicative of bit-error and likeness in a redundant pair is indicative of correctness.