1. A fail safe differential receiver circuit wherein a fail safe condition includes loss in amplitude of the differential signal and wherein the signal frequency is lower than a defined limit, the circuit comprising: a differential amplifier, two complementary auxiliary differential amplifiers, each auxiliary amplifier incorporating complementary offset voltages set to a value, wherein the input differential signal is connected to the differential inputs of the differential amplifier and of the two auxiliary amplifiers, a frequency detector that detects when the input differential signal is less than a frequency limit, a logic circuit that receives inputs from the frequency detector and the two auxiliary amplifiers, wherein the logic circuit determines that, when the differential signal amplitude is less than the value and the frequency is less than the frequency limit, the logic circuit fail safe condition is activated.