1. A security system for a microprocessor based system having multiple subsystems for ensuring that power consumption of the microprocessor based system is not indicative of a plurality of instructions that the microprocessor is executing, the security system comprising: a power correlator for estimating power that each instruction of the plurality of instructions will consume during its execution; and a subsystem inhibition control, coupled to said power correlator, for utilizing said estimated power, and for selectively turning on/off ones of the multiple subsystems within the microprocessor based system during execution of the instructions, wherein the ones of the multiple subsystems that are turned on/off are selected so as to disassociate total power consumed by the microprocessor based system from the instructions it is executing.