1. A reconfigurable processor comprising: a plurality of memories divided into a plurality of different areas, the different divided areas corresponding to respective different threads from a plurality of threads and with sizes proportional to the respective different threads, with corresponding areas of the different divided areas storing context information of the respective different threads; and a plurality of function units to perform a corresponding calculation based on received context information stored in an area, from the different divided areas, corresponding to a respective thread indicated to be executed, wherein the plurality of memories include a plurality of local register files each divided into a plurality of local register file areas, where each local register file area of a local register file is respectively configured to collectively store information for different threads from a particular function unit configured to execute the different threads, with the particular function unit being paired with the local register file distinguished from a different particular function unit paired with a different local register file, and wherein the plurality of memories receive identification information of the respective thread to be executed and make available to the plurality of function units the area, the area being mapped to the identification information.