1. A multiprocessing system, comprising: a multithreading microprocessor, comprising: a first plurality of thread contexts; a translation lookaside buffer (TLB), shared by said first plurality of TCs; and an instruction scheduler, coupled to said first plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on said first plurality of TCs; a multiprocessor operating system (OS), configured to schedule execution of said threads on said first plurality of TCs, wherein a thread of said threads executing on one of said first plurality of TCs is configured to update said shared TLB, and prior to updating said TLB to: disable interrupts, to prevent said OS from unscheduling said TLB-updating thread from executing on said first plurality of TCs; and disable said instruction scheduler from dispatching instructions from any of said first plurality of TCs except from said one of said first plurality of TCs on which said TLB-updating thread is executing; wherein said multithreading microprocessor further comprises: a virtual processing element (VPE), bound to said first plurality of TCs, wherein said VPE is an exception domain for said first plurality of TCs; wherein said TLB-disabling thread disabling interrupts comprises disabling interrupts on said VPE; wherein said multithreading microprocessor further comprises: a second plurality of TCs; and a second VPE, bound to said second plurality of TCs, wherein said second VPE is an exception domain for said second plurality of TCs; wherein said TLB-disabling thread is further configured, prior to updating said shared TLB, to disable said instruction scheduler from dispatching instructions from any of said first and second plurality of TCs except from said one of said plurality of TCs on which said TLB-updating thread is executing; and wherein said TLB-disabling thread is further configured, after updating said shared TLB, to restore said instruction scheduler to an instruction-dispatching state said instruction scheduler was in prior to disabling said instruction scheduler from dispatching instructions from any of said first and second plurality of TCs except from said one of said plurality of TCs on which said TLB-updating thread is executing.