1. An information processing device for mitigating busy time in a hierarchical store-through memory cache structure, the information processing device comprising: a plurality of processing cores; at least one memory cache communicatively coupled to the plurality of processing cores; at least one cache directory associated with the at least one memory cache, wherein the at least one cache directory comprises a plurality of portions each associated with a portion of the at least one memory cache; a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory, wherein the shared cache pipeline comprises at least one pipeline partitioned into a first subpipe and at least a second subpipe; and at least one cache controller communicatively coupled to the at least one memory cache and the plurality of processing cores, wherein the at least one cache controller is configured to perform a method comprising: determining that at least two or more store requests satisfy a set of conditions to be processed simultaneously, wherein a store request comprises a set of store information comprised of at least a store address; performing, in the shared cache pipeline and based on the determining, simultaneous cache lookup operations between the plurality of portions of the cache directory, wherein the performing comprises simultaneously performing a first cache lookup operation on a first of the plurality of portions based on a first set of store information within the first subpipe, wherein the first set of store information is associated with a first of the two or more store requests, and at least a second cache lookup operation on at least a second of the plurality of portions based on at least a second set of store information within the second subpipe wherein the at least second set of store information is associated with at least a second of the two or more store requests; and performing a first write operation based on the first cache lookup and at least a second write operation based on the second cache lookup.