1. A memory circuit comprising: a first die; a first dynamic random access memory (DRAM) array configured as a content addressable memory (CAM) located on the first die, wherein the CAM comprises a first block of a plurality of DRAM cells configured for storing a first reference pattern and a second block of a plurality of DRAM cells configured for receiving a first input pattern; and a second DRAM array configured as a random access memory (RAM) located on the first die, wherein the RAM comprises a third block of a plurality of DRAM cells configured for storing a second reference pattern.