1. A processor connected to a different processor via an interconnection network, and also connected to a main storage device, the processor comprising: a directory cache provided with a data cache configured to hold data and a memory directory configured to hold directory information indicating whether or not data stored in the main storage device is held in a data cache of a different processor, configured to hold dirty information indicating whether or not the held directory information is the same as the directory information held in the memory directory, and local information indicating that the directory information of the memory directory is not held in a data cache of a different processor when the directory information from the memory directory is registered; and a control circuit configured to make a setting such that the directory information of the memory directory is the same as directory information held in a data cache of a different processor as dirty information of the directory cache when the directory information of the directory cache and the local information of the directory cache indicate that the directory information of the memory directory is not held in the data cache of the different processor.