1. A method for designing a semiconductor circuit arrangement, comprising: providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros; using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform; and extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software.