1. A nonvolatile semiconductor memory comprising: a memory core section having a plurality of cell array blocks each including a plurality of nonvolatile memory cells, a plurality of word lines and a plurality of bit lines; a column address decoder for specifying a column address in said cell array block; a block address decoder for specifying an address of said cell array block; a programming load for outputting a voltage corresponding to programming data to be programmed into said memory cell array; and a row decoder for selecting the word line; wherein said bit line is selected by the column address and the block address and said block address decoder sets said plurality of blocks into a selected state and supplies the output of said programming load to said plurality of bit lines to effect the data programming operation.