1. A method for evaluating assertions for verifying a circuit design, the method comprising: identifying m semantically equivalent assertions, wherein each of the m semantically equivalent assertions is evaluated using n logical expressions; determining a set of vectors based on the m semantically equivalent assertions, wherein each vector element corresponds to a logical expression that is used for evaluating one of the m semantically equivalent assertions; and evaluating, by computer, the m semantically equivalent assertions using the set of vectors.