1. A hardware emulation system for verifying electronic circuit designs including a design memory system having a design memory depth that comprises a predetermined number of design memory registers and a design data width that includes a preselected quantity of design data bits that can be stored in each of the design memory registers, comprising: a emulation memory system having a emulation memory depth that comprises a predetermined number of emulation memory registers and a emulation data width including a preselected power-of-two quantity of emulation data bits; and a compiler system that maps the design memory system to said emulation memory system by: factorizing the design data width of the design memory system to form a plurality of design memory sub-regions having respective sub-region memory depths that are equal to the design memory depth and respective sub-region data widths that include respective portions of the design data bits, the design data width being spanned by said sub-region data widths, said respective sub-region data widths being equal to said emulation data width divided by respective predetermined integer values; selecting a selected design memory sub-region with a selected sub-region memory depth and a selected sub-region data width that is equal to said emulation data width divided by a selected integer value; identifying sub-region register contents within the design memory registers, said sub-region register contents comprising memory contents within the design memory registers that are associated with the selected design memory sub-region; dividing said selected sub-region memory depth into a plurality of sub-region memory depth groups each including the selected integer value of the design memory registers; and storing said sub-region register contents associated with each respective sub-region memory depth group in a side-by-side manner across a selected emulation memory register of said emulation memory system.