1. A system adapted to implement delay reduction during technology mapping into a programmable logic device, the system comprising: one or more computer devices; and one or more storage devices storing computer readable program code configured to cause operations for the technology mapping, the program code readable by the one or more computer devices to: locate critical fan-in nodes in mapping logic of the programmable logic device; create replicating logic for the critical fan-in nodes; perform parallel computation on the critical fan-in nodes and on non-critical nodes in the mapping logic; and select output at a last critical fan-in node after performing the parallel computation.