1. A computer processor comprising: a plurality of execution pipelines, each execution pipeline comprising a configuration of one or more execution units of the processor, each execution pipeline characterized by an execution pipeline type, each execution pipeline type determined according to the types of computer program instructions executed in each execution pipeline; a plurality of hardware threads of execution, each hardware thread comprising computer program instructions characterized by instruction types, each hardware thread comprising sequences of instructions of a same instruction type, the sequences interspersed with instructions of other types, wherein each hardware thread includes a register for storing instructions; synchronization detection circuitry capable of detecting synchronization of sequences of instructions of a same type among two or more hardware threads, wherein synchronization occurs when two or more threads present sequences of a same instruction type at the same time; and an instruction dispatcher capable of: dispatching instructions preferentially during a predefined preference period from a preferred hardware thread to a particular execution pipeline in dependence upon whether the preferred hardware thread presents a sequence of instructions, ready for execution from the preferred hardware thread, of a type for execution in the particular execution pipeline; designating as the preferred hardware thread a hardware thread in which such synchronization is detected; and dispatching instructions preferentially from such a designated preferred hardware thread when such synchronization is detected.