1. A data processing circuit, the data processing circuit comprising: a variable gain amplifier operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output; a gain circuit operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output; and a hybrid gain feedback combination circuit operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.