1. A system for coupling additional memory to a plurality of processors, comprising: a switching device; a plurality of processors, the plurality of processors each coupled to the switching device; a plurality of memory modules coupled to the plurality of processors, wherein at least one memory module of the plurality of memory modules is coupled to a processor of the plurality of processors; additional memory that is distinct from the plurality of memory modules, the additional memory coupled to the switching device; and a controller, wherein the controller is adapted to signal the switching device to couple the additional memory to a processor from the plurality of processors, and wherein the controller uses parameters to determine a priority, in terms of duration, of an exclusive use of the additional memory by the processor from the plurality of processors.