1. A non-volatile memory apparatus, comprising: a non-volatile memory array; and a controller in communication with the memory array, the controller configured to: receive an n-bit data block which would, without encoding, require a first number of programmed bits to store in the memory array, n comprising an integer; analyze at least a part of the n-bit data block; determine whether to encode the n-bit data block based on the analysis; and if it is determined to encode the n-bit data block based on the analysis, encode the n-bit data block as an n+k-bit data block, k comprising an integer, by inverting at least some the bits in the n-bit data block and instructing a second number of programmed bits to be stored in the memory array, the second number less, on average, than the first number.