1. A hardware circuit for returning scalar single precision denormal results to double precision normal results in architected format, the hardware circuit comprising: a hardware circuit component configured to count leading zeros of an unrounded single precision denormal result; a hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result; and a hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.