1. A processor, comprising: a memory hierarchy; a buffer for input to the memory hierarchy; and a compression module including: a first logic to read elements to be compressed according to a compression scheme; a second logic to selectively modify a format of the compression scheme based upon a number of literals received; a third logic to modify the format of the compression scheme with respect to information in an output data sequence at a position located before the literals; a fourth logic to compress, in hardware, the elements to produce the output data sequence; and a fifth logic to send the output data sequence to the memory hierarchy.