1. A processor comprising: an instruction fetch unit configured to fetch instructions from a memory; a plurality of architectural flags, wherein at least one architectural flag is configured to store data indicative of a result of an execution of an instruction; and an instruction decode unit coupled to the instruction fetch unit and configured to: decode fetched instructions into micro-operations for execution by an execution unit; detect an occurrence of an arithmetic instruction followed by a first branch instruction in program order, wherein the first branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction regardless of respective values of the plurality of architectural flags; fuse together the arithmetic instruction and the first branch instruction such that a first single micro-operation is formed, wherein the first single micro-operation includes execution information based upon both the arithmetic instruction and the first branch instruction; discard the arithmetic instruction in response to a formation of the first single micro-operation; and an execution unit including an adder, wherein the execution unit is configured to: execute the first single micro-operation; wherein the adder is configured to generate a flag set signal using execution information based on the arithmetic instruction; halt a propagation of the flag set signal to the plurality of architectural flags; and generate a result of the first single micro-operation using the flag set signal regardless of the respective values of the plurality of architectural flags.