1. A bit counting device comprising: a first data register for storing a data word; an offset register for storing an offset value; a second data register; a one-cycle shifter, electrically coupled to the first data register, to the second data register, and to the offset register, for shifting the data word by a value stored in the offset register and storing the shifted data word in the second data register; a third data register; and at least one carry save adder (CSA) device, electrically coupled to the second data register and to the third data register, for counting the number of bits set to one in the data word stored in the second data register and storing in the third data register a value representing the count of bits set to one in the data word.