1. An integrated semiconductor dynamic memory comprising: a memory matrix containing memory cells divided into two groups; a plurality of select buses of said memory matrix located along a respective matrix line; a plurality of first number buses of said memory matrix located along a respective matrix column; a plurality of second number buses of said memory matrix located along a respective matrix column parallel to said first number bus; memory cells of a first group of memory cells having a first termminal connected to a respective select bus and a second terminal connected to a respective first number bus; memory cells of a second group of memory cells having a first terminal connected to a respective select bus and a second terminal connected to a respective second number bus; a plurality of differential amplifiers, the number of which being equal to that of the columns in said memory matrix, having information terminals connected to respective first and second number buses; said memory cells belonging to different groups and connected to respective number buses so that along a column they are interspaced by at least one memory cell; a memory matrix line decoder to which said memory matrix select buses are connected; data input/output buses; memory matrix column select keys connecting at least one of said number buses of a respective column to said data input/output buses; a matrix column decoder having outputs connected to a control unit of said matrix column select keys; a numeric data input/output unit having outputs connected to said data input/output buses; a control unit having outputs connected to respective control inputs of said column differential amplifiers, of said matrix line decoder, of said matrix column decoder and of said numeric data input/output unit.