1. A superscalar microprocessor for processing instructions, the microprocessor comprising: an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order; a branch prediction circuit configured to provide a branch bias signal indicating whether a conditional branch controlled by a conditional branch instruction is predicted to be taken or not taken; an instruction buffer coupled to receive fetched instructions from the instruction fetch unit and configured to buffer a plurality of fetched instructions, including an instruction selected according to the branch bias signal; a plurality of functional units configured to execute instructions, thereby generating result data; a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file; a resource identifying circuit configured to concurrently identify execution resources for a first one and a second one of a plurality of buffered instructions, wherein the second one of the buffered instructions has a data dependency on the first one of the buffered instructions, thereby making a plurality of instructions concurrently available for issue, wherein the identified execution resources for each of the available instructions includes a functional unit capable of executing the instruction; a register rename circuit configured to provide references to locations in the register file for logical register references included with the plurality of buffered instructions; an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and availability of respective operands for each instruction in the referenced locations in the register file, without regard to the sequential program order; a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file; and bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via an alternate data path that bypasses the register file, wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file.