1. An embedded ROM-based processor system comprising: a processor; system memory, coupled to said processor, including a read-only memory (ROM); a programmable memory that stores patch information including patch code and one or more patch vectors, each patch vector comprising a break-out address from said ROM and a patch-in address to a corresponding location within said patch code; a data selector having an input coupled to said system memory and an output coupled to said processor; and a patch controller, coupled to said processor and said selector, operative to compare an address provided by said processor with each break-out address to determine a breakout condition, and to control said selector to transfer said processor to a corresponding location within said patch code in response to said break-out condition.