1. A processor, comprising: an instruction buffer comprising a plurality of instruction entries; a content addressable memory (CAM) array unit coupled to said instruction buffer, said CAM unit comprising a first array having two cycle CAM entries corresponding to a set of said instruction entries, and a second array having one cycle CAM entries corresponding to a set of said instruction entries, each CAM entry storing at least one source tag for the corresponding instruction entry, the content addressable memory array unit receiving a result tag from an execution circuit over a result bus, each CAM entry generating a CAM match signal if the result tag matches the source tag; a ready generation circuit coupled to said CAM array unit, said ready generation circuit receiving the CAM match signals and selecting the instruction entry that corresponds to the source tag for dispatch to the execution circuit.