1. A method for enhancing register transfer level (RTL) simulation, the method comprising: accessing an RTL file and a sideband file for a design; identifying design constraints in the sideband file, the design constraints including multi-cycle paths; using a computer, modifying the design by duplicating portions of the multi-cycle paths to create modified multi-cycle paths, inserting delays in the modified multi-cycle paths, and cutting the multi-cycle paths from their sources; and simulating the modified design during the RTL simulation.