1. A method for generating a partial stochastic rounding operation including managing hardware mechanisms to add a random number to an intermediate result executed by a processor coupled to a memory, the processor including wires routing outputs of a random number generator to inputs of a rounder, comprising: generating the intermediate result from at least two operands; causing the random number generator to generate the random number, the random number comprising M bits; inputting the random number to the rounder; causing the rounder to add the random number to M most significant bits of N lower significant bits of the intermediate result to perturb any incrementing of most significant bits of the intermediate result to produce a resulting sum, wherein M<N; and truncating the N lower significant bits from the resulting sum into a final result, wherein the intermediate result comprises guard bits followed by a sticky bit of all the remaining bits, wherein the intermediate result with the guard bits and the sticky bit are added to the random number and the final result is truncated.