1. A performance invarient execution apparatus for non-communicative instructions comprising: a first and a second addressable operand file, each having a first and a second output port; a first multiplexer inputted by said first output ports of said first and second operand file; a second multiplexer inputted by said second output ports of said first and said second operand file; a first and a second working register inputted respectively by said first and said second multiplexer; a plurality of execution units, each execution unit therein inputted by both said first and said second working register and each execution unit thereof having an operation code input for receiving an operation code specifying an operation to be executed; a common bus for transferring outputs from said plurality of execution units to said second addressable operand file; means for addressably writing from said common bus into said second addressable operand file; first operand means for reading an operand into said first working register, said first operand means addressing in parallel said first and second addressable operand files for reading operands in parallel from said first ports thereof, and addressing said first multiplexer for selecting operand passage therethrough to said first working register; and second operand means for reading an operand into said second working register, said second operand means addressing in parallel said first and said second addressable operand files for reading operands in parallel from said second ports thereof, and addressing said second multiplexer for selecting operand passage therethrough to said second working register.