1. An information processing apparatus comprising: a plurality of nodes each including a storage device; and an interconnect that connects the plurality of nodes, wherein at least one node among the plurality of nodes includes: a first processor that detects abnormality in a data transmission path of data transmission using a shared memory area sharable in the one node and another node, which is included in a storage device provided in the one node or the another node, or abnormality in a certain node included in a data transmission path of data transmission using a shared memory area sharable in the one node and the another node, which is included in a storage device provided in the one node or the another node, generates error information, based on the detected abnormality, and generates an interrupt with respect to a processor within the one node; a second processor that performs recovery processing, based on the error information according to the interrupt; and a cache memory that caches data, and when the second processor receives the interrupt, the second processor deletes the data cached in the cache memory, when performing the recovery processing, based on the generated error information.