1. A high-speed input buffered packet switch, comprising: a switching fabric which connects input ports to output ports; for each input port, an input pointer which references an output port; for each output port, an output pointer which references an input port; an arbiter, comprising: an input credit allocator which resets input credits associated with input/output pairs and which updates the input pointers, an output credit allocator which resets output credits associated with input/output pairs and which updates the output pointers, and a matcher which matches inputs to outputs based on pending requests and available input and output credits; and a scheduler which schedules transmissions through the switching fabric according to the arbiter's matches.