1. A multi-core microprocessor that supports a plurality of operating states representing different levels of performance and power consumption, the microprocessor comprising: a plurality of cores; a control unit configured to put selected cores into selected operating states at selected times; and a core-specific synchronization register external to each core and readable by the control unit; wherein each core is configured to respond to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register; and wherein the control unit is configured to cause a power saving action that affects a shared resource provided that the action does not reduce performance of any core sharing that resource below its target operating state.