1. A method of emulating a circuit design using an emulator, the method comprising: allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design; and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.