1. A circuit for converting M-bits of an input data word having M+A bits in addition to an input parity bit having a predetermined parity value, to B-bits of an output data word having B+A bits in addition to an output parity bit, comprising: a code conversion circuit responsive to the input M-bits for generating a converted data word having B-bits plus a secondary parity bit which gives the converted data word a parity value the same as that of the input M-bits; and means for exclusive-ORING the input parity bit and the secondary parity bit to produce an output parity bit, whereby the output data word comprises the A and B bits in addition to the output parity bit which gives the output data word a parity value which is the same as that of the first data word.