1. An integrated circuit comprising: (a) a test data in lead; (b) a test data out lead; (c) a test clock in lead; (d) a test mode select in lead; (e) TAP controller circuitry coupled to the test clock in lead and the test mode select in lead and having control outputs that include a Clock-DR output; (f) instruction register circuitry coupled between the test data in lead and the test data out lead, the instruction register circuitry having control inputs coupled with the control outputs; (g) boundary scan circuitry coupled between the test data in lead and the test data out lead, the boundary scan circuitry having control inputs coupled with the control outputs, the control inputs including a delayed Clock-DR input; and (h) clock delay circuitry including: (i) course delay register circuitry and fine delay register circuitry coupled in series between the test data in lead and the test data out lead, the course delay register circuitry and fine delay register circuitry each having parallel select outputs; (ii) separate course delay circuits, each separate course delay circuit having an input coupled with the test clock in lead and having a time delay output; (iii) course select circuitry having select inputs coupled to the time delay outputs of the course delay circuits, course select control inputs coupled with the select outputs of the course delay register circuitry, and a course delayed clock out lead; (iv) separate fine delay circuits, each separate fine delay circuit having an input coupled with the course delayed clock out lead and having a time delay output; and (v) fine select circuitry having select inputs coupled to the time delay outputs of the fine delay circuits, fine select control inputs coupled with the select outputs of the fine delay register circuitry, and a fine delayed clock out lead coupled with the delayed Clock-DR input.