1. A method comprising: receiving, at least in part, data corresponding to a predetermined problematic layout pattern, the problematic layout pattern being associated with at least one performance characteristic, the problematic layout pattern being one or more geometric elements; receiving, at least in part, data corresponding to an integrated circuit layout design; scanning the integrated circuit layout design for the one or more geometric elements of the problematic layout pattern; identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern; and modifying a netlist associated with the integrated circuit layout design based on the at least one performance characteristic, wherein at least one step of said method is executed by a processor.