1. An apparatus implementing an Advanced Encryption Standard (AES) S-box encryption process on a 128-bit block including 16 byte values, the apparatus comprising: a first field conversion circuit to convert each of the 16 byte values, respectively, from a first corresponding polynomial representation in GF(256) to a second corresponding polynomial representation in GF((2 2 ) 4 ); a multiplicative inverse circuit to compute for each of the second corresponding polynomial representations in GF((2 2 ) 4 ) of the 16 byte values, respectively, a corresponding multiplicative inverse polynomial representation in GF((2 2 ) 4 ); and a second field conversion circuit to convert each corresponding multiplicative inverse polynomial representation in GF((2 2 ) 4 ) and to apply an affine transformation to generate, respectively, a third corresponding polynomial representation in GF(256), wherein the conversion, in the second field conversion circuit, of each corresponding multiplicative inverse polynomial representation in GF((2 2 ) 4 ) and application of the affine transformation is performed by multiplication of each byte value with an 8-bit by 8-bit matrix and XORs with a set of constants according to: b 0 =a 0 ⊕a 1 ⊕a 2 , b 1 =a 0 ⊕a 3 ⊕a 5 , b 2 =a 0 ⊕a 2 ⊕a 6 , b 3 =a 0 ⊕a 1 ⊕a 3 ⊕a 4 ⊕a 5 , b 4 =a 0 ⊕a 1 ⊕a 4 ⊕a 5 ⊕a 7 , b 5 =a 4 , b 6 =a 3 ⊕a 6 , b 7 =a 2 ⊕a 3 , where [a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ] is the multiplicative inverse polynomial representation in GF((2 2 ) 4 ) and [b 7 , b 6 , b 5 , b 4 , b 3 , b 2 , b 1 , b 0 ] is the third corresponding polynomial representation in GF(256).