1. An apparatus comprising: a processor configured to provide memory commands for memory access operations; and a memory controller coupled to the processor; and a memory comprising: a plurality of memory elements; and control logic coupled to the memory controller via a control channel, the control logic configured to decode control information and to selectively provide the control information to at least one of the plurality of memory elements, wherein the control logic is further configured to select an internal control channel of a plurality of internal control channels based on the selectively provided control information regarding the internal control channel, the selected internal control channel coupling the control logic and a selected memory element of the plurality of memory elements.