1. A circuit comprising: a memory comprising: a first bitcell array having a first density and a first access speed; a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed; a first set of wordline drivers coupled to the first bitcell array; a second set of wordline drivers coupled to the second bitcell array; and a row decoder coupled to both the first and second bitcell arrays.