1. A central processor comprising: A) a first execution unit for performing data manipulation operations, said first execution unit having an input for receiving information to be processed and an output for issuing a first execution unit result; B) a second execution unit for performing data manipulation operations, said second execution unit having an input for receiving information to be processed and an output for issuing a second execution unit result; C) a single accumulator register having an input and an output; D) means selectively coupling said single accumulator register output to said first execution unit input and to said second execution unit input; E) means selectively coupling said first execution unit output and said second execution unit output to said single accumulator register input; F) a single supplementary accumulator register; G) means selectively coupling said single supplementary accumulator register output to said first execution unit input and to said second execution unit input; H) means selectively coupling said first execution output and said second execution output to said single supplementary accumulator register input; I) a multi-level register stack having an input and an output, said register stack being configured two-words-wide; J) a multi-level register stack input multiplexer switch; and K) a multi-level register stack output multiplexer switch; and in which: L) said accumulator register and said supplementary accumulator register are incorporated into said multi-level register stack at the same level; M) said multi-level register stack input multiplexer switch incorporates: 1) said means selectively coupling said first execution output and said second execution output to said single accumulator register input; and 2) said means selectively coupling said first execution output and said second execution output to said single supplemental accumulator register input; and N) said multi-level register stack output multiplexer switch incorporates: 1) said means selectively coupling said single accumulator register output to said first execution unit input and said second execution unit input; and 2) said means selectively coupling said single supplementary accumulator register output to said first execution unit input and said second execution unit input.