1. A processor comprising: a queue comprising a set of locations for storing addresses associated with vectorized memory access instructions; execution logic to execute a first vectorized memory access instruction to access the queue and to compare a new address associated with the first vectorized memory access instruction with existing addresses stored within a specified range of locations within the queue to detect whether a conflict exists, the existing addresses having been previously stored responsive to one or more prior vectorized memory access instructions and wherein if no conflict is detected, the new address is to be stored in a specified location in the queue, and wherein if a conflict is detected, results of the execution of the vectorized memory access instructions are to be rolled back to a specified point and scalar memory access instructions are to be executed.