1. A three-dimensional (3D) flip-flop, comprising: a master latch disposed in a first tier of a 3D integrated circuit (IC) (3DIC), the master latch configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output; at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output; and at least one monolithic intertier via (MIV) coupling the master latch output to an input of the at least one slave latch.