1. An apparatus, comprising: at least one multi-core processor; at least one shared cache shared by a plurality of processing cores, the shared cache comprising a plurality of cache lines and being partitioned into a plurality of sub-caches including at least one private sub-cache for each single processing core, and at least one public sub-cache shared by all of the processing cores; a plurality of monitoring circuits, each monitoring circuit configured to detect shared cache hit information for each respective processing core of the plurality of processing cores; and a partitioning logic circuit, configured to determine whether the cache line should be allocated to the public sub-cache or to a private sub-cache associated with one of the plurality of processing cores.