1. A memory system for use with a plurality of processors, the memory system comprising: a memory controller configured to receive memory requests from the plurality of processors over a first bus, the memory controller further configured to generate address signals based on respective memory requests; a system memory coupled to the memory controller over a second bus, the system memory comprising: a plurality of memory cells; and a cache system included within the system memory and configured to store data from a portion of the plurality of memory cells, wherein the system memory is configured to receive the address signals from the memory controller. and access the cache system if at least one of the address signals corresponds to the portion of the plurality of memory cells for the data stored in the cache system, and wherein the data from the portion of the plurality of memory cells stored in the cache system is written back to the plurality of memory cells when a refresh command is received to refresh that portion of the plurality of memory cells with corresponding data stored in the cache system without reading the data from the plurality of memory cells within the system memory to perform the refresh.