1. A computer system for suppressing branch prediction for suppressing branch prediction for branch instructions executing in a transaction of a transactional memory (TM) environment, the computer system comprising: a memory; and a processor in communications with the memory, the processor comprising branch prediction facilities, wherein the computer system is configured to perform a method, said method comprising: fetching, for execution, by a processor, a branch instruction in a transaction execution mode; obtaining branch prediction information corresponding to the branch instruction from a branch prediction facility, the branch prediction information comprising a transaction indicator, the transaction indicator indicating whether the branch instruction was previously encountered (=PE) in a transaction; and based on the transaction indicator indicating the branch instruction was previously encountered (=PE) in a transaction, determining whether to suppress use of corresponding branch prediction information for predicting the branch instruction; and based on the transaction indicator indicating the transactional instruction was not-previously encountered (not=PE) in a transaction, using corresponding branch prediction information for predicting the branch instruction; and based on the transaction indicator indicating the branch instruction was not-previously encountered (not=PE) in a transaction, setting the transaction indicator to indicate the branch instruction was encountered in a transaction.