1. A method for executing cache memory access requests for data on a computing device, comprising: altering, by a processor, an address for writing data smaller than a cache line to align the data with an end of a cache line; determining, by the processor, padding data to combine with the data smaller than a cache line based on power required for writing the padding data to a cache memory; combining, by the processor, the data smaller than a cache line and the padding data into combined data configured to fill a cache line; and sending, by the processor to a cache memory controller, a write cache memory access request for the combined data.