1. An integrated circuit design tool comprising: a library of standard cells including at least one transistor and polysilicon dummy structures formed on cell edges; and a processor configured to: form a pre-layout netlist schematic from an input gate level netlist using the standard cells, wherein the pre-layout netlist schematic does not include the polysilicon dummy structures; perform, using the gate level netlist, an automated place and route process to form a layout netlist for fabricating an integrated circuit using the standard cells; lay out, using the layout netlist, the standard cells and lay out routing connections between the standard cells to form a layout for the integrated circuit; extract from the layout for the integrated circuit a post-layout netlist schematic, the post-layout netlist schematic including a MOS device for each polysilicon dummy structure of a standard cell in the layout netlist; and compare the pre-layout netlist schematic to the post-layout netlist schematic while using a filter to block the MOS devices corresponding to the polysilicon dummy structures from the post-layout netlist schematic.