1. A microprocessor coupled to a system memory, the microprocessor comprising: a memory subsystem, having a translation look-aside buffer (TLB) for storing TLB information; an instruction decode unit, coupled to said memory subsystem, for decoding an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy; and a stream prefetch unit, coupled to said memory subsystem, for generating a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem selectively aborts said prefetch request based on said abnormal TLB access policy specified in said instruction.