1. A memory device comprising: a sequencer configured to receive a condition instruction, selectively generate a first signal, and selectively generate a second signal having a value indicating whether a condition of the condition instruction has been met; and an internal processor coupled to the sequencer, wherein the internal processor comprises a plurality of arithmetic logic unit (ALU) blocks configured to operate in parallel, each ALU block being configured to selectively execute operations based on an output of a conditional masking logic of the internal processor, wherein the sequencer controls the output of the conditional masking logic via the selectively generated first signal and second signal, wherein each ALU block of the plurality of ALU blocks comprises a counter to count a number of first conditional instructions and then a number of second conditional instructions; wherein the memory device is a processor-in-memory or a multi-chip package device.