1. A computer-implemented method for generating a physical layout output file for fabricating a superconducting circuit, the method comprising: receiving a netlist file defining terminal input/output (I/O) connections between superconducting components; determining a respective gate tile type for each gate in the netlist, wherein the gate tile type includes a gate type associated with each gate type in the netlist and a plurality of associated unassigned Josephson junctions; determining position placement of each gate tile and its associated Josephson junctions in a circuit layout; assigning unassigned Josephson junctions to Josephson junctions defined in active interconnect circuits of the netlist that provide terminal I/O connections between superconducting components; determining wire routes to couple the assigned Josephson junctions to one another and provide the wired inductors to form the active interconnect circuits that couple the terminal I/O connections between the superconducting components; and generating a physical layout output file with the determined position placement of each gate tile, and the determined wire routes.