1. An apparatus for verifying a property associated with a target circuit, comprising: a partitioned ordered binary decision diagram (POBDD) data structure operable to receive information associated with a target circuit, the information identifying a property within the target circuit to be verified, the POBDD data structure operable to execute one or more operations in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit, the POBDD data structure operable to partition an image associated with the target circuit into a plurality of leaves that may each represent a subset of a final image to be generated by the POBDD data structure, wherein the POBDD data structure is operable to compute an analysis for one or more of the leaves using a selected one or both of conjunction and quantification operations separately.