1. A binary number substitution mechanism comprising: first and second storage arrays comprised of 2.sup.n n-bit storage locations and 2.sup.p p-bit storage locations respectively, said first and second storage arrays each including access means for simultaneously addressing one of the 2.sup.n storage locations of said first storage array and one of the 2.sup.p storage locations of said second storage array, and a total of n+p read-out signal lines for data stored in the storage locations of said first and second storage arrays; m input binary signal lines, said m input binary signal lines including an n-bit portion and a p-bit portion, the binary state of said m input binary signal lines being effective to represent 2.sup.m binary numbers; gate means, selectively and simultaneously interconnecting said n-bit portion of said m input binary signal lines to said access means of said first storage array and said p-bit portion of said input binary signal lines to said access means of said second storage array; and enabling means having an output signal connected to said gate means, and connected to said m input binary signal lines and responsive to certain ones of said binary number representations of said m input binary signal lines, for enabling said gate means whereby a substitute binary number manifestation is read out of said first and second storage arrays on said n+p read-out signal lines.