1. An aggregated memory management unit (MMU), comprising: a plurality of input data ports each configured to convey pre-translation transactions to a plurality of input data paths configured to receive a plurality of memory address pre-translation read transactions and a plurality of memory address pre-translation write transactions, the plurality of input data paths comprising a corresponding plurality of input transaction buffers each comprising a plurality of input transaction buffer slots configured to store a respective pre-translation transaction among the plurality of pre-translation transactions; and a plurality of output data paths comprising a corresponding plurality of output transaction buffers each comprising a plurality of output transaction buffer slots configured to store a respective post-translation transaction of a plurality of post-translation transactions; an MMU management circuit configured to: retrieve a memory address translation request (MATR) of a pre-translation transaction from an input transaction buffer of the plurality of input transaction buffers; perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF); and provide the TMAF and a pre-translation transaction payload as a post-translation transaction to an output transaction buffer of the plurality of output transaction buffers; and each output data path of the plurality of output data paths configured to output the post-translation transaction through a corresponding plurality of output data ports.