1. A field programmable gate array (“FPGA”) having integrated structured application specific integrated circuit fabric (“ASIC”) comprising: FPGA fabric that includes a plurality of log ic elements (“LEs”) programmably interconnected into a plurality of logic array blocks (“LABs”); and structured ASIC fabric incorporated into the FPGA fabric, wherein the structured ASIC fabric comprises an interface region and a custom region: the custom region operable to implement a structured ASIC design using a plurality of hybrid LEs connected together using at least one custom metal layer and at least one custom via layer, the interface region operable to programmably connect the plurality of LABs from the FPGA fabric and the structured ASIC design from the custom region, and wherein at least a portion of the at least one custom metal layer of the custom region is allocated for routing signals from the FPGA fabric across the structured ASIC fabric.