1. A hierarchical memory device, comprising: a Phase Change Memory (PCM) array; multiple interfaces having different memory formats, the multiple interfaces including a NAND interface and a mass storage device interface; at least one processor core to perform multi-core NAND management and autonomous computing functions, the NAND management functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND interface based on extracted control and operational information including received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands; and at least one input port and a plurality of output ports such that the hierarchical memory device is simultaneously connectable in both a daisy-chain hierarchy and a hierarchical tree structure with other hierarchical memory devices and to switch traffic between the at least one input port and one of the plurality of output ports to reduce round-trip latency to a lowest layer of the hierarchical tree structure, the plurality of output ports configured to communicatively couple to at least one NAND memory external to the hierarchical memory device, the NAND interface configured to control communications between the PCM array and the at least one NAND memory such that the PCM array can cache data received from the at least one NAND memory, the at least one input port and the plurality of output ports being configurable by the at least one processor core.