1. A method of optimizing a plurality of threads to be executed by a processor, the method comprising: identifying an instruction of a first thread as a high latency floating point instruction; determining if a pipeline stall is likely from the identified high latency floating point instruction; and in response to a determination that the pipeline stall is likely from the identified high latency floating point instruction, adding at least one thread switching instruction to the first thread, wherein the thread switching instruction is adapted to switch from the execution of the first thread to a second thread.