1. A superscalar processor adapted to execute at least one instruction out of program order, said superscalar processor comprising: an instruction window that has a first storage location and a second storage location for storing instructions, an instruction stored in the second storage location being stored in the first storage location when an instruction stored in the first storage location is retired; a plurality of functional units that execute an instruction out of program order; a buffer that has storage locations at which an execution result of each instruction is stored; register renaming circuitry that associates uniquely an address indicating a fixed storage location in the buffer with each instruction included at each storage location in the instruction window, regardless of a change in the storage location of the instruction in the instruction window; a register array that includes a plurality of array locations referenced so that an execution result of a retired instruction can be provided to the referenced array location; a retirement control block that determines whether an executed instruction can be retired or not; and an instruction retirement unit that retires an instruction that can be retired by associating an execution result of each instruction that can be retired with an array location within the register array.