1. An apparatus, comprising: a processor; and a non-transitory computer-readable storage medium having instructions stored thereupon which are executable by the processor and which, when executed, cause the processor to: receive data defining a software release pipeline, the software release pipeline comprising: one or more stages, the one or more stages each comprising one or more actions; one or more stage gates or action gates; determine whether a stage gate or an action gate of the one or more stage gates or action gates is encountered during execution of the software release pipeline; in response to encountering the stage gate during execution of the software release pipeline: determine whether a stage gate bypass is specified for the stage gate; based at least in part on a determination that a stage gate bypass is not specified for the stage gate, evaluate the stage gate; based at least in part on a determination that the stage gate bypass is specified for the stage get, bypass the stage gate; and start execution of a next stage in the software release pipeline based, at least in part, upon the evaluation of the stage gate or a determination that the stage gate bypass is specified for the stage gate; and in response to encountering the action gate during execution of the software release pipeline: determine whether an action gate bypass is specified for the action gate; based at least in part on a determination that an action gate bypass is not specified for the action gate, evaluate the action gate; based at least in part on a determination that the action Gate bypass is specified for the stage get, bypass the action gate; and start execution of a next action in the software release pipeline based, at least in part, upon the evaluation of the action gate or a determination that the action gate bypass is specified for the stage gate.