1. A computer apparatus comprising: a processor; a memory connected to the processor; and computer executable program code configured to execute on the processor, wherein the computer executable program code is configured to: detect voltages in a multi-level memory cell wherein the multi-level memory cell is configured to store at least two bits of a low-density parity-check codeword; determine that a first bit of the at least two bits correctly decoded; receive bit page data corresponding to the first bit; and erase a log-likelihood ratio associated with a second bit in the at least two bits.