1. A method of operation of a multi-slice processor, the multi-slice processor including a plurality of execution slices and a plurality of load/store slices, each load/store slice comprising a load miss queue and a load reorder queue, the method comprising: receiving, at the load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction; determining that the cache line is available; and in a first cycle: propagating data for the previous load instruction to a results bus without accessing the data cache for the cache line; and storing the cache line in the data cache; and in a cycle after the first cycle: propagating the data for the load instruction to a results bus, wherein the data is retrieved from the data cache.