1. An integrated circuit device comprising: a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region; wherein the memory cell includes: (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor; (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; and (iii) a third data state which is representative of a third charge in the body region of the electrically floating body transistor; and data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein, (ii) second write control signals to the memory cell to write the second data state therein, and (iii) third write control signals to the memory cell to write the third data state therein; and wherein, in response to: the first write control signals applied to the memory cell, the electrically floating body transistor thereof generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor, and the second write control signals applied to the memory cell, the electrically floating body transistor thereof generates a second bipolar transistor current which substantially provides the second charge in the body region of the electrically floating body transistor.