1. A hardware component graph (HCG) to hardware description language (HDL) translation method, the HCG including at least one start node and multiple component nodes, the method comprising the steps of: (A) reading a hardware component graph, wherein the hardware component graph has multiple hardware component subgraphs; (B) finding a start node of the hardware component graph to thereby obtain a corresponding hardware component subgraph; (C) analyzing all information of the start node to thereby add input and output components and generate a VHDL entity, and repeating the analyzing until all start nodes are complete; (D) determining types on all nodes of the hardware component graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture; (E) generating corresponding signal connections of VHDL components in accordance with all edges of the hardware component graph; and (F) outputting the VHDL entity and architecture to a file in a text form.