1. A NAND memory array comprising: a select line coupled to each of a plurality of NAND strings of memory cells of the memory array, wherein the select line comprises a select gate at each intersection of one of the plurality of NAND strings and the select line; wherein the select line further comprises: first and second conductive layers separated by a dielectric layer; and a contact that extends from a third conductive layer, disposed on the second conductive layer, to the first conductive layer, the contact formed in a hole that passes through the second conductive layer and the dielectric layer and that terminates at the first conductive layer, the contact electrically connecting the first and second conductive layers.