1. A design supporting method, comprising causing a computer processor to execute the operations of: partitioning a source path of circuit information into partitioned paths based on a given condition; calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path; calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path; and calculating a source propagation delay time of the source path by merging the partition propagation delay time of each of the partitioned paths.