1. An apparatus comprising: one or more error-correction decoders; a buffer configured to store data to be decoded by the one or more error-correction decoders; at least one direct memory access (DMA) engine coupling said buffer and said one or more error-correction decoders; and at least one processor enabled to send messages to said at least one DMA engine, wherein said messages are configured to deliver DMA control information and corresponding datapath control information, data is read from said buffer based upon said DMA control information and delivered to said one or more error-correction decoders along with said corresponding datapath control information, and said one or more error-correction decoders are enabled to decode the data read from said buffer according to said corresponding datapath control information.