1. A flash memory cell array, comprising: a substrate having an active area, a plurality of vertically stacked pairs of floating gates and control gates arranged in rows above the active area, with the control gates being positioned above and aligned with the floating gates, select and erase gates aligned with and positioned on opposite sides of each of the stacked gates, a bit line above each row, bit line diffusions in the active area between and partially overlapped by two select gates, a bit line contact interconnecting the bit line and the bit line diffusions in each row, and a common source region in the active area beneath the erase gate and partially overlapped by the floating gates.