1. A method of verifying an operation of a mask programmed integrated circuit (MPIC) implementation of a programmable logic device (PLD) implementation of a circuit design using a computer system, said method comprising: generating a PLD simulation model of said circuit design as implemented in a PLD; back annotating said PLD simulation model using timing information corresponding to said MPIC implementation to generate an MPIC simulation model; and verifying said operation by simulating said MPIC simulation model.