1. A data processing device, comprising: a central processing unit having an instruction execution pipeline, said pipeline operable to process and execute a first branch instruction having a first target address in a first predetermined number of pipeline phases; program counter circuitry operable to receive said first target address during a last phase of said predetermined number of pipeline phases to form a first fetch address; fetch circuitry operable to fetch an instruction fetch packet from said first fetch address specified by said program counter circuitry, said instruction fetch packet having at least one instruction for processing by said instruction execution pipeline; control circuitry for said instruction execution pipeline operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of said first branch instruction having said first target address, wherein said control circuitry has no interlock or delay circuitry to condition processing of said second branch instruction based on processing of said first branch instruction; and wherein said program counter circuitry is operable to receive said second target address to form a second fetch address on a pipeline phase immediately after receiving said first target address irrespective of said first fetch address.