1. An interleaver, comprising: multiple processors configured to generate read-addresses in parallel for respective bits of multiple write-words; multiple address queues configured to queue the read-addresses received from the respective processors, each of the address queues outputting a status thereof; a first arbiter configured to select a non-empty address queue among the multiple address queues based on the status of each address queue, the first arbiter being outputting an address from the selected address queue while outputting an address queue ID of the selected address queue; a decoder configured to decode the outputted address from the selected address queue into a word-address and a bit-address; an input storage configured to store data to be interleaved, the input storage outputting a read-word based on the word-address; a first selector configured to select a write-bit from the read-word based on the bit-address; a write controller configured to arbitrate an individual write-bit to one of the write-words based on the address queue ID, the write controller generating write-addresses for respective write-words; and an output storage configured to store the write-word based on the write-address.