1. A system comprising: a flat panel display device; a touch screen cursor control device to control cursor movement on the flat panel display device; a device to capture video images; and a general-purpose central processing unit (CPU) having a reduced instruction set computing (RISC) architecture coupled with the flat panel display device, the touch screen cursor control device, and the device to capture video images, the general-purpose CPU comprising: a plurality of registers to store 64-bit packed data operands; a cache; a decoder coupled with the cache to decode a multiply and add instruction, the multiply and add instruction to have a 32-bit instruction format, the multiply and add instruction to have a first field to indicate a first register of the plurality of registers that is to store a first 64-bit packed data operand that is to have a first four signed 16-bit integer data elements A 1 , A 2 , A 3 , and A 4 , and the multiply and add instruction to have a second field to indicate a second register of the plurality of registers that is to store a second 64-bit packed data operand that is to have a second four signed 16-bit integer data elements B 1 , B 2 , B 3 , and B 4 ; and an execution unit coupled with the decoder and the plurality of registers, the execution unit operable, in response to the multiply and add instruction, to store a 64-bit destination operand in a third register of the plurality of registers that is to be indicated by a third field of the multiply and add instruction, the 64-bit destination operand to include two 32-bit integer data elements, a first data element of the destination operand to include A 1 *B 1 +A 2 *B 2 , and a second data element of the destination operand to include A 3 *B 3 +A 4 *B 4 .