1. A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising: receiving instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, wherein a given predicate value indicates elements in at least the portion of the vector that can be processed in parallel; and executing the instructions for detecting the conflict between the memory addresses and generating the one or more predicate values.