1. A system for generating a circuit description for a multi-die field-programmable gate array (FPGA) comprising a first FPGA die and at least one further FPGA die, the system comprising: a processor; and a memory storing instructions executable by the processor, the instructions when executed cause the processor to: evaluate, automatically, a first partition and a second partition of a partitioned circuit description, the first partition being associated with the first FPGA die and the second partition being associated with the at least one further FPGA die; insert at least one multiplexing element into the first partition and a corresponding de-multiplexing element into the second partition based on the automated evaluation; and perform one of: execute, in response to direct physical connections between the first partition and the second partition with the first FPGA die and second FPGA die located adjacent within the multi-die FPGA, direct signal transmission between the first partition and the second partition; and execute, in response to indirect inter-die connections between the first partition and the second partition with at least a third FPGA die inserted between the first FPGA die and the second FPGA die, insertion of at least one intermediate register in the third FPGA die, the third FPGA die being associated with a third partition of the partitioned circuit description.