1. A fault tolerant computer comprising: a processor to execute instructions, said processor including instructions to execute an original and mirror instructions to produce results to be compared in a redundancy routine, a radiation hardened comparison circuit coupled to compare an original result and a first mirror result, said comparison circuit providing an output of a first state when said original result agrees with said mirror result and an output of a second state when said original result and said mirror result disagree, said second state comprising an SEU error signal.