1. A method of compiling a circuit design for hardware-accelerated functional verification, comprising: receiving a description of the circuit design which includes a plurality of nodes interconnected to form a plurality of nets having at least one associated uniform operator logic tree by executing first instructions in a computer system; removing selected components from nodes of the uniform operator logic tree while retaining node information to create a dissolved circuit description for the circuit design by executing second instructions in the computer system; partitioning the circuit design into multiple partitions which map logical primitives of the dissolved circuit description to resources of a hardware accelerator by executing third instructions in the computer system; constructing uniform operator logic sub-trees for the partitions using the node information by executing fourth instructions in the computer system; and aggregating the uniform operator logic sub-trees into a master uniform operator logic tree for the circuit design by executing fifth instructions in the computer system.