1. A charge domain bit-serial multiplying digital-analog converter including a plurality of pipelined processing stages, each of said processing stages comprising: an analog input for receiving an analog input signal; a digital input for receiving a digital input signal; a dividing circuit operable for receiving said analog signal and dividing it into first and second equal portions; a first output unit which receives a magnitude product of said first equal portion of said analog input signal and said digital input signal in response to said digital signal having a first digital value; and a second output unit which receives said first equal portion in response to said digital signal having a second digital value or said second equal portion in response to said digital signal having said first digital value.