1. A microprocessor comprising: a secure memory configured to store and provide cryptographic keys for use in decrypting encrypted instructions; and an instruction-processing pipeline configured to fetch instructions from a cache and execute them, the pipeline comprising: a fetch unit configured to fetch both unencrypted and encrypted instructions of an instruction set architecture (ISA) supported by the microprocessor; a decryption circuit configured to decrypt encrypted instructions using cryptographic keys received from the secure memory; and one or more execution units configured to execute instructions or microinstructions translated from instructions; wherein the ISA includes a store-key instruction to store one or more cryptographic keys into the secure memory, and wherein the microprocessor supports store-key instructions that are encrypted; wherein when presented with an encrypted store-key instruction, the microprocessor is configured to use a first set of one or more cryptographic keys to decrypt the encrypted store-key instruction, and thereafter execute the decrypted store-key instruction, and thereafter use a second set of one or more cryptographic keys provided by the encrypted store-key instruction to decrypt a subsequent set of one or more encrypted instructions; the microprocessor enabling an encrypted program to change the sets of cryptographic keys used to decrypt successive sets of the program's instructions; wherein the ISA includes a secure execution mode (SEM) instruction to request a switch from a normal execution mode into the SEM, and wherein the microprocessor is configured to prevent decryption of an encrypted program unless the microprocessor is in the SEM.