1. A system comprising: trace rule file containing trace rules describing a sub-circuit of a larger circuit design; a sub-circuit netlist generation processor configured to generate a sub-circuit netlist, a portion of which is based on a hardware descriptive language (HDL) netlist of the larger circuit design, a parasitic capacitance database and the trace rules, wherein the trace rules instruct the sub-circuit netlist generation processor how to build the sub-circuit netlist so that the sub-circuit netlist contains only sub-circuits of special intrest rather than create an analog netlist that includes the entire larger circuit design, whereby the sub-circuit netlist contains fewer circuit paths than the HDL netlist of the larger circuit design; an analog simulation processor configured to generate analog simulation results of the sub-circuit netlist based on dynamic inputs; and a gate level functional simulation processor configured to generate static stimulus of the HDL netlist, wherein the analog simulation processor is configured to generate the analog simulation results based, at least in part, on the static stimulus.