1. An apparatus comprising: a processor; an execution logic to enable, in a transactional memory system, concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode, the first hardware transaction mode different than the second hardware transaction mode; a tracking logic to activate a flag to indicate that at least one software transaction is undergoing execution in the first software transaction mode or the second software transaction mode; an intersection logic to determine, when the flag is activated and a first lock is taken by the at least one software transaction, whether, at a conclusion of a first hardware transaction of the second hardware transaction mode, a filter set of the first hardware transaction of the second hardware transaction mode conflicts with a filter set of the at least one software transaction undergoing execution; and a finalization logic to commit the first hardware transaction if there is no conflict, and to abort the first hardware transaction if there is a conflict.