1. A method performed by a computer system for optimizing a design point for an integrated circuit design, the method comprising: receiving an integrated circuit design, the integrated circuit design comprising at least two memory instances, the memory instances defined by calls to a generic memory model of the memory instances, each call for a memory instance using (a) a generic memory call interface for the generic memory model, the generic memory call interface including a set of memory parameters, and (b) memory parameters for the memory instance; estimating a trial PPA (power, performance, area) metric for the integrated circuit design evaluated at a trial design point within a design space; iteratively optimizing the trial design point based on the trial PPA metric, wherein iteratively optimizing the trial design point comprises iteratively optimizing the memory parameters for the memory instances; and synthesizing specific memory models for each memory instance from the generic memory model using the optimized memory parameters for the memory instances, wherein the specific memory models are used in a flow for designing and fabricating the integrated circuit.