1. A timing signal generator for use in a processor for digitally processing a picture block constituting a part of a picture frame, comprising: column counter means reset in synchronization with a horizontal sync signal and advanced to produce a column count in synchronization with a sampling signal; column comparator means for comparing a transition point column number, indicating a transition point in the column direction, and the column count, and outputting a column identity signal if said transition point column number and said column count are found identical; column address counter means advanced by said column identity signal to produce a column address and reset by said horizontal sync signal; column memory means responsive to said column address for outputting said transition point column number; row counter means reset in synchronization with a vertical sync signal and advanced to produce a row count in synchronization with said horizontal sync signal; row comparator means for comparing a transition point row number, indicating a transition point in the row direction, and the row count, and outputting a row identity signal if said transition point row number and said row count are found identical; row address counter means advanced to produce a row address by said row identity signal and reset by said vertical sync signal; row memory means responsive to the row address for outputting said transition point row number; and signal generator means responsive to said column identity signal and row identity signal for generating signals to instruct the inputting, outputting and processing of said picture block to, from and by said processor respectively.