1. A method for managing memory in a computer comprising, for each of at least one input set of memory addresses, and iteratively for each of the memory addresses in the at least one input set: a) loading a current memory address, belonging to the at least one input set, into a processor cache; b) detecting whether an eviction occurs from the cache as a result of the loading of current memory address into the processor cache; c) if an eviction is detected: i) adding the current memory address to a conflict set of memory addresses; ii) flushing the cache; and iii) loading the conflict set into the cache; d) if no eviction is detected, determining whether all of the input set of memory addresses has been loaded into the cache and, if not, loading a next one of the input set of memory addresses into a processor cache; whereby the input set of memory addresses is determined to be partitioned into a plurality of partitions such that memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict in the cache.