1. A system comprising: a processor element having a fixed instruction set, and a reconfigurable co-processor, wherein said co-processor comprises at least one attribute selected from the following: at least one reconfigurable fixed instruction set; sharing a common virtual and physical address space with said processor element; and a global shared, cache coherent physical address space, whereby the processor element comprises a physical memory and a cache, and whereby the co-processor comprises a physical memory and a cache, and wherein data contained in the processor element's cache and the co-processor's cache are maintained in a cache coherent state.