1. A method comprising: identifying a first pointer and a second pointer included in a high level program language loop; determining an iteration count, wherein the iteration count is a number of loop iterations after which a collision occurs between the first pointer and the second pointer; determining a memory latency for accessing a memory associated with the programmable chip; using the memory latency and the iteration count to determine a number of clock cycles required to perform the high-level language program loop; and generating a hardware accelerator for implementation on the programmable chip, the hardware accelerator operable to determine the number of clock cycles required to perform the high-level language program loop.