1. A processor to facilitate decoding of arbitrary length blocks of low-density, parity-check codes, the processor comprising: a plurality of interconnected nodes; and a memory interconnected with the plurality of interconnected nodes, the memory adapted to store intermediate log likelihood ratio (LLR) values based on channel LLR values representing the low-density, parity-check codes to enable outputting LLR values having improved accuracy relative to the channel LLR values; wherein the memory is adapted to store the intermediate LLR values in a circular buffer where a pointer tracks a current position in the circular buffer.