1. A memory cache apparatus for use with a processor, comprising: a first hardware based memory cache portion in communication with said processor, said first memory cache portion managed by a software process; a second hardware based memory cache portion in communication with said processor, said second memory cache portion managed by a hardware circuit; said second hardware based memory cache portion is operative to fetch a rule from main memory coupled thereto if a rule is not found in first hardware based memory cache portion and second hardware based memory cache portion; wherein said second memory cache portion comprises temporary instructions to be executed by said processor; and wherein said software process is operative to place frequently accessed instructions in said first memory cache portion.