1. An apparatus for parallelization of a computer program on a plurality of computing cores, the apparatus comprising: one or more processors; and one or more memories operatively coupled to at least one of the one or more processors and having instructions stored thereon that, when executed by at least one of the one or more processors, cause at least one of the one or more processors to: receive a computer program comprising a plurality of commands; decompose the plurality of commands into a plurality of node networks, wherein each node network corresponds to a command in the plurality of commands and includes one or more nodes corresponding to execution dependencies of the command; map the plurality of node networks to a plurality of systolic arrays, wherein each systolic array comprises a plurality of cells and wherein nodes in each node network are mapped to a cell in the plurality of cells; and map each cell in each systolic array to a computing core in the plurality of computing cores.