1. A cache coherency system in a message passing multiprocessor architecture, the system comprising: a plurality of nodes interconnected by a switch wherein each node includes at least one processor, a cache, a main memory and a system interface, wherein a portion of the main memory of each of the plurality of nodes forms a distributed shared memory; and a messaging module configured to convert memory transactions regarding the distributed shared memory into messages, and to convert messages regarding the distributed shared memory into memory transactions.