1. A pipelined processor for performing imperative control flow instructions of multiple threads of computation comprising: token storage wherein tokens are stored, each token identifying a next instruction to be processed in a thread of computation; and at least one processing pipeline which successively receives tokens from token storage for processing of the next instruction identified therein, the processing pipeline processing a forking instruction identified by a token to generate two tokens, the tokens identifying respective instructions of different threads that are subsequently applied to the at least one processor pipeline and processed independently.