1. A hardware functional verification system, comprising: a plurality of interconnected emulation chips to be programmed with a circuit design, an emulation chip comprising: a plurality of emulation processors that generate a plurality of data bits during an emulation step of the emulation chip, wherein one or more data bits of the plurality of data bits are indicated as trace data bits by one or more enable bits; a trace data register to temporarily store trace data bits in a plurality of bit positions; and a trace compaction circuit connected to an output of the plurality of emulation processors and the trace data register to compact the one or more trace data bits received from the plurality of emulation processors into adjacent bit positions of the trace data register according to the one or more enable bits.