1. A dynamic multistreaming processor, comprising: a plurality of instruction queues, each instruction queue corresponding to an instruction stream; a fetch stage configured to fetch at least one instruction from an instruction source and store the fetched instructions in a selected one of the plurality of instruction queues; a plurality of execution units; a dispatch stage configured to select at least one instruction from one of the plurality of instruction queues and to dispatch the selected at least one instruction to one of the plurality of execution units; a queue counter, associated with each instruction queue, configured to indicate a number of instructions in each instruction queue and to indicate the capacity of each instruction queue to accept additional instructions from the fetch stage; and a fetch program counter, associated with each instruction queue, configured to indicate an address from which to obtain instructions when the associated instruction queue indicates capacity to accept additional instructions.