1. A circuit arrangement, comprising: a plurality of dynamically-combinable parallel execution slices configured, to execute instructions from one or more instruction streams, the plurality of execution slices configured to operate in a plurality of threading modes that includes at least first and second threading modes, the first and second threading modes respectively supporting first and second numbers of hardware threads; and dispatch logic coupled to the plurality of execution slices and configured to dispatch the instructions from the one or more instruction streams to the plurality of execution slices; wherein when the plurality of execution slices are operating in the first threading mode, the dispatch logic is configured to dispatch instructions to each of the plurality of execution slices for execution in the first number of hardware threads; and wherein when the plurality of execution slices are operating in the second threading mode, the dispatch logic is configured to dispatch instructions associated with any hardware thread among a first subset of the second number of hardware threads to a first subset of the plurality of execution slices and to dispatch instructions associated with any hardware thread among a second subset of the second number of hardware threads to a second subset of the plurality of execution slices.