1. A method for pipelining DMA Write operations in a data processing system having a memory and an Input/Output (I/O) processor, said method comprising: performing a first operation to place a cache line being requested by a DMA write instruction in a weak ownership state; delaying issuing of a second operation that writes said cache line to said memory until all other cache lines requested by previously issued first operations are also in said weak ownership state; and forwarding said cache line along with said other cache lines to said memory in any order, responsive to said cache line and said other cache lines all being in said weak ownership state.