1. A method for processing a branch mis-prediction and an instruction rejection in a digital processor, comprising: fetching a sequence of instructions including a branch instruction that calculates an address of an instruction to be executed if the branch is taken; predicting whether the branch will be taken and accordingly selecting an instruction path corresponding to the prediction; executing the branch instruction and determining a correct instruction path; detecting a condition where the correct instruction path was not selected, a second instruction that precedes the branch instruction in the sequence of instructions is rejected, and instructions subsequent to the branch instruction cannot be flushed; and if the condition is detected, preventing instructions from being received into an instruction buffer until the branch instruction is re-executed.