1. A processor comprising: a processor core; a serial debug port formed of a plurality of pins configured to send and receive signals to and from external debug equipment; a parallel debug port formed of a plurality of pins configured to send and receive signals to and from external debug equipment; a plurality of debug registers accessible to said serial port and said parallel debug port, and coupled to said processor core for receiving and providing debug data and control signals; an on-chip trace memory coupled to said processor core and said serial debug port, said trace memory for storing trace information indicative of program execution order in said processor core; wherein said processor core performs debug operations in response to signals from said external debug equipment sent over one of said parallel and serial debug ports.