1. A programmable integrated circuit logic array device, comprising: a plurality of input terminals for receiving input signals; a plurality of I/O terminals for receiving input signals and/or transmitting output signals; a first plurality of macrocells each including at least a first programmable AND array having a first plurality of memory cells arranged in addressable rows and columns, each said cell being individually programmable to contain logic data corresponding to the memory state of the cell, first sensing means connected to said first AND array, said first sensing means being responsive to certain ones of said input signals and operative to detect the memory state of one or more of said cells and to develop a corresponding first data signal, first signal storage means, first feedback means, and first multiplexing means for selectively coupling said first data signal to one of said I/O terminals, to said first storage means, or to said first feedback means; and a plurality of data buses including a global input signal bus for coupling input signals from said input terminals to a first group of cells in the AND arrays of each said macrocell, a local feedback bus for coupling signals applied to the feedback means of at least some of said macrocells to a second group of cells of at least some of said macrocells, and a global feedback bus for coupling data signals applied to some of said feedback means to a third group of cells of all of said AND arrays of said macrocells.