1. An arrangement for vector permutation in a single-instruction multiple-data microprocessor, the arrangement comprising: a permutation logic block coupled to receive and permutate vectors from at least one vector register according to control parameters; a plurality of control registers, each coupled to selectively provide control parameters to the permutation logic block; and, control means coupled between the plurality of control registers and the permutation logic block and arranged for selecting one of the plurality of control registers and for providing the control parameters from the selected one of the plurality of control registers to the permutation logic block.