1. Apparatus for processing a plurality of successive data packets, the apparatus comprising: at least one multi-threaded processor that is operable to perform processor tasks; a plurality of hardware blocks each of which is dedicated to perform a hardware event; and interface circuitry that is operable to control the transfer of packet information associated with each of the plurality of successive data packets between the at least one multi-threaded processor and the plurality of hardware blocks, the interface circuitry comprising: an input controller having: an input queue operable to store pointers associated with packet information waiting to be transferred to the at least one multi-threaded processor, and a task scheduler operable to identify idle threads in any of the at least one multi-threaded processor and load an instance of packet information into the idle thread based on the next pointer in the input queue; and an output controller having an output queue operable to store pointers associated with packet information waiting to be transferred to one of the plurality of hardware blocks.