1. A method of level sensitive testing a single sided delay dependent embedded array logic unit, said unit including combinational network circuit means having primary input terminals and primary output terminals, said combinational network circuit means including at least a first combinational network and a second combinational network, means including array circuit means interconnecting said first and second combinational networks and sequential circuit means interconnected with said combinational circuit means said sequential circuit means having access for scanning data into said sequential circuit means independent of said primary input terminals and primary output terminals, said method including the steps of: (a) scanning in a test pattern, via said scanning access into said sequential circuit means; (b) applying the same test pattern, via said primary input terminals, to the combinational network circuit means to provide a primary output at said primary output terminals; and (c) comparing said primary output with a known expected response for an indication as to the merit or lack of merit of the unit.