1. A comparison circuit for a memory management unit (MMU) comprising: a bit adder configured to provide a bitwise sum and a bitwise carry using a first operand portion, a second operand portion, and a comparison value; and a comparator configured to receive the bitwise sum and a bitwise inverse of the bitwise carry and configured to provide a match value, wherein the match value has a first logic value when a wordwise sum of the first operand portion and the second operand portion matches the comparison value, and a second logic value otherwise.