1. An apparatus, comprising: a first generator to generate a behavioral representation of a design for an integrated circuit including 1×N arrays of cells, wherein the behavioral representation comprises a register transfer level (RTL) description of one of the 1×N arrays of cells; a second generator to generate a logical representation of the design, wherein further the second generator is arranged to generate the logical representation via a flat netlist of a physical design representation, wherein further the flat netlist comprises a circuit element altered via at least one of a logic design tool, a synthesis tool, a physical design tool, and a timing analysis tool; and a third generator to generate the physical design representation of the design, wherein at least one of the behavioral, logical, and physical design representations is generated by detecting the alteration of the circuit element from a comparison of the flat netlist with a second netlist of the design before the alteration.