1. A Boolean processor for manipulating a plurality of Boolean variables stored in an associated I/O image memory by executing programs stored in an associated program memory, comprising: a node memory having a plurality of individually addressable locations; AT- register; a destination register; and means for interpreting instructions fetched from the associated program memory and directing corresponding operations including means, activated on the occurrence of at least one of a first class of instructions (structure instructions), for specifying selected first and second node memory locations in said node memory, storing the address of said second node memory location in said address destination register, performing a binary logical operation on the logical values stored in said first and second node memory locations, and storing the result of said binary logical operation in said second node memory location, and means, activated on the occurrence of a second class of instructions (input instructions), for specifying a selected location in the associated I/O image memory, reading an input variable from said selected location in the associated I/O image memory and performing a logical AND between said input variable and the content of said T-register.