1. A method of configuring a programmable integrated circuit device to perform a multiplication operation on a number of multiplicand input values each having a first plurality of bits, wherein: said programmable integrated circuit device incorporates multiplier circuits for multiplicand input values each having a second plurality of bits, said multiplier circuits are grouped into specialized processing blocks, each of said specialized processing blocks comprises only two of said multiplier circuits, and further comprises combinatorial circuitry for combining outputs of said two of said multiplier circuits, and said programmable integrated circuit device further comprises interconnection conductors for selectably connecting output of at least one multiplier circuit in a first one of said specialized processing blocks to said combinatorial circuitry in at least a second one of said specialized processing blocks; said method comprising: configuring logic of said programmable integrated circuit device to break up each of said multiplicand input values into a plurality of segments, each segment having said second plurality of bits, a first one of said segments of one of said multiplicand input values being of greater significance than a second one of said segments of said one of said multiplicand input values, said second one of said segments being of lesser significance; configuring logic of said programmable integrated circuit device for adding together, for each of said multiplicand input values, said segments of greater significance and lesser significance, to create a respective sum for each of said multiplicand values; configuring logic of said programmable integrated circuit device for multiplying together said segments of greater significance using a first one of said multiplier circuits, for multiplying together said segments of lesser significance using a second one of said multiplier circuits, and for multiplying together said sums using a third one of said multiplier circuits, said configuring logic of said programmable integrated circuit device for multiplying comprises configuring said interconnection conductors to connect output of at least one multiplier circuit in said first one of said specialized processing blocks to said combinatorial circuitry in said at least a second one of said specialized processing blocks; and configuring logic of said programmable integrated circuit device to shift outputs of said first and second ones of multiplier circuits by respective amounts and to combine outputs of said first, second and third ones of said multiplier circuits according to a recursive decomposition of said multiplication operation.