1. A system-on-a-chip device comprising: a plurality of parallel masters; a global shared memory switch (GSM) structurally related as a slave with respect to the plurality of parallel masters and in communication therewith, the GSM including on-chip shared memory resources to provide an interconnect mechanism among hardware components, processors and software entities, the GSM arranged to arbitrate among the plurality of parallel masters to allow the plurality of parallel masters to concurrently access the shared memory resources; the plurality of parallel masters including a processor complex subsystem and a memory interface controller, the processor complex subsystem including a high priority processor and one or more low priority processors; the memory interface controller, to manage memory access requests for a plurality of memory interfaces external to the processor complex subsystem; the system-on-a-chip device further including, a dedicated low latency physical path from the high priority processor to the memory interface controller to prioritize traffic from the high priority processor; and an arbitrated physical path from the low priority processors to the memory interface controller, the arbitrated physical path having a higher latency than the dedicated low latency physical path, wherein the GSM comprises, a system wide GSM with high port count to connect all subsystems together; and a smaller GSM with ports only connecting to the CPUs and the storage interface controller subsystem to provide context and/or queue storage for the storage controller.