1. An out-of-order computer processor for load latency speculation, the out-of-order computer processor comprising an instruction fetch logic, an instruction queue, and an instruction execution logic, wherein the out-of-order computer processor—is configured to carry out the steps of: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed upon the expiration of the expected execution latency; determining, upon the expiration of the expected execution latency, whether the load instruction has completed; and responsive to determining that the load instruction has not completed upon the expiration of the expected execution latency, issuing a negative dependent instruction wakeup signal on the instruction wakeup bus, wherein the negative dependent instruction wakeup signal indicates that the load instruction has not completed upon the expiration of the expected execution latency, and wherein the negative dependent instruction wakeup signal further indicates that data to be utilized by instructions dependent upon the load instruction will be unavailable at the expiration of the expected execution latency.