1. A non-volatile memory device, comprising: an array of non-volatile memory cells configured to support single bit and multi-bit programming states; and a control circuit configured to program a first page of non-volatile memory cells in said array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation that is separated in time from the first programming operation by at least one operation to erase the first page of non-volatile memory cells, where M and N are unequal integers greater than zero.