1. A resistive memory device, comprising: a substrate, having an active region, wherein a front end circuit is formed in the active region, and the front end circuit has a plurality of conductive channels arranged as an array; a plurality of bottom electrodes which are disposed in the active region, each of the bottom electrodes being disposed to correspond to each of the conductive channels; a patterned resistance switching material layer and a patterned top electrode layer which are sequentially stacked on the plurality of bottom electrodes, wherein a continuous air dielectric layer exists between the patterned resistance switching material layer and the plurality of bottom electrodes, wherein the patterned resistance switching material layer is a continuous layer; and a plurality of patterned interconnections, which are disposed on the patterned top electrode.