1. An apparatus for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction, the apparatus comprising: a counter that increments by one each time data is clocked from one register to the next; logic for comparing a value of the counter with a preselected register address on each count of the counter; and logic for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.