1. A processor, comprising: an execution unit; and a binary translator including circuitry to: receive an instruction, the instruction to be executed for control flow; identify a source address of the instruction; identify a target address of the instruction, the target address including an address to which execution would indirectly branch upon execution of the instruction; access one or more entries in a control structure, the one or more entries associated with at least one of the source address and the target address; and determine whether to route the instruction to the execution unit based upon the one or more entries in the control structure.