1. A system, comprising: a processor that supports data flow and timing to a dynamic random access memory (DRAM) buffer component; a controller that regulates read and write access to a FLASH memory device employed for random access memory applications; a free list component that evaluates the FLASH memory device and the DRAM buffer component and identifies free areas that are not in use by an application; and a wear leveling component that moves data from a heavily used area of the FLASH memory device to the free areas of the FLASH memory device or the DRAM buffer component.