1. Apparatus for prefetching instructions from a first cache to an instruction cache of a processor comprising: an instruction pointer multiplexer that generates one of a plurality of instruction pointers (IPs) in a first pipeline stage of the processor; an instruction streaming buffer (ISB) that stores instructions returned from the first cache before they are written into the instruction cache; an instruction translation look-aside buffer (ITLB) that produces a physical address from the one of the plurality of IPs; a way multiplexer coupled to the ISB, the way multiplexer having an output that provides an instruction from a set in the instruction cache responsive to a hit signal, a miss signal causing the ISB to be read in a third pipeline stage, with the instruction being bypassed to the way multiplexer from the ISB in response to an ISB hit; and compare logic that performs a comparison, in the first pipeline stage, between the physical address and tags of the set in the instruction cache, the set being associated with the one of the plurality of IPs.