1. A semiconductor memory, comprising: a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, and a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line; and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.