1. An integrated circuit comprising: an array, which is provided by a plurality of unit cells having a predetermined shape and arranged in a matrix manner, wherein each unit cell includes: a first input terminal, to which a first signal is supplied; a second input terminal, to which a second signal is supplied; first and second output terminals, which are disposed to face the first and second input terminals, respectively; a first logical block for supplying one of a signal relating to a logical operation result of the first signal and the second signal according to first setting information, the first signal or a reverse signal of the first signal, and the second signal or a reverse signal of the second signal to the first output terminal when receiving the first signal and the second signal; and a second logical block for supplying one of a signal relating to a logical operation result of the first signal and the second signal according to second setting information, the first signal or the reverse signal of the first signal, and the second signal or the reverse signal of the second signal to the second output terminal when receiving the first signal and the second signal.