1. An apparatus for generating signals designating the least recently used level for use in a cache memory having a plurality of levels, each level containing a plurality of addressable locations, and said cache memory including circuits for generating a page hit signal indicative of hit being detected indicating that the data requested has been located in said cache memory and a page level number coded for indicating the level in which said hit occurred, said apparatus comprising: a number of register stages including an input stage and an output stage, each of said stages for storing a different replacement level value and being connected in tandem and each stage having only a clocked single multibit register for storing said different replacement level value; input means coupled to said cache memory for receiving said page hit signal and said page level value for indicating said level in which said hit condition occurred, said input means being enabled during normal operation to transfer said page level value and said page hit signal as replacement level value and shift enable signal inputs respectively to said input stage multibit register; means for simultaneously applying a single clock signal to each of said stage registers; each of said register stages except said output stage further including: a comparison circuit having an output and first and second sets of inputs respectively coupled to receive said different replacement value stored in said each stage multibit register and to receive from said input means, said page level number value; and, logic gating means having first and second inputs and an output, said first and second inputs being connected to receive said shift enable signal and to said output of said comparison circuit respectively and said output being connected to both a first input of a logic gating means and an input to a stage multibit register of a next adjacent stage, said comparison circuit of each stage generating an output signal for indicating when there is the absence of an identical comparison between said page level value and said different replacement value stored in said each stage multibit register for enabling said logic gating means to transfer and apply said shift enable signal as said first input to said logic gating means and to said multibit register of said next adjacent stage; said input means being inhibited by said absence of said page hit signal from applying said shift enable signal to said input stage thereby preventing any change in the stored different replacement level value contents of said number of stage multibit registers in response to said clock signal; and said input and the remaining ones of said number of stages of multibit registers in response to said clock signal and said shift enable signal applied from said outputs of said logic gating means, loading said page level value into said multibit register of said input stage and simultaneously shifting the stored different replacement level contents through successive stages of said multibit registers up to and including the stage whose comparison circuit detected said identical comparison and inhibited said logic gating means from transferring and applying said shift enable signal to said multibit register and to said first input of said logic gating means of said next adjacent stage and any remaining stages, thereby providing at said output stage register within a minimum of time following the transfer of said hit signal, a replacement value which accurately represents said least recently used replacement level within said cache memory.