1. A method of graphics processing comprising: allocating, by a graphics processing unit (GPU), a first ring buffer as a first shared data channel in on-chip graphics memory of the GPU, wherein the first ring buffer is shared by a first two stages of a graphics processing pipeline to store first and second data produced by the respective first two stages of the graphics processing pipeline; allocating, by the GPU, a second ring buffer as a second shared data channel in the on-chip graphics memory of the GPU that is shared by a second two stages of the graphics processing pipeline to store third and fourth data produced by the respective second two stages of the graphics processing pipeline; executing, on shader units in the GPU, the first two stages of the graphics processing pipeline and the second two stages of the graphics processing pipeline, including consuming, by one of the first two stages of the graphics processing pipeline, the third data stored in the second ring buffer to produce the first data that is stored into the first ring buffer; reserving, by the GPU, free space in the first ring buffer for storing the second data produced by a second of the first two stages of the graphics processing pipeline and free space in the second ring buffer for storing the fourth data produced by one of the second two stages of the graphics processing pipeline to prevent deadlock between the first ring buffer and the second ring buffer; storing, by the GPU into the first ring buffer in on-chip graphics memory, the first and second data produced by first two stages of the graphics processing pipeline executing on the shader units as queues of the first and second data produced by the first two stages of the graphics processing pipeline; and reading, by the GPU from the first ring buffer in on-chip graphics memory, the second data produced by the second of the first two stages of the graphics processing pipeline, including deleting from the ring buffer the second data produced by the second of the first two stages of the graphics processing pipeline that is read from the first ring buffer, thereby increasing space in the first ring buffer for the GPU to store additional data produced by the one of the first two stages of the graphics processing pipeline.