1. A memory system comprising: a memory array, the memory array comprising a plurality of sections, each of the plurality of sections being individually configurable to operate in a more error resistant mode of operation and a less error resistant mode of operation; a memory controller, the memory controller determining whether data to be written to the memory array comprises modified information, the memory controller storing the modified information to a section operating in the more error resistant mode of operation; and, wherein the more error resistant mode of operation comprises providing a first voltage across at least one of the plurality of sections of the memory array and the less error resistant mode of operation comprises providing a second voltage across at least another of the plurality of sections of the memory array.