1. A system for multithreaded computing, comprising: one or more memory components configured to meet memory requirements of one or more multithreaded microprocessors; error-correction means responsive to the detection of a transient or soft error in a memory location of the one or more memory components, the transient or soft error being associated with one or more threads; and routing means associated with a multithreaded computing architecture that is operably connected to the one or more memory components and the error-correction means.