1. An electrically erasable programmable memory cell of a type having interconnected transistors coupled to a conducting read, write, sense and row line, comprising: a floating gate transistor having a control gate, connected to said sense line, a source to drain conducting path and a floating gate; a tunnel device having a cathode coupled to the floating gate, an anode, and a tunnel control electrode coupled to the sense line; read switch means for providing a conducting path between said read line and one end of the source to drain path of said floating gate transistor in response to the voltage on said row line exceeding a selective threshold value and for opening the conductive path when the row line voltage falls below the selective threshold value; write switch means for providing a conductive path between said write line and the anode of said tunnel device in response to the voltage on said row line exceeding a write selective value and for opening the conductive path when the row line voltage falls below the write selective value; wherein another end of the source to drain path of said floating gate transistor is connected to said write line and said tunnel device is operative in response to a voltage between said sense line and said write line exceeding a tunnel threshold value to tunnel electrons to or from said cathode.