1. A method of operating a processor, comprising: in response to a first execution unit of the processor attempting to write a first result of a first completed instruction to a register file of the processor at a same processor time as a second execution unit of the processor is attempting to write a second result of a second completed instruction to the register file, storing the first result to a writeback buffer of the processor, wherein the writeback buffer is positioned in a dataflow between the first execution unit and the register file; detecting, using a buffer full indicator logic, that the writeback buffer is unavailable; transmitting, from the buffer full indicator logic, a buffer unavailable signal in response to detecting the writeback buffer is unavailable; in response to receiving the buffer unavailable signal at a buffer retrieving logic, writing, using the buffer retrieving logic, the first result from the writeback buffer to the register file; inspect, using merging logic, younger execution unit instructions in a processor instruction stream than a first execution unit instruction that will overwrite a target register of the first execution unit instruction; combine, by the merging logic, the first execution unit instruction of the processor instruction stream with a subsequent second execution unit instruction of the processor instruction stream into an instruction pair if the second execution unit instruction has an input data dependency to a result of the first execution unit instruction; detect, using pair detection logic, that the first execution unit instruction, which is ready for issue, is paired with the second execution unit instruction; and responsive to a signal of the pair detection logic indicating a detection that the first execution unit instruction is paired with the second execution unit instruction, issuing, by pair issuing logic, the first and the second execution unit instructions as paired execution unit instructions.