1. A method for reducing processing time associated with a direct memory access (DMA) transfer within processing system including multiple processors, said method comprising: initiating said DMA transfer to a DMA transfer target memory image within a DMA transfer target memory over a bus; determining in a cache controller managing a cache memory associated with a particular one of said multiple processors that said DMA transfer is occurring on said bus; responsive to determining that said DMA transfer is occurring, copying data being transferred in said DMA transfer to a cache line in said cache memory during said DMA transfer; and targeting said particular processor for executing a routine that accesses memory addresses of said DMA transfer target memory image, whereby said particular processor processes data transferred by said DMA transfer.