1. An apparatus, comprising: a first differential array; and a second differential array, each of the first and second differential arrays including: a first array of parallel capacitances coupled to a first common node at a first terminal and arranged to be switched at a second terminal amongst a first leg of a differential reference voltage, a second leg of the differential reference voltage, or a first leg of a differential analog input voltage, the first array including a sequence of capacitances having a capacitance value that is approximately half of a capacitance value of a previous adjacent capacitance, according to a binary numerical pattern; and a second array of parallel capacitances coupled to a second common node at a first terminal and arranged to be switched at a second terminal amongst the first leg of the differential reference voltage, the second leg of the differential reference voltage, or a second leg of the differential analog input voltage, each capacitance of the first array having an associated capacitance within the second array with an approximately equivalent capacitance value, the first differential array and the second differential array in combination arranged to determine a digital approximation for the differential analog input voltage.