1. A signal processor for performing dyadic digital signal processing instructions having main operations and sub operations, the signal processor comprising: at least one signal processing unit including, a first multiplier and a first adder to execute a main operation of a dyadic digital signal processing instruction, a second multiplier and a second adder to execute a sub operation of the dyadic digital signal processing instruction, each of the first and second adders and the first and second multipliers having a multiplexer at its input to configure the signal processing unit to execute the main operation and the sub operation of the dyadic digital signal processing instruction, and an accumulator having registers to couple to the first multiplier or the first adder to provide operands or store intermediate results therefrom and to couple to the second multiplier or the second adder to provide an operand for the sub operation of the dyadic digital signal processing instruction and to store results of the sub operation, the accumulator register having a register to couple to the buffer memory to store the digital signal processed output generated by the dyadic digital signal processing instruction.