1. A memory controller comprising: an input device, connected to a first processor and a second processor, which receives one or more incoming data bytes from the first processor and combines them to form a first data element; a memory which stores therein a second data element having one or more data bytes, said memory being connected to an output of the input device for receiving the first data element and overwriting a portion of the second data element therewith; and an output device, connected to the first processor and the second processor, which receives data bytes of the second data element from the memory and data bytes of the first data element from the input device and combines them to form a third data element which is subsequently transmitted to the second processor, wherein the first processor and the second processor each transfers data to the memory though said input device and receives data from the memory through the output device.