1. A microcomputer comprising: a compound instruction register for receiving a compound instruction that includes a cascade operation code (opcode) that, upon decoding, indicates whether the instruction is to be sent to a second microcomputer; decode logic that fetches the compound instruction from the register and decodes the cascade opcode; execution logic that executes the instruction when the decoded cascade opcode does not include an indication that the instruction is, to be sent to the second microcomputer; and a cascaded instruction pipeline for sending the instruction to the second microcomputer for execution when the decoded cascade opcode includes an indication that the instruction is to be sent to the second microcomputer.