1. A method of designing a logic circuit, comprising: providing a leaf cell including at least one transistor, the leaf cell being suitable for use as a 1-cell or a 0-cell; tiling a first array of abutting leaf cells using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells; and adding length optimized interconnects to the tiled array wherein each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact.