1. An information processor comprising: a central processing unit core comprising a direct memory access unit; and at least one tightly coupled smart memory unit, the at least one tightly coupled smart memory unit comprising: a memory unit, directly coupled to at least one of the central processing unit core or the direct memory access unit; a control register, directly coupled to the central processing unit core; a status register, directly coupled to the central processing unit core; a local processing unit adapted to process data stored in the memory unit, adapted to be controlled by the control register and adapted to update a status of the status register.