1. A microprocessor circuit, comprising: a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port, wherein each input vector element is represented by a first predetermined number of bits (X); a plurality of matrix input registers for storage of respective matrix input elements received through the input/output port, wherein each matrix input element is represented by a second predetermined number of bits (Y); a number of digital multiply-accumulate circuits comprising respective binary multiplicand inputs coupled to the respective vector input registers for receipt of respective input vector elements and comprising respective binary multiplier inputs coupled to the matrix input registers for receipt of respective matrix input elements to produce respective intermediate multiplication values; a binary adder circuit comprising one or more binary adders configured to sum a plurality of intermediate multiplication values computed through respective multiplier cycles to produce a result vector element of the M element result vector.