1. A system for latency-aware thread scheduling in non-uniform cache architecture, comprising: one or more cores operable to run one or more threads; a plurality of banks in cache memory; one or more memory locations including at least specification identifying in which bank of the plurality of banks to store data; hardware controller operable to store data into a selected bank according to the specification, wherein the hardware controller is operable to store the data in a next nearest bank if the hardware controller is unable to store the data in the selected bank.