1. A processor core comprising: a transactional memory that stores information corresponding to a plurality of atomic memory transactions executed by the processor core, wherein the transactional memory includes transactional memory logic that, for each of a plurality of aborted transactions among the plurality of atomic memory transactions, generates a respective one of a plurality of indications that an abort-causing conflict has occurred during execution of one of the plurality of aborted transactions; an instruction address register for recording instruction addresses of abort-causing and approximate abort-causing instructions, wherein the instruction address register, responsive to each of the plurality of indications generated by the transactional memory logic, records a respective instruction address for each of the plurality of aborted transactions, wherein for at least some of the plurality of aborted transactions, the instruction address recorded in the instruction address register is that of an abort-causing instruction and, for at least some of the plurality of aborted transactions, the instruction address recorded in the instruction address register is that of an approximate abort-causing instruction in the aborted transaction different than and following the abort-causing instruction; a transaction diagnostic register that, responsive to each of the plurality of indications generated by the transactional memory logic, records a first validity indication associated with a respective one of the plurality of aborted transactions, wherein the processor core indicates, via a first state of the first validity indication, that the instruction address recorded in the instruction address register is that of an abort-causing instruction, and indicates, via a second state of the first validity indication, that the instruction address recorded in the instruction address register is that of an approximate abort-causing instruction; a data address register for recording data addresses of abort-causing and approximate abort-causing instructions; a second validity indication associated with the second address register that indicates, via first and second states of the second validity indication, whether a data address recorded in the data address register is that of an abort-causing instruction or an approximate abort-causing instruction in the aborted transaction, respectively; wherein the processor core is configured to: retrieve the addresses corresponding to each of the plurality of aborted transactions from the instruction and data address registers; and generate profiling information of the plurality of aborted transactions based on the retrieved addresses and the validity indications.