1. An apparatus comprising: one or more processor cores, each of the processor cores including performance monitoring hardware; and cache units coupled to the one or more cores, wherein the performance monitoring hardware includes logic to: identify a code page in memory containing potentially optimizable instructions; request allocation of a new page in the memory associated with the code page, wherein the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page; detect a branch instruction having a branch target within the code page; increment one of the counters that has the same position in the new page as the branch target in the code page; repeat execution of the code page and incrementing the counters when branch targets fall within the code page; and provide values of the counters in the new page to a binary translator for binary translation.