1. A circuit for capturing data on a bus, comprising: a flip-flop receiving an input data bit and producing an output data bit upon assertion of a gated clock signal; comparison logic coupled to said flip-flop that receives the input and output data bits from said flip-flop and compares the logic states of said input and output data bits and, if the logic states of said bits do not match, asserts an enable signal to indicate that said input data bit has changed state; and clock logic that receives said enable signal and an external clock signal and generates the gated clock signal based on the logic state of the enable signal and external clock signal.