1. A writing driver circuit of a phase-change memory array, comprising: a pulse selection circuit that outputs a selected one of a reset pulse and a set pulse in response to a logic level of data and the data; a current control circuit that receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs the control signal at a first level during an enable duration of the set pulse when the data is at a second level; and a current drive circuit that outputs writing current to the phase-change memory array in response to the control signal during the enable duration of the reset pulse or of the set pulse.