1. A circuit arrangement, comprising: a cache configured to store instructions; a hardware prefetch circuit coupled to the cache and configured to request the cache to fetch at least one instruction specified by the hardware prefetch circuit, wherein the hardware prefetch circuit is configurable via software in association with performing a context switch to initiate a prefetch of at least one instruction likely to be executed by a thread prior to resuming execution of the thread; and a buffer accessible by the hardware prefetch circuit and writable by software, the buffer configured to store prefetch control data used by the hardware prefetch circuit to issue fetch requests to the cache.