1. A processor comprising: a memory dependence detector configured to determine a memory dependence for a given load instruction on a given store instruction; and a register rename unit; wherein in response to receiving an indication of the determined memory dependence and determining qualifying conditions are satisfied, the register rename unit is configured to: assign a rename register identifier (ID) associated with a source operand register ID of the given store instruction to a destination operand register ID of the given load instruction; and prevent the given load instruction from reading data associated with the source operand from memory.