1. A method for controlling a data path section provided in a CPU which utilizes a microcode stored in a microprogram memory, comprising the steps of: (a) storing by microprogram memory means, microcodes corresponding to operations of the CPU; (b) storing by instruction register means, an instruction code which is received from a data bus, said instruction code representing an instruction; (c) generating by address generating means, an address to access said microprogram memory means from an output of said instruction register means; (d) decoding by first address decoder means, a particular bit in said instruction code to determine an instruction type; (e) decoding by second address decoder means, another particular bit in said instruction code to determine an addressing mode; (f) designating by third address decoder means, a cycle value for accessing said microprogram memory means during each instruction cycle; and (g) outputting said microcode having a portion which is input to said third address decoder means, said microcode not being directly feedback into inputs of said microprogram memory means.