1. A memory system, comprising: a dynamic memory with a refresh cycle, said memory including a first memory portion for storing a plurality of data words and a second memory portion for storing groups of check bits, one group of check bits associated with each data word in said first memory portion; control circuitry for controlling the operation of said memory, including a refresh address counter for periodically supplying an address to said memory to refresh a block of the data words stored in said first memory portion; and error detection and correction means connected to said memory for periodically checking for and correcting any bit errors in each of the data words stored in said first memory portion, including a self-correct address counter augmenting said refresh address counter so that during each refresh cycle the address supplied to said memory defines a selected data word within the block refreshed, the selected data word being checked and corrected for any bit errors.