1. A memory controller for a plurality of banks of memory, the memory controller including an interface connectable to a bus to communicate with a processor, the memory controller redundantly mapping the plurality of banks of memory to a memory space and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space and/or one or more of the plurality of banks of memory, wherein, responsive to receipt at said interface of a request from said processor for one of said memory operators, the memory controller is configured to execute, independently of the processor, the respective memory operator on the memory space and/or one or more of the plurality of banks of memory; a first control pathway to provide the processor access to the memory space as a single addressable memory wherein, when first data is stored in the single addressable memory and a duplicate of the first data is stored in one of the plurality of banks of memory, the one of the plurality of banks of memory is not visible to the processor and the processor is not able to access the duplicate of the first data via the first control pathway; a second control pathway to provide the processor direct access to the data in each of said plurality of banks of memory including the first data and the duplicate of the first data; a pathway selection input to receive a selection of one of the first control pathway or the second control pathway to be used for a memory access request received via the interface from the processor.