1. A pipelined microprocessor, comprising: a control register, configured to store a control value that affects operation of the microprocessor; an instruction set architecture, that includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, wherein the instruction set architecture further includes a serializing instruction that updates the control value in the control register, wherein the microprocessor is configured to complete all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction; execution units, coupled to the control register, configured to update the control value in the control register in response to the serializing instruction; and a fetch unit, coupled to the control register, configured to fetch, decode, and unconditionally correctly resolve and retire the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.