1. In an array of push-pull memory cells arranged in a plurality of rows and columns, the array comprising a V P line associated with each row of the array, a p-wordline associated with each row of the array, an n-wordline associated with each row of the array, a program wordline associated with each row of the array, a bit line associated with each column of the array, and a plurality of memory cells, each memory cell uniquely associated with a row in the array and a column in the array, each memory cell including a p-channel non-volatile transistor having a source coupled to the Vp line associated with its row, a drain, a floating gate and a control gate, the control gate coupled to the p-wordline associated with its row, a p-channel volatile transistor having a source coupled to the drain of the p-channel non-volatile transistor, a drain, and a control gate coupled to the program wordline associated with its row, and an n-channel non-volatile transistor having a source coupled to the bit line associated with its column, a drain coupled to the drain of the p-channel volatile transistor, a floating gate and a control gate, the control gate coupled to an n-word line associated with its row, a method for simultaneously programming the n-channel and p-channel non-volatile transistors in a selected memory cell comprising: driving to 0 v the p-wordline and the n-wordline for any row in which programming of memory cells is to be inhibited; driving to a positive voltage the p-wordline and the n-wordline for any row in which programming of memory cells is to be performed; driving to a positive voltage the bit line for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bit line for any column in which programming of memory cells is to be performed; driving to one of 0 v and a negative voltage the program wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0 v and a positive voltage the program wordline for any row in which programming of memory cells is to be performed.