1. A multi-core processor system comprising: a plurality of mutually communicatively inter-coupled processor cores, at least one processor core of the plurality of mutually communicatively inter-coupled processor cores being configured to: receive an instruction directing the at least one processor core to read a variable associated with a memory address; and in response to receiving the instruction and before execution of the instruction, cause ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values of the variable, the plurality of locally stored values usable to determine a global value of the variable, the locally stored values being stored individually in the ones of the plurality of mutually communicatively inter-coupled processor cores and being associated with the memory address.