1. A logical operations functional block for an execution unit of a processor, the logical operations functional block including a first input data link for a first operand and a second input data link for a second operand, wherein the execution unit includes a register connected to an error correction code detection unit, the logical operations functional block comprising: a look-up table configured to receive an error correction code syndrome from the error correction code detection unit, wherein the error correction code syndrome indicates a mismatch between data in the register and a related error correction code memory, and wherein the error correction code syndrome indicates a location of one or more wrong bits in a data word; and a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein the multiplexer further comprises a select signal input for receiving a select signal; wherein the input of the look-up table is connected to an output of the error correction code detection unit, wherein an output of the look-up table is coupled to the first input of the multiplexer, and wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.