1. A data processing system that provides a debug capability, said data processing system comprising: an arithmetic logical unit with a first ALU input; a write back bus register that receives results from the arithmetic logical unit; a first selector circuit that selects one of a plurality of selector circuit inputs as the first ALU input, wherein: one of the plurality of selector circuit inputs is an output from the write back bus register; and a feed forward control circuit that programatically forces the first selector circuit to select the output from the write back bus register during an execution of a standard processor instruction in order to perform a debug function.