1. A data-array processing system, comprising: a memory system (700,740) for storing an array of data elements and addressable (on 319) by a single address (xq,yq); a plural number N of processors (606(0)-(15); PROC(0)-(15)) capable of processing data elements in parallel and operable to read data elements from and/or write data elements to the memory system at addresses which can be the same or different for the different processors; and an address bus (323); wherein each processor (PROC(q)) is selectable (steps 630 to 640) to supply (step 645) its respective required address (xq,yq) via the address bus to the memory system to access (step 652) the memory system; and wherein each non-selected processor is operable to determine (steps 646,648) whether it requires access to the address (xq,yq) on the bus and if so to access (step 652) the memory system at the same time as the processor (PROC(q)) which supplied the address to the bus.