1. An embedded-DRAM (dynamic random access memory) processor comprising: a DRAM array comprising a plurality of random access memory cells arranged in rows and columns; a set of row address registers; one or more sets of registers, each of said sets of registers capable of being loaded or stored in response to a single latch signal; and an instruction set which includes: (i) at least one command to perform arithmetic on said row address registers; (ii) a command to precharge (activate) rows pointed to by said row address registers; (iii) a command to deactivate rows pointed to by said row address registers; (iv) a command to load a plurality of words of a row designated by said row address registers into designated sets of data registers; and (v) a command to load selected columns of rows pointed to by said row address registers into designated sets of data registers, said selection based on bits in a mask.