1. A memory test system comprising: a set of memory banks; a pointer configured to point to a next memory bank in the set of memory banks to be tested such that said next memory bank is skipped when a memory access is currently blocking access said next memory bank; a first deficit bank pointer configured to identify a first deficit memory bank among the set of memory banks that has been skipped due to a blocking memory access; and a first deficit counter associated with said first deficit bank pointer, said first deficit counter configured to store a count of a number of times that said first deficit memory bank has been skipped for testing; wherein said first deficit memory bank identified by said first deficit bank pointer is given priority for testing over said next memory bank pointed to by said pointer when said first deficit counter is not zero.