1. A system for processing an operation, comprising: a microengine configured to issue a plurality of command sets to a hardware accelerator unit; a shared memory unit operatively connected to the microengine, the shared memory unit configured to store control information that may be accessed by the microengine and used to generate a command set; a plurality of circuitries included within the hardware accelerator unit, each circuitry configured to receive the command set from the microengine, the command set configured to allow for the processing of a plurality of different operations; and a hardware configuration register located within each of the plurality of circuitries, the hardware configuration register configured to receive configuration data from the microengine.