1. A circuit arrangement, comprising: a plurality of processing nodes coupled to one another over a shared network; and a plurality of address translation data structures respectively disposed in the plurality of processing nodes; wherein a first processing node among the plurality of processing nodes is configured to decode a translation management instruction defined in an instruction set for the first processing node, and in response to decoding the translation management instruction, initiate an invalidation operation on the address translation data structure in a second processing node among the plurality of processing nodes to invalidate an entry in the address translation data structure in the second processing node without invalidating a corresponding entry in the address translation data structure in the first processing node.