1. An apparatus for detecting a thread switch condition in a processor having one or more processor registers and an associated memory system including one or more caches and a main memory, the apparatus comprising: a load tracking module, the load tracking module to monitor loads that return data to the processor registers, including bus requests generated in response to loads that miss in one or more of the caches; a cache miss register including entries, each of which is associated with one of the processor registers; and a mapping module coupled to the load tracking module and the cache miss register, the mapping module to map a bus request to a register and to set a bit in a cache miss register entry associated with the register when the bus request is directed to a higher level structure in the memory system.