1. A circuit for testing multiple memories, comprising: two or more BIST controllers within an integrated circuit, wherein each of the two or more BIST controllers comprises a BIST address port for coupling with address ports on the multiple memories and a BIST data port for coupling with data ports on the multiple memories; and two or more resume inputs on the integrated circuit for receiving resume signals, wherein each of the two or more resume inputs is coupled in parallel to at least one of the two or more BIST controllers, wherein the two or more BIST controllers are responsive to the resume signals on the two or more resume inputs to exit an idle state.