1. A method of analyzing a partition of a circuit design, comprising: determining a predetermined partition of a circuit design being emulated; sampling an emulator to obtain one or more input values provided at a first time to the predetermined partition of the circuit design being emulated; sampling the emulator to obtain one or more first state values produced by the circuit design partition at the first time; using the obtained one or more input values and the one or more first state values to execute a software model that describes the operation of the circuit design partition, so as to calculate one or more second state values produced by the circuit design partition at a second time; and registering the one or more second state values in a tangible medium.