1. A system, comprising: a data store configured to store a record associated with an instruction processed by a pipelined processor; a performance monitoring logic configured to detect an event caused by an instruction in the pipelined processor, to store a processor state information concerning the pipelined processor when the event occurred, to write the record to the data store, and to selectively suspend the writing of records to the data store upon occurrence of an identified event; and an instruction location logic configured to navigate through records in the data store by cycle counting to locate a first record associated with an instruction retiring from the pipelined processor when the identified event occurred and by retirement counting to locate a second record associated with an instruction executing at a pipeline stage when the identified event occurred.