1. A method comprising: selecting an operation to be performed by a circuit, the operation including a plurality of partial operations of different types; identifying variables to be used by the plurality of partial operations; ordering the variables based on a time order in which the variables are used by the plurality of partial operations; ordering the plurality of partial operations based on the ordering of the variables; representing a plurality of hardware components for performing the operations with a data flow graph having edges and nodes, the edges and nodes being connected based on the ordering of the plurality of partial operations; simulating a plurality of solutions for performing the operations, each solution corresponding to a hardware component combination represented as a path on the data flow graph; determining a cost for each solution, each cost including a number of edges and nodes traversed on the data flow graph for a path corresponding to the respective solution; and selecting a solution with a lowest cost as a hardware component combination for a circuit.