1. A chipset with RAID access, comprising: a Northbridge coupled between a central processing unit and a system memory, having a RAID accelerator for performing RAID operations; and a Southbridge coupled between the Northbridge and a RAID having a plurality of hard disks, for accessing data in the RAID, wherein the Northbridge further comprises a Northbridge register storing RAID control commands and disk access commands and the Northbridge register further comprises a memory mapping register for storing disk access commands and a shadow register for storing RAID control commands, wherein the RAID accelerator performs RAID operations according to RAID control commands and the Northbridge snoops the memory mapping register and maps RAID control commands from the Southbridge to the shadow register while the memory mapping register is accessed.