1. A processor for performing a Fast Fourier Transform (FFT), comprising: at least one radix-2 butterfly structure; at least one radix-4 butterfly structure; a buffer structure for inputting a data stream and storing data output from the radix-2 and radix-4 butterfly structures; FFT logic configured to perform an FFT on a data stream in multiple stages by alternately coupling the data stream to inputs of the radix-2 butterfly structure or to inputs of the radix-4 butterfly structure, the FFT logic being capable of performing at least two different resolution fast Fourier transforms dependent on the inputs selected; and address generation logic configured to generate buffer addresses for the buffer structure during the multiple stages by reordering bits of a sequential counter, and wherein the buffer structure is structured in a parallel paired configuration such that addressing for the radix-4 butterfly structure at a first resolution is reusable for addressing the radix-2 butterfly structure at a second resolution.