1. A method of operating a processor; the processor including processing circuitry for performing arithmetic operations in parallel on operands; the processing circuitry having two or more processing positions, each for performing operations on one bit; the processing circuitry comprising position connecting circuitry connecting the processing positions in pairs to form an array of processing positions; the position connecting circuitry connecting each pair of processing positions so that a signal from one of-the processing positions in the pair can be transferred to the other processing position in the pair; the method comprising acts of: providing to the processing circuitry a composite operand that includes two or more component data items, each including more than one bit; each component data item being provided to a respective subarray of processing positions in the processing circuitry; and operating the processing circuitry to perform an arithmetic operation in parallel on the composite operand; the arithmetic operation obtaining, in the subarray of each component data item, a respective resulting data item; the subarray of a first one of the component data items providing an inter-component signal to position connecting circuitry connecting to a receiving processing position that is not in the subarray of the first component data item during performance of the arithmetic operation; the component data items being ordered in a sequence, each pair of adjacent component data items in the sequence being separated by at least one buffer bit whose value can be modified to ensure that each resulting data item indicates a valid result despite the inter-component signal; the act of providing a composite operand comprising providing one of the buffer bits to the receiving processing position; the act of operating the processing circuitry comprising obtaining a value in the receiving processing position so that the receiving processing position does not respond to the inter-component signal by providing a signal to the position connecting circuitry and so that each resulting data item indicates a valid result of the arithmetic operation on the respective component data item despite the inter-component signal.