1. A system for executing a symmetric key cryptographic method comprising: a processor selecting data paths, a key, an initialization vector; a memory storing batched operation parameters; a bus connected to the processor and the memory; a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately; and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to the processor via the cryptographic processor or the bus, wherein the bus bypasses the cryptographic processor.