1. A method comprising: receiving a programmable processor reset command from a debug access port of an integrated circuit; blocking, by a boot logic upon said reset of a programmable processor on the integrated circuit, commands to said programmable processor from said debug access port, while still allowing said reset command to said programmable processor to be asserted from said debug port; and allowing, by said boot logic, write access to memory by said debug access port to receive a boot loader code image written to said memory while said reset command is asserted.