1. An intelligent packet switch for reducing data processing latency at a packet destination by embedding data processing operations that would conventionally be performed at the packet destination into the intelligent packet switch, the switch comprising: a plurality of ports; switching logic; and a processor, wherein the processor comprises at least one member of the group consisting of a reconfigurable logic device, a graphics processor unit (GPU), and a chip multi-processor (CMP); wherein the switching logic and processor are co-resident within the intelligent switch; at least one of the ports being configured to receive a plurality of incoming data packets, the incoming data packets comprising a plurality of financial market data messages, the financial market data messages comprising data that describes financial market data for a plurality of financial instruments; at least another of the ports being configured to output a plurality of outgoing data packets, the outgoing data packets comprising data that describes at least a portion of the financial market data; wherein the switching logic is configured to determine a port for the outgoing data packets with reference to the incoming data packets; and wherein the at least one member is configured to perform a packet mapping operation on at least a portion of the data describing the financial market data; and wherein, as part of the packet mapping operation for each of a plurality of the received incoming data packets, the at least one member is further configured to (1) determine a financial market data feed associated with a received incoming data packet, (2) access metadata associated with the determined financial market data feed, the metadata comprising data for enabling a parsing of that received incoming data packet, and (3) associate the accessed metadata with that received incoming data packet.