1. A computer-implemented method of designing a stacked integrated circuit having an interposer and at least a first die disposed upon the interposer, wherein, a portion of the first die and a portion of the interposer have the same function, the method comprising: providing a physical layout group, comprising: a first layout corresponding to the first die having both a first function and a second function, the second function being different from the first function; and a second layout corresponding to the interposer configured for the first die connected thereon; partitioning the physical layout group into a first physical layout partition corresponding to the first function, wherein the first physical layout partition is composed of the portion of the first layout and the portion of the second layout having the first function; performing a first automatic place-and-route (APR) process to obtain a first hierarchical layout according to the first physical layout partition; verifying the first hierarchical layout to obtain a verified first hierarchical layout by using a first verification, wherein the verification of the portion of the first die and the portion of the interposer having the same function is performed in parallel; partitioning the physical layout group into a second physical layout partition according to the second function; performing a second automatic place-and-route (APR) process to obtain a second hierarchical layout according to the second physical layout partition; performing a second verification on the second hierarchical layout; and merging the first hierarchical layout and the second hierarchical layout to obtain a single physical layout of a stacked integrated circuit device comprising the first die, the second die and the interposer; and performing a third verification on the single physical layout; and fabricating the integrated circuit based on the verified first hierarchical layout.