1. A system in a processor comprising: a central processing unit (CPU) within a CPU cache coherency domain having a first set of coherency rules; a graphics device within a graphics cache coherency domain having a second set of coherency rules different from the first set of coherency rules; a CPU cache hierarchy including the CPU and including: a level 1 (L1) CPU cache operatively coupled with the CPU, and a second cache at a different level than the L1 CPU cache, the second cache being physically addressed; and a graphics cache hierarchy including the graphics device and including: an L1 graphics cache operatively coupled with the graphics device, and a third cache at a different level than the L1 graphics cache, the third cache being physically addressed; said CPU to apply the first set of coherency rules to the third cache, and said graphics device to apply the second set of coherency rules to the third cache, thereby allowing data to be shared between the CPU cache coherency domain and the graphics cache coherency domain.