1. A processor comprising an execution core configured to execute a first instruction defined in an instruction set architecture implemented by the processor, wherein the first instruction comprises at least a first operand from which the execution core is configured to determine a virtual address, and wherein the first instruction comprises a second operand that specifies one or more translation attributes that exist in a page table entry that defines a translation for the virtual address, wherein the one or more translation attributes exclude the physical address to which the virtual address translates, and wherein the execution core comprises translation circuitry configured to translate the virtual address, and wherein the translation circuitry is configured to verify that the translation attributes in the page table entry match the specified translation attributes, wherein the translation circuitry is configured to fault the first instruction responsive to locating a translation for the virtual address in the page table entry but with the translation attributes in the entry failing to match the specified translation attributes, and wherein the execution core is configured to complete the instruction without a fault responsive to the translation circuit locating the translation and the translation attributes match the specified translation attributes.