1. A memory cell configuration, comprising: a semiconductor substrate; and a multiplicity of memory cells each having a selection transistor with a terminal, a memory transistor with a control electrode, and a ferroelectric capacitor disposed in an integrated manner in said semiconductor substrate, said selection transistor and said memory transistor connected in series through said terminal of said selection transistor, said ferroelectric capacitor connected between said terminal of said selection transistor and said control electrode of said memory transistor.