1. A programmable logic device comprising: a plurality of logic blocks; a plurality of registers; routing resources adapted to provide a programmable data path between the logic blocks and the registers; configuration memory adapted to store configuration data for configuration of the logic blocks and the routing resources of the programmable logic device; and a logic circuit adapted to control a transfer of data from the logic blocks to the registers via the routing resources to maintain the data transferred to the registers during a reprogramming operation of the programmable logic device.