1. A specialized processing block for a programmable logic device, said specialized processing block comprising: a plurality of multipliers; and circuitry for adding and/or subtracting and/or accumulating outputs of said multipliers; wherein: at least one of said multipliers has a respective sign control input associated with at least one respective multiplicand input thereof, to which a signal is applied that controls whether said respective multiplicand input is treated as signed or unsigned; said specialized processing block further comprising: a selector at each said sign control input that controllably selects between a first signal that forces said multiplicand input to be unsigned and a second signal that indicates whether said multiplicand input is signed or unsigned, in response to a control signal separate from said first signal and from said second signal.