1. A vector mask operation control unit in a data processing system for executing processing of masked, vector instructions decoded by an instruction control unit comprising: counting means for counting consecutive operation-inhibitory bits in a plurality of bits, each operation-inhibitory bit masking one of a plurality of vector operands pointed to by said vector instructions decoded by said instruction unit; means for preventing memory access and arithmetic operations on said masked operands comprising: (a) increment generating means for generating a total address increment value in response to the count of consecutive operation-inhibitory bits counted by said counter means, said total address increment value being comprised of at least one address increment value multiplied by a power of two; and (b) address generating means for obtaining an operand address by adding the total address increment value received from said increment generating means, and a vector address.