1. A method of soft bit computation for a reduced-state equalizer, comprising the steps of: (a) computing a first set of soft bits for bits transmitted in a received signal, wherein the first set is computed using a reduced-state trellis with finite non-zero delay (b) calculating hard decisions in response to the received signal, and (c) ensuring that substantially all soft bits are computed, by employing zero-delay soft decision-making or decision-feedback equalization to compute a second set of soft bits, while also using the hard decisions to compute the second set.