1. A computer-implemented method of parallel processing digital input signal vectors of an input block of a synchronous decision feedback circuit, the input block having N branches, the computer-implemented comprising: pre-computing N input signal vectors each having M entries, each entry being a possible value of one of the N branches; evaluating all possible values of the input signal vectors according to a set of M pre-assigned decision feedback signals to provide M intra-block decision signal vectors, each intra-block decision signal vector having N entries; and processing each of the entries of each of the intra-block decision signal vectors according to an inter-block decision feedback signal to select N outputs for the input block, the inter-block decision feedback signal being based on outputs for a previous block.