1. A computer-implemented method for handling a plurality of constraints in an integrated circuit layout using at least one computing device, the method comprising: building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints on the graph to form a marked constraint graph; generating two-dimensional clusters including groups of the two-dimensional constraints, using the at least one computing device; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster, using the at least one computing device; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters.