1. A hardware-implemented system for generating an instruction operation code, comprising: a processor; an operation code bit width decision section which decides, according to specification data associated with a processor instruction set, a bit width to be assigned for an operation code of each instruction of the processor instruction set based on a width of a bit pattern of all operands of each instruction read out from the specification data in such a way that the bit width to be assigned for the operation code of each instruction is decided to be a difference which is obtained by subtracting the width of the bit pattern of all operands of said each instruction from a word length of said each instruction; an instruction classification section which rearranges the instructions within said processor instruction set in an order which accords to the operation code bit width; and an operation code value decision section which decides a value of the operation code of each instruction according to the operation code bit width and a rearranged sequence of the instructions.