1. A central processing unit CPU for processing data streams having a plurality of threads, the central processing unit comprising: an arithmetic logic unit ALU coupled to a first and second bus; a shift/extract block coupled to the first and second buses; a timer unit coupled to the first and second buses; a plurality of general purpose register sets for storing data, each of the sets, when associated with corresponding state information, being representative of one of the threads and being coupled to the first and second buses, such that each general purpose register set is dedicated to a particular thread, whether or not the particular thread is being executed; a plurality of special purpose registers for storing data, each of the special purpose registers being coupled to the first and second buses; a memory controller for controlling access to an external memory, the memory controller being coupled to an external bus and the first and second buses; an events system for sampling hardware events and software events, for storing said hardware events and said software events as hardware events, and for associating one of the threads with at least one of the hardware events; a scheduler, coupled to the events system, for determining which one of the threads has priority for use of the CPU; a pipeline controller for controlling use of the ALU, the shift/extract block and timer and for selecting the general and special purpose registers used; the pipeline controller coupled to the ALU, the shift/extract block, the timer, the general and special purpose registers, scheduler and memory controller; and a masque register for storing data, for providing access to the general and special purpose registers and the second bus, and for providing access to the general and special purpose registers of other threads.