1. A multiplication engine for a digital processor, the multiplication engine comprising: a first partial-product generation circuit to generate a first set of unequally weighted partial products from a set of input operands; a second partial-product generation circuit to generate a second set of equally weighted partial products from the set of input operands; a multiplexer to select the first set of unequally weighted partial products or the second set of equally weighted partial products in accordance with first and second multiplier modes, respectively; and a carry save adder array configured to add the selected set of partial products, wherein, in the first multiplier mode, the carry-save adder array folds over higher-order bits of the first set of unequally weighted partial products into lower-order slots in the carry-save adder array, thereby allowing the same carry-save adder array to be used in either the first or the second multiplier modes.