1. A processor comprising: a virtual state mechanism to form a critical update loop that does not include state update logic, the critical update loop being formed each time an actual active thread state of a thread of a plurality of threads is detected, the critical update loop being formed between a virtual state reload multiplexer and a virtual thread state structure, the virtual state mechanism including the virtual state reload multiplexer to receive the actual active thread state of the thread; and the virtual thread state structure coupled with the virtual state reload multiplexer, the virtual thread state structure having a virtual thread state register to generate and store a virtual active thread state based on the actual active thread state, wherein the virtual thread state structure is further to forward the actual active thread state to the state update logic, and the virtual thread state structure to continuously reload the virtual active thread state within the critical update loop until another actual active thread is detected.