1. An apparatus, comprising: processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by: splitting the data into a plurality of elements; copying each of the plurality of elements into elements that are wider than before being copied; and performing a logical operation associated with the reduction operation on each of the copied elements; and wherein the processing circuitry is configured to compute the reduction operation without transferring the data via an input/output (I/O) line external to the group of memory cells.