1. In a flash memory system, program control circuitry for programming a flash memory array in response to an active program control signal, the flash memory system and the program control circuitry residing on a single substrate, the flash memory system including terminals for coupling external signals to the flash memory system, a command state machine for recognizing a program command sequence applied to the terminals and generating the program control signal, the command state machine bringing the program control signal to the active state in response to the program command sequence, a step of the program command sequence including application of address signals representing an address of a first byte of the flash memory array to be programmed and application of reference data signals representing reference data to be programmed into the first byte, the program control circuitry including: 1) programming means for applying a single programming pulse at a time to the first byte in response to a first state of a set of control signals, the programming means programming the first byte to the reference data; 2) program verify means for verifying the programming of the first byte in response to a second state of the set of control signals, the program verify means bringing a match signal active if the data stored by the first byte matches the reference data signals and, if not, bringing the match signal inactive; 3) control means responsive to the program control signal for controlling the programming means and program verify means via the set of control signals, the control means determining a state of the set of control signals based upon the match signal and a number of program pulses previously applied to the first byte, the control means bringing the set of control signals to the first state if the match signal is inactive and the number of program pulses does not equal a maximum number, the control means bringing a program status bit to a fail state indicating failure of the first byte to program when the match signal is inactive and the number of program pulses equals the maximum number, the control means bringing the program status bit to a success state indicating successful programming of the first byte when the match signal is active.