1. A method comprising: signaling a plurality of state registers of a processor that a processor power state of the processor is going to be changed to a zero processor power state from an active processor power state; then based on the signaling, writing a plurality of state data stored in a plurality of state bits of the plurality of state registers to a plurality of keeper circuits of the plurality of registers; then changing a processor power state of the processor and of the state bits from the active processor power state to the zero processor power state to reduce power consumption, while maintaining a processor power state of the keeper circuits to maintain the plurality of state data stored in the plurality of keeper circuits.