1. A superscalar processing system, comprising: a plurality of pipelines configured to process instructions of a computer program; coalescing circuitry configured to receive, from said pipelines, a plurality of register identifiers identifying a plurality of registers, said coalescing circuitry configured to coalesce said register identifiers thereby generating a coalesced register identifier identifying each of said plurality of registers; and hazard detection circuitry configured to receive said coalesced register identifier and to perform a comparison of said coalesced register identifier with other information received from said pipelines, said hazard detection circuitry further configured to detect a data hazard based on said comparison.