1. A set of circuits for a computing device comprises: a processing module; and a memory controller operably coupled to the processing module, wherein the memory controller is operable to: utilize a memory map of memory of the computing device, wherein the memory map identifies a user section and a kernel section within the memory, wherein the user section includes a plurality of pillars and the kernel section includes a plurality of pillars; facilitate reading of data by the processing module from the memory by: determining whether the data is stored as one or more sets of encoded data slices; when the data is stored as the one or more sets of encoded data slices: determining whether the data is user data or system data; when the data is user data, retrieving, for each of the one or more sets of encoded data slices, an encoded user data slice from a threshold number of pillars of the plurality of pillars in the user section; decoding the retrieved encoded user data slices in accordance with a dispersed storage error coding function to produce the user data; and sending the user data to the processing module.