1. A method of reading a semiconductor storage device comprising memory cells arranged at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells including a rectifier element and a variable resistance element connected in series, the method comprising: performing a first concurrent read operation on M of the first wirings (where M is a natural number); and performing a second concurrent read operation on N of the first wirings (where N<M, N is a natural number) according to a result of a determination of the first concurrent read operation.