1. A method for reading out a non-volatile memory element having at least two stable states 0 and 1, the non-volatile memory element comprising a DRAM memory cell and an antiserial connection of two resistive memory cells A and B, which are connected in series with a capacitor of the DRAM memory cell, the method comprising: encoding one state of the stable states 0 and 1 into a state in which resistive memory cell A has a low resistance state (LRS) and resistive memory cell B has a high resistance state (HRS); and encoding another state of stable states 0 and 1 into a state in which resistive memory cell A has a high resistance state (HRS) and resistive memory cell B has a low resistance state (LRS).