1. A security system for a microprocessor based system having multiple subsystems for insuring that the power consumption of the microprocessor based system is not indicative of the instructions that it is executing, the security system comprising: a power correlator, for estimating the power that the microprocessor based system will consume during execution of instructions; and subsystem inhibition control, coupled to said power correlator, for utilizing said estimated power, and for selectively turning on/off ones of the multiple subsystems within the microprocessor based system during execution of the instructions; wherein the ones of the multiple subsystems that are turned on/off are selected so as to disassociate the total power consumed by the microprocessor based system from the instructions it is executing.