1. A method of identifying a cause of an interrupt related to an interrupt indication received from an interrupt indicating circuit in a processor, the method comprising: providing in the interrupt indicating circuit a plurality of lowest-layer registers having a plurality of bits, each of the plurality of bits corresponding to the cause of the interrupt, and one or more upper-layer registers for aggregating the plurality of lowest-layer registers; forming a hierarchical structure with the one or more upper-layer registers and the plurality of lowest-layer register; when the processor receives a first interrupt indication from the interrupt indicating circuit, having the processor read the upper-layer registers and the lowest-layer registers in order following the hierarchical structure to identify a cause of a first interrupt; and when the processor receives a second interrupt indication while identifying the cause of the first interrupt related to the first interrupt indication, having the processor directly read the lowest-layer register corresponding to a cause of a second interrupt related to the second interrupt indication based on an address read from the interrupt indicating circuit, to identify the cause of the second interrupt.