1. A computer system comprising: an instruction pipeline circuit, comprising: an address register for fetching instruction addresses; an instruction cache for storing fetched instructions; an instruction queue for storing decoded instructions; a branch prediction circuit, comprising: a global history register maintaining a global history vector, wherein the global history register comprises a fetch group history portion and a branch history portion; a predictor for predicting a direction of any branches in the fetch group; combination logic for combining an instruction from the instruction register with the global history vector for indexing into the predictor; a global history update circuit, comprising: a storage register for storing the global history vector associated with the fetch group; and fetch group history check logic for: speculatively updating the fetch group history of the global history register with a fetch group history value for the fetch group; evaluating whether the fetch group contains a predicted taken branch; flushing instructions from the instruction cache and instruction queue when the fetch group contains a taken branch; repairing the global history register to the global history vector stored in the storage register when the fetch group contains a taken branch; updating the fetch group history of the global history register based on branch prediction information from the predictor when the fetch group contains a taken branch; and updating the branch history of the global history register with a branch history value for each branch in the fetch group when the fetch group does not contain a taken branch.