1. A majority decision device in a system of the type wherein a data word of M bits is serially and repeatedly received a given number of times N, comprising: a plurality of parallel shift registers, each having a bit length equal in number to the length of said received data word, said plurality being the smallest integer equal to or exceeding log.sub.2 N; a full adder having parallel output signals from said shift registers applied thereto as first addition input signals; means for setting a predetermined bias value at second parallel addition input terminals of said full adder, means for serially applying said received data words as a carry input signal to said full adder, the parallel sum output signals obtained from said full adder being connected to said plurality of shift registers, wherein each time said data word is received, said data word is added with the parallel output signals given from said shift register group and the result signals are again fed to said shift register group, said addition being repeated N .times. M times, and after said bias value has been added to the adder, a carry signal from full adder constituting the majority decision-data.