1. A circuit arrangement, comprising: a system memory; a slave processor coupled to the system memory and including, a control unit configured to process instructions of a first set retrieved from the system memory by the slave processor, wherein the first set of instructions is native to the slave processor, an internal control register arrangement configured to provide at least one of several operational states for the slave processor, a program counter register in the internal control register arrangement configured to point to an address of a next instruction to be processed by the control unit, and a control register access port coupled to the internal control register arrangement to provide external access thereto; and a master processor coupled to the system memory and coupled to the slave processor, the master processor configured to process instructions of a second set retrieved from the system memory and to selectively start execution of the slave processor with a predetermined operational state by writing data into the internal control register arrangement through the control register access port to modify the program counter register, wherein the second set of instructions is native to the master processor and different from the first set.