1. A processor of a virtualization based system comprising: a processor bus; a buffer to store a mapping from a guest address to a host physical address; fetch logic to receive an instruction and to receive an operand; decode logic to decode the instruction; and a logic circuit to perform, at least in part in response to the decoding of the instruction, a synchronization of a mapping from a guest address to a physical address of the host (host physical address) stored in the buffer with a corresponding mapping stored at least in part in an extended paging table (EPT), the synchronization further based at least in part on the operand of the instruction, the operand further comprising at least one of a context descriptor and an EPT pointer.