1. A cache memory for a cached processor, the cached memory being arranged to record a program flow of the cached processor, the cache memory comprising: a cache array for storing information; a tag array for storing tag addresses for the information stored in the cache array; input means for receiving program addresses of information to be processed in the cache array by the program; address generating means for generating a sequence of addresses; and mode switching means for switching the cache memory between a normal mode of operation in which the cache array is accessed by the program using the program addresses and tag addresses and an address capture mode of operation in which, during execution of the program, the program addresses are fetched and stored in at least a part of the cache array according to the sequence of addresses.