1. An apparatus comprising: one or more memory die, a memory die comprising: a plurality of non-volatile memory cores that share a data path, the cores comprising arrays of non-volatile memory cells; a command/address buffer that queues command and address information for a plurality of storage operations for the non-volatile memory cores; and an on-die controller that initiates a first unexecuted read operation and a first unexecuted write operation from the command/address buffer in parallel, in response to determining that core dependencies are satisfied for the read operation and the write operation, and that updates a core dependency indicator for a core to indicate that a core dependency is not satisfied in response to one or more of a read pointer for the command/address buffer pointing to an unexecuted write operation for the core and a write pointer for the command/address buffer pointing to an unexecuted read operation for the core.