1. A semiconductor memory comprising: a plurality of memory cells aligned with one another along a first wordline and a second wordline; each of said memory cells comprising an access transistor and a capacitor, said access transistor selectively connecting a digitline to said capacitor; said first wordline being connected to control the access transistors of every other one of said plurality of memory cells; and said second wordline being connected to control the access transistors of the remaining ones of said plurality of memory cells.