1. An early evaluation, self-timed phased logic gate, comprising: a block compute function; a master arrival detection function; a trigger compute function; a trigger arrival detection function; a plurality of inputs; and at least one block output; wherein said at least one block output is capable of being updated by said block compute function upon the arrival of only a subset of said plurality of inputs as indicated by said trigger arrival detection function and said trigger compute function evaluating to true; and wherein said at least one block output is capable of being updated by said block compute function upon the arrival of all of said plurality of inputs as indicated by said master arrival detection function and said trigger arrival detection function, and upon said trigger compute function evaluating to false.