1. A microprocessor, comprising: one or more memories, configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed; a decompression unit, configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed; wherein the one or more memories are configured to provide words in response to an address input, wherein the words include the microcode instructions at least a portion of which are compressed; wherein the decompression unit is configured to determine whether the words fetched from the one or more memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction having a second portion included in an adjacent word; wherein the decompression unit is configured to decompress the compressed microcode instructions into uncompressed microcode instructions and to join the first and second portions of the uncompressed microcode instructions into uncompressed microcode instructions.