1. A method of testing coherency of data storage in a memory shared by a plurality of processor cores through core interconnects in a device under test (DUT), wherein the processor cores includes caches, the method comprising: running test patterns including data transactions between the processor cores and the shared memory; and comparing results of the data transactions with expected results, wherein the test patterns cause memory thrashing, wherein the data transactions include transactions with the caches as well as transactions with the shared memory, and wherein at least some of the test patterns include irritator operations having interrupts that modify cache lines or cache line states indirectly.