1. A method for performing circuit verification, comprising: receiving a circuit design having multiple path networks; encoding signals to account for the multiple path networks, wherein the signals are used to model multiple activation paths; performing equivalence checking, by using a processor, on the circuit design to check for errors by flagging actual and potential collisions in the circuit design based at least in part upon the encoded signals such that the multiple path networks with the potential collisions are determined to be in an error condition, for the equivalence checking, wherein the multiple path networks with the potential collisions comprise a scenario that does not indicate a collision but has the potential to result in the collision, in which equivalence checking is performed by evaluating the signals; and storing the circuit design in a volatile or non-volatile computer-usable medium or displaying the circuit design on a display.