1. An apparatus for mapping an architectural register to a physical register, the apparatus comprising: a memory configured to store an intra-core register rename map and an inter-core register rename map, the intra-core register rename map configured to map the architectural register to the physical register of a first core of a multi-core processor, the inter-core register rename map configured to relate the architectural register to an identification of the first core in response to determining that the physical register is a location of a most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core, the most recent write being according to a program order, wherein the multi-core processor is configured according to a block-based microarchitecture, the first core is configured to execute instructions assigned to blocks of instructions, and the blocks of instructions are configured according to a block-based instruction set architecture, wherein the intra-core register rename map comprises a first input intra-core register rename map associated with a first block of instructions, a first output intra-core register rename map associated with the first block of instructions, a second input intra-core register rename map associated with a second block of instructions, and a second output intra-core register rename map associated with the second block of instructions, and wherein the first block of instructions includes a block header having a write mask, the write mask having a bit that corresponds to the architectural register, a value of the bit configured to indicate if the architectural register is an object of a write instruction, of the first block of instructions, that is expected to execute on the first core; and control circuitry configured to maintain the intra-core register rename map and the inter-core register rename map.