1. A processor, comprising: a resource scheduler including circuitry to assign alias resources to instructions within an atomic region of instructions, the atomic region including a plurality of reordered instructions; and a memory execution unit including circuitry to: identify an executed, unretired store operation from the atomic region in a memory ordered buffer; determine that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation; determine that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations; and determine that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.