1. A Reed-Solomon code generator comprising: first modulo 2 adder means supplied with an externally derived data word signal; a first register supplied with an output of said first modulo 2 adder means and first clock pulses, an output of said first register being fed to the first modulo 2 adder means, the first register being updated in response to every one of the first clock pulses to store a result of modulo 2 addition of the data word signal and data stored in the first register just before the arrival of each clock pulse of said first clock pulses; second modulo 2 adder means supplied with the data word signal which is received simultaneously by the first modulo 2 adder means; first .alpha. multiplier means for multiplying an output of said second modulo 2 adder means supplied thereto by a primitive root .alpha. of a predetermined generating polynomial; and a second register supplied with an output of said first .alpha. multiplier means and second clock pulses, an output of said second register being supplied to the second modulo 2 adder means, the second register being updated in response to every one of the second clock pulses to store a product of the primitive root .alpha. and a result of modulo 2 addition of the data word signal and data stored in the second register just before the arrival of each clock pulse of said second clock pulses, which is provided by the first .alpha. multiplier means.