1. An integrated circuit including a field programmable gate array (FPGA) which includes a programmable function unit (PFU), the programmable function unit comprising: an input line; an output line; and a programmable element for generating at least first and second functions in response to a configuration bit stream, in which the input line provides a control line to the programmable element when the first function is generated, and the input line provides a data line to the programmable element when the second function is generated; and wherein the programmable element is a look-up table.