1. A processor comprising: a register file comprising a plurality of registers; and a processing core to: execute a first instruction from a primary thread that has read and write access to the plurality of registers during a first execution mode of the processor; and execute a second instruction that: creates a secondary mini-thread associated with a first subset of the plurality of registers, and associates the primary thread with a second subset of the plurality of registers, wherein the primary thread operates as a primary mini-thread during a second execution mode of the processor, wherein the primary mini-thread is user-level code that has read and write access to the second subset and cannot modify registers not in the second subset, and wherein the secondary mini-thread is user-level code that has read and write access to the first subset and cannot modify registers not in the first subset.