1. A superscalar microprocessor for executing instructions having a prescribed program order, comprising: a decoder for decoding instructions; an instruction storage unit for storing a plurality of pending instructions that have been decoded by said decoder but are not executed; a plurality of functional units for executing at least one instruction regardless of the prescribed program order; an execution result buffer for storing the execution results from said plurality of functional units; a register array; a selection unit for selecting said register array to store execution results of instructions capable of retiring upon completion and for selecting said execution result buffer for temporarily storing executions results of instructions not capable of retiring upon completion; a rename unit for selecting a register entry to be used by each pending instruction among said execution result buffer and said register array, and N units (N an even number) of single word registers in said execution result buffer, wherein said rename unit can use said N units of single word registers as N/2 units of double word registers.