1. A multi-port memory device comprising: a plurality of memory banks; a clock distribution network for distributing a system clock signal and a port clock signal within the memory device, the system clock signal having a signal clock frequency and the port clock signal having a port clock frequency; and a plurality of ports connected to the clock distribution network and providing access to the plurality of memory banks, wherein the system clock signal and the port clock signal are applied to each of the plurality of ports, and wherein each of the plurality of ports includes an associated clock divider circuit that receives the port clock signal and uses the port clock signal to generate a local port clock signal for the respective port at a local port clock frequency, the local port clock signal being utilized by the associated port to operate at the local port clock frequency; wherein each of the ports includes a physical layer, the physical layer of each port including a first portion that operates at the local port clock frequency and a second portion that operates at the system clock frequency.