1. A processor comprising: a plurality of execution cores, each including a local storage to store a last monitored address for each of a plurality of execution threads when the execution thread is to issue a monitor request; and a distributed cache having a plurality of distributed cache portions, each cache portion to store data corresponding to an address of a memory storage location, the cache portion also including state storage to store monitor requests and associated states, and wherein responsive to receipt of a monitor request for the address from an execution thread, the cache portion is to store the address and to record in the state storage the monitor request for the execution thread and an associated speculative state for a monitor state machine of the cache portion for the execution thread, and to transition the monitor state machine from an idle state to the speculative state; further responsive to receipt of an mwait request from the execution thread for the address prior to issuance of a clear request or a monitor request for a second address, to record in the state storage the mwait request for the execution thread and an associated wait-to-trigger state for the monitor state machine, and to transition the monitor state machine from the speculative state to the wait-to-trigger state, and then to send a monitor-wake event to the execution thread responsive to receipt of a write request that matches the address while the monitor state machine is in the wait-to-trigger state and to record in the state storage the idle state for the monitor state machine; and responsive to receipt of the monitor request for the second address from the execution thread while the monitor state machine is in the speculative state, the cache portion is to store the second address and to transition the monitor state machine to be maintained in the speculative state, and responsive to receipt of a write request for the second address while the monitor state machine is in the speculative state and the second address is stored in the cache portion to transition the monitor state machine to the idle state.