1. In an instruction handling unit for a data processing system handling variable field length (VFL) instructions with a source (SRC) operand address and a destination (DST) operand address, the instruction handling unit having an operand fetch system comprising: a plurality of address operand pairs (AOPs), each AOP haing a subline request register and a subline buffer register, duplicate AOP assignment control means for normally initiating the selection of two non-busy AOPs for receiving an aligned first subline to be fetched using the SRC operand address when end-around byte shifting is indicated for SRC operand alignment, one subline detecting means for detecting that all shifted bytes in said fetched (s) for the SRC operand will occupy only one subline in the DST operand and providing a one subline control output in response thereto, means for connecting the one subline control output to the duplicate AOP assignment control means to inhibit a duplicate fetch initiation signal from being provided by the duplicate AOP assignment controls, whereby the inhibiting of the AOP assignment control means from providing the duplicate fetch initiation signal for an instruction causes an assignment of one SRC AOP to receive all bytes of the fetched SRC first subline.