1. A computer-implemented method for design analysis comprising: obtaining a set of constraints for a semiconductor circuit wherein one or more constraints from the set of constraints is defined over one or more variables; modeling the semiconductor circuit as part of a test bench wherein the test bench is modeled as a random process; solving the set of constraints by generating random values for the one or more variables within the test bench; using a subset of the one or more variables to determine a structure for a first constraint problem; monitoring information content for the subset of the one or more variables; evaluating changes in the information content for the subset of the one or more variables; caching into problem storage, the first constraint problem along with the information content for the subset of the one or more variables, based on the changes in the information content; iterating to a second constraint problem with a second subset of the set of constraints and a second subset of the one or more variables; searching through the problem storage to identify a previously cached constraint problem which matches the second constraint problem; and retrieving from the problem storage a structure corresponding to the second constraint problem to be solved.