1. A method for analyzing a layout related to a circuit on a semiconductor chip, comprising: receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes; wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy; modifying the design hierarchy to produce a modified design hierarchy by, examining a set of sibling nodes that are located under a parent node in the design hierarchy, identifying a set of interacting geometrical features between the set of sibling nodes, and moving the set of interacting geometrical features to a new child node under the parent node; and performing an analysis on the modified design hierarchy.