1. A method for integrated chip (IC) manufacturing within a lithography process, comprising: simulating formation of a layout pattern of the IC, within a lithographic simulation tool, under a first lithography condition comprising a set of parameters, wherein a value of each parameter is defined by a process model; randomly varying the value of a parameter of the first lithography condition within a range of values defined by its process model to create a second lithography condition; re-simulating the formation of the layout pattern under the second lithography condition; and repeating the random variation of values of parameters of the set of parameters to create additional lithography conditions, re-simulating each lithography condition until the value of each parameter has been substantially varied across a range of its respective process model by obtaining simulation results for values of the parameter that are within a predefined resolution, such that any value of a parameter sampled from its process model is within a predefined percentage of the range from another value of the parameter sampled from the process model.