1. A method for performing parallel processing of a computer code via a plurality of processors, the method comprising: (a) separating the computer code into a plurality of sequential stages, wherein each stage of the plurality of sequential stages comprises a respective portion of the computer code; (b) associating each stage of the plurality of sequential stages with a respective software thread, wherein each software thread is designated to execute on a respective processor of the plurality of processors; (c) for each stage of the plurality of sequential stages, when a respective stage includes software instructions for performing a data load having an expected latency exceeding a threshold: (i) modifying the respective portion of the computer code for a previous stage to perform a fill of data into a respective FIFO (“First In First Out”) buffer; (ii) modifying the respective portion of the computer code for the stage to drain data from the respective FIFO; (d) based upon processing information for the plurality of stages, coordinating the parallel processing of the plurality of processors by performing scheduling of each software thread as a function of a state of each of the respective FIFOs.