1. A method for optimizing a layout design based on a first gate-level design, comprising: (a) obtaining a placement of circuit elements of said gate-level design; (b) based on said placement, providing routing or routing estimates between circuit elements; (c) based on said routing or routing estimates, performing a timing analysis to provide estimates of interconnect delays between circuit elements; (d) performing a logic optimization operation to obtain a second gate-level logic design based on a cost function, said cost function being a function of said estimates of interconnect delays; (e) repeating (b)-(d) until said cost function is less than a predetermined value.