1. A method for scan testing logic within an integrated circuit, the method comprising: shifting input test data into multiple input-side scan chains in parallel, wherein at least two input-side scan chains are on different levels of a pipeline; applying the input test data from the multiple input-side scan chains to the logic under test; capturing output test data from the logic under test into multiple output-side scan chains, wherein at least two output-side scan chains are on different levels of the pipeline, the output test data being the result of the input test data being applied to the logic under test; and shifting the output test data out from the multiple output-side scan chains in parallel.