1. A self-aligned coding process for mask ROM, comprising the steps of: providing a substrate having a plurality of bit-lines formed therein, a gate oxide layer formed on said bit-lines, and a plurality of word-lines formed on said gate oxide layer, which together define an array of memory cells; forming a barrier layer on said word-lines; forming a silicon dioxide layer on said gate oxide layer between said word-lines by using liquid phase deposition, wherein the thickness of said silicon dioxide layer is larger than that of said word-lines; removing said barrier layer so as to define trenches in said silicon dioxide layer; forming a mask layer on said substrate exposing parts of said memory cells that will be programmed; and implanting impurities into said substrate not covered by said mask layer and said silicon dioxide layer whereby said memory cells that are programmed operate in a first state and other non-programmed memory cells operate in a second state.