1. A method for managing instruction flow in an SMT processor having a shared dispatch pipeline comprising the steps of: detecting an imbalance in a dispatch of instructions of a first thread compared to dispatch of instructions of a second thread relative to their respective thread priority; determining if said imbalance is because a selected thread of said first or second has excessive use of a shared resource; and issuing a dispatch flush for instructions of said selected thread in said shared dispatch pipeline when said selected thread has excessive used of a shared resource.