1. A method of verifying timing of a circuit using a timing verification tool, comprising: identifying failing paths and false paths of the circuit; formulating a linear programming problem for path delays satisfying timing constraints for all of the failing paths; identifying a first clock period that fixes timing for all of the failing paths; and using the first clock period as an upper bound and an original clock period as a lower bound, performing a binary search to find a minimum clock period with all of the timing constraints being satisfied; filtering out the false paths from the circuit; and determining maximum operating frequency of the circuit with the false paths filtered out, wherein an inverse of the minimum clock period is the maximum operating frequency.