1. A method of encoding an error correction code, comprising steps of: computing an intermediate parity bits vector from a message bits vector using a sub-matrix of a parity check matrix; and computing a parity bits vector from the intermediate parity bits vector using fixed hardware resources comprising logic gate trees that are configured to compute parity bits for multiple different codes and wherein an arrangement for the hardware resources is determined from a common sub-expression solution such that portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.