1. A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions, the method comprising: partitioning the plurality of physical register files into a first set of register files having a fixed one-to-one mapping with a first set of logical registers in the architected state and into a second set of register files being mapped to a second set having multiple copies of logical registers in a non-architected state by a register-renaming unit; assigning an instruction tag to each of the plurality of instructions for tracking instruction dependencies; using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at an instruction dispatch or wake-up/issue time in order to reduce a number of the plurality of physical register files.