1. A processor comprising: a vector register comprising a plurality of data fields to store values of vector elements; a decode stage to decode a first instruction specifying: a destination operand, a size of the vector elements, a portion of the data fields, and a source operand; and an execution unit, responsive to the decoded first instruction, to: read a number of values from data fields of the size of the vector elements in the source operand; and store a result value in the destination operand specified by the first instruction, wherein the result value is computed from most common values read from the number of the values from the data fields of the source operand.