1. A method for detecting errors in hardware, the method comprising: running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction; periodically synchronizing the transaction on the cores throughout execution of the transaction; comparing results of the transaction on the cores; determining an error in one or more of the cores; and copying a thread of the transaction from a first core of the plurality of cores to one or more second cores of the plurality of cores before running the transaction on the plurality of cores, wherein the first core and the one or more second cores are components of a multi-core processor.