1. An electronically programmable gate array comprising a plurality of rows of logic cells, each row of logic cells includes alternating three-input cells of programmable gates and two-input cells of programmable gates, each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell, wherein each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials, and a plurality of sets of interconnect lines, one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable means connecting inputs and an output of each cell in a row of cells with either of two adjacent sets of interconnect lines, each electronically programmable means comprises a voltage alterable resistor.