1. A processor for performing the radix-N.sup.2 discrete Fourier transform (DFT) of a sequence of N.sup.2 input data values, where N represents a predetermined integer, comprising: means for providing a first sequence of N.sup.2 input data values in upper/lower address reversed order; a first radix-N DFT processor circuit for receiving said first sequence of N.sup.2 input data values, dividing said first sequence into N groups of N values each, and producing a second sequence of N groups of N transformed data values, wherein each group of transformed data values is the radix-N DFT of the corresponding group of N data values in the first sequence; a first circuit and a second circuit each having an input and an output, the input of the first circuit being connected to receive the second sequence from the first radix-N DFT circuit, output of the first circuit being connected to the input of the second circuit, and the output of the second circuit producing a third sequence; wherein one of said first and second circuits is a multiplier circuit for receiving a sequence of N.sup.2 data values and producing a sequence of N.sup.2 output data values, wherein each output data value equals the corresponding input data value multiplied by a weighting factor whose value is a predetermined function of the position of the data value in the sequence; and wherein the other one of said two circuits is a memory circuit for receiving a sequence of N.sup.2 data values and outputting the N.sup.2 data values in an upper/lower address reversed order; and a second radix-N DFT processor circuit for receiving the third sequence of N.sup.2 data values, dividing the third sequence into N groups of N values each, and producing a fourth sequence of N.sup.2 transformed data values having N groups of N values each, wherein each group of transformed data values is the radix-N DFT of the corresponding group of data values in the third sequence.