1. A method for performing, in a processor, a plurality of bit field extractions to populate a plurality of destination lanes via a single instruction, comprising: (a) reading a plurality of bit field sizes, one bit field size per destination lane; (b) reading a plurality of bit fields from a source reservoir of bits, one bit field per destination lane, wherein the number of bits in each bit field is determined by the bit field size of its respective destination lane; and (c) writing each bit field into a respective one of the plurality of destination lanes.