1. A processor comprising: a plurality of cores including a first core, wherein the first core includes a first plurality of accumulator logics, each accumulator logic of the first plurality of accumulator logics to store corresponding first core telemetry data; and a power management unit (PMU) to request first core telemetry data from the first core and in response to receive at least one first core telemetry data stored in a corresponding accumulator logic of the first plurality of accumulator logics.