1. A method for performing equivalence checking between integrated circuit (IC) designs, comprising: receiving a first model of an IC design and a second model of the IC design for equivalence checking; converting the first model and the second model of the IC design into a first data-flow graph and a second data-flow graph, respectively; generating a combining structure by combining the first data-flow graph and the second data-flow graph, which involves: classifying the first data-flow graph to determine a first data-flow graph class; classifying the second data-flow graph to determine a second data-flow graph class; and selecting the combining structure based on the first data-flow graph class and the second data-flow graph class; and checking, by computer, if the first and second models of the IC design are equivalent by applying a formal analysis process to the first data-flow graph, the second data-flow graph, and the combining structure.