1. A programmable logic circuit, comprising: a first dedicated logic cell having a first logic and routing cell and a second logic and routing cell, the first logic and routing cell comprising a configurable logic function (LL) having at least one input and at least one output; and a sequential logic function (LS) having at least one input and at least one output, the at least one input of the sequential logic function coupled to the at least one output of the configurable logic function; wherein the configurable logic function structure comprises: a first look-up table having a plurality of inputs for receiving a set of inputs and at least one output; a second look-up table having a plurality of inputs for receiving the set of inputs and at least one output; a third look-up table having at least one input and at least one output; a fourth look-up table having at least one input and at least one output; and a 4-to-1 multiplexer having a first input coupled to the at least one output of the first look-up table, a second input coupled to the least one output of the second look-up table, a third input coupled to the least one output of the third look-up table, a fourth input coupled to the at least one output of the fourth look-up table, a first select pin or a fifth input pin, a second select pin or a sixth input pin, and an output.