1. A processor core, comprising: a plurality of dispatch queues for receiving instructions of a corresponding plurality of instruction streams; a plurality of parallel instruction execution slices for executing the corresponding plurality of instruction streams in parallel; a dispatch routing network for routing outputs of the plurality of dispatch queues to the plurality of parallel instruction execution slices; a dispatch control circuit that dispatches the instructions of the corresponding plurality of instruction streams via the dispatch routing network to issue queues of the plurality of parallel instruction execution slices; a mode control circuit, responsive to a mode control signal for reconfiguring a relationship between the plurality of parallel instruction execution slices such that in a first configuration corresponding to a first state of the mode control signal, at least two of the plurality of parallel instruction execution slices are independently operable for executing at least two of the corresponding plurality of instruction streams, and wherein in a second configuration corresponding to a second state of the mode control signal the at least two of the plurality of parallel instruction execution slices are linked for executing a single one of the corresponding plurality of instruction streams; a plurality of cache slices containing mutually-exclusive segments of a lowest-order level of cache memory; and a plurality of load-store slices coupling the plurality of cache slices to the plurality of parallel instruction execution slices, the plurality of load-store slices for executing load and store portions of execution corresponding to the instructions of the corresponding plurality of instruction streams and controlling access by the plurality of parallel instruction execution slices to the plurality of cache slices, wherein individual ones of the plurality of load-store slices are coupled to the at least two of the plurality of parallel instruction execution slices to exchange data with the at least two of the plurality of parallel instruction execution slices, independent of whether the at least two of the plurality of parallel instruction execution slices are in the first configuration or in the second configuration, and wherein the individual ones of the plurality of load-store slices are coupled to corresponding ones of the plurality of cache slices, whereby storage of the lowest-order level of cache memory is partitioned among the plurality of load-store slices, wherein the individual ones of the plurality of load-store slices manage access to a corresponding one of the plurality of cache slices, wherein the individual ones of the plurality of load-store slices include a load-store access queue that receives load and store operations corresponding to the load and store portions of the execution, a load reorder queue containing first entries for tracking load operations issued to a corresponding cache slice and a store reorder queue containing second entries for tracking store operations issued to the corresponding cache slice.