1. A computer implemented method for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations during a circuit design implemented by the computer, said method comprising: identifying one or more gates in the circuit design that are equivalent in all reachable states, wherein the one or more identified gates are equivalent gates; assigning equivalent gates to an equivalence class, wherein all gates within the equivalence class are equal; determining when one or more implication paths are associated with one or more equivalence classes; and outputting a circuit design implication for the one or more equivalence classes.