1. Apparatus for processing data comprising: processing circuitry configured to perform processing operations upon data values; and decoder circuitry coupled to said processing circuitry and configured to decode program instructions to generate control signals for controlling said processing circuitry to perform processing operations specified by said program instructions; wherein said decoder circuitry is responsive to an argument reduction instruction to generate control signals to control said processing circuitry to perform a processing operation upon a vector floating point value having a plurality of components, each of said plurality of components including an integer exponent value and a mantissa value, said processing operation including generating a plurality of result components, the processing operation comprising: for each of said plurality of components, forming a high order exponent portion E ho being an uppermost P bits of said integer exponent value, where P is less than a total number of bits within said integer exponent value, and selecting a highest value E homax from among said high order exponent portions E ho , wherein E homax identifies a highest integer exponent value B of said plurality of components; selecting an exponent shift value C such that (B+C) is less than a first predetermined value E dotmax and (B+C) is greater than a second predetermined value E dotmin , where said exponent shift value C is an integer value; and for each of said plurality of components, if said exponent shift value C is non-zero, then adding a value of (2 (P−1) −E homax ) to said high order exponent portion E ho to generate one of said plurality of result components.