1. A nonvolatile memory device comprising: a memory cell array comprising a first area, comprising a plurality of columns and rows which store bad block management information comprising a plurality of bits, and a second area which stores user data; a decoder configured to select at least one of the rows of the first area and the second area based on an address; a page buffer configured to store data in memory cells connected to the selected at least one row of the first area and the second area, or to detect data stored in the memory cells; and a control logic configured to control the decoder and the page buffer in response to a specific command, to access the first area, wherein a first bit among the plurality of bits is programmed into a first row and a first column, and a second bit among the plurality of bits, adjacent to the first bit, is programmed into the first row and a second column adjacent to the first column, wherein the first bit is programmed into a second row, adjacent to the first row, and the second column, and the second bit is programmed into the second row and a third column adjacent to the second column, and wherein the first bit is programmed into a third row, adjacent to the second row, and the third column, and the second bit is programmed into the third row and a fourth column adjacent to the third column.