1. A hardware accelerator module driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor, the hardware accelerator module comprising: a register interface block adapted to receive a parameter set from the system processor; an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by said parameter set, and to output the processed streaming data; and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the accelerator core as a function of a busy state received from the hardware accelerator core.