1. A method of interfacing a pipeline with two or more interfaces in a hardware processor, the method comprising: providing a single pipeline in a hardware processor, the single pipeline presenting at least two visible units, the single pipeline including replicated architecturally visible structures belonging to each the visible units, shared logic resources shared among the replicated architecturally visible structures, and shared architecturally hidden structures shared among the visible units; receiving a request from one of a plurality of interfaces at one of the at least two visible units; tagging the request with an identifier based on the one of the at least two visible units that received the request; and processing the request in the single pipeline by propagating the request through the replicated architecturally visible structures of a respective one of the visible units that corresponds with the identifier as directed by the shared logic resources.