1. A computing machine including a main memory and employing conditional branch prediction comprising: a prediction random access memory coupled to the main memory for receiving a selected number of least significant bits of a previously written memory address; branch prediction logic for determining if a branch guess is in progress; generating a guess bit, if a branch is in progress, and producing a prediction based on the previously written memory address; operational code compression means for re-mapping all processor execution instruction files into compressed operational codes and embedding the guess bit into the compressed operational codes of lesser size than original operational codes included in the instruction files; and control logic means for interfacing between the main memory and an instruction execution read-only-memory to fetch execution instruction files from main memory, decode the instruction based on the compressed operational code including the embedded guess bit, and predict a conditional branch based on the previous written memory address and the guess bit wherein the read-only-memory is reduced in size due to the compressed operational codes including the embedded guess bit and the computing machine is improved in performance.