1. A computer-implemented process comprising: (a) receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance; (b) associating a pre-placement model with each named memory type in the list; (c) mapping the design memories in the list to a circuit layout pattern, wherein at least one type comprises first and second instances that are mapped differently from one another; (d) after step (c), renaming at least one of the first and second instances to have a different name than the other; and (e) associating a post-placement model with each named memory type in the list, including a separate model for each renamed design memory.