1. A semiconductor device, comprising: a first test group operation unit configured to be locally reset and enter a test operation mode when a test entry code designates a first given value and selectively perform a plurality of first test operations in response to a test selection code; and a second test group operation unit configured to be locally reset and enter the test operation mode when the test entry code designates a second given value and selectively perform a plurality of second test operations in response to the test selection code, wherein the first and second test group operation units are reset in response to a global test reset signal, respectively, before the entering of the test operation mode.