1. A decoder, comprising: variable-node circuitry and check-node circuitry, which are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that comprises L-by-L sub-matrices, L denoting a positive integer that defines a dimensionality of the sub-matrices, wherein the variable-node circuitry and the check-node circuitry are further configured to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC; and a Message Passing (MP) module, which comprises multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0. .. L−1, L denoting the positive integer that defines the dimensionality of the sub-matrices, wherein the MP module is configured to schedule the variable-node circuitry and the check-node circuitry in accordance with a respective sub-matrix to exchange L messages simultaneously, by assigning a given partial cyclic shifter to shift the L messages cyclically by a shift value that is supported by the given partial cyclic shifter and depends on a structure of the respective sub-matrix.