1. A data processing apparatus comprising: a plurality of parallel lanes for parallel processing of sets of threads, each lane comprising a plurality of pipelined stages, said pipelined stages of each lane being operable to process instructions from said sets of threads; and scheduling logic operable to schedule instructions for processing by said lanes, said scheduling logic being operable to identify that one of said sets of threads being processed is to be split into a plurality of sub-sets of threads and to schedule at least two of said plurality of sub-sets of threads for processing by different pipelined stages concurrently, wherein said scheduling logic is operable to identify that a possible divergence in an instruction pointer value may occur which is identified by a divergence indicator within a thread included within said identified set of threads and to perform an adjustment of a reconvergence counter for said set of threads from an initial value on an occurrence of said divergence indicator.