1. A memory system comprising: a volatile memory subsystem; a non-volatile memory subsystem; a controller coupled to the non-volatile memory subsystem; and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system, wherein: in a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system, and in a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.