1. One or more integrated circuits (ICs) comprising: controller circuitry to: receive a command to execute an operation for a plurality of data inputs stored in an external memory or a local memory; and convert the operation into a set of matrix operations to operate on sub-portions of the plurality of data inputs; and at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include: arithmetic logic units (ALUs); a local memory external to the ALUs and accessible by the ALUs; and processing control circuitry to: create at least one matrix operand in the local memory from the plurality of data inputs of the operation, the at least one matrix operand comprising at least one of a scalar, a vector, or a two-dimensional (2D) matrix; and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing one of the matrix operations.