1. A method of data processing in a processor core including a store-through upper level cache, an instruction execution unit, and a core reservation flag, the method comprising: responsive to the processor core executing a load-reserve instruction that binds to a load target address held in the store-through upper level cache: the processor core setting the core reservation flag; the processor core transmitting a load-reserve operation to a store-in lower level cache that records a reservation in the store-in lower level cache for the load target address; the processor core tracking, during a core reservation tracking interval, the reservation requested by load-reserve operation until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the reservation; responsive to receipt during the core reservation tracking interval of an invalidation signal indicating presence of a conflicting snooped operation, the processor core cancelling the reservation by resetting the core reservation flag and failing a subsequent store-conditional operation; and responsive to not canceling the reservation during the core reservation tracking interval, the processor core determining whether a store-conditional operation succeeds by reference to a pass/fail indication provided by the store-in lower level cache.