1. A processor comprising: a first core including a first level one cache and a second core including a second level one cache, the first core to enter a plurality of low power modes, including but not limited to: a first low power mode, wherein one or more clocks for the first core is to be halted while maintaining power to the first core in response to the first core entering the first low power mode, and a second low power mode, wherein upon entering the second low power mode data from the first level one cache is to be stored to a level two cache and the first core is powered down while power to other portions of the processor are maintained; and a third low power mode, wherein upon an entry into the third low power mode, data from the first level one cache is to be stored to a level two cache and the processor, including the first core, is powered down.