1. A Fast Fourier Transform, FFT, circuit comprising: a pipeline in which L number of butterfly operational elements each having Single-path Delay Feedback, SDF, architecture are connected with each other, wherein the L number of butterfly operational elements include LHF number of first butterfly operational elements corresponding to a first stage to an LHFth stage, and LHS number of second butterfly operational elements corresponding to a (LHF+1)th stage to an Lth stage, where LHF+LHS=L, and each of the LHF number of first butterfly operational elements is configured to rearrange output data order such that, in units of N/(2 S−1 )pieces of output data starring from head output data whose Data Flow Graph, DFG, index i is “ 0 ”, intermediate result data G S (i) whose b S (i) is 1 is output after intermediate result data G S (i) whose b S (i) is G in the N/(2 S−1 ) pieces of the output data, where N represents the number of FFT points, S represents an integer indicating a stage number equal to or snore than 1 and equal to or less than LHF, and b S (i) represents the Sth bit from the least significant bit in binary representation of the DFG index i.