1. A single chip device for digital signal processing comprising: A. data bonding pads; B. a data bus coupled to the data bonding pads; C. a program bus separate from the data bus and coupled to the data bonding pads; D. address bonding pads separate from the data bonding pads; E. a program address bus separate from the data bus and separate from the program bus and the program address bus being coupled to the address bonding pads; F. a data address bus separate from the data bus, separate from the program bus and separate from the program address bus; G. data memory coupled to the data address bus and coupled to the data bus; H. program memory coupled to the program address bus and coupled to the program bus; and I. multiplier circuitry and ALU circuitry coupled together and to the data bus.