1. An integrated circuit device comprising: a first processor core; a first target state register coupled to the first processor core having a trace data portion for instructions executed by the first processor core and a marker data portion; a second processor core coupled to the first processor core; a second target state register coupled to the second processor core having a trace data portion for instructions executed by the second processor core and marker data portion; and a time stamp register containing marker data coupled to the marker data portion of the first target state register and to the marker data portion of the second target state register, in which (i) one of the first or second processor cores periodically updates the marker data in the time stamp register; (ii) the time stamp register is a hardware register accessible to both the first and second processor cores; (iii) including time stamp driver circuitry coupled to the time stamp register and periodically updating the marker data in the time stamp register; and iv) the time stamp register is part of the shared memory external to the first core processor and second core processor.