1. A cache controller structure for managing cache access for a computer system, comprising: (a) a processor having a direction flag, said processor configured to run a repetitive string operation wherein the string operation is configured to sequentially access a targeted memory block for each repetition depending on the state of the direction flag; (b) a cache interfaced with said processor, said cache comprising a plurality of cache lines for accessing system memory data blocks, wherein each cache line comprises a sequential group of data blocks; (c) a system memory in communication with said cache and said processor, the system memory comprising a plurality of sequentially ordered data blocks; and (d) a cache controller logic element in communication with said processor and said cache, said cache controller logic configured to control access to the cache by said processor; wherein said cache controller logic is configured to manipulate the cache lines in said cache responsive to the direction flag and to a position of a targeted memory block within a cache line.