1. A nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of two-terminal or three-terminal structured nonvolatile memory cells are arranged in a row direction and a column direction, first terminals of the plurality of memory cells arranged in a same row are connected to a common word line, and second terminals of the plurality of memory cells arranged in a same column are connected to a common bit line; a word line selection circuit adapted to select a predetermined number of word lines from a plurality of word lines; a bit line selection circuit adapted to select a predetermined number of bit lines from a plurality of bit lines; and a plurality of load resistive characteristic variable circuits connected to the respective bit lines, wherein each of the memory cells has a variable resistive element having two terminals, the variable resistive element is configured such that resistive characteristics defined by current-voltage characteristics between the two terminals can transit between two stable resistive characteristics of a low resistance state and a high resistance state when a voltage is applied from one terminal to the other terminal with at least one of positive and negative polarities, a first threshold voltage as a lower limit value of an absolute value of an applied voltage required for the resistive characteristics to transit from the low resistance state to the high resistance state is lower than a second threshold voltage as a lower limit value of an absolute value of an applied voltage required for the resistive characteristics to transit from the high resistance state to the low resistance state, and storage state of the variable resistive element is determined based on whether the resistive characteristics of the variable resistive element are the low resistance state or the high resistance state, each of the load resistive characteristic variable circuits has two different load resistive characteristics defined by the current-voltage characteristics and is configured to select one of the two load resistive characteristics individually based on whether a first writing operation is performed or a second writing operation is performed, the first writing operation having the resistive characteristics of the variable resistive element to be written transit from the low resistance state to the high resistance state, the second writing operation having the resistive characteristics of the variable resistive element to be written transit from the high resistance state to the low resistance state, and a writing voltage pulse application circuit is provided to apply a first voltage pulse to be applied in the first writing operation and a second voltage pulse to be applied in the second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit lines.