1. A method for operating a digital processor that includes a memory, a program sequencer and an execution unit, comprising: storing instructions of a code sequence in the memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence.