1. An integrated circuit (IC) fabrication method to form an IC structure on a substrate having one or more through silicon via (TSV) features, comprising: performing a plurality of processing steps including via etching, grinding, and recessing; collecting physical metrology data from the plurality of processing steps, the physical metrology data including: a first thickness of the substrate; a first height of the one or more TSV features associated with the via etching; a second thickness of the substrate associated with the grinding; a second height of the one or more TSV features determined as a lesser one of the second thickness and the first height; a third thickness of the substrate associated with the recessing; and a third height of the one or more TSV features associated with the recessing; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.