1. A memory device, comprising: an integrated circuit substrate; a plurality of stacks of conductive strips, the stacks being ridge-shaped and including at least two conductive strips separated by insulating material; a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining an multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and conductive lines; and memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of conductive strips and the plurality of conductive lines.