1. An instruction execution control device for executing a plurality of threads including a plurality of instructions, comprising: an instruction decoder that decodes an instruction; a reservation station that receives a decoding result from the instruction decoder, and controls computing processing; a main storage reservation station which controls the generation of an address of an operand to be stored in a main storage; an instruction control mechanism which controls executed instructions so that the instructions are completed according to the sequence of a program; and a hang prevention circuit which, when the instruction control mechanism detects that an instruction in one thread cannot be completed in a predetermined period, selects a thread of an entry that can be executed from all of the reservation stations to be the same as the thread of which incompletion in the predetermined period has been detected.