1. An integrated circuit, comprising: a floating-point adder that receives first and second numbers, each having a mantissa and an exponent, wherein the floating-point adder comprises: a mantissa alignment circuit; and an addition circuit, wherein the mantissa alignment circuit and the addition circuit are operable in a first mode that supports a first mantissa size and are also operable in a second mode that supports a second mantissa size that is different than the first mantissa size.