1. A processor, comprising: a first translation look-aside buffer to support a guest operating mode; a second translation look-aside buffer to support a root operating mode; and hardware resources supporting the guest operating mode controlled by guest mode control registers defining guest context, wherein the guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address, and the hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.