1. An apparatus for executing an atomic memory transaction comprising a plurality of speculative memory access operations as a single atomic transaction, said apparatus comprising: a data cache configured to buffer data accessed at respective locations in a shared memory by respective ones of the plurality of speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction, wherein the shared memory is shared by a plurality of processing cores; an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction; and a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.