1. A method, in a data processing system, for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design, comprising: receiving an abstracted netlist corresponding to an original netlist of the integrated circuit design; determining elements already present in the abstracted netlist; refining the abstracted netlist by expanding the abstracted netlist to include additional elements that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist; and utilizing the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design.