1. A method for design simulation, comprising: partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE; computing an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device, such that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device; executing the PEs on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result; and verifying a performance of the design responsively to the simulation result.