1. A data processing apparatus comprising: pre-decoding circuitry for receiving a sequence of instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions; a cache for storing the pre-decoded instructions for access by a processing circuitry, said processing circuitry for executing said sequence of instructions, the processing circuitry having a plurality of processor states, each processor state having a different instruction set associated therewith; the pre-decoding circuitry performing the pre-decoding operation assuming a speculative processor state, and the cache being arranged to store an indication of the speculative processor state in association with the pre-decoded instructions; the processing circuitry configured only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache in association with that corresponding pre-decoded instruction, wherein, when the processing circuitry issues an access request specifying an address of an instruction in the sequence, the cache performs a lookup operation to determine whether the corresponding pre-decoded instruction is present in the cache and further to determine whether the current processor state matches the speculative processor state and, if the lookup operation identifies that the corresponding pre-decoded instruction is in the cache but the current processor state does not match the speculative processor state stored in the cache in association with that corresponding pre-decoded instruction, the cache generates a miss condition causing a linefill operation to be performed to re-fetch from the memory the instruction which is the subject of the access request, and wherein the cache is an n-way set associative cache, and, when the instruction which is the subject of the access request is re-fetched from the memory, the cache causes the corresponding pre-decoded instruction output by the pre-decoding circuitry to be allocated to a different way of the cache than the way storing the corresponding pre-decoded instruction that gave rise to the miss condition.