1. A multithreaded processor for processing a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor, comprising: an instruction queue for queuing instructions into a plurality of threads associated with said plurality of processor pipelines issue logic associated with said instruction queue for receiving said plurality of threads and comprising thread switching logic for predetermining at least one triggering event causing the multithreaded processor to switch from a first thread to a second thread, said triggering event being variably and dynamically determined to optimize performance of the multithreaded processor; an execution data path for processing a first set of instructions from a first thread until the occurrence of said triggering event; said thread switching logic further for switching the multithreaded processor in processing from the first thread to processing from a second thread upon the occurrence of said triggering event; said execution data path further for processing a second set of instructions from the second thread until the occurrence of said triggering event; and said thread switching logic further for switching the multithreaded processor in processing from the second thread to processing from a next thread upon the occurrence of said triggering event.