1. A computer implemented method for performing semiconductor failure analysis comprising: having a set of rules wherein each rule of the set of rules describes a design rule check for a semiconductor layout; selecting a rule from the set of rules to apply to the semiconductor layout wherein the rule describes a two-dimensional Boolean operation on shapes where the rule further describes shapes of one or more layers and shapes of potential defects derived from defect scanning tools or yield managements systems, wherein the Boolean operation on shapes further includes shapes of electrical traces identified from electrical analysis of a netlist representing circuitry in the semiconductor layout; identifying a portion of the semiconductor layout by searching through the semiconductor layout for a match to the rule which was selected; and displaying the portion of the semiconductor layout.