1. A processor for decoding an instruction and executing said decoded instruction, comprising: a flag register in which a plurality of conditional execution flags are stored, said plurality of conditional execution flags being used as predicates for conditional execution instructions; a decoding unit operable to decode an instruction; and an execution unit operable to execute the instruction decoded by the decoding unit, wherein when the instruction decoded by the decoding unit is a loop instruction, an iteration of a loop to be executed terminates in the execution unit, based on a value of one of the plurality of conditional execution flags for an epilog phase in the loop in a case where said loop is unrolled into the conditional execution instructions by means of software pipelining.