1. A circuit arrangement, comprising: a processing unit including issue logic and an execution unit, the issue logic configured to issue instructions from at least one instruction stream to the execution unit, the execution unit including a register file within which is stored operand data, and the execution unit configured to execute the instructions issued to the execution unit by the issue logic, wherein at least a portion of the instructions executed by the execution unit manipulate the operand data stored in the register file; and control logic coupled to the execution unit and configured to utilize at least a portion of the register file as a local instruction loop buffer, wherein the control logic is configured to cause instructions stored in the register file of the execution unit to be executed by the execution unit.