1. A method for increasing the address range of a cache system having a cache memory comprised of a plurality of cache entries, said method comprising the steps of: providing a plurality of cache tag field memory locations corresponding to each cache entry, each cache tag field memory location having a plurality of bits comprising address bits and at least one programmable bit; storing a portion of address data in said address bits; and programming said programmable bit with another portion of said address data to provide an additional address bit.