1. Logic element circuitry comprising: first combinational logic circuitry consisting of one one-input look-up table circuit having an input and two two-input NAND gates, wherein each of the NAND gates has an output; and programmable interconnection circuitry for selectively conveying signals to, from, and between the look-up table circuit and the NAND gates, wherein the programmable interconnection circuitry is configured to selectively couple each of the outputs of the NAND gates to the input of the look-up table circuit.