1. A programmable logic device (PLD), comprising: a plurality of programmable logic blocks (PLBs); and at least first and second logic cells within at least one of the plurality of PLBs, each logic cell comprising a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT, wherein: the associated mode logic is configured to use a single physical output port to provide a logic cell output signal from its respective logic cell corresponding to an operational mode selected from a logic function operational mode, a ripple arithmetic operational mode, and an extended logic function operational mode; when the selected operational mode for the first logic cell comprises the logic function operational mode, the associated mode logic for the first logic cell is configured to provide the LUT output signal of the first logic cell as the logic cell output signal on the single physical output port; and when the selected operational mode for the first logic cell comprises the extended logic function operational mode, the associated mode logic for the first logic cell is configured to: multiplex the LUT output signal of the first logic cell and the LUT output signal of the second logic cell, and provide the multiplexed signal as a first logic cell output signal on the single physical output port of the first logic cell and to an input of the second logic cell.