1. A processor core comprising: a shared memory having a plurality of addressable storage locations; a plurality of processing engines each adapted to execute a different thread of a group of threads in parallel, each thread of the group of threads including at least one instruction that, when executed, results in an access to a target one of the addressable storage locations in the shared memory; and an interconnect circuit coupling the plurality of processing engines to the shared memory such that any one of the addressable storage locations in the shared memory is readable and writeable by any one of the processing engines, wherein the interconnect circuit is adapted such that first data read from the shared memory by a selected one of the processing engines and second data written to the shared memory by the selected one of the processing engines is transferred through at least a portion of the interconnect circuit in a same direction during both read operations and write operations.