1. A hybrid programmable logic device, comprising: transceivers that receive data packets, wherein the data packets comprise header data and payload data; programmable logic elements, wherein a first portion of the programmable logic elements provide hardware acceleration functions; processors interleaved with the programmable logic elements, wherein each of the processors process the received header data using the hardware acceleration functions and processing threads, and a second portion of the programmable logic elements schedule the distribution of header data to the processing threads.