1. A processing system that executes multiple instruction contexts comprising: an instruction memory for storing instructions that are executed by the system; a processor unit for executing instructions in a pipelined fashion; a plurality of context registers for storing instructions and instruction addresses for contexts awaiting execution; and fetch logic for selecting an address from one of said plurality of context registers and for selecting an instruction from a second of said plurality of context registers for execution by said processor unit, with the fetch logic selecting the address and the instruction substantially simultaneously for each cycle of execution of said processor unit.