1. A microprocessor having architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising: a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the operation on the source operands to generate the result; wherein in response to the second microinstruction, the execution pipeline: writes the destination register with the result generated by the first microinstruction, if the architectural condition flags satisfy the condition; and writes the destination register with the current value of the destination register, if the architectural condition flags do not satisfy the condition.