1. A processor comprising: a plurality of thread execution units that each executes a thread including a plurality of instructions and each provided with a performance analysis circuit that measures an event resulting from executed instructions and a commit stack entry unit that controls completion of the executed instructions; a commit scope register that stores an instruction of completion candidates stored in the commit stack entry unit of each of the plurality of thread execution units and performs completion processing for the executed instructions included in the thread when each of the plurality of thread execution units completes the executed instructions; a thread selecting unit that selects one of the plurality of thread execution units and sends instruction completion events of the completed instructions to a performance analysis circuit provided for the selected thread execution unit corresponding to the completed instructions when the commit scope register performs completion processing for the executed instructions stored in the commit scope register, sends an instruction incompletion event representing a failure of a completion of the executed instruction to a performance analysis circuit provided for the selected thread execution unit corresponding to the failed executed instruction when the selected thread execution unit failed to complete the executed instruction and the executed instruction is not stored in the commit scope register; and a plurality of cause registers, each provided for the plurality of thread execution units that holds a factor of the failure only when a first head instruction of an executed thread is not completed by the selected thread execution unit, wherein the thread selecting unit simultaneously sends a first event of a first factor stored in a first cause register corresponding to the selected thread execution unit due to which another head instruction of another thread including an instruction of completion candidate stored in the commit scope register cannot be completed and a second event of a second factor stored in a second cause register corresponding to an unselected thread execution unit to the performance analysis circuit provided for each of the plurality of thread execution units.