1. A field programmable gate array (FPGA) having a dedicated random access memory (RAM) and a RAM decoder, the RAM decoder comprising: a logic gate for providing a decoder output signal to an enable input terminal of the dedicated RAM, wherein the dedicated RAM is enabled and disabled in response to the decoder output signal; a plurality of multiplexers, each having an output terminal coupled to an input terminal of the logic gate, and each having a control terminal coupled to receive a corresponding enable signal; and a plurality of decoder programming lines coupled to provide input signals to the multiplexers, wherein each of the multiplexers is coupled to a corresponding set of the decoder programming lines.