1. A processor comprising: a hardware decoder to decode a secure enter instruction; control logic to find a first entry corresponding to the processor in a match table in a master authenticated code module, the first entry to indicate a first correspondence between the processor and a first individual authenticated code module, the match table also including a second entry to indicate a second correspondence between an other processor and a second individual authenticated code module, the master authenticated code module including the match table, a master header, and the first and the second individual authenticated code modules, the control logic also to, in response to decoding the secure enter instruction and finding the first entry in the match table and using the first entry to identify the first individual authenticated code module in the master authenticated code module, read the master header and the first individual authenticated code module from the master authenticated code module, wherein the second individual authenticated code module is to be read from the master authenticated code module in response to the other processor decoding the secure enter instruction and finding the second entry in the match table and using the second entry to identify the second individual authenticated code module in the master authenticated code module.