1. A data processing device comprising: a set associative type cache memory which stores cache entries in a plurality of ways, wherein when reading cache tags, the cache memory selects, from among the plurality of ways, part of the ways according to a value of select data created based on tag address information which is part of address information, and reads cache tags from the selected ways by use of an index address in the address information, and when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways according to the value of the select data, wherein the cache memory has an LRU data array for storing LRU data used as an index to identify a cache entry targeted for a cache fill by a pseudo LRU when deciding a cache entry to perform cache fill on, the LRU data array has a region for storing history data of more than one bit showing, for reach index address to a cache entry, a history of use of each group of part of the ways selected according to select data, and the cache memory selects a cache entry to perform cache fill on based on the history data read from an LRU data array by use of index address information, and corresponding select data.