1. A charge coupled A/D system including a plurality of pipelined charge processing stages for performing successive approximations on a reference analog charge Q.sub.r and an input signal charge Q.sub.s wherein: each of said pipelined charge processing stages are coupled only to directly adjacent stages for propagation of reference and input signal charges, each said pipelined charge processing stage includes charge processing means, including comparator means, for performing an inequality function, said plurality of pipelined charge processing stages providing a bit string b.sub.1 through b.sub.N representing a digital representation of said input analog signal charge Q.sub.s ; which includes a different stage for each bit, b.sub.1 through b.sub.N, of said digital representation an in which each stage, other than an initial and final stage comprise: charge splitter means subjected to an input charge packet Qi for delivering, on separate charge transfer paths, a pair of charge packets Qi/2; a pair of commonly controlled charge switching means, each with a charge input and a pair of outputs, each said charge switching means connected to receive a one of said charge packets Qi/2; a single electrode and means coupling an output of each of said charge switching means to said electrode; and a pair of field gate means for generating input voltages for said comparator means each coupled to other outputs of said charge switching means; and means for controlling said charge switching means whereby a charge packet Qi/2 is input to one or another of said field gate means regardless of a condition of said charge switching means.