1. An information processing device comprising: an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed; an order generation section that generates order information indicating a generation order of the writing operation; and a write control section that stores write information to the write address generated by the address generation section, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.