1. A random access memory device, comprising: a memory array of memory cells organized into rows and columns, including a plurality of word lines and column lines, each row of memory cells being coupled to a word line and each column of memory cells being coupled to a column line; sense amplifier circuitry coupled to the column lines; address decode circuitry for receiving an address value and asserting a row line associated therewith; and test circuitry, coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the random access memory device an electrical signal representative of the sensed voltage levels.