1. A data processing apparatus comprising: combined divide-square root circuitry to perform, in response to a divide instruction identifying a first operand A and a divisor D, a radix-N SRT division algorithm to generate a result value Q=A/D, and to perform, in response to a square root instruction identifying a second operand B, a radix-N SRT square root algorithm to obtain a result value Q=√{square root over (B)}, where N is an integer power of 2; wherein the SRT division algorithm and the SRT square root algorithm each comprise a plurality of iterations, each iteration for determining an updated remainder value R i based on a quotient value q i selected for that iteration in dependence on a previous remainder value R i−1 , the updated remainder value from one iteration becoming the previous remainder value for a following iteration, and the result value Q being derivable from the quotient values selected for the plurality of iterations; and the combined divide-square root circuitry comprises shared remainder updating circuitry to generate the updated remainder value for a greater number of iterations per processing cycle for the SRT division algorithm than for the SRT square root algorithm; wherein in the SRT square root algorithm, the i th iteration is for determining the updated remainder value R i based on the previous remainder value R i−1 , the quotient value q i and a partial result value Q i−1 corresponding to a combination of the quotient values selected in the preceding iterations; the partial result value Q i−1 is represented in signed-digit format; and the shared remainder updating circuitry comprises circuitry to perform a calculation for determining the updated remainder value R i with the partial result value Q i−1 remaining in the signed-digit format, when performing the SRT square root algorithm.