1. A method for post-route optimization of a plurality of objects in a region of an integrated circuit layout layer having two dimensions, comprising the steps of: selecting a first group of at least one object in the plurality in the region; using with a computer system an explicit formula to move the first group to an optimal position in a particular dimension of the two dimensions of the layer, the optimal position being a position in the particular dimension that minimizes a sum of an average critical area on a first side of the first group and an average critical area on a second side of the first group, the first and second sides being opposite each other in the particular dimension; and repeating the steps of selecting and using for all other objects in the plurality.