1. A method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design, comprising: traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis; and using a processor, generating the control and data flow graph by adding an execution unit to the control and data flow graph for each module having concurrent paths, each execution unit comprising nodes in the control and data flow graph, the nodes including a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths.