1. An apparatus comprising: a first device level including a first memory cell; a second device level stacked over the first device level, the second device level including a second memory cell, each of the first and second memory cells including a memory element and an access component coupled to the memory element, the access component includes a material, wherein the material excludes silicon; a first conductive line and a second conductive line coupled to the first memory cell, wherein the first conductive line is substantially perpendicular to the second conductive line; and a third conductive line and a fourth conductive line coupled to the second memory cell, wherein the third conductive line is substantially perpendicular to the fourth conductive line.