1. A method performed by an embedded port of a host bus adapter of a storage controller, the method comprising: receiving, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations; receiving one or more commands to resume selected I/O operations in the embedded port; receiving a second set of commands to quiesce I/O operations for a second period; and receiving a command to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations, wherein the one or more commands to resume selected I/O operations in the embedded port are received subsequent to configuration space registers of the buses and other logic being restored to a state prior to performing of the hardware resets, and wherein in response to receiving the first set of commands the embedded port performs: quiescing processing of received frames from a link; latching states of selected hardware inputs; completing active direct memory access into driver memory; deferring processing of link transitions; stopping all accesses to driver memory; and dequeing any messages to be sent to the driver.