1. A logic circuit generation device that receives a program in which an operation description, indicating a flow of a series of processes of hardware for a circuit design, is written using a procedural software programming language, the program including a top-level function of a logic circuit generation target, and generates a logic circuit description, the logic circuit generation device comprising: a processor, wherein the processor is configured to execute: a non-cyclical and non-hierarchical conversion process including: a full inline expansion process that, when the top-level function includes a function call instruction, subjects each function call instruction to inline expansion to convert the top-level function into a lowermost function including no function call instruction; and a full loop expansion process that, when the lowermost function converted by the full inline expansion process includes a loop processing part of a fixed repeat count, subjects each loop processing part of the fixed repeat count to loop expansion to convert the lowermost function into a non-cyclical type lowermost function including no loop processing part, a control flow graph generation process that generates a control flow graph from the top-level function; a control flow degeneration process that generates a control flow degenerated program that is a program having a control flow which is degenerated by removing all condition branch instructions from the control flow graph that includes, for each variable, a single assignment instruction to the each variable a data flow graph generation process that generates a data flow graph from the control flow degenerated program, by using each instruction in the control flow degenerated program as a node, and adding a directed edge from an assignment instruction to each variable to an instruction that refers to the variable; and a logic circuit description output process that generates the logic circuit description expressing a sequential circuit which has wiring of a logic circuit corresponding to the directed edge of the data flow graph, and a computing element of the logic circuit corresponding to the node of the data flow graph, wherein a program inputted into the logic circuit generation device is converted into a non-cyclical type lowermost function by the non-cyclical and non-hierarchical conversion process, and then is inputted into the control flow graph generation process, wherein the program inputted into the logic circuit generation device comprises a data flow lacking a timing definition among elements of the sequential circuit and includes a state variable expressing a state of the sequential circuit representing a local variable of a high-order hierarchy function calling the top-level function or a static variable, wherein the current state of the sequential circuit corresponds to a value reference of the state variable occurring before its assignment instruction, and wherein the next state of the sequential circuit corresponds to a value reference of the state variable occurring after its assignment instruction.