1. A neuro-chip which comprises: a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip; a broadcast bus connected to each of said neuron operation circuit means which broadcasts data between each of said neuron operation circuit means; a program data bus connected to each of said neuron operation circuit means which supplies a common program externally input to each of said neuron operation circuit means; and a pair of ring bus terminals connected to said connecting neuron operation circuit means, for transferring data among said connecting neuron operation circuit means of said neuro-chip and said other neuron operation circuit means which are not a part of said neuro-chip through a ring bus.