1. A data processing system, comprising: a plurality of processing units; a plurality of high level cache memories, wherein ones of said plurality of high level cache memories are associated with respective ones of said plurality of processing units; a lower level cache memory associated with said plurality of high level cache memories, wherein said lower level cache memory is imprecisely inclusive of said plurality of level one cache memories; a plurality of local invalidation buses connected between said lower level cache memory and said plurality of high level cache memories; and an imprecise inclusivity tracking means coupled to said lower level cache memory for tracking cache line inclusivity of said high level cache memories, wherein said imprecise inclusivity tracking means associates with lower lever cache lines last_processor_to_store information and more_than_two_loads information to selectively invalidate cache lines in said high level cache memories that shared identical information with a specific cache line, as identified by said last_processor_to_store information, within said lower level cache memory via said plurality of local invalidation buses.