1. An adder circuit comprising: a propagate and generate circuit stage to provide propagate signals and generate signals; a plurality of carry-merge stages to receive the propagate signals and the generate signals from the propagate and generate circuit stage, the plurality of carry-merge stages to provide carry signals based on the propagate signals and the generate signals received from the propagate and generate circuit stage; a conditional sum generator to receive the propagate signals and the generate signals from the propagate and generate circuit stage, the conditional sum generator to provide conditional sum signals based on the propagate signals and the generate signals received from the propagate and generate circuit stage, the conditional sum generator including ripple carry gates and logical exclusive OR (XOR) gates, the logical XOR gates being provided on different stages of the conditional sum generator; and a plurality of multiplexers to receive the carry signals from the carry-merge stages and to receive the conditional sum signals from the conditional sum generator, and each of the multiplexers to provide an output based on the corresponding received signals.