1. A method for translating instructions for a processor, comprising: accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch; building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch; assembling a guest instruction block from the instruction sequence; translating the guest instruction block to a corresponding native conversion block, wherein an at least one native far branch corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch; and upon encountering a missprediction, obtaining a correct instruction sequence by accessing the opposite guest address.