1. A processor comprising: a plurality of architectural registers of the processor, wherein the architectural registers are used by the processor to execute one or more instructions; a renaming module configured to rename one or more of the architectural registers to one or more physical registers in the processor in response to the processor receiving a plurality of instructions for execution; a memory comprising a first table configured to store pointers to the physical registers storing data generated in response to the processor completing execution of one or more instructions, and a second table configured to store pointers to the physical registers storing data to be (i) generated by a set of instructions received but not executed by the processor and (ii) used by instructions to be received by the processor; an execution module configured to execute the plurality of instructions, and discard one or more instructions from the set of instructions received but not executed by the processor in response to an event; and an updating module configured to update pointers in the second table in response to the event, wherein the updated pointers are generated based on (i) pointers stored in the first table at a time of occurrence of the event, and (ii) one or more instructions from the set of instructions not discarded by the execution module.