1. A method of performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode, the method comprising steps of: executing the mask bit compression instruction to determine which writemask bits of the source writemask register are to be written into the least significant bit positions of the destination writemask register, wherein each bit of the source and destination writemask registers is a writemask bit; and storing the determined writemask bits into the least significant bit positions of the destination writemask register.