1. A system, comprising: a first processorconfigured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code; wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode; wherein the first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block; and wherein the first processoris configured to determine that a first error occurred, if the determined error code is different from the stored error code; and a second processor, wherein the second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode; wherein the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.