1. A processor comprising: a branch scanner configured to scan predecode information corresponding to a plurality of instruction bytes fetched by said processor for execution, said predecode information including a boundary indication corresponding to each of said plurality of instruction bytes and a control transfer indication corresponding to said each of said plurality of instruction bytes, and wherein said branch scanner is configured to select an instruction byte from said plurality of instruction bytes, said instruction byte having a corresponding boundary indication indicating that said instruction byte is a boundary of an instruction and a corresponding control transfer indication indicating that said instruction is a control transfer instruction; and a prefetch control unit coupled to said branch scanner, wherein said prefetch control unit is configured to select a next fetch address from a plurality of addresses corresponding to a plurality of types of control transfer instructions, said prefetch control unit configured to receive said instruction byte and to decode a portion of said instruction byte, said portion indicative of which of said plurality of types corresponds to said instruction, and wherein said prefetch control unit is configured to select said next fetch address in response to decoding the portion.