1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions; and an optimizing compiler residing in the memory and executed by the at least one processor, the optimizing compiler including a strength reduction mechanism that performs the steps of: (A) generating a control flow graph of the computer program, the control flow graph comprising a plurality of basic blocks; (B) generating a dominator tree that represents which basic blocks in the control flow graph dominate other basic blocks in the control flow graph; (C) processing the instructions in the control flow graph in an order determined by the dominator tree to generate a candidate table of instructions with corresponding data; (D) selecting a root candidate from the candidate table; and (E) processing the candidate table of instructions to generate an increment table for the selected root candidate and related candidates in the candidate table.