1. A system for performing physical verification processing on an integrated circuit (IC) design, comprising: a parallel portion for distributed processing of the IC design, the parallel portion comprising a parallel queue manager to manage a first set of instructions for partitioning an IC design data of the IC design into a first IC design data, the first set of instructions based at least in part upon one or more design rules corresponding to the IC design; a multi-threaded portion for multi-threaded processing of the IC design, in which the multi-threaded portion comprises a multi-threaded queue manager which manages a second set of instructions associated with the IC design data partitioned for multi-threaded processing, wherein a subset of the second set of instructions for a subset of a second IC design data of the IC design originating with the multi-threaded portion is sent to the parallel queue manager of the parallel portion to be processed in parallel by a plurality of processing units; the plurality of processing units to process physical verification operations in parallel, the first set of instructions and the subset of the second set of instructions being processed by the plurality of processing units; a plurality of threads for performing multi-threaded processing of the IC design, the second set of instructions being processed by the plurality of threads, wherein the first IC design data and the subset of the second IC design data of the IC design are processed with the distributed processing, and the second IC design data of the IC design minus its subset is processed with the multi-thread processing; and a dispatcher for managing a job associated with the second IC design data, wherein the job originates in the multi-threaded portion and is redirected to be processed in the parallel portion such that the subset of the second IC design data is of the type to be processed with the multi-threaded processing but has been redirected to be processed by using the distributed processing.