1. A synchronous semiconductor memory device taking in control signals and external signals including address signals having bank addresses and input data in synchronization with a clock signal in a form of a series of pulses, comprising: a memory cell array including a plurality of memory cells, said memory cell array including a plurality of banks activated for memory cell selection independent from each other in accordance with the bank addresses included in the address signals, and one of the bank addresses designating one of the banks; a plurality of write data register means provided corresponding to each of said plurality of banks for storing write data to the corresponding bank; and a plurality of read register means provided corresponding to each of said plurality of banks for storing data read from the corresponding bank, wherein a data read or write operation is performed only for the one of the banks designated by the one of the bank addresses.