1. A memory device for storing one or more data bits, each of the one or more of the data bits is associated with a first logic state magnitude to represent a first logic state and a second logic state magnitude to represent a second logic state, the memory device comprising: a memory cell configured to store a first data bit; and a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude, the write access circuit configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.