1. A computing device for transactional memory execution, the computing device comprising: a cache memory to hold a cache line with a corresponding hardware transaction tracking field; and a processing element to: encounter, within a transaction, a transactional memory access to the cache line with the corresponding hardware transaction tracking field set to an un-accessed value indicating that the transaction has not previously accessed the cache line during its pendency; generate a transactional event in response to an encounter of the transactional memory access; determine an address from a storage element of the processing element associated with the transactional event; and perform an access barrier operation associated with the address, wherein the transactional memory access includes a transactional read, and wherein the access barrier operation associated with the address is selected from a group consisting of logging of the transactional read, acquisition of a lock for the address, and validation of a previous transactional read.