1. A processor comprising: a source vector register to store a plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate operand of an instruction; vector bit reversal circuitry to determine a bit group size from the immediate operand and to responsively reverse positions of contiguous bit groups within the source vector register to generate a set of reversed bit groups; and a destination vector register to store the reversed bit groups; wherein the vector bit reversal circuitry comprises one or more multiplexers to reverse the bit groups from the source vector register to the destination register in accordance with the immediate operand.