1. A method for statically analyzing timing of an electronic circuit design, the method comprising: reading a netlist of an electronic circuit design to determine a sequence of a plurality of logic gates coupled together between an input pin and an output pin by interconnect networks; generating a set of state-space equations for the sequence of the plurality of logic gates in response to a time varying linear gate model; solving the set of state space equations for the first logic gate of the sequence to determine a first vector representation of a voltage full waveform at an output of the first logic gate in the sequence; sequentially, next logic gate by next logic gate, determining coefficients for the time varying linear gate models in response to vector representations of voltage full waveforms at inputs of the time varying linear gate models and solving the set of state space equations with the coefficients to determine next vector representations of voltage full waveforms at outputs of the next logic gates in the sequence to efficiently propagate a substantially accurate response to the input voltage full waveform to the output pin as a last vector representation of a voltage full waveform at the output pin; and wherein one or more of the reading, the generating, the solving, and the sequentially determining are performed with a processor.