1. A cache control apparatus for one of a plurality of caches, respectively used by one of a plurality of processors for accessing a memory, for maintaining data coherency of the plurality of caches, each cache including an instruction cache and a tag memory, the apparatus comprising: a coherency controller including an MESI (modified exclusive shared invalid) register that is included in the instruction cache of the one cache, and is configured to store one of a modified state, an exclusive state, a shared state, and an invalid state for each cache line of the instruction cache; a coherency interface connected to the coherency controller, and configured to transmit and receive broadcast address information including a broadcasted address for a cache read or write operation, an index address that corresponds to the broadcast address and that indicates a location in the tag memory for internally storing the cache read or write operation, read or write information, and hit or miss information of another one of the plurality of caches to and from the instruction cache, wherein the coherency controller is configured to, upon detecting that a cache line of the instruction cache is in the modified state and is required to be emptied by using a least recently used (LRU) controller, write information in the cache line to the memory, modify the modified state of the cache line to the invalid state, and transmit a signal for requesting access to a coherency bus and a signal for allowing an occupation of the coherency bus.