1. A data processing system for out-of-order logical condition register processing comprising: input means for communicating a plurality of instructions, said instructions implementing logical condition register operations; a processing unit, receiving one or more of said plurality of instructions, coupled to an output of each of one or more execution units for receiving instruction operand values therefrom, said processing unit including a portion for receiving a plurality of instruction identifiers (IID) wherein execution unit instructions corresponding to said plurality of instruction identifiers modify one or more architected register operands; and a data storage device receiving data from said architected register, said data storage device being coupled to said processing unit for providing said IIDs thereto.