1. A programmable logic device comprising: a programmable soft-logic portion configurable by a programmed bit stream, said soft-logic portion comprising at least one initiator; and, a hard-logic portion having an interconnect fabric and a memory interface structure, the memory interface structure comprising a plurality of input queue modules including a plurality of physical thread pointers and a thread look-up table (LUT), wherein a request from a plurality of logical threads initiated by the at least one initiator is written onto a queue module random access memory (RAM) using the LUT and corresponding physical thread pointer; and a plurality of output data queue modules to temporarily store responses from the RAM until arbitrated onto the interconnect fabric.