1. A data processing system comprising a plurality n of simultaneously operable data processing stages each of which contains an arithmetic unit for performing arithmetic operations on data in response to control signals, program control means for producing a sequence of control codes, a new control code being produced each time a shift signal is received by the program control means, and a plurality n of buffers connected in series, the first buffer in the series being connected to the output of the program control means, and each buffer being clocked by said shift signal so that when a said shift signal occurs the contents of each buffer is transferred into the next buffer, if any, in the series and the control code currently produced by the program control means is transferred into the first buffer in the series, whereby at any given time the series of buffers contains the latest n control codes produced by the program control means, wherein the improvement comprises (a) means connected to all the buffers for merging together the current contents of all the buffers to form a single microprogram start address; (b) a microprogram store containing a plurality of sequences of microinstructions; (c) microprogram sequencing means, connected to receive the microprogram start address from the merging means, for producing a sequence of microprogram addresses starting at said microprogram start address, and for applying the sequence of microprogram addresses to the microprogram store so as to read out a corresponding sequence of microinstructions therefrom; and (d) microinstruction decoding means for decoding each microinstruction read out of the store, to produce said control signals which are applied to said n data processing stages, and for producing said shift signal at the end of each sequence of instructions.