1. An integrated circuit device comprising: a first processor core; a first target state register coupled to the first processor core having a trace data portion for instructions executed by the first processor core and a marker data portion; a second processor core coupled to the first processor core; a second target state register coupled to the second processor core having a trace data portion for instructions executed by the second processor core and marker data portion; and a time stamp register containing marker data coupled to the marker data portion of the first target state register and to the marker data portion of the second target state register.