1. A processor comprising: an instruction fetch unit configured to fetch instructions from a memory; a decoder coupled to the instruction fetch unit; and an execution unit coupled to the decoder; wherein the decoder is configured to: receive an instruction comprising at least an escape code field and an opcode field; and determine via the escape code field that said instruction comprises three operand identifiers which identify three operands of the instruction; and wherein the execution unit is configured to execute said instruction, wherein said executing comprises utilizing the three operands.