1. A processor, comprising: a front end including a decoder, the decoder including circuitry to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction; and a memory management unit (MMU) including circuitry to: based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction; and flush the dirty data from the volatile cache upon a subsequent FoF operation.