1. A Programmable Resistive Device (PRD) memory, comprising: a plurality of PRD memory cells, at least one of the PRD memory cells including at least: a Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to an element selector and a read selector; the read selector having an read source input (SLR) and/or a read enable input (ENR) coupled to a second supply voltage line and/or a third supply voltage line, respectively, and wherein the PRE is configured to be readable by applying voltages to the first, second, and/or the third supply voltage lines to conduct current flowing through the PRE to thereby sense the PRE resistance into a logic state.