1. A reconfigurable asynchronous logic element, comprising: a plurality of edges providing bit-level asynchronous communication with at least one neighboring logic element, each edge comprising: at least one input for receiving at least one input state token from a neighboring logic element; and at least one output for transferring an output state token to a neighboring logic element; and computational circuitry configured to perform a logic operation utilizing at least one received input state token as at least one input to produce an output state token reflecting the result of the logic operation, wherein the logic operation performed by the logic element is reconfigurably programmable, wherein the computational circuitry is neither globally or locally clocked, and wherein the input and output state tokens are implemented as charge packets and the charge packets are conserved during the logic operation.