1. A system for determining a chip yield comprising: a first level integration solver configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level integration with the first probability distribution function; and a second level integration solver, implemented by a hardware processor, configured to perform a continuous second level integration based on a second probability distribution function modeling variations between dies to determine the chip yield, wherein a solution of the first probability distribution function modeling variations within the chip is a variable for solving the second probability distribution function.