1. A resistive memory device comprising: a memory cell array comprising a plurality of memory layers stacked in a vertical direction, wherein each of the plurality of memory layers comprises a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other, and a bad region management unit that defines as a bad region a first memory layer, comprising a bad cell from among the plurality of memory cells, and second memory layers, one of the second memory layers disposed adjacent to an upper surface of the first memory layer and another of the second memory layers disposed adjacent to a lower surface of the first memory layer.