1. An asymmetric vector multiprocessor consisting of a plurality of scalar units for processing scalar instructions and a vector unit for processing a vector instruction transmitted from each of the scalar units, wherein said plurality of scalar units have completely or partially different architectures; and said vector unit comprises: one or more instruction converting means, each corresponding to each of said one or more architectures different from an architecture of said vector unit among plural types of architectures of said plurality of scalar units, for converting vector instructions transmitted from said one or more scalar units having said one or more architectures into instruction forms executable in said vector unit without changing a language level of the vector instructions; and vector instruction executing means for executing a vector instruction transmitted from said one or more instruction converting means or from the scalar unit having a compatible architecture as said vector unit.