1. A method implemented in a processor comprising: identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete, wherein the commit operation associated with the first transactional memory region includes at least one speculative execution, wherein the one or more of plurality of operations that follow the first transactional memory region are treated as part of the first transactional memory region so that states of architectural registers of the processor from execution of the first transactional memory region and the one or more of the plurality of operations are preserved.