1. A computer implemented method for reducing failure in time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology, the method comprising: receiving an input data file that includes register transfer level (RTL) data of the circuit design, wherein the RTL data includes the one or more sequential devices; identifying a preferred logic state for each of the one or more sequential devices; adjusting the one or more sequential devices based on the preferred logic state.