1. A method of executing code in a processor, wherein the processor has an Instruction Set Architecture and a microcoded microarchitecture including an execution unit, and wherein there is provided a memory containing ISA instructions, the method comprising: fetching from the memory a first ISA instruction which identifies the presence of a customer code routine; decoding the first ISA instruction; in response to the first ISA instruction, fetching from the memory a customer code sequence of ISA instructions, decoding the customer code sequence of ISA instructions into a customer code sequence of first microinstructions, and storing the customer code sequence of microinstructions for future execution; fetching from the memory a second ISA instruction which is not part of the customer code sequence; decoding the second ISA instruction into at least one second microinstruction; and executing the second microinstruction.