1. A processor comprising: a subcircuitry configured to perform a sign extension associated with a sign extension field value of a multi-byte non-branch instruction, wherein said subcircuitry is further configured to perform a sign extension associated with a sign extension field value of a multi-byte branch instruction, wherein said subcircuitry is operable to use the multi-byte branch instruction to bypass access to a first byte of a multi-byte target instruction to access another byte of the multi-byte target instruction.