1. A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits, said method comprising the steps of: converting logical cones in the logic circuits into logical expressions, each logic cone including all of inputs and logic circuits which affect one output of the combinational logic circuit; storing a correlation between the logical expression converted by said converting step and one or more logic circuit elements included in the logic cone; and identifying the logic circuit element corresponding to a specified term included in the converted logical expression.