1. A parallel processor array comprising: a plurality of processing elements, each comprising: a processor having an arithmetic logic unit, control store, program sequences and instruction decoder; a read/write memory associated with said processor; an input/output means associated with said processor and read/write memory; means for interconnecting said processing elements in a binary tree in which each processing element except those at extremities of the binary tree is connected to one parent processing element and at least first and second child processing elements; said input/output means comprising: means for broadcasting information received from a parent processing element to said child processing elements, such that common information is distributed to each processing element of the binary tree or a subtree thereof without direct control of the processors of the processing elements; and means for determining a priority among respective values of information received from said child processing elements and information received from the processor with which said input/output means is associated without direct control of the processors of the processing elements; wherein the input/output means of the processing elements connected in said binary tree cooperate so that information is broadcast from a first parent processing element to the child processing elements in said binary tree or subtree that are most remote from said first parent processing element, and a priority is determined among values of information at each processing element in said binary tree or subtree, each in a time on the order of the logarithm of the number of processing elements in said binary tree or subtree multiplied by the time for the broadcasting of information from a parent processing element to child processing elements connected thereto, and the time required to determine priority amoung values of information received from the processor of a processing element and the child processing elements connected thereto, respectively.