1. An apparatus comprising: processing circuitry to process M-bit data values having a redundant representation representing a P-bit numeric value using a plurality of N-bit portions, where M>P>N, wherein the processing circuitry is configured to identify a significance of bits of each N-bit portion of the redundant representation based on programmable anchor value stored in a control register, and within a group of at least two adjacent N-bit portions, a plurality of overlap bits of a lower N-bit portion of the group have a same significance as a plurality of least significant bits of at least one upper N-bit portion of the group; and the processing circuitry comprises a plurality of operation circuit units to perform a plurality of independent N-bit operations in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation.