1. A processor comprising: an interface to perform a transaction to fetch information from a memory; and memory management logic to translate an untranslated address to a memory address, including; a storage location to store a first address of a first data structure for the first translation stage of a plurality of translation stages; the plurality of translation stages, each translation stage having translation logic to find an entry in a corresponding data structure based on a corresponding portion of the untranslated address, each entry to store one of a second address of a second data structure for the first translation stage, an address of a data structure for a successive translation stage, and the memory address; determination logic to determine whether an entry is storing a second address of a second data structure for the first translation stage; and a translation on lookaside b utter to store translations.