1. An integrated circuit (IC) comprising: a) a plurality of tiles arranged in a particular tile arrangement, wherein said tiles comprise a plurality of memory tiles and a plurality of computational tiles, wherein at least one particular computational tile comprises a set of configurable input select interconnects; and b) a plurality of memory arrays for storing data, each memory array embedded in the tile arrangement between two sets of memory tiles, wherein each of said two sets of memory tiles comprises a set of configurable input select interconnects that correspond to the set of configurable input select interconnects of said particular computational tile, wherein a subset of the set of configurable input select interconnects of each memory tile forms at least part of a port for accessing at least one memory array.