1. A pipelined out-of-order execution in-order retire microprocessor, comprising: a branch predictor, configured to predict a target address of a branch instruction; a fetch unit, coupled to the branch predictor, configured to fetch instructions at the predicted target address; an execution unit, coupled to the fetch unit, configured to: resolve a target address of the branch instruction and detect that the predicted and resolved target addresses are different; determine whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and refrain from executing the branch instruction, if there is an instruction older than the branch instruction in program order and that must be corrected.