1. A method for analog circuit placement which is executed in a computer to perform a layout for an analog circuit, the method comprising: using the computer to perform the following: inputting a plurality of modules of said analog circuit, a netlist of said analog circuit and a constraint file of said analog circuit; creating a QB-tree construction by combining a B*-tree and a quadtree based-on said plurality of modules and said constraint file; performing a node perturbation of said QB-tree; performing a look-ahead constraint checking to check whether constraints of said constraint file are met or not; performing a QB-tree packing when said constraints of said constraint file are met; and performing layout for said analog circuit by performing a cost evaluation to guide a simulated annealing process using said packed QB-tree.