1. A method of generating a logical representation of a functional logical system from a physical representation of the system, the method comprising: loading a physical hardware description language (HDL) representation of the system and creating a physical HDL representation from a physical schematic of the system; identifying from the physical HDL representation power nets and component blocks, loading from a rule library initial condition rules for the power nets and the component blocks, and assigning the initial condition rules to the power nets and component blocks; and using at least in part the initial condition rules to transform the physical HDL representation to a logical HDL representation by identifying connector blocks and converting the connector blocks to hierarchical IO logical HDL representations; identifying component blocks appropriate for conversion to logical instantiations and converting the appropriate component blocks to logical HDL representations; identifying component blocks appropriate for deletion and deleting the component blocks appropriate for deletion; and identifying resistor components and converting resistor components to logical HDL representations.