1. Apparatus for correcting instruction errors in a data processing system comprising, in combination: first and second instruction memory means for storing instructions in memory locations defined by addresses; register means for receiving and holding instructions from said first and second instruction memory means; instruction error detection means operable in association with the register means for evaluating an instruction held in said register means to determine whether the instruction is valid or erroneous; means for freezing the state of at least a portion of the data processing system in response to the detection of an erroneous instruction by the instruction error detection means; and means operable in response to the detection of an erroneous instruction for replacing the erroneous instruction in said register means with a corresponding valid instruction retrieved from the second instruction memory means.