1. A processor comprising: an on-die interconnect that enables receipt of incoming data and transmission of outgoing data; a plurality of core-cache clusters, each of the plurality of core-cache clusters including both a cache memory and one or more processor cores in communication with the cache memory; and a scalability agent coupled to the on-die interconnect, the scalability agent (i) operating in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent and (ii) managing a flow of the incoming data and the outgoing data into a socket associated with at least one of the plurality of core-cache clusters.