1. A memory device comprising a plurality of memory cells, each memory cell in the plurality of memory cells comprising: a diode comprising a top contact surface, and a member comprising doped semiconductor material having an outside surface defining sides of the diode; an insulating layer over the diode, and including a first opening over the diode; a dielectric spacer within said first opening on the diode, the dielectric spacer having an inside surface defining a more narrow opening and having an outside surface defining sides of the dielectric spacer that are self-aligned with sides of the diode; and a memory element including a first portion within the more narrow opening and contacting the top contact surface of the diode, and including a second portion over the first portion within the first opening, the second portion having an outside surface defining sides self-aligned with the sides of the diode.