1. A processor system comprising: a processing unit with a predetermined instruction set; a predicate register comprising a first plurality of predicate data locations, including PL 1 , PL 2 , and PL 3 , each predicate data location being adapted to store predicate data, the first plurality of predicate data locations is an integer number N; a general purpose register comprising a second plurality of general purpose data locations, the second plurality of general purpose data locations are configured to be partitioned into sets of general purpose register locations, each set of the M sets having N general purpose data locations; a data pathway for transmitting data between the predicate register and the general purpose register; and the processor system configured to carry out a predicate swap instruction of the predetermined instruction set to: swap, via the data pathway, predicate data at PL 1 of the predicate register with data at a corresponding general purpose data location of a first set of the M sets based on a first portion of the predicate swap instruction identifying PL 1 and a second portion of the predicate swap instruction identifying the first set of the M sets; and to swap, via the data pathway, predicate data at PL 2 of the predicate register with data at a corresponding general purpose data location of a second set of the M sets based on a third portion of the predicate swap instruction identifying PL 2 and a fourth portion of the predicate swap instruction identifying the second set of the M sets.