1. A design structure embodied in a non-transitory machine readable storage medium for at least one of designing, manufacturing, and testing a design, wherein when executed by a processor, the design structure implements the design comprising: a memory subsystem having a plurality of buffer chips configured for retrieving memory data from memory components connected thereto; and a memory controller associated with the memory subsystem, the memory controller comprising: logic for scheduling a next data request among one or more received data requests for execution at a next scheduling cycle based on a comparison of binary return time vectors corresponding to the one or more received data requests with a history vector corresponding to currently executing data requests, wherein the next data request does not present a data bus conflict to the currently executing data requests.