1. A cache memory system for implementing the transfer of instruction codes from a main memory to a processing unit, said processing unit including a program counter the contents of which specify an address in the main memory which contains a next instruction code to be executed by said processing unit, comprising: prefetch buffer means connected to prefetch and store instruction codes from addresses in the main memory which sequentially follow the addresses contained in the program counter; a head buffer; a use buffer; and instruction transfer control means responsive to the contents of the program counter, the prefetch buffer means, the head buffer, and the use buffer, which function so that: a) if an instruction code specified by the program counter is in the prefetch buffer, said code is transmitted to the processing unit and is also stored in use buffer, b) if the instruction code specified by the program counter is in the head buffer or the use buffer, said code is transmitted to the processing unit; or c) if the instruction code specified by the program counter is not in any of the prefetch buffer means, the head buffer, or the use buffer, said code is fetched from the main memory, transmitted to the processing unit and also 1) stored in the head buffer if the contents of the program counter satisfy a predetermined test or 2) stored in the use buffer if the contents of the program counter do not meet the predetermined test.