1. A processor comprising: one or more execution units; an instruction cache having instructions stored therein for execution by an execution unit; an instruction unit coupled to the one or more execution units and which provides instructions fetched from the instruction cache to the one or more execution units for execution; logic associated with the instruction unit for: detecting a presence of a single branch, backwards short loop within a stream of fetched instructions; buffering the single branch, backwards short loop in a local loop buffer of the instruction unit; and retrieving instructions for completing the single branch, backwards short loop from the local loop buffer rather than fetching the instructions from the instruction cache.