1. A macro scheduler, comprising: a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices; a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design; resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition; and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.