1. An apparatus comprising: a semiconductor die device including a multi-ported three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate of the semiconductor die, wherein the semiconductor die that includes the multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells; and a second semiconductor die that includes a multi-ported memory interface that is connected to the multi-ported 3D memory, the second semiconductor die including a multi-ported static random access memory (SRAM), wherein the second semiconductor die includes a state machine configured to store data at the multi-ported SRAM and to initiate a data store operation at the multi-ported 3D memory by sending the data and an instruction to the multi-ported 3D memory via the multi-ported memory interface.