1. A memory device comprising: a plurality of sub-tiles in a memory section configured to include a plurality of memory cells; a plurality of wordlines each configured to couple to a row of memory cells in the sub-tile; and a column select circuit configured to control at least two level column lines; a common bit line (CBL) coupled to the column select circuit, the common bit line also coupled to a sense and program circuit; a common source line (CSL) coupled to the memory section, wherein a selected time of one of the two level column lines is different from that of the other of the two level column lines, and a pulse of the common source line is set to a low voltage for a reset operation.