1. A computer implemented method of circuit equivalence checking, comprising: solving at least a first equivalence checking problem, wherein the act of solving at least the first equivalence checking problem is performed by a processor; storing at least a first solution to at least the first equivalence checking problem; reusing at least part of the first solution to the first equivalence checking problem for a second equivalence checking problem, wherein the first equivalence checking problem includes comparing logic cones and the first solution includes one or more problem signatures, the first solution includes one or more stored problems, and the one or more stored problems permit matching between stored and searching logic cone pairs; and storing the one or more problem signatures in a memory.