1. A logic decoder circuit adapted for performing Boolean or fuzzy logic comprising: one or more logic components configured to perform a logic function of an AND-NOT gate, said AND-NOT gate comprising a circuit that performs a conjunction of a first input X and a second input Y to obtain an output X-AND-NOT-Y that is either Boolean or substantially linear for given ranges for X and Y (max{0, X-Y}), wherein said AND-NOT gate is used in a fast fuzzy decoder.