1. A resistance change memory device comprising: a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner, bit lines each commonly connecting one ends of plural memory cells arranged in a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged in a second direction of the matrix; a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit, wherein the memory cell comprises a variable resistance element for storing as information a resistance value, the variable resistance element including a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d”-orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less, wherein the read/write circuit comprises: a global bus region having a plurality of data lines to which read data are transferred and a plurality of write pulse signal lines for transferring write pulses to the bit lines, the data lines and the write pulse signal lines being so disposed as to cross a central portion of the cell layout region in the second direction; first and second bit line select circuits disposed along the first and second boundaries of the cell layout region, respectively, to which the respective bit lines of neighboring two cell arrays are connected; first and second sense amp arrays for sensing data of bit lines selected by the first and second bit line select circuits, respectively, the first and second sense amp arrays being disposed between the first, second bit line select circuits and the global bus region, respectively; a word line select circuit disposed along the third or fourth boundaries of the cell layout region, to which shared word lines of the neighboring two cell arrays are connected; and a write circuit for generating the write pulses supplied to the write pulse signal lines, wherein the write circuit comprises: a logic pulse generation circuit for generating positive logic pulses and negative logic pulses to be supplied to selected words lines and selected bit lines in each of the cell array, respectively, the positive logic pulses and negative logic pulses being controlled to have overlap widths therebetween; and a write pulse generation circuit for selectively boosting the logic pulses output from the logic pulse generation circuit to output the write pulse signal lines, wherein the logic pulse generation circuit comprises: a pulse generation circuit for generating two pulses with the same pulse width, which are phase-shifted each other; and a logic gate circuit for outputting the negative logic pulses and positive logic pulses with an overlap time determined by combination logics determined depending on write data.