1. A microprocessor comprising: an instruction cache operable to store encrypted instructions; fetch logic configured to fetch encrypted instructions from the instruction cache; a secure memory configured to store a plurality of master keys; key selection logic configured to select a set of one or more master keys based upon an encrypted instruction fetch address; and decryption logic configured to use the selected set of one or more master keys or a decryption key derived from the selected set of one or more master keys to decrypt the encrypted instructions fetched from the instruction cache.