1. A locally synchronous shared built in self test (BIST) architecture for testing a plurality of embedded memories, comprising: a programmable master controller configured to initialize testing by generating and controlling a plurality of control signals; and one or more interface receivers and one or more interface transmitters each operatively coupling a memory to the programmable master controller and configured to respond to the plurality of control signals, the interface receivers configured to latch data on two data inputs in response to a handshake signal and the interface transmitters configured to transmit complementary signals onto two data outputs for transmission of a data bit data in response to the handshake signal.