1. A memory device operating in an architecture scheme having a plurality of memory sub-arrays, said memory device comprising: a storage element, said storage element being uniquely addressed; an activating element for activating at least one memory cell within said storage element; a first selecting element for selecting said storage element and being coupled to said storage element; a second selecting element for selecting said activating element and being coupled to said activating element; a bus element for reading information from said at least one memory cell within said storage element, wherein said bus element is coupled to said storage element; and an alternative storage element for alternatively storing information in the event that said storage element is defective permanently disabling said defective storage element and programming an unique address of said defective storage element for said alternative storage element, said alternative storage element being coupled to said activating and bus elements, wherein said defective storage element and said alternative storage element are located in either the same or separate of said plurality of memory sub-arrays, said alternative storage element including at least one redundancy memory block, wherein said at least one redundancy memory block includes a programmable element, and wherein said programmable element includes a sense amplifier.