1. Redundancy circuitry for a semiconductor memory device, the redundancy circuitry comprising: a matrix of rows and columns of memory elements and redundancy rows and redundancy columns of redundancy memory elements; a plurality of programmable non-volatile memory registers programmable to store addresses of defective memory elements which must be replaced by redundancy memory elements, said plurality of programmable non-volatile memory registers being formed by a first set of programmable non-volatile memory registers each associated with one of said redundancy rows and by a second set of programmable non-volatile memory registers each associated with one of said redundancy columns; and combinational circuit means, each set of programmable non-volatile memory registers being provided with respective combinatorial circuit means respectively supplied with row address signals and column address signals for inhibiting the selection of the redundancy rows and of the redundancy columns respectively when a matrix row or a matrix column is addressed whose address coincides with the address stored in a non-programmed memory register of the first set or of the second set.