1. A method for full integrated circuit (IC) mask pattern generation, comprising: generating, by a processor, an initial mask image from target polygons, wherein main feature polygons and SRAF image pixels are identified in the initial mask image; performing, by the processor using iterative optimization based on an inverse lithographic technology (ILT), a co-optimization on segments of main feature polygons and subresolution assist feature (SRAF) image pixels; after iterations of the co-optimization, determining SRAF polygons from the SRAF image pixels; determining optimized mask patterns by performing an edge based optimization on the segments of the main feature polygons and the SRAF polygons using gradient-based iterative optimization; and generating a full-IC mask based on the optimized mask patterns.