1. A semiconductor integrated circuit having a CPU for executing code comprising instructions from memory including an operating system (OS), the CPU being configured to execute the instructions as a pipeline and to use a table to translate virtual addresses of the instructions to physical addresses in the memory, the CPU being further configured to expose execution parameters including at least an address of an instruction, a mode of operation of the CPU and an indication of whether an instruction was executed to completion, the integrated circuit further comprising an instruction monitor configured to receive the execution parameters and to determine, based on at least the exposed address, the exposed mode of operation and the exposed indication, an authenticity of code executed from the memory to selectively impair function of the integrated circuit if the code is not authentic, wherein determining the authenticity of code comprises determining whether the exposed address is from a region of the memory checked by the instruction monitor.