1. A processor comprising: an interface to non-volatile memory; logic circuitry to track, with a same specialized hardware that tracks a cache line change, a cache line written in a transactional operation and perform either of a commit and a roll back at an end of the transactional operation; and an execution unit to execute a first instruction to cause the same specialized hardware that tracks the cache line change to track a cache line written in the non-volatile memory for a modification by a non-transactional operation.