1. A device comprising: a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode; and a controller configured to: receive write data from a host device; program the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode; and perform a data consolidation operation on the first block at least in part by programming at least a portion of the write data together with data stored in a separate second block of the memory array to a third block of the memory array using the multiple-bit per cell mode.