1. A device comprising: a memory; and a processor in communication with the memory, the processor operating in a white box implementation, and the processor being configured to: split data processed in a first round to produce a first output value and a second output value, wherein the first output value equals the second output value, and wherein the first round is one round of a plurality of rounds; encrypting the first and second output values with different functions, wherein the different functions provide protection to the processor from differential fault analysis attacks; process a first input by a second round of the plurality of rounds to produce a third output, wherein the first input is based upon the first output value; process a second input by the second round to produce a fourth output, wherein the second input is based upon the second output value; process a third input by a third round of the plurality of rounds to produce a first share using a first weight, wherein the third input is based upon the third output; process a fourth input by the third round to produce a second share using a second weight, wherein the first and second weights are complementary, wherein the fourth input is based upon the fourth output; combine the first share and the second share to produce a combined output; and process the combined output by a fourth round; and performing further processing of the combined output to produce a cryptographic key.