1. A method of generating a test vector, comprising the steps of: providing a design functional unit which is designed to emulate a paradigm functional unit; executing a plurality of program instructions on a processor which includes a fabricated circuit form of the paradigm functional unit, the program instructions including a plurality of instructions in a paradigm instruction set executed by the paradigm functional unit; selecting a test instruction of the paradigm instruction set; generating operand data which is operated upon by the paradigm functional unit executing the test instruction; executing the test instruction operating upon the generated data; accessing a storage stored by the fabricated circuit form of the paradigm functional unit within the processor to retrieve a test vector result; and recording a test vector result of the test instruction execution for testing the design functional unit.