1. A computer-implemented method for more rapidly and reliably optimizing a circuit design, the method comprising: receiving a boundary specification for a circuit design region; deriving a reduced netlist comprising circuitry within the circuit design region and all external circuitry that is outside the circuit design region but that is connected to circuit paths crossing the specified boundary, including all connected non-critical-path circuitry up to a first clocked respective storage element, with the external circuitry described by a reverse interface logic model; using a computer, optimizing the reduced netlist with a circuit simulator tool under full circuit design constraints, wherein changes made to the reduced netlist are retained for coordinated optimizations of other circuit design regions; and outputting optimization results.