1. A processor comprising: a plurality of arithmetic units; an accumulator unit; and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit, the reduction unit receiving products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit; wherein the reduction unit is operative to process the products and the first accumulator value, and to generate a second accumulator value for delivery to the accumulator unit; and wherein the processor implements a plurality of vector multiply and reduce operations having guaranteed sequential semantics.