1. A microprogrammable data processing unit comprising: a plurality of registers, one of said registers for storing instructions to be processed, said instruction including an operation code; a first addressable control store having a plurality of locations, one for each different instruction operation code and including at least a multibit control sequence field, a constant field having a number of bits and an address field; a cycled second addressable control store coupled to said first control store and having a plurality of locations for storing at least one microinstruction of a plurality of execution sequences; sequence control circuit means coupled to said first control store for generating one of a plurality of sequences of control signals designated by the coding of said control sequence field contained in the location read out in response to each instruction operation code, said sequence control circuit means including bistable storage means for storing signals corresponding to at least one bit of said constant field of said location, said bit signals coded for specifying the differences in the operations defined by differently coded instruction operation codes; and, an execution unit for executing the operations specified by said instruction operations code under control of microinstructions of the execution routine specified by said address field of said location read out from said second control store, said execution unit being operatively coupled to different ones of said plurality of registers and to said bistable storage means, and said execution unit being conditioned by said bit signal to execute the operations specified by each of said differently coded operation codes without requiring further testing of the operation code of the instruction under execution.