1. An integrated circuit (IC) design method comprising: receiving an IC design layout having a plurality of IC features; identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules, and complex features as a second layout wherein the second layout violates the design rules; and generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.