1. A method of diagnosing a failure in a complex semiconductor device comprising the steps of: selecting a semiconductor device having logic circuits formed of latches; selecting a functional test procedure; testing the logic circuits in the device with said functional test procedure and upon identifying a failing vector in said device; selecting a structural design and test technique; combining said functional test procedure and said structural design and test technique to dynamically create a new test pattern based on the functionally identified failure; and transforming said new test pattern into a scan deterministic pattern; and diagnosing the failing circuit with said scan deterministic pattern to determine the location of and, type of error in said failing circuit.