1. A method comprising steps of: (a) receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; (b) calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; (c) estimating a stage delay for each of the inputs by adding a gate delay of each of the inputs to the separate interconnect delay for each of the inputs; and (d) generating as output the stage delay for each of the inputs.