1. A system for assigning addresses to input/output (I/O) devices in a control network, and for verifying addresses assigned to the I/O devices, comprising: a logic controller providing memory into which a connectivity map may be programmed, said connectivity map defining a specific expected address for each I/O device in the network, said logic controller further providing an external controller bus and logic for downloading said connectivity map to an I/O bus manager connected to said logic controller via said external controller bus, said I/O bus manager providing a mechanism for assigning said specific addresses to said I/O devices; at least one node processor connected to said I/O bus manager, said at least one node processor including a multiplexer for multiplexing output signals from said I/O bus manager and a demultiplexer for demultiplexing input signals from said I/O devices; and at least one I/O cluster processor connected to each of said at least one node processor, said at least one I/O cluster processor including a multiplexer for multiplexing input signals from said I/O devices and a demultiplexer for demultiplexing output signals from said at least one node processor; said at least one I/O cluster processor including (i) a manager; (ii) a visual indicator for displaying the address device for manually requesting an address from said I/O bus assigned by said I/O bus manager; and (ii) a device for manually rejecting said address assigned to it by said I/O bus manager if said assigned address is not the expected address for said I/O cluster process defined in said connectivity map.