1. A computer system for generating a summary of test coverage for a hardware description, said hardware description corresponding to a finite state machine (FSM), said computer system comprising: a) a memory for storing said hardware description and a predetermined test vector, and b) a processor, coupled to said memory, using said hardware description, generates state information corresponding to said FSM, said processor, using said state information, generates a first description, said first description including a description for monitoring states and signals in said hardware description, and said processor, using said test vector, said hardware description and said first description, generates said test coverage summary.