1. A computer processor comprising: a processor having an I-unit that fetches and decodes instructions, an E-unit that executes those instructions in an overlapped manner with those of the I-unit, a PSW (Program Status Word) execution unit which allows a ESA/390 SPKA (SET PSW KEY FROM ADDRESS) instruction to be executed without serializing said processor in most cases in order to improve performance of said ESA/390 SPKA instruction, and having a cache that provides recently used instruction data to said I-unit, and having control logic in the PSW execution unit for controlling processor serialization which includes a fetch detection logic and SPKA instruction execution logic whereby the cache continually monitors instruction data passed to the I-unit to determine if the instruction data currently being fetched by said I-unit has a ESA/390 Fetch Protect bit active in a storage key of a PSW (Program Status Word) for the instruction's page, and if the Fetch Protect bit is active the control logic notifies the PSW execution unit that said Fetch Protect bit is active for the instruction data currently being fetched and said fetch detection logic sets a first latch indicating the Fetch Protect bit is active, and when the PSW execution unit determines if an SPKA instruction is to be executed said PSW execution unit updates the PSW with the data for said SPKA instruction and sets a second latch in the PSW execution unit that is set and held when an said SPKA instruction executes, whereby said control logic in the PSW execution unit which continually monitors the state of the first latch that indicates if the Fetch Protect bit was active for a recent instruction fetch and the state of the second latch that indicates if an SPKA instruction has recently executed allows the processor to execute instructions normally, without serializing said processor, if either one of these two latches is not active.