1. A cache memory controller capable of servicing multiple, pipelined multi-word read memory requests issued by a processor to a cache memory containing data, the cache memory controller comprising: means for detecting a first pipelined multi-word read memory request issued by the processor; means for initiating a servicing of the first pipelined multi-word read memory request; means for determining whether data within the cache memory corresponds to the first pipelined multi-word read memory request; means for completing the servicing the first pipelined multi-word read memory request; means for detecting a second pipelined multi-word read memory request issued by the processor prior to the completion of servicing the first pipelined multi-word read memory request; means for initiating the servicing of the second pipelined multi-word read memory request prior to completing the servicing of the first pipelined multi-word read memory request; and means for completing the servicing the second pipelined multi-word read memory request; whereby the servicing of the second pipelined multi-word read memory request overlaps in time with the servicing of the first pipelined multi-word read memory request.