1. A method of manufacturing an integrated circuit, comprising: providing a data file that includes a scaling enhanced circuit layout; and providing a first standard cell layout using a plurality of design rules and the data file, wherein the scaling enhanced circuit layout includes a design rule violation layer that violates at least one of the plurality of design rules, and wherein the first standard cell layout includes: a first layout region of the first standard cell layout corresponding to the data file and including the design rule violation layer, and a second layout region of the first standard cell layout using the plurality of design rules; creating a layout of the integrated circuit, the layout of the integrated circuit comprising the first standard cell layout including the first layout region that includes design elements that violate at least one of the plurality of design rules, and the second layout region, creating a plurality of photolithographic masks using the layout of the integrated circuit; and creating the integrated circuit using the plurality of photolithographic masks, wherein creating the layout of the integrated circuit comprises using a netlist and a standard cell library including the first standard cell layout, the netlist comprising a plurality of instances, their functions and interconnections between the instances.