1. A computer system comprising: a) a processor comprising a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy; b) a first memory channel comprising a first set of address and data lines coupled to the processor; c) a second memory channel comprising a second set of address and data lines coupled to the processor; d) a first first-level memory and a second first-level memory each comprising a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed, the first first-level memory coupled to the first memory channel and the second first-level memory coupled to the second memory channel; and e) a first second-level memory communicatively coupled to the first memory channel, and a second second-level memory communicatively coupled to the second memory channel, the first and second second-level memories including a second set of characteristics associated therewith, the second set of characteristics including: i) second read and write access speeds wherein at least one of the second read and write access speeds is relatively lower than either the first read access speed or first write access speed, respectively, ii) non-volatility such that the first and second second-level memories are to maintain content if power to the first and second-level memories is removed, wherein at least a portion of the first first-level memory is configured as a first cache for instructions and/or data stored in the first second-level memory and at least a portion of the second first-level memory is configured as a second cache for instructions and/or data stored in the second second-level memory; f) first-level memory controller circuitry to implement said at least a portion of the first first-level memory and said at least a portion of the second first-level memory as the first and second caches; g) second-level memory interface circuitry to generate memory channel addresses to access the first second-level memory and the second second-level memory.