1. A method of securing a performance state change of a processor, the method comprising: detecting a request to change a current performance state of the processor to a target performance state, the processor having a plurality of performance states each including a target operating level and an operating level tolerance range; and adjusting, in response to the request, the operating level tolerance range of the current performance state of the processor to include operating levels associated with a transition from the current performance state to the target performance state.