1. An information processing apparatus comprising: a processor; a memory interface module configured to read one of instructions stored in a memory in accordance with a memory address designated by a fetch request from the processor; an error detection module configured to detect whether an error exists in the read instruction using an error correction code on the memory, which corresponds to the read instruction: and an instruction transmission module configured to send to the processor a first instruction to store the same memory address as the memory address designated by the fetch request into a stack and a second instruction to jump to an error correction routine for correcting an error of the read instruction instead of sending the read instruction to the processor upon detection of the error in the read instruction, wherein the memory address stored in the stack is loaded on a program counter of the processor after completion of an error correction by the error correction routine.