1. An apparatus for use in microprocessors that avoids the complete re-execution of traces when assumptions made in generating the said traces are determined to be not valid at the time of executing said traces or when interrupts occur, the said apparatus comprising of: (a) One or a plurality of facilities that support the decomposition of a trace into one or a plurality of commit groups, each commit group comprising a series of operations within the said trace; (b) A plurality of storage slots for holding the results of the execution of operations within the trace that generate a result targeting least one architectural destination, with at least a single slot within the said apparatus for holding the result of the final operation in program order within a commit group to update a specific architectural destination; (c) The architectural destination of claim 1 b may include but is not limited to architectural registers, condition registers, control registers, or memory locations; (d) One or a plurality of facilities that permit results to be written to their assigned slots in the order in which the said results are generated; (e) One or a plurality of facilities to associate one or a plurality of operations from each of the said commit groups to an aforesaid slot of claim 1 b; (f) One or a plurality of facilities for noting the state of each slot of claim 1 b at least as ready or not ready, where ready signifies that the result(s) within said slot are complete and valid; (g) One or a plurality of facilities to determine when all slots assigned to operations within a given commit group are in the ready state of claim 1 f; (h) One or a plurality of facilities to identify and extract values stored in any slots in the ready state assigned to a given commit group, wherein said commit groups are processed in a predetermined order; (i) One or a plurality of facilities to atomically commit the values extracted in claim 1 h to structures for maintaining a consistent user visible architectural state only when all assumptions made in generating all operations within the commit group of claim 1 h are satisfied, wherein the aforesaid atomic commitment comprises one or a plurality of steps to move all results within the slots assigned to the said commit group into the user visible architectural state in one logically indivisible step. (j) One or a plurality of facilities to reset the state of the slots within the apparatus of claim 1 b to the not ready state once the data of said slots have been moved into the architectural state in accordance with claim 1 i. (k) One or a plurality of facilities to permit the microprocessor to establish an unambiguous state to resume execution from on recognizing an exception or an interrupt, the said unambiguous state being the one established by the most recently committed commit group in accordance with claim 1 i. (l) One or a plurality of facilities to discard any slots assigned to operations in commit groups other than the most recently committed commit group within the said trace once a decision has been made made to perform actions to service an interrupt or exception.