1. A memory hub device with test logic, the memory hub device configured to communicate with memory devices via multiple hub device ports and configured to communicate on one or more busses in an upstream and downstream direction, the test logic comprising: a built-in self test (MBIST) apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns; and configuration registers to hold fault and diagnostic information, and to initiate one or more tests.