1. A device, comprising: a plurality of partitioned registers useable for storing floating point numbers; a first arithmetic logic unit coupled to combine output from an operand routing unit with a first operand stored within a first fixed one of a plurality slots of a first register of said plurality of partitioned registers, said operand routing unit is coupled to output a second operand selected from any of a plurality of operands stored within a second register of said plurality of registers to said first arithmetic logic unit; and a second arithmetic logic unit coupled to combine output from said operand routing unit with a third operand stored within a second fixed one of said plurality slots of said first register of said plurality of partitioned registers, said operand routing unit is coupled to output a fourth operand selected from any of said plurality of operands stored within said second register of said plurality of registers to said second arithmetic logic unit.