1. A processor that includes one or more cores, at least one core of the one or more cores comprising: an instruction cache; and a pre-decode unit to: read a first byte from the instruction cache using a logical instruction pointer that points to the first byte in the instruction cache; detect whether the first byte includes a length of an instruction; in response to detecting that the first byte includes the length of the instruction, read the instruction from the instruction cache based on the length of the instruction; and in response to detecting that the first byte excludes the length of the instruction, detect the length of the instruction, and perform operations comprising modifying the first byte of the plurality of bytes to include the length of the instruction.