1. A hardware-implemented apparatus for comparing a pair of input binary words (u, uâ€²), the apparatus comprising: an intermediate value determiner configured to determine an intermediate binary word (z), based on the pair of input binary words (u, uâ€²), and compare the intermediate binary word to a reference binary word or to an inversion of the reference binary word; and an error detector configured to detect that the binary words of the pair of input binary words (u, uâ€²) are equal or inverted to with respect to each other to detect a faultless preceding processing of the pair of input binary words when the intermediate binary word (z) is equal to the reference binary word or equal to the inversion of the reference binary word, and to detect that the binary words of the pair of input binary words (u, uâ€²) are not equal and not inverted with respect to each other to detect an erroneous preceding processing of the pair of input binary words when the intermediate binary word (z) is unequal to the reference binary word and unequal to the inversion of the reference binary word; wherein a bit of the intermediate binary word (z) depends on a XOR-combination of a binary constant, a bit of a first binary word of the pair of input binary words (u, uâ€²), a corresponding bit of a second binary word of the pair of input binary words (u, uâ€²), and a non-constant Boolean function of at least the bit of the first binary word of the pair of input binary words and the corresponding bit of the second binary word of the pair of input binary words.