1. An apparatus comprising: (i) A address ports, wherein A is a positive integer greater than one; (ii) D data ports, wherein D is a positive integer greater than one; (iii) N independent memory banks, wherein N is a positive integer greater than one; (iv) an address switch for routing addresses on said address ports to said memory banks, wherein said routing is based, at least in part, on said addresses; and (v) a data switch for routing data between said data ports and said memory banks, wherein said routing is based, at least in part, on (1) said addresses, and (2) which of said addresses is on which of said address ports.