1. A method of modeling an input slew and output load dependent CMOS gate pin capacitance in a modeled plurality of gates and interconnects representing an integrated circuit, the method comprising: using a computer: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting said extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.