1. A processor comprising: a first register to store a first vector input operand; a second register to a store a second vector input operand; a third register to store a packed data structure containing a first scalar input operand, a second scalar input operand, and a third scalar input operands; a decoder to decode a single instruction into a decoded single instruction, having a first field specifying the first register, a second field specifying the second register, and a third field specifying the third register; and an execution unit comprising a multiplier coupled to the first register, the second register, and the third register, the execution unit to execute the decoded single instruction to for each element position, multiply the first scalar input operand with an element of the first vector input operand to produce a first value, multiply the second scalar input operand with a corresponding element of the second vector input operand to produce a second value, and add the first value, the second value, and the third scalar input operand to produce a result, and store in parallel a result for each element position of the first vector input operand and the second vector input operand into a corresponding element position of a resultant register.