1. A first data processor adapted for coordinating the execution of an instruction received for execution by said first processor with a second data processor responsive to a unique address comprised of a general address portion and a value unique to the second data processor contained in an address field of said instruction, the first data processor comprising: first means for receiving said instruction; second means for providing said unique address by combining said general address portion and the value contained in said address field of said received instruction; and third means for coordinating the execution of said instruction by said second processor at the address provided by said second means.