1. A hardware processor comprising: an input buffer configured to receive data and store the data; a data extractor configured to extract kernel data comprising a plurality of data elements and corresponding to a kernel in the data from the input buffer; a plurality of multipliers configured to multiply the kernel data by convolution coefficients; and an adder configured to calculate a sum of multiplication results from the plurality of multipliers, wherein the data extractor comprises a matrix switch configured to form electrical connections to the input buffer, to the plurality of multipliers, and to the adder based on the kernel.