1. A configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K.ltoreq.N+M); combinational logic means for receiving said K binary signals from said means for selecting, said combinational logic means having a plurality of configurations including at least a first configuration in which said combinational logic means generates a first set of binary output signals, each of which represents a function of some of said K binary signals and a second configuration in which said configurable combinational logic means generates a second set of binary output signals, each of which represents a function of some of said K binary signals, wherein the set of functions represented by said first set of binary signals is not the same as the set of functions represented by said second set of binary signals; a configurable storage circuit comprising: a plurality of input leads for receiving a plurality of input signals, said input signals corresponding to said input leads on a one-to-one basis, said input signals comprising selected ones of said binary output signals of said combinational logic means and selected ones of said N binary input signals, memory means for storing data, said memory means having at least a first and a second input lead and at least one output lead; first means having a first configuration in which said first means provides a first selected one of said input signals of said configurable storage circuit to said first input lead of said memory means second means having a first and a second configuration in which said second means provides a second and a third selected one, respectively of said input signals of said configurable storage circuit to said second input lead of said memory means, said memory means generating said second plurality of M binary signals in response to said signals provided by said first and said second means; and a configurable select logic comprising: means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit, and means for selecting output signals from among the signals received by said select logic.