1. A system for reducing instruction cache miss penalties in application code execution, the system comprising: a processor; and a non-transient storage medium having instructions stored thereon, which, when executed, cause the processor to instantiate a compiler comprising: a code profiler, operable to: determine an instruction cache miss penalty for each of a plurality of code sections of application code, the instruction cache miss penalty indicating a likelihood that execution of the corresponding code section in the target execution environment will result in an instruction cache miss; and generate execution traces from the application code, each execution trace comprising at least one of the plurality of code sections; and an instruction prefetcher operable, for each execution trace having a code section with a corresponding instruction cache miss penalty that exceeds a predetermined penalty threshold, to: traverse a set of code blocks of the execution trace in reverse starting from a source code block of the execution trace until an accumulated instruction latency exceeds a prefetch latency by, for each of the set of code blocks, adding a latency covered by the code block to latencies of previously traversed code blocks of the set of code blocks to calculate the accumulated instruction latency, the prefetch latency corresponding to a predicted time to prefetch into an instruction cache a number of code blocks defined by a prefetch chunk size; and insert an instruction prefetch ahead of a last-traversed code block in the execution trace when the accumulated instruction latency exceeds the prefetch latency.