1. A system for merging data from a first register in a first component together with data from a second register in a second component, wherein the first register and the second register have the same address value, comprising: a bus interface unit connected to said first component and to said second component by a bus line; a CPU connected to said bus interface unit by a local bus; an address control register associated with said bus interface unit, said address control register including a dedicated bit to indicate the location of said second component; a configuration register also associated with said bus interface unit, said configuration register including a dedicated bit to indicate whether the bus interface unit is to perform the data merger between said first register and said second register; and a second configuration register in said first component, said second configuration register including a bit indicating whether said first component is authorized to respond to an access to said address value.