1. A processor comprising: first circuitry to track, on a hardware thread by hardware thread basis, whether a hardware thread is in a state in which its TLB information is to be flushed; second circuitry coupled to said first circuitry to provide information so that said information is visible to software, said information identifying specific hardware threads that are in a state in which their respective TLB information is to be flushed; and power management circuitry to place said processor in a power state that is to flush TLB information of hardware threads from the hardware threads' respective processing core.