1. In a cache memory having a first cache unit chip holding a first program word address register for receiving even addresses, and a second cache unit chip holding a second program word address register for receiving odd addresses, a system for insuring that the even address residing in said first program word address register is coherent with the odd address residing in said second program word address register at all time periods of operation, said system comprising: (a) said first cache unit chip including: (a1) a first data memory holding a first group of data words having even addresses; (a2) a first tag memory holding a group of even addresses corresponding to said first group of data words; (a3) first cache controller means for addressing said first tag memory; (a4) said first program word address register for holding the next even address of the program word to be executed; (b) said second cache unit chip including: (b1) a second data memory holding a second group of data words having odd addresses; (b2) a second tag memory holding a group of odd addresses corresponding to said second group of data words; (b3) second cache controller means for addressing said second tag memory; (b4) said second program address word register for holding the next odd address of the program word to be executed; (c) intercommunication means between said first and second cache unit chip to simultaneously maintain coherency of address content, at all time periods, between said first and second program address word registers.