1. A microcode computer wherein each of a plurality of machine instructions is implemented by executing a corresponding series of microinstructions, the computer comprising: a memory for storing said machine instructions therein, an arithmetic logic unit which receives and executes said microinstructions but does not receive said machine instructions, an instruction processing unit for receiving and decoding said instructions received from said memory, to produce an entry address for the first microinstruction corresponding to a decoded machine instruction; a dispatch control store connected to receive said entry address and having stored therein the first microinstruction for each of said machine instructions, said dispatch control store producing a selected one of said microinstructions stored therein as determined by said entry address, a main control store for storing therein all of said microinstructions for each of said machine instructions other than the first microinstruction for each of said machine instructions; a microsequencer for generating addresses for said main control store for producing corresponding microinstructions from said main control store, a control store buffer connected to receive and store microinstructions from both said dispatch control store and said main control store, said control store buffer providing a portion of said first microinstruction from said dispatch store to said microsequencer for generating a second microinstruction address for said main control store, said main control store for providing said second microinstruction and sequentially the remaining microinstructions of said decoded machine instruction to said control store buffer, registers connected between said control store buffer and said arithmetic logic unit for transferring said microinstructions from said control store buffer to said arithmetic logic unit for execution therein, and means for transferring operands between said memory and said arithmetic logic unit in response to said microinstructions executed in said arithmetic logic unit.