1. A computer architecture comprising: a plurality of computing cores programmed to execute a plurality of commands, the commands being decomposed into a plurality of node networks whereby each node network corresponds to a command in the plurality of commands and includes one or more nodes corresponding to execution dependencies of the command, the plurality of node networks are mapped to a plurality of systolic arrays, wherein each systolic array comprises a plurality of cells and wherein nodes in each node network are mapped to a cell in the plurality of cells, each cell in each systolic array is mapped to a computing core in the plurality of computing cores; an input interface coupled to the plurality of computing cores, the input interface being configured to receive input data in fixed packets; and an output interface coupled to the plurality of computing cores and configured to transmit output data from the plurality of computing cores to an order book.