1. A video processor comprising: an input for receiving a Direct-Current (DC) block, said DC block comprising a plurality of DC values; an internal register for storing said plurality of DC values; a multiplier, comprising a Hadamard transform matrix and configured to receive Single Instruction Multiple Data (SIMD) instructions, wherein upon receiving a first transform SIMD instruction, said multiplier operable to perform a 1-D Hadamard transform of said plurality of DC values using said Hadamard transform matrix, operable to produce a partially transformed plurality of DC values, and further operable to write said partially transformed plurality of DC values directly in a transposed manner to said internal register as transposed plurality of DC values to save processor cycles; and wherein upon receiving a second transform SIMD instruction, said multiplier is operable to perform a 1-D Hadamard transform of said transposed plurality of DC values using said Hadamard transform matrix, producing a Hadamard transformed plurality of DC values, and is operable to write said Hadamard transformed plurality of DC values directly in a transposed manner to said internal register to save processor cycles.