1. A system comprising: a processor coupled to a platform control hub, an external voltage regulator and an embedded controller, the processor having a sustain power plane including: a cache memory to store a processor context, a wake logic to handle processor wakeup and context restore, and an input/output (I/O) interface coupled between the processor and the platform control hub; wherein the processor is to enter a connected standby sleep state upon: receipt of a timer signal from the wake logic; gating of a clock of the processor; powering of the cache memory with a dedicated power plane separate from the sustain power plane; powering down of remaining components powered by the sustain power plane and powering down of the sustain power plane; redirection of wakeup sources for handling processor wakeup and context restore to the platform control hub; and the external voltage regulator coupled to the processor; and the embedded controller coupled to the processor.