1. A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, which embedded system provides a parallelized hardware and software implementation of the original computer program, which parallellized implementation satisfies one or more predetermined criteria regarding hardware constraints of the embedded system, characterized by a step of analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain control data flow graphs with static data dependencies and static data types, and a step of executing the executable on a host computer using test data, comprising observing a working memory of the host computer during the executing of the executable identifying sets of load and store operations of the original computer program that access the same memory locations as dynamic data dependencies, and representing said dynamic data dependencies in a dynamic tree, a step of representing the static data dependencies in a static tree from the obtained control data flow graphs, a step of merging the static tree and dynamic tree into a merged tree, being a data structure capturing the behavior of the original computer program, where in the merged tree the static data dependencies in the static tree are complemented with the dynamic data dependencies in the dynamic tree, a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying in the merged tree at least one dynamic data dependency that crosses a thread boundary, which dependency comprises a particular communication pattern that observes ordering relations among a set of load and store operations, where the store operations of the set are on a side of the thread boundary opposite to the side of the load operations, identifying in the control data flow graph the load and store operations from the merged tree that have the particular communication pattern to provide identified load and store operations, and converting said identified load and store operations in the identified control data flow graph from said dynamic data dependency into read/write access to a buffered communication channel with read/write access, by transforming instructions in the intermediary computer program that correspond to said identified load and store operations in the control data flow graph into instructions that implement said buffered communication channel with read/write access, the intermediary computer program employing a process network representing an assignment of program elements to processes or threads and an assignment of read and write operations in a transformed intermediary computer program to buffered communication channels between processes, using said process network, and a step of building the parallelized hardware and software implementation from the transformed intermediary computer program, comprising a step of compiling the transformed intermediary computer program to obtain the software implementation, wherein the parallelized hardware and software implementation are generated via a generate step that generates an architecture description and involves an acceleration step to convert the program function into register transfer level, which are then subjected to an integrate process, and wherein the parallelized hardware and software implementation exhibit an implementation of the process network and operate in parallel without further dynamic data dependency analysis.