1. A method of a designer generating a hardware design for an integrated circuit, comprising: generating a first hardware sub-design at the designer; receiving a second hardware sub-design and a license from an IP block owner, the second hardware sub-design including a license verification sub-design, wherein the license is generated based on a trusted host identifier of the integrated circuit; and uploading said first hardware sub-design and said second hardware sub-design to the integrated circuit having the trusted host identifier, the license verification sub-design enabling said second hardware sub-design based on a validation of the license with the trusted host identifier.