1. An integrated circuit comprising: a differential input buffer having a first input coupled to a first pad and a second input coupled to a second pad; a single-ended input buffer having an input coupled to the first pad; and a serial-to-parallel converter having: a data input selectably coupled to an output of the single-ended input buffer or an output of the differential input buffer; and a clock input selectably coupled to a low-speed clock signal or a high-speed clock signal.