1. A non-volatile memory device, comprising: a first wordline (WL); a first local bitline (LBL); a first global bitline (GBL); a first re-writable non-volatile two-terminal memory element positioned between the first WL and the first LBL; a first transistor with a first terminal coupled to the first LBL and a second terminal coupled to the first GBL; and a second transistor with a gate coupled to the first LBL and a first terminal coupled to the first GBL.