1. A processor for scheduling a request to a deterministic finite automata-based graph thread engine (DTE) workstation, the processor comprising: a selector configured to select a request from an instruction queue and to extract from the selected request, a graph identifier for a deterministic finite automata-based (DFA) graph associated with the selected request; a scheduling table configured to provide placement information for choosing which of a plurality of DTE workstations, including one or more DTE workstations allocated to process requests associated with the DFA graph, to send the request to be processed, the placement information being provided based on the graph identifier extracted from the selected request; and an assigner configured to determine which of the plurality of DTE workstations to send the request to be processed, based on the placement information.