1. A finite impulse response (FIR) filter, implemented in hardware, configured to receive an input signal and generate an output signal, the filter comprising: a plurality of first stages, each stage of the plurality of first stages having an order of four or greater; and one or more second stages, each stage of the one or more second stages having an order less than four, wherein the one or more second stages and the plurality of first stages are coupled together in cascade and wherein a total order of the plurality of first stages is higher than a total order of the one or more second stages, and wherein at least one of the plurality of first stages comprises a pairing of two 2 nd order factors to make a 4 th order factor, and wherein at least one of plurality of first stages includes a stage having a coefficient that is not any one of 1, 0, or −1.