1. A semiconductor memory device comprising an error detection and correction system with an error correcting code over Galois field GF(2 n ), wherein the error detection and correction system includes an operation circuit configured to execute addition/subtraction with modulo 2 n −1, and wherein the operation circuit includes a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2 n −1), which perform addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2 n −1.