1. A processor core having an out-of-order pipeline, comprising: an instruction identification generator that generates instruction identification tags used to identify a program order of instructions; and a mispredict instruction identification checker that compares a first instruction identification tag associated with a first control transfer instruction to a second instruction identification tag stored in a register of the mispredict instruction identification checker, the second identification tag being associated with a second control transfer instruction, wherein if the comparison of the first instruction identification tag and the second instruction identification tag indicates that the first control transfer instruction executed out of program order relative to the second control transfer instruction, the mispredict instruction identification checker generates a signal that enables instruction fetching to be redirected in accordance with a program counter value associated with the first control transfer instruction.