1. A host system comprising a processor, the processor including: a branch counter register configured to store a count of branch instructions occurring within a sequence of instructions executed by the processor; an inter-branch instruction counter register configured to store a count of instructions occurring between two consecutive branch instructions within the sequence of instructions; and a counter control unit connected to the branch counter register, to the inter-branch instruction counter register, and to an instruction decoder module of the processor, the counter control unit comprising hardware logic configured to trigger a switch event within the processor according to a value stored in the branch counter register and according to a value stored in the inter-branch instruction counter register, wherein the switch event causes the processor to switch from executing the sequence of instructions to executing an event handler routine.