1. An ASIC device comprising: a first wafer comprising a plurality of microcircuit components; an M3 level masked on said first wafer, said M3 level comprising a first unique mask; a V3 level masked on said M3 level, said V3 level comprising a second unique mask; an M4 level masked on said V3 level, said M4 level comprising a third unique mask; and an M5 level masked on said M4 level.