1. In a microprocessor system comprising a CPU, a cache memory coupled to said CPU having cache line locations associated with addresses in said microprocessor system, a main memory, and a write buffer coupled to said main memory a concurrent cache line replacement method comprising the steps of: (a) initiating a read access to a first address in said microprocessor system; (b) in the event of first predesignated conditions, initiating writing of a first d-word from a first d-word location in a cache line in said cache memory to said write buffer, and simultaneously initiating reading of a second d-word from said main memory, wherein said cache line stores a plurality of d-words; (c) writing said second d-word into said first d-word location in said cache memory and to said CPU upon completion of writing said first d-word to the write buffer; (d) upon completion of writing said second d-word, initiating writing a next d-word of the plurality of d-words stored in the cache line at a next d-word location to said write buffer and simultaneously initiating reading of a next d-word from the main memory; (e) writing said next d-word read from main memory into said next d-word location in said cache memory and to said CPU upon completion of writing said next d-word to the write buffer; (f) repeating steps (d) and (e) until the plurality of d-words stored in the cache line are written to the write buffer and a plurality of d-words are read from main memory and stored in the cache line; and writing the plurality of d-words from said write buffer to said main memory.