1. A semiconductor device, comprising: a first processor chip comprising a first processor; a second processor chip comprising a second processor; wherein the first and second processor chips are connected in a stacked configuration, wherein the first and second processors are vertically aligned and connected through vertical connections, and wherein the vertically aligned first and second processors are configured to operate as a single logical processor and commonly share a plurality of input/output ports; and a mode control circuit configured to: (i) generate different sets of configuration parameters to operate the single logical processor in different power operating modes; (ii) generate a first control signal to selectively input a first set of the configuration parameters to the single logical processor; and (iii) generate a second control signal to selectively input a second set of the configuration parameters to the single logical processor; wherein the single logical processor is configured to (i) utilize the first set of the configuration parameters to operate the single logical processor in a first power operating mode wherein the first processor is turned on and the second processor is turned off; and (ii) utilize the second set of the configuration parameters to operate the single logical processor in a second power operating mode wherein both the first processor and the second processor are turned on; wherein in the second power operating mode, both the first processor and the second processor operate at less than full power so that a total power of the single logical processor in the second power operating mode is substantially the same as a total power of the single logical processor in the first power operating mode when only the first processor is turned on and operating at full power.