1. An apparatus for processing an instruction for accessing an N-dimensional tensor, the apparatus comprising: for each dimension of the N-dimensional tensor, a partial address offset value element that stores a partial address offset value for the dimension, the partial address offset value for each dimension being based at least on an initial value for the dimension, a step value for the dimension, and a number of iterations of a loop for the dimension, wherein each partial address offset value element comprises hardware storage circuitry; one or more hardware adders; and one or more hardware processors configured to execute one or more instructions of an instruction set executable by the one or more hardware processors, wherein execution of the one or more instructions causes the one or more hardware processors to perform operations comprising: obtain an instruction to access a particular element of the N-dimensional tensor, wherein the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and wherein N is an integer that is equal to or greater than two; obtain, for each dimension of the N-dimensional tensor, a current partial address offset value for the dimension from the partial address offset value element for the dimension; determine, using the one or more hardware adders, a memory address of the particular element, including determining, using the one or more hardware adders, a sum of the obtained current partial address offset values, the determined memory address of the particular element being different from a value of the particular element stored at the determined memory address of the particular element; output data indicating the determined address for accessing the particular element of the N-dimensional tensor; and update the partial address offset value for at least one of the dimensions by adding, using the one or more hardware adders, the step value for the at least one dimension to the current partial address offset value for the at least one dimension.