1. A microprocessor instruction fetcher for accessing an instruction cache using a virtual fetch address, for each of a plurality of threads, comprising: a macro-TLB to cache physical address translations for memory pages for the plurality of threads; a micro-TLB to cache a plurality of translation entries for a subset of the memory pages cached in the macro-TLB; and a plurality of nano-TLBs, each nano-TLB associated with a respective one of the plurality of threads to cache a physical address translation of at least one memory page for the respective one of the plurality of threads.