1. A processing system for performing data processing operations in response to a single-instruction multiple data (SIMD) data processing instruction, comprising: at least two registers, each of the at least two registers storing a vector having at least three fields, each field for storing a multiple-bit vector element; first control circuitry, the first control circuitry, in response to the SIMD data processing instruction, comparing multiple-bit vector elements in respective corresponding fields of the at least two registers to create a plurality of condition values, the plurality of condition values comprising at least three condition values; second control circuitry for receiving the plurality of condition values and performing one or more predetermined logic operations on one or more subsets of the plurality of condition values, wherein each of the one or more subsets includes less than all of the plurality of condition values and more than one condition value of the plurality of condition values, to generate a condition code for each of the one or more subsets; and a condition code register for storing the condition code for each of the one or more subsets.