1. A method for performing a fused multiply-and-add operation, said method comprising: performing Booth-encoding on a first operand by a Booth encoder; multiplying said encoded first operand by a second operand by a fraction multiplier to produce a set of partial products and to reduce said partial products to a set of sum and carry vectors, wherein one of said sum vectors includes a high sum vector and a low sum vector, and one of said carry vectors includes a high carry vector and a low carry vector; generating a set of carry correction factors via a carry corrector to correct an artifact carry bit when said first operand is less than a full-precision of said fused multiply-adder, wherein said carry correction factors are determined by S M OR C M , wherein said S M is a boundary bit position located between said high sum vector and said low sum vector, said C M is a boundary bit position located between said high carry vector and said low carry vector; and operation on said sum and carry vectors, said set of carry correction factors by using an adder, and a third operand to produce a final result of said fused multiply-and-add operation.