1. A modulation policy for a modular multi-level convertor, wherein, the switching state of each submodule is determined by combining the current direction in each bridge arm and the capacitive voltage order of the submodule on the basis of a carrier stacking method, comprising: (1) employing N triangular carrier waves with the same amplitude value, frequency, and phase position, and stacking them into a region within −1˜1 vertical coordinate range, i.e., carrier waves 1, 2,. .. , N when counted from bottom to top; after comparing a modulation wave with the N carrier waves, outputting ‘1’ as the comparison result if the value of the modulation wave is greater than the value of a triangular carrier wave, on the contrary, output ‘0’ as the comparison result if the value of the modulation wave is smaller than the value of a triangular carrier wave; through comparison, obtaining N PWM pulses, i.e., PWM 1 , PWM 2 , PWM N , which are in one-to-one correspondence to the triangular carrier waves; negating the N PWM pulses, to obtain N PWM pulses PWM 1 ′, PWM 2 ′, PWM N ′; (2) measuring the current i au in the upper bridge arm and the current i ad in the lower bridge arm of each phase, and measuring the capacitive voltages u cu1 , u cu2 ,. .. , u cuN of the submodules in the upper bridge arm and the capacitive voltages u cd1 , u cd2 ,. .. , u cdN of the submodules in the lower bridge arm at the same time, at a beginning of a voltage balance control period; (3) sorting the capacitive voltages of the submodules in the upper bridge arm and the lower bridge arm measured in step (2) in ascending order respectively, and keeping the sorting result unchanged within a voltage balance control period; putting the sequence numbers of the submodules sorted by capacitive voltage in the upper bridge arm into an array t u [i], and putting the sequence numbers of the submodules sorted by capacitive voltage in the lower bridge arm into an array t d [i]; (4) allocating PWM pulses of the submodules in the upper bridge arm and lower bridge arm according to the capacitive voltage sorting result of the submodules and the current direction in bridge arm; for the upper bridge arm, allocating the N PWM pulses PWM 1 , PWM 2 ,. .. , PWM N obtained in step (1) to the submodules SM( tu[1] ), SM( tu[2] ),. .. , SM( tu[N] ) in sequence, if the current in the upper bridge arm is i au >0; otherwise allocating the N PWM pulses PWM 1 , PWM 2 ,. .. , PWM N obtained in step (1) to the submodules SM(t u [N]), SM(t u [N−1]),. .. , SM(t u [1]) in sequence if the current in the upper bridge arm is i au <0; for the lower bridge arm, allocating the N PWM pulses PWM 1 ′, PWM 2 ′,. .. , PWM N ′ obtained in step (1) to the submodules SM( td[N] ), SM( td[N-1] ),. .. , SM( td[1] ) in sequence, if the current in the lower bridge arm is i du >0; otherwise allocating the N PWM pulses PWM 1 ′, PWM 2 ′,. .. , PWM N ′ obtained in step (1) to the submodules SM(t d [1]), SM(t d [2]),. .. , SM(t d [N]) in sequence if the current in the lower bridge arm is i du <0.