1. A method for vector processing in an active memory device that includes memory and a processing element, the method comprising: decoding, in the processing element, an instruction comprising a plurality of sub-instructions to execute in parallel; determining an iteration count to repeat execution of the sub-instructions in parallel based on decoding an iteration count source field of the instruction that defines whether to set the iteration count based on an iteration count field of the instruction or based on an iteration count register; repeating execution of the sub-instructions in parallel for multiple iterations, by the processing element, based on the iteration count; accessing multiple locations in the memory in parallel based on the execution of the sub-instructions; identifying a lane control sub-instruction in the instruction based on the decoding of the instruction, the lane control sub-instruction controlling a sequence of instruction execution and positioned in parallel with the sub-instructions to execute in parallel; and executing the lane control sub-instruction, by the processing element, only once after execution of the sub-instructions is performed in parallel for multiple iterations.