1. A method for concurrently optimizing multiple routing objectives during routing of an integrated circuit (IC) chip design, the method comprising: receiving a routing solution for the IC chip design and a set of routing objectives; partitioning the IC chip design into a set of partitions; and for each partition in the set of partitions, optimizing the routing solution by, iteratively: analyzing the routing solution to determine weights for the set of routing objectives; constructing a cost function based on the weights for the set of routing objectives; and modifying the routing solution within the partition to attempt to optimize the cost function.