1. A method for timing analysis using a processor, comprising: using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and one of the group consisting of a second ILV and a device as a function of at least different frequency values, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determining an effective capacitance value corresponding to each respective impedance value; providing at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and conducting an RC extraction of a design layout of an ILV circuit using the populated table and based on determined effective capacitance values therein.