1. A method of design rule checking of a dataset of a circuit layout, comprising: before using a design rule checker to validate the dataset against a plurality of design rules: comparing a plurality of patterns within the dataset against a plurality of design waivers, and designating a pattern within the plurality of patterns that matches a design waiver as a valid pattern, wherein the design waiver comes from the plurality of design waivers; and using the design rule checker, via a computer system, to validate only patterns within the plurality of patterns that are not designated a valid pattern.