1. An engineering-change method of a semiconductor circuit comprising: a placement and routing step of carrying out placement and routing and logical optimization using a first netlist to generate a second netlist and a first layout that undergo logical optimization; an engineering-change step of making logical changes in design for the first netlist to generate a third netlist; an engineering-change and formal verification step of conducting formal verification of the second netlist and the third netlist to generate a fourth netlist by changing the second netlist such that the fourth netlist becomes logically equivalent to the third netlist; and a layout generating step of generating a second layout by changing the first layout such that the second layout matches the fourth netlist.