1. A computer-implemented method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design, said method comprising: receiving, by a computer, a layout of a wire layer from said IC chip design; identifying, by said computer, a signal gate-circuit comprising a signal gate and segments of wires and vias, including electrically parallel paths, connected to an output of said signal gate from said layout of said wire layer; simulating, by said computer, switching transitions of said signal gate-circuit; based on widths for each of said segments, determining from stored data of a technology, by said computer, a maximum current of each of said segments at a standard corner of a timing analysis; calculating, by said computer, an average current output to each of said segments by said signal gate-circuit at said standard corner of said timing analysis; computing, by said computer, an EM limiting current ratio by dividing said average current of each of said segments by said maximum current of each of said segments; identifying, by said computer, an EM current limiter from each of said segments based on a highest value of said EM limiting current ratio; computing, by said computer, a parallel paths uplift factor for a maximum EM current output by dividing a total average current output by said signal gate by said average current of said EM current limiter; and storing in a design library, by said computer, said maximum EM current output, which equals said parallel paths uplift factor multiplied by said maximum current of said EM current limiter.