1. Apparatus comprising: a semiconductor substrate; a plurality of interface processors formed on said substrate, the number of said processors being at least five; internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors; internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors; said internal data memory having a plurality of memory elements, the number of said memory elements being correlated to the number of said interface processors; a request controller operatively interposed between each of said interface processors and said memory elements and controlling the flow of requests from data from said interface processor to said memory elements; a memory arbiter operatively interposed between each of said memory elements and said interface processors and controlling access to said memory element by said interface processors; each of said interface processors having access to a plurality of said memory elements and each of said memory elements being responsive to requests from a plurality of said interface processors; and a plurality of input/output ports formed on said substrate; at least one of said input/output ports connecting said internal data memory with external data memory; and at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors.