1. In a video system controller adapted to transfer data between a microprocessor and a display memory in a bit-mapped video display system, said video system controller comprising addressing means for storing a display memory address from said microprocessor and for presenting said display memory address to said display memory, display controller means for synchronizing a video display with said display memory, arbiter logic for choosing whether said microprocessor or said video display shall have access to said display memory via said video display controller, and memory cycle generator means for generating the memory cycle information required for reading or writing said display memory, the improvement comprising: a first sequential logic block in said memory cycle generator means comprising: a data input for receiving digital data; a data output for presenting digital data; a clock input for receiving clock pulses; and a plurality of logic cells connected to said data input and said data output, said plurality of logic cells responsive to a clock pulse received by said clock input to cause said output to present data dependent solely upon the data received by said data input during prior clock pulses; and a second sequential logic block in said memory cycle generator means comprising: a data input for receiving digital data; a data output for presenting digital data; a clock input for receiving clock pulses; and a plurality of logic cells connected to said data input and said data output, said plurality of logic cells responsive to a clock pulse received by said clock input to cause said output to present data dependent upon the data received by said data input during prior clock pulses; wherein said logic cells in said first and said second sequential logic blocks comprise substantially the same circuit components which are interconnected dependent upon the desired responsive behavior of said logic cells; and wherein said memory cycle information is comprised of the outputs of said first and said second sequential logic blocks.