1. Apparatus for processing data, said apparatus comprising: a processor for generating virtually addressed data access requests to virtual addresses, said virtual addresses being mapped to physical addresses using a plurality of page table entries, each page table entry having a page size corresponding to a number of contiguous virtual addresses mapped to contiguous physical addresses with said page table entry; and a cache memory having one or more cache ways, each of said cache ways comprising a plurality of cache rows and receiving said data access requests from said processor, said cache memory being virtually indexed and physically tagged; wherein each of said one or more cache ways stores data values for a block of virtual addresses larger in size than a minimum page size such that a plurality of different virtual addresses corresponding to different cache rows within one of said one or more cache ways can have respective page table entries mapping to a common physical address; and further comprising: aliasing management logic for managing coherency between data values within different cache rows of a plurality of different virtual addresses within a cache way mapping to a common physical address, each of said different cache rows concurrently storing a valid copy of data values stored at said common physical address.