1. A data processing architecture comprising: a parallel array of processing elements arranged in a single instruction multiple data processing array; a hardware accelerator unit operable to receive, in series, processing requests from the processing elements and to return processing results to respective processing elements when those processing results are available; and an input/output system which is operable to transfer respective processing requests from the processing elements to the hardware accelerator, and to return processing results to the processing elements concerned, wherein the processing elements are operable to process the returned processing results when all such results are returned, or after a predetermined time period.