1. An integrated circuit comprising a field programmable gate array having: (a) at least one look-up table having a plurality of input terminals and an output terminal; (b) a decoder circuit arrangement coupled to said output terminal of said at least one look-up table, said decoder circuit arrangement including: (i) a multiplexing circuit having an address selector terminal and at least one input terminal, said at least one input terminal being connected to said output terminal of said at least one look-up table; and (ii) a decoder circuit having a plurality of inputs, said decoder circuit being coupled to said address selector of said multiplexing circuit.