1. A multi-level memory comprising: an electrically programmable memory cell having at least an erased state, a first programming state and a second programming state, and a programming circuit for programming data by repeating a programming operation by applying a programming voltage to said memory cell, a first programming verification operation for confirming whether said memory cell has reached said first programming state after said programming operation, or a second programming verification operation for confirming whether said memory cell has reached the second programming state after said programming operation, wherein said programming circuit repeats said programming operation and said first programming verification operation except for said second programming verification operation in a first period of data programming, and repeats said programming operation, said first programming verification operation and said second programming verification operation in a second period after the first period of data programming.