1. A content addressable memory (CAM) device including a plurality of independently configurable CAM groups, each CAM group comprising: a number of CAM rows, each CAM row including a plurality of CAM cells coupled to a match line that generates a row match signal during a compare operation between a search key and data stored in the CAM row; and a programmable combinational logic circuit for logically combining the row match signals to generate a corresponding group match signal according to a respective one of a plurality of selectable logical operations selected by a corresponding function select signal, wherein the plurality of selectable logical operations include a logic AND operation, a logic OR operation, and a logic NOT operation.