1. A layout of an integrated circuit chip comprising: a plurality of input/output blocks positioned around the perimeter of said integrated circuit chip; a core logic region positioned away from said perimeter; an interface region positioned between said plurality of input/output blocks and said core logic region, said interface region including first lines connectable to said core logic region and extending into said input/output blocks, and second lines connectable to said core logic region, pairs of said second lines being connected together in said interface region, each line of said pair of second lines being connectable to the same portions of said core logic region as one of said first lines; whereby said integrated circuit chip layout can be replaced by an integrated circuit chip layout having a smaller core logic region by decreasing the number of said input/output blocks positioned around the perimeter and altering said interface region to replace pairs of said first lines with pairs of said second lines.