1. A split very long instruction word (VLIW) processing apparatus comprising: a VLIW central processor comprising: a set of functional units which receive a plurality of instructions for execution in parallel; a first VLIW program cache which holds a collection of very long instruction words, each very long instruction word comprising a set of instruction fields, each instruction field comprising an instruction to be executed by a functional unit; a dispatch unit which scans bit fields within said instruction fields to decide how many instructions to dispatch in parallel and to which functional unit to direct each instruction; one or more register files coupled to said functional units; an external memory interface which carries instructions and data from an external source; and an on-board data memory coupled to said functional units, said register files, and said external memory interface, wherein: at least one of said functional units includes a branch processing unit which processes branch instructions; said branch processing unit is coupled to a prefetch unit used to sequence said VLIW control words from said VLIW program cache or external memory; and said branch processing unit is coupled to an external interface for transferring branch related information; a VLIW extension processor which cooperates with said VLIW central processor to jointly execute a single VLIW program, said VLIW extension processor comprising: a set of at least one functional unit which receives one or more instructions for execution in a given clock cycle; a second VLIW program cache which holds a collection of very long instruction words, whereby each very long instruction word comprises one or more instruction fields, wherein each instruction field comprises an instruction to be executed by a functional unit; and a second dispatch unit which scans bit fields within said instruction fields to decide how many instructions to dispatch in parallel and to which functional unit to direct each instruction, wherein at least one of said functional units includes a second branch processing unit which processes branch instructions, said branch processing unit coupled to a prefetch unit which sequences VLIW control words from said second VLIW program cache, said branch processing unit coupled to a second external interface which transfers branch related information.