1. A processor, comprising: a plurality of functional units each having at least one output event signal of a plurality of event signals for indicating an occurrence of a plurality of differing events within said processor; and a weighted performance counter having inputs for receiving said plurality of event signals and updating a performance count according to states of said plurality of event signals, wherein a change in said performance count according to at least two of said plurality of events is differently weighted, and whereby a latency between accumulation of performance metrics corresponding to said events is reduced and said events are further separately weighted according to their correlation to performance of said processor.