1. In a microprocessor system using pipelined instruction processing, a method for accessing multiple entries from a branch history table (BHT) in a single clock cycle, the method comprising: accepting a first microprocessor instruction of consecutive operations at a fetch stage in a pipelined microprocessor execution process; in a first clock cycle, fetching a plurality of conditional branch instructions associated with a corresponding plurality of instruction addresses; accessing a value from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction; left-shifting the GHR value; hashing an instruction address associated with the fetched conditional branch instruction with the left-shifted GHR value, creating a hash result; using the hash result to access a word in an indexed BHT stored in a single-port random access memory (RAM), the word comprising a branch direction count for each of the fetched conditional branch instructions; executing a conditional branch instruction at an execute stage in a second clock cycle; and, in the second cycle, writing the BHT with an updated branch direction count in response to a resolution of the executed conditional branch instruction.