1. A computer system comprising: a plurality of memory segments, each of the plurality of memory segments having a first channel comprising a first memory capacity and a second channel comprising a second memory capacity different than the first memory capacity; a memory controlling system coupled to each of the plurality of memory segments via a respective bus segment, the memory controlling system being adapted to write data on each of the first and second channels of each of the plurality of memory segments; and a host/data controller coupled to the memory controlling system, the host/data controller determining the data capacity of each of the first and second channels of the respective plurality of memory segments, selecting a smallest memory capacity common to each of the first and second channels of the plurality of memory segments, and designating the smallest common memory capacity as an interleaving region for each of the plurality of memory segments.