1. A microprocessor, comprising: fetch logic for retrieving an instruction; decode logic configured to identify an arithmetic add operation specified in the instruction; and execution logic configured to receive operands specified by the instruction and including, a primary logic path configured to perform the arithmetic add operation on such operands to produce a primary result, and a secondary logic path, arranged in parallel to the primary logic path, that is configured to output metadata associated with the primary result of the arithmetic add operation, such metadata indicating whether or not the primary result is equal to zero and being generated by comparing an XOR vector of the operands with a shifted OR vector of the operands.