1. A system for optimizing processor operations, comprising: a transmission source configured to provide priority information for use by an electronic device; a cache memory coupled to said transmission source and configured for temporarily storing said priority information, said cache memory including an isochronous cache that is reserved for storing only said isochronous data on a priority basis, said cache memory also including an asynchronous cache that is configured to store asynchronous data on a non-priority basis; and a processor coupled to said cache memory for utilizing said priority information from said cache memory.