1. In a stored program computer comprising a plurality of data processors, a common control system comprising: (a) a master controller, operatively connected and responsive to said plurality of data processors, and a plurality of subcontrollers wherein each of said master controller and subcontrollers has a specific function and responsibility for a plurality of said processors and wherein each of said master controller and subcontrollers is autonomous with respect to its function and responsibility; and (b) memory register means for interconnecting said master controller and subcontrollers in a fixed hierarchy of control, said master controller being bilaterally connected to at least one of said subcontrollers through said memory register means, said subcontrollers being bilaterally connected to at least the next least and next most significant subcontrollers in said hierarchy through said memory register means.