1. A parallel data processor system for maintaining the consistency of data blocks, each block containing a plurality of bits of data and a master flag bit, said means for maintaining comprising: a main memory for storing blocks of data, a plurality of caches, each storing a plurality of addressable data blocks, each cache comprising a first and second data port and each data block comprising data and a master flag bit. one data bus connecting the main memory and the first port of all caches, a processor associated with each cache and connected to the second port of its associated cache, means in each cache for allowing the processor to write into an addressed data block comprising, (a) if the block is contained in the associated cache, means for setting the master flag in that cache, means for writing into any other cache that is sharing the block, means for resetting the master flag in all other caches, and means for allowing the processor to write into the block of the associated cache, or (b) if the block is not contained in the associated cache, means for reading the block from another cache if any other cache has the block with the master flag set for that block, or from main memory otherwise, means for setting the master flag in the associated cache and resetting the master flag in all other caches, and (c) means for allowing the processor to write into the block of the associated cache, and means each cache for allowing the processor to read from an addressed block comprising, (a) if the block is in the associated cache, means for allowing the associated processor to read from the block, or (b) if the block is not in the associated cache, means for reading it into the associated cache from the cache having the block in which the master flag is set, or for reading it from memory otherwise, and (c) means for allowing the associated processor to read from the block.