1. A memory controller for accessing memory, said memory controller comprising: at least one stream buffer, said at least one stream buffer being a FIFO and buffering data, control registers, said control registers receiving stream parameters from a data processor, a memory scheduling unit for decoupling memory access requests from a processor to enable access of data elements in an order that increases effective bandwidth over a program's natural order and that reduces average memory latency for data patterns, wherein a data processor sends said stream parameters to said control registers identifying data streams to be accessed and said memory scheduling unit generates memory addresses of the data elements based on said stream parameters and accesses the data elements in a dynamically determined order.