1. A hardware simulation system having a simulation model of a logic design to be simulated in a hardware simulation accelerator, the hardware simulation accelerator comprising: at least one simulator chip having at least one logic evaluation unit having a plurality of programmable hardware resources; at least one instruction memory associated with each of the at least one logic evaluation unit in the at least one simulator chip, the instruction memory having a plurality of encoded instructions to simulate the simulation model using the hardware resources; the logic evaluation unit connected to receive the plurality of encoded instructions from its associated at least one instruction memory; an instruction decode logic connected to the at least one instruction memory and its associated logic evaluation unit to decode each of the plurality of the instructions into an opcode and a data part having a plurality of encoded bits, the opcode determining which of the plurality of hardware resources use which of the encoded bits of the data part.