1. A single event upset (SEU) immune three-input AND-NOR circuit comprising: primary p-channel CMOS transistors, T 1, T 3 and T 5, and redundant p-channel CMOS transistors, T 2, T 4 and T 6 ; and primary n-channel CMOS transistors, T 8, T 10 and T 12, and redundant n-channel CMOS transistors, T 7, T 9 and T 11 ; wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that, a first primary input, A1, is coupled with the gate of T 1 and the gate of T 12 ; a first redundant input, A2, is coupled with the gate of T 2 and the gate of T 11 ; a second primary input, B1, is coupled with the gate of T 3 and the gate of T 10 ; a second redundant input, B2, is coupled with the gate of T 4 and the gate of T 9 ; a third primary input, C1, is coupled with the gate of T 5 and the gate of T 8 ; a third redundant input, C2, is coupled with the gate of T 6 and the gate of T 7 ; the source of T 1 is coupled with a power supply; the drain of T 1 is coupled with the source of T 2 ; the drain of T 2 is coupled with the drain of T 4 ; the source of T 3 is coupled with the power supply; the drain of T 3 is coupled with the source of T 4 ; the drain of T 4 is coupled with the drain of T 2 ; the source of T 5 is coupled with the drain of T 2 and the drain of T 4 ; the drain of T 5 is coupled with the source of T 6 ; the drain of T 6 is coupled with an output, Y; the drain of T 7 is coupled with the output, Y; the source of T 7 is coupled with the drain of T 8 ; the source of T 8 is coupled with ground; the drain of T 9 is coupled with the output, Y; the source of T 9 is coupled with the drain of T 10 ; the source of T 10 is coupled with the drain of T 11 ; the source of T 11 is coupled with the drain of T 12 ; and the source of T 12 is coupled with ground.