1. A system for integrated sub-block interleaving and rate matching, the system comprising: a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm; a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm and modified according to a rate matching algorithm such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm as modified by the rate matching algorithm.