1. A solid state drive controller, comprising: a processor, the processor being configured to couple to an array of flash memory devices, the array comprising a plurality of dies, each die comprising a plurality of flash blocks (F-Blocks), each F-Block comprising a plurality of flash pages (F-Pages), at least some of the F-Page comprising at least one error correcting code page (E-Page), and at least some of the E-Pages comprising a variably-sized error correction code (ECC) portion and a corresponding variably-sized data portion, the variably-sized data portions within one F-Page defining, in the aggregate, an F-Page data portion, wherein the processor is configured to: define an S-Page that comprises a plurality of F-Pages from one or more of the plurality of dies; within the S-Page, store an E-Page error correction code within the variably-sized ECC portion of each E-Page within the F-Pages to correct an error within the corresponding variably-sized data portion; designate at least one F-Page having a largest size F-Page data portion among the F-Pages in the S-Page as a Check Page; and store a cross-F-Page error correction code within the at least one Check Page.