1. A method for fabricating an integrated memory cube which emulates a single memory chip architecture, said fabricating method comprising the steps of: (a) providing N memory chips (wherein N.gtoreq.2) each having M memory devices (wherein M.gtoreq.2), along with two parallel planar main surfaces and an edge surface; (b) providing a logic chip having two parallel planar main surfaces and an edge surface; (c) forming a stack by securing the N memory chips and the logic chip together such that at least one planar main surface of each chip in the stack is coupled to a planar main surface of an adjacent chip in the stack, and such that the edge surfaces of the memory chips and the edge surface of the logic chip align to form at least one side surface of the stack, the stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack: and (d) electrically intercom mating the logic chip and the N memory chips, said logic chip coordinating external communication with the N memory chips of the stack so that an integrated memory structure exists which emulates the functional characteristics of a single memory chip structure with N.times.M memory devices.