1. A processing network comprising: a plurality of processing elements on a programmable microchip, wherein each of the processing elements have one or more instruction tables each including one or more blocks; a plurality of on-chip routers on the microchip for routing the data between the processing elements, wherein each of the on-chip routers is communicatively coupled with one or more of the processing elements; and a compiler stored on a non-transitory computer-readable memory and comprising an instruction table mapper that maps one or more instructions derived from assignments of a source code into one or more lines of the blocks of the instruction tables.