1. A processing system, comprising: a predecoder configured to identify two or more instructions that perform computational operations on architectural data, wherein the instructions are combinable to form a single executable internal instruction; an instruction storage configured to merge two or more instructions that are identified as combinable to form a single, executable internal instruction that can perform computational operations on wide data which is wider than architectural data; and an instruction execution unit configured to execute the single, executable internal instruction on a hardware wide datapath by executing two or more merged operations associated with said two or more identified instructions and included in the single, executable internal instruction in parallel.