1. An easily testable integrated logic circuit, comprising: a combinational logic circuit receiving a plurality of first inputs and a plurality of second inputs for providing logic outputs; a feedback shift register having an output and including a plurality of first through n-th series-connected flip-flops each having an input and an output, said flip-flops receiving in parallel at least a portion of said logic outputs from said combinational logic circuit and advancing said outputs in series through said first through n-th flip-flops while feeding an output from at least one of said flip-flops back to the input of another of said flip-flops to thereby compress a signal sequence in said logic outputs, the output of any one of said flip-flops constituting the output of said feedback shift register; and means for selectively disconnecting the series connection of said flip-flops whereby each of said flip-flops receives and stores a respective one of said portion of said logic outputs received in parallel from said combinational logic circuit, at least a portion of said outputs of said flip-flops being fed back in parallel as said second inputs to said combinational logic circuit when said series connection of said flip-flops is disconnected.