1. A processor comprising: a vector register comprising a plurality of data fields to store values of vector elements of data referenced in single instruction multiple data (SIMD) instructions; a decoder to decode a first instruction specifying: a destination operand, a size of the vector elements, a mask, and a source operand, wherein the mask is to identify a portion of the plurality of data fields in the source operand; and an execution unit operatively coupled to the decoder and the vector register and, responsive to the decoded first instruction, is to: read a plurality of values from unmasked data fields of the plurality of data fields of the vector register, wherein respective values of the plurality of values are of the size of the vector elements in the source operand, and wherein the plurality of values comprise at least eight values; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, to signal the detection of the inequality, set a mask field to a masked state for a corresponding detected unequal value with a flip of a bit value of the mask field.