1. A system comprising: a memory device having a n-bit multi-purpose register (MPR); and a memory controller coupled with the memory device, the memory controller to, for at least N combinations of N bits, wherein N is equal to the number of bits in the MPR: write a bit combination to the MPR over a non-swizzled address bus, read the bit combination from the MPR over a swizzled data bus, and generate a mapping of bit ordering between the memory device and the memory controller corresponding to the swizzled data bus, the memory controller to internally swizzle data using the mapping before writing the data to the memory so that the data appears in the correct order at pins of a memory chip, and on reads, the memory controller internally de-swizzles the data before performing error correction operations using the mapping.