1. A memory array, comprising: at least one string of series-coupled memory cells; a first select gate coupled to a first memory cell of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells for selectively coupling the particular string of series-coupled memory cells to a bit line; a second select gate coupled to a last memory cell of the particular string of series-coupled memory cells for selectively coupling the particular string of series-coupled memory cells to the bit line; a first select line coupled to a control gate of the first select gate; and a second select line coupled to a control gate of the second select gate; wherein each memory cell of the particular string of series-coupled memory cells is located between the first select line and the second select line.