1. A microprocessor for use in a system including program memory means and data memory means, each having address bus means and data bus means, comprising in combination: a data execution unit comprising general register array means having two access ports for simultaneously reading the contents of two registers from said general array means and two input ports for simultaneously writing in the contents of two registers, arithmetic-logic means coupled to receive operands from said access ports of the general register array means for performing selective operations to produce result signals, means for coupling said result signals to the data bus means of the data memory means, control means, including instruction register means for storing the current instruction being executed and timing means, for supplying control signals to control the execution of said current instruction; and an instruction fetch unit comprising address register array means having two access ports for simultaneously reading the contents of two registers from said address array means and two input ports for simultaneously writing in the contents of two registers, instruction counter means for storing the program memory address of the next instruction to be executed, means for coupling said instruction counter means to said program memory address bus, data addressing means for coupling the contents of said access ports of the address register array to the address bus means of said data memory means.