title: What is the behavior of __faststorefence?
body: <p>In regards to this question, I'm interested only in x86 and x86-64.<br>
  <br>
  For MSVC 2005, the documentation for __faststorefence says: <i>"Guarantees that every preceding <b>store</b> is globally visible before any subsequent <b>store</b>."</i><br>
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  For MSVC 2008 and 2010, it changed to: <i>"Guarantees that every previous <b>memory reference, including both load and store</b> memory references, is globally visible before any subsequent <b>memory reference</b>."</i><br>
  <br>
  The way the latter is written, it implies in my opinion that this would also block the CPU's reordering of loads before older stores.  This is different from the first definition, which implies that the intrinsic is only to deal with blocking or the reordering of non-temporal stores with older stores (the only other reordering x86(-64) does).<br>
  <br>However, then the documentation appears to contradict itself: <i>"On the x64 platform, this routine generates an instruction that is a faster <b>store fence</b> than the <b>sfence</b> instruction. Use this intrinsic instead of _mm_sfence on the x64 platform."</i><br>
  <br>
  This implies that it still has sfence-like functionality, and thus loads can still be reordered with older stores.  So which is it?  Can someone clear up my confusion?<br>
  <br>
  PS: looking for a GCC version of this function, I came across <code>long local; __asm__ __volatile__("lock; orl $0, %0;" : : "m"(local));</code> but I think it's from 32-bit code; what would be the 64-bit analog?</p>