title: MIPS Pipeline Cpu Architecture
body: <p>I'm dealing with the following exercise on which I can't really get my head around and any kind of help would be really appreciated. <br></p>
  
  <p>Considering this CPU:<a href="https://i.stack.imgur.com/1KmO5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1KmO5.png" alt="enter image description here"></a></p>
  
  <p>I have to: </p>
  
  <ol>
  <li>Determine how many total clock cycles are needed to complete all the instructions.</li>
  <li>Determine the content of the <strong>ID/EX</strong> register after 6 cc(clock cycles) since the beginning of the fist instruction.</li>
  </ol>
  
  <p>These are the instructions:<br>
          <code>0x450: addi $1, $4, -1</code><br>
  &ensp;&ensp;&ensp;&ensp;&ensp;     &ensp;<code>lw   $2, 0($1)</code><br>
  &ensp;&ensp;&ensp;&ensp;&ensp;     &ensp;<code>lw   $3, 0($2)</code><br>
  &ensp;&ensp;&ensp;&ensp;&ensp;     &ensp;<code>sw   $3, 80($1)</code><br></p>
  
  <p><br>
  I've tried to answer to the first question creating a pipeline diagram with the 5 stages(Fetch, Decode, Execute, Memory access, Write back) and this is what I've done: <br></p>
  
  <pre>
                  |  1 |  2 |  3 |  4 |  5  |  6 |  7 |  8  |  9 | 10  |
  addi $1, $4, -1 | IF | ID | EX |  M |  W  |    |    |     |    |     |
  lw $2, 0($1)    |    | IF | ID | EX |  M  |  W |    |     |    |     |
  lw $3, 0($2)    |    |    | IF | *  |  ID | EX |  M |  W  |    |     |
  sw $3, 80($1)   |    |    |    | IF |  *  | *  | ID |  EX |  M |  W  |
  
  </pre>
  
  <p>So I've answered 10 clock cycles.
  <br>
  If the first one is right(which I cannot be sure if it is) I'd really need some help in the second one regarding the content of the <strong>ID/EX</strong> register.</p>
  
  <p>Thanks in advance!</p>