title: How to interpret blocking vs non blocking assignments in Verilog?
body: <p>I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram. Do we have to infer that a non blocking assignment gives us a register? Then according to this statement <code>c &lt;= a+b </code>, c would be a register right, but not a and b? </p>
  
  <pre><code>module add (input logic clock,  
  output logic[7:0] f);   
  
  logic[7:0] a, b, c;  
  
  always_ff @(posedge clock)  
  begin   
    a = b + c;   
    b = c + a;   
    c &lt;= a + b;  
  end   
  
  assign f = c;  
  
  endmodule
  </code></pre>