title: Inferred RAM doesn't initialize in ModelSim Altera edition
body: <p>I have a memory module for an Altera FPGA target that I've written to be inferred into one of Altera's ALTSYNCRAM blocks. The memory is 1024x16 and I have a memory initialization file specified with an attribute.
  When synthesizing, the synthesis report indicates that it generated the type of RAM block that I wanted, and it notes that the initialization file is the one I specified.
  When trying to simulate with Altera's edition of ModelSim, the data signal starts out completely uninitialized, and I can't figure out why.
  I looked on forums and such and some people mentioned that ModelSim might not support the ".mif" format that I was using, but would support ".hex" so I changed my initialization file to ".hex". I also read that relative file paths can be an issue, but I checked my simulation directory and it looks like QuartusII copied the initialization file into that directory when I tried to simulate. </p>
  
  <p>Any ideas on why the memory isn't being initialized and how to make it do so?</p>
  
  <p>A heavily trimmed model that contains the inferred memory:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  library work;
  --use work.types.all;
  entity CPU is
  --...
  end entity CPU;
  architecture rtl of CPU is
  --these types are actually included in a package
  subtype reg is std_logic_vector(15 downto 0);
  type mem is array (0 to 1023) of reg;
  
  --...
      --memory read port
      signal MR : reg;
      signal MRA : std_logic_vector(9 downto 0); --flops
      --memory write port
      signal MW : reg; --flops
      signal MWA : std_logic_vector(9 downto 0); --flops
      signal MWE : std_logic; --flop
  
      signal data : mem;
      attribute ram_init_file : string;
      attribute ram_init_file of data : signal is "RAM_init.hex";
      attribute ramstyle : string;
      attribute ramstyle of data : signal is "no_rw_check";
  begin
  --...
       --memory spec
       MR &lt;= data(to_integer(unsigned(MRA(9 downto 0))));
      memory_process : process(clk)
      begin
          if (clk'event and clk = '1') then
                  if(MWE = '1') then
                      data(to_integer(unsigned(MWA(9 downto 0)))) &lt;= MW;
                  end if;
          end if;
      end process;
  end architecture rtl; --CPU
  </code></pre>
  
  <p>Modelsim does not show any warnings or errors while compiling CPU.vhd, nor does it have any indication of loading the initialization file.</p>
  
  <p>This is my first design using Altera software or memory initialization files, and it wouldn't surprise me if the problem was something really basic, or I'm approaching this from a fundamentally incorrect angle.
  I'd normally define the memory with a constant in a package, but this is for a class, and it requires that I have a memory initialization file (it requires .mif format too, but that's only a 3 character change between simulation and synthesis file).</p>