title: Bit wise 'AND' an array of registers in Verilog
body: <p>I have an array of registers/buses and a single result bus defined as follows.</p>
  
  <pre><code>wire [BW-1:0] bus_array[NUM-1:0];
  reg  [BW-1:0] and_result;
  </code></pre>
  
  <p>where </p>
  
  <pre><code>parameter BW  = 4;
  parameter NUM = 8;
  </code></pre>
  
  <p>I wish to perform a BW-bit AND operation on the elements of the array and assign the result to the register <code>and_result</code>.</p>
  
  <p>I try doing this as follows.</p>
  
  <pre><code>integer l;
  
  generate 
  genvar m;
  for (m=0; m&lt;BW; m=m+1)
  begin : BW_LOOP
  
      always @ (*)
      begin
        and_result[m] = 1'b1;
        for (l=0; l&lt;NUM; l=l+1)
          and_result[m] = and_result[m] &amp; bus_array[l][m];
      end
  
  end
  endgenerate
  </code></pre>
  
  <p>However when I simulate this in Modelsim 10.1e, I get the following error.</p>
  
  <blockquote>
    <p>Error: (vsim-3601) Iteration limit reached at time 2 ns</p>
  </blockquote>
  
  <p>If I do not use the generate loop, and instead have BW instances of the <code>always @ (*)</code> block, the simulation works okay.</p>
  
  <p>I can infer from the error message, that there is a problem with the generate for loop, but I am not able to resolve the problem.</p>