title: Makefile dependencies on multiple files
body: <p>I have created a Makefile for unit tests which uses GCC with arguments to create profiling files (gcno) during compiling. Here's a similified part of it where compiling and linking takes place:</p>
  
  <pre><code>UTEXE        = $(UTOBJSDIR)\$(UTUNIT).exe
  UTOBJS       = $(UTUUTSRC:.c=.o) $(UTUTSRC:.c=.o) $(UTCSRC:.c=.o)
  UTOBJSFULL   = $(addprefix $(UTOBJSDIR)\,$(UTOBJS))
  UTOBJSGCNO   = $(addprefix $(UTOBJSDIR)\,$(UTOBJS:.o=.gcno))
  
  $(UTOBJS): %.o: %.c $(UTMAKEDEP)
      $(call report,Compiling $(*F).c)
      $(MKDEP) $(MKDFLAGS) -o.o -f$(UTOBJSDIR)\$(*F).dep $(subst /,\,$&lt;)
      $(CC) -c $(CFLAGS) $(subst /,\,$&lt;) -o $(UTOBJSDIR)/$@
  
  $(UTOBJSGCNO): $(UTOBJS) $(UTMAKEDEP)
  
  utbuild: $(UTEXE) $(UTOBJSGCNO) $(UTOBJS) $(UTMAKEDEP)
  
  $(UTEXE): $(UTOBJSGCNO) $(UTOBJS) $(UTMAKEDEP)
      $(call report,Linking to $(UTUNIT).exe)
      $(LINK) $(UTOBJSFULL) $(LNKFLAGS) -o $(UTEXE)
  </code></pre>
  
  <p>It compiles all the object and profile files and links together a binary. However when i delete some profile file (gcno) and call "utbuild" again it won't re-compile to restore the .gcno file. It tries to do linking again because gcno is a prequisite to it, but it wont do the compiling.</p>
  
  <p>I don't know how to name this case so couldn't find solution from internet. Basically one recipe creates two files and i don't know how to write the rule that re-run's recipe even when only one file needs to re-created.</p>
  
  <p>I would appreciate some links or hints.</p>