title: I have a Verilog code and the issue is that I need to C bit to go HIGH at the same time as B_G2 and that is done at the else statement
body: <p>The issue is that I need C bit to go HIGH at the same time as B_G2 and that it is done at the else statement.</p>
  <p>Here is the code that I have so far:</p>
  <pre><code>module lightcontrol(clk, R,C, A_CAR, B_CAR, lightsA, lightsB, cnt);
       
      `define A_G2 3'b000
      `define A_Y 3'b001
      `define B_G1 3'b010
      `define B_G2 3'b110
      `define B_Y 3'b101
      `define A_G1 3'b100
       
      `define RED 3'b100
      `define YELLOW 3'b010
      `define GREEN 3'b001
       
      input clk;            
      input A_CAR;          
      input B_CAR;          
      input R ;            
       
      output [2:0] lightsA;      
      output [2:0] lightsB;      
      output [3:0] cnt;
      output C;
            
      reg [3:0] cnt = 0;
      reg [2:0] state;           
      reg C = 0;
       
      always @(posedge clk)
   
          begin   
              if (R==0 &amp;&amp; C==1)
                  begin 
                      if((state == `B_G2)&amp;&amp;(A_CAR == 1'b1)) 
                          state=`B_Y;
                          C=0; 
                  end
   
              else if ((R==1 &amp;&amp;C==0) | (R==1 &amp;&amp; C==1))
                   state = `A_G2;
              else
                  case(state)
                      `A_G2: state = B_CAR ? `A_Y : `A_G2;
                      `A_Y: state = `B_G1;
                      `B_G1: 
                          begin 
                              state = `B_G2;
                              C=1;
                          end
                      `B_G2: state = A_CAR ? `B_Y : `B_G2 ;
                      `B_Y: state = `A_G1 ;
                      `A_G1: state = `A_G2 ;
                  endcase
          end
          assign lightsA = ((state == `A_G2)|(state == `A_G1)) ? `GREEN: (state == `A_Y) ? `YELLOW : `RED;
          assign lightsB = ((state == `B_G2)|(state == `B_G1)) ? `GREEN: (state == `B_Y) ? `YELLOW : `RED;
  endmodule
  </code></pre>