title: Is it possible to have generic type in vhdl?
body: <p>Is there a way in VHDL to have generic types? So for example I want to call a procedure but I'm not sure what type the signal has I want to give as paarameter, is it possible to declare the parameter as generic?
  Like in C++ you would use a Template.</p>
  
  <pre><code>procedure eq_checker(name : string; sig : ANYTHING); should : ANYTHING; at : time) is
    if (at = now) then
      if sig = should then
        report "has same value" severity note;
      else
        report "has not same value" severity note;
      end if;
    end if;
  end checker;
  </code></pre>
  
  <p>At least it should be possible to use different signal types as "sig".</p>