title: System Verilog Clocking block
body: <p>I am trying to perform a simple test with demo code of Clocking block, but encountered the error.</p>
  
  <p>The code could be find at "EDA playground" <a href="http://www.edaplayground.com/x/3Ga" rel="nofollow">http://www.edaplayground.com/x/3Ga</a></p>
  
  <p>And the error says:
  ** Error: testbench.sv(38): A default clocking block must be specified to use the ##n timing statement.
  ** Error: testbench.sv(40): A default clocking block must be specified to use the ##n timing statement.</p>
  
  <p>I think the clocking block has already been specified in the code. </p>
  
  <p>Any Help?</p>