title: RISC-V NOP instruction
body: <p>I am working on RISC-V 32I instructions recently. I got a question about <code>NOP</code> instruction, which the specification says it is equal to <code>ADDI x0, x0, 0</code>.</p>
  
  <p>However, <code>x0</code> is not a general register which can be modified by the programmer. Thus, why <code>x0</code> serves as a destination register here for the <code>NOP</code> instruction?</p>
  
  <p>Can anyone please shed some lights on this point?</p>