title: SystemVerilog $test$plusargs matches substring
body: <p>We usually write testcases with VCS plusargs as follows</p>
  
  <pre><code>if($test$plusargs("Hello"))
      do_hello_stimulus();
  else if($test$plusargs("Hello1"))
      do_hello1_stimulus();
  </code></pre>
  
  <p>But I found out <code>$test$plusargs</code> match even the substring. Even if we pass <code>Hello1</code>, it will call <code>do_hello_stimulus()</code>. Can anyone help me out how I should use to match exact string?</p>
  
  <p>Thanks in advance</p>