title: Verilog: Setting a constant value on clock even
body: <p>I am new to Verilog, so this question might be quite dumb.</p>
  
  <p>What I am trying: I have a component that has a clk, an 8 bit input and an 8 bit output. What it should do, is:</p>
  
  <p>If the clock event is negative edge, it should set the output to 0
  If the clock event is positive edge, it should set the output to whatever input is at this moment of the edge event. During the high phase of the clock, the output should NOT change, regardless changes on the input.</p>
  
  <p>What I tried so far:</p>
  
  <pre><code>always @(negedge clk)
      _ledOut &lt;= 0;
  
  always @(posedge clk)
      _ledOut[RowSize-1:0] &lt;= ledIn[RowSize-1:0];
  </code></pre>
  
  <p>This tells my, that it can't resolve multiple constant drivers for net _ledOut.</p>
  
  <p>However, putting this together in an always @(negedge clk, posedge clk) tells me, it can't test for both conditions.</p>
  
  <p>So I tried to make just one always @(clk) block and then used an if statement:</p>
  
  <pre><code>always @(clk) begin
      if(clk == 0)
          _ledOut &lt;= 0;
      else if(clk == 1)
          _ledOut[RowSize-1:0] &lt;= ledIn[RowSize-1:0];
  end
  </code></pre>
  
  <p>But this didn't just switch on a clk event. During the high phase of the clock, it links _ledOut with ledIn, so that changes on ledIn do also have effect on _ledOut. What am I doing wrong here?</p>
  
  <p>Best regards,
  Michael</p>