title: SystemVerilog randc reinitialization
body: <p>I was wondering if there is a way to reinitialize a randc variable.  I am trying to set several registers, but need to make sure they can be set in arbitrary order.  This object may get re-randomized (there are some other random values in the class), and then the function may get called again.  My code looks something like this:</p>
  
  <pre><code>typedef enum bit[N:0] { REG1, REG2, REG3, REG4, ... } reg_order_e;
  local randc reg_order_e reg_order;
  
  function void set_regs();
      repeat( reg_order.num() ) begin
          case( reg_order )
              REG1: set_reg1();
              REG2: set_reg2();
              REG3: set_reg3();
              REG4: set_reg4();
          endcase
          assert(randomize( reg_order ));
      end
  endfunction : set_regs
  </code></pre>
  
  <p>Alternatively, is there a way of calling std::randomize() on a variable to make it a randc? 
  Thanks,
  -Tim</p>