title: How to force a single bit in an array of bits in systemverilog?
body: <p>I'm now trying to force a bit in an array of bits. The position of bit to be "forced" depends on the variable i while others bits keeps 0.
  for example, if I have the array bit <code>[2:0] A</code>
  when <code>i=0</code>, I want <code>A</code> to be <code>3'b001</code> when <code>i=1</code>, <code>A</code> should be <code>3'b010</code> when <code>i=2</code>, <code>A</code> should be <code>3'b100</code>
  but I have to use force statement since I'm writing testbench to test path of signals.
  Does anyone know how I can do that?</p>
  
  <p>update 1: @Serge I have to use the force statement it was declared like this: bit [31:0] A I tried this: force A[31:0] = 32'd0; for (int i=0;i&lt;=31;i++) begin force A[i]=1; end Obviously it doesn't work. Actually I was testing different scearios to see if the path of the signal is properly done or not</p>
  
  <p>update2: I have now generated a script to force the signal one by one
  However, I'm not sure whether I encounter a bug or not
  when this statement is executed
  a[31:0] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,`TOP_TB.clk_1T,0};
  a[1] keeps to be 0. Instead, the 1T clk appear at a[0]. Does anyone know what's happening?</p>
  
  <p>update3: Thanks for your help!!I have actually thought that the 0s are interpreted in 32 bits, but I don't really know why the 1T clk appears at bit 0 instead of bit 1 (I'm using questasim). Btw, I have solved this by generating a script and copy and paste the content inside a text file generated by the script.</p>