title: VHDL: Subtract std_logic_vector
body: <p>I am developing a code on VHDL and I need to make subtraction operation on <code>std_logic_vector</code>. I tried to define and use the following libraries:</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  </code></pre>
  <p>then I defined signals like:</p>
  <pre><code>signal r0,r1,r2,r3,r4,r5,r6,r7: STD_LOGIC_VECTOR (19 DOWNTO 0);
  </code></pre>
  <p>then I wanted to do the following subtraction:</p>
  <pre><code>        r0 &lt;= r0(16 downto 8) - r0(7 downto 0);
  </code></pre>
  <p>But it gives me error on the <code>-</code> operator. The error says:</p>
  <blockquote>
  <p>Error (10327): VHDL error at euclidian_vhd_hls.vhd(84): can't
  determine definition of operator &quot;&quot;-&quot;&quot; -- found 0 possible definitions</p>
  </blockquote>
  <p>Please help me to solve this issue.</p>
  <p>Thanks a lot.</p>