title: VHDL standard layout & syntax for "header" file
body: <p>IDE: Quartus 15</p>
  
  <p>I'm new to VHDL programming so there are some nuances I am not used to (translating from C++). Whilst I have found resources for programming the "source" files, I've struggled to find anything for the "header" files.</p>
  
  <p>In short, what is the standard layout / syntax of a VHDL "header" file?</p>
  
  <p>To keep things simple, the use cases I'm interested in are declaring <code>subtype</code> and function references for use between "source" files.</p>
  
  <p>I found the following code snippet <a href="http://www.edaboard.com/thread169224.html" rel="nofollow">here</a> which has helped a little, but I'm still not sure of what the differences between <code>package</code> and <code>package body</code> are. I'm also unsure of where "work" comes from.</p>
  
  <p>"Header":</p>
  
  <pre><code>    package DEFS is
          CONSTANT MAJOR_VERSION: INTEGER := 0;
          CONSTANT MINOR_VERSION: INTEGER := 22;
          CONSTANT MAXREG: integer := 52;
          TYPE REGS_TYPE is array (0 to MAXREG) of STD_LOGIC_VECTOR(15 downto 0);
          FUNCTION opndrn(inp: std_logic) return std_logic;
      end package DEFS;
  
      package body DEFS is
          FUNCTION opndrn(inp: std_logic) return std_logic IS
          begin
              CASE INP is
                  WHEN '0' =&gt; return '0';
                  WHEN OTHERS =&gt; return 'Z';
              END CASE;    
          end;
      end package body DEFS;
  </code></pre>
  
  <p>"Source":</p>
  
  <pre><code>    LIBRARY work;
      USE work.defs.all;
  </code></pre>
  
  <p>Any and all help is appreciated.</p>