title: Cascading BRAM in iCE40 FPGA
body: <p>I'm really new to FPGA and Verilog. I've been working on the Tri-SPI PHY controlling Noritake Itron VFD Display. One of the feature I want to implement is the framebuffer memory on the FPGA itself. I'm using the iCE40LP1K which has 64kbit BRAM (8Kbytes). But the Verilog BRAM Primitive is 4kbit and I required 3003 bytes for buffer.</p>
  <p>The question is how can I cascade the BRAM ? in the datasheet (refer to iCE40 LP/HX Family Data Sheet, page 2-6) mentioned about using multiple BRAM. Is there a way that I can use multiple instance of SB_RAM40_4K? and the later treat as a one large mem array.</p>