title: Why my 4 bit binary half adder circuit design is showing incompatible width in LOGISIM?
body: <p>I am trying to create a half adder circuit using logisim to compute two 4 bit binary numbers but somehow Logisim tells me that I have incompatible widths and I therefore have to change the bit width of every single component including the carry-out which is suppose to be a 1 bit (showing carry 1 or carry 0). Now I understand that my output has to be at least 4 bit in length and I need an extra bit as a carry out but even when I change the length the way Logisim wants then my design does not work anymore.</p>
  
  <p><a href="https://i.stack.imgur.com/LVa0T.png" rel="nofollow noreferrer">Half adder of a 2 four bit binaries</a></p>