title: generate signal assignmen in vhdl
body: <p>I have a question. I want to use generate to signal assignment. but simulator takes me an error. the error is : " Illegal target for signal assignment." and "Unknown identifier A0_i."</p>
  
  <pre><code>architecure sss of fff is
  signal A0_0 : bit ;
  signal A0_1 : bit ;
  signal A0_2 : bit ;
  signal A0_3 : bit ;
  
  begin
  
  U0 : for i in 0 to 3 generate
  U1 : A0_i &lt;= a(i) and b(i) ;
  end generate;
  
  end sss;
  </code></pre>