title: vhdl asynchronous assignment in for loop
body: <p>I am doing something like this:</p>
  
  <pre><code>x        : in  STD_LOGIC_VECTOR(15 downto 0);
  
  signal x_d: std_logic_vector(15 downto 0);
  
  type inp_concat_array is array (0 to 15) of std_logic_vector(1 downto 0); 
  signal inp_concat : inp_concat_array;
  
  process (clk, reset)
  
  begin
  
     if (rising_edge(clk)) then 
  
          if (reset = '1') then
  
              for i in 0 to 15 loop
  
                  x_d(i) &lt;= '0';  
  
              end loop;
  
          else 
  
              for i in 0 to 15 loop
  
                  x_d(i) &lt;= x(i); 
  
              end loop;
  
          end if;
  
     end if;
  
  
  end process;
  
  
  
  for j in 0 to 15 loop
  
      inp_concat(j) &lt;= x(j) &amp; x_d(j);
  
  end loop;  
  </code></pre>
  
  <p>Xilinx ISE 14.2 gives following errors</p>
  
  <p>Syntax error near "for"
  Syntax error near "loop"</p>
  
  <p>Can i use asynchronous assignments in FOR loop?</p>