title: How do I assign one multidimensional array to another in system verilog
body: <p>In System Verilog, I have:</p>
  
  <pre><code>wire [2:0][1:0] sig1;
  wire [2:0][3:0] sig2;
  </code></pre>
  
  <p>I'm attempting to do:</p>
  
  <pre><code>assign sig1[2:0][1:0] = sig2[2:0][1:0];
  </code></pre>
  
  <p>NCVerilog tells me:</p>
  
  <pre><code>assign sig1[2:0][3:0] = sig2[2:0][3:0];
                  |
  ncvlog: *E,MISEXX (acc_llcprdbctl.v,89|48): expecting an '=' or '&lt;=' sign in an assignment [9.2(IEEE)].
  </code></pre>
  
  <p>Is there a way to assign multidimensional arrays?</p>
  
  <p>Edit: Apparently, you can't assign arrays using more than one index. So the above example didn't fully represent what I wanted to do. I wanted to splice the second dimension and assign it to the first.</p>
  
  <p>This could be accomplished if I rearranged the array:</p>
  
  <pre><code>wire [1:0][2:0] sig1;
  wire [3:0][2:0] sig2;
  
  assign sig1[1:0] = sig2[1:0];
  </code></pre>
  
  <p>But for any other more precise splicing, I'd have to use a nested for loop.</p>