title: Makefile - .o: file not recognized: File truncated?
body: <p>I'm just learning GNU make, but I'm having trouble linking when using .d (dependency) files. Can anyone point me in the right direction with this <strong>error</strong>:</p>
  
  <p><code>...../part1.o: file not recognized: File truncated 
  recipe for target 'bin/target/prog' failed</code></p>
  
  <p>It's a simple program containing: <em>main.cpp, part1.cpp, part1.h, part2.cpp, part2.h</em></p>
  
  <p>Where part1 and part2 have a method to print something.</p>
  
  <p><strong>This is from terminal when running make:</strong></p>
  
  <p>I don't get why I'm getting a warning for using <em>#pragma once</em>?</p>
  
  <pre><code>stud@GoldenImageASE:~/Desktop/ISU/L1/2$ make ARCH=target -f Makefile.th
  Compiling...part2.cpp
  arm-devkit-g++ -MTbuild/target/part2.o -MM -I. part2.cpp &gt; build/target/part2.d
  Compiling...part1.cpp
  arm-devkit-g++ -MTbuild/target/part1.o -MM -I. part1.cpp &gt; build/target/part1.d
  Compiling...main.cpp
  arm-devkit-g++ -MTbuild/target/main.o -MM -I. main.cpp &gt; build/target/main.d
  object file....main.o
  arm-devkit-g++ -I. -c main.cpp part1.h part2.h &gt; build/target/main.o
  part1.h:1:9: warning: #pragma once in main file
   #pragma once
           ^
  part2.h:1:9: warning: #pragma once in main file
   #pragma once
           ^
  object file....part1.o
  arm-devkit-g++ -I. -c part1.cpp &gt; build/target/part1.o
  object file....part2.o
  arm-devkit-g++ -I. -c part2.cpp &gt; build/target/part2.o
  arm-devkit-g++ -I. -o build/target/main.o build/target/part1.o build/target/part2.o -o prog
  build/target/part1.o: file not recognized: File truncated
  collect2: error: ld returned 1 exit status
  Makefile.th:27: recipe for target 'bin/target/prog' failed
  make: *** [bin/target/prog] Error 1
  </code></pre>
  
  <p><strong>My Makefile is found below:</strong></p>
  
  <pre><code># Variables
  SOURCES=main.cpp part1.cpp part2.cpp
  OBJECTS=$(SOURCES:.cpp=.o)
  DEPS=$(SOURCES:.cpp=.d)
  EXE=prog
  CXXFLAGS =-I.
  
  
  # Making for host
  # &gt; make ARCH=host
  ifeq (${ARCH},host)
  CXX=g++
  BUILD_DIR=build/host
  EXE_DIR=bin/host
  endif
  
  # Making for target
  # &gt; make ARCH= target
  ifeq (${ARCH},target)
  CXX=arm-devkit-g++
  BUILD_DIR=build/target
  EXE_DIR=bin/target
  endif
  
  $(addprefix ${EXE_DIR}/,$(EXE)): $(addprefix ${BUILD_DIR}/,$(DEPS)) $(addprefix ${BUILD_DIR}/,$(OBJECTS))
  # &lt;&lt; Check the $(DEPS) new dependency
      @mkdir -p $(dir $@)
      $(CXX) $(CXXFLAGS) -o $(addprefix ${BUILD_DIR}/,$(OBJECTS))
  
  $(addprefix $(BUILD_DIR)/, %.o): %.cpp
      @echo "object file...."$*.o
      $(CXX) $(CXXFLAGS) -c $^ &gt; $@
  
  
  # Rule that describes how a .d ( dependency ) file is created from a .cpp
  # Similar to the assigment %. cpp -&gt; %.o
  ${BUILD_DIR}/%.d: %.cpp
      @mkdir -p $(dir $@)
      @echo "Compiling..."$&lt;
      $(CXX) -MT$(@:.d=.o) -MM $(CXXFLAGS) $^ &gt; $@
  
  debug:
      @echo "DEPS: "$(DEPS)"\n"
      @echo "OBJ: " $(addprefix ${BUILD_DIR}/,$(OBJECTS))"\n"
      @echo "EXE: " $(addprefix ${EXE_DIR}/,$(EXE))"\n"
  
  
  .PHONY:clean
  clean: 
      rm -f $(EXE) $(addprefix ${BUILD_DIR}/,$(DEPS)) $(addprefix ${BUILD_DIR}/,$(OBJECTS))
  
  ifneq ($(MAKECMDGOALS),clean)
  -include $(addprefix ${BUILD_DIR}/,$(DEPS))
  endif
  </code></pre>