title: Why is the following clock multiplication Verilog code not working for me?
body: <p>I am trying to generate a clock which is (3/16) of the system clock. So, I have decided to generate a 3x clock from the system clk and then (1/16)x clock from that.
  Right now, I am stuck at generating just the 3x clock. I am doing this by calculating the time period of the system clock and then toggling the 3x clock every 1/6th of that period. But my simulation just stalls forever with that. I have not used the <code>forever</code> block anywhere, I have checked. Hence no timing construct.
  Following is the code that I am working on.</p>
  
  <pre><code>module eec_clk_gen (
      input logic arst,
      input logic sys_clk,
      output logic eec_clk
  );
  
  real t0;
  real t1;
  real sys_clk_tp;
  
  
  logic eec_clk_x3;
  
  
  //Calculating clock period of sys_clk
  initial
  begin
      @(posedge sys_clk) t0 = $realtime;
      @(posedge sys_clk) t1 = $realtime;
      sys_clk_tp = t1 - t0;
  end
  
  
  
  //Generating clock at 3 times sys_clk freq
  
  initial
  begin
      @(posedge sys_clk) eec_clk_x3 = 1'b1;
  end
  
  always
  begin
      #(sys_clk_tp/6) eec_clk_x3 &lt;= ~eec_clk_x3;
  end
  
  endmodule: eec_clk_gen
  </code></pre>
  
  <p>I am not concerned about the <code>arst</code> signal which is missing from my code. It will be implemented once the <code>eec_clk</code> is functional.
  Some help please?</p>