title: How to set all the bits to be 0 in a two-dimensional array in Verilog?
body: <p>I've built a 8*2bits array to represent a piece of memory in Verilog</p>
  
  <pre><code>reg [1:0] m [0:7]
  </code></pre>
  
  <p>There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a concise way, because if there are hundreds thousands of bits in the memory, the following way is obviously unfeasible.</p>
  
  <pre><code>always@(posedge clk or posedge reset)
  begin
    if (reset) 
      begin
        m[0]&lt;=2'b00;
        m[1]&lt;=2'b00;
        m[2]&lt;=2'b00;
        m[3]&lt;=2'b00;        
        m[4]&lt;=2'b00;
        m[5]&lt;=2'b00;
        m[6]&lt;=2'b00;
        m[7]&lt;=2'b00;
      end
    else
      ....
  end
  </code></pre>