title: Why does this VHDL code work? 4:2 Priority encoder using Case statement
body: <p>The code is below:</p>
  
  <pre><code>entity encoder_case is
   port(
       din : in STD_LOGIC_VECTOR(3 downto 0);
       dout : out STD_LOGIC_VECTOR(1 downto 0)
       );
  end encoder_case;
  
  architecture encoder_case_arc of encoder_case is
  begin
  encoder : process (din) is
  begin
      case din is
          when "1000" =&gt; dout &lt;= "00";
          when "0100" =&gt; dout &lt;= "01";
          when "0010" =&gt; dout &lt;= "10";
          when "0001" =&gt; dout &lt;= "11";
          when others =&gt; dout &lt;= "ZZ";
      end case;
  end process encoder;
  end encoder_case_arc;
  </code></pre>
  
  <p>Now you'd expect that this code does not cover cases suh as when din is "0101", "1010" etc. But for those inputs, dout produces "10" and "11" respectively. Why does this work? Does VHDL intelligently give higher priority to the higher order bits? Does it 'know' that we're trying to accomplish a priority encoder here?</p>