title: Std logic vector in VHDL compare with zero and other vector
body: <pre><code>when S3 =&gt;
  
      NS&lt;=S5;
      Rd_ack&lt;='0';
      if (u=0) then
          send:=u;
          NS&lt;=S4;
      end if;
  
      if (v=0) then
          send:=u;
          NS&lt;=S4;
      end if;
  
  when S4 =&gt;
  </code></pre>
  
  <p>How can I compare u and v with 0 and u with v ?
  I want following statements</p>
  
  <pre><code>if( v= u) then. ....
  if( u= 0) then
  u and v are signa
  </code></pre>
  
  <p>signal u, v: std_logic_vector(0 to 31);</p>
  
  <p>In VHDL can i use send to store the value? send is a variable.
  If when we go to state s4 we want to take data in send and assign it to a signal.</p>