title: Arithmetic Shift Operation In verilog
body: <p>I have an Verilog module which has to shift one bit at a time.<br>
  Please help me completing the module.</p>
  
  <pre><code>module shift_right1 (
    output logic [15:0] shifted,
    input  wire  [15:0] unshifted,
    input  wire   [3:0] amt );
  
    localparam int width = 16;
  
    always @* begin 
      automatic int limit = width - amt;
  
      for ( int i=0; i&lt;limit; i++ ) begin
        shifted[i] = unshifted[i+amt];
      end
    end
  endmodule
  </code></pre>