title: VHDL Input & output code
body: <p>I just started with VHDL so this is hopefully a pretty basic question, My problem is that i want to code this ciruit! --> <a href="http://postimg.org/image/rrd2czsox/" rel="nofollow">http://postimg.org/image/rrd2czsox/</a> &lt;--</p>
  
  <p>In my ciruit as u can see, p and q both acts as input &amp; outputs signal.
  Here is my code for this ciruit! </p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  
  entity pracc is
  
  port(a,b,s,p,q : in std_logic;
          y,z: out std_logic);
  
  end pracc;
  
  architecture Exercise5 of pracc is
  
  begin 
  
  p &lt;= a AND b;
  q &lt;= NOT p;
  y &lt;= p;
  z &lt;= q;
  
  end architecture;
  </code></pre>
  
  <p>But i can't compile this. Even if i change p &amp; q as output signals! </p>
  
  <p>Glad for help!</p>