title: Is it possible to bind the output of a submodule to two different output ports?
body: <p>I am trying to make a circuit which computes the carries for an addition.</p>
  
  <p>In this piece of code, I would like to connect the output port <code>rOut</code> of the submodule <code>pg</code> to two output ports (<code>rOut</code> and <code>carries[0]</code>) of the parent module, so both get the same value.</p>
  
  <pre><code>template&lt;&gt;
  struct Carries&lt;1&gt; : ::sc_core::sc_module {
      sc_vector&lt;sc_in&lt;bool&gt;&gt; a, b;
      sc_in&lt;bool&gt; rIn;
      sc_out&lt;bool&gt; p, g, rOut;
      sc_vector&lt;sc_out&lt;bool&gt;&gt; carries;
  
      CarryPropGen pg {"PG"};
  
      SC_CTOR(Carries)
          :   a {"vectA", 1}, b {"vectB", 1},
              rIn {"rIn"},
              p {"p"}, g {"g"}, rOut {"rOut"},
              carries {"vectCarries", 1} {
          pg.a(a[0]);
          pg.b(b[0]);
          pg.r(rIn);
  
          pg.p(p);
          pg.g(g);
          pg.rOut(rOut);
          pg.rOut(carries[0]);
      }
  };
  </code></pre>
  
  <p>However, I get the error <code>(E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'Carries.PG.port_5' (sc_out)</code>. 
  I also tried with a signal, with and without the writer policy <code>SC_MANY_WRITER</code>, as it was suggested by someone on a forum, but it didn't work either.</p>
  
  <p>I am new to SystemC and while I understand the error, I don't really understand why this can't work and how to do it differently.
  So, is there a way to bind one submodule's output to multiple <code>sc_out</code> of the parent module, and how?</p>