title: cannot use an input for if statement in Verilog
body: <p>I am trying to pass an integer value to a module, but the <code>IF</code> statement does not work with the parameter. It throws the following error. I am new to <strong>Verilog</strong> so I have no idea how to make this work.</p>
  
  <pre><code>Error (10200): Verilog HDL Conditional Statement error at clock_divider.v(17): 
  cannot match operand(s) in the condition to the corresponding edges in the enclosing
  event control of the always construct
  </code></pre>
  
  <p><strong>clock_divider.v module</strong></p>
  
  <pre class="lang-verilog prettyprint-override"><code>module clock_divider (clockHandler, clk, rst_n, clk_o);
  
  parameter DIV_CONST = 10000000 ;  // 1 second
  parameter DIV_CONST_faster = 10000000 / 5;
  input clockHandler;
  input clk;
  input rst_n;
  
  output reg clk_o;
  
  reg [31:0] div;
  reg en;
  integer div_helper = 0;
  
  always @ (posedge clk or negedge rst_n)
  begin
      if(clockHandler == 0)
      begin div_helper = DIV_CONST;
      end
  
      else
      begin div_helper = DIV_CONST_faster;
      end
  
      if (!rst_n)
      begin div &lt;= 0;
            en &lt;= 0;
      end
  
      else
      begin
          if (div == div_helper)
          begin div &lt;= 0;
                en &lt;= 1;
          end
  
          else
          begin div &lt;= div + 1;
                en &lt;= 0;
          end
      end
  end
  
  always @ (posedge clk or negedge rst_n)
  begin
  if (!rst_n)
  begin
      clk_o &lt;= 1'b0;
  end
  else if (en)
      clk_o &lt;= ~clk_o;
  end
  
  endmodule
  </code></pre>
  
  <p><strong>main.v module</strong></p>
  
  <pre class="lang-verilog prettyprint-override"><code>reg clockHandler = 1;
  
  // 7-seg display mux
  always @ (*)
  begin
      case (SW[2:0])
          3'b000: hexdata &lt;= 16'h0188;
          3'b001: hexdata &lt;= register_A ;
          3'b010: hexdata &lt;= program_counter ;
          3'b011: hexdata &lt;= instruction_register ;
          3'b100: hexdata &lt;= memory_data_register_out ;
          3'b111: hexdata &lt;= out;   
          default: hexdata &lt;= 16'h0188;
      endcase
  
      if(SW[8] == 1)
      begin
        clockHandler = 1;
      end
      else
      begin
        clockHandler = 0;
      end
  end
  
  HexDigit d0(HEX0,hexdata[3:0]);
  HexDigit d1(HEX1,hexdata[7:4]);
  HexDigit d2(HEX2,hexdata[11:8]);
  HexDigit d3(HEX3,hexdata[15:12]);
  
  
  clock_divider clk1Hzfrom50MHz (
                  clockHandler,
                  CLOCK_50,
                  KEY[3],
                  clk_1Hz
                  );
  </code></pre>