title: VHDL map for each bit in a vector
body: <p>Whats the best way to perform a port map for each bit in a vector? Say I have a vector representing a series of buttons, and wish to debounce each one using a bebounce module, how should I go about that?</p>
  
  <p>Right now I have the following, but I believe there should be a better way</p>
  
  <pre><code>entity ButtonDebouncer is
      Port (
          clock : in std_logic;
          buttons : in std_logic_vector(0 to 5);
          --{ more stuff }
      );
  end ButtonDebouncer;
  
  architecture Behavioral of ButtonDebouncer is
      signal bufferedButtons : std_logic_vector(0 to 5) := (others =&gt; '0');
  begin
      c1: entity debounce port map (Clock, buttons(0), bufferedButtons(0));
      c2: entity debounce port map (Clock, buttons(1), bufferedButtons(1));
      c3: entity debounce port map (Clock, buttons(2), bufferedButtons(2));
      c4: entity debounce port map (Clock, buttons(3), bufferedButtons(3));
      c5: entity debounce port map (Clock, buttons(4), bufferedButtons(4));
      c6: entity debounce port map (Clock, buttons(5), bufferedButtons(5));
  
      --{ Do stuff with debounced buttons }
  end Behavioral;
  </code></pre>