title: Structuring Makefiles with multiple directories
body: <p>I am trying to compile my project which has the following structure</p>
  
  <p>Project:</p>
  
  <ul>
  <li>MakeFile</li>
  <li>Executable</li>
  <li>Source1
  <ul>
  <li><em>.cxx</li>
  <li></em>.h</li>
  </ul></li>
  <li>Source2
  <ul>
  <li><em>.cxx</li>
  <li></em>.h</li>
  </ul></li>
  <li>Build
  <ul>
  <li>*.o</li>
  </ul></li>
  </ul>
  
  <p>And I'm having difficulty writting a Makefile to compile.  I currently have commands like:</p>
  
  <pre><code>Src1 = $(wildcard $(SRCDIR1)/*.cxx)
  Obj1 = $(patsubst $(SRCDIR1)/%.cxx, $(OBJDIR)/%.o, $(Src1))
  </code></pre>
  
  <p>But then I have difficulty making the compile rules for the object files a) Because I can no longer do:</p>
  
  <pre><code>$(Obj1): %.cxx
      $(CXX) $(CFLAGS) -c $(@:.o=.cxx) -o $@
  </code></pre>
  
  <p>Because the '$@' command now includes the path of the build directory and b) because the prerequisites now include the build path and I should have a source path.  I have read large bits of the make manual to try and find a solution but no luck.
  Any help towards a solution appreciated!
  Jack</p>