title: Why Makefile include should be after all: target?
body: <p>I've been using Makefile and to keep some stuff sepparate I decided to include a new common makefile. The problem I faced is that my First makefile looks like this:</p>
  
  <p>Filename Makefile.test</p>
  
  <pre><code>include ./Makefile.a
  all: a b c
  b:
      @echo "b"
  c:
      @echo "c"
  </code></pre>
  
  <p>Filename Makefile.a</p>
  
  <pre><code>a:
      @echo "a"
  </code></pre>
  
  <p>When I execute my makefile: make -f Makefile.test I only get "a" printed out and it finishes.</p>
  
  <p>The only way to make it work is place the include bellow (anywhere) the all: target</p>
  
  <p>Is there a reason why this behaves liks this?</p>
  
  <p>Thanks!</p>