title: Parallel Crc-32 calculation Ethernet 10GE MAC
body: <p>I have generated an Ethernet 10GE MAC design in VHDL. Now I am trying to implement CRC. I have a 64-bit parallel CRC-32 generator in VHDL.</p>
  
  <p><strong>Specification:</strong><br>
  - Data bus is of 64-bits<br>
  - Control bus is of 8-bits (which validates the data bytes)  </p>
  
  <p><strong>Issue:</strong><br>
  Let's say, my incoming packet length is 14-bytes, (assuming no padding). </p>
  
  <p>The CRC is calculated for the first 8 bytes in one clock cycle, but when I try to calculate the CRC over the remaining 6 bytes the results are  wrong due to zeros being appended.</p>
  
  <p>Is there a way I can generate the CRC for any length of bytes packet length using a 64-bit parallel CRC generator?</p>
  
  <p><strong>What I've tried:</strong><br>
  I used different parallel CRC generators (8-bit parallel CRC, 16-bit parallel CRC generator and so on). But that consumes a lot of FPGA resources. I want to conserve resources using just 64-bit parallel CRC generators. </p>