title: VHDL extend string literal to std_logic_vector
body: <p>I am trying to convert a string literal like B"101" to C_NO_OF_CHANNELS bits std_logic_vector.</p>
  
  <p>Doing:</p>
  
  <pre><code>library ieee, std, switch_core;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  std_logic_vector(resize(unsigned(B"101"), C_NO_OF_CHANNELS))
  </code></pre>
  
  <p>raises:</p>
  
  <pre><code>Type conversion (to UNSIGNED) can not have string literal operand.
  </code></pre>