title: Refilling Ram vhdl
body: <p>After writing to each address of Ram and then reading every address of Ram, how would I reinitialize the Ram so that when I write to it again a second time it starts off as if it were the first time writing to it or in other words a clean slate.</p>
  
  <p>Breakdown:</p>
  
  <p>1) write to RAM</p>
  
  <p>2) read from Ram</p>
  
  <p>3) set all ram values back to 0? or can I just go ahead and provide address = 0 begin writing from 0-23 again?</p>
  
  <p>Here is my Ram:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.numeric_std.all;
  
  entity Ram is
  Port(   
      clk       : in  std_logic;                      
      address : in  std_logic_vector(4 downto 0);                         
      write_en  : in  std_logic;                      
      data_in   : in  std_logic_vector(15 downto 0);    
      data_out  : out std_logic_vector(15 downto 0)   
  );
  
  end Ram;
  
  architecture Behavioral of Ram is
  
  type ram_type is array(0 to 23) of std_logic_vector(15 downto 0);
  signal Memory : ram_type;
  
  begin
  process(clk)
  begin
       if(rising_edge(clk)) then
          if(write_en = '1') then
              Memory(to_integer(unsigned(address))) &lt;= data_in;
          end if;
          data_out &lt;= Memory(to_integer(unsigned(address)));
       end if;
    end process;
  end behavioral;
  </code></pre>