title: Verilog - difference between %0d and %d
body: <p>I don't understand why some of the code example in the internet uses <code>%0d</code> to display the value of the variables and some of the code use <code>%d</code>? what are the difference between <code>%0d</code> and <code>%d</code>?</p>
  
  <pre><code>   data_1bit   = {32{4'b1111}};
     $display("data_1bit    = %0d",data_1bit);
  
     data_1bit_unsigned   = {32{4'b1111}};
     $display("data_1bit_unsigned  = %d",data_1bit_unsigned);
  </code></pre>