title: No port 'a' on instance
body: <p>so I am working on the students labs from the xilinx website. I've been trying to look through many different examples online but I can't seem to find one to help fix my problem. I'm getting the following errors when trying to synthesize my code. I've tried mostly switching to different letters and cases. Even the sample code in the lab pdf had syntax errors for declaring components. Any help would be great thanks.</p>
  <p>Below is a list of errors i'm getting.</p>
  <blockquote>
  <p>[Synth 8-485] no port 'a' on instance [&quot;C:/Nexys 4 &gt;Projects/lab1_3_1/lab1_3_1.srcs/sources_1/new/mux_2bit_2_to_1.vhd&quot;:67]</p>
  <p>[Synth 8-485] no port 'a' on instance [&quot;C:/Nexys 4 &gt;Projects/lab1_3_1/lab1_3_1.srcs/sources_1/new/mux_2bit_2_to_1.vhd&quot;:67]</p>
  <p>[Synth 8-485] no port 'b' on instance [&quot;C:/Nexys 4 &gt;Projects/lab1_3_1/lab1_3_1.srcs/sources_1/new/mux_2bit_2_to_1.vhd&quot;:67]</p>
  <p>[Synth 8-485] no port 'b' on instance [&quot;C:/Nexys 4 &gt;Projects/lab1_3_1/lab1_3_1.srcs/sources_1/new/mux_2bit_2_to_1.vhd&quot;:67]</p>
  <p>[Synth 8-485] no port 'b' on instance [&quot;C:/Nexys 4 &gt;Projects/lab1_3_1/lab1_3_1.srcs/sources_1/new/mux_2bit_2_to_1.vhd&quot;:60]</p>
  </blockquote>
  <p>Below is my code:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity mux_2bit_2_to_1 is
      Port ( x0 : in STD_LOGIC;
             x1 : in STD_LOGIC;
             y0 : in STD_LOGIC;
             y1 : in STD_LOGIC;
             s : in STD_LOGIC;
             m0 : out STD_LOGIC;
             m1 : out STD_LOGIC);
  end mux_2bit_2_to_1;
  
  architecture Behavioral of mux_2bit_2_to_1 is
      component and2 port
      (
          i0, i1 : in STD_LOGIC;
          o : out STD_LOGIC
      ); end component;
      
      component or2 port
      (
          i0, i1 : in STD_LOGIC;
          o : out STD_LOGIC
      ); end component;
  
      component INV port
      (
          a : in STD_LOGIC;
          b : out STD_LOGIC                                         LINE 60
      ); end component;
  
      signal c, d, f, g, h : STD_LOGIC;
  
  begin
  
  inv_comp1 : INV port map (                                       LINE 67
      a=&gt;s, 
      b=&gt;c
  );
  and_comp1 : and2 port map (
      i0 =&gt; x1, 
      i1 =&gt; c,
      o =&gt; d
  );
  and_comp2 : and2 port map (
      i0 =&gt; x0, 
      i1 =&gt; c,
      o =&gt; g
  );
  and_comp3 : and2 port map (
      i0 =&gt; y1, 
      i1 =&gt; s,
      o =&gt; f
  );
  and_comp4 : and2 port map (
      i0 =&gt; y0, 
      i1 =&gt; c,
      o =&gt; h
  );
  or_comp1 : or2 port map (
      i0 =&gt; d,
      i1 =&gt; f,
      o =&gt; m1
  );
  or_comp2 : or2 port map (
      i0 =&gt; f,
      i1 =&gt; h,
      o =&gt; m0
  );
  end Behavioral;
  </code></pre>