title: Error (10170): Verilog HDL syntax error at mult.v(9) near text "="; expecting ".", or an identifier, or "["
body: <p>I am trying to implement the circuit mentioned at this question: <a href="https://stackoverflow.com/questions/41002038/how-to-perform-right-shifting-binary-multiplication/41012855#41012855">How to perform right shifting binary multiplication?</a></p>
  
  <p>I am getting the error: </p>
  
  <blockquote>
    <p>Error (10170): Verilog HDL syntax error at mult.v(9) near text "=";  expecting ".", or an identifier, or "["</p>
  </blockquote>
  
  <p>I tried to Google it, but I couldn't find anything</p>
  
  <p>Code:</p>
  
  <pre><code>module mult (multiplier, multiplicand, result, clk);
  
  input [3:0] multiplier;
  input [4:0] multiplicand;
  input clk;
  output [8:0] result;
  reg [8:0] product;
  
  initial
  begin
      product [8:4] = 4'b00000;
      product [3:0] = multiplier [3:0];
  end
  
  assign result = product;
  
  always @ (posedge clk)
  begin
      if (product[0] == 1)
      begin
          product = product &gt;&gt; 1; // shift right, and assign the most significant bit to 0
          product[8:4] = product[7:3] + multiplicand[4:0]; // add 5-bits so we can handle the carry-out
      end
      else
      begin
          product = product &gt;&gt; 1; // shift to the right
      end
  end
  
  endmodule 
  </code></pre>