title: VHDL small error when using a conditional signal assignment (when...else)
body: <p>I'm currently working on a component that will perform addition or subtraction, depending on the user input. Right now, I am working on a process that handles the assignment of values to the internal signals which will be used by the internal components I am using. One problem that comes up is in the line when I'm assigning b_in with either the input b or the 2's complement of the input b. Two errors show up: </p>
  
  <blockquote>
    <p>Error: COMP96_0015: addsub_16.vhd : (85, 17): ';' expected.<br>
    Error: COMP96_0046: addsub_16.vhd : (85, 41): Sequential statement expected.<br>
    The errors all reference to the line<br>
    b_in &lt;= (b) when add_sub = '0' else (b_2scomp);<br>
    However when I placed this outside the process, no error occurred; only when it's inside the process. Can someone please help me why this is and what I can do to solve it?</p>
  </blockquote>
  
  <p>In addition, I know that normally port mapping is done between the architecture declaration and the begin statement of the architecture. The reason I placed them after the process is because I needed to make sure that b_in has the right signal before the other components can use it. I don't know if this is the right way to do it, but I hope it is. This is just in case you guys are wondering why I'm dong it like this. Thanks</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.STD_LOGIC_UNSIGNED.all;  
  use IEEE.STD_LOGIC_ARITH.all;
  
  entity addsub_16 is
       port(
           c_in : in STD_LOGIC; 
           enable : in std_logic;
           reset : in std_logic;
           clk : in std_logic;
           add_sub : in STD_LOGIC;
           a : in STD_LOGIC_VECTOR(15 downto 0);
           b : in STD_LOGIC_VECTOR(15 downto 0);
           c_out : out STD_LOGIC;
           result : out STD_LOGIC_VECTOR(15 downto 0)
           );
  end addsub_16;
  
  architecture addsub_16 of addsub_16 is 
  
  --Signal declarations to hold internal vectors a, b g, p, and carry
  signal a_in : std_logic_vector(15 downto 0);        --Holds input a
  signal b_in : std_logic_vector(15 downto 0);        --Holds input b if add_sub = 0. Otherwise, holds b_2scomp
  signal b_2scomp : std_logic_vector(15 downto 0);    --Holds the 2s complement of b
  signal prop_in : std_logic_vector(15 downto 0);     --Holds the propagate signals from CLAs
  signal gen_in : std_logic_vector(15 downto 0);      --Holds the generate signals from CLAs
  signal carry_in : std_logic_vector(15 downto 0);    --Holds the carry signal from carry_logic 
  signal temp_result : std_logic_vector(15 downto 0); --Holds the temporary result to be driven out
  
  --Component declarations 
  component cla_4bit
      port (
          a, b : in std_logic_vector(3 downto 0);
          gen, prop : out std_logic_vector(3 downto 0)
          );
  end component;
  
  component carry_logic
      port (
          g, p : in std_logic_vector(15 downto 0);
          c_in : in std_logic;
          carry : out std_logic_vector(15 downto 0);
          c_out : out std_logic
      ); 
  end component;
  
  --Actual behavior of module
  begin   
  
  --b_in &lt;= (b) when add_sub = '0' else (b_2scomp);
  
      process (clk, reset)
      begin 
          if reset = '0' then                 --At reset, everything is 0
              a_in &lt;= (others =&gt; '0');
              b_in &lt;= (others =&gt; '0');
              b_2scomp &lt;= (others =&gt; '0');
              temp_result &lt;= (others =&gt; '0');
  
          elsif (rising_edge(clk)) then       --Read in data to components on rising edge
              if enable = '1' then            --Only if enable is on
                  a_in &lt;= a;
                  b_2scomp &lt;= ((not b) + '1');
                  b_in &lt;= (b) when add_sub = '0' else (b_2scomp);             
              end if;
          elsif (falling_edge(clk)) then      --Drive out values on falling edge
              for i in 0 to 15 loop
                  temp_result(i) &lt;= a_in(i) xor b_in(i) xor carry_in(i);
              end loop;
              result &lt;= temp_result;  
          end if;
      end process;
  
  --portmapping of the components here. I don't think it'd be necessary to include them, but let me know if they are needed.
  </code></pre>