title: concurrent and conditional signal assignment (VHDL)
body: <p>In VHDL, there are two types for signal assignment:</p>
  
  <pre><code>concurrent   ----&gt;    when...else
               ----&gt;    select...when...else
  
  sequential   ----&gt;    if...else
               ----&gt;    case...when
  </code></pre>
  
  <p>Problem is that some say that <code>when...else</code> conditions are checked line by line (king of sequential) while <code>select...when...else</code> conditionals are checked once. See this <a href="http://quartushelp.altera.com/14.1/mergedProjects/hdl/vhdl/vhdl_pro_conditional_assign.htm" rel="nofollow noreferrer">reference</a> for example.</p>
  
  <p>I say that <code>when..else</code> is also a sequential assignment because you are checking line by line. In other words, I say that there no need to say <em>if..else within a process is equivalent to when..else</em>. Why they assume <code>when..else</code> is a concurrent assignment? </p>