title: VHDL wrapper for 1-wire core for DS18B20 temperature sensor
body: <p>currently I am trying to write a VHDL wrapper for <a href="http://opencores.org/project,sockit_owm" rel="nofollow noreferrer">this</a> Opencore Verilog module (1-wire master) so that I can send/receive from <a href="http://www.sparkfun.com/products/11050" rel="nofollow noreferrer">this</a> temperature sensor (DS18B20).</p>
  
  <p>However I am struggling to understand the usage. Namely the read/write enable vs. the cyc bit in the control/status register of the 1-wire master module.</p>
  
  <p>The code I have so far sets the cyc bit to 1 and the read/write enable to one simultaneously but does not cycle them during each bit. Is this correct or am I misunderstanding it? I'm new to VHDL/ reading a datasheet so I have been struggling over this for a few days. Any help would be appreciated.</p>
  
  <p>I found <a href="https://github.com/Yesser-Morales95/DS18B20-VHDL-ONEWIRE/blob/master/DS18B20Czech/ds18b20.vhd" rel="nofollow noreferrer">this site</a> that I have been using as a reference but it does not deal with the Verilog module that I am using.</p>
  
  <p>I am also looking for tips on my code style, and VHDL tips in general.</p>
  
  <p>My current code:</p>
  
  <pre><code>LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL; --may need to remove if signed not used
  
  ENTITY one_wire_temp_probe_control IS
      GENERIC (
          one_us_divider_g : integer range 0 to 50      := 50      -- clock divider for one micro second
      );    
      PORT (
          i_clk_50mhz      : IN STD_LOGIC;
          i_read_enable    : IN std_logic;
          io_temp_probe    : INOUT STD_LOGIC; --how do i register an inout
          o_temperature    : OUT signed(6 DOWNTO 0); 
          o_temp_ready     : OUT std_logic
       );
  END one_wire_temp_probe_control;
  
  ARCHITECTURE rtl of one_wire_temp_probe_control IS
      ----temp commands----
      CONSTANT skip_rom_c          : std_logic_vector(7 DOWNTO 0) := x"CC"; --command to skip ROM identity of temperature sensor
      CONSTANT convert_temp_c      : std_logic_vector(7 DOWNTO 0) := x"44"; --command to start temperature conversion
      CONSTANT read_scratchpad_c   : std_logic_vector(7 DOWNTO 0) := x"BE"; --command to read the scratchpad i.e. get temperature data
      CONSTANT command_bits_c      : integer RANGE 0 TO 8         := 8;     --number of bits in the above commands (note: range used to limit number of bits to minimum needed)
      CONSTANT data_bits_c         : integer RANGE 0 to 12        := 12;    --number of bits in received data
      ----1-wire commands----
      CONSTANT send_reset_pulse          : std_logic_vector(7 DOWNTO 0) := "00001010"; --command to send reset pulse
      CONSTANT write_command_structure_c : std_logic_vector(6 DOWNTO 0) := "0000000";  --structure of the command that must be passed to the 1-wire controller (----EDIT----)
      ----timing constants----
      CONSTANT delay_65us_c        : integer := one_us_divider_g * 65;      --65 micro-second delay
      CONSTANT delay_960us_c       : integer := one_us_divider_g * 960;     --960 micro-second delay 
      CONSTANT delay_750ms         : integer := one_us_divider_g * 1000 * 750; --760 milli-second delay
  
      ----state machine----
      TYPE state_type              IS (idle, presence_pulse, wait_presence_pulse, skip_rom, temp_conversion, wait_for_conversion,
                                       read_scratchpad, data_read, convert_data, wait_65us);
      SIGNAL state                 : state_type := idle;
      SIGNAL previous_state        : state_type := idle;
      ----1-wire----
      SIGNAL read_enable_s, write_enable_s, reset_s, owr_e_s : std_logic := '0';
      SIGNAL write_data_s, read_data_s                       : std_logic_vector(7 DOWNTO 0):= (OTHERS =&gt; '0'); --8 bit mode chosen in sockit_owm 
      SIGNAL address_s                                       : std_logic_vector(1 DOWNTO 0) := "00"; 
      SIGNAL timer_s                                         : integer := 0;
      ----commands---
      SIGNAL bit_counter_command_s : integer RANGE 0 TO command_bits_c := 0;  --counter for bits in commands (note: not -1 due to using 9th bit as state change)
      SIGNAL bit_counter_data_s    : integer RANGE 0 TO data_bits_c    := 0;  --counter for bits in data recieved
      ----temperature----
      SIGNAL temperature_raw_data  : std_logic_vector(11 DOWNTO 0) := (OTHERS =&gt; '0');
  
      ----one wire control----
      COMPONENT sockit_owm IS
      PORT (
          ----control interface----
          clk     : IN std_logic;
          rst     : IN std_logic;
          bus_ren : IN std_logic;
          bus_wen : IN std_logic;
          bus_adr : IN std_logic_vector(7 DOWNTO 0);
          bus_wdt : IN std_logic_vector(7 DOWNTO 0);
          bus_rdt : OUT std_logic_vector(7 DOWNTO 0);
          bus_irq : OUT std_logic;
          ----1-wire interface----
          owr_p   : OUT std_logic; --verilog code is a one bit wide vector
          owr_e   : OUT std_logic;
          owr_i   : IN std_logic
      );
      END COMPONENT;
  
  BEGIN
  
      address_s &lt;= "00"; --for the temp probe control we're not interested in other address spaces
  
      PROCESS(i_clk_50mhz) BEGIN --state change
          IF rising_edge(i_clk_50mhz) THEN
              CASE state is
                  WHEN idle =&gt;
                      o_temp_ready &lt;= '0';
                      IF (i_read_enable = '1') THEN
                          state &lt;= presence_pulse;
                      ELSE
                          state &lt;= idle;
                      END IF; 
  
                  WHEN presence_pulse =&gt;
                  ----send reset/presence pulse----
                      write_enable_s  &lt;= '1';
                      write_data_s    &lt;= send_reset_pulse;
                      timer_s         &lt;= delay_960us_c;
                      state           &lt;= wait_presence_pulse;
  
                  WHEN wait_presence_pulse =&gt;
                  ----wait for 960 micro seconds----
                      read_enable_s &lt;= '1';
                      IF (timer_s = 0) THEN
                          IF (read_data_s(0) = '0') THEN
                              state &lt;= skip_rom;
                          ELSIF (read_data_s(0) = '1') THEN
                              --precence not detected
                          ELSE
                              state &lt;= wait_presence_pulse;
                          END IF;
                      ELSE
                          timer_s &lt;= timer_s - 1;
                          state   &lt;= wait_presence_pulse;
                      END IF;
  
                  WHEN skip_rom =&gt;
                  ----send skip rom command----
                      previous_state &lt;= skip_rom;
                      write_enable_s &lt;= '1';
                          IF (bit_counter_command_s = command_bits_c) THEN
                              bit_counter_command_s &lt;= 0;
                              state                 &lt;= temp_conversion;
                          ELSE
                              write_data_s &lt;= write_command_structure_c &amp; skip_rom_c(bit_counter_command_s); ---command structure concatonated with 1 bit from command
                              bit_counter_command_s &lt;= bit_counter_command_s + 1;
                              timer_s               &lt;= delay_65us_c;
                              state                 &lt;= wait_65us;
                          END IF;   
  
                  WHEN temp_conversion =&gt;
                  ----send temp conversion command to probe----
                      previous_state &lt;= temp_conversion;
                      IF (bit_counter_command_s = bit_counter_command_s) THEN
                          bit_counter_command_s   &lt;= 0;
                          timer_s                 &lt;= delay_750ms;
                          state                   &lt;= wait_for_conversion;
                      ELSE
                          write_data_s &lt;= write_command_structure_c &amp; convert_temp_c(bit_counter_command_s); ---command structure concatonated with 1 bit from command
                          bit_counter_command_s   &lt;= bit_counter_command_s + 1;
                          timer_s                 &lt;= delay_65us_c;
                          state                   &lt;= wait_65us;
                      END IF;
  
                  WHEN wait_for_conversion =&gt;
                  ----wait for temperature conversion to finish----
                      IF (timer_s = 0) then
                          state &lt;= read_scratchpad;
                      ELSE
                          timer_s &lt;= timer_s - 1;
                      END IF;
  
                  WHEN read_scratchpad =&gt;
                  ----send read scratchpad command----
                      previous_state &lt;= read_scratchpad;
                      IF (bit_counter_command_s = command_bits_c) THEN
                          state                 &lt;= data_read;
                          bit_counter_command_s &lt;= 0;
                      ELSE
                          write_data_s &lt;= write_command_structure_c &amp; read_scratchpad_c(bit_counter_command_s); ---command structure concatonated with 1 bit from command
                          bit_counter_command_s &lt;= bit_counter_command_s + 1;
                          timer_s               &lt;= delay_65us_c;
                          state                 &lt;= wait_65us;
                      END IF;
  
                  WHEN data_read =&gt;
                  ----read incoming data----
                      previous_state &lt;= data_read;
                      read_enable_s &lt;= '1';
                      IF (bit_counter_data_s = data_bits_c) THEN
                          bit_counter_data_s &lt;= 0; --may need to invert this
                          state              &lt;= convert_data;
                      ELSE
                          temperature_raw_data(bit_counter_data_s) &lt;= read_data_s(0);
                          bit_counter_data_s                       &lt;= bit_counter_data_s + 1;
                          timer_s                                  &lt;= delay_65us_c;
                          state                                    &lt;= wait_65us;
                      END IF;
  
                  WHEN convert_data =&gt;
                  ----convert raw data into temperature----
                      o_temp_ready &lt;= '1';
  
                  WHEN wait_65us =&gt;
                  ----wait for read/write cycle to finish----
                      IF (timer_s = 0) THEN
                          state &lt;= previous_state;
                      ELSE 
                          timer_s &lt;= timer_s - 1;   
                          state   &lt;= wait_65us;
                      END IF;
              END CASE;
          END IF;
      END PROCESS;
  
      ----one wire component instantiation----
      one_wire_control : sockit_owm
      PORT MAP(
          ----control interface----
          clk     =&gt; i_clk_50mhz,
          rst     =&gt; reset_s,
          bus_ren =&gt; read_enable_s,
          bus_wen =&gt; write_enable_s,
          bus_adr =&gt; address_s,
          bus_wdt =&gt; write_data_s,
          bus_rdt =&gt; read_data_s,
          bus_irq =&gt; OPEN,
          ----1-wire interface----
          owr_p   =&gt; OPEN,
          owr_e   =&gt; owr_e_s,
          owr_i   =&gt; io_temp_probe
      );
      io_temp_probe &lt;= owr_e_s ? '0' : 'Z'; --I also need help converting this line to VHDL
  
  END rtl;
  </code></pre>
  
  <p>Thank you in advance.
  Best
  Tom</p>