title: How can AXI4 support PCIE Producer/Consumer ordering model?
body: <p>PCIE uses <strong>Producer/Consumer ordering model</strong>, but AXI4 uses a different ordering model. AXI4's read and write channels are independent.</p>
  
  <p>For instance, a system like this,</p>
  
  <p><strong><em>CPU &lt;-> PCIE Controller &lt;-> PCIE AXI Bridge &lt;-> AXI4 with DEC and DDR slaves (DEC module is connected to AXI4 slave data port0 and APB register port, DDR memory module is connected to AXI4 slave data port1)</em></strong></p>
  
  <p>CPU performs the follwing two operations,</p>
  
  <pre><code>1.CPU writes data to DDR
  2.CPU writes DEC APB register to start DEC
  </code></pre>
  
  <p>Because PCIE memory writes (both <strong>prefetchable and non-prefetchable</strong>) are <strong>posted</strong>, i.e. <strong>without responses</strong>, PCIE AXI Bridge will perform the above two operations successively with the same ID but without waiting for <strong>BRESP</strong>. Before data reaches DDR, DEC may have seen the APB register write and start read the data, so the data may be old and invalid.</p>
  
  <p>This ordering issue can be solved by writing a data then reading it back as follows,</p>
  
  <pre><code>1.CPU writes data to DDR
  2.CPU read the same data back
  3.CPU writes DEC APB register to start DEC
  </code></pre>
  
  <p>But it's inefficient.</p>
  
  <p>So how can we solve this ordering issue when PCIE and AXI4 are connected? Is it better to solve this ordering issue in the PCIE side or AXI interconnect side?</p>