title: I get this error vlog-13069
body: <p>First of all, sorry for my English skills.</p>
  
  <p>I am studying Verilog and I have this code</p>
  
  <pre><code>module paralelo_serie ( data_in,clk,  D_serie, nSyn, Done );
  input wire [12:0] data_in;
  input clk;
  output reg D_serie, nSyn, Done;
  genvar i;
  
  84 if (data_in == 0) Done= 1;
  else....
  </code></pre>
  
  <p>When I try to compile this code, I get this error message:</p>
  
  <blockquote>
    <p>Error: (vlog-13069) C:/Users/Pedro/Documents/master/asignaturas/primer cuatrimestre/Metodologia de diseño y herramientas cad/proyecto digital/proyecto digital.v(84): near "=": syntax error, unexpected '='.</p>
    
    <p>Error: C:/Users/Pedro/Documents/master/asignaturas/primer cuatrimestre/Metodologia de diseño y herramientas cad/proyecto digital/proyecto digital.v(84): (vlog-13205) Syntax error found in the scope following 'Done'. Is there a missing '::'?</p>
  </blockquote>
  
  <p>I am a beginner at this language and I don't know what happened. I get this error a few times in the code, but I can solve it sometimes by changing the reg to wire and other time change blocking assignment to no blocking... I don't really know how I can fix and really I am getting frustrated... please help, you are my last hope...</p>
  
  <p>Sorry I forgotten, I use modelsim 10.4 student version</p>