title: VHDL Initialize std_logic
body: <p>I'm writing a sequential counter which is comprised of a series of single-counter components which use D-flip-flop components.  Within the single-counter, I need to start with an initial value of <code>'0'</code> for <code>q</code>, but I am having problems initializing this.</p>
  
  <p><code>q</code> is a <code>STD_LOGIC</code> signal, and I have attempted to initialize it as follows:</p>
  
  <pre><code>signal q : STD_LOGIC := '0';
  </code></pre>
  
  <p>However, when I run the program using ModelSim it shows a value of <code>U</code> as though it is unassigned.  If I force freeze a signal of <code>'0'</code> to <code>q</code> when I run it in ModelSim, then it works.</p>
  
  <p>Is the only way to accomplish this to check the value at the beginning of the behavioral description and set it to <code>'0'</code> if it is unassigned?</p>
  
  <p>If I use <code>BIT</code> instead of <code>STD_LOGIC</code>, everything works perfectly.</p>
  
  <p>I would post my code, but I don't want to risk academic integrity violations as this is for a school project.</p>