title: 8-bit Adder Error: The logic does not match a known FF or Latch template
body: <p>As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:</p>
  
  <pre><code>module Addr_8bit(Clk, Rst, En, LEDOut  
      );
  
       input Clk;
       input Rst;
       input En;
       output reg [7:0] LEDOut;
  
      always @(posedge Clk or posedge Rst) begin
              if(Rst)
                  LEDOut &lt;= 8'b00000000;
              if(En)
                  LEDOut &lt;= LEDOut + 8'b00000001;
      end
  endmodule
  </code></pre>
  
  <p>The error is on the line where the non-blocking assignment: <code>LEDOut &lt;= LEDOut + 8'b00000001;</code> is located.</p>
  
  <p>Particularly it says that:</p>
  
  <pre><code>ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for &lt;LEDOut&gt; does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
  </code></pre>
  
  <p>I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).</p>
  
  <p>Thank You.</p>