title: MPU settings for ARM Cortex M7
body: <p>I am working on a SoC with several Cortex M7 cores. It has SRAM mapped to region <code>0x2000 0000</code>  -&gt; <code>0x3FFF FFFF</code> and DDR mapped to <code>0x6000 0000</code> -&gt; <code>0xDFFF FFFF</code>.</p>
  <p>It seems that configuring the 4 partitions of DDR to <em>cached normal memory</em> (WT, WB or WBA) is triggering an HW bug which freezes the whole chip after a few seconds. <strong>Even the debugger get disconnected</strong>. Note that I do <strong>not</strong> need to access the DDR to raise the problem. Just running code in SRAM to configure the MPU and do various stuff will, after a random delay, trigger the bug.</p>
  <p><strong>Is there any limitation to the attributes I set when configuring the MPU?</strong></p>
  <p>I would say only the system space in <code>0xE000 0000</code> has fixed attributes and others are freely configurable depending on the HW implementation, but I have a doubt because if I refer to ARMv7-M arch ref manual, I can for instance find this:</p>
  <blockquote>
  <p><strong>B3.1 The system address map</strong> (p. 588)</p>
  <p>[...] A declared cache type can be demoted but not promoted [...]</p>
  </blockquote>
  <p>I am not sure here if this is just a limitation during runtime for two sequential configurations or an absolute limitation that forbids enabling the cache for partitions at 0xA... and 0xC... even once during init as they are not enabled in the default address map.</p>
  <p>Also, the documentation indicates that the DDR is <em>normal memory</em>, but is there any problem if I keep it configured by default as <em>device space</em> (without taking into account slower non re-ordered accesses inherent to this configuration)?</p>
  <hr />
  <p>Here is the exact configuration for the 4 DDR partitions:</p>
  <pre><code>RBAR -&gt; 60000000 80000000 A0000000 C0000000 (start addresses)
  RASR =&gt; 03080039 03080039 13010039 13100039 (default settings)
  RASR =&gt; 03020039 03020039 03020039 03020039 (new settings triggering the bug)
  </code></pre>
  <p>Note that for the SRAM I keep the same setting:</p>
  <pre><code>RBAR -&gt; 20000000 
  RASR =&gt; 030B0039 
  </code></pre>