title: Syntax errors in VHDL code
body: <p>Hey guys I was working with VHDL and my problem statement is as below:</p>
  
  <p><strong>Write a VHDL code for XOR and XNOR functions, same as previous lab session,  and define another input “x” in your code such that if input x=1 then  F = X1 XOR X2, 
  else F = X1 XNOR X2.</strong></p>
  
  <p>So I started writing this code:</p>
  
  <pre><code>LIBRARY ieee ;
  
  USE ieee.std_logic_1164.all ;
  
  ENTITY prework IS
  
  PORT ( x1, x2, x : IN STD_LOGIC ;
  
  f: OUT STD_LOGIC ) ;
  
  END prework ;
  
  ARCHITECTURE LogicFunction OF prework IS
  
  
  PROCESS (x,x1,x2)
  BEGIN
  if x = '1' then
      f &lt;= (x1 AND NOT x2) OR (NOT x1 AND x2);
  else
      f &lt;= NOT((x1 AND NOT x2) OR (NOT x1 AND x2));
  end if;
  end PROCESS;
  
  END LogicFunction ;
  </code></pre>
  
  <p>But I keep getting these errors: </p>
  
  <p>Error (10500): VHDL syntax error at prework.vhd(16) near text "PROCESS";  expecting "begin", or a declaration statement</p>
  
  <p>Error (10500): VHDL syntax error at prework.vhd(20) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement</p>
  
  <p>Error (10500): VHDL syntax error at prework.vhd(22) near text "if";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"</p>
  
  <p>So can you please help me solve these errors,
  Thank you</p>