title: Why do I get Syntax error near always in Verilog code?
body: <p>I am trying to run this code, and it is giving these errors:</p>
  
  <pre><code>Syntax error near "always"
  Syntax error near "endmodule"
  </code></pre>
  
  <p>I don't understand what is wrong in this code:</p>
  
  <pre><code>module fortran_v2(
      input clk
      );
  parameter N=8;
  parameter M=6;
  parameter size=1000;     
  reg [N-1:0] A [0:size-1];
  reg [N-1:0] B [0:size-1];
  reg [M-1:0] C [0:size-1];
  reg [M-1:0] D [0:size-1];
  reg [15:0] k=0;
  integer open_file;
  initial begin
  open_file= $fopen("output.txt","w");
  end
  
  always @ (posedge clk) begin
  if(k&lt;1000)
  k&lt;=k+1;
  else
  k&lt;=1000;
  end
  
  always @ (posedge clk) begin
  if(k&lt;1000) begin
    A[k]&lt;=$random;
    B[k]&lt;=$random;
    end
  
  always @ (posedge clk) begin
  if (k&lt;1000) begin
    C[k]&lt;=A[k]*B[k] +5;
    D[k]&lt;=A[k]+B[k] -5;
    $fwrite(open_file,"A[%d",k,"]",A[k],"B[%d",k,"]",B[k],"C[%d",k,"]",C[k],"D[%d",k,"]",D[k]);
  end
  else
    A[k]=0;
  end  
  endmodule
  </code></pre>