title: PCIe TLP write packet address only 31:2 bits
body: <blockquote>
    <p>Let's take a sample write packet :  Suppose that the CPU wrote the
    value <code>0x12345678</code> to the physical address <code>0xfdaff040</code> using 32-bit
    addressing</p>
    
    <p><a href="https://i.stack.imgur.com/0OlFU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0OlFU.png" alt="sample write packet"></a></p>
    
    <p>This example is from this <a href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1" rel="nofollow noreferrer">site</a> (<em>I didn't understand the explanations in the original post</em>)</p>
  </blockquote>
  
  <ol>
  <li>Why does the address start at the second bit <code>[31 : 2]</code></li>
  <li>Why isn't the address the same</li>
  </ol>