title: FPGA efficient (a)synchronous resets
body: <p>I remember reading a while ago that either asynchronous or synchronous resets are more efficiently implemented in FPGAs since the flip flops already have one, but the other would require additional logic.</p>
  
  <p>Does anyone know which way round this is? Is this the same for Xilinx, Altera, Other..</p>
  
  <p>When learning, I used to add an asynchronous clear and a synchronous reset to every FSM, just in case. Is there any benefit at all to this?</p>
  
  <p>Thanks for any feedback!</p>