title: System Verilog Illegal assignment: Cannot assign an unpacked type to a packed type
body: <p>In System Verilog I wrote:</p>
  <pre><code>module mult32x32_arith (
      input logic clk,             // Clock
      input logic reset,           // Reset
      output logic [63:0] product  // Miltiplication product
  );
  
  logic left_decoder, right_decoder, product_FF[63:0]={64{1'b0}};
  
      always_ff @(posedge clk, posedge reset) begin
          if (reset==1'b1)begin
              product &lt;= product_FF;
          end
          else begin
              
          end
      end
  </code></pre>
  <p>But, I'm getting errors on this line:</p>
  <pre><code>product &lt;= product_FF;
  </code></pre>
  <p>It says:</p>
  <blockquote>
  <p>Error: mult32x32_arith.sv(19): Illegal assignment to type 'reg[63:0]' from type 'reg $[63:0]': Cannot assign an unpacked type to
  a packed type.</p>
  </blockquote>
  <p>But, I don't understand what the problem is.</p>