title: How does Verilog decide when events happen "simultaneously"?
body: <p>I know Verilog for only like 2 months, 3 months tops. I am absolutely frustrated about this one thing, which I would refer to as <em>race condition</em> if it was happening in some other, non-HDLanguage I know. Here are the files in their most simplified form, describing the case:</p>
  
  <p>The <code>circuit.v</code></p>
  
  <pre><code>module circuit(f, x, clk, rst);
  
      output f;
      input x, clk, rst;
  
      wire d, q;
  
      d_flip_flop flipper (q, d, clk, rst);
  
      assign f = q;
      assign d = x;
  
  endmodule
  </code></pre>
  
  <p>The <code>d_flip_flop.v</code></p>
  
  <pre><code>module d_flip_flop(q, d, clk, rst);
  
      output reg q;
      input d, clk, rst;
  
      always @(posedge clk, posedge rst)
      begin
          if (rst)
              q &lt;= 1'b0;
          else
              q &lt;= d;
      end
  
  endmodule
  </code></pre>
  
  <p>And I test these with this <code>tester.v</code></p>
  
  <pre><code>module tester;
  
      reg x, clk, rst;
      wire f;
  
      circuit uut (f, x, clk, rst);
  
      initial clk &lt;= 0;
      always #10 clk &lt;= ~clk;
  
      initial
      begin
          x &lt;= 0;
          rst &lt;= 0;
  
          rst &lt;= #2 1;
          rst &lt;= #4 0;
  
          #10 x &lt;= 1;
      end
  
  endmodule
  </code></pre>
  
  <p>And here's the waveform I get:</p>
  
  <p><img src="https://i.stack.imgur.com/mTYuZ.png" alt="waveform"></p>
  
  <p>What I see from that waveform is that Verilog has decided that it should first process the change in <code>clk</code>, hence perform the <code>q &lt;= d;</code>; and only then process the change in <code>x</code>, hence perform <code>assign d = x;</code>.</p>
  
  <p>What I said there probably doesn't even make sense in the hardware, but whatever.</p>
  
  <p>Now: I have people around me, so called the assistants of the lecture, more experienced and presumably more knowledgeable, claiming that a <em>properly written</em> Verilog sequential module always considers the changes as happened, as the clock hits posedge. Even in this extremely simple example, however, I see it to be otherwise (and probably not necessarily, either).</p>
  
  <p>So, the question is, what should I be doing to turn this into a <em>properly written</em> Verilog sequential module? How could I make my bad code to be a good one like the others? Or is there just no such thing, and Verilog is just proudly non-deterministic in such cases?</p>