title: Makefile builds everything each time
body: <p>I have the following Makefile (reduced to ignore irrelevant stuff):</p>
  
  <pre><code>BUILD_DIR=./build
  OBJS = \
    $(BUILD_DIR)/main.o \
    $(BUILD_DIR)/common.o \
    ...
  
  roo: $(OBJS)
      $(CXX) -o $@ $(OBJS) $(LFLAGS)
  
  .PHONY: $(BUILD_DIR)
  $(BUILD_DIR):
      mkdir -p $(BUILD_DIR)/passes
  
  $(BUILD_DIR)/%.o: src/%.cpp $(BUILD_DIR)
      $(CXX) -o $@ -c $&lt; $(CFLAGS)
  </code></pre>
  
  <p>However, every object file is recompiled every time, even thought I'm following the rule to directly use <code>$@</code> in each non-phony target.</p>
  
  <p>I don't think this is a duplicate of <a href="https://stackoverflow.com/questions/15598747/makefile-rebuilds-everything-every-time-why">this</a> because I'm applying the subdirectory in the rule rather than in the recipe, but I may be wrong? How do I get Make to correctly track the dependencies in the build directory?</p>