title: Has Vivado unlearned to do type inference?
body: <p>I have masses of entity instances like that:</p>
  
  <pre><code>GPIO : entity L_PicoBlaze.pb_GPIO_Adapter
    generic map (
      [...]
    )
    port map (
      Clock    =&gt; CPU_Clock,   -- Clock : in STD_LOGIC;
      Reset    =&gt; '0',         -- Reset : in STD_LOGIC;  -- line 645
      [...]
    );
  </code></pre>
  
  <p>The code from above is working with:<br>
  - ISE XST 14.7<br>
  - Quartus II 13.x<br>
  - ISE iSim 14.7<br>
  I'm also sure, I successfully compiled my design with Vivado 2013.x !!!</p>
  
  <p>Vivado (2014.4) Synth complains, that there are 3 possible type resolutions for <code>'0'</code>:<br>
  [Synth 8-2396] near character '0' ; 3 visible types match here ["D:/git/.../PicoBlaze/System.vhdl":645]</p>
  
  <p>Reset is declared as following:<br>
  <code>Reset : in STD_LOGIC</code></p>
  
  <p>I can solve this problem by using a qualified expression:</p>
  
  <pre><code>GPIO : entity L_PicoBlaze.pb_GPIO_Adapter
    generic map (
      [...]
    )
    port map (
      Clock    =&gt; CPU_Clock,
      Reset    =&gt; STD_LOGIC'('0'),  -- line 645
      [...]
    );
  </code></pre>
  
  <p><strong>I think this (a) looks bad and (b) is a bug in Synth.</strong></p>
  
  <p>I think ISE XST and other tools are doing reverse/backward type inference to determine the correct literal type.</p>
  
  <p>Has anyone encountered this problem, too?<br>
  Is my coding style so bad, if I write '0', x"00..00" or "00..00" in port maps?</p>
  
  <h2>Edit 1 - Minimal and Complete Example:</h2>
  
  <pre><code>library IEEE;
  use     IEEE.std_logic_1164.all;
  
  entity top is
    port (
      Clock   : in  STD_LOGIC;
      Reset   : in  STD_LOGIC;
      OUTPUT  : out  STD_LOGIC
    );
  end entity;
  
  architecture rtl of top is
  begin
    toggle : entity work.TFF
      port map (
        Clock    =&gt; Clock,
        Reset    =&gt; '0',            -- line 17
        Q        =&gt; Output
      );
  end;
  
  -- a simple toggle flip flop
  library IEEE;
  use     IEEE.std_logic_1164.all;
  
  entity TFF is
    port (
      Clock   : in  STD_LOGIC;
      Reset   : in  STD_LOGIC;
      Q       : out  STD_LOGIC
    );
  end entity;
  
  architecture rtl of TFF is
    signal Q_r    : STD_LOGIC    := '0';
  begin
    process(Clock)
    begin
      if rising_edge(Clock) then
        if (Reset = '1') then
          Q_r    &lt;= '0';
        else
          Q_r    &lt;= not Q_r;
        end if;
      end if;
    end process;
    Q    &lt;= Q_r;
  end;
  </code></pre>
  
  <p>Vivado 2014.4 Error message:<br>
  [Synth 8-2396] near character '0' ; 3 visible types match here ["D:/Temp/OverloadTest/overload.vhdl":17]</p>
  
  <h2>Edit 2:</h2>
  
  <p>I found a working example: I just put the declaration of entity tff in front the top-level declaration. It seams that a <strong>[Synth 8-2396] near ..... visible types match here</strong> error message from Vivado just a clumsy way to tell us, it can't find a reference to an entire component / file?</p>
  
  <p>I'll need some time to recheck my file list (>300) for missing files/components.</p>