title: Splitting a bit array in Verilog
body: <p>I am designing a basic AES algorithm on verilog, and I need to split a 128 bits array into 16 parts each one of 8 bits.</p>
  
  <p>For example (basic 8 bit example), if I receive 10111011 I need to generate 4 outputs 10 11 10 11</p>