title: Always block with posedge triggering somehow works at time 0
body: <p>I wrote a basic piece of Verilog code. </p>
  
  <pre><code>    `timescale 1ns / 1ps
  module lab3_2(
              input[3:0] command,
              input CLK,
              input mode,
              output reg [7:0] total_time1,
              output reg [7:0] total_time0
       );
       initial begin
       total_time1 = 8'b00000000;
       total_time0 = 8'b00000000;
  
       end
  
       always @(posedge CLK) begin
  
              if(total_time1 == 8'b00000001 &amp;&amp; total_time0 == 8'b00001001)
                  begin
                  total_time0 &lt;= 8'b00000000;
                  total_time1 &lt;= 8'b00000000;
                  end
              else if(total_time0 == 8'b00001001)
                  begin
                  total_time1 &lt;= 8'b00000001;
                  total_time0 &lt;= 8'b00000000;
                  end
              else
                  begin
                  total_time0 &lt;= total_time0 + 8'b00000001;
                  end
          end
  
  endmodule
  </code></pre>
  
  <p>It counts time up to 20, <code>total_time1</code> showing the leftmost digit  and <code>total_time0</code> showing the rightmost digit.<br>
  If <code>total_time1</code> = 1 and <code>total_time0</code> = 5, then it is the 15th time that the <code>always</code> block worked. </p>
  
  <p>My problem is that when I try  this testbench: </p>
  
  <pre><code>`timescale 1ns /1ps
  
  module lab3_2_testbench;
  
  reg[3:0] command;
  reg CLK;
  reg mode ;
  wire[7:0] total_time1;
  wire[7:0] total_time0;
  
  
  lab3_2 uut(
  .command(command),
  .CLK(CLK),
  .mode(mode),
  .total_time1(total_time1),
  .total_time0(total_time0)
  );
  
  
  initial CLK = 1;
      always #5 CLK = ~CLK;
  
  initial begin
  $monitor("Time=%t | command=%b mode=%b| total_time1=%b total_time0=%b   CLK=%b      ", $time, command, mode,total_time1,total_time0,CLK);
  mode = 0 ;
  
  
  command = 4'b0000;
  
  $display("Current simulation time = %t",$time);
      #10;
      $display("Current simulation time = %t",$time);
  
      $finish;
  
  
  
  
  
  end
  
  endmodule
  </code></pre>
  
  <p>What I get as output is:  </p>
  
  <pre><code>Time=                   0 | command=0000 mode=0| total_time1=00000000 total_time0=00000001   CLK=1      
  Time=                5000 | command=0000 mode=0| total_time1=00000000 total_time0=00000001   CLK=0      
  Current simulation time =                10000
  Stopped at time : 10 ns : File "/home/bs04/e2237006/Desktop/liy/testbench_part2.v" Line 35 ** 
  </code></pre>
  
  <p>How come <code>total_time0</code> is equal to 1 at time time 0?  Should it be not 0? I thought that the only way to increase <code>total_time0</code> is via triggering the <code>always</code> block, but how did I manage to trigger the <code>always</code> block at time 0?  </p>
  
  <p>According to my code, <code>CLK</code> starts as 1.</p>