title: ARM Cortex M3 GPIO Interrupts - One ISR per port with 8 pins - How to handle all pins?
body: <p>I'm using the Luminary LM3S8962 micro-controller and its included Library Guide, but this should be relevant to any ARM Cortex-M3s that have Nested Vector Interrupts.</p>
  
  <p>You can only register one interrupt service routine function with an entire GPIO Port. A GPIO port typically has 8 pins on it, each of which can be configured with an interrupt. For each pin, you can test whether or not an interrupt "happened" on it (is pending), right? and for each pin you can clear a pending interrupt, right?</p>
  
  <p>If a pin on the GPIO port triggers the ISR then the processor is in the ISR. Then what happens if another pin on the same port triggers an interrupt while we're in the ISR? We assume the code detects what pins have pending interrupts.
  - Is this ISR interrupted and a new one begins, with the same code, but an updated PinInterruptStatus register ? (I hope not)
  - Is this ISR executed until completion, immediately executing the interrupt for the other pin right afterward? (I know ARM Cortex M3 implements tail-chaining of interrupts)
  - Or must there be a while loop that loops until all the pins have been cleared, clearing a pin after it has been processed?</p>
  
  <p>maybe this will help:</p>
  
  <p><a href="http://www.ti.com/lit/gpn/lm3s8962" rel="nofollow">http://www.ti.com/lit/gpn/lm3s8962</a></p>