title: Difference between "," and "or" in always@ (Verilog)
body: <p>I have just embarked on Verilog system to design hardware.</p>
  
  <p>I don't know if there is a difference between using <code>,</code> and <code>or</code> in <code>always@</code>.</p>
  
  <p>For example: </p>
  
  <pre><code>always @(S or C)
  </code></pre>
  
  <p>and</p>
  
  <pre><code>always @(S,C)
  </code></pre>
  
  <p>Is there a difference, and if so, what is it?</p>