title: Verilog- in memory address width and data width
body: <p>I am a beginner of Verilog code. So I have a doubt in address width and data width. By Google, I got address width is a log base 2 of RAM depth and there is no relation between address width and data width. But in a memory, address width is a number of columns. So my doubt is if the data width is larger than the address width means there is any problem occurred? Whether the data can be stored in it. </p>
  
  <p>EX: If I have 16-bit address width and 32-bit data width means what will happen?</p>