title: Need help handling multiple shared I2C MAX3107 chips on shared ARM9 GPIO interrupt (linux)
body: <p>Our group is working with an embedded processor (Phytec LPC3180, ARM9).  We have designed a board that includes four MAX3107 uart chips on one of the LPC3180's I2C busses.  In case it matters, we are running kernel 2.6.10, the latest version available for this processor (support of this product has not been very good; we've had to develop or fix a number of the drivers provided by Phytec, and Phytec seems to have no interest in upgrading the linux code (especially kernel version) for this product.  This is too bad in that the LPC3180 is a nice device, especially in the context of low power embedded products that DO NOT require ethernet and in fact don't want ethernet (owing to the associated power consumption of ethernet controller chips). The handler that is installed now (developed by someone else) is based on a top-half handler and bottom-half work queue approach.</p>
  
  <p>When one of four devices (MAX3107 UART chips) on the I2C bus receives a character it generates an interrupt. The interrupt lines of all four MAX3107 chips are shared (open drain pull-down) and the line is connected to a GPIO pin of the 3180 which is configured for level interrupt. When one of the 3017's generates an interrupt a handler is run which does the following processing (roughly):</p>
  
  <pre><code>spin_lock_irqsave();
  disable_irq_nosync(irqno);
  irq_enabled = 0;
  irq_received = 1;
  spin_unlock_irqrestore()
  set_queued_work();  // Queue up work for all four devices for every interrupt
                      // because at this point we don't know which of the four
                      // 3107's generated the interrupt
  return IRQ_HANDLED;
  </code></pre>
  
  <p>Note, and this is what I find somewhat troubling, that the interrupt is not re-enabled before leaving the above code. Rather, the driver is written such that the interrupt is re-enabled by a bottom half work queue task (using the "enable_irq(LPC_IRQ_LINE) function call".  Since the work queue tasks do not run in interrupt context I believe they may sleep, something that I believe to be a bad idea for an interrupt handler.</p>
  
  <p>The rationale for the above approach follows:
  1. If one of the four MAX3107 uart chips receives a character and generates an interrupt (for example), the interrupt handler needs to figure out which of the four I2C devices actually caused the interrupt. However, and apparently, one cannot read the I2C devices from within the context of the upper half interrupt handler since the I2C reads can sleep, something considered inappropriate for an interrupt handler upper-half.
  2. The approach taken to address the above problem (i.e. which device caused the interrupt) is to leave the interrupt disabled and exit the top-half handler after which non-interrupt context code can query each of the four devices on the I2C bus to figure out which received the character (and hence generated the interrupt).
  3. Once the bottom-half handler figures out which device generated the interrupt, the bottom-half code disables the interrupt on that chip so that it doesn't re-trigger the interrupt line to the LPC3180. After doing so it reads the serial data and exits.</p>
  
  <p>The primary problem here seems to be that there is not a way to query the four MAX3107 uart chips from within the interrupt handler top-half. If the top-half simply re-enabled interrupts before returning, this would cause the same chip to generate the interrupt again, leading, I think, to the situation where the top-half disables the interrupt, schedules bottom-half work queues and disables the interrupt only to find itself back in the same place because before the lower-half code would get to the chip causing the interrupt, another interrupt has occurred, and so forth, ....</p>
  
  <p>Any advice for dealing with this driver will be much appreciated. I really don't like the idea of allowing the interrupt to be disabled in the top-half of the driver yet not be re-enabled prior to existing the top-half drive code. This does not seem safe.</p>
  
  <p>Thanks,</p>
  
  <p>Jim</p>
  
  <p>PS: In my reading I've discovered threaded interrupts as a means to deal with the above-described requirements (at least that's my interpretation of web site articles such as <a href="http://lwn.net/Articles/302043/" rel="nofollow">http://lwn.net/Articles/302043/</a>). I'm not sure if the 2.6.10 kernel as provided by Phytec includes threaded interrupt functions.  I intend to look into this over the next few days.</p>