title: how to use alias commands in vhdl
body: <p>i use alias command in vhdl but had error "Index constraint cannot be applied to already-constrained type vec." </p>
  
  <p>my code is</p>
  
  <pre><code>    type vec is array (11 downto 0) of std_logic;
      signal s:vec;
      alias s1:vec (3 downto 0) is s(11 downto 8);
      alias s2:vec (4 downto 0) is s(7 downto  4);
  </code></pre>