title: Verilog Always block using (*) symbol
body: <p>I have a simple question regarding how to write an <code>always</code> block in a Verilog module.<br>
  If I have the following inputs in my Verilog module:   </p>
  
  <pre><code>input        [31:0] PCplus4 ;       // Value of PC + 4
  input        [31:0] A;          // Value A, i.e. RSbus (Use Forwarded Value)
  input        [31:0] B;          // Value B, i.e. RTbus (Use Forwarded Value)
  input        [31:0] IMM;            // Extended Immediate Value
  input        [25:0] TARGET;         // Target Address for Jumps
  input         [3:0] BR;         // Branch Selector Input
  </code></pre>
  
  <p>Is there any difference if I use  </p>
  
  <pre><code>always @ (*)  
  </code></pre>
  
  <p>instead of  </p>
  
  <pre><code>always @ (PCplus4  or A or B or IMM or TARGET or BR)  
  </code></pre>
  
  <p>Is this <code>always @ (*)</code>   syntax valid for all versions of Verilog?</p>