title: Error VHDL Quartus: can't determine definition of operator ""="" -- found 0 possible definitions
body: <p>I write this vhdl code but I have this problems:</p>
  
  <blockquote>
    <p>Error (10327): VHDL error at CircuitoCombinatorio.vhd(16): can't determine definition of operator ""="" -- found 0 possible definitions.</p>
  </blockquote>
  
  <p>Line error is: if(areset="1") then.</p>
  
  <pre><code>Library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  Entity CircuitoComparatore is
      port(a:in std_logic_vector(2 downto 0);
           clk,areset:in std_logic;
            u: out std_logic );
  end CircuitoComparatore;
  
  architecture ACircuitoComparatore of CircuitoComparatore is
      signal c,d: std_logic_vector(2 downto 0);
      begin
      c&lt;=a+"011";
      reg:process(areset,clk)
          begin
          if(areset="1") then
              d&lt;="000";
          elsif(ck'event and ck="1") then
              d&lt;=c;
          end if;
      end process reg;
     CMP:process(a,d)
     begin
     if(a&gt;d) then
          u&lt;="001";
      else 
          u&lt;="000";
      end if;
      end process CMP;
  end ACircuitoComparatore;   
  </code></pre>