title: Update variables within makefile label
body: <p>I have C++ static libraries and executable that uses them, each one is in a seperate folder. Each such project can be built in Debug or Release configuration, when the files hierarchy is like the following:
  Static_Lib1\Debug\staticlib1.a<br>
  Static_Lib1\Release\staticlib1.a<br>
  //same for all other static libraries<br>
  Executable\Debug\executable<br>
  Executable\Release\executable  </p>
  
  <p>All Debug and Release folders contain makefiles.<br>
  I'm trying to write an external makefile to call each one of the internal projects, using the selected configuration - debug or release.<br>
  So, I tried something like:  </p>
  
  <pre><code>CFG= #empty declaration  
  PROJECTS=Static_Lib1 Static_Lib2 ... Executable
  all:  
    release #default config is release  
  
  release:  
    CFG = Release  
    make build-all  
  
  debug:  
    CFG = Debug  
    make build-all  
  
  build-all:  
    make clean  
    $(foreach projectName, $(PROJECTS), cd $(projectName)/$(CFG) &amp;&amp; make all;)
  </code></pre>
  
  <p>But I get this output when trying, for example, to run <code>make debug</code>:  </p>
  
  <pre><code>CFG = Debug  
  make: CFG: Command not found  
  make: *** [debug] Error 127 
  </code></pre>
  
  <p>How can I fix this?<br>
  My OS is SLED 11x64.  </p>
  
  <p>Thank you in advance!  </p>