title: How to manage uninitialized input signals
body: <p>I would like to know your opinion on how to test and manage input signals of a component that are 'U', 'X', '-', ...</p>
  
  <p>For example, if I want the output to be 'X' for all non-valid inputs, where at least one bit of the input isn't '0' or '1':</p>
  
  <pre><code>entity foo is
      port (
          signal inp : std_logic_vector(7 downto 0);
          signal outp: std_logic );
  end entity foo;
  
  architecture bar of foo is
  begin
      process(inp)
          if (inp &lt; "11001010") then
              outp &lt;= '1';
          else
              outp &lt;= '0';
          end if;
      end process;
  end architecture bar;
  </code></pre>
  
  <p>This way, the test defaults to being false.</p>
  
  <p>How would be a general way to test the inputs?</p>