title: Illegal Concurrent Statement in VHDL?
body: <p>I've been trying to learn how to use conditional signal assignments in VHDL (which are the WHEN ELSE statements I believe?) and came up with what SHOULD be a simple code. But ModelSim doesn't let it compile and keeps telling me that I have an illegal concurrent statement. Where? Why? I've tried doing an IF ELSIF ELSE statement inside a process but I still got the exact same error so I'm now more confused than when I started...</p>
  
  <pre><code>Library ieee;
  Use ieee.std_logic_1164.all;
  
  Entity Q59122 is port (
      A, B : IN  STD_LOGIC;
      Y    : OUT STD_LOGIC
  );
  End Entity Q59122;
  
  ARCHITECTURE csa OF Q59122 IS
  BEGIN
      Y &lt;= '0' WHEN A = '0'
      ELSE Y &lt;= '0' WHEN B = '0'
      ELSE Y &lt;= '1';
  END csa;
  </code></pre>
  
  <p>Basically I'm trying to imitate an AND gate using conditional signal assignments. I know that there is an "and" command you can use in VHDL but that would defeat the purpose. Thanks for the help in advance. </p>