title: VHDL Type of xxx is incompatible with type of xxx
body: <p>Ich have two different types:</p>
  
  <pre><code>type signal_4bit_t is
  record
     signals_v      : STD_ULOGIC_VECTOR (3 downto 0);
  end record;
  
   type signal_8bit_t is
  record
     signals_v      : STD_ULOGIC_VECTOR (7 downto 0);
  end record;
  </code></pre>
  
  <p>and I create two Arrays:</p>
  
  <pre><code> type Array_signal_4bit_t   is array (0 to 2) of signal_4bit_t;
   type Array_signal_8bit_t   is array (0 to 2) of signal_8bit_t;
  </code></pre>
  
  <p>and one entity uses the 4bit Array as Input:</p>
  
  <pre><code>entity test_input is
      Port ( 
             hx_i      : in  Array_signal_4bit_t;
             lx_i      : in  Array_signal_4bit_t;
            );
  end test;
  </code></pre>
  
  <p>and another uses the 8bit Array as Output:</p>
  
  <pre><code>entity test_ouput is
      Port ( 
             out_o      : out Array_signal_8bit_t
            );
  end test;
  </code></pre>
  
  <p>For the Conncetion between the two components I use the signal:</p>
  
  <pre><code>signal tets_out_to_test_in   : Array_signal_8bit_t;
  </code></pre>
  
  <p>The Instantation looks like this:</p>
  
  <pre><code>in: test_input 
      Port Map ( 
             hx_i  =&gt;    tets_out_to_test_in(7 downto 4),
             lx_i  =&gt;    tets_out_to_test_in(3 downto 0)
            );
  
  out: test_out 
      Port Map ( 
             out_o  =&gt;    tets_out_to_test_in
            );
  </code></pre>
  
  <p>Now I get the error "Type of hx_i is incompatible with type of tets_out_to_test_in. I see that Array_signal_4bit_t is different to Array_signal_8bit_t, but is there a "easy" way to fix this problem without chanching my entites? Or any idea how I can solve this problem?</p>