title: VHDL nested case statement for some case options
body: <p>I am new to VHDL and working with case statements, I have something like the following:</p>
  
  <pre><code>process(state)
  begin
    case state is
      when stop =&gt;
        a &lt;= input;
        b &lt;= output;
      when move =&gt;
        a &lt;= input_1;
        b &lt;= output_1;
    end case;
  end process;
  </code></pre>
  
  <p>where a,b,input, output,input_1 and output 1 are signals.</p>
  
  <p>My issue is that I want to have a nested case in only one of the options:</p>
  
  <p>for example:</p>
  
  <pre><code>process(state)
  begin
    case state is
      when stop =&gt;
        a &lt;= input;  
        b &lt;= output;
      when move =&gt;
        a &lt;= if c='0' then input_1 else input_2;
        b &lt;= if c='0' then output_1 else output_2;
    end case;
  end process;
  </code></pre>
  
  <p>My question is can i do something like above where not all case options are nested but only some of them are or is there any other way in such situation , i tried using when else but got an error, saying that such syntax is not supported.</p>
  
  <p>Any help is appreciated</p>