title: Verilog: keep value in register (assign to same register)
body: <p>I want to keep the value in a register for arbitrary amount of clock cycles. Basically I want to do it similar like the treatment of a state machine:</p>
  
  <pre><code>always@ (posedge Clock ) begin
  if ( Reset ) CurrentState &lt;= STATE_Initial ;
  else CurrentState &lt;= NextState ;
  end
  
  always@ ( * ) begin
  NextState = CurrentState ;
    case ( CurrentState )
    STATE_Initial : begin
    NextState = STATE_1 ;
    end
    STATE_1 : begin
    NextState = STATE_2 ;
    end
    endcase
  end
  </code></pre>
  
  <p>My problem is now that I want to proceed in addition to that and similarly with a standard register of 24 bits: </p>
  
  <pre><code>always@ (posedge Clock ) begin
  if ( Reset )
    CurrentState &lt;= STATE_Initial ;
    curReg &lt;= 24'd0;
  else 
    CurrentState &lt;= NextState ;
    curReg &lt;= nextReg;
  end
  
  always@ ( * ) begin
  NextState = CurrentState ;
  nextReg = curReg;
    case ( CurrentState )
    STATE_Initial : begin
    NextState = STATE_1 ;
    nextReg = 24'd2048;
    end
    STATE_1 : begin
    NextState = STATE_2 ;
    nextReg = 24'd211;
    end
    endcase
  end
  </code></pre>
  
  <p>For me it seems to be treated the same way, but I always receive some errors that the timing constraints are not met. So, why is that a problem? </p>