title: floating point operations per cycle - intel
body: <p>I have been looking for quite a while and cannot seem to find an official/conclusive figure quoting the number of single precision floating point operations/clock cycle that an Intel Xeon quadcore can complete.  I have an Intel Xeon quadcore E5530 CPU.</p>
  <p>I'm hoping to use it to calculate the maximum theoretical FLOP/s my CPU can achieve.</p>
  <p>MAX FLOPS = (# Number of cores) * (Clock Frequency (cycles/sec) ) * (# FLOPS / cycle)</p>
  <p>Anything pointing me in the right direction would be useful.  I have found this
  <a href="https://stackoverflow.com/questions/15655835/flops-per-cycle-for-sandy-bridge-and-haswell-sse2-avx-avx2">FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2</a></p>
  <blockquote>
  <p>Intel Core 2 and Nehalem:</p>
  <p>4 DP FLOPs/cycle: 2-wide SSE2 addition + 2-wide SSE2 multiplication</p>
  <p>8 SP FLOPs/cycle: 4-wide SSE addition + 4-wide SSE multiplication</p>
  </blockquote>
  <p>But I'm not sure where these figures were found.  Are they assuming a fused multiply add (FMAD) operation?</p>
  <p>EDIT: Using this, in DP I calculate the correct DP arithmetic throughput cited by Intel as 38.4 GFLOP/s (cited <a href="http://download.intel.com/support/processors/xeon/sb/xeon_5500.pdf" rel="noreferrer">here</a>).  For SP, I get double that, 76.8 GFLOP/s.  I'm pretty sure 4 DP FLOP/cycle and 8 SP FLOP/cycle is correct, I just want confirmation of how they got the FLOPs/cycle value of 4 and 8.</p>