title: SystemVerilog: derive input width from parameter
body: <p>I have an input whose width I want to determine at elaboration time. Instead of feeding two parameters I want to determine the width derived from a single parameter. Something like this:</p>
  
  <pre><code>module my_module #(
    COUNT = 9
  ) (
    [bitwidth(COUNT)-1:0] index
  );
  </code></pre>
  
  <p>I have a function which works for me if I declare a reg internal to my module <em>but</em> I need this to be driven externally via the port map.</p>
  
  <pre><code>function integer bitwidth;
    input integer n;
    integer exp2, width;
  begin
    width=1;
    for (exp2=1; exp2&lt;&lt;1 &lt;= n; exp2=exp2&lt;&lt;1)
      width=width+1;
    bitwidth = width;
  end
  endfunction
  
  reg [bitwidth(COUNT)-1:0] this_works = COUNT;
  </code></pre>
  
  <p>How do I accomplish this? Can I utilize an interface (+modports) to get me what I want?</p>