title: using a conditional variable which is defined later in verilog
body: <p>Suppose I have the following instantiation<br>
  <code>first_mux_input=top.middle.down[i]; 
   second_mux_input=top.middle.down[i+1]; 
   assign down = (select[i])? first_mux_input:second_mux_input;</code>  </p>
  
  <p>supposing there are a lot of muxes and their outputs go to the inputs to muxes that are placed below them.  </p>
  
  <p>I'm using the variable "down" before I define it. is this legal since verilog compiles all the lines subsequently and not by order(in this case)?<br>
  thanks</p>