title: Verilog - individual output arrays
body: <p>This is my first time on stackoverflow.com and new to verilog coding.  I may use some terms  incorrectly so if I do please correct me so I can be clearer in future posts.</p>
  
  <p>I am using an Altera FPGA board where there are 7 LEDG lights which can be triggered on and off.  For my project I am making a BCD adder where LEDG [7] turns on when the BCD value is not 0 - 9.  However, I don't want to declare outputs [6:4].  LEDG[3:0] displays the binary equivalent of the summation of the two inputs.</p>
  
  <p>I thought I could use two separate declaration statements but it tells me that LEDG is already declared which it is.  I then tried to combine it using brackets but it also complained about that.  Is there any way to simplify my code.  Below are examples of what I've tried.</p>
  
  <p>Example 1:</p>
  
  <blockquote>
  <pre><code>module BCD (..., LEDG, ...);
  output reg [3:0] LEDG;
  output reg [7] LEDG;
  endmodule
  </code></pre>
  </blockquote>
  
  <p>Example 2:</p>
  
  <pre><code>module BCD (..., LEDG, ...);
  output reg ({[3:0], [7]} LEDG);
  endmodule
  </code></pre>
  
  <p>Any help would be greatly appreciated!  Thanks in advance. :-)</p>