title: VHDL multiplexing seven segment display
body: <p>I am trying to implement a half adder. I am using a multiplexer to drive two digits on a seven segment display on a board with a 32 MHz clock. I want each digit (connected to active-low anodes 0 and 1) to be on for 1 ms. I am using a counter to try to achieve this.</p>
  
  <p>The multiplexer code is below. Cmux and Smux are vectors representing the seven segments (plus the decimal point) for the carry and sum, which are being multiplexed. </p>
  
  <p>The code I have written is below. I am getting the error FF/latch seg has a constant value in block mux.  </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_arith.all;
  
  entity mux is
      port(Cmux, Smux: in std_logic_vector(7 downto 0);
           CLK: in std_logic;
           Seg: inout std_logic_vector(7 downto 0);
           AN0, AN1: out std_logic);
  end mux;
  
  architecture Behavioral of mux is
      signal counter: integer range 0 to 32000 := 0;
  begin
      process(CLK)
      begin
          if CLK'event and CLK='1' then
              if counter = 32000 then
                  if Seg = Cmux then
                      Seg &lt;= Smux;
                      AN0 &lt;= '1';
                      AN1 &lt;= '0';
                  else
                      if Seg = Smux then
                          Seg &lt;= Cmux;
                          AN0 &lt;= '0';
                          AN1 &lt;= '1';
                      else
                          Seg &lt;= Smux;
                          AN0 &lt;= '1';
                          AN1 &lt;= '0';
                      end if;
                      counter &lt;= 0;
                  end if;
              else
                  counter &lt;= counter + 1;
              end if;
          end if;
      end process;
  end Behavioral;
  </code></pre>