title: Makefile wildcard dependencies
body: <p>I want to include all .cpp and .cc files in the dependencies of a target using a wildcard.</p>
  
  <p>Currently, I have to do the following:</p>
  
  <pre><code>all: main.cpp file1.cc file2.cc
      g++ -O3 -o all main.cpp file1.cc file2.cc -I./include -L./lib
  </code></pre>
  
  <p>The following does not seem to be working:</p>
  
  <pre><code>all: %.cpp %.cc
      g++ -O3 -o $@ $^ -I./include -L./lib
  </code></pre>
  
  <p>I get as error make: *** No rule to make target '%.cc', needed by 'all'.  Stop.</p>