title: Parameterized function errors
body: <p>I am trying to write the following systemverilog code where different parameters can be used for functions, so the same functions can be reused just by changing parameters instead of using parameterized modules.</p>
  
  <p>My following code compiles without error, but when I try to simulate with the testbench it gives error 211 in Modelsim. I have seen people suggesting it has something to do with the version of Modlesim, so I tried with 2 different versions and it is giving the same error. I think its not a modelsim version problem, because some of the functions works ok, but some doesnt. </p>
  
  <p>The code is quite simple, so it should work. But the error occurs when the 2nd function is calling the 1st function. Can you see any error in there or in any other part of the code that the simulation fails?  </p>
  
  <pre><code>   /************This package is used in the module*************/
  
      package RealARITH;
  
  
      typedef struct {
          int  WIDTH_INT;
          int  WIDTH_FRAC;
          int SIG_TYPE;
          } FixP;
  
  
      /************1st parameterized function*************/
  
      virtual class resize_verilog 
     # (parameter Total_width_InB = 3, 
     parameter Total_width_InA = 4);
  
     static function [Total_width_InB-1:0] resize_verilog(input logic     [Total_width_InA-1:0] InA);
  
      logic [Total_width_InB-1:0] InB;
  
      InB = $signed(InA);
      if (Total_width_InA &gt; Total_width_InB)
      InB[Total_width_InB-1] = InA[Total_width_InA-1];
  
     return InB;
  
     endfunction
     endclass
  
     /***************the 2nd parameterized function that uses the 1st function*/
  
     virtual class align_un
     # (
     parameter FixP InA_FixP = {2,3,1},
     parameter FixP InB_FixP = {2,3,1},
     parameter ExtraMSB = 0);
  
     static function [InB_FixP.WIDTH_INT+InB_FixP.WIDTH_FRAC+1:0]   RealALIGN_SIGNED(input logic    [InA_FixP.WIDTH_INT+InA_FixP.WIDTH_FRAC+InA_FixP.SIG_TYPE-1:0] InA);
  
     localparam Total_width_InA =     InA_FixP.WIDTH_INT+InA_FixP.WIDTH_FRAC+InA_FixP.SIG_TYPE;
     localparam Total_width_InB = InB_FixP.WIDTH_INT + InA_FixP.WIDTH_FRAC + 1;
  
  
     logic [Total_width_InB-1:0] InB;
  
     InB = resize_verilog #   (.Total_width_InA(Total_width_InA),.Total_width_InB(Total_width_InB))::resize_verilog(InA);  
  
     return InB;
  
  
     endfunction
  
  endclass    
  
  endpackage
  
  /************module where the 2nd function  called from package********/
  
  module test_align
  import RealARITH::*; 
  (
  input logic [15:0] A,
  output logic [18:0] B1);
  
  parameter FixP InA = {5,10,1};
  parameter FixP InB1 = {10,8,1};
  
  assign B1 = align_un #(.InA_FixP(InA),.InB_FixP(InB1),.ExtraMSB(1))::RealALIGN_SIGNED(A);
  
  endmodule 
  
  
  /**************testbench***********************/
  
  module test_align_tb;
  
  logic [15:0] A;
  logic [18:0] B1;
  
  test_align DUT (.*);
  
  initial 
  
  begin
  
  A = '0; 
  
  # 10
  
  A = 16'b0000000110000001;
  
  end
  
  endmodule 
  
  /****************  Code ends here ***************************/
  </code></pre>
  
  <p>The error shown is given here:</p>
  
  <pre><code># Attempting stack trace sig 11
  # Signal caught: signo [11]
  # vsim_stacktrace.vstf written
  # Current time Fri Feb 13 10:42:19 2015
  # QuestaSim Stack Trace
  # Program = vsim
  # Id = "10.3"
  # Version = "2014.01"
  # Date = "Jan  6 2014"
  # Platform = linux_x86_64
  # 0    0x00007fefec1e40ca: '/home/sshahabu/Structure_test6_align_again/test.sv:49'
  # 1    0x00000000007160a8: '&lt;unknown (@0x7160a8)&gt;'
  # 2    0x0000000000716dd4: '&lt;unknown (@0x716dd4)&gt;'
  # 3    0x00007fefec1e5cd6: '/home/sshahabu/Structure_test6_align_again/test.sv:17'
  # 4    0x0000000000575364: '&lt;unknown (@0x575364)&gt;'
  # 5    0x00007fefec1e48b4: '/home/sshahabu/Structure_test6_align_again/test.sv:49'
  # 6    0x0000000000575364: '&lt;unknown (@0x575364)&gt;'
  # 7    0x00007fefec1e76eb: '/home/sshahabu/Structure_test6_align_again/test.sv:71'
  # 8    0x0000000000581a1c: '&lt;unknown (@0x581a1c)&gt;'
  # 9    0x00000000006f0d07: '&lt;unknown (@0x6f0d07)&gt;'
  # 10   0x00007fefec1e3b6e: '&lt;unknown (@0x7fefec1e3b6e)&gt;'
  # 11   0x0000000000581a1c: '&lt;unknown (@0x581a1c)&gt;'
  # 12   0x00000000006f0d07: '&lt;unknown (@0x6f0d07)&gt;'
  # 13   0x00000000006f0f8c: '&lt;unknown (@0x6f0f8c)&gt;'
  # 14   0x00000000006f11c9: '&lt;unknown (@0x6f11c9)&gt;'
  # 15   0x00000000006f1f0e: '&lt;unknown (@0x6f1f0e)&gt;'
  # 16   0x000000000074ff98: '&lt;unknown (@0x74ff98)&gt;'
  # 17   0x0000000000751207: '&lt;unknown (@0x751207)&gt;'
  # 18   0x0000000000aba60d: '&lt;unknown (@0xaba60d)&gt;'
  # 19   0x00000000013c3a1f: '&lt;unknown (@0x13c3a1f)&gt;'
  # 20   0x00000000013c4bd9: '&lt;unknown (@0x13c4bd9)&gt;'
  # 21   0x000000000140739a: '&lt;unknown (@0x140739a)&gt;'
  # 22   0x000000000140fecf: '&lt;unknown (@0x140fecf)&gt;'
  # 23   0x00000000013c5ef3: '&lt;unknown (@0x13c5ef3)&gt;'
  # 24   0x00000000013d0d84: '&lt;unknown (@0x13d0d84)&gt;'
  # 25   0x00000000013c4bd9: '&lt;unknown (@0x13c4bd9)&gt;'
  # 26   0x000000000140739a: '&lt;unknown (@0x140739a)&gt;'
  # 27   0x00000000014101f0: '&lt;unknown (@0x14101f0)&gt;'
  # 28   0x00000000013c35c3: '&lt;unknown (@0x13c35c3)&gt;'
  # 29   0x00000000013d6088: '&lt;unknown (@0x13d6088)&gt;'
  # 30   0x00000000013c4bd9: '&lt;unknown (@0x13c4bd9)&gt;'
  # 31   0x00000000013c5826: '&lt;unknown (@0x13c5826)&gt;'
  # 32   0x00000000013c5ba6: '&lt;unknown (@0x13c5ba6)&gt;'
  # 33   0x0000000001102c3c: '&lt;unknown (@0x1102c3c)&gt;'
  # 34   0x0000000001420bf1: '&lt;unknown (@0x1420bf1)&gt;'
  # 35   0x0000000001469f81: '&lt;unknown (@0x1469f81)&gt;'
  # 36   0x00000000014366ad: '&lt;unknown (@0x14366ad)&gt;'
  # 37   0x00000000014369e5: '&lt;unknown (@0x14369e5)&gt;'
  # 38   0x00000000012e02b6: '&lt;unknown (@0x12e02b6)&gt;'
  # 39   0x000000000089c9cb: '&lt;unknown (@0x89c9cb)&gt;'
  # End of Stack Trace
  
  
  ** Fatal: (SIGSEGV) Bad pointer access. Closing vsimk.
  ** Fatal: vsimk is exiting with code 211.
  (Exit codes are defined in the QuestaSim messages appendix
  of the QuestaSim User's Manual.)
  </code></pre>
  
  <hr>
  
  <p>17th line of the code:</p>
  
  <pre><code>virtual class resize_verilog 
  # (parameter Total_width_InB = 3, 
  parameter Total_width_InA = 4);
  </code></pre>
  
  <p>49th line  of the code:</p>
  
  <pre><code> InB = resize_verilog # (.Total_width_InA(Total_width_InA),.Total_width_InB(Total_width_InB))::resize_verilog(InA);
  </code></pre>
  
  <p>71st line:</p>
  
  <pre><code>assign B1 = align_un #(.InA_FixP(InA),.InB_FixP(InB1),.ExtraMSB(1))::RealALIGN_SIGNED(A);
  </code></pre>