title: MSI/MESI: How can we get "read miss" in shared state?
body: <p>In The Cache Memory Book by Jim Handy (excerpt is below), the author has  the table description of MESI protocol. The table looks very unclear to me, and unfortunately the text does not help.</p>
  
  <p>The first question (in green on the picture):</p>
  
  <pre><code>Is this right? -- a data block is in the cache of a CPU,
  and it is in the shared state, but when the CPU reads it, 
  the CPU gets read miss. 
  How is this possible?
  </code></pre>
  
  <p>The second question (in purple): </p>
  
  <pre><code>Who and when create all these messages "Read miss", etc.?
  (afaik, the system bus just translates messages of others) 
  </code></pre>
  
  <p>And finally, the third question (not on the pic):</p>
  
  <pre><code>Do all these cache coherency protocols 
  (MSI,MESI,MOESI,Firefly,Dragon...)
  maintain sequential consistency memory model?
  Are there protocols that maintain other consistency models?
  </code></pre>
  
  <p><img src="https://i.stack.imgur.com/IVgZ6.jpg" alt="Mesi protocol description"></p>