title: How to handle the interface with package in systemverilog
body: <p>I am creating a simple uvm tb these days and I meet an issue with interface usage. Here is my code. </p>
  
  <p>in the /my_proj/tb_uvm/intf/my_if.svh file: (interface definition)</p>
  
  <pre><code>interface my_if (
      input iCLK,
      input iRSTb,
      inout data
  );
  clocking monitor_cb @(posedge iCLK);
      input iRSTb;
      input data;
  endclocking
  modport monitor_mp(
      clocking monitor_cb
  ); 
  endinterface : my_if
  </code></pre>
  
  <p>and I need to instance this interface in the /my_proj/tb_uvm/agent/my_driver.svh file :</p>
  
  <pre><code>class my_driver extends uvm_driver;
      `uvm_component_utils(my_driver)
      virtual my_if m_vif;
      ...
  endclass
  </code></pre>
  
  <p>I tried to define a package file(named my_agt_pkg.sv) under /my_proj/tb_uvm/agent/ because there are several driver/monitor files in this directory including the my_driver.svh I mentioned above. </p>
  
  <pre><code>package my_agt_pkg;
      import uvm_pkg::*;
  
      `include "my_driver.svh"
      `include "../intf/my_if.svh"
       ....
  endpackage
  </code></pre>
  
  <p>but I failed to compile because of below error. Could anyone kindly give me a help on this issue ? </p>
  
  <p>Found 'interface' inside package before 'endpackage'. 'interface' inside   'package' is not allowed.</p>