title: Verilog : Use of assign and always
body: <pre><code>module circuit_1 (a, b, c);
  input [1:0J a,b;
  output [3:0J c;
  assign c = a + b;
  </code></pre>
  
  <p>If input a = 2'b11 and input b = 2'b10, </p>
  
  <p>what value would output c have ? Please give a descriptive answer.</p>
  
  <p>Also kindly tell me functionality of assign and always. I am a bit confused.</p>