title: SystemVerilog macros not needing a ';' at the end of a line
body: <p>In <em>SystemVerilog</em>, it is not required to add a '<code>;</code>' at the end of a line.  For example:  </p>
  
  <pre><code>`uvm_do(pkt) 
  </code></pre>
  
  <p>I wonder why the compiler can handle this, but can't handle regular lines without the '<code>;</code>'.  </p>