title: How to load a text file on a ram in VHDL?
body: <p>i have a text file describing an image in terms of it's RGB components i want to load that file on the FPGA to produce a RGB signal so if you would be kind enough to enlighten me i would be thankful</p>
  
  <p>Okey so this is what i came up with but there's a problem the synthesis is taking forever to finish, so what do you think is the problem here ??!</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use STD.TEXTIO.ALL; 
  
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  --use IEEE.NUMERIC_STD.ALL;
  
  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  entity RGB_Gen is
  
    port(CLK : in STD_LOGIC;
         EN : in STD_LOGIC;
           R,G,B : out STD_LOGIC);
  
  end RGB_Gen;
  
  architecture Behavioral of RGB_Gen is
  
    Type ram is array (0 to 611) of BIT_VECTOR(203 downto 0);
  
    impure function InitRamFromFile(Filename : in string) return ram is
  
     File readFile : text is in Filename;
     Variable lineRead : Line;
      Variable my_ram : ram;
  
      begin
  
        for i in ram'range loop
           readline(readFile, lineRead);
           read(lineRead, my_ram(i));
       end loop;
  
       return my_ram;
  
    end function;
  
    function toSTD(B : in Bit) return STD_LOGIC is
    begin    
          if B = '1' then 
             return '1';
          else 
             return '0';
        end if;
    end function;
  
    Signal my_ram : ram := InitRamFromFile("C:\Users\Mos_X\Desktop\output.txt");
  
    begin
  
      process(CLK)
  
       Variable X : Integer := 0;
       Variable Y : Integer := 0;
  
       begin
  
       if rising_edge(CLK) then
         if EN = '0' then 
            R &lt;= '0';
              G &lt;= '0';
              B &lt;= '0';
          else 
             R &lt;= toSTD((my_ram(Y)(X)));
              G &lt;= toSTD((my_ram(Y + 204)(X)));
              G &lt;= toSTD((my_ram(Y + 408)(X)));       
          end if;
  
         if X = 203 then 
             X := 0;
           if Y = 203 then 
              Y := 0;
           else
              Y := Y + 1;
             end if;
          else 
             X := X + 1;
          end if;
  
      end if;
  
   end process;
  
  end Behavioral;
  </code></pre>