title: How to resolve "Register/latch pins with no clock driven by root clock pin" error in Vivado?
body: <p>As a learning exercise I am doing some HDMI experiments on an FPGA using VHDL. When coming to implement it in Vivado (2017.1) I am encountering the following warning in the timing report:</p>
  
  <pre><code>There are 11 register/latch pins with no clock driven by root clock pin: Hsync_i_reg/Q (HIGH)
  </code></pre>
  
  <p>I have opened the implemented schematic and looked for the pin in question. It seems to be connected to the same clock that everything else is connected to (and those are not flagged in the timing report), so I am confused as to what the errors above are referring to. Here are some shots from the schematics:</p>
  
  <p><a href="https://i.stack.imgur.com/5ILOa.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5ILOa.png" alt="enter image description here"></a>
  <a href="https://i.stack.imgur.com/Y6NMe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Y6NMe.png" alt="enter image description here"></a></p>
  
  <p>Here is the VHDL code of the offending design:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity ctrl_gen is
      generic (
          ha: integer := 96; --hpulse
          hb: integer := 144; --hpulse+hbp
          hc: integer := 784; --hpulse+hbp+hactive
          hd: integer := 800; --hpulse+hbp+hactive+hfp
          va: integer := 2; --vpulse
          vb: integer := 35; --vpulse+vbp
          vc: integer := 515; --vpulse+vbp+vactive
          vd: integer := 525 --vpulse+vbp+vactive+vfp
      );
      port (
          clk25: in std_logic; --tmds clock (25mhz)
          hsync: out std_logic; --horizontal sync
          vsync: out std_logic; --vertical sync
          hactive: out std_logic; --active portion of hsync
          vactive: out std_logic; --active portion of vsync
          dena: out std_logic --display enable
      );
  end entity;
  
  architecture behavioral of ctrl_gen is
      signal hsync_i, hactive_i, vactive_i, vsync_i : std_logic;
  begin
      -- horizontal signals generation
      hproc : process (clk25)
          variable hcount: integer range 0 to hd := 0;
      begin
          if rising_edge(clk25) then
              hcount := hcount + 1;
  
              if (hcount=ha) then
                  hsync_i &lt;= '1';
              elsif (hcount=hb) then
                  hactive_i &lt;= '1';
              elsif (hcount=hc) then
                  hactive_i &lt;= '0';
              elsif (hcount=hd) then
                  hsync_i &lt;= '0';
                  hcount := 0;
              end if;
          end if;
      end process;
  
      -- vertical signals generation
      vproc : process (hsync_i)
          variable vcount: integer range 0 to vd := 0;
      begin
          if falling_edge(hsync_i) then
              vcount := vcount + 1;
  
              if (vcount=va) then
                  vsync_i &lt;= '1';
              elsif (vcount=vb) then
                  vactive_i &lt;= '1';
              elsif (vcount=vc) then
                  vactive_i &lt;= '0';
              elsif (vcount=vd) then
                  vsync_i &lt;= '0';
                  vcount    := 0;
              end if;
          end if;
      end process;
  
      dena &lt;= hactive_i and vactive_i;
      hsync &lt;= hsync_i;
      vactive &lt;= vactive_i;
      hactive &lt;= hactive_i;
  end behavioral;
  </code></pre>
  
  <p>On reflection, I think that the warning is telling me that Hsync_i_reg/Q is the clock used for the Vcount registers, not that Hsync_i_reg itself if not connected to the root clock pin?</p>
  
  <p>Is the method I have used bad practice and unlikely to work? The overall design is not working and I'm trying to understand whether this is the cause.</p>
  
  <p>Thanks.</p>