title: Address of array provided as std_logic_vector
body: <p>I'm trying to construct a ROM, which has as declaration <code>a : in std_logic_vector(5 downto 0)</code> for the access address. My problem its that I don't know how to access the ROM array with a std_logic_vector, Should I use a cast to integer or what else  can I do?</p>
  
  <p>My code:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  --------------------------------------------------------------------------------
  entity imem is
      GENERIC(CONSTANT N : INTEGER := 32);
      port (a : in std_logic_vector(5 downto 0);
           result : out std_logic_vector(N-1 downto 0));
  end imem;
  
  
  architecture behavior of imem is
      signal addres : integer;
      type memory is array (0 to 64) of std_logic_vector(N-1 downto 0) ;
      constant myrom : memory := (
           2 =&gt; x"11111111" , --255
           3 =&gt; x"11010101" , 
           4 =&gt; x"01101000" , 
           6 =&gt; x"10011011" , 
           8 =&gt; x"01101101" , 
           9 =&gt; x"00110111" , 
           others =&gt; x"00000000" ) ;
  
  begin 
      addres &lt;= signed(a);
      result &lt;= memory(addres);
  
  end behavior;
  </code></pre>
  
  <p>With this code as shown I get the following error: </p>
  
  <pre><code>imem.vhd:25:21: can't match type conversion with type integer  
  imem.vhd:25:21: (location of type conversion)
  imem.vhd:26:21: conversion not allowed between not closely related types  
  imem.vhd:26:21: can't match type conversion with type array type "std_logic_vector"
  imem.vhd:26:21: (location of type conversion)
  ghdl: compilation error  
  </code></pre>