title: Warning "has no load", but I can't see why
body: <p>I got these warnings from Lattice Diamond for each instance of any uart (currently 11)</p>
  
  <pre><code>WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_14' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_0_COUT1_9_14' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_12' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_10' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_8' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_6' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_4' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_2' has no load
  WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_0' has no load
  </code></pre>
  
  <p>The VHDL-code is</p>
  
  <pre><code>entity UART is 
      generic (
          dividerCounterBits: integer := 16
      );
      port (
          Clk         : in  std_logic;                        -- Clock signal
          Reset       : in  std_logic;                        -- Reset input
          ClockDivider: in  std_logic_vector(15 downto 0);
  
          ParityMode  : in std_logic_vector(1 downto 0);      -- b00=No, b01=Even, b10=Odd, b11=UserBit
      [...]
  
  
  architecture Behaviour of UART is
      constant oversampleExponent : integer := 4;
  
      subtype TxCounterType is integer range 0 to (2**(dividerCounterBits+oversampleExponent))-1;
      subtype RxCounterType is integer range 0 to (2**dividerCounterBits)-1;
      signal rxCounter: RxCounterType;
      signal txCounter: TxCounterType;
      signal rxClockEn: std_logic; -- clock enable signal for receiver
      signal txClockEn: std_logic; -- clock enable signal for transmitter
  begin
      rxClockdivider:process (Clk, Reset)
      begin
          if Reset='1' then
          rxCounter &lt;= 0;
          rxClockEn &lt;= '0';
      elsif Rising_Edge(Clk) then
          -- RX counter (oversampled)
          if rxCounter = 0 then
              rxClockEn &lt;= '1';
              rxCounter &lt;= to_integer(unsigned(ClockDivider));
          else
              rxClockEn &lt;= '0';
              rxCounter &lt;= rxCounter - 1;
          end if;
      end if;
      end process;
  
      txClockDivider: process (Clk, Reset)
      [...]
  
      rx: entity work.RxUnit
      generic map (oversampleFactor=&gt;2**oversampleExponent)
      port map (Clk=&gt;Clk, Reset=&gt;Reset, ClockEnable=&gt;rxClockEn, ParityMode=&gt;ParityMode,
              ReadA=&gt;ReadA, DataO=&gt;DataO, RxD=&gt;RxD, RxAv=&gt;RxAv, ParityBit=&gt;ParityBit,
              debugout=&gt;debugout
               );
  
  end Behaviour;
  </code></pre>
  
  <p>This is a single Uart, to create them all (currently 11 uarts) I use this</p>
  
  <pre><code>-- UARTs
  
      UartGenerator: For i IN 0 to uarts-1 generate
      begin
          Uart_i : entity work.UartBusInterface 
              port map (Clk=&gt;r_qclk, Reset=&gt;r_reset, 
                  cs=&gt;uartChipSelect(i), nWriteStrobe=&gt;wr_strobe, nReadStrobe=&gt;rd_strobe,
                  address=&gt;AdrBus(1 downto 0), Databus=&gt;DataBus,
                  TxD=&gt;TxD_PAD_O(i), RxD=&gt;RxD_PAD_I(i),
                  txInterrupt=&gt;TxIRQ(i), rxInterrupt=&gt;RxIRQ(i), debugout=&gt;rxdebug(i));
  
          uartChipSelect(i) &lt;= '1' when to_integer(unsigned(adrbus(5 downto 2)))=i+4 and r_cs0='0' else '0';
      end generate;
  </code></pre>
  
  <p>I can syntesis it and the uarts work, but why I got the warning?  </p>
  
  <p>IMHO the rxCounter should use each single possible value, but why each second bit creates the warning <strong>"has no load"</strong>?  </p>
  
  <p>I read somewhere that this mean that these net's aren't used and will be removed.<br>
  But to count from 0 to 2^n-1, I need no less than n-bits.</p>