title: Adding 2 std_logic_vector in variable type VHDL
body: <p>I'm working in this school project.
  I have two std_logic_vector (31 downto 0) A and B, and I have a variable type std_logic_vector (32 downto 0) and I want to add A+B and put the result in my std_logic_vector with 32 bits.</p>
  
  <p>This is my design:</p>
  
  <pre><code>library IEEE;    
  use IEEE.STD_LOGIC_1164.ALL;    
  USE ieee.numeric_std.ALL;    
  use ieee.std_logic_arith.all;
  
  entity Ej3 is
      Port ( A :     in  STD_LOGIC_VECTOR (31 downto 0);   
             B :     in  STD_LOGIC_VECTOR (31 downto 0);    
             S :     out STD_LOGIC_VECTOR (31 downto 0);    
             AluOp : in  STD_LOGIC_VECTOR (3 downto 0);    
             COut :  out STD_LOGIC;   
             Z :     out STD_LOGIC;    
             OFL :   out STD_LOGIC);    
  end Ej3;
  
  
  architecture Behavioral of Ej3 is
  
      begin
  
      process(AluOp)    
          variable Temp: STD_LOGIC_VECTOR (32 downto 0);   
      begin
  
          Temp := A+B;
  </code></pre>
  
  <p>And I have this error: <strong>found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"</strong></p>
  
  <p>Can someone help??</p>