title: ARM IT conditional instruction assembler (armcc)
body: <p>why below  compiles :</p>
  
  <pre> <code>
      ITE EQ         
      MRSEQ  R0, MSP
      MRSNE   R0, PSP        </code></pre>
  
  <p>but this not:<pre> <code>
      ITT NE<br>
      MRSNE   R0, PSP<br>
      MRSEQ  R0, MSP </code></pre>
  Is it possible, that both  MRSNE   R0, PSP and MRSEQ  R0, MSP execute (this is my case)?</p>
  
  <pre>This compiles:</pre>
  
  <pre> <code>
      ITT NE         
      MRSNE   R0, PSP       
      MRSNE  R0, MSP </code></pre>
  
  <p>Is it ARM standard?</p>