title: vlog-7 error. failed to open design unit file in read mode
body: <p>i am trying to run an example design by IntelFPGA, using a tcl script provided by Intel. It reports 'error (vlog-7) failed to open unit file "blabla" in read mode. No such file or directory (errno = ENOENT). i can not find the error. Then i tried a modelsim project i used earlier, which used to work. I get the same error! What could be wrong?</p>
  
  <h1>At start of tb_run.tcl (run from commandline MODELSIM> VHDL 2008 do tb_run.tcl), this tb_run.tcl file is generated by quartus example</h1>
  
  <pre><code>global env ;
  
  # set QUARTUS_INSTALL_DIR "$env(QUARTUS_ROOTDIR)" =&gt; initially i thought
  # there is something wrong with the rootdir, so i changed to the row 
  # below:
  set QUARTUS_INSTALL_DIR "C:/intelFPGA/18.0/quartus"
  set SETUP_SCRIPTS ../setup_scripts
  set tb_top_waveform msim_wave.do
  set QSYS_SIMDIR "./../setup_scripts"
  
  set TOP_LEVEL_NAME tb_top
  
  source $SETUP_SCRIPTS/mentor/msim_setup.tcl
  
  # Compile device library files
  
  dev_com 
  </code></pre>
  
  <p>================================================
  => dev_com, this is line 29, here the error occurs, see below</p>
  
  <p>modelsim reports:</p>
  
  <pre><code>Modelsim&gt; VHDL 2008 do tb_run.tcl
  # C:/intelFPGA/18.0/quartus
  # ../setup_scripts
  # msim_wave.do
  # ./../setup_scripts
  # tb_top
  # [exec] file_copy
  # List Of Command Line Aliases
  # 
  # file_copy                                         -- Copy ROM/RAM files to simulation directory
  # 
  # dev_com                                           -- Compile device library files
  # 
  # com                                               -- Compile the design files in correct order
  # 
  # elab                                              -- Elaborate top level design
  # 
  # elab_debug                                        -- Elaborate the top level design with novopt option
  # 
  # ld                                                -- Compile all the design files and elaborate the top level design
  # 
  # ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
  # 
  # 
  # 
  # List Of Variables
  # 
  # TOP_LEVEL_NAME                                    -- Top level module name.
  #                                                      For most designs, this should be overridden
  #                                                      to enable the elab/elab_debug aliases.
  # 
  # SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
  # 
  # QSYS_SIMDIR                                       -- Qsys base simulation directory.
  # 
  # QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
  # 
  # USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
  # 
  # USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
  # 
  # USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
  # 
  # USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
  # 
  # SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
  # 
  # FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
  # [exec] dev_com
  # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017
  # Start time: 10:43:14 on Jun 25,2019
  # vlog -reportprogress 300 C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver 
  # ** Error: (vlog-7) Failed to open design unit file "C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v" in read mode.
  # No such file or directory. (errno = ENOENT)
  # End time: 10:43:14 on Jun 25,2019, Elapsed time: 0:00:00
  # Errors: 1, Warnings: 0
  # ** Error: C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
  # Error in macro ./tb_run.tcl line 29
  # C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
  #     while executing
  # "vlog C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver"
  #     ("eval" body line 1)
  #     invoked from within
  # "eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"             ..."
  #     invoked from within
  # "if [string is false -strict [modelsim_ae_select $FORCE_MODELSIM_AE_SELECTION]] {
  #     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_CO..."
  #     ("eval" body line 5)
  #     invoked from within
  # "dev_com "
  </code></pre>