title: Why didn't x86 implement direct core-to-core messaging assembly/cpu instructions?
body: <p>After serious development, CPUs gained many cores, gained distributed blocks of cores on multiple chiplets, numa systems, etc but still a piece of data has to pass through not only L1 cache (if on same core SMT) but also some atomic/mutex synchronization primitive procedure that is not accelerated by hardware.</p>
  <p>I wonder why didn't Intel or IBM come up with something like:</p>
  <pre><code>movcor 1 MX 5 &lt;---- sends 5 to Messaging register of core 1
  pipe 1 1 1 &lt;---- pushes data=1 to pipe=1 of core=1 and core1 needs to pop it
  bcast 1 &lt;--- broadcasts 1 to all cores' pipe-0 
  </code></pre>
  <p>to make it much faster than some other methods? GPUs support block-wise fast synchronization points, like <code>barrier()</code> or <code>__syncthreads()</code>. GPUs also support parallel atomic update acceleration for local arrays.</p>
  <p>When CPUs gain 256 cores, won't this feature enable serious scaling for various algorithms that are bottlenecked on core-to-core bandwidth (and/or latency)?</p>