title: What is the purpose of the `std_logic` enumerated type in VHDL?
body: <p>What is the purpose of the <code>std_logic</code> enumerated type?</p>
  
  <pre><code>'U': uninitialized. This signal hasn't been set yet.
  'X': unknown. Impossible to determine this value/result.
  '0': logic 0
  '1': logic 1
  'Z': High Impedance
  'W': Weak signal, can't tell if it should be 0 or 1.
  'L': Weak signal that should probably go to 0
  'H': Weak signal that should probably go to 1
  '-': Don't care. 
  </code></pre>