title: How to initialize a wire with constant in verilog ?
body: <p>In the below mentioned verilog code for J-K Flip Flop , i want to initialize wire type q and q_bar with some value. For eg : I am initializing here q and q_bar with 0. But in the output, q and q_bar has don't care (1'hx) value . So how to initialize wire type with constant ?      </p>
  
  <pre><code>module JK_FF(j,k,clk,q,q_bar) ;
  input j,k,clk ;
  output q , q_bar  ;
  wire s,r,w,z ;
  
  assign w = q ;
  assign z = q_bar ;
  
  nand U1(s,j,clk,z) ;
  nand U2(r,k,clk,w) ;
  nand U3(q,s,z) ;
  nand U4(q_bar,r,w) ;
  
  endmodule
  
  /*  TEST BENCH  */
  
  module JK_FF_TB ;
  
  reg j,k,clk ;
  wire q , q_bar ;
  
  assign q = 1'b0 ;
  assign q_bar = 1'b0 ;
  
  initial begin
  clk = 1'b1 ;
  end 
  
  JK_FF DUT(j,k,clk,q,q_bar) ;
  
   initial
   begin
   j = 1'b0 ;
   k = 1'b0 ;
  
   #5
  
    j = 1'b0 ;
    k = 1'b1 ;
  
    #5
  
    j = 1'b1 ;
    k = 1'b0 ;
  
    #5
  
    j = 1'b1 ;
    k = 1'b1 ;
  
    end
    endmodule 
  </code></pre>