title: System Verilog parameters in generate block
body: <p>I'd like to set a parameter based on a parameter which is set when the module is instantiated. I have the following.</p>
  
  <pre><code>module foo #(WORDS = 8);
  
  parameter P00 = 33;
  logic [7:0] tmp;
  
  generate
    case (WORDS)
      4: begin : A
           assign tmp = 8'haa;
           parameter P00 = 4;
         end
      8: begin : B
           assign tmp = 8'hbb;
           parameter P00 = 8;
         end
     16: begin : C
           assign tmp = 8'hcc;
           parameter P00 = 16;
         end
     default: begin : D
                assign tmp = 8'hdd;
                parameter P00 = 8;
              end
    endcase
  endgenerate
  
  initial begin
    $display ("WORDS = %d", WORDS);
    $display ("tmp   = %h", tmp);
    $display ("P00   = %d", P00);
  end
  
  endmodule
  </code></pre>
  
  <p>I expected to get an error for redefining P00 but it compiled and ran and displayed the following instead.</p>
  
  <pre><code>WORDS =       8
  tmp    = bb
  P00    = 33
  </code></pre>
  
  <p>If I comment the "parameter P00 = 33" assignment, I get a "Identifier P00 has not been declared yet." error.</p>
  
  <p>It seems that the generate block is being ignored. What is wrong here?</p>