title: VDHL loop with variable outside of the process (how to be)
body: <p>How can I avoid variable in this loop (outside the process)?</p>
  
  <pre><code>variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others =&gt; '0');
  
          for i in 0 to ADRESS_WIDTH-2 loop
              var1 := var1 + '1';
              with r_addr select
               fifo_data_out &lt;= array_reg(i) when var1,
          end loop;
          array_reg(ADRESS_WIDTH-1) when others;
  </code></pre>
  
  <p>This version (in process) isn't correct too - syntax errors</p>
  
  <pre><code>process (r_addr, r_addr1, fifo_data_out, array_reg, r_data1)
  variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others =&gt; '0');
  
  begin
  
  case r_addr is
      when "0000000000" =&gt; fifo_data_out &lt;= array_reg(0);
          for i in 1 to ADRESS_WIDTH-2 loop
              when var1 =&gt; fifo_data_out &lt;= array_reg(i);
              var1 := var1 + '1';
          end loop;
       when others =&gt; fifo_data_out &lt;= array_reg(ADRESS_WIDTH-1);
  end case;
  </code></pre>