title: system verilog parameterized interfaces, how
body: <p>Hi I am struggling to get my head wrap around interfaces... at first they seem simple enough but once I started to work with parameterized interfaces I just can't the pieces to fall into place.</p>
  
  <p>say I have interface</p>
  
  <pre><code>interface my_if #( 
      parameter H_WIDTH = 64,
      parameter L_WIDTH = 8
  );
  logic [H_WIDTH -1:0]  a;
  logic [L_WIDTH -1:0]  b;
  logic                 ready;
  modport in ( input a, input b, output valid);
  modport out( output a, output b, input ready);
  endinterface;
  </code></pre>
  
  <p>and I want to use that as a port in my module</p>
  
  <pre><code>module my_module (
  logic input clk,
  logic input rst,
  my_if.in    my_if
  );
  </code></pre>
  
  <p>firstly I don't see how to set the parameters of my iterface
  I have tried the following instead of the above:</p>
  
  <pre><code>my_if(#.H_WIDTH((64), .L_WIDTH(64)) my_if()
  </code></pre>
  
  <p>and</p>
  
  <pre><code>my_if(#.H_WIDTH((64), .L_WIDTH(64)).in my_if()
  </code></pre>
  
  <p>which does not compile...</p>
  
  <p>but how do I then set the parameters of my interface?
  PLZ help I have googled a ton of examples but they are all very basic.</p>
  
  <p>BTW the solutions has to  synthesize as this is not for verification</p>