title: How do I access an internal reg inside a module?
body: <p>I have this architechture/topology in Verilog:</p>
  
  <p><img src="https://i.imgur.com/irIsD40.png" alt="picture"></p>
  
  <p>How can I access the internal reg <code>IntReg</code>, that isn't a input/output in <code>IntModule</code>, in SystemVerilog?</p>
  
  <pre><code>always @(posedge clk) begin
      $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg);
  end
  </code></pre>
  
  <p>Can I use bind? How?</p>