title: makefiles - compile all c files at once
body: <p>I want to experiment with GCC whole program optimizations. To do so I have to pass all C-files at once to the compiler frontend. However, I use makefiles to automate my build process, and I'm not an expert when it comes to makefile magic.</p>
  
  <p>How should I modify the makefile if I want to compile (maybe even link) using just one call to GCC?</p>
  
  <p>For reference - my makefile looks like this:</p>
  
  <pre><code>LIBS  = -lkernel32 -luser32 -lgdi32 -lopengl32
  CFLAGS = -Wall
  
  OBJ = 64bitmath.o    \
        monotone.o     \
        node_sort.o    \
        planesweep.o   \
        triangulate.o  \
        prim_combine.o \
        welding.o      \
        test.o         \
        main.o
  
  %.o : %.c
      gcc -c $(CFLAGS) $&lt; -o $@
  
  test: $(OBJ)
      gcc -o $@ $^ $(CFLAGS) $(LIBS)
  </code></pre>