title: How to simulate memory on VHDL test bench?
body: <p>I'm writing a universal test bench for my design that communicates with a RAM via a pretty standard bus. I consulted some examples and wrote it like this:</p>
  
  <pre><code>signal memory: mem_array;
  signal mem_address: std_logic_vector(31 downto 0);
  signal mem_data: std_logic_vector(31 downto 0);
  signal mem_read: std_logic;
  signal mem_write: std_logic;
  
  cpu_mem_data &lt;= transport memory(to_integer(unsigned(mem_address))) after DELAY when mem_read = '1' else (others =&gt; 'Z');
  
  always : PROCESS
      file in_file: text open read_mode is "in.txt";
      variable line_str: line;
      variable address: std_logic_vector(31 downto 0);
      variable data: std_logic_vector(31 downto 0);
  BEGIN
      reset &lt;= '1';
  
      readline(in_file, line_str);
      hread(line_str, address);
      starting_pc &lt;= address;
      while not endfile(in_file) loop
          readline(in_file, line_str);
          hread(line_str, address);
          read(line_str, data);
          memory(to_integer(unsigned(address))) &lt;= data;
          report "Initialized " &amp; integer'image(to_integer(unsigned(address))) &amp; " to " &amp; integer'image(to_integer(unsigned(data)));
      end loop;
  
      wait for 30 ns;
  
      reset &lt;= '0';
  WAIT;                                                        
  END PROCESS always; 
  
  process (mem_write)
  begin
      if (rising_edge(mem_write)) then
          memory(to_integer(unsigned(mem_address))) &lt;= transport mem_data after DELAY;
          report "Will write " &amp; integer'image(to_integer(unsigned(mem_data))) &amp; " to " &amp; integer'image(to_integer(unsigned(mem_address)));
      end if;
  end process;
  </code></pre>
  
  <p>I'm encountering two problems.</p>
  
  <p>When compiled and simulated in ModelSim Altera SE, memory is showing all X for all locations. Reports are showing that correct values are read from the in.txt file, but nothing is getting written into the memory. I also try initializing all locations or just a single location to all '0' and it doesn't work either. On the contrary, the signal starting_pc is being set to correct value.</p>
  
  <p>The other problem is that delayed assignments do not seem to work. My design attempts to read from the memory and mem_read and mem_address are correctly set, but after DELAY time mem_data remains at high impedance.</p>
  
  <p>What am I doing wrong?</p>