title: A 4-bit counter D flip flop with + 1 logic
body: <p><img src="https://i.stack.imgur.com/ahv4B.png" alt="enter image description here" /></p>
  <p>I am trying to implement this D flip-flop counter with + 1 logic through Verilog. Bu,t I'm getting a lot of error codes about multiple constant drivers for net. Can anyone give me a hand?  Here is the code so far:</p>
  <pre><code>module LAB (clk, clear, Enable, Q);
  
  input clk, clear, Enable;   
      
  output[3:0] Q; 
                  
  reg[3:0] Q;
  
  wire D;
  
      
  assign D = Q;
      
  always @ (posedge clk)
  
  begin
  
  if (!clear)
  
  Q &lt;= 1'b0;
  
  else
  
  Q &lt;= D;
  
  end
      
  always @ (Enable)
  
  begin
  
  if (Enable == 1)
  
  Q &lt;= D + 1;
  
  else
   
  Q &lt;= D;
  
  end 
      
  endmodule
  </code></pre>
  <p>Here are the error codes I am getting:</p>
  <pre><code>Error (10028): Can't resolve multiple constant drivers for net &quot;Q[3]&quot; at 
  
  
  LAB.v(17)
  Error (10029): Constant driver at LAB.v(9)
  
  
  Error (10028): Can't resolve multiple constant drivers for net &quot;Q[2]&quot; at LAB.v(17)
  
  
  Error (10028): Can't resolve multiple constant drivers for net &quot;Q[1]&quot; at LAB.v(22)
  
  
  Error (10028): Can't resolve multiple constant drivers for net &quot;Q[0]&quot; at LAB.v(22)
  
  
  Error (12153): Can't elaborate top-level user hierarchy
  
  
  Error: Quartus II 64-Bit Analysis &amp; Synthesis was unsuccessful. 6 errors, 4 warnings
  
  Error: Peak virtual memory: 4613 megabytes
  
  
  Error: Processing ended: Sun Apr 19 18:39:09 2020
  
  
  Error: Elapsed time: 00:00:01
  
  
  Error: Total CPU time (on all processors): 00:00:00
  
  
  Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 4 
  warnings
  </code></pre>