title: How to assign bits from a changing STD_LOGIC output to a STD_LOGIC_VECTOR input
body: <p>I'm new to this web site and I had a question I was hoping to get help with. I am writing VHDL code for a <strong>LFSR</strong> which consists of a transmitter and receiver.
  The transmitter is supposed to generate a random binary number (preamble,which it does) and this binary number then has to be concatenated, but I first need to put it in a STD_LOGIC_VECTOR and that's what im having trouble with. </p>
  
  <p>Here is my code for testbench in which this assignment must take place,thank for any help in advance:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all; 
  
  entity testbench is --definig the entity
  end testbench;
  
  architecture tb1 of testbench is
  
      component transmitter is port(
          clk :in std_logic;
          reset:in std_logic;
          enable:in std_logic;
          output :out std_logic);--output is the random generated binary which i need to pass to a vector
      end component;
  
      --type bit_vector is array (natural range &lt;&gt;) of bit; --this is so that we can define the whole thing otherwise bit can
      --only be 1 or 0 this allows to define them as vectors
  
      constant SOF: std_logic_vector(0 to 15) := "0101010100001010";  
      constant trailer: std_logic_vector(0 to 7) := "10111110";
      constant payload: std_logic_vector(0 to 7) := "01110010";
      constant L: std_logic_vector(0 to 7) := "00101110";
      signal preamble: std_logic_vector(0 to 95);
  
      signal clk , reset, enable : std_logic;--output signal
      signal data_packet: std_logic_vector(0 to 135);
      signal output: std_logic;
  
  begin
  
  
      --problem is here
      --my attempt
      get_preamble: process
          variable i: std_logic;--this will be used to walk through the preamble vector and put the out put values in 
          --variable j: std_logic;
      begin
  
          n1: for i in 0 to 95 loop
              if output = '1' then
                  preamble(i) &lt;= '1';
              end if;
          end loop;
  
          if output = '0' then
              for i in 0 to 95 loop
                  preamble(i) &lt;= '0';
              end loop;
          end if;
  
          wait;
      end process;--end of get_preamble
  
      concatenation :process 
      begin
          data_packet &lt;= preamble &amp; SOF &amp; L &amp; payload &amp; trailer;
          wait;
      end process;
  END tb1;
  </code></pre>