title: Way to initialize synthesizable 2D array with constant values in Verilog
body: <p>in VHDL, I can easily do this:</p>
  
  <pre><code>constant    cmdbytes       : bytearray(0 to Total) := (x"05", x"00", x...};
  </code></pre>
  
  <p>I want synthesizable constants so that when the FPGA starts, this array has the data I supplied.  These registers are wired to VCC or ground to represent 1 or 0.  I can then use them to generate a waveform.  Also I would like to have 2D byte array which is 3D in verilog world.  </p>