title: searchpath for prereqisites, like vpath, but only for some pattern rules
body: <p>I'm trying to build several executables in one <code>make</code> instance, as suggested by 
  <a href="http://aegis.sourceforge.net/auug97.pdf" rel="nofollow">Recursive Make Considered Harmful</a>.
  The arguments of that paper apply to my project because some of my source files are generated, and go into multiple executables.</p>
  
  <p>The object files for each of these executables go into separate directories, because they are compiled with different preprocessor flags.</p>
  
  <p>How can I specify separate <code>vpath</code> settings for each of these executables, so that source files with duplicate filenames in separate directories go into the executables where I want them to go?</p>
  
  <p>Setting <code>vpath</code> before the rules to build the object files for one executable, and erasing it afterwards (by not giving any directories) doesn't have the desired effect. Apparently, the last setting is used for all the rules.</p>
  
  <p>Solutions I see currently:</p>
  
  <ul>
  <li>Rename source filenames to use unique names so that I can use a global <code>vpath</code> setting</li>
  <li>Instead of <code>vpath</code>, use separate rules for each source directory, with the source directory in the prerequisite pattern (*)</li>
  <li>Recursive make, with separate <code>vpath</code> settings in each <code>make</code> instance, and somehow deal with the resulting trouble.</li>
  <li>Use something different than <code>make</code>.</li>
  </ul>
  
  <p>Is there a better solution, or which one of the above would you prefer?</p>
  
  <p>(*) The solution with separate rules looks like this:</p>
  
  <pre><code>build/$(PROGRAM)/%.o: %.c
      $(COMPILE_RECIPE)
  
  build/$(PROGRAM)/%.o: $($(PROGRAM)_SOURCE_DIR)/%.c
      $(COMPILE_RECIPE)
  </code></pre>
  
  <p>Ok for my current project, but would become ugly fast, if there where more than one directory different in the source paths of the executables</p>
  
  <p><strong>Edit:</strong> Test for suggestion of @Etan, which shows that <code>$^</code> is empty, when the prerequisites appear only in pattern rules (<code>y/y.c</code>) - this only works if each dependency is given directly, as for <code>x/x.c</code>.</p>
  
  <pre><code>.PHONY: all
  
  all: build/x.o build/y.o
  
  build/x.o: x/x.c
  # the following rule is ignored:
  build/%.o: y/%.c
  # because there is a matching pattern rule with a recipe:
  build/%.o:
      @echo \"$@\" from \"$^\"
      @touch $@
  </code></pre>
  
  <p>The files <code>x/x.c</code>,  <code>y/y.c</code> and the directory <code>build</code> exist.</p>
  
  <p>output:</p>
  
  <pre><code>"build/x.o" from "x/x.c"
  "build/y.o" from ""
  </code></pre>
  
  <p>Tested with <code>GNU Make 3.82.90</code></p>