title: Can SystemVerilog represent a flip-flop with asynchronous set and reset without adding unsynthesizable code?
body: <p>I'm coming from a Verilog-95 background, and I'm trying to figure out what Verilog-95 hoops I don't have to jump through anymore.</p>
  
  <p>The obvious way to write a flip flop with async set and reset in Verilog-95 is:</p>
  
  <pre><code>always @(posedge clk or negedge resetb or negedge setb) begin
    if (!resetb)      q &lt;= 0;
    else if (!setb)   q &lt;= 1;
    else              q &lt;= d;
  end
  </code></pre>
  
  <p>This works in synthesis. But, this doesn't work in simulation if we ever assert both resetb and setb, and then de-assert resetb before de-asserting setb, since there's no posedge trigger for either of those signals. We need to add the following (which varies depending on your synthesis tool), to get simulation to match synthesis:</p>
  
  <pre><code>// synopsys translate_off
  always @(resetb or setb)
    if (resetb &amp;&amp; !setb) force q = 1;
    else               release q;
  // synopsys translate_on
  </code></pre>
  
  <p>Is there a SystemVerilog construct that will let you do this without this extra junk? Better yet, is there a straightforward way to do it in Verilog-95?</p>