title: problem in synchronization of timer0 and CPU clock cycles
body: <p>I am a beginner in AVR. I need to sample input at odd intervals of 8 ms. i have used CTC mode for generating 8 ms timer. i used CTC with compare interrupt so that i can get a flag (timer_count) set at every comparison. i.e. after every 8 ms. The 8 ms timer starts on External Interrupt at PIN D0.
  when i am checking the input conditions in main loop, due to large difference in frequency of main controller (18.432 MHz) and 8 ms timer, i am unable to sample inputs correctly. Can anyone tell me any other method to do this. The code is pasted here for reference.</p>
  <p>#include &lt;mega128.h&gt;</p>
  <p>#include &lt;stdio.h&gt;</p>
  <p>#include &lt;stdlib.h&gt;</p>
  <p>#define CHECK_BIT(ADDRESS,BIT) (ADDRESS &amp; (1&lt;&lt;BIT))</p>
  <p>#define SET_BIT(ADDRESS,BIT) (ADDRESS |= (1&lt;&lt;BIT))</p>
  <p>#define CLEAR_BIT(ADDRESS,BIT) (ADDRESS &amp;= (~(1&lt;&lt;BIT)))</p>
  <p>#define TGL_BIT(ADDRESS, BIT) (ADDRESS ^= (1&lt;&lt;BIT))</p>
  <p>volatile unsigned int flag;</p>
  <p>volatile unsigned int timer_count=0;</p>
  <p>volatile unsigned int frequency_979_sense;</p>
  <p>volatile unsigned int frequency_885_sense;</p>
  <p>volatile unsigned int frequency_933_sense;</p>
  <p>volatile unsigned int flag_979_received;</p>
  <p>volatile unsigned int flag_885_received;</p>
  <p>volatile unsigned int data;</p>
  <p>volatile unsigned int i;</p>
  <p>volatile unsigned char SOP_valid;</p>
  <p>volatile unsigned int previous_state=0;</p>
  <p>volatile unsigned int current_state=0;</p>
  <p>// Timer 0 output compare interrupt service routine</p>
  <p>interrupt [TIM0_COMP] void timer0_comp_isr(void)
  {</p>
  <p>timer_count++;</p>
  <p>}</p>
  <p>void init_timer0()
  {</p>
  <p>// Timer/Counter 0 initialization</p>
  <p>// Clock source: System Clock</p>
  <p>// Clock value: 18.000 kHz</p>
  <p>// Mode: CTC top=OCR0</p>
  <p>// OC0 output: toggle output on compare match</p>
  <p>ASSR=0x00;</p>
  <p>TCCR0=0x1F;</p>
  <p>TCNT0=0x00;</p>
  <p>OCR0=0x90;</p>
  <p>// Timer(s)/Counter(s) Interrupt(s) initialization</p>
  <p>TIMSK=0x02;</p>
  <p>}</p>
  <p>// External Interrupt 0 service routine</p>
  <p>interrupt [EXT_INT0] void ext_int0_isr(void)
  {</p>
  <p>if ((CHECK_BIT(PIND,4)==0) &amp; (CHECK_BIT(PIND,5)==0))</p>
  <pre><code>  {
  
    init_timer0();
  
    flag=1;
  
    CLEAR_BIT(EIMSK,0);
  
    CLEAR_BIT(EIFR,0);
  
  }
  </code></pre>
  <p>}</p>
  <p>void main(void)
  {
  // Port D initialization</p>
  <p>PORTD=0xFF;</p>
  <p>DDRD=0x00;</p>
  <p>// External Interrupt(s) initialization</p>
  <p>// INT0: On</p>
  <p>// INT0 Mode: Rising Edge</p>
  <p>EICRA=0x03;</p>
  <p>EICRB=0x00;</p>
  <p>EIMSK=0x01;</p>
  <p>EIFR=0x01;</p>
  <p>// Global enable interrupts</p>
  <p>#asm(&quot;sei&quot;)</p>
  <p>while (1)
  {<br />
  while (timer_count &gt; 0 &amp; timer_count&lt;32)</p>
  <pre><code>            {                                   
                  if (timer_count%2==1) 
                  {     
                      frequency_979_sense= CHECK_BIT(PIND,0);
                      frequency_885_sense= CHECK_BIT(PIND,4);
                      frequency_933_sense= CHECK_BIT(PIND,5); 
                      
                      if ((frequency_979_sense != 0) &amp;&amp; (frequency_885_sense == 0) &amp;&amp; (frequency_933_sense == 0) &amp;&amp; (flag_885_received==0 || flag_885_received== 8)) 
                      {                                    
                                flag_979_received++;
                                SET_BIT(data,i);         
                      }
  
                      if ((frequency_979_sense == 0) &amp;&amp; (frequency_885_sense != 0) &amp;&amp; (frequency_933_sense == 0) &amp;&amp; (flag_979_received==6)) 
                      { 
                                flag_885_received++;
                                SET_BIT(data,i); 
                      }   
                     else
                      {
                               flag_979_received=0;
                               flag_885_received=0;
                               frequency_979_sense=0;
                               frequency_885_sense=0;
                               frequency_933_sense=0; 
                               data=0;
                               TCCR0=0x00;
                               TIMSK=0x00;
                               timer_count=0;
                               i=0;
                               SET_BIT(EIMSK,0);
                               SET_BIT(EIFR,0);
                      }      
                  }   
                                 
                 i++;
              }  
              
              if (data==65535) 
                   {
                     SOP_valid=1;
                   }  
  </code></pre>
  <p>}
  }</p>