title: Makefile target with makefile as dependency
body: <p>I am currently working on a project where I have a couple applications in a parent folder that need to be rebuilt whenever the libraries contained in child folders are updated. The apps in the parent folder are built with a makefile, and the libraries are built with a separate makefile in the respective folder. This looks something like : </p>
  
  <ul>
  <li>ParentDir
  <ul>
  <li>app1</li>
  <li>app2</li>
  <li>Makefile
  <ul>
  <li>libdir1
  <ul>
  <li>Makefile</li>
  </ul></li>
  <li>libdir2
  <ul>
  <li>Makefile</li>
  </ul></li>
  </ul></li>
  </ul></li>
  </ul>
  
  <p>I'm currently doing something like this for my makefile in the parent dir</p>
  
  <pre><code>all : app1 app2
  
  libs = libdir1/lib1.a libdir2/lib2.a
  .PHONY : $(libs)
  
  
  $(all) : $(libs)
      #do stuff to make the apps
  
  libdir1/lib1.a : 
      $(MAKE) -c libdir1
  
  
  libdir2/lib2.a : 
      $(MAKE) -c libdir2
  </code></pre>
  
  <p>My problem is, I don't want the apps in the parent dir's makefile to rebuild unless one of the makefiles it "depends" on are updated. I know that the reason this is happening currently is that I have my libs declared as PHONY ( so they always rebuild ), but that was the only way I could figure out to actually call the children makefiles. </p>
  
  <p>So, what I want is for each app to build only when either of the libdirs makefile's would actually do something, and to call each libdir's makefile that would "do something" before building the app. </p>
  
  <p>Thanks for your help in advance.</p>