title: How to expand a single bit to multi-bits depending on parameter in verilog?
body: <p>For example, I have an input <code>wire fx</code>, and <code>parameter DATAWIDTH</code>.</p>
  
  <p>Can I write</p>
  
  <pre><code>wire [DATAWIDTH - 1 : 0] exfx;
  assign exfx = {(DATAWIDTH - 1){1'b0}, fx};
  </code></pre>
  
  <p>to zero expand the signal fx to DATAWIDTH?</p>
  
  <p>What if I want (DATAWIDTH - 1) bits 1? or more complex combination?</p>