title: How does cache coherence work in multi-core and multi-processor architecture?
body: <p>Let me explain my understanding and ask you to either confirm its correctness or correct me:</p>
  
  <ol>
  <li>There's a MESI protocol which allows for efficient cache coherence (<a href="https://en.wikipedia.org/wiki/MESI_protocol" rel="nofollow">https://en.wikipedia.org/wiki/MESI_protocol</a>). It's the state of the art mechanism.</li>
  <li>For several cores of a single processor, MESI operates via L3 cache which is shared among cores of a processor.</li>
  <li>For several processors (with no shared L3), MESI operates via Main Memory.</li>
  <li>When using global variables, which are read and written by several threads, <em>volatile</em> type specifier is used to prevent unwanted optimizations as well as to prevent caching in <em>registers</em> (<strong>not</strong> in L1-3 caches). Thus, if value is not in a register but in cache or main memory, MESI would do its work to make threads see correct values of globals.</li>
  </ol>