title: object <name> is not declared
body: <p>Here's my code, and as far as I can tell, <code>LEDs</code> is defined:</p>
  
  <pre><code>module sevenseg (LEDs,in);
  output reg [6:0] LEDs;
  input [3:0] in;
  
  always@(in) begin 
      case(in)
          0 : LEDs = 7'b1000000;
          1 : LEDs = 7'b1111001;
          2 : LEDs = 7'b0100100;
          3 : LEDs = 7'b0110000;
          4 : LEDs = 7'b0011001;
          5 : LEDs = 7'b0001010;
          6 : LEDs = 7'b0000010;
          7 : LEDs = 7'b1111000;
          8 : LEDs = 7'b0000000;
          9 : LEDs = 7'b00010000;
          default : LEDs = 7'b1111111;
      endcase
  end 
  endmodule 
  </code></pre>
  
  <p>Here are the compilation errors:</p>
  
  <blockquote>
    <p>Error (10161): Verilog HDL error at sevenseg2.v(39): object "LEDs" is
    not declared</p>
    
    <p>Error: Quartus II 64-Bit Analysis &amp; Synthesis was unsuccessful. 1
    error, 1 warning</p>
    
    <p>Error (293001): Quartus II Full Compilation was unsuccessful. 3
    errors, 1 warning</p>
  </blockquote>