title: can someone explain fork and loop in system verilog?
body: <p>I was going through <a href="https://standards.ieee.org/getieee/1800/download/1800-2012.pdf" rel="nofollow">SV LRM section 9.3.2</a> and got this doubt, i am pasting the example below for reference</p>
  
  <pre><code>for(int j=1; j &lt;=3; ++j)
      fork
          automatic int k = j;
          begin
              .... # use k here
          end
      join_none
  </code></pre>
  
  <ul>
  <li><p>Can someone explain me what is actually happening?</p></li>
  <li><p>What happens if i move the <code>automatic</code> variable outside the fork?</p>
  
  <pre><code>for(int j=1; j &lt;=3; ++j) begin
      automatic int k = j;
      fork
          begin
              .... # use k here
          end
      join_none
  end
  </code></pre></li>
  <li><p>What happens if i move the loop inside the fork?</p>
  
  <pre><code>fork
      for(int j=1; j &lt;=3; ++j) begin
          automatic int k = j;
          begin
              .... # use k here
          end
      end
   join_none
  </code></pre></li>
  </ul>
  
  <p>Thanks in advance.</p>