title: makefile target specific variables as prerequisites
body: <p>Related: <a href="https://stackoverflow.com/questions/1340060/target-specific-variables-as-prerequisites-in-a-makefile">Target-specific Variables as Prerequisites in a Makefile</a></p>
  
  <p>I'm trying to craft a Makefile which uses a target-specific-variable to specify the output directory for the object files and the final executable.  The idea is to maintain two separate binary versions, a 'release' version and a 'debug' version with extra debugging information.</p>
  
  <p>My problem is that 'make' does a clean build every time, even if I haven't changed a thing.  I'm pretty sure it's because 'make' is evaluating the prerequisites of the target 'corewars' before the variable declaration in the prerequisites for the 'debug' or 'release' target.</p>
  
  <p>The Makefile is presented below.</p>
  
  <pre><code>CXX=g++
  LD=g++
  LDFLAGS=
  CXXFLAGS=-Iinclude -Wall -Wextra
  OBJECTS=main.o Machine.o Core.o ProcessQueue.o Instruction.o
  OUTPUT_DIR:=Test/
  
  .PHONY: default
  .PHONY: all
  .PHONY: release
  default: release
  all: release
  release: OUTPUT_DIR:=Release/
  release: corewars
  
  .PHONY: debug
  debug: CXXFLAGS+=-DDEBUG -g
  debug: OUTPUT_DIR:=Debug/
  debug: corewars
  
  corewars: $(OUTPUT_DIR) $(addprefix $(OUTPUT_DIR),$(OBJECTS))
      $(LD) -o $(addprefix $(OUTPUT_DIR),corewars) $(addprefix $(OUTPUT_DIR),$(OBJECTS))
  
  Release:
      mkdir -p $@
  Debug:
      mkdir -p $@
  
  %.o: %.cpp include/%.h
      $(CXX) -c $(CXXFLAGS) $&lt; -o $(OUTPUT_DIR)$@
  
  
  .PHONY: clean
  clean:
      $(RM) -r Release
      $(RM) -r Debug
  </code></pre>