title: Conditional in makefile that redefines variable?
body: <p>I have a variable in my makefile I would like to either <code>unset</code> or redefine, so that targets <code>a</code>, <code>b</code> and <code>c</code> use the correct value of <code>MY_VARIABLE</code> (or none at all) within their respective makefiles.</p>
  
  <p>If I run <code>make foo</code> with the following:</p>
  
  <pre><code>export MY_VARIABLE := 'false'
  foo: prep_foo dist
  prep_foo:
      $(shell export MY_VARIABLE='true')
      echo ${MY_VARIABLE}
  dist: a b c
  a: 
      make -C a/src
  b: 
      make -C b/src
  c: 
      make -C c/src
  </code></pre>
  
  <p>I get this output:</p>
  
  <pre><code>export MY_VARIABLE='true'
  echo 'false'
  false
  ...
  </code></pre>
  
  <p>If, instead, I run <code>make foo</code> with the following makefile:</p>
  
  <pre><code>export MY_VARIABLE := 'false'
  foo: prep_foo dist
  prep_foo:
      $(shell unset MY_VARIABLE)
      echo ${MY_VARIABLE}
  dist: a b c
  a: 
      make -C a/src
  b: 
      make -C b/src
  c: 
      make -C c/src
  </code></pre>
  
  <p>I get the following output:</p>
  
  <pre><code>make: unset: No such file or directory
  echo 'false'
  false
  ...
  </code></pre>
  
  <p>How can I unset or redefine <code>MY_VARIABLE</code> when specifying a target (like <code>foo</code>, in this case)?</p>
  
  <p><strong>EDIT</strong></p>
  
  <p>Here is the situation I would like to avoid:</p>
  
  <pre><code>dist: a b c 
  foo: a_foo b_foo c_foo
  a:
      make -C a/src
  ...
  a_foo
      make -C a_foo/src
  </code></pre>
  
  <p>I just want the <code>a</code> target to use a different value for my particular variable, so that compilation is handled differently in that target's makefile. </p>
  
  <p>Also, it doesn't look like I can <code>export</code> or <code>unset</code> variables within a target. For example:</p>
  
  <pre><code>dist: a b c 
  foo: a_foo b_foo c_foo
  a:
      make -C a/src
  ...
  a_foo:
      export MY_VARIABLE='true'; make -C a/src
  </code></pre>
  
  <p>If I try to do so, I get something similar to the following error on the <code>export MY_VARIABLE='true'</code> line (and similarly if I try to use <code>unset</code>):</p>
  
  <pre><code>Makefile:16: *** unterminated variable reference.  Stop.
  </code></pre>
  
  <p>Does this help clarify what I'm trying to do?</p>
  
  <p><strong>EDIT 2</strong></p>
  
  <p>I tried a target which <code>touch</code>-es a file and tries to run the child target's <code>makefile</code> (which checks for the file's existence):</p>
  
  <pre><code>foo: prep_foo
  prep_foo:
      touch a/src/.foo
      make -C a/src
  </code></pre>
  
  <p>When I try to run this via <code>make foo</code>, I get the following error:</p>
  
  <pre><code>Makefile:14: *** commands commence before first target.  Stop.
  </code></pre>
  
  <p>If I remove the <code>make</code> statement from <code>prep_foo</code>, then I can <code>touch</code> the file without getting the error message, but I cannot trigger making the <code>a</code> target, so this doesn't seem to help.</p>
  
  <p>The following yields the same <code>commands commence before first target</code> error message:</p>
  
  <pre><code>foo: prep_foo a
  prep_foo:
      touch a/src/.foo
  </code></pre>
  
  <p>Is there an example of using <code>touch</code> to communicate state to child targets?</p>