title: How to write u-boot environment variables in mmcblk0boot0 instead of mmcblk0p1
body: <p>I'm working on board bring-up of a custom iMX6 based board. I'm using the Android package from iMX6 Sabre SD board, and have got most of the things working with booting from eMMC which on on-board, but I'm facing issue with 'saveenv' of u-boot.</p>
  
  <p>Firstly, everytime on boot there is a print :</p>
  
  <pre><code>*** Warning - bad CRC or MMC, using default environment
  </code></pre>
  
  <p>I search online and found that we have to do 'saveenv' once to let this error go away. So I did saveenv but after that the board doesn't boot completely and got stuck on <code>'Uncompressing Linux ...'</code> !</p>
  
  <p>I then boot-up the board using SD card and got the hexdump of /dev/block/mmcblk0boot0 and /dev/block/mmcblk0p1 (both are eMMC partitions, SD card is dev/block/mmcblk1)</p>
  
  <p>To my surprise, from hexdump I found that 'saveenv' writes the environment variable data to /dev/block/mmcblk0p1 and not /dev/block/mmcblk0boot0 which was the reason the board didn't boot-up as boot.img is in dev/block/mmcblk0p1 partition was corrupted by u-boot doing saveenv and over-writing the boot.img data.</p>
  
  <p>So, my question is how can I change the u-boot code to modify it to read and save environment variables on <code>/dev/block/mmcblk0boot0</code> instead of <code>/dev/block/mmcblk0p1</code></p>
  
  <p>I'm trying to dig into the code and so far I have found that <code>common/env_mmc.c</code> is the file which has all functions to read/write environment variables, and <code>include/configs/mx6solo_sabresd.h</code> includes the configuration of my board.</p>
  
  <p><strong>P.S. : The u-boot itself is located in /dev/block/mmcblk0boot0</strong></p>
  
  <p><strong>Edit : Below the information regarding partitions :</strong></p>
  
  <pre><code>root@imx6:/ # cat /proc/partitions                                           
  major minor  #blocks  name
  
    31        0         64 mtdblock0
   179        0    3833856 mmcblk0
   179        1      15640 mmcblk0p1
   179        2       7840 mmcblk0p2
   179        3          1 mmcblk0p3
   179        5     500024 mmcblk0p5
   179        6     500024 mmcblk0p6
   179        7      78136 mmcblk0p7
   259        0     500024 mmcblk0p8
   259        1      19544 mmcblk0p9
   259        2    2212568 mmcblk0p10
   179       16       1024 mmcblk0boot1
   179        8       1024 mmcblk0boot0
   179       24    3887104 mmcblk1
   179       25       7168 mmcblk1p1
   179       26     484352 mmcblk1p2
   179       27          1 mmcblk1p3
   179       29     289792 mmcblk1p5
   179       30     550912 mmcblk1p6
   179       31     570368 mmcblk1p7
   259        3     799744 mmcblk1p8
  root@imx6:/ # 
  root@imx6:/ # cat /proc/mtd                                                  
  dev:    size   erasesize  name
  mtd0: 00010000 00008000 "bootloader"
  mtd1: 00000000 00000000 "kernel"
  root@imx6:/ # 
  root@imx6:/ # fdisk -l /dev/block/mmcblk0                                    
  
  Disk /dev/block/mmcblk0: 3925 MB, 3925868544 bytes
  4 heads, 16 sectors/track, 119808 cylinders
  Units = cylinders of 64 * 512 = 32768 bytes
  
                Device Boot      Start         End      Blocks  Id System
  /dev/block/mmcblk0p1               1         489       15640  83 Linux
  /dev/block/mmcblk0p2             490         734        7840  83 Linux
  /dev/block/mmcblk0p3             735      119808     3810368   5 Extended
  /dev/block/mmcblk0p5             735       16360      500024  83 Linux
  /dev/block/mmcblk0p6           16361       31986      500024  83 Linux
  /dev/block/mmcblk0p7           31987       34428       78136  83 Linux
  /dev/block/mmcblk0p8           34429       50054      500024  83 Linux
  /dev/block/mmcblk0p9           50055       50665       19544  83 Linux
  /dev/block/mmcblk0p10          50666      119808     2212568  83 Linux
  root@imx6:/ # 
  root@imx6:/ # fdisk -l /dev/block/mmcblk0boot0                               
  
  Disk /dev/block/mmcblk0boot0: 1 MB, 1048576 bytes
  4 heads, 16 sectors/track, 32 cylinders
  Units = cylinders of 64 * 512 = 32768 bytes
  
  Disk /dev/block/mmcblk0boot0 doesn't contain a valid partition table
  root@imx6:/ # fdisk -l /dev/block/mmcblk0boot1                               
  
  Disk /dev/block/mmcblk0boot1: 1 MB, 1048576 bytes
  4 heads, 16 sectors/track, 32 cylinders
  Units = cylinders of 64 * 512 = 32768 bytes
  
  Disk /dev/block/mmcblk0boot1 doesn't contain a valid partition table
  root@imx6:/ # 
  </code></pre>
  
  <p><strong>U-Boot config file :</strong></p>
  
  <pre><code>/*
   * Copyright (C) 2012 Freescale Semiconductor, Inc.
   *
   * Configuration settings for the MX6DL SabreSD Freescale board.
   * The board is configured with SOLO and 32-bit DDR bus-width.
   *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License as
   * published by the Free Software Foundation; either version 2 of
   * the License, or (at your option) any later version.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.
   *
   * You should have received a copy of the GNU General Public License
   * along with this program; if not, write to the Free Software
   * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
   * MA 02111-1307 USA
   */
  
  #ifndef __CONFIG_H
  #define __CONFIG_H
  
  #include &lt;asm/arch/mx6.h&gt;
  
   /* High Level Configuration Options */
  #define CONFIG_ARMV7    /* This is armv7 Cortex-A9 CPU core */
  #define CONFIG_MXC
  #define CONFIG_MX6DL
  #define CONFIG_MX6DL_DDR3
  #define CONFIG_MX6DL_SABRESD
  #define CONFIG_DDR_32BIT /* for DDR 32bit */
  #define CONFIG_FLASH_HEADER
  #define CONFIG_FLASH_HEADER_OFFSET 0x400
  #define CONFIG_MX6_CLK32       32768
  
  #define CONFIG_SKIP_RELOCATE_UBOOT
  
  #define CONFIG_ARCH_CPU_INIT
  #undef CONFIG_ARCH_MMU /* disable MMU first */
  #define CONFIG_L2_OFF  /* disable L2 cache first*/
  
  #define CONFIG_MX6_HCLK_FREQ    24000000
  
  #define CONFIG_DISPLAY_CPUINFO
  #define CONFIG_DISPLAY_BOARDINFO
  
  #define CONFIG_SYS_64BIT_VSPRINTF
  
  #define BOARD_LATE_INIT
  
  #define CONFIG_CMDLINE_TAG  /* enable passing of ATAGs */
  #define CONFIG_SERIAL_TAG
  #define CONFIG_REVISION_TAG
  #define CONFIG_SETUP_MEMORY_TAGS
  #define CONFIG_INITRD_TAG
  #define CONFIG_MXC_GPIO
  /*
   * Size of malloc() pool
   */
  #define CONFIG_SYS_MALLOC_LEN       (2 * 1024 * 1024)
  /* size in bytes reserved for initial data */
  #define CONFIG_SYS_GBL_DATA_SIZE    128
  
  /*
   * Hardware drivers
   */
  #define CONFIG_MXC_UART
  #define CONFIG_UART_BASE_ADDR   UART1_BASE_ADDR
  
  /* allow to overwrite serial and ethaddr */
  #define CONFIG_ENV_OVERWRITE
  #define CONFIG_CONS_INDEX       1
  #define CONFIG_BAUDRATE         115200
  #define CONFIG_SYS_BAUDRATE_TABLE   {9600, 19200, 38400, 57600, 115200}
  
  /***********************************************************
   * Command definition
   ***********************************************************/
  
  #include &lt;config_cmd_default.h&gt;
  
  #define CONFIG_CMD_PING
  #define CONFIG_CMD_DHCP
  #define CONFIG_CMD_MII
  #define CONFIG_CMD_NET
  #define CONFIG_NET_RETRY_COUNT  100
  #define CONFIG_NET_MULTI 1
  #define CONFIG_BOOTP_SUBNETMASK
  #define CONFIG_BOOTP_GATEWAY
  #define CONFIG_BOOTP_DNS
  
  #define CONFIG_CMD_SPI
  #define CONFIG_CMD_I2C
  #define CONFIG_CMD_IMXOTP
  
  /* Enable below configure when supporting nand */
  #define CONFIG_CMD_SF
  #define CONFIG_CMD_MMC
  #define CONFIG_CMD_ENV
  #define CONFIG_CMD_REGUL
  
  #define CONFIG_CMD_CLOCK
  #define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
  
  #undef CONFIG_CMD_IMLS
  
  #define CONFIG_CMD_IMX_DOWNLOAD_MODE
  
  #define CONFIG_BOOTDELAY 3
  
  #define CONFIG_PRIME    "FEC0"
  
  #define CONFIG_LOADADDR     0x10800000  /* loadaddr env var */
  #define CONFIG_RD_LOADADDR  (CONFIG_LOADADDR + 0x300000)
  
  #define CONFIG_EXTRA_ENV_SETTINGS                   \
      "netdev=eth0\0"                         \
      "ethprime=FEC0\0"                       \
      "uboot=u-boot.bin\0"                        \
      "kernel=uImage\0"                       \
      "nfsroot=/opt/eldk/arm\0"                   \
      "bootargs_base=setenv bootargs console=ttymxc0,115200 nosmp\0"  \
      "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "   \
          "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"   \
      "bootcmd_net=run bootargs_base bootargs_nfs; "          \
          "tftpboot ${loadaddr} ${kernel}; bootm\0"       \
      "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp "     \
          "root=/dev/mmcblk0p1 rootwait\0"            \
      "bootcmd_mmc=run bootargs_base bootargs_mmc; "          \
      "mmc dev 3; "                           \
      "mmc read ${loadaddr} 0x800 0x2000; bootm\0"            \
      "bootcmd=run bootcmd_net\0"                 \
  
  
  #define CONFIG_ARP_TIMEOUT      200UL
  
  /*
   * Miscellaneous configurable options
   */
  #define CONFIG_SYS_LONGHELP     /* undef to save memory */
  #define CONFIG_SYS_PROMPT       "MX6Solo SABRESD U-Boot &gt; "
  #define CONFIG_AUTO_COMPLETE
  #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
  /* Print Buffer Size */
  #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  #define CONFIG_SYS_MAXARGS      16  /* max number of command args */
  #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size */
  
  #define CONFIG_SYS_MEMTEST_START    0x10000000  /* memtest works on */
  #define CONFIG_SYS_MEMTEST_END      0x10010000
  
  #undef  CONFIG_SYS_CLKS_IN_HZ       /* everything, incl board info, in Hz */
  
  #define CONFIG_SYS_LOAD_ADDR        CONFIG_LOADADDR
  
  #define CONFIG_SYS_HZ           1000
  
  #define CONFIG_CMDLINE_EDITING
  
  #define CONFIG_FEC0_IOBASE      ENET_BASE_ADDR
  #define CONFIG_FEC0_PINMUX      -1
  #define CONFIG_FEC0_MIIBASE     -1
  #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
  #define CONFIG_MXC_FEC
  #define CONFIG_FEC0_PHY_ADDR        1
  #define CONFIG_ETH_PRIME
  #define CONFIG_RMII
  #define CONFIG_CMD_MII
  #define CONFIG_CMD_DHCP
  #define CONFIG_CMD_PING
  #define CONFIG_IPADDR           192.168.1.103
  #define CONFIG_SERVERIP         192.168.1.101
  #define CONFIG_NETMASK          255.255.255.0
  
  /*
   * OCOTP Configs
   */
  #ifdef CONFIG_CMD_IMXOTP
      #define CONFIG_IMX_OTP
      #define IMX_OTP_BASE        OCOTP_BASE_ADDR
      #define IMX_OTP_ADDR_MAX    0x7F
      #define IMX_OTP_DATA_ERROR_VAL  0xBADABADA
  #endif
  
  /*
   * I2C Configs
   */
  #ifdef CONFIG_CMD_I2C
      #define CONFIG_HARD_I2C
      #define CONFIG_I2C_MXC          1
      #define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
      #define CONFIG_SYS_I2C_SPEED            100000
      #define CONFIG_SYS_I2C_SLAVE            0x8
      #define CONFIG_MX6_INTER_LDO_BYPASS 0
  #endif
  
  /*
   * SPI Configs
   */
  #ifdef CONFIG_CMD_SF
      #define CONFIG_FSL_SF
      #define CONFIG_SPI_FLASH_IMX_M25PXX
      #define CONFIG_SPI_FLASH_CS     0
      #define CONFIG_IMX_ECSPI
      #define IMX_CSPI_VER_2_3        1
      #define MAX_SPI_BYTES           (64 * 4)
  #endif
  
  /* Regulator Configs */
  #ifdef CONFIG_CMD_REGUL
      #define CONFIG_ANATOP_REGULATOR
      #define CONFIG_CORE_REGULATOR_NAME  "vdd1p1"
      #define CONFIG_PERIPH_REGULATOR_NAME    "vdd1p1"
  #endif
  
  /*
   * MMC Configs
   */
  #ifdef CONFIG_CMD_MMC
      #define CONFIG_MMC
      #define CONFIG_GENERIC_MMC
      #define CONFIG_IMX_MMC
      #define CONFIG_SYS_FSL_USDHC_NUM        4
      #define CONFIG_SYS_FSL_ESDHC_ADDR       0
      #define CONFIG_SYS_MMC_ENV_DEV      2
      #define CONFIG_DOS_PARTITION
      #define CONFIG_CMD_FAT
      #define CONFIG_CMD_EXT2
  
      /* detect whether SD1, 2, 3, or 4 is boot device */
      #define CONFIG_DYNAMIC_MMC_DEVNO
  
      /* SD3(Mircro SD) 4 bit, SD4(EMMC) are 8 bit */
      #define CONFIG_MMC_8BIT_PORTS       0x8
  
      /* Setup target delay in DDR mode for each SD port */
      #define CONFIG_GET_DDR_TARGET_DELAY
  #endif
  
  /*
   * GPMI Nand Configs
   */
  /* #define CONFIG_CMD_NAND */
  
  #ifdef CONFIG_CMD_NAND
      #define CONFIG_NAND_GPMI
      #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK
      #define CONFIG_GPMI_NFC_V2
  
      #define CONFIG_GPMI_REG_BASE        GPMI_BASE_ADDR
      #define CONFIG_BCH_REG_BASE     BCH_BASE_ADDR
  
      #define NAND_MAX_CHIPS          8
      #define CONFIG_SYS_NAND_BASE        0x40000000
      #define CONFIG_SYS_MAX_NAND_DEVICE  1
  
      /* NAND is the unique module invoke APBH-DMA */
      #define CONFIG_APBH_DMA
      #define CONFIG_APBH_DMA_V2
      #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR
  #endif
  
  /*-----------------------------------------------------------------------
   * Stack sizes
   *
   * The stack sizes are set up in start.S using the settings below
   */
  #define CONFIG_STACKSIZE    (128 * 1024)    /* regular stack */
  
  /*-----------------------------------------------------------------------
   * Physical Memory Map
   */
  #define CONFIG_NR_DRAM_BANKS    1
  #define PHYS_SDRAM_1        CSD0_DDR_BASE_ADDR
  #define PHYS_SDRAM_1_SIZE   (1u * 1024 * 1024 * 1024)
  #define iomem_valid_addr(addr, size) \
      (addr &gt;= PHYS_SDRAM_1 &amp;&amp; addr &lt;= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
  
  /*-----------------------------------------------------------------------
   * FLASH and environment organization
   */
  #define CONFIG_SYS_NO_FLASH
  
  /* Monitor at beginning of flash */
  #define CONFIG_FSL_ENV_IN_MMC
  /* #define CONFIG_FSL_ENV_IN_NAND */
  
  #define CONFIG_ENV_SECT_SIZE    (8 * 1024)
  #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
  
  #if defined(CONFIG_FSL_ENV_IN_NAND)
      #define CONFIG_ENV_IS_IN_NAND 1
      #define CONFIG_ENV_OFFSET   0x100000
  #elif defined(CONFIG_FSL_ENV_IN_MMC)
      #define CONFIG_ENV_IS_IN_MMC    1
      #define CONFIG_ENV_OFFSET   (768 * 1024)
  #elif defined(CONFIG_FSL_ENV_IN_SF)
      #define CONFIG_ENV_IS_IN_SPI_FLASH  1
      #define CONFIG_ENV_SPI_CS       1
      #define CONFIG_ENV_OFFSET       (768 * 1024)
  #else
      #define CONFIG_ENV_IS_NOWHERE   1
  #endif
  
  /* #define CONFIG_SPLASH_SCREEN */
  /* #define CONFIG_MXC_EPDC */
  
  /*
   * SPLASH SCREEN Configs
   */
  //#define CONFIG_SPLASH_SCREEN
  #ifdef CONFIG_SPLASH_SCREEN
      /*
       * Framebuffer and LCD
       */
      #define CONFIG_LCD
      #define CONFIG_FB_BASE              (TEXT_BASE + 0x300000)
      #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  #ifdef CONFIG_MXC_EPDC
      #undef LCD_TEST_PATTERN
      /* #define CONFIG_SPLASH_IS_IN_MMC          1 */
      #define LCD_BPP                 LCD_MONOCHROME
      /* #define CONFIG_SPLASH_SCREEN_ALIGN       1 */
  
      #define CONFIG_MXC_EPDC             1
  
      #define CONFIG_WORKING_BUF_ADDR         (TEXT_BASE + 0x100000)
      #define CONFIG_WAVEFORM_BUF_ADDR        (TEXT_BASE + 0x200000)
      #define CONFIG_WAVEFORM_FILE_OFFSET     0x600000
      #define CONFIG_WAVEFORM_FILE_SIZE       0xF0A00
      #define CONFIG_WAVEFORM_FILE_IN_MMC
  
  #ifdef CONFIG_SPLASH_IS_IN_MMC
      #define CONFIG_SPLASH_IMG_OFFSET        0x4c000
      #define CONFIG_SPLASH_IMG_SIZE          0x19000
  #endif
  #else /* !CONFIG_MXC_EPDC */
      #define CONFIG_IPU_V3H
      #define CONFIG_VIDEO_MX5
      #define CONFIG_IPU_CLKRATE          260000000
      #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
      #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
      #define LCD_BPP                 LCD_COLOR16
      #define CONFIG_CMD_BMP
      #define CONFIG_BMP_8BPP
      #define CONFIG_SPLASH_SCREEN_ALIGN
      #define CONFIG_SYS_WHITE_ON_BLACK
  
      #define CONFIG_IMX_PWM
      #define IMX_PWM1_BASE    PWM1_BASE_ADDR
      #define IMX_PWM2_BASE    PWM2_BASE_ADDR
  #endif
  #endif /* CONFIG_SPLASH_SCREEN */
  #endif              /* __CONFIG_H */
  </code></pre>