title: How does a simple state machine look in Verilog?
body: <p>I'm trying to convert a flow chart simple <code>state machine</code> into <code>Verilog</code> code.
  But I'm somehow stuck with the following, and as I have hardly any knowledge in Verilog I'm probably missing something.</p>
  
  <p>The statemachine detects for an input stream of <code>0 and 1</code>, if the count of <code>1</code>s can be divided by 3 (or simply: if there have been 3 times number 1).</p>
  
  <p><img src="https://i.stack.imgur.com/UgNjh.png" alt="enter image description here"></p>
  
  <pre><code>module example (
    input clk,
    input rst,
    input input1,
    output output
  );
  
  reg state;
  reg nextstate;
  
  localparam state2 = 3'd0;
  localparam state1 = 3'd1;
  localparam state0 = 3'd2;
  
  always @(posedge clk or posedge rst) begin
    if (rst)
      state &lt;= state0;
    else
      state &lt;= nextstate;
  end
  
  always @* begin
    case(state)
      state0: begin
        if(input1)
          nextstate = state1;
        end
      state2: begin
        if(input1)
          nextstate = state0;
        end
      state1: begin
        if(input1)
          nextstate = state2;
        end
      default: nextstate = state0;
    endcase
  end
  
  always @* begin
    output1 = state0 &amp; input1;
  end
  
  endmodule
  </code></pre>
  
  <p>I'm not sure:</p>
  
  <ul>
  <li><p>do I have to define the inputs + outputs as <code>reg</code> or <code>wire</code>? Or is <code>input</code> and <code>output</code>! sufficient?</p></li>
  <li><p>must I provide a vector dimension for the <code>reg state, nextstate</code>? If yes, how to I know which dimension to pick?</p></li>
  <li><p>can I write these kind of assertions at the end like <code>state0 &amp; input1</code>? Or should I use <code>state = state0 &amp; input1 = ??</code> - yes, what?</p></li>
  </ul>