title: Make doesn't automatically invoke my "clean" target
body: <p>I have seen similar questions, but in my case none of the answers given work. I have written the following Makefile:</p>
  
  <pre><code># Compiler to use
  CC = gcc
  
  # flags to pass compiler
  CFLAGS = -ggdb3 -O0 -std=c99 -Wall -Werror
  
  # Name for the executable
  EXE = cuaterniones
  
  # space-separated list of header files
  HDRS = cuaternion.h
  
  # space-separated list of libraries, if any,
  # each of which should be prefixed with -l
  LIBS = -lm
  
  # space-separated list of source files
  SRCS = main.c cuaternion.c
  
  # automatically generated list of object files
  OBJS = $(SRCS:.c=.o)
  
  # default target
  $(EXE): $(OBJS) $(HDRS) Makefile
      $(CC) $(CFLAGS) -o $@ $(OBJS) $(LIBS)
  
  # dependencies 
  $(OBJS): $(HDRS) Makefile
  
  # housekeeping
  clean:
      rm -f *.o
  </code></pre>
  
  <p>As it can be inferred, I want to remove all object files after compiling. However, when I call make, the program is compiled, but object files are not removed. However, if I do: make clean, it works as expected. The thing is, I have seen that this should be automatic, if I call make it should automatically clean the files for me, and that is what I want. Moreover, I want to know why it is not working, what is my mistake?</p>