title: No feasible entries for infix operator "=" [VHDL]
body: <p>I have been writing the state machine for a traffic light controller.</p>
  
  <pre><code>-- Ampelsteuerung mit Zähler und FSM Componente
  
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;
  
  entity AMPLSTRG is 
      port (  CLK, B1, RES : in bit;
              MAINRE, MAINYE, MAINGR : out bit;
              FARMRE, FARMYE, FARMGR : out bit);
  end AMPLSTRG;
  
  architecture FUNKTION of AMPLSTRG is
  type AMP_STATE is (S0, S1, S2, S3, S4, S5, S6, S7, S8); -- Typendefinition
  signal SCLR : bit;
  signal CYCLES : unsigned (4 downto 0);
  signal STATE, NEXT_STATE : AMP_STATE;                   -- STATE = aktueller Status, NEXT_STATE nächster Status (Typenzuweisung)
  begin
  -- COUNTER Prozess
  CO: process (CLK)
  begin
      if CLK = '1' and CLK'event then
          if SCLR = '1' then
              CYCLES &lt;= (others =&gt; '0');                  -- 'others' = gesamten Vektor auf '0' setzten
          else
              CYCLES &lt;= CYCLES + 1;
          end if;
      end if;
  end process CO;
  
  AMP_SYNC: process (CLK, RES)
  begin
      if RES = '1' then
          STATE &lt;= S0 after 5 ns;
          SCLR &lt;= '1' after 5 ns;
      elsif CLK = '1' and CLK'event then
          STATE &lt;= NEXT_STATE after 5 ns;                 -- Zustandszuweisung
      end if;
  end process AMP_SYNC;
  
  AMP_KOMB: process (STATE, B1, CYCLES)
  begin
      -- default Werte Setzen
      MAINRE &lt;= '0' after 5 ns; 
      MAINYE &lt;= '0' after 5 ns;
      MAINGR &lt;= '0' after 5 ns;
  
      FARMRE &lt;= '0' after 5 ns; 
      FARMYE &lt;= '0' after 5 ns; 
      FARMGR &lt;= '0' after 5 ns;
  
      NEXT_STATE &lt;= STATE; 
      SCLR &lt;= '0';
  
      case STATE is
          when S0 =&gt; if B1 = '1' then 
                          MAINGR &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                          NEXT_STATE &lt;= S1 after 5 ns;
                          SCLR &lt;= '1' after 5 ns;
                      else                                -- MAINGR | FARMRE until B1 pressed
                          MAINGR &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                          SCLR &lt;= '1' after 5 ns;
                     end if;
  
          when S1 =&gt; if CYCLES = '5' then 
                          MAINGR &lt;= '0' after 5 ns;
                          MAINYE &lt;= '1' after 5 ns;               
                          NEXT_STATE &lt;= S2 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINGR | FARMRE for 5 sec
                          MAINGR &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                      end if;
  
          when S2 =&gt; if CYCLES = '5' then                         MAINRE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;               
                          NEXT_STATE &lt;= S3 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINYE | FARMRE for 5 sec
                          MAINYE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                      end if;
  
          when S3 =&gt; if CYCLES = '2' then 
                          MAINRE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                          FARMYE &lt;= '1' after 5 ns;               
                          NEXT_STATE &lt;= S4 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINRE | FARMRE for 2 sec
                          MAINRE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                      end if;
  
          when S4 =&gt; if CYCLES = '2' then 
                          MAINRE &lt;= '1' after 5 ns;
                          FARMGR &lt;= '1' after 5 ns;           
                          NEXT_STATE &lt;= S5 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINRE | FARMRE | FARMYE for 2 sec
                          MAINRE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;
                          FARMYE &lt;= '1' after 5 ns;
                      end if;
  
          when S5 =&gt; if CYCLES = '30' then 
                          MAINRE &lt;= '1' after 5 ns;
                          FARMYE &lt;= '1' after 5 ns;           
                          NEXT_STATE &lt;= S6 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINRE | FARMGR for 30 sec
                          MAINRE &lt;= '1' after 5 ns;
                          FARMGR &lt;= '1' after 5 ns;   
                      end if; 
  
          when S6 =&gt; if CYCLES = '5' then 
                          MAINRE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;           
                          NEXT_STATE &lt;= S7 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINRE | FARMYE for 5 sec
                          MAINRE &lt;= '1' after 5 ns;
                          FARMYE &lt;= '1' after 5 ns;   
                      end if;
  
          when S7 =&gt; if CYCLES = '2' then 
                          MAINRE &lt;= '1' after 5 ns;
                          MAINYE &lt;= '1' after 5 ns;   
                          FARMRE &lt;= '1' after 5 ns;       
                          NEXT_STATE &lt;= S8 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINRE | FARMRE for 2 sec
                          MAINRE &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;       
                      end if;
  
          when S8 =&gt; if CYCLES = '2' then 
                          MAINGR &lt;= '1' after 5 ns;
                          FARMRE &lt;= '1' after 5 ns;           
                          NEXT_STATE &lt;= S0 after 5 ns;
                          SCLR &lt;= '1';
                      else                                -- MAINRE | MAINYE | FARMRE for 2 sec
                          MAINRE &lt;= '1' after 5 ns;
                          MAINYE &lt;= '1' after 5 ns;   
                          FARMRE &lt;= '1' after 5 ns;       
                      end if;
  
  end process AMP_KOMB;
  end FUNKTION;
  </code></pre>
  
  <p>While compiling the code in <strong>Modelsim PE Student</strong> I get the following error:</p>
  
  <pre><code>No feasible entries for infix operator "="
  </code></pre>
  
  <p>After trying many different libraries I can't find any solution to fix this error. I guess it's a problem with the wrong library or the wrong use of the "=" operator. </p>
  
  <p>Here is the full error report from Modelsim:</p>
  
  <pre><code>** Error: [...]/AMPSTR.vhdl(68): No feasible entries for infix operator "=".
  ** Error: [...]/AMPSTR.vhdl(68): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
  ** Error: [...]/AMPSTR.vhdl(78): No feasible entries for infix operator "=".
  ** Error: [...]/AMPSTR.vhdl(78): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
  ** Error: [...]/AMPSTR.vhdl(87): No feasible entries for infix operator "=".
  ** Error: [...]/AMPSTR.vhdl(87): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
  ** Error: [...]/AMPSTR.vhdl(98): No feasible entries for infix operator "=".
  ** Error: [...]/AMPSTR.vhdl(98): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
  ** Error: [...]/AMPSTR.vhdl(109): near "'": syntax error
  ** Error: [...]/AMPSTR.vhdl(114): near "else": expecting END or WHEN
  ** Error: [...]/AMPSTR.vhdl(117): near "if": expecting PROCESS
  </code></pre>