title: why PCIe TLP header has "Last DW BE" and "First DW BE"?
body: <p>I've met a problem related to PCIe. I use a driver to write <code>0x12345678</code> to BAR0+offset, and use Xilinx Chipscope to see the waveform. On our Intel Rangeley board, we see TLP payload is split into two DWs, that is <code>00_00_00_78 56_34_12_00</code>, while on a dell PC, we see only one DW in payload. I'm sure both case conform the PCIe specification. </p>
  
  <p>But I really wonder, why should PCIe specification has this kind of design, that is "Last DW BE" and "First DW BE" in 2nd DW of TLP header?</p>