title: initialize constant array of records from another constant in vhdl
body: <p>I am writing constants for stimulus and having a problem with building constant form other constants.</p>
  
  <p><strong>UPDATE: 
  in the example below (provided by user1155120)</strong></p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all; 
  
  package snippet_pkg is
  
  type pixel is record
    x: std_logic_vector(3 downto 0);
    y: std_logic_vector(3 downto 0);     
  end record;   
  
  type array_pixel is array (natural range &lt;&gt;) of pixel;
  constant array_1 : array_pixel(0 to 2) := 
    (0 =&gt; (x"0", x"0"),   
     1 =&gt; (x"1", x"1"),  
     2 =&gt; (x"2", x"2")  
    );
  constant array_2 : array_pixel(0 to 3) := 
    (array_1'range =&gt; array_1,    
     3 =&gt; pixel'(x"3", x"3") 
  );
  
  constant element : pixel := (x =&gt; x"3", y =&gt; x"3");
  constant array_3 : array_pixel(0 to 3) := array_1 &amp; element;
  constant array_4 : array_pixel(0 to 3) := array_1 &amp; pixel'(x =&gt; x"3", y =&gt; x"3");
  
  end package; 
  
  library ieee; 
  use ieee.std_logic_1164.all;
  
  use work.snippet_pkg.all;
  
  entity snippet_test is
  end entity;
  
  architecture foo of snippet_test is  
  begin
  
  PASSIVE: process  
  begin  
    for i in 0 to 2 loop  
      report "array_1(" &amp; integer'image(i) &amp; ").x = " &amp; to_string(array_1(i).x);
      report "array_1(" &amp; integer'image(i) &amp; ").y = " &amp; to_string(array_1(i).y);
    end loop;
    for i in 0 to 3 loop  
      report "array_2(" &amp; integer'image(i) &amp; ").x = " &amp; to_string(array_2(i).x);
      report "array_2(" &amp; integer'image(i) &amp; ").y = " &amp; to_string(array_2(i).y);
   end loop;
  
  wait;
  end process; 
  end architecture;
  </code></pre>
  
  <p>I have an array of records like below:</p>
  
  <pre><code>type pixel is record
    x  : std_logic_vector(3 downto 0);
    y  : std_logic_vector(3 downto 0); 
  end record;
  
  type array_pixel is array (natural range &lt;&gt;) of pixel;
  </code></pre>
  
  <p>and then I build a constant from this like this:</p>
  
  <pre><code>constant array_1 : array_pixel(0 to 2) :=
    (0 =&gt; (x"0" , x"0"),
     1 =&gt; (x"1" , x"1"),
     2 =&gt; (x"2" , x"2")
    );
  </code></pre>
  
  <p>Now I want to build another array with a bigger index using array_1 like this:</p>
  
  <pre><code>constant array_2 : array_pixel(0 to 3) :=
    (0 to 2 =&gt; array_1,
     3 =&gt; (x"3" , x"3")
    );
  </code></pre>
  
  <p>but I am getting this error in ModelSim:</p>
  
  <p>fatal: (SIGSEGV) Bad pointer access.
  fatal: vsimk is exiting with code 211.</p>
  
  <p>I am compiling via VUnit. Is this a bug in ModelSim or wrong VHDL coding?</p>
  
  <p><strong>UPDATE:</strong> ModelSim mentor graphic doesn't produce this error but it gives wrong values as below:</p>
  
  <pre><code># ** Note: array_1(0).x = 0000
  # ** Note: array_1(0).y = 0000
  # ** Note: array_1(1).x = 0001
  # ** Note: array_1(1).y = 0001
  # ** Note: array_1(2).x = 0010
  # ** Note: array_1(2).y = 0010
  
  # ** Note: array_2(0).x = ?(16) U ?(66) ?(9)
  # ** Note: array_2(0).y = ?(164) U ?(76) 1
  # ** Note: array_2(1).x = ?(208) ?(81) ?(147) 0
  # ** Note: array_2(1).y = ?(85) ?(88) U X
  # ** Note: array_2(2).x = ?(238) ?(255) ?(238) ?(255)
  # ** Note: array_2(2).y = 0UUU
  # ** Note: array_2(3).x = 0011
  # ** Note: array_2(3).y = 0011 
  </code></pre>
  
  <p>only last index is right and the one which are assigned by <code>0 to 2 =&gt; array_1</code> are wrong.</p>