title: Using Generate in Vhdl
body: <p>I have following piece of code in Vhdl now I want to redirect this signal S1 conditionally  to the output port, I will be gratful if someone can guide me through this.</p>
  
  <pre><code>Gen: for index in 0 to 4 generate
  
   signal s1 : ARRAY_TYPE; --- array of (0 to 7) std_logic_vector (7 downto 0);
   begin  
    process(CLK)
    begin
      if (rising_edge (CLK)) then
          S1(counter_index) &lt;= S_in((index*8+7) downto (index*8));
        end if;  
      end  if;
    end process;
  end generate Gen;
  </code></pre>
  
  <p>I know we can use a process inside generate loop but is otherway around also possible! If I declare S1 as global signal it complains of connected to multi driven net? How this is different?</p>
  
  <p>I will be really grateful if someone can guide me through this</p>