title: Generate all project dependencies in a single file using gcc -MM flag
body: <p>I want to generate a single dependency file which consists of all the dependencies of source files using gcc -M flags through Makefile. I googled for this solution but, all the solutions mentioned are for generating multiple deps files for multiple objects. </p>
  
  <pre><code>DEPS = make.dep
  
  $(OBJS): $(SOURCES)
      @$(CC) -MM $(SOURCEs) &gt; $(DEPS)
      @mv -f $(DEPS) $(DEPS).tmp
      @sed -e 's|.$@:|$@:|' &lt; $(DEPS).tmp &gt; $(DEPS)
      @sed -e 's/.*://' -e 's/\\$$//' &lt; $(DEPS).tmp | fmt -1 | \
        sed -e 's/^ *//' -e 's/$$/:/' &gt;&gt; $(DEPS)
      @rm -f $(DEPS).tmp
  </code></pre>
  
  <p>But it is not working properly. Please tell me where i'm making the mistake.</p>