title: How to use const in verilog
body: <p>Instead of using </p>
  
  <pre><code>module ... ( .. )  ;
  
       #15 
  endmodule
  </code></pre>
  
  <p>I want use </p>
  
  <pre><code>module ... ( ... ) ;
   // GateDelay is a const, like in c language const int GateDelay = 15 ;
   # GateDelay     
  
  endmodule
  </code></pre>
  
  <p>Or same thing</p>
  
  <pre><code>module ... ( ... ) ;
   // assume Wordsize is defined at " define Wordsize 15 "
   reg [ Wordsize -1 : 0 ] mem ;
  
  endmodule
  </code></pre>
  
  <p>Can I do that wish in verilog ? </p>