title: Difference between Behavioral, RTL and gate Level
body: <p>I'm trying to fully understand the differences between the abstraction levels of Verilog, I get what the description of each level says but I still can't get it on the play.</p>
  
  <p>For this case, I will paste some Verilog codes and what I think about them:</p>
  
  <ol>
  <li><p>The following code is in Behavioral Level.</p>
  
  <pre><code>always  @ (a or b or sel)
    begin
      y = 0;
      if (sel == 0) begin
        y = a;
      end else begin
      y = b;
    end
  end
  </code></pre></li>
  <li><p>This (just an example) is in Gate Level</p>
  
  <pre><code>module test(clk,  ready, next, Q);
    input clk, enable, next;
    output Q;
  
    \**SEQGEN** reg_1 (.clear(1'b0), .next_state(next), .clocked_on(clk), .Q(Q), .synch_enable(enable) );
  
  endmodule
  </code></pre></li>
  <li><p>I don't know if this code is in RTL or Gate Level ( I expect that the always keyword make this RTL and not Gate Level )</p>
  
  <pre><code>module dff_from_nand();
    wire Q,Q_BAR;
    reg D,CLK;
  
    nand U1 (X,D,CLK) ;
    nand U2 (Y,X,CLK) ;
    nand U3 (Q,Q_BAR,X);
    nand U4 (Q_BAR,Q,Y);
  
    // Testbench of above code
    initial begin
      $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
      CLK = 0;
      D = 0;
      #3  D = 1;
      #3  D = 0;
      #3  $finish;
    end   
  
    always  #2  CLK = ~CLK;
  
  endmodule
  </code></pre></li>
  </ol>
  
  <p>I already know that <code>initial begin</code> and <code>end</code> are not synthesizeable and just used for testing. Now I have 2 questions</p>
  
  <ol>
  <li><p>Third (and second) code is RTL or Gate-Leve? What would be a good RTL code example? I found this <a href="https://stackoverflow.com/questions/11007729/better-way-of-coding-a-d-flip-flop">RTL Code Example</a> but is that really RTL? For me it looks like behavioral level.</p></li>
  <li><p>What means Verilog netlist? Is it the same as gate level or it have a context base definition?</p></li>
  </ol>
  
  <p>I'm confused because in some websites I don't know if they're saying 'this is a Verilog code that is using logic gates'  or 'this is a Verilog code in gate-level'</p>
  
  <p>I will be very happy if somebody who wants to explain more details about this topic :)</p>