title: vhdl: too many actuals for block...with only 0 formals
body: <p>Last day, last 3 hours before we give the project and we just realized we have this error!
  I am not very good in vhdl so I can't understand what the problem is!</p>
  
  <p>Error (10588): VHDL Generic Map Aspect error at addsub16.vhd(31): too many actuals for block "fulladder16" with only 0 formals</p>
  
  <pre><code>LIBRARY ieee;   
  USE ieee.std_logic_1164.all;   
  
  ENTITY addsub16 IS    
   PORT(X, Y    :IN STD_LOGIC_VECTOR(15 DOWNTO 0);    
       Add_Sub  :IN STD_LOGIC;    
       Result   :OUT STD_LOGIC_VECTOR(15 DOWNTO 0);    
       Cout     :OUT STD_LOGIC;   
       Overflow :OUT STD_LOGIC);   
  END addsub16;   
  
  ARCHITECTURE Structure OF addsub16 IS    
      COMPONENT fulladder16   
          PORT(Cin      :IN STD_LOGIC;    
               X, Y     :IN STD_LOGIC_VECTOR(15 DOWNTO 0);    
               Sum      :OUT STD_LOGIC_VECTOR(15 DOWNTO 0);     
               Cout     :OUT STD_LOGIC;    
               Overflow :OUT STD_LOGIC);    
      END COMPONENT;    
      SIGNAL y_mod :STD_LOGIC_VECTOR(15 DOWNTO 0);    
      BEGIN
  
      gen_XOR:    
      FOR i IN 0 TO 15 GENERATE    
          y_mod(i) &lt;= Y(i) XOR Add_Sub;     
      END GENERATE;     
  
      adder:fulladder16 GENERIC MAP(16)     
                   PORT MAP(Add_Sub, X, y_mod, Result, Cout, Overflow);    
    END Structure;     
  </code></pre>