title: ERROR:HDLCompiler:1731 - found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
body: <p>I have an error in my vhdl code. I'm using ISE design.
  What should I do to solve my problem?</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;
  use ieee.math_real.all;
  
  library std;
  use std.standard.all;
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  --use IEEE.NUMERIC_STD.ALL;
  
  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  entity neuron2 is
      port ( A : in integer :=1;
                  B : in integer :=2;
  
                  D : out real);
      constant C : real := 1.25;
      constant E : real := 2.25;
      end neuron2;
  
  architecture Behavioral of neuron2 is
  
  begin
  
    D &lt;= A+B+C+E;
  
  end Behavioral;
  </code></pre>
  
  <p>I get the following error:</p>
  
  <blockquote>
    <p>ERROR:HDLCompiler:1731 -
    "C:\Users\Ida\Downloads\Mojo-Base-VHDL\percobaan2\neuron2.vhd" Line
    51: found '0' definitions of operator "+", cannot determine exact
    overloaded matching definition for "+"  ERROR:HDLCompiler:854 -
    "C:\Users\Ida\Downloads\Mojo-Base-VHDL\percobaan2\neuron2.vhd" Line
    46: Unit  ignored due to previous errors.</p>
  </blockquote>