title: How to rename the .mcs output file when synthesizing a design with Xilinx ISE
body: <p>When I synthesize a design using <code>Xilinx ISE</code>, the output file is named <code>untitled.mcs</code>. I would like to configure the project to use an output filename more appropriate to the project I am synthesizing.</p>
  
  <p>I have examined all the properties easily reachable by right clicking the the implementation panel in the tool, but I can't find a configuration option to change output file names. I have also searched the help, but couldn't find anything useful. Can anyone suggest where I need to configure the output filename or tell me where or what to search?</p>
  
  <p>I am aware of at least two things I could be doing wrong and would appreciate comments. First, I am not using <code>TCL</code> to synthesize my project. I just right click in the implementation panel and choose run. Perhaps if I create a <code>TCL</code> script to I would have finer control or output file naming. Second, I can see several files named <code>untitled.x</code> where <code>x</code> is <code>[cfi|mcs|prm|sig]</code>. I guess these are a sequence of files processed from one format to another, and if I understood the process, I could configure the name of the first and see all the derived files change their names to follow.</p>