title: Verilog: Using reg As Counters For for-loops
body: <p>In a module:</p>
  
  <pre><code>reg a, b;
  integer i, j;
  
  initial
       begin
            for (a = 0; a &lt; 2; a = a + 1)     
                 //some code
       end
  </code></pre>
  
  <p>The textbook says it would be incorrect to get rid of integers <strong>i</strong> and <strong>j</strong> and use reg <strong>a</strong> and <strong>b</strong> directly as loop counters. Hint: reg variables have a fixed size and, hence, they wrap.</p>
  
  <p>What does that mean? Doesn't integer have a fixed size as well? And what's wrapping?</p>