title: Why can't I increment this `std_logic_vector`
body: <p>What's going on here? Why am I getting an 'operator argument type mismatch', and what can I do to fix it?</p>
  
  <pre><code>--
  -- 32-bit counter with enable and async reset
  --
  architecture synthesis1 of counter_32bit is    
  signal nextvalue : std_logic_vector ( 31 downto 0 );    
  begin
  
    --
    -- combo
    --
    nextvalue &lt;= value + 1; -- here
  
    --
    -- sequential
    --
    ff:process( clk, rst )
    begin
  
      if( rst = '1' ) then
        value &lt;= 0; -- and here...
      elsif( clk'event and ( clk ='1' ) ) then
        if( ena = '1' ) then
           value &lt;= nextvalue;
        end if;
      end if;
  
    end process ff;    
  
  end synthesis1;
  </code></pre>
  
  <p>Thanks</p>