title: Verilog error: XXX is not a constant
body: <p>I am doing my homework about making an ALU, and I get an error. I search it but didn't get the reason.Why does it happen?
  The error message is S2 is not a constant.<code>case ({S2,S1,S0})</code></p>
  
  <p>```</p>
  
  <pre><code>module ALU(
      input S0,
      input S1,
      input S2,
      input IN1,
      input IN2,
      input IN3,
      output OUT1,
      output OUT2
      );
  
  
  case ({S2,S1,S0})//{S2,S1,S0}
  3'b000:
  begin
      assign OUT1=IN1&amp;IN2;//and a1(OUT1,IN1,IN2);
      assign OUT2 = 1'b0;
  end
  3'b001:
  begin
      assign OUT1=IN1|IN2;//or o1(OUT1,IN1,IN2);
      assign OUT2=1'b0;
  end
  3'b010:
  begin
      assign OUT1=!IN1;
      assign OUT2=1'b0;
  end
  3'b011:
  begin
      assign OUT1=!IN2;
      assign OUT2=1'b0;
  end
  3'b100:
  begin
      assign OUT1=IN1^IN2;
      assign OUT2=1'b0;
  end
  3'b101:FullAdder1 fa(.IN1(IN1),.IN2(IN2),.IN3(IN3),.OUT1(OUT1),.OUT2(OUT2));
  3'b110:FullSubtracter1 fs(.IN1(IN1),.IN2(IN2),.IN3(IN3),.OUT1(OUT1),.OUT2(OUT2));
  3'b111:
  begin
      assign OUT1=1'b0;
      assign OUT2=1'b0;
  end
  default:
  begin
      assign OUT1=1'b0;
      assign OUT2=1'b0;
  end
  endcase
  endmodule
  
  ```
  </code></pre>