title: Dynamic Arrray Size in VHDL
body: <p>I want to use dynamic range of array , so using "N" for converting an incoming vector signal to integer.  Using the specifc incoming port "Size" gives me an error, while fixed vector produces perfect output.</p>
  
  <pre><code>architecture EXAMPLE of Computation is
  
  signal size :std_logic_vector (7 downto 0);
  
  process (ACLK, SLAVE_ARESETN) is
  
  variable N: integer:=conv_integer  ("00000111") ;  ---WORKING
  
  --variable N: integer:=conv_integer  (size) ; -- Not working
  type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 ); 
  
  variable RAM :memory; 
  </code></pre>
  
  <p>Only reason to do this type of coding is send as much data as possible to FPGA .As I need to send Data from DDR to Custom IP via DMA in vivado may be more than 100 MB. so kindly guide me if I am trying to implement in wrong way as stated above. </p>