title: vhdl generic parameters used by other generic parameters (error: generic "parameter" is not visible here)
body: <p>In Verilog, I can define a parameter and then use it to define another parameter.  For example:</p>
  
  <pre><code>module stuff1 #(
     parameter AW = 16,
     parameter DW = 16,
     parameter FW = AW + DW + 2,
  ) (
      input   wire [AW-1:0]     adr,
      input   wire [DW-1:0]     dat,
      output  wire [FW-1:0]     fifo
  );
  endmodule
  </code></pre>
  
  <p>How can I do something similar in VHDL generic?  Example:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity stuff1 is
      generic(
          AW          : integer := 15;
          DW          : integer := 15;
          FW          : integer := AW + DW + 2
      );
      port(
          adr   : in    std_logic_vector(AW-1 downto 0);
          dat   : in    std_logic_vector(DW-1 downto 0);
          fifo  : out   std_logic_vector(FW-1 downto 0)
      );
  end entity;
  
  architecture rtl of stuff1 is
  begin
  
  end architecture;
  </code></pre>
  
  <p>When I try to compile this code, I get the following error in VHDL:</p>
  
  <pre><code>..\..\simtools\ghdl\bin\ghdl.exe -a bus_direct_server.vhdl
  stuff1.vhdl: generic "aw" is not visible here
  stuff1.vhdl: generic "dw" is not visible here
  </code></pre>
  
  <p>I'm wondering, is this possible in VHDL to automatically calculate FW parameter from AW and DW? or was Verilog more snazzy on this one occasion?</p>