title: Vivado 2016.1: Upon synthesis it is removing useful logic. Verilog
body: <p>I am currently working on building a soft core processor, and I have been having trouble synthesizing a Verilog Implemented RAM and other sequential elements. I decided to work individually on each section of the processor in order to find out what´s going on, no luck yet I'm afraid. The circuit I tried to synthesize does mainly 2 things: Fills memory with data driven by a clock; after the memory is filled with data a flag will indicate this sending a signal to an external processor, which will send another signal called ready in order to read and store memory content.</p>
  <p>These are the modules:</p>
  <blockquote>
  <h2>TOP MODULE</h2>
  </blockquote>
  <pre><code>module DATATEST(clk,JRED,led,jd,ja);
   
   input clk;
   input  JRED;
   output [1:0] led;
   output [7:0] ja;
   output [1:0] jd;
   
   
   
   wire RESP,FLAG,RDY,SENT,CL;
   wire [7:0] DATA;
   
   wire BFLAG, BCL,BFL,BL;
   wire WD;
   wire [31:0] MR,MW,FAD,LAD,AD;
   
   assign CL = clk;
   assign RDY = JRED;
   assign led[0] = BL;
   assign led[1] = SENT;
   assign ja = DATA;
   assign jd[0] = RESP; 
   assign jd[1] = FLAG;
   
    fill_mem FM1(.clock(BCL),.flag(FLAG),.out(MW),.ad(FAD));
  
    not_gate NG1(.I(BFLAG),.O(WD));
  
    mux MUX1(.a(FAD),.b(LAD),.c(BFL),.o(AD));
  
    data_memory DM1(.address(AD),.wr_da(MW),.mem_write(WD),.mem_read(FLAG),.re_da(MR));
  
    com_out CM1(.ready(RDY),.flag(BFL),.in(MR),.out(DATA),.sent(SENT),.response(RESP),
    .address(LAD));
   
  
    buffer F1(.in(FLAG),.out(BFLAG));
  
    buffer F2(.in(FLAG),.out(BFL));
  
    buffer F3(.in(FLAG),.out(BL));
  
    buffer C1(.in(CL),.out(BCL));
    
  endmodule
  `
  </code></pre>
  <blockquote>
  <h2>OTHER MODULES:</h2>
  </blockquote>
  <pre><code>module data_memory(address,wr_da,mem_write,mem_read,re_da);
   
   parameter SIZE = 16;
   input [31:0] address;
   input [31:0] wr_da;
   input mem_write;
   input mem_read;
   output [31:0] re_da;
    
   reg [7:0] MEM [0:SIZE-1];
   
   assign re_da = (mem_read == 1) ? {MEM[address],MEM[address+1],MEM[address+2],MEM[address+3]}:0 ;
   
   always @ (wr_da, address)
    begin
   
    
   
      if (mem_write == 1)
      begin
       MEM[address] = wr_da[31:24];
       MEM[address+1] = wr_da[23:16];
       MEM[address+2] = wr_da[15:8];
       MEM[address+3] = wr_da[7:0];
      end
  
     
    
    end
  
  module mux(a,b,c,o);
  
   parameter N = 32;
   input [N-1:0] a;
   input [N-1:0] b;
   input c;
   output reg [N-1:0] o = 0;
  
   always @*
   begin
   
    o = 0;
   
    case (c)
     
     0: o = a;
     1: o = b;
    
     default: o = 0;
    
    endcase
  
   end
   
  endmodule
  
  module com_out(ready,flag,in,out,sent,response,address);
  
   input ready;
   input flag;
   input [31:0] in;
   output reg [7:0] out;
   output reg sent;
   output reg [31:0] address = 0;
   output  response;
   reg SINT = 0;
   reg COUNT = 0;
   reg R = 0; 
   reg [15:0] SEND = 0;
   wire  [7:0] DATA [3:0];
   
   assign DATA[0] = in[31:24];
   assign DATA[1] = in[23:16];
   assign DATA[2] = in[15:8];
   assign DATA[3] = in[7:0];
   
   assign response = (R == 1) ? 1:0;
    
   always @ (ready)
   begin
    out = 0;
    
    if (ready == 1)
    begin
    
     if ((flag==1) &amp;&amp; (SINT==0))
      begin
     
       out = DATA[SEND];
       R = 1;
       SEND = SEND+1;
     
       if (SEND==4)
       begin
        address = address + 4;
        SEND = 0; 
        COUNT = COUNT + 1; 
       end
       else
        address = address;
        
      end
     
      else
       out = 0;
     
     end
     
     else 
      R = 0;
  
     
     if (COUNT == 4)
     begin
      sent = 1;
      SINT = 1;
     end
     
     else
     begin
      sent = 0;
      SINT = 0;
     end
   end
   
  endmodule
  
  
  module fill_mem (clock,flag,out,ad);
   
   input clock;
   output reg flag = 0;
   output reg [31:0] out = 0; 
   output  [31:0] ad ;
   reg [31:0] COMP = 0;
   reg [31:0] COND = 0;
   assign ad = COND;
   
   always @ (negedge clock)
   begin
    
    COMP = COMP + 4;
    COND = COMP - 4;
    
    case  (COND)
     0 : out = 32'hACDECACA; 
     4 : out =  32'hACAFECAD; 
     8: out = 32'hCAFEBEEF; 
     12: out = 32'hDEADCAFE; 
     default: out = 0; 
    endcase
    
    
    
    if (COMP &gt;= 20)
     flag = 1;
    else
     flag = 0;
     
   end
  endmodule
  </code></pre>
  <p>Even tho simulation works perfectly, synthesis throws some warning messages:</p>
  <blockquote>
  <h2>WARNING MESSAGES</h2>
  </blockquote>
  <pre><code>[Synth 8-3332] Sequential element (FM1/out_reg[31]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[27]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[26]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[25]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[24]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[23]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[20]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[19]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[18]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[11]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[10]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[9]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[7]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[5]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[4]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[2]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[1]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/COND_reg[0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[0][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[1][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[2][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[3][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[4][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[5][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[6][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[7][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[8][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[9][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[10][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[11][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[12][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[13][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[14][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[15][3]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/COMP_reg[0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/COMP_reg[1]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/COND_reg[1]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (FM1/out_reg[8]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[0][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[2][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[4][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[6][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[8][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[10][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[12][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (DM1/MEM_reg[14][0]) is unused and will be removed from module DATATEST.
  
  [Synth 8-3332] Sequential element (CM1/address_reg[0]) is unused and will be removed from module DATATEST.
  </code></pre>
  <p>And I wish I understood why, since all the elements are actually used.</p>
  <p>So, I would be very grateful if could help me to figure out what the problem is and how to solve it. Thanks in advance :D T.T</p>