title: VHDL unsigned vector vs integer comparison
body: <p>In vhdl, assume I have an unsigned vector defined as follows:</p>
  
  <pre><code>signal s_col_rd_check : unsigned(7 downto 0);
  </code></pre>
  
  <p>Now, whether I use the following library,</p>
  
  <pre><code>use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
  </code></pre>
  
  <p>Or the following</p>
  
  <pre><code>use ieee.numeric_std.all;
  </code></pre>
  
  <p>Can I use do a comparison between my unsigned vector and an integer value as follows?</p>
  
  <pre><code>some_assignment &lt;= '1' when (s_col_rd_check &lt; 190) else '0';
  </code></pre>
  
  <p>where 190 is just an integer.
  Will the above comparison be the same whether I use either one of the libraries? </p>
  
  <p>Thanks, 
  --Rudy </p>