title: When should I use std_logic_vector and when should I use other data types?
body: <p>I'm new to VHDL and am having trouble figuring out which data types are appropriate to use where. If I understand correctly, for synthesis, all top level entity ports should be declared either std_logic_vector or std_logic and never any other type.</p>
  
  <p>But std_logic_vector doesn't support arithmetics so how should I handle this?</p>
  
  <p>My intuition tells me that I should simply use std_logic_vector at the top level and then convert this to and from integral data types when passing it to other entities. Is this correct?</p>
  
  <p>And what integral data type (integer, unsigned, signed) should be used where? I understand the difference between signed and unsigned but when should I use integer?</p>