title: Upsample with Verilog
body: <p>I need to upsample(2x) my data using Verilog. I think to use three ports for input and one port for output. Input ports are filterin, reset and clock. Output port is filterout. Also I need dynamic input size. How can I realize this with Verilog.</p>
  
  <p>Edit1:
  My input and output datas are 16 bit long. I just need a Verilog code to do this:</p>
  
  <p>If Input: 1 2 3,
  Then Output: 1 0 2 0 3 0.</p>
  
  <p>If Input: 1 2 3 4 5,
  Then Output: 1 0 2 0 3 0 4 0 5 0.</p>
  
  <p>Edit2:
  I created a verilog file to solve this but it didn't solve my problem.</p>
  
  <h2>US1.v file</h2>
  
  <pre><code>`timescale 1ns / 1ps
  
  module US1 (filterin,clk,filterinus);
  
      input [15:0] filterin;
      input clk;
  
      output reg [15:0] filterinus;
  
      integer i=0;
  
      always @ (posedge clk) begin
          if (i==0) begin
              filterinus &lt;= filterin;
          end
          else begin
              filterinus &lt;= 0;
          end
          i=~i;
      end
  
  
  endmodule
  </code></pre>
  
  <p>I tested this code with the following Test bench:</p>
  
  <h2>Test.v file</h2>
  
  <pre><code>`timescale 1ps/1ps
  module Test;
  
      reg [15:0] filterin;
      reg clk;
      wire [15:0] filterinus;
  
      US1 uut (
          .filterin(filterin), 
          .clk(clk),
          .filterinus(filterinus)
      );
  
      initial begin
          clk = 1;
  
          filterin = 1;
          #2 filterin = 2;
          #2 filterin = 3;
          #2 filterin = 4;
          #2 filterin = 5;
  
          #30 $finish;
      end
  
      always #1 clk = ~clk;
  
  endmodule
  </code></pre>
  
  <p>As is seen, my input is: 1 2 3 4 5. 
  My output is: 1 0 3 0 5 0 5 0 5 0...
  I need to see: 1 0 2 0 3 0 4 0 5 0 0 0 0 0...</p>