title: Case statements in Verilog?
body: <p>Say I have a 8 bit output reg called &quot;myReg&quot; and a 8 bit input called &quot;checkReg&quot;. Can I check and assign their values in a case statement using hex values?</p>
  <p>For instance (assume the code is in an always block)</p>
  <pre><code>case (checkReg)
      2'hA0:myReg &lt;= 2'h10;
      2'hB0:myReg &lt;= 2'hC0;
      //Other cases
  endcase
  </code></pre>
  <p>I want the above piece of code to do the following: If checkReg = 10100000, set myReg to 00010000. If checkReg = 10110000, set myReg to 11000000.</p>
  <p>I wasn't sure if I could check and assign hex values to a vector and have it automatically converted to binary.</p>