title: Trying to understand simulation errors with Xilinx
body: <p>I am getting some erros that I cant make sense and was hoping I could get some help.</p>
  
  <pre><code>ERROR: [VRFC 10-469] cannot update 'in' object shift_reg [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:25]
  ERROR: [VRFC 10-925] indexed name is not a std_logic_vector [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:27]
  ERROR: [VRFC 10-1504] unit simple_one_bit_serial_shift_register_behavior ignored due to previous errors [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:16]
  INFO: [VRFC 10-240] VHDL file C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd ignored due to errors
  </code></pre>
  
  <p>I have tried altering the code to suit but nothing works ! this is the code: </p>
  
  <pre><code>    library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
  
  entity simple_one_bit_serial_shift_register is
     port(
        clk      : in  std_logic;
        reset      : in  std_logic;
        shift_in  : in  std_logic_vector(31 downto 0);
        shift_reg  : in std_logic_vector(1 downto 0);
        shift_out : out std_logic_vector(31 downto 0)
     );
  end simple_one_bit_serial_shift_register;
  
  architecture simple_one_bit_serial_shift_register_behavior of simple_one_bit_serial_shift_register is 
  begin
  
  --signal shift_reg : std_logic_vector(31 downto 0);
  --signal shift_in : std_logic;
  --signal shift_out : std_logic;
  process (clk) 
      begin
      if rising_edge(clk) then
          shift_reg &lt;= shift_reg(30 downto 0) &amp; shift_in;
      end if;
      shift_out &lt;= shift_reg(31);
  end process;
  end simple_one_bit_serial_shift_register_behavior
  </code></pre>
  
  <p>;</p>