title: ARMv8 exception vectors and handling
body: <p>I am working on a ARM Cortex A53 processor and can not figure out how to set up interrupts to work.</p>
  
  <p>I've read the documentation regarding this subject but still find it confusing and cannot get interrupts to work in a bare metal environment.</p>
  
  <p>Here is the vector table I currently have:</p>
  
  <pre><code>_vectors:
      /* Current EL with SP0 */
      b sync_addr /* Synchronous */
      .balign 128
      b irq_addr  /* IRQ/vIRQ */
      .balign 128
      b fiq_addr  /* FIQ/vFIQ */
      .balign 128
      b serr_addr /* SError/vSError */
      /* Current EL with SPn */
      b sync_addr /* Synchronous */
      .balign 128
      b irq_addr  /* IRQ/vIRQ */
      .balign 128
      b fiq_addr  /* FIQ/vFIQ */
      .balign 128
      b serr_addr /* SError/vSError */
      /* Lower EL with Aarch64 */
      b sync_addr /* Synchronous */
      .balign 128
      b irq_addr  /* IRQ/vIRQ */
      .balign 128
      b fiq_addr  /* FIQ/vFIQ */
      .balign 128
      b serr_addr /* SError/vSError */
      /* Lower EL with Aarch32 */
      b sync_addr /* Synchronous */
      .balign 128
      b irq_addr  /* IRQ/vIRQ */
      .balign 128
      b fiq_addr  /* FIQ/vFIQ */
      .balign 128
      b serr_addr /* SError/vSError */
  
  sync_addr: .word reset_handler
  irq_addr:  .word irq_handler
  fiq_addr:  .word reset_handler
  serr_addr: .word reset_handler
  </code></pre>
  
  <p>I got this via the ARMv8 Programmer's Guide section 10.4.</p>
  
  <p>As far as I know, I need to set the VBAR_ELn register to point to the table, which I do as such:</p>
  
  <pre><code>ldr x0, =_vectors
  msr vbar_el1, x0
  </code></pre>
  
  <p>Is there anything else I am missing?
  Any help or point to a reference would be greatly appreciated.</p>