title: Simulating LDREX/STREX (load/store exclusive) in Cortex-M0
body: <p>In the Cortex-M3 instruction set, there exist a family of LDREX/STREX instructions such that if a location is read with an LDREX instruction, a following STREX instruction can write to that address only if the address is known to have been untouched.  Typically, the effect is that the STREX will succeed if no interrupts ("exceptions" in ARM parlance) have occurred since the LDREX, but fail otherwise.</p>
  
  <p>What's the most practical way to simulate such behavior in the Cortex M0?  I would like to write C code for the M3 and have it portable to the M0.  On the M3, one can say something like:</p>
  
  <pre>
  __inline void do_inc(unsigned int *dat)
  {
    while(__strex(__ldrex(dat)+1,dat)) {}
  }
  </pre>
  
  <p>to perform an atomic increment.  The only ways I can think of to achieve similar functionality on the Cortex-M0 would be to either:</p>
  
  <ol>
  <li>Have "ldrex" disable exceptions and have "strex" and "clrex" re-enable them, with the requirement that every "ldrex" must be followed soon thereafter by either a "strex" or "clrex".
  <li>Have "ldrex", "strex", and "clrex" be a very small routines in RAM, with one instruction of "ldrex" being patched to either "str r1,[r2]" or "mov r0,#1".  Have the "ldrex" routine plug a "str" instruction into the "strex" routine, and have the "clrex" routine plug "mov r0,#1" there.  Have all exceptions that might invalidate a "ldrex" sequence call "clrex".
  </ol>
  
  <p>Depending upon how the ldrex/strex functions are used, disabling interrupts might work reasonably, but it seems icky to change the semantics of "load-exclusive" so as to cause bad side-effects if it's abandoned.  The code-patching idea seems like it would achieve the desired semantics, but it seems clunky.</p>
  
  <p>(BTW, side question: I wonder why STREX on the M3 stores the success/failure indication to a register rather than simply setting a flag?  Its actual operation requires four extra bits in the opcode, requires that a register be available to hold the success/failure indication, and requires that a "cmp r0,#0" be used to determine if it succeeded.  Was it expected that compilers wouldn't be able to handle a STREX intrinsic sensibly if they didn't get the result in a register?  Getting Carry into a register takes two short instructions.)</p>