title: How to use throughout operator in systemverilog assertions
body: <p>Here is a spec:
   If signal <code>a</code> is asserted then it must be asserted till signal <code>b</code> is asserted and then it should de-assert on next clock edge.
   I'm reading through 16.9.9 of LRM (as well as <a href="http://www.testbench.in/AS_06_SEQUENCES.html" rel="nofollow">http://www.testbench.in/AS_06_SEQUENCES.html</a>) and the way I understood it, above mentioned spec can be written as</p>
  
  <pre><code>   property a2b_notA;
          @(posedge clk) ($rose (a) ##0 (a throughout b)) |=&gt; (~a);
     endproperty
     a_a2b_notA: assert property (a2b_notA);
  </code></pre>
  
  <p>However this fails immediately on second clock edge after starting, and I can't figure out why.</p>