title: how to create a generic procedure in VHDL?
body: <p>I have already written code for a generic Carry Look-Ahead Adder. but I can't convert this code to be a procedure in a package. can anyone help me do it?</p>
  
  <p>when I try to compile this code, it does not register <code>n</code> as a generic number.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Carry_Look_Ahead is
  
      Generic(n:integer:=4);
  
  Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
  B : in STD_LOGIC_VECTOR (n-1 downto 0);
  Cin : in STD_LOGIC;
  S : out STD_LOGIC_VECTOR (n-1 downto 0);
  Cout : out STD_LOGIC);
  end Carry_Look_Ahead;
  
  architecture Behavioral of Carry_Look_Ahead is
  
  begin
  
  process(A,B,Cin)
  
  variable ci :STD_LOGIC_VECTOR(n downto 0);
  variable P: STD_LOGIC_VECTOR(n-1 downto 0);
  variable G: STD_LOGIC_VECTOR(n-1 downto 0);
  variable si :STD_LOGIC_VECTOR(n-1 downto 0);     
            begin
         ci(0) := Cin;
  
  FOR i IN 0 TO n-1 LOOP 
  
    P(i) := A(i) xor B(i);
    G(i) := A(i) and B(i);
    ci(i+1) := G(i) or (P(i) and G(i));
    si(i) := P(i) xor ci(i);
  
   END LOOP;
      S&lt;=si;
      Cout&lt;=ci(n);
  end process;   
  
  end Behavioral;
  </code></pre>
  
  <p>This is the error I get when I try to compile this code:</p>
  
  <pre><code>Unknown identifier "n".
  </code></pre>