title: Systemverilog doesn't allow variable declarations after call to super.foo()?
body: <p>I'm running into a weird issue working with SystemVerilog on DVT. The code snippet in question looks something like this:</p>
  
  <pre><code>class parent;     
  
     int A;
     function void foo();
        A = 5;
     endfunction
  
  endclass
  
  
  class childA extends parent;
  
     function void foo();
        bit test_one; //Does not flag as a syntax error.
        super.foo();
        bit test_two; //Flags as error: Expected endfunction, found bit.
     endfunction      //Subsequently: Expected endclass, found endfunction
  
  endclass            //And lastly: Unexpected token: Endclass
  </code></pre>
  
  <p>As far as I know it is legal to call any hidden parent function using super. but this behavior is perplexing me. Can someone tell me if this is legal SV syntax? Or if not: What's the reasoning behind this?</p>