title: vhdl program not swapping integers
body: <p>The VHDL code below is a simple swap program. But it is not swapping the inputs <code>a</code> and <code>b</code>. I have given the transcript values in the comments.</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity vhdl_swap is
    port(a,b: inout integer);
  end vhdl_swap;
  
  architecture ar of vhdl_swap is
    signal s : std_logic;
  begin
  
    process(s)
      variable var : integer:=0;
    begin
      report "var is" &amp; integer'image(var); -- 0
      report "a is " &amp; integer'image(a);    -- 10 - (given value when simulated)
      report "b is " &amp; integer'image(b);  -- 20 - (given value when simulated)
  
      report "---------------------------";
  
      var := a;
      report "var is " &amp; integer'image(var);--var = 10 (assigned properly)
      a&lt;=b;
      report "a is " &amp; integer'image(a);-- a=10(same value but not assigned)
      b&lt;=var;
      report "b is " &amp; integer'image(b);-- b=20(same value but not assigned)
  
      report "-----------------------------------";
  
      report "a is " &amp; integer'image(a);--a=10
      report "b is " &amp; integer'image(b);--b=20
  
      --print()  
  
    end process;
  end;
  </code></pre>
  
  <p>There is something which acts in the statement <code>a&lt;=b</code>, but i don't know what prevents itself from assigning it. </p>