title: How to make while loop, with no definite bounds, synthesizable?
body: <p>I have this part of code which is not synthesizable because the number of times the loop will execute is not definite. I am a beginner with VHDL, how can I convert it to a synthesizable form?
  Note: I tried doing it with for loop too, along with break statement, but it is still not synthesizable due to the break statement.
  The code below is to calculate the value of ee such that the greatest common divisor of ee and Phi is 1.</p>
  
  <pre><code> library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  entity gcd11 is
  Port ( ee : out integer;
         Phi : in integer);
         --gc : out integer);
  end gcd11;
  
  architecture Behavioral of gcd11 is
  signal rem1,dd,dv,gc,temp: integer;
  begin
  process(temp,Phi,rem1,dd,dv,gc)
  begin
  gc&lt;=2;
  temp&lt;=1;
  while(gc/=1) loop
     temp&lt;=temp+1;
     rem1&lt;=1;
     if (temp&lt;Phi)then
         dd&lt;=Phi;
         dv&lt;=temp;
         elsif(temp&gt;=Phi) then
         dd&lt;=temp;
         dv&lt;=Phi;
     end if;
     while(rem1/=0) loop
         rem1&lt;= dd mod dv;
         dd&lt;=dv;
         gc&lt;=dv;
         dv&lt;=rem1;
     end loop;
  end loop;
  ee&lt;=temp;
  end process;
  end Behavioral;
  </code></pre>