title: Type of "variable" incompatible with type of "variable"
body: <p>I'm getting the following error: from my VHDL project:</p>
  <blockquote>
  <p>ERROR:HDLParsers:800 - &quot;C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd&quot; Line 90. Type of in_tilt is incompatible with type of tilt.</p>
  <p>ERROR:HDLParsers:800 - &quot;C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd&quot; Line 91. Type of in_pan is incompatible with type of pan.</p>
  <p>ERROR:HDLParsers:800 - &quot;C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd&quot; Line 92. Type of pwm_tilt is incompatible with type of pwm_tilt.</p>
  <p>ERROR:HDLParsers:800 - &quot;C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd&quot; Line 93. Type of pwm_pan is incompatible with type of pwm_pan.</p>
  </blockquote>
  <p>Here's the applicable code. I have a top level VHDL module with the following code:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_unsigned.all; 
  
  entity top is
  port (
    clk_in : in std_logic;
    pause : in std_logic;
    reset : in std_logic;
    switch : in std_logic_vector(3 downto 0);-----------------------------------------
    deb_in : in std_logic; ---from another switch
    deb_out : out std_logic; ---to test the debouncer
    pwm_pan : out std_logic_vector(7 downto 0);
    pwm_tilt : out std_logic_vector(7 downto 0)
  );
  end top;
  </code></pre>
  <p>the component declaration for PWM:</p>
  <pre><code>COMPONENT PWM
  PORT(
       clk_100 : in  std_logic;
       reset : IN  std_logic;
          in_tilt : in std_logic;
          in_pan : in std_logic;
       pwm_pan : OUT  std_logic;
          pwm_tilt : out std_logic
      );
  END COMPONENT;
  </code></pre>
  <p>Also the appropriate signals:</p>
  <pre><code>signal tilt : std_logic_vector (7 downto 0);
  signal pan : std_logic_vector (7 downto 0);
  </code></pre>
  <p>and then later on this code: (This is where my error is appearing.)</p>
  <pre><code>    u1: PWM PORT MAP (
       clk_100 =&gt; clk_100,
       reset =&gt; reset,
  --Line 90    in_tilt =&gt; tilt,
  --Line 91   in_pan =&gt; pan,          
  --Line 92    pwm_tilt =&gt; pwm_tilt,
  --Line 93    pwm_pan =&gt; pwm_pan
  );  
  </code></pre>
  <p>This is the code in the PWM VHDL module:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_unsigned.all; 
  
  entity PWM is
  Port ( clk_100 : in  STD_LOGIC;
         reset : in  STD_LOGIC;
            in_tilt : in std_logic_vector( 7 downto 0);
            in_pan : in std_logic_vector( 7 downto 0);
            pwm_tilt : out std_logic_vector (7 downto 0);
            pwm_pan : out std_logic_vector (7 downto 0)
            );
  end PWM;    
  </code></pre>
  <p>Any idea what's causing this error? I hope I've included all the relevant code. Thanks.</p>