title: verilog assignment compiler error
body: <p>I have a basic compiler error I am not able to figure out.
  Code:</p>
  
  <pre><code>module (input [127:0] in1,
          input [2:0] en);
  real a1;
  if(en==3'b001)
  begin
    a1=$bitstoreal(in1[31:0]);
  end
  </code></pre>
  
  <p>The error is :</p>
  
  <pre><code>Error: E:/Modeltech_pe_edu_10.0/examples/FloatingPt.v(20): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER or '#' or '('
  </code></pre>