title: How to fix indentation in Systemverilog source
body: <p>I am using systemverilog very often.<br>
  I am using <strong>UltraEdit</strong> as text editor. I use also VIM.<br>
  Sometimes I have to copy code from some other places and paste it into my code.<br>
  It may not be indented properly. It is a difficult task to indent it properly again.</p>
  
  <p>Can anybody suggest any method or tool to do it easily?</p>