title: Verilog - generate weighted random numbers
body: <p>I am trying to generate random single bits and this is simple as long as you want a normal randomization:</p>
  
  <pre><code>wire R;
  assign R = $random % 2;
  </code></pre>
  
  <p>What I am looking for is a sort of weighted probability like:</p>
  
  <pre><code>wire R;
  assign R = 60%(0) || 40%(1);
  </code></pre>
  
  <p>Forgive me if it is not conform to standard Verilog code, it is just to give an idea of what I want.
  Can anyone help me out?
  Thank you</p>