title: Fifo buffer in Verilog. generate always
body: <p>I'm tring to write universal fifo buffer.
  To make it universal i used code like this.</p>
  
  <pre><code>genvar i;
  generate
  for(i=0;i&lt;BusWidthIn;i=i+1) begin: i_buffin
    always @ (negedge clkin) begin
      if (!full)
        Buffer[wr_ptr+i] &lt;= datain[i*BitPerWord+BitPerWord-1:i*BitPerWord];
    end
  end
  endgenerate
  </code></pre>
  
  <p>In simulation it works properly, but in Quartus it gives
  Error (10028): Can't resolve multiple constant drivers for net "Buffer[30][6]" at fifo.v(33) and so on.</p>
  
  <p>All Code </p>
  
  <pre><code>module fifo_m(clkin,datain,clkout,dataout,full,empty);
  parameter BusWidthIn  = 3, //in 10*bits
            BusWidthOut = 1, //in 10*bits
            BufferLen   = 4, // in power of 2 , e.g. 4 will be 2^4=16 bytes
            BitPerWord  = 10;
  
  input                               clkin;
  input  [BusWidthIn*BitPerWord-1:0]  datain;
  input                               clkout;
  output [BusWidthOut*BitPerWord-1:0] dataout;
  output                              full;
  output                              empty;
  
  reg    [BusWidthOut*BitPerWord-1:0] dataout;
  reg    [BitPerWord-1:0]             Buffer [(1 &lt;&lt; BufferLen)-1  : 0];
  wire   [BusWidthIn*BitPerWord-1:0]  tbuff;
  reg    [BufferLen - 1 : 0]          rd_ptr, wr_ptr;
  wire   [BufferLen - 1 : 0]          cnt_buff;
  wire                                full;
  wire                                empty;
  
  assign cnt_buff = wr_ptr &gt; rd_ptr ? wr_ptr - rd_ptr  :  (1 &lt;&lt; BufferLen)  -  rd_ptr + wr_ptr;
  assign full     = cnt_buff &gt; (1 &lt;&lt; BufferLen) - BusWidthIn;
  assign empty    = cnt_buff &lt; BusWidthOut;
  
  initial  begin
  rd_ptr = 0;
  wr_ptr = 0;
  end
  
  genvar i;
  generate
  for(i=0;i&lt;BusWidthIn;i=i+1) begin: i_buffin
    always @ (negedge clkin) begin
      if (!full)
        Buffer[wr_ptr+i] &lt;= datain[i*BitPerWord+BitPerWord-1:i*BitPerWord];
    end
  end
  endgenerate
  
  always @ (negedge clkin)
  begin   
    if (!full)
      wr_ptr = wr_ptr + BusWidthIn;
  end
  
  genvar j;
  generate 
  for(j=0;j&lt;BusWidthOut;j=j+1) begin : i_buffout
    always @ (posedge clkout) begin
      dataout[j*BitPerWord+BitPerWord-1:j*BitPerWord] &lt;= Buffer[rd_ptr+j];
    end
  end
  endgenerate
  
  always @ (posedge clkout)
  begin
    if (!empty) 
      rd_ptr = rd_ptr + BusWidthOut;
  end
  
  endmodule
  </code></pre>
  
  <p>To solve this problem I must put for inside always, but how I can do it?</p>