title: Is there any recommended way to automate module port connection?
body: <p>I'm trying to understand or research about the best practices of ASIC design in verilog. I'm working on a medium size block with ~20 sub modules (each ~1000 lines of code). It's a painstaking job to manually instantiate all the sub-module and do port connection to create top level RTL. </p>
  
  <p>I want to write a script to automate this. As long as we can define the input/outputs of all the sub-modules and how each sub-modules are connected with each other, it shouldn't be super hard to auto-generate the top level. I don't have enough expertise in design automation though. I was wondering if anyone can give me some pointers about how to get started. </p>
  
  <ul>
  <li>Is there any open source tool to achieve what I'm trying to do? I didn't find any so far.</li>
  <li>Is there any standardize way to generate synthesizable code of this sort? </li>
  </ul>
  
  <p>I'll highly appreciate any sort of input or advice. </p>