title: Trying to access an interface inside interface from the env (SystemVerilog, OVM)
body: <p>Inside the build function of my env class trying to connect interfaces:</p>
  
  <pre><code>   virtual my_if  my_vif;
  
     for (int i = 0; i&lt;32; i++) begin
       _agent[i]._vif = my_vif._if[i];
     end
  </code></pre>
  
  <p>Inside my_if:</p>
  
  <pre><code>  interface my_if();
        if     _if[32]();
    endinterface :my_if
  </code></pre>
  
  <p>When running simulation I get this error:</p>
  
  <pre><code>Error-[MFNF] Member not found
  my_env.sv, 229 "this.my_vif." 
  Could not find member '_if' in interface 'my_if', at "my_if.sv", 1.
  </code></pre>
  
  <p>_if is also an interface with the next signals:</p>
  
  <pre><code>interface if(); 
   logic                   clk;
   logic                   rstn;
   logic [101:0] requests;
   logic [63:0]  dataOut;
  endinterface :if
  </code></pre>
  
  <p>The thing is that everything worked fine when the interface _if was not wrapped under the my_if interface.</p>