title: How to write an integer to stdout as hexadecimal in VHDL?
body: <p>I can print an <code>integer</code> as decimal to stdout with:</p>
  
  <pre><code>library std;
  use std.textio.all;
  
  entity min is
  end min;
  
  architecture behav of min is
  begin
      process is
          variable my_line : line;
      begin
          write(my_line, 16);
          writeline(output, my_line);
          wait;
      end process;
  end behav;
  </code></pre>
  
  <p>which outputs:</p>
  
  <pre><code>16
  </code></pre>
  
  <p>But how to output instead either:</p>
  
  <pre><code>10
  0x10
  </code></pre>