title: VHDL std_logic_vector conversion to signed and unsigned with numeric_std
body: <p>I have some doubts about the use of the conversions from <code>std_logic_vector</code> to <code>signed</code>/<code>unsigned</code>. I always use the conversion <code>signed(...)</code>, <code>unsigned(...)</code>, but when I try to use the conversions defined in the library <code>numeric_std</code> (<code>to_signed</code>, <code>to unsigned</code>), it doesn't work. Can someone explain to me why this happens? And why the conversion <code>unsigned()</code> and <code>signed()</code> works?</p>