title: How to use if statements in verilog
body: <p>I'm a total disaster at using verilog for implementing but this issue is walking on my nerves around an hour and I can't fix it!</p>
  
  <p>here's my code </p>
  
  <pre class="lang-bash prettyprint-override"><code>genvar i;
  assign eq=1; 
  assign gr=0;
  generate for(i=7 ; i&gt;=0 ; i=i-1)
          initial begin
          if(eq&amp;&amp;~gr)
              if (a[i]&amp;~b[i])
                initial begin
                 assign gr=1;
                 assign eq=0;
                end
              else if (~a[i]|b[i])
              initial begin
                assign gr=0;
  
      assign eq=0;
      end
      end
  endgenerate
  </code></pre>
  
  <p>the idea was to create some if statements so I could compare a[i] and b[i] if gr was 0 and eq was 1. 
  the algorithm cannot be changed cause it's an assignment and I have to work this way but I'm really eager to find where the problem is (verilog's error description is not helping at all)</p>