title: Understanding CPU L2 cache and L2_REJECT_BUSQ_THIS_CORE_ALL_INVALID
body: <p>Consider a Intel Core 2 architecture that has the following core topology:</p>
  
  <pre><code>Socket 0: ( 0 2 4 6 )
  Socket 1: ( 1 3 5 7 )
  </code></pre>
  
  <p>Each core has its own L1 cache; L2 cache group is like this: </p>
  
  <pre><code>( 0 2 ) ( 4 6 ) ( 1 3 ) ( 5 7 )
  </code></pre>
  
  <p>1
  . I observe that on some applications, the value of the performance counter L2_REJECT_BUSQ_THIS_CORE_ALL_INVALID is rather high. On those applications, the #L2 data cache miss is also high. Also the RESOURCE_STALLS_ROB_FULL is also high and be the main portion of total stall cycles.</p>
  
  <p>Is it correct to tell that, for example, core 0 finds a data in L2 and misses, then its L2 cache's bus controller broadcasts some messages to other L2's bus controllers to see if the data is in their L2s or not. However, due to the limit of bus bandwidth, there is high contention in the bus, somehow the others' bus queues keep being full then core 0 has to re-broadcast the look-up message many times? And if that's true then that's why the L2_REJECT_BUSQ_THIS_CORE_ALL_INVALID is so high? Or am I interpreting?</p>
  
  <p>2
  . Is the correct to assume that, putting aside the effect of cold misses, if I execute a loop that has 100 L2 data cache misses on a core, causing 200 L2_REJECT_BUSQ_THIS_CORE_ALL_INVALID, then executing a longer loop (for example with the number of iterations doubled) that has 200 L2 data cache misses will result 400 L2_REJECT_BUSQ_THIS_CORE_ALL_INVALID? If not, what would be the reason to cause unexpected non-linearity?</p>