title: Undefined output of Ring Counter Test waveform
body: <p>I have modeled 4 bit Ring Counter using D Flip Flop. </p>
  
  <p>The D flip flop is in separate file, included in my workspace. The D flip flop works correctly (gives correct output waveform).</p>
  
  <p>This is the code of ring counter:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  
  entity ring4counter is
      port (
          clk: std_logic;
          output: out std_logic_vector(3 downto 0));
  end ring4counter;
  
  architecture ring4counter_arch of ring4counter is
      component dff
      port (
          clk: std_logic;
          d: in std_logic;
          q: out std_logic;
          qbar: out std_logic);
      end component;
  
      signal temp:std_logic_vector(3 downto 0):=(others=&gt;'0');
  begin
      r1: dff port map(clk, temp(3), temp(0));
      r2: dff port map(clk, temp(0), temp(1));
      r3: dff port map(clk, temp(1), temp(2));
      r4: dff port map(clk, temp(2), temp(3));
      output &lt;= temp;
  end ring4counter_arch;
  </code></pre>
  
  <p>Here is the testbench code for Ring counter:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity ring4_tb is end ring4_tb ;
  
  architecture arch of ring4_tb is
      component tbc is
      port (
          clk: std_logic;
          output: out std_logic_vector(3 downto 0));
      end component ;
  
      component dff
      port (
          clk: std_logic;
          d: in std_logic;
          q: out std_logic;
          qbar: out std_logic);
      end component;
  
      constant period : time := 50 ns ;
  
      signal clk      : std_logic := '0' ;    
      signal done     : boolean := false ;
      signal output   : std_logic_vector(3 downto 0) ;
  
      shared variable cycle : natural := 0 ;
  
      signal temp:std_logic_vector(3 downto 0):=(others=&gt;'0');
  
  begin
  -- this is the unit under test
      u1: tbc
      port map(
          clk    =&gt; clk,
          output =&gt; output) ;
  
      clkprocess: process(done, clk)
      begin
      if (not done) then
          if (clk = '1') then
          cycle := cycle + 1 ;
          end if ;
          clk &lt;= not clk after period / 2 ;
      end if ;
      end process ;
  
      r1: dff port map(clk, temp(3), temp(0));
      r2: dff port map(clk, temp(0), temp(1));
      r3: dff port map(clk, temp(1), temp(2));
      r4: dff port map(clk, temp(2), temp(3));
      output &lt;= temp;
  
      testbench: process
      begin
      wait until (clk = '0') ;
      temp &lt;= "1000";
      wait for period*4 ;
  
      done &lt;= true ;      -- force the clock process to shutdown
      wait ;          -- this waits forever
      end process ;
  end arch ;
  </code></pre>
  
  <p>But the waveform for 'output' is 'U' for all bits.
  Where am I going wrong?</p>