title: ARM SWP instruction and cache
body: <p>I've been reading about synchronisation methods in ARM processors. I came across some question regarding this area. If I'm using SWP instruction I need to give some address in memory as third parameter. But if the system is multicore ARM - what in case when the contents of this memory address is cached in other processor's cache? </p>
  
  <p>Will the cache be invalidated at this case or something else will happen? Anyone can explain it?</p>