title: Why the depth of Ram or FIFO is always 2 times of the width of address in RTL design?
body: <p>I saw lots of examples of ram and FIFO design, the depth of memory is always 2 time of the width of address:</p>
  
  <pre><code>parameter addr_width=4;
  parameter ram_depth=1&lt;&lt; addr_width;
  </code></pre>
  
  <p>Why? If the width of the address equal to 4, then the depth should have 16 possibilities right? why use 2*4?
  Thanks in advance. </p>