title: Graph/schematic generator for VHDL
body: <p>I have a VHDL project that consists of a top level module containing other modules interconnected in various ways (and some of these modules are, themselves, containers for other modules).</p>
  
  <p>Is there a utility that can generate a schematic illustrating the relationships between the modules? I'm not concerned with configuration details or architecture, just the inputs, outputs and nesting for each module in my project.</p>