title: How to write case insensitive Lex pattern rules?
body: <p>Structure of my file is,</p>
  
  <pre><code>`pragma TOKEN1_NAME TOKEN1_VALUE
  `pragma TOKEN2_NAME TOKEN2_VALUE
  `pragma TOKEN3_NAME TOKEN3_VALUE
  `pragma TOKEN4_NAME TOKEN4_VALUE
   TEXT{
  
   // A valid VHDL or verilog
   }
  `pragma TOKEN2_NAME TOKEN2_VALUE
   TEXT{
  
     // VHDL or verilog
   }
  </code></pre>
  
  <p>Since i am dealing with both Verilog and VHDL.I need to restructure my token names by taking into mind that VHDL is case insensitive.
  I want to use single parser for both the cases.What can be the most efficient way for the same ?
  Do flex support some sort of functionality to allow case insensitive pattern match and we can later check if token names are sanitized(having all small letters),if the format of the file is Verilog ?</p>