title: Does Verilog `ifdef respond to environment variables?
body: <p>If I have the following Verilog code:</p>
  
  <pre><code>//test.v
  
  `ifdef V1
  {code block 1}
  `else
  {code block 2}
  `endif
  </code></pre>
  
  <p>can I "steer" the conditional from the command line, using standard environment variable definition syntax?
  For instance, would this cause {code block 1} to execute?:</p>
  
  <pre><code>$ V1=1 &lt;simulator&gt; test.v
  </code></pre>