title: Pattern target in Makefile not recognized?
body: <p>I don't understand why the pattern target <code>%.o: %.cpp</code> ist not recognized by the Makefile below. Line 42 should invoke the rule at line 58.</p>
  
  <p>The purpose is to create a Makefile to generate different executables out of the same code.</p>
  
  <p>Further the Makefile shall (in future) take into account to rebuild the code if header-files were changed (dependencies). But this is no question at this point.</p>
  
  <pre><code>.SECONDEXPANSION:
  
  SUFFIXES += .d
  
  MD := mkdir
  MD_FLAGS := -p
  
  RM := rm
  RM_FLAGS := -rf
  
  EC := echo
  
  SRC_DIR := src
  # SRC_FILES - target specific
  
  OBJ_DIR := obj
  # OBJ_FILES - target specific
  
  DEP_DIR := dep
  # DEP_FILES - target specific
  
  BUILD_DIR := build
  
  CC := clang++
  CC_FLAGS := -c -std=c++11 -I $(SRC_DIR) -O3
  
  LD := clang++
  # LD_FLAGS - target specific
  
  .PHONY: all
  all: first
  
  .PHONY: first
  first: LD_FLAGS :=
  
  first: SRC_FILES :=\
          $(SRC_DIR)/executables/first.cpp\
          $(SRC_DIR)/factory/milk.cpp
  
  first: obj
  
  first: $(OBJ_FILES)
          @echo $(OBJ_FILES)
          @echo making $@
  
  first: dep
  
  first: lnk
  
  .PHONY: obj
  obj:
          $(eval OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES)))
  
  .PHONY: dep
  dep:
          $(eval DEP_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(DEP_DIR)/%.dep, $(SRC_FILES)))
  
  %.o: %.cpp
          @$(EC) "Begin compiling "$@
          @$(MD) $(MD_FLAGS) $(dir $@)
          @$(CC) $(CC_FLAGS) $&lt; -o $@
          @$(EC) "Done compiling "$@
  
  .PHONY: lnk
  lnk: $(DEP_FILES) $(OBJ_FILES) $(SRC_FILES)
          @$(EC) $(SRC_FILES)
          @$(EC) $(OBJ_FILES)
          @$(EC) $(DEP_FILES)
          @$(EC) "Begin linking "$@
          @$(MD) $(MD_FLAGS) $(DEP_DIR) $(BUILD_DIR)
          @$(LD) -o $(BUILD_DIR)/$@ $(OBJ_FILES) $(LD_FLAGS)
          @$(EC) "Done linking "$@
  
  .PHONY: clean
  clean:
          @$(EC) "Begin cleaning"
          @$(RM) $(RM_FLAGS) $(DEP_DIR) $(OBJ_DIR) $(BUILD_DIR)
          @$(EC) "Done cleaning"
  </code></pre>
  
  <p>A snippet of a debug output (<code>make -d</code>) is not a big help I guess but for completion...</p>
  
  <pre><code>Updating goal targets....
  Considering target file 'all'.
   File 'all' does not exist.
    Considering target file 'first'.
     File 'first' does not exist.
      Considering target file 'obj'.
       File 'obj' does not exist.
       Finished prerequisites of target file 'obj'.
      Must remake target 'obj'.
      Successfully remade target file 'obj'.
      Considering target file 'dep'.
       File 'dep' does not exist.
       Finished prerequisites of target file 'dep'.
      Must remake target 'dep'.
      Successfully remade target file 'dep'.
      Considering target file 'lnk'.
       File 'lnk' does not exist.
       Finished prerequisites of target file 'lnk'.
      Must remake target 'lnk'.
  </code></pre>
  
  <h1><b>Update 1</b></h1>
  
  <p>I've updated the code as it now uses <code>MAKECMDGOALS</code> to build several executables (e.g. <code>first</code>,<code>second</code>) from subsets of a biger set.</p>
  
  <p>No it works as expected but the target all is broken. It's clear to me why but I don't have a solution right now.</p>
  
  <pre><code>.SECONDEXPANSION:
  
  SUFFIXES += .d
  
  MD := mkdir
  MD_FLAGS := -p
  
  RM := rm
  RM_FLAGS := -rf
  
  EC := echo
  
  SRC_DIR := src
  
  ifeq ($(filter first, $(MAKECMDGOALS)), first)
          SRC_FILES :=\
          $(SRC_DIR)/executables/first.cpp\
          $(SRC_DIR)/factory/milk.cpp
  endif
  
  ifeq ($(filter second, $(MAKECMDGOALS)), second)
          SRC_FILES :=\
          $(SRC_DIR)/executables/second.cpp\
          $(SRC_DIR)/factory/milk.cpp\
          $(SRC_DIR)/factory/cream.cpp
  endif
  
  OBJ_DIR := obj
  
  OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES))
  
  DEP_DIR := dep
  
  DEP_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(DEP_DIR)/%.dep, $(SRC_FILES))
  
  BUILD_DIR := build
  
  CC := clang++
  
  CC_FLAGS := -c -std=c++11 -I $(SRC_DIR) -O3
  
  LD := clang++
  
  ifeq ($(filter first, $(MAKECMDGOALS)), first)
          LD_FLAGS :=
  endif
  
  ifeq ($(filter second, $(MAKECMDGOALS)), second)
          LD_FLAGS :=
  endif
  
  .PHONY: all
  all: first second
  
  .PHONY: first
  first: $(OBJ_FILES) lnk
  
  .PHONY: second
  second: $(OBJ_FILES) lnk
  
  %.o: %.cpp
          @$(EC) "Begin compiling "$@
          @$(MD) $(MD_FLAGS) $(dir $@)
          @$(CC) $(CC_FLAGS) $&lt; -o $@
          @$(EC) "Done compiling "$@
  
  .PHONY: lnk
  lnk: $(OBJ_FILES)
          @$(EC) "Begin linking "$@
          @$(MD) $(MD_FLAGS) $(DEP_DIR) $(BUILD_DIR)
          @$(LD) -o $(BUILD_DIR)/$@ $(OBJ_FILES) $(LD_FLAGS)
          @$(EC) "Done linking "$@
  
  .PHONY: clean
  clean:
          @$(EC) "Begin cleaning"
          @$(RM) $(RM_FLAGS) $(DEP_DIR) $(OBJ_DIR) $(BUILD_DIR)
          @$(EC) "Done cleaning"
  </code></pre>
  
  <h1><b>Update 2</b></h1>
  
  <p>I had to change the targets <code>first</code> and <code>second</code>, a copy-paste error. Here's the working example:</p>
  
  <pre><code>MD := mkdir
  MD_FLAGS := -p
  
  RM := rm
  RM_FLAGS := -rf
  
  EC := echo
  
  SRC_DIR := src
  
  ifeq ($(filter first, $(MAKECMDGOALS)), first)
          SRC_FILES :=\
          $(SRC_DIR)/executables/first.cpp\
          $(SRC_DIR)/factories/milk.cpp
  endif
  
  ifeq ($(filter second, $(MAKECMDGOALS)), second)
          SRC_FILES :=\
          $(SRC_DIR)/executables/second.cpp\
          $(SRC_DIR)/factories/milk.cpp\
          $(SRC_DIR)/factories/cream.cpp
  endif
  
  OBJ_DIR := obj
  
  OBJ_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRC_FILES))
  
  DEP_DIR := dep
  
  DEP_FILES := $(patsubst $(SRC_DIR)/%.cpp, $(DEP_DIR)/%.dep, $(SRC_FILES))
  
  BUILD_DIR := build
  
  CC := clang++
  
  CC_FLAGS := -c -std=c++11 -I $(SRC_DIR) -O3
  
  LD := clang++
  
  ifeq ($(filter first, $(MAKECMDGOALS)), first)
          LD_FLAGS :=
          LD_FILE := first
  endif
  
  ifeq ($(filter second, $(MAKECMDGOALS)), second)
          LD_FLAGS :=
          LD_FILE := second
  endif
  
  .PHONY: all
  all:
          @$(MAKE) $(MAKEFLAGS) first
          @$(MAKE) $(MAKEFLAGS) second
  
  .PHONY: first
  first: $(OBJ_FILES) lnk
  
  .PHONY: second
  second: $(OBJ_FILES) lnk
  
  $(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
          @$(EC) "Begin compiling "$@
          @$(MD) $(MD_FLAGS) $(dir $@)
          @$(CC) $(CC_FLAGS) $&lt; -o $@
          @$(EC) "Done compiling "$@
  
  .PHONY: lnk
  lnk: $(OBJ_FILES)
          @$(EC) "Begin linking "$(LD_FILE)
          @$(MD) $(MD_FLAGS) $(DEP_DIR) $(BUILD_DIR)
          @$(LD) -o $(BUILD_DIR)/$(LD_FILE) $(OBJ_FILES) $(LD_FLAGS)
          @$(EC) "Done linking "$(LD_FILE)
  
  .PHONY: clean
  clean:
          @$(EC) "Begin cleaning"
          @$(RM) $(RM_FLAGS) $(DEP_DIR) $(OBJ_DIR) $(BUILD_DIR)
          @$(EC) "Done cleaning"
  </code></pre>