title: VCD Dump of only a sub part of the design via modelsim
body: <p>I have a big design that includes a test-bench, some testing circuit and the circuit under test itself.
  I use modelsim to simulate the design and I want to have a dump of the simulation. I was suggested to generate the dump using the command:</p>
  
  <pre><code>vcd file myvcd1.vcd
  vcd add -r /sim_minimips/*
  </code></pre>
  
  <p>it seams to work but what i would like is to generate the dump only for the circuit under test.</p>
  
  <p>i tried to use the same command in specifying just the name of the file i would like to be taken in consideration:</p>
  
  <pre><code>vcd file myvcd2.vcd
  vcd add -r /minimips/*
  </code></pre>
  
  <p>but the following error was generated:</p>
  
  <pre><code>Error vsim 3561 No object matching minimips
  </code></pre>
  
  <p>I do not understand the error and i am not sure even if this is the correct procedure to isolate a subpart.</p>
  
  <p>does anyone knows how to do or knows where could i get a decent simply tutorial about this Value Change Dump?</p>
  
  <p>I attach my test bench entity:</p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  
  library std;
  use std.textio.all;
  
  library work;
  use work.pack_mips.all;
  
  entity sim_minimips is
  end;
  
  architecture bench of sim_minimips is
  
    component minimips is
    port (
        clock    : in std_logic;
        reset    : in std_logic;
  
        ram_req  : out std_logic;
        ram_adr  : out bus32;
        ram_r_w  : out std_logic;
        ram_data : inout bus32;
        ram_ack  : in std_logic;
  
        it_mat   : in std_logic
    );
    end component;
  
  
    component ram is
      generic (mem_size : natural := 256;
               latency : time := 10 ns);
      port(
          req        : in std_logic;
          adr        : in bus32;
          data_inout : inout bus32;
          r_w        : in std_logic;
          ready      : out std_logic
    );
    end component;
  
    component rom is
    generic (mem_size : natural := 256;
             start : natural := 0;
             latency : time := 10 ns);
    port(
            adr : in bus32;
            donnee : out bus32;
            ack : out std_logic;
            load : in std_logic;
            fname : in string
    );
    end component;
  
    signal clock : std_logic := '0';
    signal reset : std_logic;
  
    signal it_mat : std_logic := '0';
  
    -- Connexion with the code memory
    signal load : std_logic;
    signal fichier : string(1 to 7);
  
    -- Connexion with the Ram
    signal ram_req : std_logic;
    signal ram_adr : bus32;
    signal ram_r_w : std_logic;
    signal ram_data : bus32;
    signal ram_rdy : std_logic;
  
  begin
  
      U_minimips : minimips port map (
          clock =&gt; clock,
          reset =&gt; reset,
          ram_req =&gt; ram_req,
          ram_adr =&gt; ram_adr,
          ram_r_w =&gt; ram_r_w,
          ram_data =&gt; ram_data,
          ram_ack =&gt; ram_rdy,
          it_mat =&gt; it_mat
      );
  
      U_ram : ram port map (
          req =&gt; ram_req,
          adr =&gt; ram_adr,
          data_inout =&gt; ram_data,
          r_w =&gt; ram_r_w,
          ready =&gt; ram_rdy
      );
  
      U_rom : rom port map (
          adr =&gt; ram_adr,
          donnee =&gt; ram_data,
          ack =&gt; ram_rdy,
          load =&gt; load,
          fname =&gt; fichier
      );
  
      clock &lt;= not clock after 20 ns;
      reset &lt;= '0', '1' after 5 ns, '0' after 70 ns;
      ram_data &lt;= (others =&gt; 'L');
  
      process
          variable command : line;
          variable nomfichier : string(1 to 3);
      begin
          write (output, "Enter the filename : ");
          readline(input, command);
          read(command, nomfichier);
  
          fichier &lt;= nomfichier &amp; ".bin";
  
          load &lt;= '1';
          wait;
      end process;
  
      -- Memory Mapping
      -- 0000 - 00FF      ROM
  
      process (ram_adr, ram_r_w, ram_data)
      begin -- Emulation of an I/O controller
          ram_data &lt;= (others =&gt; 'Z');
  
          case ram_adr is
              when X"00001000" =&gt; -- program an interrupt after 1000ns
                                  it_mat &lt;= '1' after 1000 ns;
                                  ram_rdy &lt;= '1' after 5 ns;
              when X"00001001" =&gt; -- clear interrupt line on cpu
                                  it_mat &lt;= '0';
                                  ram_data &lt;= X"FFFFFFFF";
                                  ram_rdy &lt;= '1' after 5 ns;
              when others      =&gt; ram_rdy &lt;= 'L';
          end case;
      end process;
  
  end bench;
  </code></pre>
  
  <p>Cheers,
  Ste</p>