title: assign data(i) into std_logic_vector(0 downto 0) in vhdl
body: <p>I have the following problem:</p>
  
  <p>My code has this constant value</p>
  
  <pre><code>constant source_vector : std_logic_vector(7 downto 0) := "1011000";
  </code></pre>
  
  <p>This value needs to be fed into a signal of type std_logic_vector, bit by bit. The problem is that the destination vector has a size defined in a constant. For the test, I am using size 1.</p>
  
  <pre><code>constant k : integer := 1;
  dest_vector : in std_logic_vector(k-1 downto 0);
  </code></pre>
  
  <p>When I try to assign the first bit:</p>
  
  <pre><code>dest_vector &lt;= std_logic_vector(to_unsigned(source_vector(0), k));
  </code></pre>
  
  <p>I got this error:
  ERROR: [VRFC 10-925] indexed name is not a natural</p>
  
  <p>I have tried several things, but no luck. Perhaps I am missing something... Any advice here?</p>