title: integer comparison doesn't work in if statement (vhdl)
body: <p>What is the error in the following code? </p>
  
  <p>In the testbench <code>x</code> is set to <code>"00001111"</code>, yet the else branch is executed (in the simulation all of <code>y</code>'s bits are set to high impedance state, but <code>y</code> should equal <code>x</code>). I'm using <code>XILNX ISE Design Suite</code> and <code>ISim</code> as simulation environment. Thanks in advance.</p>
  
  <pre><code>entity test is
      Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);
             y : out  STD_LOGIC_VECTOR (7 downto 0));
  end test;
  
  architecture Behavioral of test is
  
  signal tmp : integer;
  
  begin
  
  process(x)
  begin
  tmp &lt;= to_integer(unsigned(x(3 downto 0)));
  if tmp = 15 then
      y &lt;= std_logic_vector(to_unsigned(tmp, 8));
  else
      y &lt;= "ZZZZZZZZ";
  end if;
  end process;
  
  end Behavioral;
  </code></pre>