title: How to write a verilog testbench to loop through 4 inputs?
body: <p>I have to create the verilog code and testbench for this schematic.</p>
  
  <p><img src="https://puu.sh/c0JTS/e6ff3707c6.png" alt="problem"></p>
  
  <p>I have the design for it here.</p>
  
  <pre><code>module prob1(input wire a,b,c,d, output wire out);
      assign out = (a||d)&amp;&amp;(!d&amp;&amp;b&amp;&amp;c);
  endmodule
  </code></pre>
  
  <p>Here is what I have for the testbench so far.</p>
  
  <pre><code>module prob1_tb();
      reg a,b,c,d;
      wire out;
  
      prob1 prob1_test(a,b,c,d, out);
  
      initial begin
          for(i=0; i=16; i=i+1)
              &lt;loop code here&gt;
          end
      end
  endmodule
  </code></pre>
  
  <p>Now I guess the part I am having issue with is how can I convert that number into those 4 inputs that are being used in the schematic. Or is there a better way to go about doing this?</p>