title: Making a clock divider
body: <p>I found this code in how to make a clock divider. I have a general understanding on how to make a divider using counters but i not sure what this code is doing and why its doing it.</p>
  
  <pre><code>entity clkdiv is
      Port ( mclk : in  STD_LOGIC;
             clr : in  STD_LOGIC;
             clk190 : out  STD_LOGIC;
             clk48 : out  STD_LOGIC);
  end clkdiv;
  
  architecture clkdiv of clkdiv is
  signal q: std_logic_vector(23 downto 0);
  begin
      --clock divider
      process(mclk,clr)
      begin   
          if clr ='1' then
              q &lt;= X"000000";
          elsif mclk'event and mclk = '1' then
              q &lt;= q+1;
          end if;
      end process;
      clk48 &lt;= q(19);
      clk190 &lt;= q(17);
  
  end clkdiv;
  </code></pre>
  
  <p>I know that the example is on the basis 2 board, the input clock is 50MHz. This code is supposed to create a 48hz clock signal and 190hz clock signal. </p>