title: Active VHDL: Design Unit Declaration Expected
body: <p>I am trying to figure out what is wrong with this code below.  Every other file works however when I tried to compile this file I get</p>
  
  <pre><code># Error: COMP96_0019: file_io.vhd : (30, 6): Keyword 'begin' expected.
  # Error: COMP96_0016: file_io.vhd : (30, 11): Design unit declaration expected.
  </code></pre>
  
  <p>The error is for the segment shown below.</p>
  
  <pre><code>data : in std_logic_vector(63 downto 0);
  initial_addr:in std_logic_vector(3 downto 0);
  rst_iar_bar:in std_logic; 
  clk:in std_logic;
  wb_data:out std_logic_vector(63 downto 0);
  
  ----fetch
  instruction:out std_logic_vector(15 downto 0);
  
  ----IDRD
  idrd_srcA,idrd_srcB,idrd_data:out std_logic_vector(63 downto 0);
  idrd_opcode,idrd_rd_addr,idrd_rs2_addr:out std_logic_vector(3 downto 0);
  
  idrd_addorsub,idrd_lv,idrd_alu_op,idrd_B_select,idrd_saturate,idrd_reg_wr:out std_logic;
  idrd_sel: out std_logic_vector(6 downto 0);
  
  ----IFID
  ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,ifid_rd_addr:out std_logic_vector(3 downto 0)   
  </code></pre>
  
  <p>Below is the full file, I need to figure out how to fix this error!  I am following an example that was created by my professor however it is not working properly for me.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.all; 
  use std.textio.all;     
  use ieee.numeric_std.all;  
  use txt_util.all;
  
  entity fileio is
  end fileio;
  
  
  architecture fileio of fileio is
  signal data:std_logic_vector(63 downto 0);
  signal initial_addr,idrd_rs2_addr,idrd_rd_addr,idrd_opcode,ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,
  ifid_rd_addr:std_logic_vector(3 downto 0);
  signal reset: std_logic;    -- 
  
  signal Instr_out: std_logic_vector(15 downto 0);
  
  
  signal clk: std_logic;  --  
  signal idrd_addorsub,idrd_lv,idrd_alu_op,idrd_saturate,idrd_B_select,idrd_reg_wr:std_logic;
  signal instruction_in:std_logic_vector(15 downto 0);
  signal wb_data,idrd_srcA,idrd_srcB,idrd_data: std_logic_vector(63 downto 0); 
  signal idrd_sel:std_logic_vector(6 downto 0);
  signal instruction:std_logic_vector(15 downto 0);
  constant period:time:=20ns;     
  
  
      data : in std_logic_vector(63 downto 0);
      initial_addr:in std_logic_vector(3 downto 0);
      rst_iar_bar:in std_logic; 
      clk:in std_logic;
      wb_data:out std_logic_vector(63 downto 0);
  
      ----fetch
      instruction:out std_logic_vector(15 downto 0);
  
      ----IDRD
      idrd_srcA,idrd_srcB,idrd_data:out std_logic_vector(63 downto 0);
      idrd_opcode,idrd_rd_addr,idrd_rs2_addr:out std_logic_vector(3 downto 0);
      idrd_addorsub,idrd_lv,idrd_alu_op,idrd_B_select,idrd_saturate,idrd_reg_wr:out std_logic;
      idrd_sel: out std_logic_vector(6 downto 0);
  
      ----IFID
      ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,ifid_rd_addr:out std_logic_vector(3 downto 0);
  
  
  
  
  begin                 
  uut:cellliteunit 
  port map(
      instruction=&gt;instruction,
      idrd_srcA=&gt;idrd_srcA,
      idrd_srcB=&gt;idrd_srcB,
      idrd_data=&gt;idrd_data,
      idrd_opcode=&gt;idrd_opcode,
      idrd_rd_addr=&gt;idrd_rd_addr, 
      idrd_rs2_addr=&gt;idrd_rs2_addr,
      idrd_addorsub=&gt;idrd_addorsub,idrd_lv=&gt;idrd_lv,idrd_alu_op=&gt;idrd_alu_op,
      idrd_B_select=&gt;idrd_B_select,idrd_saturate=&gt;idrd_saturate,idrd_reg_wr=&gt;idrd_reg_wr, 
      idrd_sel=&gt;idrd_sel,
      ifid_opcode=&gt;ifid_opcode,ifid_rs1_addr=&gt;ifid_rs1_addr,
      ifid_rs2_addr=&gt;ifid_rs2_addr,ifid_rd_addr=&gt;ifid_rd_addr,
      data=&gt;data,
      initial_addr=&gt;initial_addr,
      rst_iar_bar=&gt;rst_iar_bar,
      clk=&gt;clk,
      wb_data=&gt;wb_data
      );       
  
  a:process       
  begin
      data&lt;=X"FFFFFFFFFFFFFFFF"; 
      wait for 6*period;
  
      data&lt;=X"0000000100000000";
  
      wait;
  end process;
  
  b:process
  begin    
      initial_addr&lt;=X"0";
  
      rst_iar_bar&lt;='0', '1' after period;
      wait;
  end process b;
  
  clock:process
  begin
      clk&lt;='1';
      for i in 0 to 100 loop
          wait for period;
          clk&lt;=not clk;
      end loop;
      wait;
  end process clock;  
  
  
  write_p:process
      file outfile:text;          
      variable r:string(1 to 5);
      variable s:string(1 to 5);
      variable t:string(1 to 5);
  
  begin                
      for j in 1 to 15 loop
          wait for 2*period;
          case instruction(15 downto 12) is
              ...
              ...
              ...
          end case;
      end loop;
  end fileio;
  </code></pre>