title: parameter based typedef in system Verilog
body: <p>I would like to have parameterized typedef struct in System Verilog.</p>
  <p>For example, Instead of separate definitions for 8 and 16 bits complex data, can I have parameterized typedef for complex data type?</p>
  <pre><code>typedef struct {logic [7:0] i, q;} complex_datatype_8b;
  typedef struct {logic [15:0] i, q;} complex_datatype_16b;
  
  </code></pre>