title: How to pass array structure between two verilog modules
body: <p>I am trying to pass a array structure as reg [0:31]instructionmem[0:31] between two modules.</p>
  
  <p>I coded it as follows : </p>
  
  <p>Module No 1: </p>
  
  <pre><code>       module module1(instructionmem);
              output reg [0:31]instructionmem[0:31];
              ------------------
              ----lines of code---
  
              ---------------
         endmodule 
  </code></pre>
  
  <p>Module No 2:</p>
  
  <pre><code>         module module2(instructionmem);
             input [0:31]instructionmem[0:31];
             --------------------------------
             -----line of code---------------
             -------------------------------
             endmodule
  </code></pre>
  
  <p>Testbench:</p>
  
  <pre><code>     module test_bench();
       wire [0:31]instructionmem[0:31];
  
       module1 m1(instructionmem);
       module2 m2(instructionmem);
       endmodule
  </code></pre>
  
  <p>I am getting errors for this implementation. So how can we send such array structures ?</p>