title: VHDL sequencer: incrementing output sigals in FSM
body: <p>I am working on a Sequencer and I can not figure out how to increment some output signals. In state 1 (<code>S1</code>) I want to increment the <code>ram_add_wr</code> (on every clock cycle).</p>
  
  <pre><code>clocked_process:PROCESS(clk,rst)
      VARIABLE count: INTEGER RANGE 0 TO 32;
  BEGIN  
        IF (rst = '0') THEN  
            pr_state &lt;= idle; 
            count := 0;
        ELSIF (clk'event AND clk='1') THEN    
            count := count+1;
            IF (count&gt;=timer) THEN
                pr_state &lt;= nx_state;
                count := 0;
            END IF;
        END IF;
  END PROCESS;        
  
  PROCESS(pr_state, en) 
  BEGIN         
      CASE pr_state IS
          WHEN idle =&gt;  
          timer &lt;= 1;
              IF (en = '1') THEN
                  sig_ram_add_wr &lt;= "00000";  
                  nx_state &lt;= s1;  
              ELSE
                  nx_state &lt;= idle;
                  sig_ram_add_wr &lt;= "00000";  
      END IF;
  
          WHEN s1 =&gt;           
          timer &lt;= 32;
              IF (en ='1') THEN
          --timer &lt;= 1;
  </code></pre>