title: Continuous assignment verilog
body: <p>-This code is written in verilog using Modelsim 10.2d.The errors below indicate there is some problem with {cout,l3} assignment.</p>
  
  <pre><code>module alu(a,b,bin,cin,op,cout,res);
  input [31:0] a,b;
  input [1:0] op;
  input bin,cin;
  reg [31:0] l1,l2,l3;
  output cout;
  output [31:0] res;
  
  assign l1 = a &amp; b;
  assign l2 = a | b;
  
  initial
  if(bin == 1'b0)
    assign {cout,l3} = a + b + cin;
  else
    assign {cout,l3} = a - b + cin;
  
  mux4to1(l1,l2,l3,op,res);
  endmodule
  
  Error-
  v(14): LHS in procedural continuous assignment may not be a net: cout.
  v(16): LHS in procedural continuous assignment may not be a net: cout.
  </code></pre>