title: Creating a frequency divider in VHDL
body: <p>MAJOR EDIT:</p>
  
  <p>Problem was solved after reading Will Dean's comment. The original question is below the revised code:</p>
  
  <pre><code>-- REVISED CODE (NOW WORKS)
  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  
  entity CLOCK_DIVIDER is
      port(
          reset   :   in std_logic;
          clk :   in std_logic;
          half_clk    :   out std_logic
          );
  end CLOCK_DIVIDER;
  
  
  architecture CLOCK_DIVIDER of CLOCK_DIVIDER is
  signal tick : std_logic;
  
  begin
  
      process(clk, reset)
      begin
          if reset = '1' then
              tick &lt;= '0';
          elsif clk = '1' and clk'EVENT then
              if tick = '0' then
                  tick &lt;= '1';
              elsif tick = '1' then
                  tick &lt;= '0';
              end if;
          end if;
      end process;
  
      process(tick)
      begin
          half_clk &lt;= tick;
      end process
  
  end CLOCK_DIVIDER;
  </code></pre>
  
  <p>The synthesized logic block of the revised code is a single asynchronous-reset DFF that takes half_clk as output and inverted half_clk as input, which means the value of half_clk changes on every rising edge of clk.</p>
  
  <p>Thanks, Will Dean :)</p>
  
  <p>==== ==== ==== ==== ====</p>
  
  <p>Original question below:</p>
  
  <p>==== ==== ==== ==== ====</p>
  
  <p>I need a simple clock divider (just divide-by-two) and instead of usinga template, I thought I'd try to write one myself to keep in training.</p>
  
  <p>Unfortunately, the synthesized logic block does not appear to work - I present the logic block and the code (which I really think ought to work), in that order.</p>
  
  <p><a href="http://img808.imageshack.us/img808/3333/unledly.png" rel="nofollow noreferrer">logic block http://img808.imageshack.us/img808/3333/unledly.png</a></p>
  
  <p>What I'm really wondering is what the devil is up with the "tick" DFF - it apparently takes its input from the mux-selector which is... Yeah.</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  
  entity CLOCK_DIVIDER is
      port(
          reset   :   in std_logic;
          clk :   in std_logic;
          half_clk    :   out std_logic
          );
  end CLOCK_DIVIDER;
  
  
  architecture CLOCK_DIVIDER of CLOCK_DIVIDER is
  signal tick : std_logic;
  
  begin
      process(clk, reset)
      begin
          if reset = '1' then
              half_clk &lt;= '0';
              tick &lt;= '0';
          elsif clk = '1' and clk'EVENT then
              if tick = '0' then
                  half_clk &lt;= '0';
                  tick &lt;= '1';
              elsif tick = '1' then
                  half_clk &lt;= '1';
                  tick &lt;= '0';
              end if;
          end if;
      end process;
  end CLOCK_DIVIDER;
  </code></pre>
  
  <p>I'm sure the error in the code is obvious but I've been staring myself blind trying to find it.</p>