title: Detecting rising edge synchronization of 2 different clocks
body: <p>How do you detect rising edge synchronization of 2 different clocks(different frequencies) in VHDL programming using Xilinx software?</p>
  
  <p>There is a main clock of frequency 31.845 Mhz , and another clock of frequency 29.972 Mhz. So the basic aim is to trigger an action when there is synchronization between the rising edges of 2 clocks. We tried implementing it using flipflops but we could achieve only Level synchronization, not Edge sync. </p>
  
  <p>And we cannot compare the rising edges of 2 different clocks in statements like <code>IF</code> and <code>WAIT</code> in vhdl, So that is out of question.</p>
  
  <p>We are trying to count pulses using a counter. For that, we need to stop the count whenever edge matching takes place. We are trying to implement a method called 'Vernier Interpolation'.  </p>
  
  <ol>
  <li><p>Initially, we used the following statement code, but since rising edges of 2 different clocks (clk0, clk1) cannot be compared in an <code>IF</code> statement, we had to drop it.</p>
  
  <p><code>if(rising_edge(clk0)=rising_edge(clk1)) then wait;</code></p></li>
  <li><p>We then tried using <code>WAIT</code> statements (<code>wait until</code>) but it failed. </p></li>
  <li>Then we tried using flipflops and delay circuits (D flipflop), but it resulted in level sync, and not Edge sync. </li>
  </ol>