title: VHDL case found in a tutorial video online
body: <p>I was just trying to practice some VHDL programming which I came across a tutorial video on youtube. I saw an interesting challenging question which asked the viewer ti implement the foolowing case:</p>
  
  <p>Can someone please help me as I am very new to VHDL and quite novice.</p>
  
  <p>first, second, and third, are of std_logic_vector (7 downto 0):</p>
  
  <p>second = first/4
  third =  first rem 4</p>