title: GNU Make: How to call $(wildcard) within $(eval)
body: <p>I'm trying to create a generic build template for my Makefiles, kind of like they discuss in the <a href="http://www.gnu.org/software/automake/manual/make/Eval-Function.html#Eval-Function" rel="nofollow noreferrer">eval documentation</a>.</p>
  
  <p>I can't seem to get the wildcard function to work within an eval.  The basic code I'm having issues with looks like this.</p>
  
  <pre><code>SRC_DIR = ./src/
  
  PROG_NAME = test
  
  define PROGRAM_template
    $(1)_SRC_DIR = $(join $(SRC_DIR), $(1)/)
    $(1)_SRC_FILES = $(wildcard $$($(1)_SRC_DIR)*.c)
  endef
  
  $(eval $(call PROGRAM_template, $(PROG_NAME)))
  
  all:
      @echo $(test_SRC_DIR)
      @echo $(test_SRC_FILES)
      @echo $(wildcard $(wildcard $(test_SRC_DIR)*.c)
  </code></pre>
  
  <p>When I run make with this, the output is</p>
  
  <pre><code>./src/test
  
  [correct list of all .c files in ./src/test/]
  </code></pre>
  
  <p>Basically, the wildcard call within PROGRAM_template is not being eval'd as I expect it.  The call results in an empty list.<br>
  The join call is being eval'd correctly though.</p>
  
  <p>So, what am I doing wrong?  My guess is that </p>
  
  <pre><code>$$($(1)_SRC_DIR) 
  </code></pre>
  
  <p>is not correct, but I can't figure out the right way to do it.</p>
  
  <p><strong>EDIT</strong>
  Once this was solved, it didn't take long for me to hit another issue with eval.
  I posted it as a new question at
  <a href="https://stackoverflow.com/questions/2428506/workaround-for-gnu-make-3-80-eval-bug">Workaround for GNU Make 3.80 eval bug</a></p>