title: vhdl 4 bit vedic multiplier
body: <pre><code>entity fourbitmult is
      Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
         p : out  STD_LOGIC_VECTOR (7 downto 0));
   end fourbitmult;
  
   architecture Behavioral of fourbitmult is
   component twobitmult
  
   port(a,b:in std_logic_vector(1 downto 0);
   p:out std_logic_vector (3 downto 0));
   end component;
  component rca
  port(a,b:in std_logic_vector(3 downto 0);
  s:out std_logic_vector(3 downto 0);
  carry:out std_logic;
  cin:in std_logic='0'
  );
   end component;
  component halfadder
  port(a,b:in std_logic;
  s,c:out std_logic);
  end component;
  signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22: std_logic;
  begin
  m1:twobitmult port map(a(0),a(1),b(0),b(1),p(0),p(1),c1,c2);
  m2:twobitmult port map(a(2),a(3),b(0),b(1),c15,c16,c17,c18);
  m3:twobitmult port map(a(0),a(1),b(2),b(3),c19,c20,c21,c22);
  m4:twobitmult port map(a(2),a(3),b(2),b(3),c7,c8,c9,c10);
  r1:rca port map(c15,c16,c17,c18,c19,c20,c21,c22,c3,c4,c5,c6,c12);
  r2:rca port map(c1,c2,c7,c8,c3,c4,c5,c6,p(2),p(3),p(4),p(5),c11);
  c13&lt;=c11 or c12;
  h1:halfadder port map(c13,c9,p(6),c14);
  h2:halfadder port map(c14,c10,p(7));
  end Behavioral;
  </code></pre>
  
  <p>I wrote a VHDL code for the 4 bit vedic multiplier.
  I am getting an error as:</p>
  
  <pre><code>Line 45. parse error, unexpected EQ, expecting SEMICOLON or CLOSEPAR"..
  </code></pre>
  
  <p>The syntax is perfectly right, I don't understand why it's an error. What could be wrong?</p>