title: Expecting an identifier
body: <p>The code was working fine earlier. I just switched A and B from being represented by switches to just being modular inputs. </p>
  
  <p>The error message: </p>
  
  <p><code>Error (10170): Verilog HDL syntax error at Part4.v(6) near text "4";  expecting an identifier</code></p>
  
  <p>The following code produces the error:</p>
  
  <pre><code>module 4bitAdder(A,B,Cin,LEDG);
      input [0:3] A;
      input [0:3] B;
      input [0:1] Cin;
      output [0:4] LEDG;
  
      fulladder FA1(Cin,A[0],B[0],c1,s0);
      fulladder FA2(c1,A[1],B[1],c2,s1);
      fulladder FA3(c2,A[2],B[2],c3,s2);
      fulladder FA4(c3,A[3],B[3],c4,s3);
  
      assign LEDG[4] = c4;
      assign LEDG[3] = s3;
      assign LEDG[2] = s2;
      assign LEDG[1] = s1;
      assign LEDG[0] = s0;
  
  endmodule
  
  module fulladder(carryin,a,b,carryout,s);
      input carryin, a, b;
      output carryout, s;
      assign s = a ^ b ^ carryin;
      assign carryout = (a &amp; b)|(a &amp; carryin)|(b &amp; carryin);
  
  endmodule 
  </code></pre>