title: How could I generate signal output as a slow clock domain that is a multiple of a fast clock domain?
body: <p>I have an FPGA which I have 40-60 MHz clock domain I am working with. My output will be a slow multiple of that clock domain.</p>
  
  <p>So if I have 40 MHz oscillator, the output interface would be 5 MHz.</p>
  
  <p>I was planning on using a clock divide by 2 and sending the signal to the input, but I don't like this design because I read about how I would need to send the signals through a clock buffer which I may not have enough resources and others have stated it could create hold violations. (<a href="https://www.thecodingforums.com/threads/pulse-stretching.377607/" rel="nofollow noreferrer">https://www.thecodingforums.com/threads/pulse-stretching.377607/</a>)</p>
  
  <p>My second idea is to use a counter that counts the amount of time required to hold the Q output of a DFF and apply back pressure to source logic.</p>
  
  <p>I currently do not have code. I am still thinking of it conceptually.</p>
  
  <p>The initial plan was use several clock divide by 2 block in series to get the output desired.</p>
  
  <p>For signals that seem like a 5 MHz clock domain but were generated with a 40 MHz clocked system, what is the terminology for this type of clock domain crossing?</p>
  
  <p>Are there any other options?</p>
  
  <p>Thank You</p>