title: improve atomic read from InterlockedCompareExchange()
body: <p>Assuming architecture is ARM64 or x86-64.</p>
  
  <p>I want to make sure if these two are equivalent:</p>
  
  <ol>
  <li><code>a = _InterlockedCompareExchange64((__int64*)p, 0, 0);</code></li>
  <li><code>MyBarrier(); a = *(volatile __int64*)p; MyBarrier();</code></li>
  </ol>
  
  <p>Where <code>MyBarrier()</code> is a memory barrier (hint) of compiler level, like <code>__asm__ __volatile__ ("" ::: "memory")</code>.
  So method 2 is supposed to be faster than method 1.</p>
  
  <p>I heard that <code>_Interlocked()</code> functions would also imply memory barrier of both compiler and hardware level.</p>
  
  <p>I heard that read (proper-aligned) intrinsic data is atomic on these architectures, but I am not sure if method 2 could be widely used?</p>
  
  <p>(ps. because I think CPU will handle data dependency automatically so hardware barrier is not much considered here.)</p>
  
  <p>Thank you for any <strong>advise</strong>/<strong>correction</strong> on this.</p>
  
  <hr>
  
  <p>Here is some benchmarks on Ivy Bridge (i5 laptop).</p>
  
  <p>(1E+006 loops: <strong>27ms</strong>):</p>
  
  <pre><code>; __int64 a = _InterlockedCompareExchange64((__int64*)p, 0, 0);
  xor eax, eax
  lock cmpxchg QWORD PTR val$[rsp], rbx
  </code></pre>
  
  <p>(1E+006 loops: <strong>27ms</strong>):</p>
  
  <pre><code>; __faststorefence(); __int64 a = *(volatile __int64*)p;
  lock or DWORD PTR [rsp], 0
  mov rcx, QWORD PTR val$[rsp]
  </code></pre>
  
  <p>(1E+006 loops: <strong>7ms</strong>):</p>
  
  <pre><code>; _mm_sfence(); __int64 a = *(volatile __int64*)p;
  sfence
  mov rcx, QWORD PTR val$[rsp]
  </code></pre>
  
  <p>(1E+006 loops: <strong>1.26ms</strong>, not synchronized?):</p>
  
  <pre><code>; __int64 a = *(volatile __int64*)p;
  mov rcx, QWORD PTR val$[rsp]
  </code></pre>