title: syntax error in accessing 2d register array in verilog code to synthesize in leonardo tool
body: <p>I made a simple cache with verilog code in ISE tool, and used a 2d array of registers as my cache memory, simulating testbench on it in Modelsim done well and no syntax errors and no mistake in desires output signals, but in Leonardo tool when I tell Leonardo read it in library ams600nm it return syntax error near first line that I accessed my 2d array (cache), do you have any idea?</p>
  <p>code:</p>
  <pre><code>module Cache(clk , wr
  ,din,adr,dout
  );
  input clk;
  input wr;
  input [3:0] din;
  input [3:0] adr;
  output [3:0] dout;
  output hit;
   reg [8:0] cache [3:0];
   reg h;
   reg [3:0] out;
   initial
      begin
          ***cache[0][8] = 1'b0; -----here-----
          cache[1][8] = 1'b0; -----also here for sure-----
          cache[2][8] = 1'b0;
          cache[3][8] = 1'b0;***
      end 
  </code></pre>