title: For loop in `define Macro
body: <p>I searched on SO, and on web, no where found the ans.
  I have following code, where It success fully parsed `define and generate expected results, but if number of times calling of macro is large then, Can we using <strong><em>Looping Construct?</em></strong>. </p>
  
  <pre><code>`define myreg(name) \
     addr_``name    
  
  `define para(i) \
    parameter `myreg(i) = i  
  
  module register;
  
  `para(1);
  `para(2);
  `para(3);
  `para(4);
  
  initial
  begin
    $display("ADDR1 = %d, ADDR2 = %d", addr_1, addr_2);
    $display("ADDR3 = %d, ADDR4 = %d", addr_3, addr_4);
    #100 $finish;
  end
  endmodule
  </code></pre>
  
  <p>Simulation Result:</p>
  
  <pre><code>// # Loading work.register(fast)
  // # run -all
  // # ADDR1 =           1, ADDR2 =           2
  // # ADDR3 =           3, ADDR4 =           4
  // # ** Note: $finish    : reg.v(18)
  </code></pre>
  
  <p>Now, when I use <strong><em>for loop</em></strong>, like in below code,</p>
  
  <pre><code>`define myreg(name) \
     addr_``name    
  
  `define para(i) \
    parameter `myreg(i) = i  
  
  module register;
  
  genvar i;
  generate 
    for (i = 1; i&lt;=4; i=i+1)
    begin
      `para(i);
    end
  endgenerate
  
  initial
  begin
    $display("ADDR1 = %d, ADDR2 = %d", addr_1, addr_2);
    $display("ADDR3 = %d, ADDR4 = %d", addr_3, addr_4);
    #100 $finish;
  end
  endmodule
  </code></pre>
  
  <p>In that case, It shows an error while displaying or using it,
  Simulation Result:</p>
  
  <pre><code>// # vsim -lib work register -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt 
  // # ** Note: (vsim-3813) Design is being optimized due to module recompilation...
  // # ** Error (suppressible): (vopt-7063) reg.v(24): Failed to find 'addr_1' in hierarchical name '/addr_1'.
  // # ** Error (suppressible): (vopt-7063) reg.v(24): Failed to find 'addr_2' in hierarchical name '/addr_2'.
  // # ** Error (suppressible): (vopt-7063) reg.v(25): Failed to find 'addr_3' in hierarchical name '/addr_3'.
  // # ** Error (suppressible): (vopt-7063) reg.v(25): Failed to find 'addr_4' in hierarchical name '/addr_4'.
  // # Optimization failed
  // # Error loading design
  </code></pre>
  
  <p>It is asked more times but proper solution is not given by any one, any help appreciated a lot.</p>