title: robustness of Xilinx ISE block ram inference
body: <p>I have a question regarding the robustness of Xilinx ISE block ram inference.</p>
  
  <p>I don't have xilinx ise installed on my machine (today) but I usually infer block rams perfectly using a dedicated coding, basically relying on :</p>
  
  <pre><code>type   ram_type is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
  </code></pre>
  
  <p>My question is : could you tell me if ISE will infer a correct block ram with</p>
  
  <pre><code>signed(DATA_WIDTH-1 downto 0)` instead of `std_logic_vector(DATA_WIDTH-1 downto 0)
  </code></pre>
  
  <p>or even more (in a package):</p>
  
  <pre><code>subtype signed8 is signed(7 downto 0)
  </code></pre>
  
  <p>and then</p>
  
  <pre><code>type   ram_type is array(2**ADDR_WIDTH-1 downto 0) of signed8;
  </code></pre>
  
  <p>I know the synthesizers are sometimes touchy...</p>