title: How to use a variable list as a target in a Makefile?
body: <p>Suppose I am working on a makefile and I have the following variable declaration at the top:</p>
  
  <pre><code>FILES = file1.cpp file2.cpp file3.cpp
  </code></pre>
  
  <p>Now suppose I want to compile each of those with a special command without specifying each target like this:</p>
  
  <pre><code>file1.o : file1.cpp
      custom_command file1.cpp
  file2.o : file2.cpp
      custom_command file2.cpp
  file3.o : file3.cpp
      custom_command file3.cpp
  </code></pre>
  
  <p>Is there a better way to do this using the <code>$(FILES)</code> variable I declared above?</p>
  
  <p>Something like:</p>
  
  <pre><code>$(FILES:.cpp=.o) : $(FILES)
      custom_command $(FILES)
  </code></pre>
  
  <p>...only it needs to do this for each file in the <code>$(FILES)</code> variable.</p>