title: How to tell make to never re-make prerequsities?
body: <p>I have a Makefile where <code>a: b</code> and  <code>b: c</code>. When I run <code>make a</code> while <code>b</code> exists, I expect Make to leave <code>b</code> alone even if <code>c</code> does not exist. But it seems like GNU Make goes all the way up the tree, and remakes everything down from the most upstream parent that has an issue.</p>
  <p>There is a flag <code>--always-make</code> that cause Make to always remake all prerequisites, even if not needed. Unfortunately, there does not appear to be a <code>--never-make</code> flag that never remakes any prerequisites, even if needed. Is there a general way I can get this behavior?</p>
  <p>Some possible solutions that don't seem suitable:</p>
  <ul>
  <li><code>touch</code>ing every file one by one is tedious, and in the case of missing files, results in empty &quot;fake&quot; files which I find far too hacky</li>
  <li>Commenting out the prereq as in <code>a: #b</code> breaks Make variables like <code>touch $&lt;</code>.</li>
  <li>Commenting out the rule for <code>b:</code> works, but often there are quite a few b scattered throughout the file, so this is a lot of commenting and also tedious</li>
  </ul>