title: Compare std_logic_vector to a constant using std_logic_vector package ONLY
body: <p>I use the following package only in my VHDL file:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  </code></pre>
  
  <p>In the code, I compare a std_logic_vector signal : A with a constant value, e.g</p>
  
  <pre><code>...if A&lt;="00001011" then
  </code></pre>
  
  <p>yet the code was checked correctly by Xilinx ISE. My understanding is that STD_LOGIC_1164 package does not include an implementation of inequalities having as an operand std_logic_vector so why the above code statement was accepted and will the above comparison treat A as signed or unsigned number?</p>