title: Linking (two) bidirectional ports between (two) modules in VHDL
body: <p>I have an FPGA which accepts an 8-bit address and data bus (one bus is used for both) from two microcontrollers.</p>
  <p>Using a 2:1 multiplexer, my FPGA only selects one device's inputs at a time (address and data) and the selection is based on an external signal to the FPGA.</p>
  <p>I also have a separate decoder and register module which the microcontroller reads and writes to.  How do I link the bidirectional output signal from my multiplexer to the decoder/register bidirectional input module at the higher level using the port map assignment?</p>
  <p>Using a std_logic_vector(7..0), it will not work as I get an error &quot;this signal is connected to multiple drivers&quot;.  I think I need to <a href="https://en.wikipedia.org/wiki/Three-state_logic" rel="nofollow noreferrer">tri-state</a> the two, but I'm not sure.  Looking at the image below, the green circle is what I'm trying to glue together.</p>
  <h3>My FPGA project</h3>
  <p><a href="https://i.stack.imgur.com/Bwc1I.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Bwc1I.jpg" alt="Enter image description here" /></a></p>