title: convert multiple makefiles into one makefile
body: <p>I just have writed some pure c programs for practice, each little program have a <code>XXX.h</code> file <code>XXX.c</code> file and <code>XXX_test.c</code> file with the main function in it. both of the <code>XXX.c</code> file and the <code>XXX_test.c</code> may have include some other <code>YYY.h</code> files. I use the the gcc -MM to find the dependency of <code>XXX_test.c</code> files automatically. finally, I come up with the makefile(using GNU makefile) <code>XXX.mk</code>:</p>
  
  <pre><code># change your targets to your real targets
  MINGW := MINGW32_NT-6.1
  CC = gcc
  OFLAG = -o 
  CFLAGS = -Wall -g -DDEBUG
  # get the dependent header files and change their name to source files
  TARGET := XXX_test
  FILES := $(filter %.c %.h, $(shell gcc -MM $(addsuffix .c, $(TARGET))))
  SRCS := $(FILES:.h=.c)
  DEPS := $(SRCS:.c=.d)
  OBJECTS := $(SRCS:.c=.o)
  
  #determine the os platform
  ifdef SystemRoot
     ifeq ($(shell uname), ${MINGW})
        RM = rm -f
        FixPath = $1
     else
        RM = del /Q
        FixPath = $(subst /,\,$1)
     endif
  else
     ifeq ($(shell uname), Linux)
        RM = rm -f
        FixPath = $1
     endif
  endif
  
  
  all: ${TARGET}
  # include .d files generated by gcc -MMD opt
  -include $(DEPS)
  # to generate the .o files as well as the .d files
  %.o:%.c
      $(CC) $(CFLAGS) -c -MMD $&lt; -o $@
  
  # generate the executable program
  ${TARGET}: ${OBJECTS}
      ${CC} $^ ${OFLAG} $@
  
  .PHONY:clean
  # the "$" is not needed before "FixPath"
  clean:
      $(RM) $(call FixPath, ${OBJECTS} ${DEPS})
  </code></pre>
  
  <p>each little program have a <code>XXX.mk</code> file. they are almost the same except that the content in the variable <code>TARGET</code> is different(see the makefile above). so I have <code>XXX.mk</code>, <code>YYY.mk</code> etc ... The question I want to ask is <strong>how can I convert all the makefiles, i.e. <code>XXX.mk</code>, <code>YYY.mk</code> ... into one makefile?</strong> for example <code>generic.mk</code> with a varible <code>TARGETS</code>(note the <code>S</code>) assigned to <code>XXX_test YYY_test ...</code>. the thing that I find difficult to handle is the <code>variable dependencies</code>:</p>
  
  <pre><code>TARGET --&gt; OBJECTS --&gt; SRCS --&gt; FILES --&gt; TARGET(the FILES is generate by gcc using -MM opt)
                           ↓
                          DEPS(used to include the .d files)
  </code></pre>
  
  <p>each target(such as XXX_test) should depend on their on bunch of files. I want to see the power of GNU makefile, how could I do it? I am learning to use the gmake.</p>