title: ModelSIM : debugging SIGNALs in VHDL
body: <p>I am working in a VHDL code with a lot of SIGNALs that I should be able to see in the simulation on ModelSim to debug my design.</p>
  
  <p>My question is whether is it necessary to declare outputs on my top-level entity so I can wire them an have access to those internal SIGNALs or is there any other way to access them from ModelSim?</p>