title: Make a Verilog module sensitive to a switch turning off
body: <p>This would make a Verilog module sensitive to a clock and a reset switch being turned on:</p>
  
  <pre><code>always @(posedge clk, posedge rst)
  </code></pre>
  
  <p>How would this be changed to being sensitive to a switch being turned off?</p>