title: make recompiles everything every time, why?
body: <p>Here's my makefile:</p>
  
  <pre><code>all: lex yacc compile
  
  lex: sql.l
      lex -i sql.l
  
  yacc: sql.y
      yacc -d -v sql.y
  
  compile: y.tab.c lex.yy.c
      $(CC) -o sql_parser y.tab.c lex.yy.c -ly -ll
  
  test: all
      @./parsesql.sh selecttest.sql
      @./parsesql.sh insertintotest.sql
      @./parsesql.sh deletefromtest.sql
      @./parsesql.sh createtest.sql
  
  cleanup:
      rm test.tab.cacc
      rm y.output
  </code></pre>
  
  <p>Running <code>make</code> will always trigger a full recompile, even if nothing has changed:</p>
  
  <pre><code>parsesql&gt;  make
  lex -i sql.l
  yacc -d -v sql.y
  cc -o sql_parser y.tab.c lex.yy.c -ly -ll
  parsesql&gt;  make
  lex -i sql.l
  yacc -d -v sql.y
  cc -o sql_parser y.tab.c lex.yy.c -ly -ll
  parsesql&gt;  make
  lex -i sql.l
  yacc -d -v sql.y
  cc -o sql_parser y.tab.c lex.yy.c -ly -ll
  </code></pre>
  
  <p>None of the files have changed, so why is it doing this? The <code>lex</code> and <code>yacc</code> commands should only trigger if <code>sql.l</code> or <code>sql.y</code> respectively have changed, no?</p>