title: VHDL Moving average: simulation & synthesis result differ (Vivado)
body: <p>For my project I need to reduce a noise of an ADC output and implemented a simple moving average filter in VHDL. </p>
  
  <p>Although it works in simulation (see the picture): 
  <a href="https://i.stack.imgur.com/9TN7G.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9TN7G.png" alt="simulation of moving average"></a>
   it has some strange behavior if I display it on the chipscope when the system is running in FPGA (see the picture):
  <a href="https://i.stack.imgur.com/RrrIq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RrrIq.png" alt="enter image description here"></a></p>
  
  <p>The VHDL code I use for the moving average is as follows:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.math_real.all;
  use ieee.numeric_std.all;
  
  entity moving_avg is
      generic(
           SAMPLES_COUNT      : integer := 32
      );
      port (
           clk_i              : in   std_logic;
           rst_n_i            : in   std_logic;
           sample_i           : in   std_logic_vector(11 downto 0);
           avg_o              : out  std_logic_vector(11 downto 0)
      );
  end;
  
  architecture rtl of moving_avg is
  
      type     sample_buff_t    is array (1 to SAMPLES_COUNT) of std_logic_vector(11 downto 0);
      signal   sample_buffer  : sample_buff_t;
      signal   sum            : std_logic_vector(31 downto 0);
      constant wid_shift      : integer := integer(ceil(log2(real(SAMPLES_COUNT))));
      signal   avg_interm_s   : std_logic_vector(31 downto 0);
  
  begin
  
      process (clk_i, rst_n_i) begin
          if rst_n_i='1' then
              sample_buffer &lt;= (others =&gt; sample_i);
              sum &lt;= std_logic_vector(unsigned(resize(unsigned(sample_i), sum'length))  sll wid_shift) ;
          elsif rising_edge(clk_i) then
              sample_buffer &lt;= sample_i &amp; sample_buffer(1 to SAMPLES_COUNT-1);
              sum &lt;= std_logic_vector(unsigned(sum) + unsigned(sample_i) - unsigned(sample_buffer(SAMPLES_COUNT)));
          end if;
      end process;
  
      avg_interm_s &lt;= std_logic_vector((unsigned(sum) srl wid_shift));
      avg_o &lt;= avg_interm_s(11 downto 0);
  
  end;
  </code></pre>
  
  <p>I use Xilinx Vivado tool 2015.2 running on Ubuntu 14.04 x64. </p>
  
  <p>Could you please help me to identify the problem, such 
  that results in simulation correspond to results after synthesis?</p>