title: Use a type before it's declared in VHDL (2008)
body: <p>Is it possible in any version of VHDL, maybe in 2008, to use a type before it's declared?</p>
  
  <p>E.g. I have this array declaration in the architecture of an entity:</p>
  
  <pre><code>type my_array is array (integer range &lt;&gt;) of my_type;
  </code></pre>
  
  <p>And still in the same architecture section, but later in the file I have this:</p>
  
  <pre><code>type my_type is record 
      my_field: signed(31 downto 0);
  end record;
  </code></pre>
  
  <p>Now this gives the following error in Vivado:</p>
  
  <blockquote>
    <p>[Synth 8-1031] my_type is not declared</p>
  </blockquote>
  
  <p>The solution is of course to move the record declaration above the array declaration. However this gets very complicated and messy with the number of types increasing (since you basically have to topologically sort your types taking their dependencies into account).</p>
  
  <p>Something like this is supported in every major programming language so I figured maybe it would also exist in VHDL. I also vaguely remember reading about this having been added to VHDL 2008 but can't find any resources about it and my quick test with VHDL 2008 was negative.</p>
  
  <p>So is it possible to use a type in VHDL before its declared, given that the type is declared still in the same architecture, same file, but a few lines below?</p>