title: How to initialize a wire[4:0] array in Verilog?
body: <p>I want to initialize a 5-bit wire with a constant. How to do that in Verilog?</p>
  
  <p><code>wire [4:0] master_data_out = [1'b0, 1'b1, 1'b1, 1'b0, 1'b0];</code></p>