title: Cache miss latency in clock cycles
body: <p>To measure the impact of cache-misses in a program, I want to latency caused by cache-misses to the cycles used for actual computation.
  I use <code>perf stat</code> to measure the cycles, L1-loads, L1-misses, LLC-loads and LLC-misses in my program. Here is a example output:</p>
  <pre><code>               467 769,70 msec task-clock                #    1,000 CPUs utilized          
          1 234 063 672 432      cycles                    #    2,638 GHz                      (62,50%)
            572 761 379 098      instructions              #    0,46  insn per cycle           (75,00%)
            129 143 035 219      branches                  #  276,083 M/sec                    (75,00%)
              6 457 141 079      branch-misses             #    5,00% of all branches          (75,00%)
            195 360 583 052      L1-dcache-loads           #  417,643 M/sec                    (75,00%)
             33 224 066 301      L1-dcache-load-misses     #   17,01% of all L1-dcache hits    (75,00%)
             20 620 655 322      LLC-loads                 #   44,083 M/sec                    (50,00%)
              6 030 530 728      LLC-load-misses           #   29,25% of all LL-cache hits     (50,00%)
  </code></pre>
  <p>Then my question is:
  <strong>How to convert the number of cache-misses into a number of &quot;lost&quot; clock cycles?</strong>
  Or alternatively, what is the proportion of time spent for fetching data?</p>
  <p>I think the factor should be known by the constructor. My processor is Intel Core i7-10810U, and I couldn't find this information in the <a href="https://ark.intel.com/content/www/us/en/ark/products/201888/intel-core-i7-10810u-processor-12m-cache-up-to-4-90-ghz.html" rel="nofollow noreferrer">specifications</a> nor in this <a href="https://www.7-cpu.com/" rel="nofollow noreferrer">list</a> of benchmarked CPUs.</p>
  <p>This <a href="https://stackoverflow.com/a/21542939/196561">related problem</a> describes how to measure the number of cycles lost in a cache-miss, but is there a way to obtain this as hardware information? Ideally, the output would be something like:</p>
  <pre><code>L1-hit: 3 cycles
  L2-hit: 10 cycles
  LLC-hit: 30 cycles
  RAM: 300 cycles
  </code></pre>