title: Add a constant to an std_logic_vector
body: <p>I have an input signal which is an <code>std_logic_vector</code> and holds an address. I use it to read from the memory, I need to read 500 bits, but since my memory data bus is only 256 bit wide, I need to read two consecutive chunks of 256 bit. To do this I want to read the first time from the address stored in the signal, and the second time from the address 256 bits (32 Bytes) after the address stored. How do I add a constant number to an <code>std_logic_vector</code>:</p>
  
  <pre><code>ADRESS  : in std_logic_vector (0 to 31);
  
  --code
  
  --read first word:
  dfmc_DDR2Interface_address &lt;= ADRESS;
  dfmc_DDR2Interface_read &lt;= '1';
  
  -- more code
  
  --read second word (what I want to do)
  dfmc_DDR2Interface_address &lt;= ADRESS+32;
  dfmc_DDR2Interface_read &lt;= '1';
  </code></pre>