title: shift register using dff verilog
body: <p>I want to create a shift register using d-flip-flop as basic structural element.
  code:</p>
  
  <p>dff:</p>
  
  <pre><code>  module dff(d,q,clk,rst);
  
    input d,clk,rst;
    output reg q;
  
    always @(posedge clk)
       begin:dff_block
          if(rst==1'b1)
            q=1'b0;
          else
            q=d;
       end
    endmodule
  </code></pre>
  
  <p>shift register:</p>
  
  <pre><code>  module shift_register(s1,d,clk,s0,q);
    parameter n=3;
  
    input  s1,clk;
    input [n:0] d;
  
    output s0;
    output [n:0] q;
  
    genvar i;
  
    assign d[3]=s1;
  
  
    generate
    for(i=0; i&lt;=n; i=i+1)
       dff U1(.d(d[i]),.q(q[i]),.clk(clk));
    endgenerate
  
    assign q[3]=d[2];
    assign q[2]=d[1];
    assign q[1]=d[0];
    assign q[0]=s0;
  
  
  
    endmodule
  </code></pre>
  
  <p>test bench:</p>
  
  <pre><code>  module tb();
  
    parameter n=3;
    reg [n:0] d;
    reg s1,clk;
  
    wire [n:0] q;
    wire s0;
  
  
    shift_register UUT(.s1(s1),.d(d),.clk(clk),.q(q),.s0(s0));
  
    initial begin
  
    d=4'b0000;
    clk=0;
    end
  
  
  always
  begin:clok
  #10 clk=~clk; s1=1;
  
  end
  endmodule
  </code></pre>
  
  <p>I think test bench has the problem.I have tried to give s1 values for every #10 while clk=1 but again does not work.</p>
  
  <p>This code does not give me waveforms for q and s0.I cant find whats wrong.Any ideas?</p>