title: Implementing one-bit flags in a 32Bit ALU using Verilog
body: <p>I am working on an assignment and am a little lost and don't really know how to get started. I need to implement the following flags in a 32Bit ALU: </p>
  
  <p>• Z ("Zero"): Set to 1 ("True") if the result of the operation is zero  </p>
  
  <p>• N ("Negative"): Set to 1 ("True") if the first bit of the result is 1, which indicates a negative number </p>
  
  <p>• O ("Overflow"): Set to 1 ("True") to indicate that the operation overflowed the bus width. </p>
  
  <p>Additionally, a comparison function that compares input a to input b and then set one of three flags:</p>
  
  <p>• LT if input a is less than input b </p>
  
  <p>• GT if input a is greater than input b </p>
  
  <p>• EQ if input a is equal to input b </p>
  
  <p>I need to modify this ALU to include the three flags and comparison outputs then change the test bench to test for all of these modifications. </p>
  
  <p>This was all the information I received for this assignment and there is no textbook or any other resources really. It's an online class, and I cannot get a response from my instructor. So I am a little confused as to how to get started. I am still a total newbie when it comes to digital logic so please bear with me. I just need some help understanding how these flags and comparison works. If any one can explain this a little better to me as far as how they work and what they do, and possibly how I would implement them into the ALU and testbench, I would really appreciate it. </p>
  
  <p>I don't expect anyone to do my assignment, I really just need help understanding it.</p>
  
  <p><strong>ALU</strong></p>
  
  <pre><code>module alu32 (a, b, out, sel);      
      input [31:0] a, b;    
      input [3:0] sel;   
      output [31:0] out,
      reg [31:0] out;  
  
      //Code starts here 
      always @(a, b, sel)   
      begin     
          case (sel)       
              //Arithmetic Functions       
              0  : out &lt;= a + b;       
              1  : out &lt;= a - b;       
              2  : out &lt;= b - a;       
              3  : out &lt;= a * b;       
              4  : out &lt;= a / b;       
              5  : out &lt;= b % a;       
              //Bit-wise Logic Functions       
              6  : out &lt;= ~a; //Not       
              7  : out &lt;= a &amp; b; //And       
              8  : out &lt;= a | b; //Or       
              9  : out &lt;= a ^ b; //XOR       
              10 : out &lt;= a ^~ b; //XNOR       
              //Logic Functions       
              11 : out &lt;= !a;       
              12 : out &lt;= a &amp;&amp; b;       
              13 : out &lt;= a || b;       
              default: out &lt;= a + b;     
          endcase
      end  
  endmodule 
  </code></pre>
  
  <p><strong>ALU Testbench</strong></p>
  
  <pre><code>module alu32_tb();  
      reg [31:0] a, b; 
      reg [3:0] sel; 
      wire [31:0] out; 
  
  initial begin
  
  $monitor("sel=%d a=%d b=%d out=%d", sel,a,b,out);   
      //Fundamental tests - all a+b   
      #0 sel=4'd0; a = 8'd0; b = 8'd0;    
      #1 sel=4'd0; a = 8'd0; b = 8'd25;   
      #1 sel=4'd0; a = 8'd37; b = 8'd0;   
      #1 sel=4'd0; a = 8'd45; b = 8'd75;  
      //Arithmetic   
      #1 sel=4'd1; a = 8'd120; b = 8'd25; //a-b   
      #1 sel=4'd2; a = 8'd30; b = 8'd120; //b-a   
      #1 sel=4'd3; a = 8'd75; b = 8'd3; //a*b   
      #1 sel=4'd4; a = 8'd75; b = 8'd3; //a/b   
      #1 sel=4'd5; a = 8'd74; b = 8'd3; //a%b  
      //Bit-wise Logic Functions   
      #1 sel=4'd6; a = 8'd31; //Not   
      #1 sel=4'd7; a = 8'd31; b = 8'd31; //And   
      #1 sel=4'd8; a = 8'd30; b = 8'd1; //Or   
      #1 sel=4'd9; a = 8'd30; b = 8'd1; //XOR   
      #1 sel=4'd10; a = 8'd30; b = 8'd1; //XNOR  
      //Logic Functions   
      #1 sel=4'd11; a = 8'd25; //Not   
      #1 sel=4'd12; a = 8'd30; b = 8'd0; //And   
      #1 sel=4'd13; a = 8'd0; b = 8'd30; //Or      
      #1 $finish; 
  end  
  
  alu32 myalu (.a(a), .b(b), .out(out), .sel(sel));  
  endmodule  
  </code></pre>