title: Nucleo-STM32F429ZI Ethernet + LWIP (RAW API) - doesn't work
body: <p>I've got a project in which I have to communicate by Ethernet (TCP) Nucleo-STM32F429ZI with PC. STM32 will be sending the data from sensor periodically. I'm using STM32CubeIDE with built in CubeMX. I've connected the STM32 and the PC with a crossed cable. I configured it without RTOS, only using LwIP in RAW API mode with static IP addresses. I’m calling the MX_LWIP_Process() function in while loop.</p>
  
  <p>My problem is that I can't receive ping response from STM32 and I’m getting the “Destination Host Unreachable” message. I've tried every configuration and advice I found on forums and it didn't work. I've tried to adapt my project configuration to that from the example for my board (LwIP_HTTP_Server_Netconn_RTOS which works and response) but it didn't work too. </p>
  
  <p>As I'm debugging my project I can receive the ARP frame with request for IP address and I can see in debugger that the output frame is correct but as the whole payload is passed to "HAL_ETH_TransmitFrame" function, the output/response frame is gone, I can't see it in the Wireshark. I've checked the pinout configuration for the Ethernet peripheral and the configuration addresses. I really don't know what I’m missing. </p>
  
  <p>I've got auto-negotiation enabled in ETH CubeMX and I've change the PHY address from default 1 to 0 and PHY Link down inturrupt from 0xB to 0x10 according to datasheet (I hope it's correct).</p>
  
  <p>Below I pasted my configuration for Ethernet PHY (LAN8742A)</p>
  
  <pre><code>/* LAN8742A_PHY_ADDRESS Address*/
  
  #define LAN8742A_PHY_ADDRESS           0U
  
  /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
  
  #define PHY_RESET_DELAY                 ((uint32_t)0x00000FFFU)
  
  /* PHY Configuration delay */
  
  #define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
  
  
  
  #define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
  
  #define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
  
  
  
  /* Section 3: Common PHY Registers */
  
  
  
  #define PHY_BCR                         ((uint16_t)0x00U)    /*!&lt; Transceiver Basic Control Register   */
  
  #define PHY_BSR                         ((uint16_t)0x01U)    /*!&lt; Transceiver Basic Status Register    */
  
  
  
  #define PHY_RESET                       ((uint16_t)0x8000U)  /*!&lt; PHY Reset */
  
  #define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!&lt; Select loop-back mode */
  
  #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!&lt; Set the full-duplex mode at 100 Mb/s */
  
  #define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!&lt; Set the half-duplex mode at 100 Mb/s */
  
  #define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!&lt; Set the full-duplex mode at 10 Mb/s  */
  
  #define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!&lt; Set the half-duplex mode at 10 Mb/s  */
  
  #define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!&lt; Enable auto-negotiation function     */
  
  #define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!&lt; Restart auto-negotiation function    */
  
  #define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!&lt; Select the power down mode           */
  
  #define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!&lt; Isolate PHY from MII                 */
  
  
  
  #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!&lt; Auto-Negotiation process completed   */
  
  #define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!&lt; Valid link established               */
  
  #define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!&lt; Jabber condition detected            */
  
  
  
  /* Section 4: Extended PHY Registers */
  
  #define PHY_SR                          ((uint16_t)0x1FU)    /*!&lt; PHY status register Offset                      */
  
  
  
  #define PHY_SPEED_STATUS                ((uint16_t)0x0004U)  /*!&lt; PHY Speed mask                                 */
  
  #define PHY_DUPLEX_STATUS               ((uint16_t)0x0010U)  /*!&lt; PHY Duplex mask                                 */
  
  
  
  #define PHY_ISFR                        ((uint16_t)0x001DU)    /*!&lt; PHY Interrupt Source Flag register Offset   */
  
  #define PHY_ISFR_INT4                   ((uint16_t)0x0010U)  /*!&lt; PHY Link down inturrupt       */ 
  
  </code></pre>
  
  <p>If you need any additional information about the setup please ask. Thank you very much for any help.</p>