title: Verilog 'assign' statement
body: <p>New to verilog so this may be a dumb question? Are there any concerns I should consider when assigning an 'input' net to an 'output' net or is this not possible? For example:</p>
  
  <pre><code>module TOP( CLK1, CLK2 );
  
      input CLK1;  
      output CLK2;
  
      assign CLK2 = CLK1;
  
  endmodule
  </code></pre>
  
  <p>Suppose CLK1 was a 50MHz clock, still valid?</p>