title: VHDL 'range => '0' command
body: <p>Was hoping someone could answer my question. I came across this command in a VHDL code and was not sure what it does exactly. Could someone clarify the following?</p>
  
  <blockquote>
    <p>if ( element1 = (element1'range => '0')) then</p>
  </blockquote>
  
  <p>given that element1 is a 4 bit std_logic_vector, what is this condition saying? I could not find a direct answer for this in the few books I had or on google. 
  Thanks!</p>