title: Are makefile relative paths treated the same as gcc relative paths?
body: <p>I know this sounds like a stupid question, and it is. I'm trying to write a makefile, which builds and links against a static library that I'm writing (this is a unit testing framework). Basically I can't figure out where the working directory of the call to gcc is when I use make. </p>
  
  <p>My directory structure looks like this:</p>
  
  <pre><code>./
  |-&gt; src
  |-&gt; include
  |-&gt; project
      |-&gt; Makefile
  |-&gt; test
      |-&gt; test.c, test.h
      |-&gt; project
          |-&gt; Makefile
  </code></pre>
  
  <p>So, if I go to the test/project directory and type the following command, I don't seem to have any problems</p>
  
  <pre><code>gcc -I../../include -I../../src ../test.c
  </code></pre>
  
  <p>But if I use a makefile with essentially the same configuration (makefile is below), then I get an error along the lines of:</p>
  
  <pre><code>gcc -o test ../test.c
  In file included from ../test.c:7:0:
  ../test.h:8:24: fatal error: System.h: No such file or directory
  #include "System.h"
  </code></pre>
  
  <p>(System.h is one of my header files located in the <code>include/</code> directory).</p>
  
  <p>So here's my question. Since I'm trying to use gcc to compile a file at a different relative path from the makefile, which has includes from a different relative path from itself, what is the proper way to do this with make? Should I change my working directory to the one that contains test.c, and include relative to that directory, or should I put relative paths to everything as if I called gcc from the directory of the makefile?</p>
  
  <p>Here's my makefile</p>
  
  <pre><code>CC = gcc
  CFLAGS = -Wall -std=c99 -static -I../../include -I../../src -L$(LIBTARGET) -lmystaticlib
  TARGET_APP=test
  LIBTARGET = ../../project
  
  all : $(TARGET_APP)
  
  $(TARGET_APP) : library
          $(CC) ${CLAGS} -o $@ ../test.c
  
  library : 
          $(MAKE) -C $(LIBTARGET)
  </code></pre>