title: VHDL-2008 hierarchical signal access to array
body: <p>I am trying to access an array via VHDL-2008 hierarchical names. I am able to access the whole array, but when I try to access individual array elements, I get the compilation error:</p>
  
  <pre><code>ACOM: Error: COMP96_0015: tb.vhd : (13, 43): ':' expected.
  </code></pre>
  
  <p>Is it possible to access individual array elements? What is the correct syntax?</p>
  
  <p>Here's my code:</p>
  
  <p><strong>DUT</strong></p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity dut is
  end entity dut;
  
  architecture rtl of dut is
      type t_data is array (natural range &lt;&gt;) of std_logic_vector(7 downto 0);
      signal s_data   : t_data(0 to 15)   := (others=&gt;(others=&gt;'1'));
  begin
      --don't care
  end architecture rtl;
  </code></pre>
  
  <p><strong>TB</strong></p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity tb is
  end entity tb;
  
  architecture sim of tb is    
      signal s_data_0 : std_logic_vector(7 downto 0);
  begin
      s_data_0    &lt;=  &lt;&lt; signal i_dut.s_data(0) : std_logic_vector(7 downto 0) &gt;&gt;;
  
      i_dut : entity work.dut;
  end architecture sim;
  </code></pre>