title: What does a single quote (') mean in SystemVerilog?
body: <p>In an OVM example class, I see the following statement in the constructor:</p>
  
  <pre><code>void'(get_config_int("num_packets", this.num_packets));
  </code></pre>
  
  <p>What is the first part <code>void'(</code> supposed to be doing in this statement?</p>