title: Verilog: Accessing wire in sub-module instance
body: <p>I would like to know if there is a syntax in Verilog to access a wire in a sub-module without making that wire an output. </p>
  
  <p>For example, if have the following modules: </p>
  
  <pre><code>module Module_Sub(a,b);
     input a,b; 
     wire c; 
     ...
  endmodule
  
  
  module Module_Top(d, e);
     input d,e; 
     wire f; 
  
     Module_Sub sm(d,e); 
     ...
  endmodule
  </code></pre>
  
  <p>Now, I want to access the wire 'c' in the instance 'sm' from the scope of Module_Top. 
  Is there a way to do it? 
  maybe something like: </p>
  
  <pre><code>assign f = sm/c; 
  </code></pre>
  
  <p>(This syntax obviously didn't work for me). </p>
  
  <p>P.S: 
  I know this isn't the best practice, but in my case it will make things a lot easier. </p>
  
  <p>Thanks! </p>
  
  <p>edit: I want it for a synthesis-able code. </p>