title: vhdl code for producig triangular wave using DAC2904 is not working
body: <p>I am doing a project in college and want to produce a triangular wave using a <a href="http://www.ti.com/lit/ds/symlink/dac2904.pdf" rel="nofollow">DAC2904</a> and a Spartan 3 xc3s5000 board.</p>
  
  <p>I have written code for it but is not working.</p>
  
  <p>I don't know may be it is the problem in code or in my ucf file:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;   
  
  entity traingular is
      Port ( 
          clk :     in  std_logic; -- on board clock           
          reset :   in  std_logic;
          dac_clk : out std_logic; -- clk for dac module           
          output :  out std_logic_vector(13 downto 0); -- output to dac   
          wr_dac :  out std_logic    -- pulse given to write pin  of dac ic.
      );
  end traingular;
  
  architecture Behavioral of traingular is
      signal counter :   unsigned(3 downto 0);
      signal divide :    std_logic_vector(15 downto 0);
      signal sampling_clk , clk_s  : std_logic;
      signal decade :    std_logic_vector(3 downto 0);
  
  -- decade counter used because on board clk freq is 40 hz
  -- so the code written below reduce the freq which is applied to dac module very much
  
  begin
      process(clk, reset)
      begin
          if (reset = '1' ) then
              decade &lt;= (others =&gt; '0');
          elsif (clk' event and clk = '1') then
              if (decade = "1010") then 
                  decade &lt;= (others =&gt; '0');
              else 
                  decade &lt;= std_logic_vector(unsigned(decade) + 1);
              end if;
          end if; 
      end process;
  
      clk_s &lt;= '1' when decade = "1010" else
               '0';
  
      process(clk_s , reset)
      begin
          if (reset='1') then
              divide &lt;= (others =&gt; '0');
          elsif (clk_s'event and clk_s = '1') then
              divide &lt;= std_logic_vector(unsigned(divide) + 1);
          end if;
      end process;          
  
      sampling_clk &lt;= divide(2);
  
  -- input click is still fast so clock is divided further
  
      dac_clk &lt;= sampling_clk;
  
      wr_dac &lt;= sampling_clk;
  
      process(clk , reset)
      begin
  
  -- code below is for counter which will further feed to dac to produce traingular wave.
          if (reset = '1' ) then
              counter &lt;= (others =&gt; '0');
          elsif (clk' event and clk = '1') then
              if (counter = "1010") then 
                  counter &lt;= (others =&gt; '0');
              else 
                  counter &lt;= counter + 1;
              end if;
          end if; 
      end process;
  
      output &lt;= "0000000000" &amp; std_logic_vector(counter); -- output to dac.
  
  end Behavioral;
  </code></pre>
  
  <p>So, can you guys tell me what is the problem in my code.</p>