title: In VHDL, Can I use signal'event if signal is not a clock?
body: <p>I am trying to clean up my VHDL code. I have a signal that is NOT a clk.</p>
  
  <p>Can I write an event change monitor like the following and how do I get it to compile so it can be synthesized? (see code) I have tried several permutations but I cannot get it to compile. Will signal'event compile if signal is not a CLK and if so, how is it done? I see on the web and other literature that it can be done but all examples I see show CLK'event. </p>
  
  <pre><code>signal cntr: unsigned(15 downto 0) := (others =&gt; '0');
  
  ...
  process(CLK):
  begin
  
  IF rising_edge(CLK) THEN
      if (cntr'event) then
          do something;
      end if;
  or...
      if(cntr(0)'event) then
          do something;
      end if;
  END IF;
  end process;
  </code></pre>
  
  <p>I get the following and others
  : can't synthesize condition that contains an isolated 'EVENT predefined attribute</p>