title: How to force revaluation of variables in makefile
body: <p>I have a makefile which runs a binary to generate the cpp files. I then compile the cpp files and generate .o files for each cpp file.</p>
  
  <p>The problem is when the makefile is first invoked, the folder is empty because the binary is not invoked yet and </p>
  
  <pre><code>CPP_FILES=$(wildcard $(MY_DIR)/inc/output/*.cpp) 
  </code></pre>
  
  <p>will be an empty variable. </p>
  
  <p>So I changed the line to</p>
  
  <pre><code>CPPFILES=$$(wildcard $(MY_DIR)/inc/output/*.cpp) 
  OBJFILES=$$(patsubst $(MY_DIR)/*.cpp,$(MY_DIR)/*.o,$(CPPFILES))
  </code></pre>
  
  <p>and </p>
  
  <p>//ran the binary to generate the cpp files</p>
  
  <pre><code>.SECONDEXPANSION:
  libEXP.so:$(CPPFILES),$(OBJFILES)
         $(CC) $(CFLAGS) -I(INC) -L(LIBS) -shared -o $(OBJFILES) $@
  </code></pre>
  
  <p>The secondary expansion fails saying shell cannot find wildcard command.<br>
  What am I doing wrong??</p>