title: System Verilog always_latch vs. always_ff
body: <p>I am confused about the usage of statements <code>always_ff</code> and <code>always_latch</code>.
  The former would be used as:</p>
  <pre><code>always_ff @ (posedge clk)
  begin
      a &lt;= b;
  end
  </code></pre>
  <p>while the latter:</p>
  <pre><code>always_latch
  begin
      a &lt;= b;
  end
  </code></pre>
  <p>The first is activated just by the positive edge of the clock and, coupled with nonblocking assignment, produces a FF.</p>
  <p>The <code>always_latch</code> is obviously thought to represent a latch, but then why use a nonblocking assignment?</p>
  <p>Wouldn't it be better using an <code>always_comb</code> with blocking assignments?</p>