title: what's wrong with this vhdl code?
body: <p>this structural counter must count in this way:
  0...9 0...9 0..3  and again... 
  i think my problems are at the istances at the end, in gtk wave I have problems only with the counter2! I don't know why, please help...</p>
  
  <p><a href="http://www.cromo-pharma.it/circuito.jpg" rel="nofollow noreferrer">circuit.. http://www.cromo-pharma.it/circuito.jpg</a></p>
  
  <pre><code>            ---------component instantiations-----------
  
                  signal sR2, sE2, sR1 : std_logic;
                  signal s2, s3, s8 : std_logic;
                  signal s0sec, s1sec, s2sec : std_logic;
                  signal c1out, c2out : std_logic_vector (3 downto 0);
                  signal dec1out, dec2out : std_logic_vector(15 downto 0);
  
                  begin
  
                  i2: counter1 port map (clk =&gt; clk, reset =&gt; sR1, count1 =&gt; c1out);
                  i3: counter2 port map (clk =&gt; clk, reset =&gt; sR2, en2 =&gt; sE2, count2 =&gt; c2out);
                  i5: deco port map (binary_in =&gt; c1out, decoder_out =&gt; dec1out);
                  i6: deco port map (binary_in =&gt; c2out, decoder_out =&gt; dec2out);
  
                  sR1 &lt;= ((s8 and (s0sec or s1sec)) or (s2sec and s2)) or reset;
                  sR2 &lt;= (s2 and s2sec);
                  sE2 &lt;= s8;
  
                  s2 &lt;= dec1out(2); --_a _b c _d 0010
                  s3 &lt;= dec1out(3); --_a _b c d 0011
                  s8 &lt;= dec1out(8); -- a _b _c _d 1000
                  s0sec &lt;= dec2out(0); -- _a _b _c _d 0000
                  s1sec &lt;= dec2out(1); -- _a _b _c d 0001
                  s2sec &lt;= dec2out(2); -- _a _b c _d 0010
  
                  i4: data_out &lt;= c1out;
              ---------------end----------------
  
              --decoder--
                architecture dec of deco is 
                begin
                      decoder_out &lt;= "1000000000000000" when binary_in="1111" else
                                     "0100000000000000" when binary_in="1110" else
                                     "0010000000000000" when binary_in="1101" else
                                     "0001000000000000" when binary_in="1100" else
                                     "0000100000000000" when binary_in="1011" else
                                     "0000010000000000" when binary_in="1010" else
                                     "0000001000000000" when binary_in="1001" else
                                     "0000000100000000" when binary_in="1000" else
                                     "0000000010000000" when binary_in="0111" else
                                     "0000000001000000" when binary_in="0110" else
                                     "0000000000100000" when binary_in="0101" else
                                     "0000000000010000" when binary_in="0100" else
                                     "0000000000001000" when binary_in="0011" else
                                     "0000000000000100" when binary_in="0010" else
                                     "0000000000000010" when binary_in="0001" else
                                     "0000000000000001" when binary_in="0000" else
                                     "XXXXXXXXXXXXXXXX";
              end architecture dec;
  
                     --counter with enable--
  
              entity counter2 is
                  port (  clk : in std_logic;
                          reset : in std_logic;
                          count2 : out std_logic_vector (3 downto 0);
                          en2 : in std_logic
                          );
              end entity counter2;
  
              architecture RTL of counter2 is
  
              begin
                   process (clk, reset, en2) is -- processo di verifica
                    variable cnt : unsigned(3 downto 0);
                  begin
                    if reset = '1' then cnt := (others =&gt; '0');
                    elsif rising_edge(clk) and en2='1' then 
                          if en2 = '1' then cnt := cnt + 1;
                          end if;
                    end if;
                    count2 &lt;= std_logic_vector(cnt); 
                  end process;
  
                           --standard counter--
  
                  entity counter1 is
                      port (  clk : in std_logic;
                              reset : in std_logic;
                              count1 : out std_logic_vector (3 downto 0)  
                              );
                  end entity counter1;
  
                  architecture RTL of counter1 is
  
                  begin
                       process (clk, reset) is -- processo di verifica
                        variable cnt : unsigned(3 downto 0);
                      begin
                        if reset = '1' then cnt := (others =&gt; '0');
                        elsif rising_edge(clk) then cnt := cnt + 1;
                        end if;
                        count1 &lt;= std_logic_vector(cnt); 
                      end process;
  </code></pre>