title: System verilog: choose module input or output at compile time
body: <p>I have an issue for a system-verilog project. I simulate using Questasim, but this is more a language-related question, I actually have not been able to find any answer in more than 2 weeks of studying.</p>
  <p>I have a collection of many (~1000s) <em>almost identical</em> modules, repeated and connected one another. This module is parametrized with an <code>ID</code>. Inside the module, some actions are performed depending on the value of this <code>ID</code> and everything looks working as expected.</p>
  <p>The reason why these modules are not exactly identical is that, depending on the ID, some signals to and from the modules swap. What I mean is that, in pseudo code, I would like to have something like:</p>
  <pre><code>module test #(
      ID = 0
    )  (
      ...
      if(ID == 0) input wire A
      else if(ID == 1) output wire A
      ...
  
      ...
  
  endmodule
  </code></pre>
  <p>does systemverilog support, in any way, something like this? I can work around this problem using a verilog generating script, but that is not so maintainable in my experience.</p>
  <p>This is actually a semplification, I truly have ~10s of signal and they change from input to output in almost any possible way, therefore manual writing is hardly possible.</p>
  <p>I know it may be possible to just work with <code>inout</code> and do everything inside, but at compile time I do know exactly what is an input and what is an output for every ID, therefore this solution does not look elegant at all to me.</p>