title: Verilog implementing a<b ? 1 : 0
body: <p>I'm trying to understand this code and I can't wrap my head around it</p>
  
  <pre><code>// upper bits are always zero
  assign slt[31:1] = 0;
  
  xor (condition, a[31], b[31]);
  yArith slt_arith (tmp, cout, a, b, 1);
  yMux #(.SIZE(1)) slt_mux(slt[0], tmp[31], a[31], condition);
  </code></pre>
  
  <p><code>a</code> and <code>b</code> are some 32 bit numbers</p>
  
  <p>The code is trying to implement <code>(a &lt; b) ? 1 : 0;</code> Which is known as slt in mips</p>
  
  <p>the <code>yArith</code> part is doing (a-b) and places result into <code>tmp</code>, the 1 is a flag for subtraction.</p>
  
  <p>the <code>yMux</code> part is 2x1 mux, that takes some condition (0 or 1) to select either <code>tmp[31]</code> if condition is 0 or <code>a[31]</code> if condition is 1.</p>
  
  <p>Why does this code work to implement set on less than in Verilog?</p>