title: Rewrite code using generate statement (Verilog HDL)
body: <p>I'm trying to rewrite this code using generate statements (Verilog HDL):</p>
  <pre><code>integer j;
  always@(posedge cpu_clk) begin
          // ACCU_RST
          if(RAM[3][7]) begin
              RAM[3][7] &lt;= 1'b0;
              for(j = 10; j &lt;= 15; j = j + 1)
                  RAM[j] &lt;= 8'b0;
          end
          
          // CPU write
          RAM[addr + 0] &lt;= in_valid &amp;&amp; cmd &amp;&amp; (addr + 0 &lt;= 9 || addr + 0 &gt;= 16) ? data_in[8 * 0 + 7:8 * 0] : RAM[addr + 0];
          RAM[addr + 1] &lt;= in_valid &amp;&amp; cmd &amp;&amp; (addr + 1 &lt;= 9 || addr + 1 &gt;= 16) ? data_in[8 * 1 + 7:8 * 1] : RAM[addr + 1];
          RAM[addr + 2] &lt;= in_valid &amp;&amp; cmd &amp;&amp; (addr + 2 &lt;= 9 || addr + 2 &gt;= 16) ? data_in[8 * 2 + 7:8 * 2] : RAM[addr + 2];
          RAM[addr + 3] &lt;= in_valid &amp;&amp; cmd &amp;&amp; (addr + 3 &lt;= 9 || addr + 3 &gt;= 16) ? data_in[8 * 3 + 7:8 * 3] : RAM[addr + 3];
  
          //CPU read
          out_valid &lt;= !cmd &amp;&amp; in_valid;
          out_data[8 * 0 + 7:8 * 0] &lt;= !cmd &amp;&amp; in_valid ? RAM[addr + 0] : out_data[8 * 0 + 7:8 * 0];
          out_data[8 * 1 + 7:8 * 1] &lt;= !cmd &amp;&amp; in_valid ? RAM[addr + 1] : out_data[8 * 1 + 7:8 * 1];
          out_data[8 * 2 + 7:8 * 2] &lt;= !cmd &amp;&amp; in_valid ? RAM[addr + 2] : out_data[8 * 2 + 7:8 * 2];
          out_data[8 * 3 + 7:8 * 3] &lt;= !cmd &amp;&amp; in_valid ? RAM[addr + 3] : out_data[8 * 3 + 7:8 * 3];
  end
  </code></pre>
  <p>Yet I recieve the following errors if I try this:</p>
  <pre><code>// CPU write
      for(i = 0; i &lt;= 3; i = i + 1) begin
          if(in_valid &amp;&amp; cmd &amp;&amp; (addr + i &lt;= 9 || addr + i &gt;= 16)) 
              RAM[addr + i] &lt;=  data_in[8 * i + 7:8 * i];
      end
      //CPU read
      out_valid &lt;= !cmd &amp;&amp; in_valid;
      for(i = 0; i &lt;= 3; i = i + 1) begin
          if(in_valid &amp;&amp; !cmd) 
              out_data[8 * i + 7:8 * i] &lt;=  RAM[addr + i];
      end
  </code></pre>
  <blockquote>
  <p>ERROR: i is not a constant value.</p>
  </blockquote>
  <p>(error points to data_in[8 * i + 7:8 * i] and out_data[8 * i + 7:8 * i])</p>
  <p>Another try, using two always blocks, one for generate, one for ACCU_RST yields multiple drivers for RAM (duh).</p>
  <p>Last try:</p>
  <pre><code>genvar i;
  always@(posedge cpu_clk) begin
      if(ACCU_RST) begin
          RAM[3][7] &lt;= 1'b0;
          for(j = 10; j &lt;= 15; j = j + 1)
              RAM[j] &lt;= 8'b0;
      end
      
      // CPU write cmd
      for(i = 0; i &lt;= 3; i = i + 1) begin :CPU_W
          if(in_valid &amp;&amp; cmd &amp;&amp; (addr + i &lt;= 9 || addr + i &gt;= 16)) 
              RAM[addr + i] &lt;=  data_in[8 * i + 7:8 * i];
      end
  
      //CPU read cmd
      out_valid &lt;= !cmd &amp;&amp; in_valid;
      for(i = 0; i &lt;= 3; i = i + 1) begin :CPU_R
          if(in_valid &amp;&amp; !cmd) 
              out_data[8 * i + 7:8 * i] &lt;=  RAM[addr + i];
      end
  end
  </code></pre>
  <p>That yields:</p>
  <blockquote>
  <p>ERROR: Procedural assignment to a non-register i is not permitted,
  left-hand side should be reg/integer/time/genvar</p>
  </blockquote>
  <p>(and points to i = 0 and to i = i + 1).</p>