title: SystemVerilog: How come the enum next() method cannot be used in a constant function?
body: <p>I have a package containing a number of packed-struct typedefs and I am trying to write a CONSTANT function to tell me the maximum bit width of these structs. Each struct has an explicit message_type which is enumerated. I believe the below function I have written should be interpreted by the compiler as constant, but I am getting the error "(vlog-2118) The function 'get_max_message_length' is not a valid constant function" (this is in ModelSim).</p>
  
  <p>Can anyone tell me why this function is not constant? After debugging I have determined that it is the enum method 'next()' that is causing it to be interpreted wrong. Any possible alternate solutions? Thank you in advance!</p>
  
  <pre><code>typedef enum logic [7:0]
  {
     MESSAGE_TYPE_0=0,
     MESSAGE_TYPE_1=1,
     MESSAGE_TYPE_2=2
  } _MSGTYPE;
  
  function integer get_message_length (_MSGTYPE message_type);
     case (message_type)
        MESSAGE_TYPE_0: return ($bits(message_0));
        MESSAGE_TYPE_1: return ($bits(message_1));
        MESSAGE_TYPE_2: return ($bits(message_2));
        default: return 0;
     endcase
  endfunction
  
  function integer get_max_message_length ();
     automatic _MSGTYPE largest = largest.first();
     automatic _MSGTYPE next = next.first();
     next = next.next();
     while (next != next.first()) begin
        largest = get_message_length(largest) &gt; get_message_length(next) ? largest : next;
        next = next.next();
     end
     return get_message_length(largest);
  endfunction
  </code></pre>