title: VHDL - Shifting an array of bytes
body: <p>I'm having some problems with a shifter module that will shift the indexes of an array that is composed of bytes.</p>
  
  <p>shifter.vhd:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use work.mypackage2.all; -- contains the type reg array
  
  entity shifter is
      generic ( REGSIZE  : integer := 8);
      port(clk      : in  std_logic;
              Scan_Dav : in  std_logic;
              Data_in  : in  std_logic_vector(7 downto 0);
              Data_out : out reg_array );
  end shifter;
  
  architecture bhv of shifter is
  
      signal shift_reg : reg_array;
  begin
      process (clk) begin
          if rising_edge(clk) then
                  if Scan_Dav = '1' then
                      shift_reg &lt;= shift_reg(shift_reg'high-1 downto 0) &amp; Data_in;
                  end if;
            end if;
      end process;
       Data_out &lt;= shift_reg;
  end bhv;
  </code></pre>
  
  <p>This is a shifter that will hold the scancodes from the keyboard and the output array will be used to scroll the text on seven segment display. My package holds the type declaration used to define the output of shifter:</p>
  
  <p>mypackage2.vhd:</p>
  
  <pre><code>--  Package File Template
  --
  --  Purpose: This package defines supplemental types, subtypes, 
  --       constants, and functions 
  
  
  library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  
  package mypackage2 is
  
     subtype reg is std_logic_vector(7 downto 0); -- a byte
      type reg_array is array (7 downto 0) of reg; -- array of bytes
  
  end mypackage2;
  
  
  package body mypackage2 is
  
  end mypackage2;
  </code></pre>
  
  <p>I'm having problems with it though. The RTL schematic of this code appears to be as:</p>
  
  <p><img src="https://i.stack.imgur.com/TdRGx.jpg" alt="RTL of shifter:"></p>
  
  <p>I'm confused why this happens, can anyone help me with this issue?</p>