title: Verilog Synchronous state machine
body: <p>I'm trying to design this state machine in verilog:</p>
  
  <p><a href="https://i.stack.imgur.com/EZQOj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EZQOj.png" alt="enter image description here"></a></p>
  
  <p>I was have:</p>
  
  <pre><code>   `timescale 1ns/1ns
  module labEightMachine(y, x,clk,clr)
          output      y;
          input [1:2] x;
          input       clk, clr;
          reg [1:2]   q;
          reg         y;
          reg         nX;
          always @ (posedge clk)
              begin
              if(clr)
                  {q}&lt;=2'b00;
  
              else
                  q&lt;= {nX}
              end
          always @(y,x)
          begin
          if(q==2'b00)
              if(x==2'b00)
                  q&lt;=2'b00;
              else
                  q&lt;=2'b01;
                  y&lt;=1;
          if(q==2'b01)
              if((x==2'b00)||(x==2'b01))
                  q&lt;=2'b00;
                  y&lt;=0;
              else
                  q&lt;=2'b11;
                  y&lt;=0;
          if(q==2'b11)
              if(x==2'b10)
                  q&lt;=2'b10;
                  y&lt;=1;
              else
                  q&lt;=2'b00;
                  y&lt;=0;
          if(q==2'b10)
              q&lt;=2'b00;
                  y&lt;=0;
          end
  endmodule
  </code></pre>
  
  <p>If any one could help by telling me where it is incorrect, that would be greatly appreciated. The state machines confuse me and I'm not sure that I am reassigning everything correctly.</p>