title: how to go about designing a 16 bit carry look ahead adder in verilog
body: <p>I'm having some complications on designing a 16 bit carry look-ahead adder in verilog. I have the code here:</p>
  
  <pre><code>  module fulladder(a, b, c, s, cout);
      input a, b, c;
      output s, cout;
  
     xor  #0
      g1(w1, a, b),
      g2(s, w1, c);
     and  #0
      g3(w2, c, b),
      g4(w3, c, a),
      g5(w4, a, b);
     or   #0
      g6(cout, w2, w3, w4);
    endmodule
  </code></pre>
  
  <p>I understand on how ports work, but do I use vectors?</p>
  
  <p>p.s. its in structural verilog. Please dont give me the full code. Just need some understanding. thanks</p>