title: Verilog 4x16 Decoder outputs wrong data
body: <p>I have implemented a 4x16 Decoder using Verilog along with it's test. For each case the decoder should output a 16-bit digit with only one of the bits high. I can't manage to get all the desired outputs when I run the program. Here is the code for the Decoder and test, and the output at the console:</p>
  
  <p>4x16 Decoder:</p>
  
  <pre><code>module Decoder4x16 (input [3:0] select, input enable, output reg [16:0] out);
  
  always @(select, enable)
  begin
  
      if(enable == 1'b0)
          out = 16'b0000000000000000;
      else if(enable == 1'b1)
          if(select == 4'b0000)
              out &lt;= 16'b0000000000000001;
          else if(select == 4'b0001)
              out &lt;= 16'b0000000000000010;
          else if(select == 4'b0010)
              out &lt;= 16'b0000000000000100;
          else if(select == 4'b0011)
              out &lt;= 16'b0000000000001000;
          else if(select == 4'b0100)
              out &lt;= 16'b0000000000010000;
          else if(select == 4'b0101)
              out &lt;= 16'b0000000000100000;
          else if(select == 4'b0110)
              out &lt;= 16'b0000000001000000;
          else if(select == 4'b0111)
              out &lt;= 16'b0000000010000000;
          else if(select == 4'b1000)
              out &lt;= 16'b0000000100000000;
          else if(select == 4'b1001)
              out &lt;= 16'b0000001000000000;
          else if(select == 4'b1010)
              out &lt;= 16'b0000010000000000;
          else if(select == 4'b1011)
              out &lt;= 16'b0000100000000000;
          else if(select == 4'b1100)
              out &lt;= 16'b0001000000000000;
          else if(select == 4'b1101)
              out &lt;= 16'b0010000000000000;
          else if(select == 4'b111)
              out &lt;= 16'b0100000000000000;
          else if(select == 4'b1111)
              out &lt;= 16'b1000000000000000;
      end
  
  endmodule
  </code></pre>
  
  <p>Test:</p>
  
  <pre><code>module Decoder4x16_test;
  
  reg [3:0] select;
  reg enable;
  wire [16:0] out;
  
  parameter sim_time = 2800;
  
  Decoder4x16 decoder(select, enable, out);
  initial #sim_time $finish;
  initial
  begin
      select = 4'b0000;
      enable = 1'b0;
  
      repeat(16) #10 begin
          enable = 1'b1;
          #85 $display("select = %b \t out = %b", select, out);
          select = select + 4'b0001;
      end
  end
  endmodule
  </code></pre>
  
  <p>When I run the program it outputs the correct output until it reaches the test case where the input is 1101. After that the decoder outputs the wrong value that it is suppose to display. Here is the output:</p>
  
  <pre><code>select = 0000    out = 00000000000000001
  select = 0001    out = 00000000000000010
  select = 0010    out = 00000000000000100
  select = 0011    out = 00000000000001000
  select = 0100    out = 00000000000010000
  select = 0101    out = 00000000000100000
  select = 0110    out = 00000000001000000
  select = 0111    out = 00000000010000000
  select = 1000    out = 00000000100000000
  select = 1001    out = 00000001000000000
  select = 1010    out = 00000010000000000
  select = 1011    out = 00000100000000000
  select = 1100    out = 00001000000000000
  select = 1101    out = 00010000000000000
  select = 1110    out = 00010000000000000
  select = 1111    out = 01000000000000000
  </code></pre>