title: VHDL - Adding two 8-bit vectors into a 9-bit vector
body: <p>This is a pretty simple question, but I haven't been able to make this work yet, nor has any searching on google or here turned up anything really useful.</p>
  
  <p>All I'm trying to do is add two 8-bit vectors and store the result in a 9-bit vector.</p>
  
  <pre><code>signal operand1, operand2 : STD_LOGIC_VECTOR(7 downto 0);
  
  signal sum : STD_LOGIC_VECTOR(8 downto 0);
  
  sum &lt;= operand1 + operand2;
  </code></pre>
  
  <p>However I get the warning:</p>
  
  <pre><code>Width mismatch. &lt;sum&gt; has a width of 9 bits but assigned expression is 8-bit wide.
  </code></pre>
  
  <p>Shouldn't VHDL have some sort of built in routine to know that an extra bit is necessary for addition overflow?</p>
  
  <p>I have these packages included:</p>
  
  <pre><code>use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  </code></pre>
  
  <p>Perhaps STD_LOGIC_VECTOR is always signed? If so, then I need to define them explicity as unsigned?</p>