title: How does CUDA's nppiMalloc... function guarantee alignment?
body: <p>Something that's been confusing me for a while is the alignment requirement of allocated CUDA memories. I know that if they are aligned, accessing row elements will be much more efficient.</p>
  
  <p><strong>First a little background:</strong></p>
  
  <p>According to CUDA C Programming Guide (section 5.3.2):</p>
  
  <blockquote>
    <p>Global memory resides in device memory and device memory is accessed
    via 32-, 64-, or 128-byte memory transactions. These memory
    transactions must be naturally alignedOnly the 32-, 64-, or 128-byte
    segments of device memory that are aligned to their size (i.e., whose
    first address is a multiple of their size) can be read or written by
    memory transactions.</p>
  </blockquote>
  
  <p>My understanding is that for a 2D interleaved array of type <code>T</code>, (say pixel values in R,G,B order), if <code>numChannels * sizeof(T)</code> is either 4, 8 or 16, then the array has to be allocated using <code>cudaMallocPitch</code> if performance is a necessity. So far this has been working fine for me. I'd check <code>numChannels * sizeof(T)</code> before allocating a 2D array and if it is 4, 16 or 32, I allocate it using <code>cudaMallocPitch</code> and everything works.</p>
  
  <p><strong>Now the question:</strong></p>
  
  <p>I've realized that when using NVIDIA's NPP library, there is a family of allocator functions (<code>nppiMalloc</code>... like <code>nppiMalloc_32f_C1</code> and so on). NVIDIA has recommended using these functions for performance. My question is that, how are these functions guaranteeing the alignment? More specifically, what kind of math are they using to come up with a suitable value for <code>pitch</code>?</p>
  
  <p>For a single channel 512x512 pixel image (with float pixel values in the range [0, 1]) I've used both <code>cudaMallocPitch</code> and <code>nppiMalloc_32f_C1</code>.<br>
  <code>cudaMallocPitch</code> gave me a pitch value of 2048 while <code>nppiMalloc_32f_C1</code> gave me 2560. Where is the latter number coming from and how exactly is that?</p>
  
  <p><strong>Why I care about this</strong><br>
  I'm writing a synced memory class template for synchronizing values on GPU and CPU. This class is supposed to be taking care of allocating pitched memories (if possible) under the hood. Since I want this class to be interoperable with NVIDIA's NPP, I'd like to handle all allocations in a way that would provide good performance for CUDA kernels as well as NPP operations.<br>
  My impression was that <code>nppiMalloc</code> was calling <code>cudaMallocPitch</code> under the hood, but it seems that I'm wrong.</p>