title: What is the difference interrupt based and poll based SPI transaction
body: <p>I have some doubts regarding SPI communication protocol.On my architecture there is a SPI  communication link between processor and CPLD device.I wanted to write to one of the CPLD register.</p>
  
  <p>I am planning to write CPLd LKM which would pass address of CPLD register and value to spi linux core using calls like spi_sync.</p>
  
  <p>So Do I need to consider processor as master and CPLD device as slave?</p>
  
  <p>Also,would want to know what it mean by interrupt based and poll based SPI transaction and why poll based transaction is advisable at boot time?</p>