title: What situations cause timer interrupts to clash/miss?
body: <p>I am working on a run-to-completion state-machine RTOS. I am wondering under what conditions can interrupts be missed? Can max CPU utilization conditions (100%) cause interrupts to be missed? Also if two timers having different handlers but same interrupt lines timeout at the same tick, which ISR runs first?</p>
  
  <p>[Appreciate a reply from the perspective of a software/firmware engineer, with limited hardware knowledge.]</p>