title: NULL statement in VHDL
body: <p>What is the actual purpose of <code>null</code> statement in VHDL? Consider the following codes</p>
  
  <p>1-</p>
  
  <pre><code>CASE s IS
  BEGIN
       WHEN 0 =&gt;    y &lt;= 0;
       WHEN 1 =&gt;    NULL;
  END CASE;
  </code></pre>
  
  <p>2-</p>
  
  <pre><code>CASE s IS
  BEGIN
       WHEN 0 =&gt;    y &lt;= 0;
  END CASE;
  </code></pre>
  
  <p>In the second code, since there is no assignment when <code>s=1</code>, then <code>y</code> retains it previous value. Isn't that? So, I think in both cases, the synthesizer will put a flip flop to keep the previous value of <code>y</code>.</p>