title: Instruction accesses in Gem5 for ARM processor
body: <p>I used Gem5 to obtain instruction accesses for ARM processor. I used -marm option to generate code. </p>
  
  <pre><code>arm-linux-gnueabihf-gcc -static -marm fibcall.c
  </code></pre>
  
  <p>I believe that only 32-bit ARM instructions are generated using this option. But the result is shown below:</p>
  
  <pre><code>command line: ./build/ARM/gem5.opt --debug-flags=Exec configs/example/se.py -c tests/test-progs/malardalen/a.out
  
  Global frequency set at 1000000000000 ticks per second
  **** REAL SIMULATION ****
  info: Entering event queue @ 0.  Starting simulation...
        0: system.cpu T0 : @fini+15    :   mov.w   fp, #0           : IntAlu :  D=0x0000000000000000
      500: system.cpu T0 : @_start+3    :   mov.w   lr, #0           : IntAlu :  D=0x0000000000000000
     1000: system.cpu T0 : @_start+7    : ldmstm
     1000: system.cpu T0 : @_start+7.0  :   ldr_uop   r1, [sp, #0]   : MemRead :  D=0x0000000000000001 A=0xbeffff00
     1500: system.cpu T0 : @_start+7.1  :   addi_uop   sp, sp, #4    : IntAlu :  D=0x00000000beffff04
     2000: system.cpu T0 : @_start+9    :   mov   r2, sp             : IntAlu :  D=0x00000000beffff04
     2500: system.cpu T0 : @_start+11    : ldmstm
     2500: system.cpu T0 : @_start+11.0  :   str_uop   r2, [sp, #4]   : MemWrite :  D=0x00000000beffff04 A=0xbeffff00
     3000: system.cpu T0 : @_start+11.1  :   subi_uop   sp, sp, #4    : IntAlu :  D=0x00000000beffff00
     3500: system.cpu T0 : @_start+13    : ldmstm
     3500: system.cpu T0 : @_start+13.0  :   str_uop   r0, [sp, #4]   : MemWrite :  D=0x0000000000000000 A=0xbefffefc
     4000: system.cpu T0 : @_start+13.1  :   subi_uop   sp, sp, #4    : IntAlu :  D=0x00000000befffefc
     4500: system.cpu T0 : @_start+15    :   ldr.w   r12, [pc, #16]   : MemRead :  D=0x0000000000009039 A=0x88d8
     5000: system.cpu T0 : @_start+19    :   str.w   r12, [sp, #-4]!
     5000: system.cpu T0 : @_start+19.0  :   str.w   r12, [sp, #-4]!  : MemWrite :  D=0x0000000000009039 A=0xbefffef8
     5500: system.cpu T0 : @_start+19.1  :   subi_uop.w   sp, sp, #4  : IntAlu :  D=0x00000000befffef8
     6000: system.cpu T0 : @_start+23    :   ldr   r0, [pc, #12]      : MemRead :  D=0x0000000000008a4c A=0x88dc
  
  ...
  </code></pre>
  
  <p>We can see that at 2000, _start+9 is used, which is 2 bytes from _start+7. So I think a 16-bit instruction is used. Why is it so? Why is it not 32-bit?</p>
  
  <p>Besides, does anyone know what _start+7.0 and _start+7.1 mean? Why do I have two different instructions with the same memory address? </p>
  
  <p>Thanks in advance.</p>