title: VHDL assignment slice not implemented?
body: <p>Is it possible to specify a bit range to be assigned on the left side of the assignment? </p>
  
  <p>eg. <code>R(15 downto 8) &lt;= R(15 downto 8) -D;</code></p>
  
  <p>The above gives me the compiler error: <code>Error 722: Assignment to a signal slice is not implemented.</code> I've tried Googling the error to no avail.</p>
  
  <p>However this works:</p>
  
  <p><code>R &lt;= R(15 downto 8) - D;</code></p>