title: Division in VHDL
body: <p>I am trying to divide two 32 bit std_logic_vector signals (see code below). both inputs are variable.
  when I write a separate module and test it, it's OK but when I use it as a part of the other module it can not be simulated. Simulation has no error but it's stopped and links me to this module.
  by the way I'm working with Xilinx</p>
  
  <pre><code>library IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.NUMERIC_STD.ALL;
  entity DivEx is
  port(
      X   : in STD_LOGIC_VECTOR(31 downto 0);
      Y   : in STD_LOGIC_VECTOR(31 downto 0);
      R   : out STD_LOGIC_VECTOR(31 downto 0)
  );
  end DivEx;
  
  architecture Behavioral of DivEx is
  begin
  R &lt;= std_logic_vector(to_signed(to_integer(signed(X) / signed(Y)),32));
  end Behavioral;
  </code></pre>