title: Modelsim Optimization Issue
body: <p>I am having problem when I am trying to run the following verilog code snippet in Optimized mode using Modelsim simulator v10.2c.</p>
  
  <pre><code>always @ *
    if (dut.rtl_module.enable == 1'b1)
      force dut.rtl_module.abc_reg = xyz;
  </code></pre>
  
  <p>If the above snippet is run in non-optimized mode, this works fine. But for optimized mode, it fails.</p>
  
  <p>PS: I am using -O5 optimization level</p>