title: VHDL assigning decimal values to std_logic_vector
body: <p>I'm trying to add a decimal value to a 10 bit std_logic_vector without having to describe every bit. Though it might not be worth the trouble in this particular scenario, i believe it will be very good to know in the future. 
  So far i have:</p>
  
  <pre><code>    signal h_cnt : std_logic_vector(9 downto 0);
      ... --code
      h_cnt &lt;= std_logic_vector(to_unsigned(9, 10));
  </code></pre>
  
  <p>I get an error message saying:</p>
  
  <blockquote>
    <p>*Error (10482): VHDL error at vhdl_vga.vhd(70): object "to_unsigned" is used but not declared
    *</p>
  </blockquote>
  
  <p>could anyone help me with this one?</p>
  
  <p>Thanks in advance</p>