title: How to solve the 32-byte-alignment issue for AVX load/store operations?
body: <p>I am having alignment issue while using <code>ymm</code> registers, with some snippets of code that seems fine to me. Here is a minimal working example:</p>
  
  <pre><code>#include &lt;iostream&gt; 
  #include &lt;immintrin.h&gt;
  
  inline void ones(float *a)
  {
       __m256 out_aligned = _mm256_set1_ps(1.0f);
       _mm256_store_ps(a,out_aligned);
  }
  
  int main()
  {
       size_t ss = 8;
       float *a = new float[ss];
       ones(a);
  
       delete [] a;
  
       std::cout &lt;&lt; "All Good!" &lt;&lt; std::endl;
       return 0;
  }
  </code></pre>
  
  <p>Certainly, <code>sizeof(float)</code> is <code>4</code> on my architecture (<a href="http://ark.intel.com/products/64590/Intel-Xeon-Processor-E5-2650-20M-Cache-2_00-GHz-8_00-GTs-Intel-QPI" rel="noreferrer">Intel(R) Xeon(R) CPU E5-2650 v2 @ 2.60GHz</a>) and I'm compiling with <code>gcc</code> using <code>-O3 -march=native</code> flags. Of course the error goes away with unaligned memory access i.e. specifying <code>_mm256_storeu_ps</code>. I also do not have this problem on <code>xmm</code> registers, i.e. </p>
  
  <pre><code>inline void ones_sse(float *a)
  {
       __m128 out_aligned = _mm_set1_ps(1.0f);
       _mm_store_ps(a,out_aligned);
  }
  </code></pre>
  
  <p>Am I doing anything foolish? what is the work-around for this?</p>