title: Verilog code adding two integers generated by a for loop
body: <p>How about this? I'm looking for an output i+j=1+2, 2+3... 4+5.  </p>
  
  <pre><code>module add(i,j,b);
    input [31:0] i, j; //32 bit unsigned 
    output [31:0] y; 
  
    task ADD(i, j, y); 
    begin 
      for (i= 1; i &lt;= 4; i++) 
        begin 
        for(j=2; j &lt;= 5; j++) 
          assign y = i + j; 
        end
      end 
      $display("y ", y); 
    endtask 
  endmodule
  </code></pre>