title: VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?
body: <p>Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (<em>i.e if MAXVAL=5, then bitwidth= {<code>wcalc "floor(logtwo($MAXVAL))+1"</code>}</em>). </p>
  
  <p>I'm aware I could do: </p>
  
  <pre><code>SIGNAL myLogicVector : STD_LOGIC_VECTOR(2 downto 0) := 5; 
  </code></pre>
  
  <p>with which I'd explicitly specify an array of three std_logic 'bits', and set initial value; then I could use REPORT to print out the length (in this case, 3): </p>
  
  <pre><code>report("Bit width of myLogicVector is "&amp; integer'image(myLogicVector'length));
  </code></pre>
  
  <p>So far, so good. But, let's say I use an integer (number) type instead: </p>
  
  <pre><code>SIGNAL myInteger : NATURAL range 0 to 5 := 5;
  </code></pre>
  
  <p>I'm guessing that here the 'compiler' ('synthesizer') would <em>automatically</em> infer that it needs 3 bits of storage length, as this integer is ranged with values between 0 and 5. If that is the case, my <strong>question</strong> is: is it possible to somehow print out this bit width/length/size in a REPORT? </p>
  
  <p>The trick is, of course, that something like this: </p>
  
  <pre><code>report("Bit width of myInteger is "&amp; integer'image(myInteger'length));
  </code></pre>
  
  <p>... will fail (say, with "<em>HDLParsers:3389 - Prefix of attribute 'length must be an array object</em>"), since as far as I gather, all these attributes like <code>'length</code> and <code>'range</code> are applicable only to <em>arrays</em> (<a href="http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/objects__data_types_and_operators/understanding_vhdl_attributes.htm">Understanding VHDL Attributes</a>), whereas an integer (natural) is not an array - it is a <em>number</em> :) (<a href="http://www.edaboard.com/thread107009.html">VHDL vector integer conversion question</a>)</p>
  
  <p>Again, I'm aware I could possibly utilize a log2 (<a href="http://www.velocityreviews.com/forums/t377631-computing-the-width-of-an-unsigned-variable-from-maximum-value.html">Computing the width of an unsigned variable from maximum value?</a>) - but what I'd like is just to see quickly (<em>during synthesis</em>) how many 'bits' the 'synthesizer' allocated for an eventual synthesized design, and thus approx how much would be used in terms of final FPGA resources (<em>especially if I'd use 'generics' to somehow calculate a particular max value for an integer</em>).</p>
  
  <p>Well, thanks in advance for any responses, 
  Cheers! </p>
  
  <p>EDIT: a bit of context: I'm using ISE Webpack 9.2; I'm trying to use 'generic' variables/constants as parameters, and then use equations to calculate max values for counters. This calculation, I guess occurs at 'compile' time (which would be 'Synthesize' in ISE - not 'Implement Design'), and so it is here where I want the report messages to occur (<em>and I in fact got them so, for std_logic_vector proper, in the synthesis log - however, the same report messages for me occur at start of behavioral simulation too, which is fine</em>). </p>
  
  <p>And the goal of these report messages is to make sure both that my equations are OK, and that the synthesizer will not try to infer a 32-bit counter - even if I want to count just from 0 to 5 :)  </p>