title: How to combine multiple arrays into one array in Verilog?
body: <p>Here is my code:</p>
  
  <pre><code>module MIPS_Processor();
      reg [7:0] mem [0:4095];      // 4K memory cells that are 8 bits wide
      reg [7:0] code[0:1023];      // 1K memory cells that are 8 bits wide
      reg [31:0] registers[0:31];  // 32 registers that are 32 bits wide
      reg [31:0] PC;               // The program counter
  
      initial
          begin
              PC = 0;
          end
  
      always
          begin
              // 1. Fetch an instruction from memory
              bit [31:0] instruction = {{code[PC * 8 + 7:PC * 8 + 0]},
                                       {code[(PC + 1) * 8 + 7:(PC + 1) * 8 + 0]},
                                       {code[(PC + 2) * 8 + 7:(PC + 2) * 8 + 0]},
                                       {code[(PC + 3) * 8 + 7:(PC + 3) * 8 + 0]}};
  
              // 2. Increment the program counter register (by the instruction length)
              PC = PC + 4;
  
              // Rest of the code
  
      end
  endmodule
  </code></pre>
  
  <p>How can I combine the 4 arrays into one array to fetch the instruction from the code? The code above does not compile!</p>
  
  <hr>
  
  <p><strong>EDIT:</strong></p>
  
  <p>After changing the code to what @toolic suggested:</p>
  
  <pre><code>bit [31:0] instruction = {
                       code[PC + 0],
                       code[PC + 1],
                       code[PC + 2],
                       code[PC + 3]
  };
  </code></pre>
  
  <p>still, it does not compile:</p>
  
  <p>Using Xilinx:</p>
  
  <pre><code>=========================================================================
  *                          HDL Compilation                              *
  =========================================================================
  Compiling verilog file "MIPS_Processor.v" in library work
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 expecting ']', found ':'
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '='
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '{'
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 40 expecting '.', found ','
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 41 expecting '.', found ','
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 42 expecting '.', found ','
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 44 expecting '.', found '}'
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: '='
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: 'PC'
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'end', found '+'
  Module &lt;MIPS_Processor&gt; compiled
  ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'endmodule', found '4'
  Analysis of file &lt;"MIPS_Processor.prj"&gt; failed.
  --&gt; 
  
  Total memory usage is 274336 kilobytes
  
  Number of errors   :   11 (   0 filtered)
  Number of warnings :    0 (   0 filtered)
  Number of infos    :    0 (   0 filtered)
  
  
  Process "Synthesize - XST" failed
  </code></pre>
  
  <p>Using Verilogger Extreme:</p>
  
  <p><img src="https://i.stack.imgur.com/HpIub.png" alt="enter image description here"></p>