title: How are atomic operations implemented at a hardware level?
body: <p>I get that at the assembly language level instruction set architectures provide compare and swap and similar operations. However, I don't understand how the chip is able to provide these guarantees.</p>
  
  <p>As I imagine it, the execution of the instruction must</p>
  
  <ol>
  <li>Fetch a value from memory</li>
  <li>Compare the value</li>
  <li>Depending on the comparison, possibly store another value in memory</li>
  </ol>
  
  <p>What prevents another core from accessing the memory address after the first has fetched it but before it sets the new value? Does the memory controller manage this?</p>
  
  <p>edit: If the x86 implementation is secret, I'd be happy to hear how any processor family implements it.</p>