title: counter system verilog code
body: <p>I am having problem with this counter. the output is all xxxxxxxx, I know I should set the initial value of count and overflow to 0 but it gives an error that way. this is the code: </p>
  
  <pre><code>// Code your design here
  module counter (in, start, count, clk, overflow);
  
  input [3:0] in;
  input clk;
  input start;
  output reg [7:0] count;
  output reg overflow;
  //reg count;
  //count =0;
  //overflow=0;
  always @ (posedge clk)
    begin
      if (start) begin
        count &lt;= 8'b0;
        overflow &lt;= 1'b0;
      end
  
      else if (in == 4'b0101) begin
        count &lt;= count+1;
      end
      if (count == 4'b1111) begin
        overflow &lt;=1'b1;
      end
    end
  
  endmodule
  </code></pre>
  
  <p>this is the testbench:</p>
  
  <pre><code>// Code your testbench here
  // or browse Examples
  module tb();
  
    reg [3:0] in;
    reg clk,start;
    wire [7:0] count;
    reg overflow = 1'b0;
  
    initial begin
  
      $display ("time\t clk start in count overflow");
      $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow);
  
      clk=0;
      in=0;
      start=0;
     // overflow=0;
     // count=0;
  
      #5 in=4'd1;
      #5 in=4'd5;
      #5 in=4'd4;
      #5 in=5'd5;
      #5 in=4'd1;
      #5 in=4'd5;
      #5 in=4'd4;
      #5 in=5'd5;
      #5 in=4'd1;
      #5 in=4'd5;
      #5 in=4'd4;
      #5 in=5'd5;
      #5 in=4'd1;
      #5 in=4'd5;
      #5 in=4'd4;
      #5 in=5'd5;
      #50 $finish;
  
    end
  
      always #5 clk=~clk;
  
    counter u0(.*);
  
  endmodule
  </code></pre>
  
  <p>I know it is a simple question, but I appreciate it if you guys help out.</p>