title: Submodules in Verilog
body: <p>In Verilog, you can create a module simply with the module syntax. How do you create multiple modules and call one from the other? </p>
  
  <p>I have the following module that is my main module:</p>
  
  <pre><code>module Lab7Part1(SW, HEX0, HEX1, HEX2, HEX3);
          input  [15:0] SW;
          output [7:0] HEX0;
          output [7:0] HEX1;
          output [7:0] HEX2;
          output [7:0] HEX3;
  
          reg [7:0] OUTT;
  
          reg [7:0] ONE    = 8'b1001111;
  
          //SingleConverter sin_1(SW[3:0],   HEX0);
          //SingleConverter sin_2(SW[7:4],   HEX1);
          //SingleConverter sin_3(SW[11:8],  HEX2);
          //SingleConverter sin_4(SW[15:12], HEX3);
  endmodule
  </code></pre>
  
  <p>and the following 'submodule' that I wish to 'call' in the main module:</p>
  
  <pre><code>module SingleConverter(SW, HEX);
      input  SW;
      output HEX;
  
      reg [7:0] OUT;
  
      reg [7:0] ZERO   = 8'b1000000;
      reg [7:0] ONE    = 8'b1001111;
      reg [7:0] TWO    = 8'b0100100;
      reg [7:0] THREE  = 8'b0110000;
      reg [7:0] FOUR   = 8'b0011001;
      reg [7:0] FIVE   = 8'b0010010;
      reg [7:0] SIX    = 8'b0000010;
      reg [7:0] SEVEN  = 8'b1111000;
      reg [7:0] EIGHT  = 8'b0000000;
      reg [7:0] NINE   = 8'b0011000;
      reg [7:0] DC     = 8'b1111111;
  
      always@(1'b0==1'b0)
      begin
          // SW
          if (SW == 4'b0000)
          begin
          // 0
              OUT[7:0] = ZERO;
          end
          if (SW == 4'b0001)
          begin
          // 1
              OUT[7:0] = ONE;
          end
          if (SW == 4'b0010)
          begin
          //2
              OUT[7:0] = TWO;
          end
          if (SW == 4'b0011)
          begin
          // 3
              OUT[7:0] = THREE;
          end
          if (SW == 4'b0100)
          begin
          // 4
              OUT[7:0] = FOUR;
          end
          if (SW == 4'b0101)
          begin
          //5
              OUT[7:0] = FIVE;
          end
          if (SW == 4'b0110)
          begin
          // 6
              OUT[7:0] = SIX;
          end
          if (SW == 4'b0111)
          begin
          // 7
              OUT[7:0] = SEVEN;
          end
          if (SW == 4'b1000)
          begin
          //8
              OUT[7:0] = EIGHT;
          end
          if (SW == 4'b1001)
          begin
          // 9
              OUT[7:0] = NINE;
          end
          if (SW &gt; 4'b1001)
          begin
          // dc
              OUT[7:0] = DC;
          end
      end
  
      assign HEX = OUT;
  
  endmodule
  </code></pre>