title: Calling modules in Verilog/using generate
body: <p>I'm trying to combine two modules I wrote to create an addder/subtractor module but am having issues piecing it together. Below is what I have so far:</p>
  
  <pre><code>`include "invert.v"          //since I'll be using 2s complement for subtraction
  `include "add.v"             //basic add which also produces an overflow bit
  
  module addsub(A,B,O,overflow);
  
  input  [7:0] A,B;
  output [7:0] O;
  output       overflow;
  
  wire [7:0] notB;
                      //active high
  generate
     if(B[7] == 1)
       invert iv1(B,notB);
       add ad1(A,notB,O,overflow);
     else(B[7] == 0)
       add ad2(A,B,O,overflow);
  endgenerate
  
  endmodule
  </code></pre>
  
  <p>and these are the errors I'm receiving:</p>
  
  <p>Error-[MPD] Module previously declared
    The module was previously declared at:
    "invert.v", 3
    It is redeclared later at:
    "invert.v", 3: token is 'invert'
    module invert(in,out);
                 ^
    Please remove one of the declarations and compile again.</p>
  
  <p>Back to file 'add.v'.
  Back to file 'addsub.v'.</p>
  
  <p>Error-[SE] Syntax error
    Following verilog source has syntax error :
    "addsub.v", 17: token is 'else'
       else(B[7] == 0)
           ^
  2 errors</p>
  
  <p>I'm a total newbie to verilog so any help is much appreciated!</p>
  
  <p>-edit- adder and invert listed below:</p>
  
  <pre><code>//adder  
  module add(A,B,O,co);
  
  input  [7:0] A,B;
  output [7:0] O;
  output reg co;
  
  wire [8:0] tmp;
  
  assign tmp = A+B;
  assign O = tmp[7:0];
  
  always@*
  begin
    if(tmp[8] == 1)
      assign co = 1;
    else if(tmp[8] == 0)
      assign co = 0;
  end
  
  endmodule
  
  //inverter
  module invert(in,out);
  
  input     [7:0] in;
  output    [7:0] out;
  
  assign out[0] =  ~in[0];
  assign out[1] =  ~in[1];
  assign out[2] =  ~in[2];
  assign out[3] =  ~in[3];
  assign out[4] =  ~in[4];
  assign out[5] =  ~in[5];
  assign out[6] =  ~in[6];
  assign out[7] =  ~in[7];
  
  endmodule
  </code></pre>