title: i2c communication in vhdl, an X bit when going form master ack to first bit read vhdl
body: <p>I've got a problem with i2c master acknowledgment for the slave that the data sent were ok. In my test bench i give a Z on SDA bus so that master could do the acknowledgment, but after the ack from master (it's 0) i sand a nother part of data and when i go from master ack 0 on the SDA bus to '1' as the first bit to be sent form the slave, I get an X state od the first bit. It's like it wouldn't appear if the bus was Z. Is it the simulation problem or am I just doing it wrong that i get that result? Will it appear in reality or the slave will give a Z on the SDA bus for longer? Belowe i give the simulation code and the waveforms.</p>
  
  <pre><code> sda &lt;='Z', 
      '0' after 3200 ps, 
      'Z' after 3400 ps,
      '0' after 5800 ps, 
      'Z' after 6000 ps,
      '0' after 8600 ps, 
      'Z' after 8800 ps,
      '0' after 11600 ps, 
      '1' after 11850 ps,------ start first byte
      '1' after 12150 ps,
      '0' after 13050 ps,
      '1' after 13350 ps,
      '0' after 13650 ps, ----- end first byte 
      'Z' after 14250 ps,------ Z for master ack
      '1' after 14550 ps,------ start second byte
      '0' after 14850 ps,
      '1' after 16650 ps,------ end second byte
      'Z' after 16950 ps,------ Z for master ack
      '1' after 17250 ps,------ start third byte
      '1' after 17550 ps,
      '0' after 18150 ps,
      '1' after 18750 ps,
      '0' after 19350 ps,------ end third byte
      'Z' after 19650 ps;------ Z for master ack
  </code></pre>
  
  <p><img src="https://i.stack.imgur.com/xLOYz.jpg" alt="waveform"></p>