title: ARM program example with Keil Uvision startup file
body: <p>Sorry, I am newbie, I am just starting to explore assembly with ARM. 
  I am trying to run example from the book </p>
  
  <pre><code>        AREA Prog1, CODE, READONLY
          ENTRY
          MOV r0, #0x11 ; load initial value
          LSL r1, r0, #1 ; shift 1 bit left
          LSL r2, r1, #1 ; shift 1 bit left
  stop    B stop ; stop program
          END
  </code></pre>
  
  <p>But as far as I know program should have RESET area vector set in order to start execution. 
  So I added <code>Startup.s</code> file into my project</p>
  
  <pre><code>;/*****************************************************************************/
  ;/* STARTUP.S: Startup file for Philips LPC2000                               */
  ;/*****************************************************************************/
  ;/* &lt;&lt;&lt; Use Configuration Wizard in Context Menu &gt;&gt;&gt;                          */ 
  ;/*****************************************************************************/
  ;/* This file is part of the uVision/ARM development tools.                   */
  ;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.               */
  ;/* This software may only be used under the terms of a valid, current,       */
  ;/* end user licence from KEIL for a compatible version of KEIL software      */
  ;/* development tools. Nothing else gives you the right to use this software. */
  ;/*****************************************************************************/
  
  
  ;/*
  ; *  The STARTUP.S code is executed after CPU Reset. This file may be 
  ; *  translated with the following SET symbols. In uVision these SET 
  ; *  symbols are entered under Options - ASM - Define.
  ; *
  ; *  REMAP: when set the startup code initializes the register MEMMAP 
  ; *  which overwrites the settings of the CPU configuration pins. The 
  ; *  startup and interrupt vectors are remapped from:
  ; *     0x00000000  default setting (not remapped)
  ; *     0x80000000  when EXTMEM_MODE is used
  ; *     0x40000000  when RAM_MODE is used
  ; *
  ; *  EXTMEM_MODE: when set the device is configured for code execution
  ; *  from external memory starting at address 0x80000000.
  ; *
  ; *  RAM_MODE: when set the device is configured for code execution
  ; *  from on-chip RAM starting at address 0x40000000.
  ; *
  ; *  EXTERNAL_MODE: when set the PIN2SEL values are written that enable
  ; *  the external BUS at startup.
  ; */
  
  
  ; Standard definitions of Mode bits and Interrupt (I &amp; F) flags in PSRs
  
  Mode_USR        EQU     0x10
  Mode_FIQ        EQU     0x11
  Mode_IRQ        EQU     0x12
  Mode_SVC        EQU     0x13
  Mode_ABT        EQU     0x17
  Mode_UND        EQU     0x1B
  Mode_SYS        EQU     0x1F
  
  I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
  F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
  
  
  ;// &lt;h&gt; Stack Configuration (Stack Sizes in Bytes)
  ;//   &lt;o0&gt; Undefined Mode      &lt;0x0-0xFFFFFFFF:8&gt;
  ;//   &lt;o1&gt; Supervisor Mode     &lt;0x0-0xFFFFFFFF:8&gt;
  ;//   &lt;o2&gt; Abort Mode          &lt;0x0-0xFFFFFFFF:8&gt;
  ;//   &lt;o3&gt; Fast Interrupt Mode &lt;0x0-0xFFFFFFFF:8&gt;
  ;//   &lt;o4&gt; Interrupt Mode      &lt;0x0-0xFFFFFFFF:8&gt;
  ;//   &lt;o5&gt; User/System Mode    &lt;0x0-0xFFFFFFFF:8&gt;
  ;// &lt;/h&gt;
  
  UND_Stack_Size  EQU     0x00000000
  SVC_Stack_Size  EQU     0x00000008
  ABT_Stack_Size  EQU     0x00000000
  FIQ_Stack_Size  EQU     0x00000000
  IRQ_Stack_Size  EQU     0x00000080
  USR_Stack_Size  EQU     0x00000400
  
  ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                           FIQ_Stack_Size + IRQ_Stack_Size)
  
                  AREA    STACK, NOINIT, READWRITE, ALIGN=3
  
  Stack_Mem       SPACE   USR_Stack_Size
  __initial_sp    SPACE   ISR_Stack_Size
  
  Stack_Top
  
  
  ;// &lt;h&gt; Heap Configuration
  ;//   &lt;o&gt;  Heap Size (in Bytes) &lt;0x0-0xFFFFFFFF&gt;
  ;// &lt;/h&gt;
  
  Heap_Size       EQU     0x00000000
  
                  AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  __heap_base
  Heap_Mem        SPACE   Heap_Size
  __heap_limit
  
  
  ; VPBDIV definitions
  VPBDIV          EQU     0xE01FC100      ; VPBDIV Address
  
  ;// &lt;e&gt; VPBDIV Setup
  ;// &lt;i&gt; Peripheral Bus Clock Rate
  ;//   &lt;o1.0..1&gt;   VPBDIV: VPB Clock
  ;//               &lt;0=&gt; VPB Clock = CPU Clock / 4
  ;//               &lt;1=&gt; VPB Clock = CPU Clock
  ;//               &lt;2=&gt; VPB Clock = CPU Clock / 2
  ;//   &lt;o1.4..5&gt;   XCLKDIV: XCLK Pin
  ;//               &lt;0=&gt; XCLK Pin = CPU Clock / 4
  ;//               &lt;1=&gt; XCLK Pin = CPU Clock
  ;//               &lt;2=&gt; XCLK Pin = CPU Clock / 2
  ;// &lt;/e&gt;
  VPBDIV_SETUP    EQU     0
  VPBDIV_Val      EQU     0x00000000
  
  
  ; Phase Locked Loop (PLL) definitions
  PLL_BASE        EQU     0xE01FC080      ; PLL Base Address
  PLLCON_OFS      EQU     0x00            ; PLL Control Offset
  PLLCFG_OFS      EQU     0x04            ; PLL Configuration Offset
  PLLSTAT_OFS     EQU     0x08            ; PLL Status Offset
  PLLFEED_OFS     EQU     0x0C            ; PLL Feed Offset
  PLLCON_PLLE     EQU     (1&lt;&lt;0)          ; PLL Enable
  PLLCON_PLLC     EQU     (1&lt;&lt;1)          ; PLL Connect
  PLLCFG_MSEL     EQU     (0x1F&lt;&lt;0)       ; PLL Multiplier
  PLLCFG_PSEL     EQU     (0x03&lt;&lt;5)       ; PLL Divider
  PLLSTAT_PLOCK   EQU     (1&lt;&lt;10)         ; PLL Lock Status
  
  ;// &lt;e&gt; PLL Setup
  ;//   &lt;o1.0..4&gt;   MSEL: PLL Multiplier Selection
  ;//               &lt;1-32&gt;&lt;#-1&gt;
  ;//               &lt;i&gt; M Value
  ;//   &lt;o1.5..6&gt;   PSEL: PLL Divider Selection
  ;//               &lt;0=&gt; 1   &lt;1=&gt; 2   &lt;2=&gt; 4   &lt;3=&gt; 8
  ;//               &lt;i&gt; P Value
  ;// &lt;/e&gt;
  PLL_SETUP       EQU     1
  PLLCFG_Val      EQU     0x00000024
  
  
  ; Memory Accelerator Module (MAM) definitions
  MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
  MAMCR_OFS       EQU     0x00            ; MAM Control Offset
  MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset
  
  ;// &lt;e&gt; MAM Setup
  ;//   &lt;o1.0..1&gt;   MAM Control
  ;//               &lt;0=&gt; Disabled
  ;//               &lt;1=&gt; Partially Enabled
  ;//               &lt;2=&gt; Fully Enabled
  ;//               &lt;i&gt; Mode
  ;//   &lt;o2.0..2&gt;   MAM Timing
  ;//               &lt;0=&gt; Reserved  &lt;1=&gt; 1   &lt;2=&gt; 2   &lt;3=&gt; 3
  ;//               &lt;4=&gt; 4         &lt;5=&gt; 5   &lt;6=&gt; 6   &lt;7=&gt; 7
  ;//               &lt;i&gt; Fetch Cycles
  ;// &lt;/e&gt;
  MAM_SETUP       EQU     1
  MAMCR_Val       EQU     0x00000002
  MAMTIM_Val      EQU     0x00000004
  
  
  ; External Memory Controller (EMC) definitions
  EMC_BASE        EQU     0xFFE00000      ; EMC Base Address
  BCFG0_OFS       EQU     0x00            ; BCFG0 Offset
  BCFG1_OFS       EQU     0x04            ; BCFG1 Offset
  BCFG2_OFS       EQU     0x08            ; BCFG2 Offset
  BCFG3_OFS       EQU     0x0C            ; BCFG3 Offset
  
  ;// &lt;e&gt; External Memory Controller (EMC)
  EMC_SETUP       EQU     0
  
  ;//   &lt;e&gt; Bank Configuration 0 (BCFG0)
  ;//     &lt;o1.0..3&gt;   IDCY: Idle Cycles &lt;0-15&gt;
  ;//     &lt;o1.5..9&gt;   WST1: Wait States 1 &lt;0-31&gt;
  ;//     &lt;o1.11..15&gt; WST2: Wait States 2 &lt;0-31&gt;
  ;//     &lt;o1.10&gt;     RBLE: Read Byte Lane Enable
  ;//     &lt;o1.26&gt;     WP: Write Protect
  ;//     &lt;o1.27&gt;     BM: Burst ROM
  ;//     &lt;o1.28..29&gt; MW: Memory Width  &lt;0=&gt;  8-bit  &lt;1=&gt; 16-bit
  ;//                                   &lt;2=&gt; 32-bit  &lt;3=&gt; Reserved
  ;//   &lt;/e&gt;
  BCFG0_SETUP EQU         0
  BCFG0_Val   EQU         0x0000FBEF
  
  ;//   &lt;e&gt; Bank Configuration 1 (BCFG1)
  ;//     &lt;o1.0..3&gt;   IDCY: Idle Cycles &lt;0-15&gt;
  ;//     &lt;o1.5..9&gt;   WST1: Wait States 1 &lt;0-31&gt;
  ;//     &lt;o1.11..15&gt; WST2: Wait States 2 &lt;0-31&gt;
  ;//     &lt;o1.10&gt;     RBLE: Read Byte Lane Enable
  ;//     &lt;o1.26&gt;     WP: Write Protect
  ;//     &lt;o1.27&gt;     BM: Burst ROM
  ;//     &lt;o1.28..29&gt; MW: Memory Width  &lt;0=&gt;  8-bit  &lt;1=&gt; 16-bit
  ;//                                   &lt;2=&gt; 32-bit  &lt;3=&gt; Reserved
  ;//   &lt;/e&gt;
  BCFG1_SETUP EQU         0
  BCFG1_Val   EQU         0x0000FBEF
  
  ;//   &lt;e&gt; Bank Configuration 2 (BCFG2)
  ;//     &lt;o1.0..3&gt;   IDCY: Idle Cycles &lt;0-15&gt;
  ;//     &lt;o1.5..9&gt;   WST1: Wait States 1 &lt;0-31&gt;
  ;//     &lt;o1.11..15&gt; WST2: Wait States 2 &lt;0-31&gt;
  ;//     &lt;o1.10&gt;     RBLE: Read Byte Lane Enable
  ;//     &lt;o1.26&gt;     WP: Write Protect
  ;//     &lt;o1.27&gt;     BM: Burst ROM
  ;//     &lt;o1.28..29&gt; MW: Memory Width  &lt;0=&gt;  8-bit  &lt;1=&gt; 16-bit
  ;//                                   &lt;2=&gt; 32-bit  &lt;3=&gt; Reserved
  ;//   &lt;/e&gt;
  BCFG2_SETUP EQU         0
  BCFG2_Val   EQU         0x0000FBEF
  
  ;//   &lt;e&gt; Bank Configuration 3 (BCFG3)
  ;//     &lt;o1.0..3&gt;   IDCY: Idle Cycles &lt;0-15&gt;
  ;//     &lt;o1.5..9&gt;   WST1: Wait States 1 &lt;0-31&gt;
  ;//     &lt;o1.11..15&gt; WST2: Wait States 2 &lt;0-31&gt;
  ;//     &lt;o1.10&gt;     RBLE: Read Byte Lane Enable
  ;//     &lt;o1.26&gt;     WP: Write Protect
  ;//     &lt;o1.27&gt;     BM: Burst ROM
  ;//     &lt;o1.28..29&gt; MW: Memory Width  &lt;0=&gt;  8-bit  &lt;1=&gt; 16-bit
  ;//                                   &lt;2=&gt; 32-bit  &lt;3=&gt; Reserved
  ;//   &lt;/e&gt;
  BCFG3_SETUP EQU         0
  BCFG3_Val   EQU         0x0000FBEF
  
  ;// &lt;/e&gt; End of EMC
  
  
  ; External Memory Pins definitions
  PINSEL2         EQU     0xE002C014      ; PINSEL2 Address
  PINSEL2_Val     EQU     0x0E6149E4      ; CS0..3, OE, WE, BLS0..3, 
                                          ; D0..31, A2..23, JTAG Pins
  
  
                  PRESERVE8
  
  
  ; Area Definition and Entry Point
  ;  Startup Code must be linked first at Address at which it expects to run.
  
                  AREA    RESET, CODE, READONLY
                  ARM
  
  
  ; Exception Vectors
  ;  Mapped to Address 0.
  ;  Absolute addressing mode must be used.
  ;  Dummy Handlers are implemented as infinite loops which can be modified.
  
  Vectors         LDR     PC, Reset_Addr         
                  LDR     PC, Undef_Addr
                  LDR     PC, SWI_Addr
                  LDR     PC, PAbt_Addr
                  LDR     PC, DAbt_Addr
                  NOP                            ; Reserved Vector 
  ;               LDR     PC, IRQ_Addr
                  LDR     PC, [PC, #-0x0FF0]     ; Vector from VicVectAddr
                  LDR     PC, FIQ_Addr
  
  Reset_Addr      DCD     Reset_Handler
  Undef_Addr      DCD     Undef_Handler
  SWI_Addr        DCD     SWI_Handler
  PAbt_Addr       DCD     PAbt_Handler
  DAbt_Addr       DCD     DAbt_Handler
                  DCD     0                      ; Reserved Address 
  IRQ_Addr        DCD     IRQ_Handler
  FIQ_Addr        DCD     FIQ_Handler
  
  Undef_Handler   B       Undef_Handler
  SWI_Handler     B       SWI_Handler
  PAbt_Handler    B       PAbt_Handler
  DAbt_Handler    B       DAbt_Handler
  IRQ_Handler     B       IRQ_Handler
  FIQ_Handler     B       FIQ_Handler
  
  
  ; Reset Handler
  
                  EXPORT  Reset_Handler
  Reset_Handler   
  
  
  ; Setup External Memory Pins
                  IF      :DEF:EXTERNAL_MODE
                  LDR     R0, =PINSEL2
                  LDR     R1, =PINSEL2_Val
                  STR     R1, [R0]
                  ENDIF
  
  
  ; Setup External Memory Controller
                  IF      EMC_SETUP &lt;&gt; 0
                  LDR     R0, =EMC_BASE
  
                  IF      BCFG0_SETUP &lt;&gt; 0
                  LDR     R1, =BCFG0_Val
                  STR     R1, [R0, #BCFG0_OFS]
                  ENDIF
  
                  IF      BCFG1_SETUP &lt;&gt; 0
                  LDR     R1, =BCFG1_Val
                  STR     R1, [R0, #BCFG1_OFS]
                  ENDIF
  
                  IF      BCFG2_SETUP &lt;&gt; 0
                  LDR     R1, =BCFG2_Val
                  STR     R1, [R0, #BCFG2_OFS]
                  ENDIF
  
                  IF      BCFG3_SETUP &lt;&gt; 0
                  LDR     R1, =BCFG3_Val
                  STR     R1, [R0, #BCFG3_OFS]
                  ENDIF
  
                  ENDIF   ; EMC_SETUP
  
  
  ; Setup VPBDIV
                  IF      VPBDIV_SETUP &lt;&gt; 0
                  LDR     R0, =VPBDIV
                  LDR     R1, =VPBDIV_Val
                  STR     R1, [R0]
                  ENDIF
  
  
  ; Setup PLL
                  IF      PLL_SETUP &lt;&gt; 0
                  LDR     R0, =PLL_BASE
                  MOV     R1, #0xAA
                  MOV     R2, #0x55
  
  ;  Configure and Enable PLL
                  MOV     R3, #PLLCFG_Val
                  STR     R3, [R0, #PLLCFG_OFS] 
                  MOV     R3, #PLLCON_PLLE
                  STR     R3, [R0, #PLLCON_OFS]
                  STR     R1, [R0, #PLLFEED_OFS]
                  STR     R2, [R0, #PLLFEED_OFS]
  
  ;  Wait until PLL Locked
  PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
                  ANDS    R3, R3, #PLLSTAT_PLOCK
                  BEQ     PLL_Loop
  
  ;  Switch to PLL Clock
                  MOV     R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
                  STR     R3, [R0, #PLLCON_OFS]
                  STR     R1, [R0, #PLLFEED_OFS]
                  STR     R2, [R0, #PLLFEED_OFS]
                  ENDIF   ; PLL_SETUP
  
  
  ; Setup MAM
                  IF      MAM_SETUP &lt;&gt; 0
                  LDR     R0, =MAM_BASE
                  MOV     R1, #MAMTIM_Val
                  STR     R1, [R0, #MAMTIM_OFS] 
                  MOV     R1, #MAMCR_Val
                  STR     R1, [R0, #MAMCR_OFS] 
                  ENDIF   ; MAM_SETUP
  
  
  ; Memory Mapping (when Interrupt Vectors are in RAM)
  MEMMAP          EQU     0xE01FC040      ; Memory Mapping Control
                  IF      :DEF:REMAP
                  LDR     R0, =MEMMAP
                  IF      :DEF:EXTMEM_MODE
                  MOV     R1, #3
                  ELIF    :DEF:RAM_MODE
                  MOV     R1, #2
                  ELSE
                  MOV     R1, #1
                  ENDIF
                  STR     R1, [R0]
                  ENDIF
  
  
  ; Initialise Interrupt System
  ;  ...
  
  
  ; Setup Stack for each mode
  
                  LDR     R0, =Stack_Top
  
  ;  Enter Undefined Instruction Mode and set its Stack Pointer
                  MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                  MOV     SP, R0
                  SUB     R0, R0, #UND_Stack_Size
  
  ;  Enter Abort Mode and set its Stack Pointer
                  MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                  MOV     SP, R0
                  SUB     R0, R0, #ABT_Stack_Size
  
  ;  Enter FIQ Mode and set its Stack Pointer
                  MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                  MOV     SP, R0
                  SUB     R0, R0, #FIQ_Stack_Size
  
  ;  Enter IRQ Mode and set its Stack Pointer
                  MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                  MOV     SP, R0
                  SUB     R0, R0, #IRQ_Stack_Size
  
  ;  Enter Supervisor Mode and set its Stack Pointer
                  MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                  MOV     SP, R0
                  SUB     R0, R0, #SVC_Stack_Size
  
  ;  Enter User Mode and set its Stack Pointer
                  MSR     CPSR_c, #Mode_USR
                  IF      :DEF:__MICROLIB
  
                  EXPORT __initial_sp
  
                  ELSE
  
                  MOV     SP, R0
                  SUB     SL, SP, #USR_Stack_Size
  
                  ENDIF
  
  
  ; Enter the C code
  
                  IMPORT  __main
                  LDR     R0, =__main
                  BX      R0
  
  
                  IF      :DEF:__MICROLIB
  
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
  
                  ELSE
  ; User Initial Stack &amp; Heap
                  AREA    |.text|, CODE, READONLY
  
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
  __user_initial_stackheap
  
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + USR_Stack_Size)
                  LDR     R2, = (Heap_Mem +      Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ENDIF
  
  
                  END
  </code></pre>
  
  <p>Unfortunately I am just starting to learn assembly, so I have no idea what this code does, but more important how to fix the problem. 
  Here problematic line </p>
  
  <pre><code>; Enter the C code
  
                  IMPORT  __main
                  LDR     R0, =__main
                  BX      R0
  
  
                  IF      :DEF:__MICROLIB
  
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
  
                  ELSE
  </code></pre>
  
  <p>As I can guess here main function is being called, but as far as I am writing assembly program, it throws me an error that I have no section main. </p>
  
  <p>What is the correct way to start execution of my custom code from this startup.</p>
  
  <p>I know that I can name my area <code>RESET</code> and it will goes here, but I want to do this in right way.  </p>
  
  <p>Thank you.</p>
  
  <p><strong>UPDATE</strong></p>
  
  <p>This code works just fine </p>
  
  <pre><code>        AREA Factorial, CODE, READONLY
          EXPORT __main
          ENTRY
  __main
          MOV r0, #10 ; load initial value
          MOV r1, #1 ; if n=0 than 1 is result
  loop    CMP r0, #0 ; if n=0
          MULGT r1, r0, r1
          SUBGT r0, r0, #1
          BGT loop
  stop    B stop ; stop program
          END
  </code></pre>
  
  <p>Thank you 
  But only one warning</p>
  
  <pre><code>.\Objects\SortingAlgorithm.sct(8): warning: L6314W: No section matches pattern *(InRoot$$Sections).
  </code></pre>