title: TLB structure in intel
body: <p>I started from Patterson &amp; Hennessy book with basic definitions and then followed the intel programming reference documents for more information about TLB.</p>
  
  <p>From the intel documents i got to know the high level design of TLB.
  such as line size, associativity and levels of caching. But in need a detailed explanation of how TLB caching works with respect to cache misses and its replacement mechanisms in modern CPU. What pages moves<br>
  to L2 TLB from L1 TLB ? how many pages can a single entry in TLB address? How many entries are present in TLB ? (In particular DTLB)</p>
  
  <p>Any Information or references will be of great help to me.
  (If this is not the proper forum for this question, please suggest the right one)</p>
  
  <p>Thank you.</p>