title: How to clean object files without using command 'make clean' when compiling with makefile?
body: <p>What I want to know is how to write a makefile that compiles a program and then removes the object files created in the process with just using command 'make' so I don't have to run command 'make clean' afterwards. Here's my current makefile:</p>
  
  <pre><code>prog: prog.o prog_func.o
      gcc prog.o prog_func.o -o prog -Wall -std=c99   
  prog.o: prog.c prog_func.h
      gcc prog.c -c -Wall -std=c99 
  prog_func.o: prog_func.c prog_func.h
      gcc prog_func.c -c -Wall -std=c99
  clean:
      rm prog.o prog_func.o
  </code></pre>
  
  <p><strong>EDIT:</strong></p>
  
  <p>And this is how it's done: </p>
  
  <pre><code>prog: prog.o prog_func.o
      gcc prog.o prog_func.o -o prog -Wall -std=c99
      rm prog.o prog_func.o
  prog.o: prog.c prog_func.h
      gcc prog.c -c -Wall -std=c99 
  prog_func.o: prog_func.c prog_func.h
      gcc prog_func.c -c -Wall -std=c99
  </code></pre>
  
  <p>It works now. Thanks for quick responses.</p>