title: How to call a bunch of subdirectories Makefile from a top level Makefile with different targets
body: <p>I have a top level Makefile that define a list of subdirectories containing sub-Makefiles.</p>
  <p>Each sub-Makefile define the same targets: all, install, clean, test, verify, style...</p>
  <p>How do I make the top level Makefile call all my subdirectories Makefile with the same target ?</p>
  <p>It works for the default target, like this:</p>
  <pre><code>SUBDIRS = dir1 dir2 dir3
  
  all: subdirs
  
  subdirs: $(SUBDIRS)
  $(SUBDIRS):
      $(MAKE) -C $@
  
  .PHONY: subdirs $(SUBDIRS)
  </code></pre>
  <p>But how do I extend that to the other non default targets ?</p>