title: div in verilog for numbers 0-9
body: <p>im coding and synthesizing a module "divider" in an fpga. Inputs A,B are considered to produce output div, which is equal to A div B. Ive tested my code with a testbench module, and it was working properly. However, when im synthesizing it into my fpga, certain part of the code is not working as intended.
  Presenting the code, then I will explain what fails.</p>
  
  <pre><code>module divider(A,B,clk,reset,div,temp);
  input [3:0]A,B;
  input clk,reset;
  output [3:0]div;
  output [3:0]temp;
  reg [3:0]temp,div_result;
  reg [2:0] counter;
  always@(A,B) 
  begin
      //temp=4'd0;
      counter=3'd1;
  end
  
  always @ (posedge clk or posedge reset)
  if (reset) counter=1;
  else
  begin
      if (B==4'd1) div_result=A;
      else if (B==4'd0) div_result=4'b1111;
      else if (A&lt;B) div_result=0;
      else if (A==B) div_result=1;
      else if (A&gt;B)
          begin
              temp=A-counter*B;
              if (temp&gt;=B)  counter=counter+3'd1;
              else begin
              div_result=counter;
  
              end
  
  
          end
  
  
  
  
  end
  assign div=div_result;
  endmodule
  
  module test();
  reg [3:0] A,B;
  reg clk,reset;
  wire [3:0]div;
  wire [2:0] temp;
  divider kappa(A,B,clk,reset,div,temp);
  initial
  begin
  #0 A=4'd8; B=4'd2; clk=0; reset=1;
  #1 reset=0;
  #50 B=4'd1;
  #50 B=4'd3;
  #50 B=4'd4;
  #50 B=4'd5;
  #50 B=4'd8;
  #50 B=4'd9;
  end
  always #5 clk=~clk;
  endmodule
  </code></pre>
  
  <p>The result appears as it should in almost all cases, except when the div needs to be counted, and is greater than 1. ie, 7 div 7 works properly, 8 div 5 works properly, 6 div 0 works properly BUT 8 div 4 is NOT. neither 9 div 2 etc. They all produce the output 0.</p>
  
  <p>I have created many modules, working fine. For some reason, even though I use clk to count how many times B can "fit" into A (Since A>B, B "fits" at least once, in A,so the counter is set to 1. If A-1*B>=B, it fits again. So counter=2 etc). This logic is produced by the clk pulse.</p>
  
  <p>Can you help me figure out the problem?</p>