title: Multiplying 2D arrays in Verilog
body: <p>I am trying to port my k-nearest-neighbor code (in MATLAB) to Verilog so that I can use it in my design and ultimately put on a FPGA board. Now the code and its operations are fairly simple in MATLAB because things like making null and identity matrices, or multiplying 2D matrices are conveniently handled by prebuilt functions. I am trying to do the same in Verilog, but without the use of 'for' loops as they are only to be used in parallel structures and not terribly efficient (right?). I can handle one dimensional arrays, but I can't seem to think of anything for the 2D matrices that would be efficient (or at least as efficient as it can get on hardware). Any advice would be helpful.</p>
  
  <p>Thanks in advance!!</p>