title: How does 8259A interrupt controller deal with interrupts while servicing one already?
body: <p>I am reading the <a href="http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf" rel="nofollow">"Intel 8259A" document</a>, and there is a paragraph which I am unable to fully understand (end of page 7):</p>
  
  <blockquote>
    <p>When the 8259A PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive immediately after the second INTA pulse. After an unspecified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and can vary between parts. The designer should be aware of this consideration when designing a system which uses the 8259A. It is recommended that proper asynchronous design techniques be followed.</p>
  </blockquote>
  
  <p>I understand that after first INTA (interrupt acknowledged initially) and before second INTA (CPU wants the 8-bit interrupt vector), if a higher priority interrupt line is "activated" (I am no electronic engineer), the INT line to CPU is deactivated and re-activated again after unspecified period of time.</p>
  
  <p>What I don't understand is the following:</p>
  
  <ol>
  <li><p>What are the implications of the behavior in question to me as a bare-bones (OS kernel) developer?</p></li>
  <li><p>The "asynchronous design techniques" mentioned - are these HARDWARE design techniques, or allusions to people writing kernels? It seems to me there is not much I can do if an interrupt arrives between two INTA pulses - this is all happening on a level I really cannot control as a kernel developer, can I?</p></li>
  </ol>