title: How to do SystemVerilog-style bit vector slice assignment in C++?
body: <p>I am porting some SystemVerilog code to SystemC/C++. I am using std::bitset to represent bit vectors, but I can see already it falls short of providing methods to access a slice.</p>
  
  <p>For example, if I want to set reg1 to bits 4-8 of reg2 with the SystemVerilog code:</p>
  
  <pre><code>bit [3:0] reg1;
  bit [15:0] reg2;
  reg1 = reg2[7:4];
  </code></pre>
  
  <p>How could I do this with std::bitset?</p>
  
  <pre><code>bitset&lt;4&gt; reg1;
  bitset&lt;16&gt; reg2;
  reg1[0] = reg2[4];
  reg1[1] = reg2[5];
  reg1[2] = reg2[6];
  reg1[3] = reg2[7];
  </code></pre>
  
  <p>Is there a better way?</p>