title: How can I test bench a VHDL 24 hour Clock?
body: <p>I'm having a bit of problem when trying to test bench my VHDL. 
  I'm using a fpga Baysis 2 to run my code, and it is working pretty well on the hardware, but when I use the program Isim to simulate my code, it doesn't show any behavior for my out pins, only the letter U.</p>
  
  <p>I'm looking through the internet and couldn't find a solution, can someone help me on this one?</p>
  
  <p>Here follows the last part of my code (probably the one with the something wrong). Before that the code simply had a process to divide the clock to measure 1 second another to divide in 1/200 of a second to quickly turn on and off the led's on the fpga's display, and counted the seconds to make the 24 hour clock work, of course.</p>
  
  <pre><code>    contador: process(clk200)
  
  variable flag : std_logic_vector (1 downto 0);
  -- ledplex is the mux that controls which display should be on
  -- Segm is the 7 segments display 
  -- mu md hu hd are the signals with the time information
  begin
  
  if(clk200'event and clk200='1') then
       if (flag = "00") then
  
          ledplex &lt;= "1110";
  
              case mu is 
                  when 0 =&gt; segm &lt;= "1000000";
                  when 1 =&gt; segm &lt;= "1111001";
                  when 2 =&gt; segm &lt;= "0100100";
                  when 3 =&gt; segm &lt;= "0110000";
                  when 4 =&gt; segm &lt;= "0011001";
                  when 5 =&gt; segm &lt;= "0010010";
                  when 6 =&gt; segm &lt;= "0000011";
                  when 7 =&gt; segm &lt;= "1111000";
                  when 8 =&gt; segm &lt;= "0000000";
                  when 9 =&gt; segm &lt;= "0011000";
                  when others =&gt; segm &lt;= "1111111";   
              end case;
          flag := "01";
  
      elsif (flag = "01") then
  
          ledplex &lt;= "1101";
  
              case md is 
                  when 0 =&gt; segm &lt;= "1000000";
                  when 1 =&gt; segm &lt;= "1111001";
                  when 2 =&gt; segm &lt;= "0100100";
                  when 3 =&gt; segm &lt;= "0110000";
                  when 4 =&gt; segm &lt;= "0011001";
                  when 5 =&gt; segm &lt;= "0010010";
                  when others =&gt; segm &lt;= "1111111";           
              end case;
      flag := "10";
  
      elsif (flag = "10") then
          ledplex &lt;= "1011";
  
              case hu is 
                  when 0 =&gt; segm &lt;= "1000000";
                  when 1 =&gt; segm &lt;= "1111001";
                  when 2 =&gt; segm &lt;= "0100100";
                  when 3 =&gt; segm &lt;= "0110000";
                  when 4 =&gt; segm &lt;= "0011001";
                  when 5 =&gt; segm &lt;= "0010010";
                  when 6 =&gt; segm &lt;= "0000011";
                  when 7 =&gt; segm &lt;= "1111000";
                  when 8 =&gt; segm &lt;= "0000000";
                  when 9 =&gt; segm &lt;= "0011000";
                  when others =&gt; segm &lt;= "1111111";   
              end case;
          flag := "11";
  
      elsif (flag = "11") then
          ledplex &lt;= "0111";
  
              case hd is 
                  when 0 =&gt; segm &lt;= "1000000";
                  when 1 =&gt; segm &lt;= "1111001";
                  when 2 =&gt; segm &lt;= "0100100";
                  when others =&gt; segm &lt;= "1111111";           
              end case;
      flag := "00";
  
      end if;
  end if;
  end process contador;
  </code></pre>
  
  <p>and here follows the test bench
      LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;</p>
  
  <pre><code> ENTITY t_b IS
   END t_b;
  
     ARCHITECTURE behavior OF t_b IS 
  
  -- Component Declaration for the Unit Under Test (UUT)
  
      COMPONENT hora
     PORT(
       clk25m : IN  std_logic;
       segm : OUT  std_logic_vector(6 downto 0);
       ledplex : OUT  std_logic_vector(3 downto 0);
          x : out std_logic
      );
     END COMPONENT;
  
      signal  clk_tb : std_logic := '0';
      signal  segm_tb : std_logic_vector(6 downto 0);
      signal   ledplex_tb : std_logic_vector(3 downto 0);
      signal x_tb : std_logic;
  
      BEGIN
  
      CUT: hora port map(  clk25m =&gt; clk_tb,
                                  segm =&gt; segm_tb,
                                  ledplex =&gt; ledplex_tb,
                                  x =&gt; x_tb);
  
  
      Test_Vector: process
      begin
      clk_tb &lt;= '1';
      wait for 40 ns;
      clk_tb &lt;= '0';
      wait for 40 ns;
      end process;
  
      END behavior;
  </code></pre>