title: macros defined in verilog file but error shows undifined macros in modelsim
body: <p>I have defined the macros of all my verilog files in one verilog file, say FabScalarParam.v
  and I compile the FabScalarParam.v first in the system.do file then compile other verilog files.</p>
  
  <p>But when I run "do system.do" to compile the design, it shows me the errors like this,</p>
  
  <pre><code># ** Error: I:/programming/EDK/project_4/pcores/instruction_side_v1_00_a/hdl/verilog/StallUnit.v(6): (vlog-2163) Macro `MAX_STALL_CYCLES_LOG is undefined.
  </code></pre>
  
  <p>It says that some macros are not defined. Is there any method to choose the FabScalarParam.v as global file in compile list in modelsim? Due to the large number of macros, I cannot specify all the macros using the method: compile --> compile options --> verilog &amp; system verilog --> other verilog options --> Macros.</p>
  
  <p>I use modelsim 6.5, xilinx edk 12.4</p>