title: Debugging error "procedural assignment to a non-register k is not permitted"
body: <p>My Verilog code looks like this. The module implements a look up table ROM with an address register that increments on a clock pulse. The output of this is decoded to give a 32 bit number. I don't see why k needs to be a register. In fact I don't want k to have a clocked delay after the address register changes. How is the decoding of <code>addr</code> meant to be specified?</p>
  
  <p>(Note that seems unrelated to the similarly named other question on SO since I already checked that out - I don't want a register on the output. I just want to asynchronously decode the output of a count register. Maybe I'm confused about the &lt;= operator which I assume will always generate a clocked register, but maybe I should always be using &lt;=.)</p>
  
  <pre><code>module k_rom (input clk, input reset, output [31:0] k);
  // Constants defined by the SHA-2 standard.
  reg [5:0] addr;
  
  always @ (addr)
      begin
          case(addr)
              6'h00: k = 32'h428a2f98;
              6'h01: k = 32'h71374491;
              6'h02: k = 32'hb5c0fbcf;
              6'h03: k = 32'he9b5dba5;
              6'h04: k = 32'h3956c25b;
              6'h05: k = 32'h59f111f1;
              6'h06: k = 32'h923f82a4;
              6'h07: k = 32'hab1c5ed5;
              6'h08: k = 32'hd807aa98;
              6'h09: k = 32'h12835b01;
              6'h0a: k = 32'h243185be;                                        
  // other constants not shown for brevity
              6'h3c: k = 32'h90befffa; 
              6'h3d: k = 32'ha4506ceb; 
              6'h3e: k = 32'hbef9a3f7; 
              6'h3f: k = 32'hc67178f2;
          endcase
      end
  
  always @ (posedge clk)
      begin
          if(reset)
              addr &lt;= 6'b0;
          else
              addr &lt;= addr + 6'b1;
      end
  
  endmodule
  </code></pre>