title: Asynchronous FIFO code advice - VHDL
body: <p>All the codes I've found generate me some errors. My FPGA manufacturer FIFO's when I try to read and write at the same time it create me problems in simulation and also I can't modify it or adapt to another FPGA.</p>
  
  <p>Can someone advice me an already written Asynchronous FIFO (2 Clock FIFO) code in VHDL, possibly already used without problems?</p>
  
  <p>I need the possibilty to read and write at the same time with 2 different clocks.</p>