title: 2D Array assign problem VHDL having different size
body: <p>I have two 2D arrays defined as below</p>
  <pre class="lang-vhdl prettyprint-override"><code>type ram_1300_block is array (1300 downto 0) of std_logic_vector(7 downto 0);
  
  type ram_2700_block is array (2700 downto 0) of std_logic_vector(7 downto 0);
  
  rx_ram : ram_1300_block;
  Q1_ram : ram_2700_block;
  </code></pre>
  <p>Then I am using the below assignment statement in my code:</p>
  <pre><code>Q1_ram(1300 downto 1) &lt;= rx_ram(1341 downto 42);
  </code></pre>
  <p>While synthesizing I am getting the below error in vivado 2015.3</p>
  <pre><code>Synth 8-2234 indexed name is not a ram_3700 block?
  </code></pre>
  <p>Any workaround?</p>
  <p>I dont want to increase the small array size due to resource constraint.</p>