title: ARM LDR instruction on PC register
body: <p>Here how I understand the story:</p>
  
  <ul>
  <li>PC register holds pointer to next instruction</li>
  <li>LDR instruction is loading the value of second operand into first operand
  (for example) <pre>LDR r0, [pc, 0x5678]</pre>
  is equivalent to this "C code" <pre>
  r0 = *(pc + 0x5678)
  </pre>
  It's pointer dereferencing with base offset.</li>
  </ul>
  
  <p>And my question:</p>
  
  <p>I found this code </p>
  
  <pre>
  LDR PC, [PC,-4]
  </pre>
  
  <p>It's commented like monkey patching, etc..</p>
  
  <p>How I understand this code</p>
  
  <pre>pc = *(pc - 4)</pre>
  
  <p>I this case "pc" register will dereference the address of previous instruction and will contain the "machine code" of instruction (not the address of instruction),
  and program will jump to that invalid address to continue execution, and probably we will get "Segmentation Fault".
  So what I'm missing or not understanding?</p>
  
  <p><br><br>The thing that makes me to think is the brackets of second operand in LDR instruction.
  As I know on x86 architecture brackets are already dereferencing the pointer, but I can't understand the meaning in ARM architecture.</p>
  
  <pre>
  mov r1, 0x5678
  add r1, pc
  mov r0, [r1]
  </pre>
  
  <p>is this code equivalent to?</p>
  
  <pre>
  LDR r0, [pc, 0x5678]
  </pre>