title: Illegal reference to net rddata in FIFO
body: <p>The below code is for a FIFO.  It is showing an error as illegal reference to net datatype as <code>rddata</code> at line 38 in tb (highlighted by adding a comment &quot;//error line&quot;).</p>
  <p>Why do I get this error?</p>
  <pre><code>module fifo(clk,rst,error,empty,full,rddata,wrdata,wr_en,rd_en);
  
  parameter WIDTH = 8;
  parameter DEPTH = 16;
  input clk,rst,rd_en,wr_en;
  input [WIDTH-1:0]wrdata;
  output reg [WIDTH-1:0]rddata;
  output reg empty,full,error;
  reg [WIDTH-1:0]mem[DEPTH-1:0];
  reg [3:0]rd_ptr;
  reg [3:0]wr_ptr;
  reg wr_toggle,rd_toggle;
  integer i;
  
  always@(posedge clk)
  begin
      if(rst==1)
      begin
      empty = 1;
      full = 0;
      error = 0;
      rd_ptr = 0;
      wr_ptr = 0;
      wr_toggle = 0;
      rd_toggle = 0;
      for(i=1;i&lt;DEPTH;i=i+1)
      begin
      mem[i] = 0;
      end
  end
      else 
          begin
          if(wr_en ==1)begin
          if(full==1)begin
          $display(&quot;ERROR:Writing to full FIFO&quot;);
          error = 1;
          end
  
          else
          begin
              mem[wr_ptr] = wrdata;   
              if(wr_ptr == DEPTH-1)begin
              wr_toggle = ~wr_toggle;
              wr_ptr = 0;
              end
              else begin
              wr_ptr = wr_ptr + 1;
              end
  
          end
          end
          
                  if(rd_en ==1)begin
              if(empty==1)begin
                  $display(&quot;ERROR:REading from EMPTY FIFO&quot;);
              error = 1;
              end
          end
          else
          begin
              mem[rd_ptr] = rddata;   
              if(rd_ptr == DEPTH-1)begin
              rd_toggle = ~rd_toggle;
              rd_ptr = 0;
              end
              else begin
              rd_ptr = rd_ptr + 1;
              end
          end
          end
  
      end
      always@(wr_ptr or rd_ptr)
      begin
          full = 0;
          empty = 0;
          if(wr_ptr == rd_ptr &amp;&amp; wr_toggle == rd_toggle)begin
              empty = 1;
              full = 0;
          end
          if(wr_ptr == rd_ptr &amp;&amp; wr_toggle != rd_toggle)begin
              empty = 0;
              full = 1;
          end
      
  
      end
  endmodule
  
  //TEST BENCH
  
  `include &quot;fifo.v&quot;
  module tbfifo();
  parameter WIDTH = 8;
  parameter DEPTH = 16;
  reg clk,rst,rd_en,wr_en;
  reg [WIDTH-1:0]wrdata;
  wire [WIDTH-1:0]rddata;
  wire empty,full,error;
  integer i;
  
  fifo_buff dut (clk,rst,error,empty,full,rddata,wrdata,wr_en,rd_en);
  initial
  begin
      clk = 0;
      forever #5 clk = ~clk;
  end
  
  
  initial
  begin
      rst = 1;
      repeat(2) @(posedge clk);
      rst = 0;
  
      for(i=0;i&lt;DEPTH;i=i+1)begin
      @(posedge clk);
      wr_en = 1;
      wrdata = $random;
      end
  
      @(posedge clk);
      wr_en = 0;
      wrdata= 0;
      
      for(i=0;i&lt;DEPTH;i=i+1)begin
      @(posedge clk);
      rd_en = 1;
      rddata &lt;= $random;   //error line
      end
      @(posedge clk);
      rd_en = 0;
      
      #100;
      $finish;
  end
  endmodule
  </code></pre>