title: How to perform bit extension in system verilog?
body: <p>I want to replicate one bit for specific times using replication opreator {} but I get only the first bit as I want and others are zeros whether the bit is zero or one.</p>
  
  <pre><code>module(logic output [7:0] a);
  assign a={8{1}};
  endmodule
  </code></pre>
  
  <p>I get a equals 00000001
  Not 11111111</p>