title: How to do matrix multiplication in Verilog?
body: <p>I am trying to multiply <code>1x3 * 3X64</code> matrix, here since each value in matrix is decimal number so for each value I have taken <code>4</code> bits that is <code>4x64</code> bits in total accessing <code>4</code>bits of each row at a time.</p>
  
  <p>I tried to generalize it. </p>
  
  <p>The matrix is of form <code>1x3 [2,4,3]</code> &amp;</p>
  
  <p><code>3*64(64 decimal value in each row)</code></p>
  
  <blockquote>
    <p>row 1[111111111111111111111111111111(64)]</p>
    
    <p>row 2[11111111(8)22222222(8).....88888888(8)]</p>
    
    <p>row 3[1234567812345678..................12345678]</p>
  </blockquote>
  
  <p>The code which I tried</p>
  
  <pre><code>always@(h1,h2,h3)
          begin
  z1 =((w0[3:0]*h1[3:0])+(w1[3:0]*h2[3:0])+(w2[3:0]*h3[3:0]));
  z2=((w0[3:0]*h1[7:4])+(w1[3:0]*h2[7:4])+(w2[3:0]*h3[7:4]));
  
  .
  .
  .
  .
  .   
  z64=((w0[3:0]*h1[255:252])+(w1[3:0]*h2[255:252])+(w2[3:0]*h3[255:252]));
  
  
      end
  
          endmodule 
  </code></pre>
  
  <p>I need generalized form of this..</p>
  
  <p><strong>Error that I have got:</strong></p>
  
  <blockquote>
    <p>ERROR:HDLCompilers:110 - "mat.v" line 36 Least significant bit operand
    in part-select of vector wire 'h1' is illegal</p>
  </blockquote>
  
  <pre><code>for(i=3;i&lt;255;i=i+4)
          begin
              for(j=0;j&lt;255;j=j+4)
  
              begin
                  z[i:j]=((w0[3:0]*(h1[i:j]))+(w1[3:0]*h2[i:j])+(w2[0]*h3[i:j]));
  
              end 
  </code></pre>