title: How to access VHDL signal attributes in ModelSim via TCL?
body: <p>I am developing a CPU in VHDL. I am using ModelSim for simulation and testing. In the simulation script I load a program from a binary file to the instruction memory. Now I want to automatically check if the program fits into memory and abort simulation if it doesn't. Since the memory is basically an array of std_logic_vectors, all I would have to do is read the corresponding signal attribute for use in a comparison. My problem is: How do I access a VHDL signal attribute in TCL inside ModelSim?</p>
  
  <p>The closest I have gotten so far is to use the describe command:</p>
  
  <pre><code>describe sim/:tb:uut:imem:mem_array
  </code></pre>
  
  <p>which prints something like</p>
  
  <pre><code># Array(0 to 255) [length 256] of
  #   Array(31 downto 0) [length 32] of
  #     VHDL standard subtype STD_LOGIC
  </code></pre>
  
  <p>Now, of course I could parse the length out of there via string operations. But that would not be a very generic solution. Ideally I would like to have something like this:</p>
  
  <pre><code>set mem_size [get_attribute sim/:tb:uut:imem:mem_array'length]
  </code></pre>
  
  <p>I have searched stackoverflow, googled up and down and searched through the commands in the command reference manual, but I could not find a solution. I am confident there must be a rather easy solution and I just lack the proper wording to successfully search for it. To me, this doesn't look overly specific and I am sure this could come in hand on many occasions when automating design testing. I am using version 10.6.</p>
  
  <p>I would be very grateful if an experienced ModelSim user could help me out.</p>