title: What is the point of a "plain" begin-end block?
body: <p>I'm reading some third party Verilog, and found this:</p>
  
  <pre><code>function [31:0] factorial;
      input [3:0] operand;
      reg [3:0] index;
  
      begin
          factorial = operand ? 1 : 0;
          for(index = 2; index &lt;= operand; index = index + 1)
          factorial = index * factorial;
      end
  endfunction
  </code></pre>
  
  <p>It seems that the <code>begin</code> and <code>end</code> keywords are redundant here. Are they? What is their use?</p>