title: Verilog: Converted Integer Not Working for For loop
body: <p>I am writing a program in Verilog that accepts a binary value, converts it to Integer, and then prints "Hello, World!" that amount of times.</p>
  
  <p>However, whenever I run the program, there is no display of Hello, World. Here is the code:</p>
  
  <pre><code>// Internal Variable
  wire [0:4] two_times_rotate;
  
  // Multiply the rotate_imm by two (left shift)
  assign {two_times_rotate} = rotate_imm &lt;&lt; 1;
  integer i, times_rotated;
  
  // Convert two_times_rotate into an integer
  always @( two_times_rotate )
  begin
    times_rotated = two_times_rotate;
  end
  
  initial 
  begin
  
  for (i = 0; i &lt; times_rotated; i = i + 1)
  begin
    $display("Hello, World");
  end
  
  end
  
  assign {out} = in;
   endmodule
  </code></pre>
  
  <p>I tried using the following for loop instead: </p>
  
  <pre><code>for (i = 0; i &lt; 7; i = i + 1)
  </code></pre>
  
  <p>And this one prints Hello, World seven times, like it should.</p>
  
  <p>*<strong><em>UPDATE</em>*</strong></p>
  
  <p>This is what I have in my code so far. I am trying to do a for that compares bits instead. It is still not working. How do I fully convert from binary to integer in a way that I can use it in the comparison in the for loop?</p>
  
  <pre><code> module immShifter(input[0:31] in, input[0:3] rotate_imm, 
                output[0:31] out);
  
   // Internal Variable
   wire [0:4] two_times_rotate;
   reg [0:4] i;
  
   // Multiply the rotate_imm by two (left shift)
   assign {two_times_rotate} = rotate_imm &lt;&lt; 1;
   integer times_rotated, for_var;
  
   // Convert two_times_rotate into an integer
   always @( two_times_rotate )
   begin
      assign{times_rotated} = two_times_rotate;
   end
  
   initial 
   begin
  
   assign{i} = 5'b00000;
   assign{for_var} = times_rotated;
   for (i = 5'b00000; i &lt; times_rotated; i = i + 5'b00001)
   begin
     $display("Hello, World");
   end
  
   end
  
   assign {out} = in;
  endmodule 
  </code></pre>