title: Verilog binary addition
body: <p>Binary addition on <code>A</code> and <code>B</code> and outputs it along with proper carry bit. I'm not sure how to implement the carry bit</p>
  
  <p><code>A</code> and <code>B</code> are 4 bit inputs</p>
  
  <p><code>C</code> is 1 bit output that is used for the carry bit</p>
  
  <pre><code>module addop(C , O , A , B);
     input [3:0] A;
     input [3:0] B;
     output [3:0] O;
     output       C;
  
     assign C1 = A[0] + B[0];
     assign C2 = A[0] + B[1];
  endmodule
  </code></pre>