title: Verilog and ASM implementation
body: <p>In the question below, </p>
  
  <p>The ASM chart shows that value of <code>q_next</code> is compared to 0 to proceed to next state but before <code>q_next</code> is compared, the value of q is already updated with <code>q_next</code>, so if we compare the value of q with 0, will the results be same in terms of timing and other parameters? </p>
  
  <p>Also what should be the types of <code>q_next and q</code> ? Should they be reg or wire?</p>
  
  <p>I have attached the screenshots of the ASM chart and the Verilog code. I also don't understand the timing implications of conditional box (in general, can't we put the output of a conditional box in a separate state which doesn't depend on the output of the conditional box)?, </p>
  
  <p>like when in the wait1 state, we check the value of sw and if true, we decrement the counter and then check if counter has reached to zero and then asser db_tick. I want to understand the time flow when we move from wait1 and increment counter and assert db_tick. Are there any clock cycles involved between these stages, that is moving from a state to a conditional box? </p>
  
  <p>Also in the verilog code, we use <code>q_load</code> and <code>q_tick</code> to control the counter. Why these signals are used when we can simply control the counter in the states?</p>
  
  <p>Is it done to make sure that the FSM (control path) controls the counter (data path)? Please explain. Thanks in advance. </p>
  
  <p><a href="https://i.stack.imgur.com/HbQ9Y.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HbQ9Y.jpg" alt="enter image description here"></a></p>
  
  <p><a href="https://i.stack.imgur.com/AQPZ7.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/AQPZ7.jpg" alt="enter image description here"></a></p>