title: Four Bit Adder Understanding
body: <p>Can someone explain to me what I am doing wrong. I don't know if I just don't understand the concept or what. I have looked at two solid examples, both of which provide thorough code but maybe I am wiring things wrong or something.</p>
  
  <p>1st - I have created an file called Adder and below is my code. This works completely fine, I have created/ran a test bench file with this so I know this does exactly what is intended. However, am I supposed to somehow connect my FullAdder file or the test bench for the FullAdder file to the Adder file? Are these completely separate files and are never connected?</p>
  
  <pre><code>module Adder (a,b,ci,co,s);
      input a,b,ci;
      output co,s;
      assign s=a^b^ci;
      assign co=(a&amp;b)|(a&amp;ci)|(b&amp;ci);
  endmodule
  </code></pre>
  
  <p>2nd - Below is my code for the FullAdder file. I am not sure if this is correct but let me know where I can make possible changes. I assume the test bench I create will be linked to this FullAdder file? The syntax for this file checks out alright, so maybe it is the test bench that is causing problems for me...</p>
  
  <pre><code>module FullAdder(a,b,ci,s);
      input [3:0] a,b;
      input ci;
      output [3:0] s;
      wire [2:0] co;  // Is the wire correct here? I created this off something I saw.
  
      Adder ADD1(a[0],b[0],ci,s[0],co[0]);
      Adder ADD2(a[1],b[1],co[0],s[1],co[1]);
      Adder ADD3(a[2],b[2],co[1],s[2],co[2]);
      Adder ADD4(a[3],b[3],co[2],s[3],s[4]);
  endmodule
  </code></pre>
  
  <p>3rd - I don't understand the test bench and wiring everything all together. I have looked at these two links which have two different ways of doing this. 
  <a href="http://cs.smith.edu/dftwiki/index.php/Xilinx_ISE_Four-Bit_Adder_in_Verilog" rel="nofollow">Link 1</a> <a href="http://www.edaplayground.com/x/3UW" rel="nofollow">Link 2</a>. I have tried to replicate link 2, but can't seem to get it working. Help?</p>