title: What is `+:` and `-:`?
body: <p>What are the <code>+:</code> and <code>-:</code> Verilog/SystemVerilog operators?  When and how do you use them?  For example:</p>
  
  <pre><code>logic [15:0] down_vect;
  logic [0:15] up_vect;
  
  down_vect[lsb_base_expr +: width_expr]
  up_vect  [msb_base_expr +: width_expr]
  down_vect[msb_base_expr -: width_expr]
  up_vect  [lsb_base_expr -: width_expr]
  </code></pre>