title: How to reuse multiple always blocks in Verilog
body: <p>Below is the always block code. </p>
  
  <p>I need to have same code 11 times, with same functionality but on different variables. So how can I reuse the code?</p>
  
  <pre><code>  always @(posedge tconClk or negedge tconRst_n)
    begin
      if(~tconRst_n)
      begin
        pulse_cnt &lt;= 0;
        pulse_start = 0;
        start_written = 0;
        pulse_width &lt;= 'h271;
      end
      else if(~pulse_rst)
      begin
        pulse_cnt &lt;= 0;
        pulse_start = 0;
      end
      else
      begin
        if(start_signal)
        begin
  //        start_written = 0;
          pulse_width &lt;= (pulse_start) ? pulse_width : START_PW;
          pulse_start = 1;
        end
        pulse_cnt &lt;= (pulse_start) ? (pulse_cnt + 1) : pulse_cnt;
      end
    end
  </code></pre>
  
  <p>Naming Pattern -</p>
  
  <ul>
  <li><code>tconClk</code>, <code>tconRst_n</code> is common,</li>
  <li><code>pulse_cnt0</code>, <code>pulse_cnt1</code> upto <code>10</code>,</li>
  <li><code>pulse_width0</code>, <code>pulse_width1</code> upto <code>10</code>,</li>
  <li><code>pulse_start[0:10]</code> (Array),</li>
  <li><code>start_written[0:10]</code> (Array),</li>
  <li><code>pulse_rst[0:10]</code> (Array),</li>
  <li><code>start_signal[0:10]</code> (Array),</li>
  <li><code>START_PW</code> (No pattern, different name for each 11 always blocks)</li>
  </ul>
  
  <p>Note - </p>
  
  <ol>
  <li><p>Defining macro won't work, as this code contains many verilog tokens.</p></li>
  <li><p>I can't make module of the code, because the signals used in the always block, are also used in other part of the code. So if I make module, then I won't be able to ensure proper reg or wire connections to the module. (Like a module output port must be a wire, but that same signal has been used as a reg in other part of code)</p></li>
  </ol>