title: Syntax error. Statement labels are only allowed in SystemVerilog
body: <p>Modelsim: I check many times, but I could not find out how to fix it.   </p>
  
  <blockquote>
    <p>near ":": Syntax error. Statement labels are only allowed in SystemVerilog.</p>
  </blockquote>
  
  <pre><code> parameter [1:0] S1 = 2'b00, S2 = 2'b01, S3 = 2'b10;
          always @(cur_state or s or Cout or cnt_zero) // Combo logic for
          begin: FSM_outputs  // output signals
              load_R = 0; en_shift_R = 0; rr0mux = 0; 
              load_cnt = 0; en_cnt = 0; en_shift_A = 0; 
                  case (cur_state)
                      S1: begin
                              load_cnt = 1; en_shift_R = 1; 
                              if (s == 0) begin 
                                  load_R = 1; rr0mux = 0; 
                             end
                             else begin
                                  load_R = 0; en_shift_A = 1; rr0mux = 1;
                             end
                      S2: begin //the errors are located HERE S2.
                              Rmux = 1; en_shift_R = 1; rr0mux = 1; en_shift_A = 1; 
                              if (Cout) load_R = 1;
                              else load_R = 0;
                              if (cnt_zero == 0) en_cnt = 1;
                              else en_cnt = 0;
                             end
                      S3: done = 1;
                  endcase 
              end
  </code></pre>