title: Verilog signed multiplication: Multiplying numbers of different sizes?
body: <p>For some reason I have been unable to find any definitive resources or stackoverflow questions answering this:</p>
  
  <p>Does verilog take care of input and output dimensions when multiplying signed numbers? </p>
  
  <p>To be specific, what happens if I multiply a signed 32-bit with a signed 64-bit number? So if I have:</p>
  
  <pre><code>reg signed [31:0] a = -5;
  reg signed [63:0] b = 5;
  wire signed [63:0] c;
  assign c = a*b;
  </code></pre>
  
  <p>Will c be equal to -25 (in 64-bit 2's complement scheme)?</p>
  
  <p>What if I declared c as a 32 bit number? Would it still be -25 (in 32 bit 2's complement scheme)?</p>
  
  <p>Thanks!</p>