title: VHDL: How to use 2 regular 4-Bit adders to design an 8-Bit BCD counter?
body: <p>Unlike most counters that i have viewed on this website, my BCD counter requires the use of two 4-Bit adders in order to make 1 8-Bit BCD counter. What I have done so far is design a regular full adder, used that to design a regular 4 bit adder.</p>
  
  <p>This is my code so far:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity adder8b_custom is
  port(
      X: in std_logic_vector( 7 downto 0);
      Y: in std_logic_vector (7 downto 0);
      S: out std_logic_vector (7 downto 0));
  end adder8b_custom;
  
  architecture adder8b_custom of adder8b_custom is
  
  component adder4b 
      port (    X :   in STD_LOGIC_VECTOR (3 downto 0);   
            Y :   in STD_LOGIC_vector (3 downto 0);   
            C0: in STD_LOGIC; 
            S :    out STD_LOGIC_VECTOR (3 downto 0); 
            C4: out STD_LOGIC);
  end component;
  
  signal s1:std_logic_vector ( 7 downto 0); --for addition
  signal s2:std_logic_vector ( 7 downto 0); --for subtraction
  signal s3, s4, s5, s6: std_logic_vector (3 downto 0);--placeholders
  signal i, j, k, l: std_logic;
  
  begin 
      u1: adder4b port map (X =&gt; X (3 downto 0), Y =&gt; "0001",c0=&gt;'0', S =&gt; s3 (3 downto 0), c4=&gt;i);
      s1(3 downto 0) &lt;=s3(3 downto 0) when s3 (3 downto 0) /="1010"
      else "0000";
      s&lt;=s1;
      --u2: adder4b port map (X =&gt; X (7 downto 4), Y =&gt; "0001" ,c0 =&gt; i, S =&gt; s4 (3 downto 0), c4=&gt;j);
      --s1( 7 downto 4) &lt;= s4( 3 downto 0) when s4( 3 downto 0) /= "1010"
      --else "0000";
      --s(7 downto 4)&lt;= s1;
  end;
  </code></pre>
  
  <p>As you can see, everything after the signals is messed up and i do know know how to fix it.</p>
  
  <p>I appreciate all input.</p>