title: Alternative method for creating low clock frequencies in VHDL
body: <p>In the past I asked a <a href="https://stackoverflow.com/questions/34067276/synchronous-vs-asynchronous-resets-in-fpga-system">question</a> about resets, and how to divide a high clock frequency down to a series of lower clock square wave frequencies, where each output is a harmonic of one another e.g. the first output is 10 Hz, second is 20 Hz etc.</p>
  
  <p>I received several really helpful answers recommending what appears to be the convention of using a clock enable pin to create lower frequencies. </p>
  
  <p>An alternative since occurred to me; using a n bit number that is constantly incremented, and taking the last x bits of the number as the clock ouputs, where x is the number of outputs.</p>
  
  <p>It works in synthesis for me - but I'm curious to know - as I've never seen it mentioned anywhere online or on SO, am I missing something that means its actually a terrible idea and I'm simply creating problems for later?</p>
  
  <p>I'm aware that the limitations on this are that I can only produce frequencies that are the input frequency divided by a power of 2, and so most of the time it will only approximate the desired output frequency (but will still be of the right order). Is this limitation the only reason it isn't recommended?</p>
  
  <p>Thanks very much!</p>
  
  <p>David</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  library UNISIM;
  use UNISIM.VComponents.all;
  use IEEE.math_real.all;
  
  ENTITY CLK_DIVIDER IS
      GENERIC(INPUT_FREQ : INTEGER;       --Can only divide the input frequency by a power a of 2 
              OUT1_FREQ  : INTEGER
      );
      PORT(SYSCLK  : IN  STD_LOGIC;
           RESET_N : IN  STD_LOGIC;
           OUT1    : OUT STD_LOGIC;       --Actual divider is  2^(ceiling[log2(input/freq)])
           OUT2    : OUT STD_LOGIC);      --Actual output is input over value above
  END CLK_DIVIDER;
  
  architecture Behavioral of Clk_Divider is
      constant divider      : integer                             := INPUT_FREQ / OUT1_FREQ;
      constant counter_bits : integer                             := integer(ceil(log2(real(divider))));
      signal counter        : unsigned(counter_bits - 1 downto 0) := (others =&gt; '0');
  begin
      proc : process(SYSCLK)
      begin
          if rising_edge(SYSCLK) then
              counter &lt;= counter + 1;
              if RESET_N = '0' then
                  counter &lt;= (others =&gt; '0');
              end if;
          end if;
      end process;
      OUT1 &lt;= counter(counter'length - 1);
      OUT2 &lt;= not counter(counter'length - 2);
  end Behavioral;
  </code></pre>