title: Signed multiplication overflow detection in Verilog
body: <p>Beginner here. I'm trying to code a simple 16-bit microprocessor in Verilog and implement it on a Spartan 6. The ALU implements all signed operations (no unsigned operations at all). All inputs are wires and are signed. The result is stored in a signed register.</p>
  
  <p>My problem is finding a sensible way to detect overflow. It doesn't currently matter how quickly the overflow is detected, since all it does is trigger a fault and halt the system.</p>
  
  <p>I believe I've figured out how I could detect overflow in addition and subtraction, but I'd like assurance anyway.</p>
  
  <p>Here's addition, where o is the overflow flag register:</p>
  
  <pre><code>if((a_in &gt;= 0) &amp;&amp; (b_in &gt;= 0) &amp;&amp; (res_out &lt; 0)) o &lt;= 1'b1;
  else if((a_in &lt; 0) &amp;&amp; (b_in &lt; 0) &amp;&amp; (res_out &gt;= 0)) o &lt;= 1'b1;
  else o &lt;= 1'b0;
  </code></pre>
  
  <p>Here's subtraction:</p>
  
  <pre><code>if((a_in &gt;= 0) &amp;&amp; (b_in &lt; 0) &amp;&amp; (res_out &lt; 0)) o &lt;= 1'b1;
  else if((a_in &lt; 0) &amp;&amp; (b_in &gt; 0) &amp;&amp; (res_out &gt;= 0)) o &lt;= 1'b1;
  else o &lt;= 1'b0;
  </code></pre>
  
  <p>The control matrix takes care of the hold times for a_in and b_in so that the overflow detection could complete, as it's only done once the result has been calculated (on the next clock cycle that is).</p>
  
  <p>I did some looking around here and all I've found is detecting overflow in other languages such as C or C++. I'm looking for an example implementation for detection overflow in signed multiplication.</p>
  
  <p>Both inputs a_in and b_in are signed wires and are 16 bits wide. The result register res_out is signed, also 16 bits wide. Ideally, I'd have a 33 bit wide result register, in which overflow cannot occur anyway, but this is not an option.</p>
  
  <p>Help is appreciated. Any better ways to detect overflow in addition and subtraction are also welcome.</p>