title: Makefile header dependencies
body: <p>I am new to using make and have been learning the basics through <a href="http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/" rel="nofollow noreferrer">this tutorial</a>. Here is the final example makefile example from the tutorial:</p>
  
  <pre><code>IDIR =../include
  CC=gcc
  CFLAGS=-I$(IDIR)
  
  ODIR=obj
  LDIR =../lib
  
  LIBS=-lm
  
  _DEPS = hellomake.h
  DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
  
  _OBJ = hellomake.o hellofunc.o 
  OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
  
  
  $(ODIR)/%.o: %.c $(DEPS)
      $(CC) -c -o $@ $&lt; $(CFLAGS)
  
  hellomake: $(OBJ)
      gcc -o $@ $^ $(CFLAGS) $(LIBS)
  
  .PHONY: clean
  
  clean:
      rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~ 
  </code></pre>
  
  <p>This should work fine assuming all .c files are only including hellomake.h, but it wouldn't work if each .c file was including different headers. Is it possible to write a makefile that knows what each .c file is including, so I don't have to go in and do it manually like:</p>
  
  <pre><code>foo.o: foo.c something.h
      ...
  
  bar.o: bar.c somethingelse.h
      ...
  </code></pre>
  
  <p>because that seems like it would be a big waste of time.</p>