title: Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end"
body: <p>I'm working with Quartus Prime Lite Edition and having a <code>case</code> statement with:</p>
  <pre><code>S2: begin
              dat[WID_DAT-1 :1] &lt;= dat[WID_DAT-2 :0];
              dat[0] &lt;= 0;
              crc[0] &lt;= crc_temp[0];
              integer i;
              for (i = 1; i &lt; WID_CRC; i = i+1) begin
                  crc[i] &lt;= crc_temp[i] ^ crc[i-1];
              end
              
              if(count != 0) begin
                  r_ns &lt;= S2;
                  count &lt;= count -1;
              end
              
              else begin
              r_ns &lt;= S_DONE;
              done &lt;= 1;
              end
          end
  </code></pre>
  <p>and get the error message when I Start Anlysis &amp; Elaboration:</p>
  <blockquote>
  <p>Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near
  text: &quot;integer&quot;;  expecting &quot;end&quot;.</p>
  </blockquote>
  <p>Why is this so, and how should I avoid it?</p>