title: VHDL - How to add 1 to STD_LOGIC_VECTOR?
body: <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  -- use ieee.std_logic_arith.all;
  -- use ieee.numeric_std.all;
  
  -- entity part contain R for output of Register
      
  entity register_16 is
      port(   input:  in std_logic_vector(15 downto 0);
          ld, inc, clk, clr:  in std_logic;
          R: buffer std_logic_vector(15 downto 0));
  end register_16 ;
  
  -- it have to parallel process    
  
  architecture behavioral of register_16 is
  begin
  
  
  reg: process (input, ld, clk, clr)
      variable R_temp: std_logic_vector(15 downto 0);
  begin
      if (clr = '1') then
          R_temp := b&quot;0000000000000000&quot;;
      elsif (clk'event and clk = '1') then
          if (ld = '1') then
              R_temp := input;
          end if;
      end if;
      R &lt;= R_temp;
  end process reg;
  
  -- my error in this step    
  
  inc_R: process (inc)
  begin
      R &lt;= R + '1';
  end process inc_R;
  
  end behavioral;
  </code></pre>
  <p>Main process (reg) works correctly, but other process has error adding 1.</p>