title: ' Illegal output or inout port ' error when trying to simulate counter
body: <p>I am new to verilog HDL and I have zero experience in digital circuit.
  I learned one or two things off the internet and now I am trying to write
  a test bench script for a counter script. I've obtained counter script from following website:</p>
  
  <p><a href="http://www.asic-world.com/verilog/verilog_one_day2.html#Variable_Assignment" rel="nofollow">http://www.asic-world.com/verilog/verilog_one_day2.html#Variable_Assignment</a></p>
  
  <p>Counter:</p>
  
  <pre><code>module counter(clk,rst,enable,count);
  input clk, rst, enable;
  output [3:0] count;
  reg [3:0] count;
  
  always @(posedge clk or posedge rst) begin 
  if (rst) begin
      count &lt;= 0;                 
  end 
  else begin: COUNT           
          while (enable) begin
              count &lt;= count + 1;
              disable COUNT;
          end
  end
  end
  endmodule
  </code></pre>
  
  <p>Then I have writen a test bench as following:</p>
  
  <p>Test Bench </p>
  
  <pre><code>// counter test bench
  `timescale 1ns/100ps
  module counter_tb;
  
      reg clk_in;         // using wire won't let value to change inside initial blcok
      reg rst_in;
      reg enable_in;
      reg[3:0] count_out;
  
      counter counter_uut(.clk(clk_in), .rst(rst_in), .enable(enable_in), .count(count_out));
  
      initial begin
  
          // initialize clock, rst and others
          clk_in = 1'b0;          // clock toggles every 5 ns .... see REF_1
          rst_in = 1'b0;          // always NOT reseting
          enable_in = 1'b1;       // always counting
      end
  
      always begin 
          #5 clk_in =~ clk_in;   // ....saw REF_1
      end
  
  endmodule
  </code></pre>
  
  <p>I get error message:</p>
  
  <pre><code># ** Error: (vsim-3053) C:/Users/Daniel/Desktop/Verilog_Practice/Couter/Counter_tb.v(10): Illegal output or inout port connection for "port 'count'".
  </code></pre>
  
  <p>I've been struggle for hours trying to resolve the error.
  Can anyone tell me what is wrong with my test bench?</p>
  
  <p>Thank you</p>