title: Arithmetic Right Shift in Verilog
body: <p>As part of a processor design, I am implementing a simple behavioral right shifter using Verilog.</p>
  
  <p>The shifter inputs a 32 bit variable and outputs either a right logical shift or a right arithmetic shift based on a variable (input) choice. </p>
  
  <p>Following is the code:</p>
  
  <pre><code> module ShiftRight(
    input signed[31:0] inp,
    input [31:0] shamt,
    output [31:0] out,
    input choice
    );
  
    assign out = (choice)? (inp&gt;&gt;&gt;shamt):(inp&gt;&gt;shamt);
  
  
   endmodule
  </code></pre>
  
  <p>This results in a correct behavioral implementation but gives the following warning during synthesis:</p>
  
  <pre><code>Unit ShiftRight : the following signal(s) form a combinatorial loop: out_shift0000&lt;31&gt;.
  </code></pre>
  
  <p>(the coeff in brackets is basically the most significant bit of inp, 31 in my case). So I was wondering whether this had anything to do with inp bein signed. </p>