title: Quartus Prime VHDL component instantiation compile error
body: <p>I am having an issue when trying to compile the following code:</p>
  
  <pre><code>----------------
  ----------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity adder_top is
  Port ( a_in : in STD_LOGIC_VECTOR (3 downto 0);
         b_in : in STD_LOGIC_VECTOR (3 downto 0);
         clk : in STD_LOGIC;
         clk_en : in STD_LOGIC;
         carry_in : in STD_LOGIC;
         carry_out : out STD_LOGIC;
         c_out : out STD_LOGIC_VECTOR (3 downto 0));
  end adder_top;
  
  architecture Behavioral of adder_top is
  COMPONENT c_addsub_0
    PORT (
      A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      CLK : IN STD_LOGIC;
      C_IN : IN STD_LOGIC;
      CE : IN STD_LOGIC;
      C_OUT : OUT STD_LOGIC;
      S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
  END COMPONENT c_addsub_0;
  begin
  inst_1 : COMPONENT c_addsub_0
      port map
      (
          A =&gt; a_in,
          B =&gt; b_in,
          CLK =&gt; clk,
          C_IN =&gt; carry_in,
          CE =&gt; clk_en,
          C_OUT =&gt; carry_out,
          S =&gt; c_out
      );
  
  end Behavioral;
  
  ---------------------------
  ---------------------------
  </code></pre>
  
  <p>I receive the following error code when trying to compile:</p>
  
  <blockquote>
    <p>Error (12006): Node instance "inst_1" instantiates undefined entity
    "c_addsub_0". Ensure that required library paths are specified
    correctly, define the specified entity, or change the instantiation.
    If this entity represents Intel FPGA or third-party IP, generate the
    synthesis files for the IP.</p>
  </blockquote>
  
  <p>I am entirely unsure why I am receiving this error. Any help would be greatly appreciated.</p>