title: 4 Bit Adder using port maps
body: <p>So I am trying to do a 4 bit adder and have ran into an error I can't seem to figure out.</p>
  
  <p>Error (10430): VHDL Primary Unit Declaration error at adder1.vhd(3): primary unit "Adder1Vhd" already exists in library "work"</p>
  
  <p>I have a project called 4 bit adder and inside that project folder is the .vhd file for Adder1.vhd.  Here is the codes I have, if somebody could help me figure this out it would be greatly appreciated.</p>
  
  <p>Adder4.vhd:</p>
  
  <pre><code>LIBRARY IEEE; 
  USE IEEE.STD_LOGIC_1164.ALL; 
  
  ENTITY Adder4 IS
    GENERIC(CONSTANT N: INTEGER := 4);
    PORT(
      a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Input SW[7..4]: a[3..0] inputs,
                                               -- SW[3..0]: b[3..0]
      cIn: in std_logic;
      sum: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Output LEDR[3..0]
      cOut: OUT STD_LOGIC -- Output LEDR[4]
    );
  END Adder4;
  
  ARCHITECTURE imp OF Adder4 IS
    COMPONENT Adder1 
      PORT(
        a, b, cIn : in STD_LOGIC;
        sum, cOut : out STD_LOGIC);
    END COMPONENT;
    SIGNAL carry_sig: std_logic_vector(N-1 DOWNTO 0);
  BEGIN
  
    A1: Adder1 port map (a(0), b(0), cIn, sum(0), carry_sig(0));
    A2: Adder1 port map (a(1), b(1), carry_sig(0), sum(1), carry_sig(1));
    A3: Adder1 port map (a(2), b(2), carry_sig(1), sum(2), carry_sig(2));
    A4: Adder1 port map (a(3), b(3), carry_sig(2), sum(3), cOut);
  
  END imp;
  </code></pre>
  
  <p>Adder1.vhd(the file inside the Adder4 project folder):</p>
  
  <pre><code>library ieee; 
  use ieee.std_logic_1164.all; 
  
  entity Adder1Vhd is 
    port( 
      a, b, cIn : in std_logic; 
      sum, cOut : out std_logic);
  end Adder1Vhd; 
  
  architecture imp of Adder1Vhd is 
  begin 
    -- Add two lines (one for sum and the other for cOut) of VHDL code here
    sum &lt;= (a xor b) xor cIn;
    cOut &lt;= (a and b) or (cIn and (a xor b));
  end imp; 
  </code></pre>