title: Verilog input and output array
body: <p>I am new to verilog, so I was trying this out with it like what I always do in Java, and it just doesn't compile, I tried Googling, but nothing came up ...so, thanks !</p>
  
  <pre><code>module two_to_one_com(SW,LEDR,LEDG);
  
  input [15:0]SW ;
  input SW17;
  output [7:0]LEDR;
  output [7:0]LEDG;
  
  assign X = SW[7:0];
  assign Y = SW[15:8];
  assign s = SW17;
  assign LEDR[7:0] = SW;
  assign M = LEDG[7:0];
  
  
  integer index = 0;
  initial
  begin
  for(index=0;index&lt;=7;index = index+1)
      begin
      assign M[index] = (~s &amp;X[index])|(s&amp;Y[index]);
      end
  end
  
  
  endmodule
  </code></pre>
  
  <p>So, it just keeps telling me that array M,X and Y can't be indexed as they are undeclared ... Anyone know any solution? </p>