title: How to typecast integer to unsigned in VHDL
body: <p>I am trying to divide two integers as following:</p>
  
  <pre class="lang-vhdl prettyprint-override"><code>variable m0Low : integer := 0;
  variable m1Low : integer := 0;
  m1Low := divide(m1Low,m0Low);
  </code></pre>
  
  <p>With the  function :</p>
  
  <pre class="lang-vhdl prettyprint-override"><code>function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is    
      variable a1 : unsigned(a'length-1 downto 0):=a;    
      variable b1 : unsigned(b'length-1 downto 0):=b;    
      variable p1 : unsigned(b'length downto 0):= (others =&gt; '0');    
      variable i : integer:=0;               
      begin    
          for i in 0 to b'length-1 loop    
              p1(b'length-1 downto 1) := p1(b'length-2 downto 0);    
              p1(0) := a1(a'length-1);    
              a1(a'length-1 downto 1) := a1(a'length-2 downto 0);    
              p1 := p1-b1;    
              if(p1(b'length-1) ='1') then    
                  a1(0) :='0';    
                  p1 := p1+b1;    
              else    
                  a1(0) :='1';    
              end if;
          end loop;    
      return a1;    
  end divide;
  </code></pre>
  
  <p>However, I get the following error:
  <code>Divide can not have such operands in this context.</code></p>
  
  <p>I am trying to cast the variables to unsigned <code>m1Low := divide(unsigned(m1Low),unsigned(m0Low));</code></p>
  
  <p>But I get the following error:
  <code>The expression can not be converted to type unsigned.</code></p>
  
  <p>Any idea what I can do? 
  Thanks
  Haris</p>