title: Multidimensional Array Of Signals in VHDL
body: <p>I have a signal in VHDL declared like this : </p>
  
  <pre><code>signal Temp_Key : std_logic_vector(79 downto 0);
  </code></pre>
  
  <p>This <code>Temp_Key</code> is passed through a <code>for</code> loop 31 times and it is modified. I want to store all the 31 different <code>Temp_Keys</code> in an array. </p>
  
  <p>Is it possible to use multi-dimensional arrays in VHDL to store 80 bit signals ? </p>