title: Verilog Module Instantiation and empty begin end
body: <p>I have made two verilog modules. The first one takes a nine-bit number and returns the position of first occurrence of 1 in it.</p>
  
  <pre><code>module findPositionOf_1(
    input [8:0] data,
    output reg [3:0] position
    );
  
  
    always @(data)
    begin
      if(data==9'b0000_00000)
        position=4'b0000;
      else if(data[0]==1)
        position=4'b0000;
      else if(data[1]==1)
        position=4'b0001;
      else if(data[2]==1)
        position=4'b0010;
      else if(data[3]==1)
        position=4'b0011;
      else if(data[4]==1)
        position=4'b0100;
      else if(data[5]==1)
        position=4'b0101;
      else if(data[6]==1)
        position=4'b0110;
      else if(data[7]==1)
        position=4'b0111;
      else if(data[8]==1)
        position=4'b1000;
    end    
  
  endmodule
  </code></pre>
  
  <p>The second module is returning the second occurrence of 1. It is calling the first module first changing that bit to zero and again finding the occurrence of 1.</p>
  
  <pre><code>module findPositionOf_2nd_1(
    input [8:0] r1_data, 
    output [3:0] position1 
  );
  
  reg [3:0] pos,pos2; 
  reg [8:0] temp;
  
  integer i;
  always @(r1_data)
  begin
    findPositionOf_1 f1(.data(r1_data), .position(pos));
  
  
    i=pos;
    temp=r1_data;
    temp[i]=0;
    findPositionOf_1 f2(temp,pos2);
    if(pos2==4'b0000)
      position1=0;
    else
      position1=pos2;
  
  end
  
  endmodule
  </code></pre>
  
  <p>I am getting the following errors during compilation. Please help.</p>
  
  <blockquote>
    <p>Checker 'findPositionOf_1' not found. Instantiation 'f1' must be of a
    visible checker. 
    A begin/end block was found with an empty body.  This
    is permitted in SystemVerilog, but not permitted in Verilog.  Please
    look for any stray semicolons.</p>
  </blockquote>