title: Differences between pipeline and rising_edge in vhdl?
body: <p>I'm trying to understand some VHDL code and I'm stuck with understanding this part:</p>
  
  <pre><code>...
  accumulated_x &lt;= input_x;
  ...
       if accumulated_x = '0' and input_x = '1' then
  </code></pre>
  
  <p>For me it is the same as:</p>
  
  <pre><code>if rising_edge(input_x) then
  </code></pre>
  
  <p>But when I replace it like this, it does not work and then it means it not the same, why?       </p>