title: How do I keep Xilinx XST from merging nets from my design?
body: <p>I'm asking and answering this question so that I can find it again in the future... </p>
  
  <p>How do I  keep XST from merging two logically equivalent nets into one (which normally is a good idea to save resources, but may not be a good idea from a timing view)?</p>
  
  <p>I have a design with 2 counters that are driven by the same clk. XST merged the lowest bit of the counters into one counter, but this is a problem, because the counters need to be separated in the design due to IOB placement constraints. I need the counters (specifically the lowest bit of the counter) to be distinct.</p>