title: How to create a test bench code for full adder?
body: <p>How can I make a testbench for this full adder code. I'm a newbie and would appreciate any help.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Full_Adder is
  
  PORT(a , b , C_In : IN STD_LOGIC; S,C_Out : OUT STD_LOGIC);
  
  end Full_Adder;
  
  architecture Behavioral of Full_Adder is
  begin
  
  S &lt;= a XOR b XOR C_In;
  C_Out &lt;= (a AND b) OR (a AND C_In) OR (b AND C_In);
  
  end Behavioral;
  </code></pre>