title: Variable generic assignment in generate loop
body: <p>What I want to do doesn't seem particularly complex, but I can't think of a simple way to do it in VHDL.</p>
  
  <p>I have a component with a generic parameter called <code>FOO</code>. I would like to generate 16 of these components and for the first 8 instances I want <code>FOO</code> to be set to <code>0</code> and the other 8 instances I want <code>FOO</code> to be set to <code>4096</code>.</p>
  
  <p>Ideally, I would be able to do something like this:</p>
  
  <pre><code>generate_loop: for I in 0 to 15 generate
  begin
    comp_inst: my_component
    generic map
    (
      FOO =&gt; 0 when I &lt; 8 else 4096
    )
    port map
    (
    ...
    );
  end generate;
  </code></pre>
  
  <p>This is of course not valid VHDL, but that captures the idea of what I'd like to do.</p>
  
  <p>So my question is: is there a way to implement this in a single generate loop (i.e. without having to have 2 separate generate loops with different indices), and if so, how do I do it?</p>