title: VHDL generating control signals as flip-flops
body: <p>I created a finite state machine with four states using VHDL, but I'm having a problem to understand what is happening with the control signals that the FSM generates. I was expecting that these signals were generated dynamically without the need of storing it in flip-flops, but this is not happening - the synthesis is creating flip-flops for all of them.</p>
  
  <p>To illustrate my problem, I'll put part of my code here:</p>
  
  <p>For example, this is a register that I use:</p>
  
  <pre><code>-- register
  signal register : STD_LOGIC_VECTOR (2 downto 0);
  signal in_register : STD_LOGIC_VECTOR (2 downto 0);
  signal c_register : STD_LOGIC;
  </code></pre>
  
  <p>-- </p>
  
  <pre><code>-- register logic
  process (clock)
  begin
      if (clock = '1' and clock'event) then
          if (reset = '1') then
              register &lt;= "000";
          elsif (c_register = '1') then
              register &lt;= in_register;
          else
              register &lt;= register;
          end if;
      end if;
  end process;
  </code></pre>
  
  <p>My FSM must generate the <code>c_register</code> signal, and it is similar to this:</p>
  
  <pre><code>-- FSM
  process (clock)
  begin
      if (clock = '1' and clock'event) then
           if (reset = '1') then
                c_register &lt;= '0';
                state &lt;= A;
                ...
           else
               case state is
                   when A =&gt;
                       c_register &lt;= '0';
                       state &lt;= B;
                       ...
                   when B =&gt;
                       c_register &lt;= '0';
                       state &lt;= C;
                       ...
                   when C =&gt;
                       if (X) then
                           c_register &lt;= '0';
                       else
                           c_register &lt;= '1';
                       end if;
                       state &lt;= D;
                   when D =&gt;
                       c_register &lt;= '0';
                       state &lt;= A;
               end case;
           end if;
      end if;
  end process;
  </code></pre>
  
  <p>My FSM is not exactly the same that I showed above, but as you can see I give a value to <code>c_register</code>  in every state, just to be sure that the VHDL compiler will not think that I want a flip-flop to store an older value.</p>
  
  <p>When I compile it, the <code>c_register</code> signal becomes a flip-flop!</p>
  
  <p>I'm a bit confused. Appreciate any help! Thanks!</p>