title: VHDL MIPS 5 stage pipeline Bug
body: <p>The code for this is too long to post so Ill just describe it. I've created a 5 stage mips pipe that almost works. The catch is that EVERY lw instruction that reaches the instruction decode stage overwrites the control signal values in the execution stage. Not only that it causes the PC to skip can instruction, i.e from 300 -> 308. I just need some idea on where to look for bugs since this is a class assignment. If we take out all the LW instructions the CPU works fine.</p>
  
  <p>Example: 
   The adder in the EX stage is going to  sub $4 $1 $2  which should be 1
   Once LW enters the ID stage ALUsrc is asserted AND ALUop is changed from subtract to add
   This forces the adder in the EX stage to add $4 $1 $2 resulting in 5 being stored in $4</p>