title: Inferring latches in Verilog/SystemVerilog
body: <p>The statements in procedural blocks execute seqeuntially so why aren't any of the block1, block2 or block3 inferring a latch?</p>
  
  <pre><code>module testing(
      input  logic a, b, c,
      output logic x, y, z, v
      );
  
      logic tmp_ref, tmp1, tmp2, tmp3;
  
      //reference
      always_comb begin: ref_block
          tmp_ref = a &amp; b;
          x = tmp_ref ^ c;
      end
  
      always_comb begin: block1
          y = tmp1 ^ c;
          tmp1 = a &amp; b;
      end
  
      always @(*) begin: block2
          tmp2 &lt;= a &amp; b;
          z = tmp2 ^ c;
      end
  
      always @(c) begin: block3
          tmp3 = a &amp; b;
          v = tmp3 ^ c;
      end
  endmodule: testing
  </code></pre>
  
  <p>In block1 y is calculated using the blocking assignment before the new value of tmp1 is available.</p>
  
  <p>In block2 tmp2 is calculated using a non-blocking assignment, which should postpone the assignment for when the always block finishes. Meanwhile, z is calculated using the blocking assignment and the new value of tmp2 is not yet available.</p>
  
  <p>In block3 there is an incomplete sensitivity list and still no latch.</p>
  
  <p>Here is the synthesis result from Quartus II 14.1:
  <img src="https://i.stack.imgur.com/Fz8wh.png" alt="enter image description here"></p>
  
  <p>Only when I add this block a latch is inferred:</p>
  
  <pre><code>//infers a latch
  always @(*) begin: block4
      if (c == 1'b1) begin
          tmp4 = a &amp; b;
          w = tmp4 ^ c;
      end
  end
  </code></pre>
  
  <p>Can someone please explain why incomplete sensitivity list or using a variable before the value is updated does not infer a latch in a combinatorial block?</p>