title: verilog testbench component instantiate using generate
body: <p>I'm new to verilog and learning.  I have a testbench questions.
  Suppose in Verilog testbench I have 8 instances of a module.
  Is there a way to instantiate them in the testbench using a generate loop like a module can be declared in the HDL part of the code. For example</p>
  
  <pre><code>module my_test_bench;
  reg one_r;
  reg two_r;
  
  wire one_w;
  wire two_w;
  
  genvar i;
  generate
  (for i = 0; i &lt; 8; i=i+1)
  begin
     DDR3_module uut[i]( .clk(), .rst(), );
  end
  endgenerate
  
  initial begin
   ... test stimulus
  end
  
  end module
  </code></pre>
  
  <p>Thanks.</p>