title: Multiplexer on VHDL
body: <p>I tried to create multiplexer:</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  
  
  --  Entity Declaration
  
  ENTITY multiplekser IS
  -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
  PORT
  (
  U : IN STD_LOGIC_VECTOR(2 downto 0);
  V : IN STD_LOGIC_VECTOR(2 downto 0);
  W : IN STD_LOGIC_VECTOR(2 downto 0);
  X : IN STD_LOGIC_VECTOR(2 downto 0);
  Y : IN STD_LOGIC_VECTOR(2 downto 0);
  S : IN STD_LOGIC_VECTOR(2 downto 0);
  CS : IN STD_LOGIC;
  M : OUT STD_LOGIC_VECTOR(2 downto 0)
  );
  -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
  
  END multiplekser;
  
  
  --  Architecture Body
  
  ARCHITECTURE multiplekser_architecture OF multiplekser IS
  
  
  BEGIN
      PROCESS(CS)
      BEGIN
      if (CS = '1') then
          with S select
              M&lt;=U when "000",
                  V when "001",
                  W when "010",
                  X when "011",
                  Y when others;
      else 
          M&lt;="ZZZ";
      end if;
      END PROCESS;
  END multiplekser_architecture;
  </code></pre>
  
  <p>but some errors has occured:
  <img src="https://i.stack.imgur.com/C7wxc.png" alt="errors"></p>
  
  <p>I did it on Quartus II 64 bit. Here is my block diagram:
  <img src="https://i.stack.imgur.com/EVypG.png" alt="block diagram"></p>
  
  <p>CS is enable signal. When CS is 0, M(output) must have high impedance.</p>