title: Overriding a makefile variable
body: <p>I have a master makefile which has the default values for variables and then a child makefile which includes project specific settings. At the end of the child makefile, I include the master makefile.</p>
  
  <p>I have been using the following code in the master makefile to set default values for a variable</p>
  
  <pre><code>ifndef CC
      CC = avr-gcc
  endif
  </code></pre>
  
  <p>And then recently I read that I can also do </p>
  
  <pre><code>CC ?= avr-gcc
  </code></pre>
  
  <p>So my question is, whether both are same and if yes which one is the recommended way of overriding variables.</p>