title: SystemVerilog Parameters with defined width
body: <p>I have the following VHDL code that defines a constant of particular width.</p>
  
  <pre><code>constant WIDTH : natural := 16
  constant X : std_logic_vector(WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(16#0#, WIDTH));
  </code></pre>
  
  <p>How do I define something like this in SystemVerilog?</p>
  
  <p>I would assume that something like this would correspond to</p>
  
  <pre><code>parameter WIDTH = 16
  parameter X = WIDTH'd1231413412
  </code></pre>
  
  <p>But this doesn't seem to work with my Verilog compiler</p>