title: reevaluate wildcard in make
body: <p>In my Makefile, I want to check if a certain file exists, do something, and check again. Using gnu make, I cannot. Here is the simple example:</p>
  
  <pre><code>$(info $(wildcard OK))
  $(shell touch OK)
  $(info $(wildcard OK))
  </code></pre>
  
  <p>If I run <code>make</code> once, I see two empty lines. If I run <code>make</code> again, both lines are <code>OK</code>.</p>
  
  <p>I thought, maybe <code>$(eval)</code> will let me get the updated answer. Alas,</p>
  
  <pre><code>$(eval $$(info $$(wildcard OK)))
  </code></pre>
  
  <p>produces the same answer, as if <code>make</code> has some way to predict all wildcard calculations before it starts evaluating other commands.</p>
  
  <p>I need this to satisfy the checks performed by Android NDK: I must generate a <a href="https://android.googlesource.com/platform/ndk/+/master/build/core/prebuilt-shared-library.mk" rel="nofollow noreferrer"><em>prebuilt shared library</em></a> on the fly.</p>