title: Comparing a long std_logic_vector to zeros
body: <p>In simulation this works perfect. Is this is the best way of checking for
  zeros for a synthesisable code. What would be the resources generated?</p>
  
  <pre><code>signal vector_slv : std_logic_vector(2048 downto 0);
  ...
  if (vector_slv = (vector_slv'range =&gt; '0')) then
    -- do something...
  </code></pre>
  
  <p>Is there any other optimal way to implement this solution considering h/w mapping (with optimal resource utilization).</p>
  
  <p>I would be more interested in understanding the resources used.</p>