title: SRA can not have such operands?
body: <p>I have coded an algorithm in VHDL but I have this message that I don't understand "sra/sla can not have such operands in this context.". Any help please?</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use ieee.std_logic_arith.conv_std_logic_vector;
  
  entity hsl2rgb is
      generic(
          constant hue : integer := 85;
          constant sat : integer := 127
      );
      port(
          lum    : in  std_logic_vector(7 downto 0);
          ored   : out std_logic_vector(5 downto 0);
          ogreen : out std_logic_vector(5 downto 0);
          oblue  : out std_logic_vector(5 downto 0)
      );
  end entity;
  
  architecture behavioral of hsl2rgb is
  begin
  
      process(lum)
          variable v : integer;
          variable m : integer;
          variable sextant : integer;
          variable fract : integer;
          variable vsf : integer;
          variable mid1 : integer;
          variable mid2 : integer;
          variable lumx : integer;
      begin
          lumx := to_integer(unsigned(lum));
          if (lumx &lt; 127) then
              v := (lumx * (256 + sat)) sra 8;
          else
              v := (((lumx + sat) sla 8) - lumx * sat) sla 8;
          end if;
  
          if (v &lt;= 0) then
              ored &lt;= (others =&gt; '0');
              ogreen &lt;= (others =&gt; '0');
              oblue &lt;= (others =&gt; '0');
          else
              m := (2 * lumx) - v;
              sextant := (hue * 6) sra 8;
              fract := (hue * 6) - (sextant sla 8);
              vsf := (fract * (v - m)) sra 8;
              mid1 := m + vsf;
              mid2 := v - vsf;
  
              case sextant is
                  when 0 =&gt;
                      ored &lt;= conv_std_logic_vector(v, 6);
                      ogreen &lt;= conv_std_logic_vector(mid1, 6);
                      oblue &lt;= conv_std_logic_vector(m, 6);
                  when 1 =&gt;
                      ored &lt;= conv_std_logic_vector(mid2, 6);
                      ogreen &lt;= conv_std_logic_vector(v, 6);
                      oblue &lt;= conv_std_logic_vector(m, 6);
                  when 2 =&gt;
                      ored &lt;= conv_std_logic_vector(m, 6);
                      ogreen &lt;= conv_std_logic_vector(v, 6);
                      oblue &lt;= conv_std_logic_vector(mid1, 6);
                  when 3 =&gt;
                      ored &lt;= conv_std_logic_vector(m, 6);
                      ogreen &lt;= conv_std_logic_vector(mid2, 6);
                      oblue &lt;= conv_std_logic_vector(v, 6);
                  when 4 =&gt;
                      ored &lt;= conv_std_logic_vector(mid1, 6);
                      ogreen &lt;= conv_std_logic_vector(m, 6);
                      oblue &lt;= conv_std_logic_vector(v, 6);
                  when 5 =&gt;
                      ored &lt;= conv_std_logic_vector(v, 6);
                      ogreen &lt;= conv_std_logic_vector(m, 6);
                      oblue &lt;= conv_std_logic_vector(mid2, 6);
                  when others =&gt;
                      ored &lt;= (others =&gt; '0');
                      ogreen &lt;= (others =&gt; '0');
                      oblue &lt;= (others =&gt; '0');
              end case;
          end if;
      end process;
  end architecture;
  </code></pre>