title: FSM verilog code syntax error
body: <p>I am trying to design a fsm for showing rotational which runs the 4-digit 7-segment LED display unit, to cause a rotating pattern of circulating squares in clockwise or counterclockwise.  I am trying to fix the syntax errors in my case block but I am in verilog coding and I cannot find my mistake. Here is the code: </p>
  
  <pre><code>module fsm( EN, CW, clk, AN1,AN2,AN3,AN4, leds );
  
  //inputs and outputs
  input EN, CW, clk;
  output AN1,AN2,AN3,AN4;
  output reg leds[6:0];
  
  //state register and parameters
  reg state[3:0];
  
  parameter s0 = 3'b000;
  parameter s1 = 3'b001;
  parameter s2 = 3'b010;
  parameter s3 = 3'b011;
  parameter s4 = 3'b100;
  parameter s5 = 3'b101;
  parameter s6 = 3'b110;
  parameter s7 = 3'b111;
  
  
  //states and outputs according to the states
  
      always @ (posedge clk)
      begin
              if (EN == 1)
              begin
                      case(state)
                              s0: leds&lt;=7'b1100011; if(CW)begin  state &lt;= s1;  end else begin state &lt;= s7;  end
                              s1: leds&lt;=7'b1100011; if(CW)begin  state &lt;= s2;  end else begin state &lt;= s0;  end
                              s2: leds&lt;=7'b1100011; if(CW)begin  state &lt;= s3;  end else begin state &lt;= s1;  end
                              s3: leds&lt;=7'b1100011; if(CW)begin  state &lt;= s4;  end else begin state &lt;= s2;  end
                              s4: leds&lt;=7'b1011100; if(CW)begin  state &lt;= s5;  end else begin state &lt;= s3;  end
                              s5: leds&lt;=7'b1011100; if(CW)begin  state &lt;= s6;  end else begin state &lt;= s4;  end
                              s6: leds&lt;=7'b1011100; if(CW)begin  state &lt;= s7;  end else begin state &lt;= s5;  end
                              s7: leds&lt;=7'b1011100; if(CW)begin  state &lt;= s0;  end else begin state &lt;= s6;  end
                      endcase
              end
      end
  
  //output logic
  assign AN1 = ~((state == s0) | (state == s7));
  assign AN2 = ~((state == s1) | (state == s6));
  assign AN3 = ~((state == s2) | (state == s5));
  assign AN4 = ~((state == s3) | (state == s4));        
  
  endmodule
  </code></pre>