title: Passing parameters to Verilog modules
body: <p>I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies.
  Which of these methods is the best way to parametrize modules? 
  What is the difference? 
  Is it vendor-dependent (Altera vs Xilinx)? </p>
  
  <p>The first method:
  Module definition:</p>
  
  <pre><code>module busSlave #(parameter DATA_WIDTH = 1) (
    input [DATA_WIDTH-1:0] bus_data,
    input                  bus_wr,
    ...
  );
  endmodule
  </code></pre>
  
  <p>Module instantiation:</p>
  
  <pre><code>module top;
  
    //DATA_WIDTH is 32 in this instance
    busSlave #(.DATA_WIDTH(32)) slave32(
      .bus_data(data_0),
      .bus_wr(wr_0),
      ...
      );
  
    //DATA_WIDTH is 64 in this instance
    busSlave #(.DATA_WIDTH(64)) slave64(
      .bus_data(data_1),
      .bus_wr(wr_1),
      ...
      );
  endmodule
  </code></pre>
  
  <p>The second method:
  Module definition:</p>
  
  <pre><code>module busSlave(
    parameter DATA_WIDTH = 1;
    input [DATA_WIDTH-1:0] bus_data,
    input                  bus_wr,
    ...
  );
  endmodule
  </code></pre>
  
  <p>Module instantiation:</p>
  
  <pre><code>module top;
  
    //DATA_WIDTH is 32 in this instance
    busSlave slave32(
      .bus_data(data_0),
      .bus_wr(wr_0),
      ...
      );
    defparam slave32.DATA_WIDTH = 32;
  
    //DATA_WIDTH is 64 in this instance
    busSlave slave64(
      .bus_data(data_1),
      .bus_wr(wr_1),
      ...
      );
    defparam slave32.DATA_WIDTH = 64;
  endmodule
  </code></pre>
  
  <p>Thanks in advance</p>
  
  <p>EDIT: a few corrections in the examples</p>