title: T Flip Flop with clear (VHDL)
body: <p>I'm having problems coding a T Flip Flop with clear and reset. As the picture below shows, t_in is operating as enable input, that will be set to 1 or 0 from a mod-m counter. to_ldspkr will  then toggle. The clr_FF will clear the flip flop. </p>
  
  <p><a href="https://www.dropbox.com/s/qld5hp9qzsmnfr4/Screenshot%20from%202014-10-11%2021%3A39%3A04.png?dl=0" rel="nofollow noreferrer">Link to the block diagram</a></p>
  
  <p><img src="https://i.stack.imgur.com/hszF8.png" alt="linked block diagram"></p>
  
  <p>I'm now sure how I should code this flip flop. This is my code, but it's not working:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  
  entity T_FF is
      port(
          from_t_in : in std_logic;
          clk, reset : in std_logic;
          from_clr_FF : in std_logic;
          to_ldspkr : out std_logic
      );
  end T_FF;
  
  architecture Behavioral of T_FF is
      signal temp: std_logic;
      signal r_reg, r_next : std_logic;
  
      begin
      process(reset, clk, from_clr_FF, r_reg)
      begin
          if(reset = '1') then
              r_reg &lt;= '0';   
          elsif(from_clr_FF = '1') then
              r_next  &lt;= '0';
          elsif(clk'event and clk='1') then
              if(from_t_in = '1') then
                  temp &lt;= not temp;
              end if;
          end if;
      end process;
      to_ldspkr &lt;= temp;
  end Behavioral;
  </code></pre>