title: Array assignment not updating in Verilog
body: <p>I have the following code:</p>
  
  <pre><code>reg [7:0]data[0:7];
  always @(posedge clk) begin
      data[var1]&lt;=var2;
      $write("%d:%d:%d", var1, var2, data[var1]);
  end
  </code></pre>
  
  <p>3:100:    x is printed, so the data assignment is not working correctly. Why is this?</p>