title: Drive input clock to output
body: <p>I've a module that have a 8bit input and a serial output, I want to serialize input data and synchronize it with a clock.</p>
  
  <p>I want to set my data when falling edge then wait when clock rise, when clock fall again I set another data. I don't want to connect the directly reference clock to the output because when I don't use this module I want a 1 state on clock output.</p>
  
  <p>I've tried this code:</p>
  
  <pre><code>process(Clock, ModuleReset)
      begin
          if ModuleReset = '0' then
              OutData &lt;= '0';
              OutCK &lt;= '0';
              counter &lt;= 7;
          elsif falling_edge(Clock) then
                  OutCK &lt;= '0';
                  OutData &lt;= Data(counter);
          elsif rising_edge(Clock) then
                  OutCK &lt;= '1';
          end if;
  end process;
  </code></pre>
  
  <p>The synthesizer gives me this error:</p>
  
  <blockquote>
    <p>"Asynchronous load of non-constant data for SCK is not supported"  </p>
  </blockquote>
  
  <p>When I separate the code in two blocks like this:</p>
  
  <pre><code>process(Clock, ModuleReset)
      begin
          if ModuleReset = '0' then
              OutData &lt;= '0';
              OutCK &lt;= '0';
              counter &lt;= 7;
          elsif falling_edge(Clock) then
                  OutCK &lt;= '0';
                  OutData &lt;= Data(counter);
  end process;
  
  process(Clock)
          if rising_edge(Clock) then
                  OutCK &lt;= '1';
          end if;
  end process;
  </code></pre>
  
  <p>I have these two errors:</p>
  
  <blockquote>
    <p>"Multiple non tristate drivers for net SCK"<br>
    "Unresolved tristate drivers for net SCK"  </p>
  </blockquote>
  
  <p>Another code I've tried is:</p>
  
  <pre><code>process(Clock, ModuleReset)
      if ModuleEN = '1' then
         OutCK &lt;= Clock;
      end if;
      begin
          if ModuleReset = '0' then
              OutData &lt;= '0';
              OutCK &lt;= '0';
              counter &lt;= 7;
          elsif falling_edge(Clock) then
                  OutCK &lt;= '0';
                  OutData &lt;= Data(counter);
          end if;
  end process;
  </code></pre>
  
  <p>But the output clock looks strange with a different frequency.</p>