title: How to handle bidirectional pin (inout) in a verilog task
body: <p>I want to use a bidirectional data bus in my controller.Here's the code</p>
  
  <pre><code>module controller ( clk, data_out);
  // Port Declaration
  input   clk;
  inout   [7:0] data_out;
  
  reg     [7:0] a;
  reg     [7:0] b;
  wire    [7:0] c;
  
  // data should write to data_out (data_out act as output)
  
  task write; 
  input c;
  begin
  
  assign data_out = a;
  data_out &lt;= c;
  
  end
  endtask
  
  // data should read from data_out (data_out act as input)
  
  task read; 
  output b;
  begin
  
  assign data_out = 8'bz;
  b &lt;= data_out;
  
  end
  endtask
  
  endmodule
  </code></pre>
  
  <p>when I compile this i'm getting an error saying</p>
  
  <blockquote>
    <p>LHS in procedural continuous assignment may not be a net: data_out.</p>
  </blockquote>
  
  <p>it's says there is an error in  <code>assign data_out = a;</code> and <code>assign data_out = 8'bz;</code> 
  I know assign should be done in always or initial block but in a task using those blocks are useless/give eroor </p>
  
  <p>Then, how we can change directions of the bus in side a task?? </p>