title: VHDL Case choice is not locally static
body: <p>This code works with some tools</p>
  
  <ul>
  <li>Aldec Riviera Pro</li>
  </ul>
  
  <p>but not others</p>
  
  <ul>
  <li>GHDL ( ERROR choice must be locally static expression)</li>
  </ul>
  
  <pre><code>LIBRARY IEEE;
  USE IEEE.std_logic_1164.ALL;
  USE IEEE.numeric_std.ALL;
  
  ENTITY INSTRUCTION_PROCESSOR IS
  
      PORT (
          clk : IN std_logic;
          instruction : IN INTEGER
      );
  END ENTITY INSTRUCTION_PROCESSOR;
  ARCHITECTURE behavioural OF INSTRUCTION_PROCESSOR IS
  
      TYPE INSTRUCTION_t IS RECORD
          instr : INTEGER;
          cycles : INTEGER;
      END RECORD;
  
      CONSTANT CMD_A : INSTRUCTION_t := (instr =&gt; 0, cycles =&gt; 5);
      CONSTANT CMD_B : INSTRUCTION_t := (instr =&gt; 1, cycles =&gt; 3);
  
  BEGIN
      PROCESSOR : PROCESS (clk)
          VARIABLE loop_cycles : INTEGER := 0;
      BEGIN
          IF clk'event AND clk = '1' THEN
              CASE instruction IS
                  WHEN CMD_A.instr =&gt;
                      loop_cycles := CMD_A.cycles;
  
                  WHEN CMD_B.instr =&gt;
                      loop_cycles := CMD_B.cycles;
  
                  WHEN OTHERS =&gt;
                      NULL;
              END CASE;
          END IF;
      END PROCESS;
  END ARCHITECTURE;
  </code></pre>
  
  <p><a href="https://www.edaplayground.com/x/jYD" rel="nofollow noreferrer">https://www.edaplayground.com/x/jYD</a></p>
  
  <p>since CMD_A and CMD_B are declared as <strong>constant</strong> records i would expect this to work...</p>
  
  <p>any words of wisdom or is it just a bad idea?</p>