title: Illegal assignment expression in continuous assignment. Verilog Octal 2 to 1 Mux
body: <p>I'm trying to code an Octal (8-bit inputs) 2-to-1 Multiplexer.  Here is my code:</p>
  <pre><code>module octal2to1mux(input [7:0] a, input [7:0] b, input s, output w);
  
  assign w= (s=1'b0) ? a:
            (s=1'b1) ? b: 1'bx;
  endmodule
  </code></pre>
  <p>When I try to compile, I get the following error:</p>
  <pre><code>octal2to1mux.sv(3): Illegal assignment expression in continuous assignment.
  </code></pre>
  <p>I just want to get w=a if s=0 and w=b if s=1. a and b are both 8-bit inputs. I use this module twice in the testbench.</p>