title: Pulse generator in VHDL with any frequency
body: <p>I am doing this project that will output a desired frequency. For most frequencies i can make valid code, but when it comes to frequency like 300 Hz I'm having trouble.</p>
  
  <p>So here is my code for most of them:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;    
  
  entity test is
  port(
      clk:in std_logic:='0';
      clk_o:buffer std_logic:='0'
  );
  end test;
  
  architecture Behavioral of test is
  begin
  process(clk)
  variable temp:integer range 0 to 1000000:=0;
  begin
  if(clk'event)then
      temp:=temp+1;
      if(temp&gt;=1000000)then
          clk_o&lt;=not clk_o;
          temp:=0;
      end if;
  end if;
  end process;
  end Behavioral;
  </code></pre>
  
  <p>This will generate frequency of 50 Hz because the clock speed of my FPGA is 50 MHz. So first I tried to divide it, but problem is that you can't generate 300 Hz because 50*10^6/300 is 166666.667 and so on. </p>
  
  <p>Then I saw that you can make time type of variable and make period last 1/300 but then i realized  it is not synthesis eligible so it's no good. Also goes with REAL type of variable that could make it more accurate then integer variable but it's also not synthesis eligible.</p>
  
  <p>So I'm out of ideas, if anyone can give me some hint I would much appreciate it.</p>