title: Illegal type conversion VHDL
body: <p>I was trying to return type std_logic_vector by type conversion in vhdl.
  Here is my code:</p>
  
  <pre><code> function mul(num1,num2 : in std_logic_vector(7 DOWNTO 0)) return std_logic_vector is
      variable v_TEST_VARIABLE1 : integer;
      variable v_TEST_VARIABLE2 : integer;
      variable n_times: integer:=1;
      variable product: integer:=0;
      begin 
        for n_times in 1 to v_TEST_VARIABLE2 loop
          product:=product + v_TEST_VARIABLE1;
        end loop;
      return std_logic_vector(product);
    end mul;
  </code></pre>
  
  <p>It gives <code>"Illegal type conversion from std.standard.integer to ieee.std_logic_1164.std_logic_vector (numeric to array)."</code> on compilation.
  How do I return std_logic_vector in such a code?</p>