title: VHDL shift register with enable
body: <p>I am newbie to VHDL. I am implementing serial in serial out 72 bit shift register using VHDL. When the enable signal is high, I want the shift register to shift 72 times, irrespective of whether enable continues to be high or low. I have written the following code which is working only when the enable is high. Can anyone please help me to shift data once enable is high and then does not depend on enable to shift the data?</p>
  
  <hr>
  
  <pre><code>library ieee; 
  use ieee.std_logic_1164.all; 
  
  entity SR is
    port(clk, din, rst, enable : in std_logic; 
         sr_out : inout std_logic_vector(71 downto 0)); 
  end SR; 
  
  architecture behavioral of SR is 
     signal shift_reg: std_logic_vector(71 downto 0); 
  begin
  
  process (clk, rst) 
  begin 
     if (rst = '0') then
        shift_reg &lt;= (others =&gt; '0');
     elsif (clk'event and clk = '1') then
        if enable= '1' then 
           shift_reg(70 downto 0) &lt;= shift_reg(71 downto 1);
           shift_reg(71) &lt;= din;
        end if;
     end if;
  
  end process;
  sr_out &lt;= shift_reg;
  end behavioral; 
  </code></pre>
  
  <p>Thanks a lot!</p>