title: Ideas for a flexible/generic decoder in VHDL
body: <p>I want to create an address Decoder that is flexible enough for me to use when changing the number of bits of the selector and of the decoded output signals.</p>
  
  <p>So, instead of having a static (fixed input/output size) Decoder that looks something like this :</p>
  
  <pre><code>entity Address_Decoder is
  Generic
  (
      C_INPUT_SIZE: integer := 2
  );
  Port
  (
      input   : in  STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
      output  : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
      clk : in  STD_LOGIC;
      rst : in  STD_LOGIC
  );
  end Address_Decoder;
  
  architecture Behavioral of Address_Decoder is
  
  begin        
          process(clk)
              begin
                 if rising_edge(clk) then 
                    if (rst = '1') then
                       output &lt;= "0000";
                    else
                       case &lt;input&gt; is
                          when "00" =&gt; &lt;output&gt; &lt;= "0001";
                          when "01" =&gt; &lt;output&gt; &lt;= "0010";
                          when "10" =&gt; &lt;output&gt; &lt;= "0100";
                          when "11" =&gt; &lt;output&gt; &lt;= "1000";
                          when others =&gt; &lt;output&gt; &lt;= "0000";
                       end case;
                    end if;
                 end if;
              end process;
  
  end Behavioral;
  </code></pre>
  
  <p>Have something that is more flexible/general, that looks like this:</p>
  
  <pre><code>    entity Address_Decoder is
      Generic
      (
          C_INPUT_SIZE: integer := 2
      );
      Port
      (
          input   : in  STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
          output  : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
          clk : in  STD_LOGIC;
          rst : in  STD_LOGIC
      );
      end Address_Decoder;
  
      architecture Behavioral of Address_Decoder is
  
      begin        
  
  DECODE_PROC:
      process (clk)
      begin
  
          if(rising_edge(clk)) then
           if ( rst = '1') then
             output &lt;= conv_std_logic_vector(0, output'length);
           else
             case (input) is
               for i in 0 to (2**C_INPUT_SIZE)-1 generate
               begin
                  when (i = conv_integer(input)) =&gt; output &lt;= conv_std_logic_vector((i*2), output'length);        
               end generate;
              when others =&gt; output &lt;= conv_std_logic_vector(0, output'length);
             end case;
           end if;
          end if;
      end process;
  
      end Behavioral;
  </code></pre>
  
  <p>I know this code is not valid and that the "when" test cases must be constants and that I can't use the for-generate in between the case statement like that, but it shows what it is that I am after: an entity smart enough to grow to my needs.</p>
  
  <p>I have been trying to find an elegant solution for this problem without much success, so, I'm open for any suggestions.</p>
  
  <p>Thanks in advance,
  Erick</p>