title: RISC-V: Implementing SLLI, SRLI and SRAI
body: <p>In RISC-V  instruction set manual, the shift Immediate instructions:</p>
  
  <ol>
  <li>SLLI (Shift Left Logical Immediate).</li>
  <li>SRLI (Shift Right Logical Immediate).</li>
  <li>SRAI (Shift Right Arithmetic Immediate).</li>
  </ol>
  
  <p>It is mentioned in the manual </p>
  
  <blockquote>
    <p>Shifts by a constant are encoded as a specialization of the I-type
    format. The operand to be shifted is in rs1, and the shift amount is
    encoded in the lower 5 bits of the I-immediate field. The right shift
    type is encoded in a high bit of the I-immediate. SLLI is a logical
    left shift (zeros are shifted into the lower bits); SRLI is a logical
    right shift (zeros are shifted into the upper bits); and SRAI is an
    arithmetic right shift (the original sign bit is copied into the
    vacated upper bits).</p>
  </blockquote>
  
  <p>When it is said that</p>
  
  <blockquote>
    <p>shift amount is encoded in the lower 5 bits of the I-immediate
    field.</p>
  </blockquote>
  
  <p>How it will be encoded exactly?</p>
  
  <p>Another thing does that mean it will take multiple clock cycles to shift as specified in the lower 5 bits of the I-immediate? or can this be done in one clock cycle?
  <a href="https://i.stack.imgur.com/dXn4W.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dXn4W.png" alt="enter image description here"></a></p>