title: Component instantiation error
body: <p>For the following VHDL code:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  entity dff is
    port(
        d, clk: in std_logic;
        q: out std_logic);
  end dff;
  architecture behave of dff is
    begin
      process(clk)
        begin
        if(clk = '1') then
          q&lt;= d;
      end if;
    end process;
  end behave; 
  </code></pre>
  
  <h2>---------------------------------------------------------------------</h2>
  
  <p>and and a testbench:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  entity dff is
  end dff;
  architecture behave of dff is
    component dff is
  port(d, clk: in std_logic;
       q: out std_logic);
  
  
   end component;
  
  
      signal  d_in: std_logic;
      signal  clk_in: std_logic;
      signal  q_out: std_logic;
  
  begin
    d_ff : dff port map( d_in, clk_in, q_out);
    process
      begin
        if(clk_in = '1') then
        q_out&lt;= d_in;
        end if;
    end process;
  end behave;  
  </code></pre>
  
  <p>When trying to simulate Modelsim is showing the following error:</p>
  
  <blockquote>
    <p>#Error loading design<br>
    The following component ports are not on the entity:<br>
    &nbsp;&nbsp;&nbsp;&nbsp;          q<br>
    &nbsp;&nbsp;&nbsp;&nbsp;          clk<br>
    &nbsp;&nbsp;&nbsp;&nbsp;          d  </p>
  </blockquote>