title: How many bits are in the address field for a directly mapped cache?
body: <p>This is a question based on <a href="https://stackoverflow.com/questions/15937002/how-does-direct-mapped-cache-work">Direct Mapped Cache</a> so I am assuming that it's ok to ask here as well.</p>
  
  <p>Here is the problem I am working on: <BR />
  <strong>The Problem:</strong> " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in each of the following address fields for the cache?  1) byte 2) Index 3) Tag?"</p>
  
  <p>First I defined the terms in this problem and used the other Stack Overflow Direct Mapped Cache question and my other question on <a href="https://stackoverflow.com/questions/30552938/how-many-words-can-be-in-the-address-space">Caching</a> as references(Please correct me if any of my definitions are wrong)<BR /></p>
  
  <ul> 
       <li>64 bit words - processor can process 64 bits at a time</li>
       <li>64 bit addresses w byte level addressing - there are 2^64 memory locations in RAM and each memory location stores a byte. 
       <li><a href="http://homepage.cs.uiowa.edu/~ghosh/4-1-10.pdf" rel="nofollow noreferrer">Cache</a> is high speed and is partitioned into cache lines </li>
       <li><a href="http://homepage.cs.uiowa.edu/~ghosh/4-1-10.pdf" rel="nofollow noreferrer">Directly Mapped Cache</a> is where a RAM memory block is mapped into one cache line(not sure of the significance of this </li>
  </ul>
  
  <p>Now working off <a href="https://stackoverflow.com/questions/15937002/how-does-direct-mapped-cache-work">Direct Mapped Cache</a> as a reference<Br /></p>
  
  <ol>
        <li>Byte - Because a byte line is made up of 64 bytes, you need 6 bits to indentify a single byte within that byte line</li>
        <li>Index- Because there are 8192 "rows" of byte lines, you need at least 10 bits to identify every row</li>
  </ol> 
  
  <p>Now heres the part of where I am stuck. The other <a href="https://stackoverflow.com/questions/15937002/how-does-direct-mapped-cache-work"> post</a> said "All the other bits are TAG bits." while this lecture <a href="http://homepage.cs.uiowa.edu/~ghosh/4-1-10.pdf" rel="nofollow noreferrer">post</a> said "Each line has a tag that indicates the address in M from which the line has been copied". I am guessing that M means the RAM.</p>
  
  <p>So here, all the other bits would be 64 - 6 - 10 = 48 bits. But wouldn't you need all 64 bits in the TAG to indicate what memory location in the RAM the data in the cache came from? Can someone clarify the confusion I have here?</p>