title: Shifting through concatenation in SystemVerilog?
body: <p>I have the following question</p>
  
  <p>Implement a circuit which shifts a 32-bit vector by two to the left and fills empty spots with zeros. Use only concatenation operator.</p>
  
  <p>I'm just learning SystemVerilog, and I can't understand how I can use a concatenation operator for this. I would have just done 'assign y = a &lt;&lt; 2' without concatenation ( with a declared as 32bit vector and y a 32 bit output), but I don't understand how can concatenation have anything to do with it. </p>