title: VHDL error Error (10822): couldn't implement registers for assignm
body: <p>I try to implement a JK flip flop with asynchronous Preset and Clear, with positive edge logic on clock.</p>
  <p>I receive the following error from Altera Quartus II:</p>
  <blockquote>
  <p>Error (10822): HDL error at JK_FF_PE_D1.vhd(52): couldn't implement registers for assignments on this clock edge</p>
  <p>Error: Can't elaborate top-level user hierarchy</p>
  </blockquote>
  <p>I don't see the error... I would be really grateful for a tip or a piece of advice.</p>
  <p>Thank you in advance!</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity JK_FF_PE_D1 is
    port(
      J, K        : in    std_logic;  -- J, K inputs of flip flop
      PS          : in    std_logic;  -- Preset of flip flop
      CLR         : in    std_logic;  -- CLR of flip flop
      CLK         : in    std_logic;  -- Clock 
      Q, Qcompl   : out   std_logic  -- Q and its complementary output
      );
  end entity JK_FF_PE_D1;
  
  architecture simple of JK_FF_PE_D1 is
    signal temp_Q, temp_Qcompl : std_logic;
  
  begin
  
    p0:process(PS, CLR, CLK) is
    begin
       case std_logic_vector'(PS, CLR) is
            when &quot;00&quot; =&gt;
              temp_Q &lt;= '1';
              temp_Qcompl &lt;= '1';
            when &quot;01&quot; =&gt;
              temp_Q &lt;= '1';
              temp_Qcompl &lt;= '0';
            when &quot;10&quot; =&gt;
               temp_Q &lt;= '0';
               temp_Qcompl &lt;= '1';
            when others =&gt;   -- Preset = 1 , Clear = 1
               if rising_edge (CLK) then  -- Clock turns from 0 -&gt; 1
                 case std_logic_vector'(J, K) is
                      when &quot;11&quot; =&gt;
                        temp_Q &lt;= not temp_Q;
                        temp_Qcompl &lt;= not temp_Qcompl;
                      when &quot;10&quot; =&gt;
                        temp_Q &lt;= '1';
                        temp_Qcompl &lt;= '0';
                      when &quot;01&quot; =&gt;
                        temp_Q &lt;= '0';
                        temp_Qcompl &lt;= '1';
                      when others =&gt;
                        null;
                 end case;
               end if;
       end case;
    end process p0;
    Q &lt;= temp_Q;
    Qcompl &lt;= not temp_Qcompl;
  
  end architecture simple;
  </code></pre>