title: Passing array as argument to a module in SystemVerilog Xilinx
body: <p>I have declared the following systemverilog module:</p>
  
  <pre><code>module module_top
      (
          input  logic                              clk,
          input  logic                              rst,
          input  logic signed [7  : 0 ] x_in,
          input  logic signed [5  : 0 ] y_in [24:0]
      );
      module_1 module_1_inst_1( .clk(clk), .rst(rst), .x_in(x_in), .y_in(y_in[4 : 0 ]));
      module_1 module_1_inst_2( .clk(clk), .rst(rst), .x_in(x_in), .y_in(y_in[9 : 5 ]));
      module_1 module_1_inst_3( .clk(clk), .rst(rst), .x_in(x_in), .y_in(y_in[14: 10]));
      module_1 module_1_inst_4( .clk(clk), .rst(rst), .x_in(x_in), .y_in(y_in[19: 15]));
      module_1 module_1_inst_5( .clk(clk), .rst(rst), .x_in(x_in), .y_in(y_in[24: 20]));
  endmodule
  
  module module_1
      (
          input  logic                              clk,
          input  logic                              rst,
          input  logic signed [7 : 0 ] x_in,
          input  logic signed [5 : 0 ] y_in [4:0]
      );
  always_ff @(posedge clk) begin
      $display("INFO: ", $sformatf("y_in=%p", y_in));
  end
  
  endmodule
  </code></pre>
  
  <p>I am using Vivado 2018.2 to run a functional test on this module. I pass the following array in my testbench to module_top:</p>
  
  <pre><code>    y_in =  {
                  6'b001111, 6'b001111, 6'b001111, 6'b001111, 6'b001111,
                  6'b001111, 6'b001111, 6'b001111, 6'b001111, 6'b001111,
                  6'b001111, 6'b001111, 6'b001111, 6'b001111, 6'b001111,
                  6'b001111, 6'b001111, 6'b001111, 6'b001111, 6'b000000,
                  6'b001111, 6'b001111, 6'b001111, 6'b001111, 6'b001111
              };
  </code></pre>
  
  <p>When I look in wavforms, all the instantiation of module_1 are getting the correct y_in slice excpet module_1_inst_2. Supersingly to me, I am getting Z for y_in in module_1_inst_2. For instance if I run simulation, since I am printing y_in values every pos edge of clock, I am getting the following:</p>
  
  <pre><code>INFO: y_in='{15,15,15,15,15}
  INFO: y_in='{6'bzzzzzz,6'bzzzzzz,6'bzzzzzz,6'bzzzzzz,0}
  INFO: y_in='{15,15,15,15,15}
  INFO: y_in='{15,15,15,15,15}
  INFO: y_in='{15,15,15,15,15}
  </code></pre>
  
  <p>However, if I move this print one level up the hierarchy (module_top), y_in has all the values correctly. I got the same observation when I checked the waveform. </p>
  
  <p>On the otherhand, if I change the y_in width from 6 to 7 bits it works! So I am guessing Xilinx does not properly support passign arrays to modules? or am I doing something wrong?</p>