title: Virtually indexed physically tagged cache Multi-level page tables - hierarchical paging
body: <p>A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table
  organization. The page table base register stores the base address of the first-level table (T1), which
  occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2).
  Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page
  table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set
  associative virtually indexed physically tagged cache. The cache block size is 64 bytes.</p>
  
  <p>Q.What is the size of a page in KB in this computer?</p>
  
  <p>(A) 2 (B) 4 (C) 8 (D) 16</p>
  
  <p>Q.What is the minimum number of page colours needed to guarantee that no two synonyms map to
  different sets in the processor cache of this computer?</p>
  
  <p>(A) 2 (B) 4 (C) 8 (D) 16</p>
  
  <p>A question from last Gate exam . how do I solve this kind of question?</p>