title: VHDL directly comparing vectors
body: <p>I was wondering if its possible to directly compare 2 vectors with eachother instead of just looking at them bit by bit.</p>
  
  <p>For example:</p>
  
  <pre><code>entity Comparator is
  port(a,b in: std_logic_vector (2 downto 0);
       out1, out2 out: std_logic);
  end Comparator;
  
  architecture behavioural of Comparator1 is
  begin
      if a = b then
          out1 &lt;= '1'
      else if /= then
          out2 &lt;= '1'
      end if;
  end behaviour;
  </code></pre>
  
  <p>Is this possible? </p>