title: Verilog array of different sized vectors
body: <p>I have a problem that requires converging wires down in stages, where each stage has half as many inputs and outputs as the previous one (think similar to staged selectors). I don't want to have unconnected wires in my module.</p>
  
  <p>Can I declare an array of size numStages of vectors, and then define the size of each vector in a generate loop? For example:</p>
  
  <pre><code>module Log2Alg(x, a, b);
      parameter N = 1;
      localparam numStages = $clog2(N);
      output x;
      input [N-1:0] a, b;
      wire [???] stageInputs [0:numStages-1];
      wire [???] stageOutputs [0:numStages-1];
  
      genvar i, j;
      generate
          for(i = 0; i &lt; numStages; i = i + 1)
          begin: generateStage
              stageInputs[i] = [2**(N-i):0]; // ???
              stageOutputs[i+1] = [2**(N-i-1)-1:0] // ???
  
              // Do stuff. Loop over j = i**2-1:0
          end
      endgenerate
  
  endmodule
  </code></pre>
  
  <p>Is there another approach I should be considering, or a way to accomplish what I am attempting? </p>