title: Is there something like __LINE__ in Verilog?
body: <p>I am new to Verilog but have been a C programmer for years which makes me dangerous.</p>
  
  <p>I'm doing some Verilog for a class. I'd like to use C assert() style testing in my simulation code. <a href="https://en.wikipedia.org/wiki/Assert.h" rel="noreferrer">https://en.wikipedia.org/wiki/Assert.h</a></p>
  
  <p>We aren't using System Verilog so there is no standard assert that I could find. I have cobbled together the following macro.</p>
  
  <pre><code>`define ASSERT_EQUALS(x,y) \
      repeat(1)\
      begin\
          if( (x) != (y) ) \
          begin\
              $write( "assert failed %d != %d\n", (x), (y) );\
              $finish;\
          end\
      end 
  
      // test the assert( should fail)
      `ASSERT_EQUALS(t_data_in,16'hfffe)
  </code></pre>
  
  <p>As far as I can tell there is no way to get a line number. So if the assertion fails, I only get a message with no way to link back to the location of the failure.</p>
  
  <pre><code>assert failed 65535 != 65534
  </code></pre>
  
  <p>Is there a way to get the current line number? Or is there a better way to do an assertion test in Verilog?  </p>
  
  <p>Thanks!</p>