title: Multiplication in VHDL
body: <p>My problem is I do not know if the entity adder is right or wrong.<br>
  My other question is where I have to put the entity adder, in the same module that the entity mult? Or should I create another module?</p>
  
  <p>heres is my code: Is a multiplication code of two 5bits number in
  VHDL.
      I don´t know here is the problem: library, site of the declaration of signals or variables, ..?</p>
  
  <pre><code>`library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL; 
  use IEEE.NUMERIC_STD.ALL;
  use UNISIM.VComponents.all;
  
  entity mult is
     port (op1    : in  std_logic_vector(4 downto 0);--a
       op2    : in  std_logic_vector(4 downto 0);--x
       out : out std_logic_vector(9 downto 0)); --pp
  end mult;
  
  architecture Behavioral of mult is
  type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
  signal c, sum, mul : t_matrix ;
  signal sum_ini : std_logic_vector(9 downto 0) ;
  
  
  
  begin
     rows  :  for i in 0 to 3 generate
         columns  : for j in 0 to 9 generate
             i_u : adder port map(a =&gt; sum_ini(j),
                                b =&gt;c(i,j),
                                cin =&gt; mul(i, j),
                                sum =&gt; sum(i+1, j),
                                cout =&gt; c(i+1, j+1));
          end generate columns;
      end generate rows;
  
     p_multiplications : process (a, b)
     --variable v_producto : t_pp := ((others =&gt; (others =&gt; ’0’)));
     begin -- process multiplications
     for i in 0 to 4 loop
        for j in 0 to 4 loop
            if i = 0 then
              sum_ini(j) &lt;= a(0) and b(j);
           else
              mul(i-1, j+i) &lt;= a(i) and b(j);
           end if;
        end loop; -- j
     end loop; -- i
     end process p_multiplications;
  
  end Behavioral;´
  </code></pre>
  
  <blockquote>
    <hr>
  
  <pre><code>--I have another module my entity adder , but I don´t know where is the problem.
  </code></pre>
  </blockquote>
  
  <pre><code>`entity adder is
  port (  a   : in  std_logic_vector (9 downto 0));
  end adder; 
  
  architecture Behavioral of adder is 
  type t_matrix is array (0 to 5, 10 downto 0) of std_logic;
  signal cout, b, cin, sum  :   t_matrix  ;
  begin 
  sum &lt;= (a xor cin) xor b; 
  cout &lt;= (a and b)or(cin and a)or(cin and b); 
  end Behavioral;´
  </code></pre>