title: VHDL - Designing a simple first order IIR filter
body: <p>I'm designing a simple first order IIR filter for my Spartan-6 but I'm struggling with bus widths and coefficient quantization.</p>
  
  <p>The input data is 16-bits wide comes from integrated ADCs and the quantization noise is the main noise contribution to the front end noise.</p>
  
  <p>The input signal is filtered at roughly 300kHz and I want to implement a first order IIR filter at tunable frequencies of 1Hz, 10Hz, 100Hz, 1kHz, 10kHz: let's focus on the 1Hz filtering. In theory I should be able to gain N = log2(300k) = 18 bits of resolution.</p>
  
  <p>I've computed the filter coefficients:</p>
  
  <p>Gain: 3.1416e-6 </p>
  
  <p>Numerator: [1 1]</p>
  
  <p>Denominator: [1 -0.999993717]</p>
  
  <p>How do I deal with fractional coefficients? I was thinking to multiply the coefficients times 2^N and then cut N LSBs, choosing N to have a reasonable approximation of the coefficients.</p>
  
  <p>Let's say I use this structure:
  <img src="https://i.stack.imgur.com/Pydos.gif" alt="First order IIR filter"></p>
  
  <p>What should be the bus width of <strong>z-1 register and the y output</strong> using this multiplication method?</p>
  
  <hr>
  
  <p>Thanks to Jonathan for the help, I still need to understand some things so let's make this practical: first of all, which structure do you think is the best one for FPGA implementation?</p>
  
  <p><img src="https://i.stack.imgur.com/lVKxQ.jpg" alt="Possible structures"></p>
  
  <p>In any case let's say I multiply:</p>
  
  <pre><code>b = 3.1416e-6 * 2^36   --&gt; 110100101101001111
  a = 0.999993716 * 2^17 --&gt; 011111111111111111
  </code></pre>
  
  <p>Now what? :D</p>