title: Simple CPU design in Verilog
body: <p>I am trying to use a wire variable which will hold the output of some other module and provide it as an input to the another module. While trying to change its value initially from the test bench, it's showing an error as described below. Here <strong><em>tb.v</em></strong> is the name of the test bench file.</p>
  
  <blockquote>
    <p>tb.v:39: error: a is not a valid l-value in TB.<br/>
     tb.v:4: error: a is declared here as wire. 1 error(s) during elaboration.</p>
  </blockquote>
  
  <p>Can anybody tell me what I am doing wrong?</p>