title: Using a generate with for loop in verilog
body: <p>I'm trying to understand why we use generate in verilog along with a for loop.</p>
  
  <p>Using a generate and for loop together:</p>
  
  <pre><code>reg [3:0] temp;
  genvar i;
  generate
  for (i = 0; i &lt; 3 ; i = i + 1) begin: 
      always @(posedge sysclk) begin
          temp[i] &lt;= 1'b0;
      end
  end
  endgenerate
  </code></pre>
  
  <p>Using only for loop:</p>
  
  <pre><code>reg [3:0] temp;
  genvar i;
  always @(posedge sysclk) begin
    for (i = 0; i &lt; 3 ; i = i + 1) begin: 
      temp[i] &lt;= 1'b0;
      end
  end
  </code></pre>
  
  <p>I'm considering the two snippets would basically produce the same result i.e. temp[0] to temp[10] equal to value 0. What is the difference/advantage we see by using a generate statement in this case ?</p>