title: Unable to Implement Simple ALU
body: <p>I have a basic 8-bit ALU described in Verilog. I am trying to implement the design, but I am getting error messages:</p>
  
  <p>ERROR:NgdBuild:809 - output pad net 'quotient&lt;1>' has an illegal load:
  pin I3 on block Mmux_opcode[2]_GND_1_o_wide_mux_8_OUT81 with type LUT6</p>
  
  <p>The design does the following operation, addition, subtraction, multiplication, division, AND, OR, XOR, and XNOR. The interesting thing about it is the fact that Xilinx XST cannot synthesis a divider unless the dividend is being divided by a factor of 2 (basically shifting right). So to take care of this I used a CORE IP component generated by Xilinx Core Generator. It takes in a single clock (no clock enable or synchronous clear, and outputs the correct quotient and remainder after about 20 or so clock cycles. The core itself can be found under math functions in the Core Generator program. Anyway, here's my code:</p>
  
  <pre><code>`timescale 1ns / 1ps
  module ALU8(A,B,opcode,clk,OUT);
  
  // I/O
  // We have two 16-bit inputs
  input [7:0] A,B;
  // The opcode determines our next operation
  input [2:0] opcode;
  // The processor clock
  input clk;
  // A 32-bit output
  output [15:0] OUT;
  
  // The inputs are wires
  wire [7:0] A,B;
  wire [2:0] opcode;
  
  // The output is a register
  reg [15:0] OUT;
  
  // The quotient and remainder for tyhe divider
  wire [7:0] quotient,remainder;
  // Declare an internal dividing unit
  Divider8 divider(.rfd(), .clk(clk), .dividend(A), .quotient(quotient), .divisor(B), .fractional(remainder));
  
  // Define operation codes, there's only 9 so far
  parameter   ADD = 3'b000;
  parameter   SUB = 3'b001;
  parameter   MUL = 3'b010;
  parameter   DIV = 3'b011;
  parameter   AND = 3'b100;
  parameter   OR  = 3'b101;
  parameter   XOR = 3'b110;
  parameter   XNOR    = 3'b111;
  
  // On the rising-edge of the clock
  always @(posedge clk)
  begin
      // The output is determined by the operation
      // Think of it as a MUX
      // A MUX8 will be added in later
      case(opcode)
          ADD: OUT &lt;= A + B;
          SUB: OUT &lt;= A - B;
          MUL: OUT &lt;= A * B;
          DIV: OUT &lt;= {quotient,remainder};
          AND: OUT &lt;= A &amp; B;
          OR:  OUT &lt;= A | B;
          XOR: OUT &lt;= A ^ B;
          XNOR: OUT &lt;= A ~^ B;
          default: OUT &lt;= 16'b0000000000000000;
      endcase
  end
  endmodule
  </code></pre>
  
  <p>Obviously my code terrible and my comments are probably erroneous, but I am just a beginner with Verilog. However, I do plan on improving this code greatly and adding more operations for me to practice. The module itself does successfully synthesis and simulate correctly, but I am unable to implement it on any FPGA. Anyone know if there is a problem with the code, or Xilinx ISE (which is full of bugs as usual), or maybe the project settings?</p>
  
  <p>EDIT: I've made a few changes to the code, to reflect the advice provided by the answers.</p>