title: Mealy and Moore implementations in verilog
body: <p>Can any one tell what are the differences between these implementations in verilog/VHDl? I mean how  does Mealy and Moore Synthesize into circuits in detail ? Any links would prove useful too.
  I am quite familiar to this
  <img src="https://i.stack.imgur.com/wFPwj.png" alt="enter image description here"></p>
  
  <p>Thank you</p>
  
  <p>But is this the way it implements ??</p>