title: How to use "Chains of Implicit Rules" for Makefiles
body: <p>GNU Make supports ``chains of implicit rules". What I want to achieve is to write in a single section of a Makefile to achieve this:</p>
  
  <ol>
  <li>generate A into B with command, as: cmd1 A B</li>
  <li>generate B into C with command, as: cmd2 B C</li>
  <li>generate C into D with command, as: cmd3 C D</li>
  </ol>
  
  <p>With A, B, C and D are four files with different extensions (denote .p, .q, .r and .t, for example). B and C are intermediate files which I do not need, while A is the source file and D is the output. The problem is that A is actually a very large set of files. So I want to use chain of implicit rules of Makefile to achieve this. But I don't know how to know the file names for intermediate files B and C, as in:</p>
  
  <pre><code>%.t : %.r : %.q : %.r
          cmd1 $&lt; ?
          cmd2 ? ??
          cmd3 ?? $@
  </code></pre>
  
  <p>where ? and ?? are names for intermediate files. I haven't found very specific explanation on how to name these files. The GNU make manual page only provides variable representations such as $&lt; and $@ which are not of immediate use for me. Thanks a lot.</p>