title: Verilog - Nested generate for loop with multiple genvars, not possible?
body: <p>I'm trying to add a second level of nesting to my generate loop in the following code, but iverilog is throwing an error that the register <code>j</code> is unknown:</p>
  
  <p><code>../crc.v:119: register ``j'' unknown in crc_tb.U_crc.loop[31].</code></p>
  
  <p>So is it possible to use multiple genvars in verilog? It looks like <code>j</code> is being interpreted as a register.</p>
  
  <p>Code snippet:</p>
  
  <pre><code>genvar i;
  genvar j;
  
  reg [DATA_WIDTH-1:0] temp;
  
  generate
  for(i = 0; i &lt; CRC_WIDTH; i= i + 1)
  begin : loop
      always @(posedge clock or posedge reset)
      begin
           if (reset)
           begin
               crc_out[i+:1] = SEED[i+:1];
           end
           else if (init)
           begin
              crc_out[i+:1] = SEED[i+:1];
           end
           else if (data_enable)
           begin
              if (DEBUG)
                   $display("\n\nCRC OUT[%0d]\n***************************************************************************", i); 
              if (REVERSE)
              begin
                  for (j = DATA_WIDTH-1; j &gt;= 0; j = j - 1)
                  begin : reverse_loop
                      temp[DATA_WIDTH-1-j]  = data[i][j];
                  end
                  crc_out[i+:1] &lt;= prev(DATA_WIDTH-1,i,temp,crc_out);                
              end
              else
              begin
                  crc_out[i+:1] &lt;= prev(DATA_WIDTH-1,i,data,crc_out);
              end
           end
       end
  end
  endgenerate
  </code></pre>