title: Type conversion in VHDL: real to integer - Is the rounding mode specified?
body: <p>While debugging the handling of user defined physical types in Vivado (<a href="https://stackoverflow.com/questions/27792449/can-vivado-handle-user-defined-physical-types">read more</a>), I found a different behavior for type conversions from real to integer.</p>
  
  <p>Here is my example code:</p>
  
  <pre><code>library IEEE;
  use     IEEE.STD_LOGIC_1164.ALL;
  --use     IEEE.MATH_REAL.all;
  
  entity Top_PhysicalTest_Simple is
    port (
      Clock : in STD_LOGIC;
      Input : in STD_LOGIC;
      Output : out STD_LOGIC
    );
  end;
  
  architecture top of Top_PhysicalTest_Simple is
    constant int_1     : INTEGER  := natural(0.5);
    constant int_2     : INTEGER  := integer(-0.5);
  --  constant int_2     : INTEGER  := natural(-0.5);
  begin
    assert FALSE report "16 - int_1 (natural(0.5)):  " &amp; INTEGER'image(int_1) severity note;
    assert FALSE report "17 - int_2 (natural(-0.5)): " &amp; INTEGER'image(int_2) severity note;
  
    Output &lt;= Input when rising_edge(Clock);
  end;
  </code></pre>
  
  <p><em>The dummy flip flop is used to prevent some tools from complaining about an empty design.</em></p>
  
  <p><strong>XST 14.7:</strong></p>
  
  <pre><code>Elaborating entity &lt;Top_PhysicalTest_Simple&gt; (architecture &lt;top&gt;) from library &lt;work&gt;.
  Note: "16 - int_1 (natural(0.5)):  1"
  Note: "17 - int_2 (natural(-0.5)): 0"
  </code></pre>
  
  <p>XST seems to use the mode <em>round up</em> and it handles the type conversion inclusive range check.
  So I must use <code>integer(-0.5)</code> instead of <code>natural(-0.5)</code>.</p>
  
  <p><strong>Vivado 2014.4:</strong></p>
  
  <pre><code>[Synth 8-63] RTL assertion: "16 - int_1 (natural(0.5)):  1" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest_Simple.vhdl":80]
  [Synth 8-63] RTL assertion: "17 - int_2 (natural(-0.5)): -1" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest_Simple.vhdl":81]
  </code></pre>
  
  <p>Synth seems to use the mode <em>round to infinity</em> and it handles the type conversion without range check. So maybe <code>natural(..)</code> is just an alias to <code>integer(..)</code>.<br>
  The commented line: <code>constant int_2 : INTEGER := natural(-0.5);</code> throws no error.</p>
  
  <p><strong>GHDL 0.29:</strong></p>
  
  <p>GHDL 0.29 does no range check in <code>natural(..)</code>.
  I know it's out dated, but since 0.31 hates me I can't tell if this is already fixed.</p>
  
  <p><strong>GHDL 0.31:</strong></p>
  
  <p>I'll present the results later. GHDL refuses to analyse my code because:<br>
  <em>Top_PhysicalTest_Simple.vhdl:29:14: file std_logic_1164.v93 has changed and must be reanalysed</em></p>
  
  <p>My questions:</p>
  
  <ul>
  <li>Does VHDL define a rounding mode? And if so which one?</li>
  <li>How should I handle rounding if no mode is defined?</li>
  </ul>