title: Accessing Makefile variable in compile time shell
body: <p>I have a makefile, 1.mk with following content:</p>
  <pre><code>#!make
  
  aa := x
  bb := y
  cc := z
  
  export
  include abc.mk
  
  all:
      @echo $(chk1)
  </code></pre>
  <p>And another makefile, abc.mk with following content:</p>
  <pre><code>#!make
  
  chk1 := $(shell set -o posix; set | awk -F &quot;=&quot; 'BEGIN{ORS=&quot; &quot;}1 $$1~/[a-zA-Z_][a-zA-Z0-9_]*/ {print $$1}')
  chk2 := $(shell env &amp;&gt; pqr)
  
  export
  </code></pre>
  <p>When I check, none has the makefile-variables:</p>
  <pre><code>&gt; make all -f 1.mk | grep aa
  
  &gt; grep 'aa' pqr
  
  </code></pre>
  <p>Thus I can say, compile time shell does not have makefile variables. I want a way to access all makefile variables in compile-time shell.</p>
  <p>Constraint: I do not know variable names beforehand to write code in following manner:</p>
  <pre><code>chk2 := $(shell export aa=$(aa); env &amp;&gt; pqr)
  </code></pre>