title: SystemVerilog: Passing interfaces to functions/tasks (for synthesis!)
body: <p>Is there any synthesizable way to pass an interface to a function or a task? My use case is the following: I have a package with several functions (though I could convert them to tasks, if that helps :) ), all of which might be used in a module and might need to access the ports of the module. Now, usually I'd just group all ports in an <code>interface</code>, add it to the module, and pass the it as <code>virtual</code> to the function. However, the manual of my synthesis tool mentions that <code>virtual</code> is not supported.</p>
  
  <p>Am I missing anything? There must be a way to provide ports to tasks for synthesis, similar to VHDL's <code>signal</code> arguments?</p>
  
  <p>Some example code:</p>
  
  <pre><code>module mymod (
      input logic clk,
      input logic rst,
      input uint16_t adr,
      input bit cyc,
      input uint32_t dat_m,
      input bit stb,
      input bit we,
      output bit ack,
      output uint32_t dat_s
      );
  
      always_comb begin
          mypack::do_something(a, b, c, adr, cyc, dat_m, stb, we, ack, dat_s);
  endmodule
  </code></pre>
  
  <p>Ideally, the task <code>mypack::do_something</code> would be able to use the ports as ports, i.e. wait for changes on them, write values to them, etc; basically, the same you'd achieve in VHDL by passing them as <code>signal</code> arguments (as opposed to <code>variable</code> or <code>constant</code> arguments).</p>