title: systemverilog packages, macros and scope
body: <p>Im having trouble accessing a package and macro from another library in systenverilog. My undestanding is that a package or macro should be visible within a compilation unit and therefore visible from any library in that unit but that doesn't seem to be the case in this example</p>
  
  <blockquote>
    <p>defines.sv</p>
  </blockquote>
  
  <pre><code>`define POUTMAX
  </code></pre>
  
  <blockquote>
    <p>mtp_pkg.sv</p>
  </blockquote>
  
  <pre><code>package mtp;
  function automatic void set_mtp(string name, int val);
    $display("set_mtp");
  endfunction
  endpackage
  </code></pre>
  
  <blockquote>
    <p>tb.sv</p>
  </blockquote>
  
  <pre><code>module tb;
    initial begin
      mtp::set_mtp("l",7);
  //    $display(`POUTMAX);
    end
  endmodule
  </code></pre>
  
  <p>If I compile the testbench into its own library the mtp_pkg or macro are not accessible. e.g.</p>
  
  <blockquote>
    <p>xrun mtp_pkg.sv defines.sv -makelib tb_lib tb.sv -endlib -top tb</p>
  </blockquote>
  
  <pre><code>file: tb.sv
       mtp::set_mtp("l",7);
         | xmvlog: *E,NOPBIND (tb.sv,6|8): Package mtp could not be bound.
         module tb_lib.tb:sv
                 errors: 1, warnings: 0 xrun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code
  *E and fix those identified problems to proceed. Exiting with code (status 1).
  </code></pre>
  
  <p>What am I missing here? it seems mtp_pkg is not compiled before tb.sv.
  Adding include and or import mtp::* into tb.sv does not fix the problem I then get an error that mtp package exists in 2 places and a binding error. </p>
  
  <p>It works ok if I remove the tb_lib. </p>