title: MIPS critical path of a branch instruction
body: <p>Suppose I have a MIPS processor performing a <code>beq</code> instruction e.g. <code>beq $t1, $t2, label</code></p>
  
  <p><a href="https://i.stack.imgur.com/odCHi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/odCHi.png" alt=""></a></p>
  
  <p>I'm trying to figure out the critical path of this instruction. Suppose every component has the same delay. My idea for the critical path is as follows:</p>
  
  <pre><code>Path 1: Add -&gt; ............ -&gt; Add -&gt; Mux
  
  Path 2: IM -&gt; Control -&gt; Mux -&gt; ALU -&gt; Mux
  
  Path 3: IM -&gt; Registers -&gt; Mux -&gt; ALU -&gt; Mux
  </code></pre>
  
  <p>How do I go about filling in the rest of Path 1 (or other paths if they're wrong) considering it has to wait for some signals to be ready? </p>
  
  <p>Also is there any reason why path 3 would not be the critical path if we assume the delay of all components is the same (and ignore the gate delays)?</p>