title: How to Sign Extend a 4bit vector to 16bit vector in VHDL?
body: <p>I'm new to VHDL and I'm wondering how to use sign extension on a 4bit number to extend it to a 16bit number. I understand the idea of sign extension and how it works, but I'm having a hard time trying to find a way to implement it in my VHDL assignment. I have a small start but am wondering where to go from here.</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  
  Entity Signextend is
      port(
          numIn       :   in  std_logic_vector( 3 downto 0);
          numOut      :   out std_logic_vector(15 downto 0)
          );
  End Signextend;
  
  architecture signex of Signextend is
  
  begin
  
      numOut(3)   &lt;=  numIn(3);
      numOut(2)   &lt;=  numIn(2);
      numOut(1)   &lt;=  numIn(1);
      numOut(0)   &lt;=  numIn(0);
  --Trying to add the rest of the vectors, not sure how to proceed.
  
  end signex;
  </code></pre>
  <p>This might not even be the correct start, but could someone point me in the right direction? Or show me how to pad the number with 0s or 1s depending on the sign of the number? Thanks for the help!</p>