title: Vivado: post-synthesis simulation fails to start, although behavioral runs
body: <p>I have a module in Xilinx Vivado that fails to run post-synthesis simulation with followinf errors:</p>
  
  <pre><code>Starting static elaboration
  
  ERROR: [VRFC 10-380] binding entity insertion_sort does not have generic array_length 
  ERROR: [VRFC 10-718] formal port &lt;sort_in&gt; does not exist in entity &lt;insertion_sort&gt;.  Please compare the definition of block &lt;insertion_sort&gt; to its component declaration and its instantion to detect the mismatch. 
  ERROR: [VRFC 10-718] formal port &lt;sorted_out&gt; does not exist in entity &lt;insertion_sort&gt;.  Please compare the definition of block &lt;insertion_sort&gt; to its component declaration and its instantion to detect the mismatch. 
  ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit sort_tb in library work failed.
  </code></pre>
  
  <p>But behavioral simulation and the synthesis itself run normally. </p>
  
  <pre><code>INFO: [Common 17-83] Releasing license: Synthesis
  21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  synth_design completed successfully
  </code></pre>
  
  <p>here is the description of the module</p>
  
  <pre><code>entity insertion_sort is
      generic(
          array_length:integer:=9
      );
      Port (
          clk: in std_logic;
          reset: in std_logic;
          start_sorting: in std_logic;
          sort_in: in array_of_ints (0 to array_length-1);
          sorted_out: out array_of_ints(0 to array_length-1);
          sort_ready: out std_logic
      );
  
  end insertion_sort;
  </code></pre>
  
  <p>array_of_ints is defined in the package as</p>
  
  <pre><code>package array_def is
      type array_of_ints is array (natural range&lt;&gt;) of integer range -200 to 200 ;
  
  end package;
  </code></pre>
  
  <p>instantiation of the module in the test bench</p>
  
  <pre><code>entity sort_tb is
      generic(
       tb_length: integer:=9
      );
      --Port ( );
  end;
  
  architecture test_sorting of sort_tb is
  
      constant clock_cycle: time:=20 ns;
      signal start, ready, tclk, rst: std_logic;
      signal test_array_in, test_array_out: array_of_ints(0 to tb_length-1);
      signal  run_num: positive:=1;
      component insertion_sort
          generic ( array_length: integer);
          port(
              clk: in std_logic;
              reset: in std_logic;
              start_sorting: in std_logic;
              sort_in: in array_of_ints (0 to array_length-1);
              sorted_out: out array_of_ints(0 to array_length-1);
          sort_ready: out std_logic);
  
      end component;
  
      begin
      DUT: insertion_sort 
      generic map( array_length=&gt;tb_length)
      port map (clk=&gt;tclk,
          reset=&gt;rst,
          start_sorting=&gt;start,
          sort_in=&gt;test_array_in,
          sorted_out=&gt;test_array_out,
      sort_ready=&gt;ready  );
  </code></pre>
  
  <p>Hope i provided enough information. Thank you in advance for your help</p>
  
  <p><strong>EDIT:</strong> entity description from new file created by vivado as requested by Paebbels.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  library UNISIM;
  use UNISIM.VCOMPONENTS.ALL;
  entity insertion_sort is
    port (
      clk : in STD_LOGIC;
      reset : in STD_LOGIC;
      start_sorting : in STD_LOGIC;
      \sort_in[0]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[1]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[2]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[3]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[4]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[5]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[7]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sort_in[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[1]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[2]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[3]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[4]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[5]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[6]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[7]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      \sorted_out[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
      sort_ready : out STD_LOGIC
    );
    attribute NotValidForBitStream : boolean;
    attribute NotValidForBitStream of insertion_sort : entity is true;
    attribute array_length : integer;
    attribute array_length of insertion_sort : entity is 9;
  end insertion_sort;
  </code></pre>