title: randomization in SystemVerilog
body: <p>I am trying to randomize an address which should be not fall in a previously allocated segment
  suppose if I was allocated  address 0, 10 ,40 , and the block length is 5,
  when I randomized the address , it should not fall in the range of (0-4) ,( 10-14) , (40-44).
  how can I constraint this in system verilog.
  I tried a method but it is not working.
  <br>Here is my code: </p>
  
  <pre><code>constraint con {
  
  foreach(keys[i]){
  
      !(address inside {[keys[i]:keys[i]+BLOCK_SIZE]});    
  }
  
  }
  </code></pre>
  
  <p>keys is array of address that were already alloted , generated address should not fall in the above ranges.
  thanks
  shiva</p>