title: "Not a valid l-value" Error in Verilog
body: <p>I am new to Verilog (and, to a lesser extent, programming) and am trying to create a program that finds the absolute value of a set of numbers and then calculates for a running average. The running average is 5 points wide, and goes across a data set that is about 40 numbers wide.</p>
  
  <p>I am having trouble with the running average (lines 14-17 design, 24-28 test-bench) and am receiving the errors "o2/out is not a valid l-value in tb.avg." and "o2/out is declared here as a wire". How should I fix this?</p>
  
  <p>Here is my design:</p>
  
  <pre><code>module absolute_value(i1,o1);
    input signed [11:0] i1;
    output signed [11:0] o1;
  
    assign o1 = i1[11] ? -i1 : i1;
  endmodule 
  
  module moving_average(k1,k2,k3,k3,k4,o2,out);
    input k1, k2, k3, k4, k5;
    output [11:0] o2;
    output [11:0] out;
    integer t;
  
    always begin
      assign o2 = (k1 + k2 + k3 + k4 + k5) / 5;
      assign out = o2;
    end
  endmodule
  </code></pre>
  
  <p>And here is my test-bench:</p>
  
  <pre><code>module tb;
    reg signed [11:0] i1;
    wire signed [11:0] o1;
  
    reg k1;
    reg k2;
    reg k3;
    reg k4;
    reg k5;
    wire [11:0] o2;
    wire [11:0] out;
  
    absolute_value abs(i1,o1);  
    moving_average avg(k1,k2,k3,k4,k5,o2,out);
  
    integer t;
  
    initial begin
      for (t = -10; t &lt; 30; t = t + 1) begin
        #1
        i1 &lt;= t;
        $display("i1 = %d, o1 = %d", i1, o1);
  
        assign k5 = k4 ? k4 : o1;
        assign k4 = k3 ? k3 : o1;
        assign k3 = k2 ? k2 : o1;
        assign k2 = k1 ? k1 : o1;
        assign k1 = o1;
  
        $display("out = %d", out);
  
        $moniter($time, "i1 = %d, o1 = %d, o2 = %d, out = %d k1 = %d, k2 = %d, k3 = %d, k4 = %d, k5 = %d", i1, o1, o2, out, k1, k2, k3, k4, k5);
      end
    end
  endmodule
  </code></pre>
  
  <p>I'd bet that there are other errors in my program too, so any help is much appreciated.</p>