title: <*> of the instance <gen[1].*> is unconnected or connected to loadless signal
body: <p>when I'm synthesizing the following VHDL code I get the above error(s).</p>
  
  <p>This is a toplevel design to connect multiple entities. </p>
  
  <p>The component declaration:</p>
  
  <pre><code>    COMPONENT channel_memory IS
      PORT (
          clka : IN STD_LOGIC;
          rsta : IN STD_LOGIC;
          wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0):= (OTHERS =&gt; '0');
          addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0):=  (OTHERS =&gt; '0');
          dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0):=   (OTHERS =&gt; '0');
          douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0):= (OTHERS =&gt; '0')
          );
  END COMPONENT;
  COMPONENT MAX5190 IS
      PORT (  
          GCLK                            :   IN  STD_LOGIC;                      -- CLK in 200 MHz
          RSTN                            :   IN  STD_LOGIC;                      -- Reset
          OUTPUT_TRIGGER                  :   IN  STD_LOGIC;                      -- Enable the module    (from controller)
          TRIGGER_CHIRP                   :   IN  STD_LOGIC;                      -- Start chirping       (from channel delay)
          LOAD_ACK                        :   IN  STD_LOGIC;                      -- Data ready               
          DATA_LENGTH                     :   IN  STD_LOGIC_VECTOR (11 DOWNTO 0); -- Total words to send to DAC
          DIN                             :   IN  STD_LOGIC_VECTOR (15 DOWNTO 0) :=   (OTHERS =&gt; '0');    -- Actual data to send to DAC
          CHIRP_EN_TRIGGER                :   IN  STD_LOGIC;                      -- Enable dac &gt;&gt; ××××××××××××
                                                                      --                          ×
          -- Memory block                                                                         ×
          LOAD_OUTPUT                     :   OUT STD_LOGIC;                      -- Request data             ×
          DATA_ADDR                       :   OUT STD_LOGIC_VECTOR (11 DOWNTO 0); -- Adress to read from      ×
                                                                      --                          ×
          CHIRP_EN                        :   OUT STD_LOGIC;                      -- opamp enable &lt;&lt; ××××××××××
           -- MAX5190 outputs
          DAC_EN                          :   OUT STD_LOGIC;                      -- DAC Enable (always high)
          DAC_CS                          :   OUT STD_LOGIC;                      -- DAC chip select
          DAC_CLK                         :   OUT STD_LOGIC;                      -- DAC clock out
          DAC_DATA                        :   OUT STD_LOGIC_VECTOR (7 DOWNTO 0)       :=  (OTHERS =&gt; '0') -- dac data
  );
  END COMPONENT;
  
  COMPONENT memory_controll IS
      PORT(
          CLK                             : IN  STD_LOGIC;
  
          -- from controller
          DATA_IN                         : IN  STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); -- data to store
          DATA_LENGTH                     : in  STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); -- number of words to store
          RESET                           : IN  STD_LOGIC;                        -- reset module
          NEW_DATA                        : IN  STD_LOGIC;                        -- new data available flag
          WRITE_ENABLE                    : IN  STD_LOGIC;                        -- enable writing
  
          -- from MAX5190
          ADDRESS_SELECT                  : IN  STD_LOGIC_VECTOR ( 11 DOWNTO 0 ) := (others =&gt; '0');  -- addres selected by MAX5190 driver
          REQUEST_DATA                    : IN  STD_LOGIC;                        -- request data
          DATA_OUT                        : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); -- data to MAX5190 driver
          DATA_READY                      : OUT STD_LOGIC;                        -- data to MAX5190 driver ready
  
          -- to memory
          DOUTA                           : IN  STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) := (others =&gt; '0'); -- data from memory
          DINA                            : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); -- data to memory
          ADDRA                           : OUT STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); -- addres to write or read
          WEA                             : OUT STD_LOGIC_VECTOR (  0 DOWNTO 0);  -- write enable
          RSTA                            : OUT STD_LOGIC                         -- reset memory
  
          );
  </code></pre>
  
  <p>The port mapping:</p>
  
  <pre><code>gen: for i in 1 to number_of_channels generate
      -- memory controll
  memcont: memory_controll
      PORT MAP(
          CLK                             =&gt; clk400MHz,
  
          -- from controller
          DATA_IN                         =&gt; MEMORY_CONTROL_DATA,
          DATA_LENGTH                     =&gt; MEMORY_CONTROL_DATA_LENGTH,
          RESET                           =&gt; BUTTON,
          NEW_DATA                        =&gt; MEMORY_CONTROL_NEW_DATA,
          WRITE_ENABLE                    =&gt; MEMORY_CONTROL_WRITE_ENABLE,
  
          -- from MAX5190
          ADDRESS_SELECT                  =&gt; ADDRESS_SELECT   (i),
          REQUEST_DATA                    =&gt; REQUEST_DATA     (i),
          DATA_OUT                        =&gt; DATA_OUT         (i),
          DATA_READY                      =&gt; DATA_READY       (i),
  
          -- to memory
          DOUTA                           =&gt; DOUTA    (i),
          DINA                            =&gt; DINA     (i),
          ADDRA                           =&gt; ADDRA    (i),
          WEA                             =&gt; WEA      (i),
          RSTA                            =&gt; RSTA     (i)
          );
  
      -- max5190
  max: max5190
      PORT MAP(
          GCLK                            =&gt; clk200MHz,
          RSTN                            =&gt; MAX5190_RESET,
          OUTPUT_TRIGGER                  =&gt; MAX5190_ENABLE,
          TRIGGER_CHIRP                   =&gt; TRIGGER_CHIRP            (i),
          LOAD_ACK                        =&gt; DATA_READY               (i),
          DATA_LENGTH                     =&gt; MAX5190_DATA_LENGTH,
          DIN                             =&gt; DATA_OUT                 (i),
          CHIRP_EN_TRIGGER                =&gt; MAX5190_CHIRP_ENABLE,
  
          -- Memory block         
          LOAD_OUTPUT                     =&gt; REQUEST_DATA     (i),
          DATA_ADDR                       =&gt; ADDRESS_SELECT   (i),
  
          CHIRP_EN                        =&gt; CHIRP_EN     (i),
           -- MAX5190 outputs
          DAC_EN                          =&gt; DAC_EN       (i),
          DAC_CS                          =&gt; DAC_CS       (i),
          DAC_CLK                         =&gt; CHANNEL_CLKS (i),
          DAC_DATA                        =&gt; CHANNELS     (i)
          );
      -- memory
  mem: channel_memory
      PORT MAP(
          clka                            =&gt; clk400MHz,
          rsta                            =&gt; BUTTON,
          wea                             =&gt; WEA      (i),
          addra                           =&gt; ADDRA    (i),
          dina                            =&gt; DINA     (i),
          douta                           =&gt; DOUTA    (i)
          );
  </code></pre>
  
  <p>the package where I declared my types:</p>
  
  <pre><code>PACKAGE jelle IS
  FUNCTION lookup (input: STD_LOGIC_VECTOR(15 DOWNTO 0)) RETURN INTEGER;
  FUNCTION jOR    (input: STD_LOGIC_VECTOR( 7 DOWNTO 0)) RETURN STD_LOGIC;
  TYPE VECTOR_ARRAY   is array (POSITIVE) of STD_LOGIC_VECTOR( 7 downto 0);
  TYPE ADDRESS_ARRAY  is array (POSITIVE) of STD_LOGIC_VECTOR(11 downto 0);
  TYPE DATA_ARRAY     is array (POSITIVE) of STD_LOGIC_VECTOR(15 downto 0);
  TYPE WEA_ARRAY      is array (POSITIVE) of STD_LOGIC_VECTOR( 0 downto 0);   
  </code></pre>
  
  <p>END PACKAGE;</p>
  
  <p>The previous time I synthesized the code these where warning, now they've changed to errors, but I think they're still pretty important. </p>
  
  <pre><code>INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 288: Output port &lt;CLK_OUT3&gt; of the instance &lt;dcm&gt; is unconnected or connected to loadless signal.
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 288: Output port &lt;LOCKED&gt; of the instance &lt;dcm&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 296: Output port &lt;MAX5190_CHIRP_ENABLE_TRIGGER&gt; of the instance &lt;contr&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port &lt;DATA_OUT&gt; of the instance &lt;gen[1].memcont&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port &lt;DINA&gt; of the instance &lt;gen[1].memcont&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port &lt;ADDRA&gt; of the instance &lt;gen[1].memcont&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port &lt;WEA&gt; of the instance &lt;gen[1].memcont&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port &lt;RSTA&gt; of the instance &lt;gen[1].memcont&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 391: Output port &lt;DATA_ADDR&gt; of the instance &lt;gen[1].max&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 391: Output port &lt;DAC_DATA&gt; of the instance &lt;gen[1].max&gt; is unconnected or connected to loadless signal.
  
  INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 414: Output port &lt;douta&gt; of the instance &lt;gen[1].mem&gt; is unconnected or connected to loadless signal.
  </code></pre>
  
  <p>These errors repeat themselves for every generated object.
  The input ports are given default values because the compiler kept asking for it with errors (don't know why either though).</p>
  
  <p>If anyone could help me that would be fantastic!!</p>