title: SystemVerilog: How to merge 2 arrays into one array?
body: <p>I try this code but when i compile it, i receive this error:</p>
  
  <pre><code>Illegal assignment pattern. The number of elements (2) doesn't match with the type's width (16)
  </code></pre>
  
  <p>.</p>
  
  <pre><code>module(output [15:0] O);
    reg [7:0] a, b;
    assign O = {a, b};
  endmodule
  </code></pre>
  
  <p>when i compile the code with quartus i dont receive any errors, but Modelsim gives me this error.</p>