title: error: entity cannot be at the top of a design, generic has no default value
body: <p>I've just started VHDL and its proving to be more difficult than I gave it credit for. At the moment im trying to get my head around the 'generic' area of operation. I've cut down my code as much as possible (this extract doesn't do anything but still produces the error) and still haven't managed to crack it. If one of you could help I would be very greatful!</p>
  
  <p>thanks in advance.</p>
  
  <pre><code>library IEEE;
  
  entity ALU is
      GENERIC (constant cst:integer range 15 downto 0); 
  end ALU;
  
  architecture behavioural of ALU is
      begin
  End behavioural;
  </code></pre>
  
  <p>.</p>
  
  <pre><code>error:entity "alu" cannot be at the top of a design
  alu.vhdl:6:19: generic "cst" has no default value
  </code></pre>