title: Non-constant loop condition not supported for while
body: <p>This is my verilog code for CRC correction,</p>
  
  <pre><code>module cor(m,err);
  input m;
  output  err;
  reg  [10:0]data;                    // message and zeros concatenated
  reg  [7:0]poly;                     // polynomial equivalent
  reg  [15:0]err;                     //xor output
  reg  [3:0]cnt;                      // counter
  reg  [2:0]n;                        // zeros
  wire  [7:0]m;
  reg  [7:0]poly1;                    // copy of polynomial equivalent
  reg  [15:0]f;                       //shifted polynomial
  //wire a;
  reg [2:0]a;
  
  initial a &lt;= 3'b000;
  initial cnt = 4'b1000;
  //initial data &lt;= {m,n};
  initial poly1&lt;= poly;
  
  //always_comb
  always @ (m or poly)
  begin
  data &lt;= {m,n};
  poly1 &lt;= poly;
  //data &lt;= {m,n};
  err &lt;= data[7:0]^poly1;
  while(!cnt[2:0] == 0)
  begin
  if(err == 4||5||6||7)begin
  f &lt;= poly1&gt;&gt;1;
  cnt &lt;=cnt-1;
  err &lt;= data^f;
  err &lt;= err&lt;&lt;1;
  end
  else if(err[7:4]== 2||3) begin
  f &lt;= poly1&gt;&gt;2;
  cnt &lt;= cnt-2;
  err &lt;= data^poly1;
  err = err &lt;&lt;2;
  end
  else if(err[7:4]== 1) begin
  f &lt;= poly1&gt;&gt;3;
  cnt &lt;= cnt-3;
  err &lt;= data^poly1;
  err &lt;= err &lt;&lt;3;
  end
  else if(err[7:4]== 4'b0000)begin
  f &lt;= poly1&gt;&gt;4;
  cnt &lt;= cnt-4;
  err &lt;= data^poly1;
  err &lt;=err &lt;&lt;4;
  end
  else
  err &lt;= data^poly1;
  end
  if(err[7:4]==4'b0000)                           //checking remainder? zero
  $display("no error detected");
  else 
  $display("error detected");
  err &lt;= data^poly1;                              // correcting error
  
  end
  
  endmodule
  </code></pre>
  
  <p>i am not able to synthesize xst</p>
  
  <p>the error is: <strong>Non-constant loop condition not supported for while</strong></p>
  
  <p>here i think i cant use for loop because its not a linear increment (+1) after each iteration,(i am not wrong?)</p>
  
  <p>please suggest me other approach to synthesize it !!</p>
  
  <p>Thanks in advance 
  Madhav (VLSI student)</p>