title: How do you manipulate input arrays in an always block (verilog)?
body: <p>I'm very new to verilog and i'm just starting to understand how it works.
  I want to manipulate an input to a module <code>mant[22:0]</code>, in an always block but I am not sure how to go about it.</p>
  
  <pre><code>module normalize(mant,exp,mant_norm,exp_norm);
  
      input [22:0]mant;
      input [7:0]exp;
  
      output [22:0]mant_norm;
      output [7:0]exp_norm;
  
      reg mantreg[22:0];
      reg count=0;
  
      always@(mant or exp)
      begin
  
      mantreg&lt;=mant; //this gives an error
          if(mant[22]==0)
          begin
  
            mant&lt;={mant[21:0],1'b0};//this also gives an error
            count&lt;=count+1;
  
          end 
      end
  endmodule
  </code></pre>
  
  <p>so i have to shift the <code>mant</code> register if the bit22 is zero and count the number of shifts. I am so confused about when to use reg and when to use wire and how to do the manipulation. please help let me know how to go about it. </p>