title: Issues with my Verilog Simulation -x's and z's in signals
body: <p>I have a project, in which I have to implement a list processor that computes the squared-norm of a complex vector.</p>
  
  <p>EDITED:
  My code is compiling, and the simulation is working, and I corrected all the connections, so my input signals are reading values. But I am having some trouble with the "start" signal. In the testbench I set it to 0. then to 1 but for some reason it remains 0. Anyone know why a signal would usually stay 0 even though it was assigned to a particula value in the test bench??  </p>
  
  <p>I'm still amateurish in verilog, so I'm not sure what I did wrong. I've been tracking every module used, checked if there were errors in instantiating, but I'm missing something, silly or fundamental. I just have no idea what it is.</p>
  
  <p>Here is the code: the total modules are control, memory, datapath, testbench and VNLP (aka the module that computes the squared-norm).</p>
  
  <pre><code>module control (output reg [7:0] counter, output reg add1_sel, add2_sel, before_sel, next_sel, acc_sel, A1_sel, A2_sel, load_before, load_next, load_acc, done_op, input clk, start_op);
  wire [9:0] one, zero, before, next;
  //reg [7:0] counter;
  reg [1 : 0] state, next_state; 
  parameter Start=0, Compute=1, GetNext=2, Done=3;
  reg counter_start, counter_incr;
  assign one=before;
  assign zero=next;
  
  
  
  always@(posedge clk) begin
          if (start_op) state&lt;=Start;
          else  state&lt;=next_state;
  end
  
  always@(posedge clk) begin
  if (counter_start ==1)
      counter&lt;=0;
  else if(counter_incr==1)
      counter&lt;=counter+1;
  end
  
  
  
  
  
  
  always@(state, start_op, zero, one) begin
  load_acc=0;
  next_sel=0; 
  before_sel=0; 
  A1_sel=0; 
  A2_sel=0; 
  load_next=0; 
  load_before=0; 
  done_op=0;
  acc_sel=0;
  add1_sel=0;
  add2_sel=0;
  counter_incr=0;
  counter_start=0;
  
  
  case(state)
  
  Start: 
          begin
          next_sel=0;
          before_sel=0;
          load_next=1;
          load_before=1;
          acc_sel=0;
          load_acc=1;
  counter_start=1;
  add1_sel=0;
  add2_sel=0;
          //load_M1=0;
          //load_M2=0;
          done_op=0;
          if (start_op ==0)   next_state=Compute;
          //else next_state=Start;
      end
  
  
  Compute:
      begin
          counter_start=0;
          next_sel=1;
          before_sel=1;
          load_next=0;
          load_before=0;
          A1_sel=1;
          A2_sel=1;
  add1_sel=1;
  add2_sel=1;
          //load_M1=1;
          //load_M2=1;
          load_acc=1;
          acc_sel=1;
          done_op=0;
          if (start_op ==0) next_state=GetNext;
          //else next_state=Start;
      end
  
  GetNext:
      begin
          load_next=1;
          load_before=1;
          A1_sel=0;
          A2_sel=0;
          load_acc=0; 
          done_op=0;
          if (start_op ==0) begin
              if (zero==0 || one==1) next_state= Done;
              else if (!start_op &amp;&amp; zero!=0 &amp;&amp; one!=1) begin next_state=Compute; counter_incr=1; end
          end
      end
  
  Done:
      begin
          done_op=1;
          load_acc=0; counter_incr=0;
          if (start_op ==1) next_state=Start;
          //else next_state=Done;
      end
  
  default: next_state= Start; 
  
  endcase
  
  
  end
  
  
  endmodule
  
  
  
  
  
  module memory (D1, D2, A1, A2);
  parameter word_size=10;
  parameter address_size=9;
  parameter memory_size= 512;
  reg [9:0] memory [memory_size-1:0]; 
  output reg [word_size-1:0] D1;
  output reg [word_size-1:0] D2;
  input [address_size-1:0] A1;
  input [address_size-1:0] A2;
  always@(*) begin
           D1=memory[A1];
          D2=memory[A2];
  end
  endmodule 
  
  
  module VNLP (
  output reg[27: 0] norm2, output reg[7:0] len, output reg Done, input reg done_op, output reg [8:0] A1, A2, input [7:0] counter, 
  input [9:0] D1, D2, output reg [9:0] Next, Before, output  reg [27:0] Accumulator,
   input add1_sel, add2_sel, before_sel, next_sel, acc_sel, A1_sel, A2_sel, load_before, load_next, load_acc,clk, start_op);
  
  reg [19:0] adder1, adder2;
  wire [20:0] sum_add;
  reg [27:0] acc;
  reg [9:0] before, next;
  reg [8:0] a1, a2;
  
  reg [19:0] d1, d2;
  
  //assign d1= D1*D1;
  //assign d2=D2*D2;
  
  
  assign sum_add= adder1 + adder2;
  
  
  always@(*) begin
  
  if (add2_sel) begin adder2=D2*D2; end
  else adder2=20'b0;
  
  if (add1_sel) adder1=D1*D1;
  else adder1=20'b0;
  
  
  
  if (before_sel) before=D2;
  else before=10'b0;
  
  
  if (next_sel) next=D1;
  else next=10'b0;
  
  
  if (acc_sel) acc=sum_add+ Accumulator;
  else acc=28'b0;
  
  
  if (A1_sel) A1&lt;=Next+ 2'b10;
  else A1&lt;=Next;
  
  
  if (A2_sel) A2&lt;=Before+ 2'b10;
  else A2&lt;=Before;
  
  
  if (done_op) begin 
      norm2&lt;= Accumulator;
      len=counter;
      Done=1;
      end
      else begin 
          norm2&lt;=28'b0;
          len&lt;=8'b0;
          Done&lt;=0;
          end
  end
  
  
  always@(posedge clk) begin
      if (load_before) Before&lt;= before;
  end
  
  always@(posedge clk) begin
      if (load_next) Next&lt;= next;
  end
  
  always@(posedge clk) begin
      if (load_acc) Accumulator&lt;= acc;
  end
  
  
  
  endmodule
  
  
  
  
  
  module Datapath (
  input start_op, clk,
  output Done,
  output [7:0] len,
  output [27:0] norm2);
  
  wire [8:0] A1, A2;
  wire [9:0] D1, D2;
  
  
  wire done_op;
  wire [7:0] counter;
  wire  [9:0] Next, Before;
  wire [27:0] Accumulator;
  wire add1_sel, add2_sel, before_sel, next_sel, acc_sel, A1_sel, A2_sel, load_before, load_next, load_acc;
  
  
  
  
  VNLP VNLP(norm2, len, Done, done_op, A1, A2, counter, D1, D2, Next, Before,Accumulator, 
  add1_sel, add2_sel, before_sel, next_sel, acc_sel, A1_sel, A2_sel,
   load_before, load_next, load_acc,clk, start_op);
  
  memory M1 (D1, D2, A1, A2);
  
  control control (counter,add1_sel, add2_sel, before_sel, next_sel, acc_sel, A1_sel, A2_sel, load_before, load_next, load_acc, done_op, clk, start_op);
  
  
  
  endmodule
  
  
  module Datapath_tb;
  
  
  reg start_op, clk;
  wire Done;
  wire [7:0] len;
  wire [27:0] norm2;
  reg[8:0] k;
  
  
  wire[9:0]  word0,word1,word2,word3,
  word4,word5,word6,word7,
  word8,word9,word10,word11,
  word12,word13,word14,word15, 
  word16,word17,word18,word19,
  word20, word21,word22,word23,
  word24,word25,word26,word27, 
  word28,word29,word30,word31,
  word32, word33,word34,word35,
  word36,word37,word38,word39; 
  
  
  Datapath Datapath (
  start_op, clk,
  Done,
  len,
  norm2);
  
  assign      word0 = Datapath.M1.memory[0]; 
  assign      word1 = Datapath.M1.memory[1]; 
  
  
  assign      word2 = Datapath.M1.memory[2]; 
  assign      word3 = Datapath.M1.memory[3]; 
  assign      word4 = Datapath.M1.memory[5]; 
  assign      word5 = Datapath.M1.memory[6]; 
  assign      word6 = Datapath.M1.memory[7]; 
  assign      word7 = Datapath.M1.memory[8]; 
  assign      word8 = Datapath.M1.memory[11]; 
  assign      word9 = Datapath.M1.memory[12]; 
  assign      word10 = Datapath.M1.memory[13]; 
  assign      word11 = Datapath.M1.memory[14]; 
  assign      word12 = Datapath.M1.memory[17]; 
  assign      word13 = Datapath.M1.memory[18]; 
  assign      word14 = Datapath.M1.memory[19]; 
  assign      word15 = Datapath.M1.memory[20]; 
  assign      word16 = Datapath.M1.memory[22]; 
  assign      word17 = Datapath.M1.memory[23]; 
  assign      word18 = Datapath.M1.memory[24]; 
  assign      word19 = Datapath.M1.memory[25]; 
  assign      word20 = Datapath.M1.memory[28]; 
  assign      word21 = Datapath.M1.memory[29]; 
  assign      word22 = Datapath.M1.memory[30]; 
  assign      word23 = Datapath.M1.memory[31]; 
  assign      word24 = Datapath.M1.memory[33]; 
  assign      word25 = Datapath.M1.memory[34]; 
  assign      word26 = Datapath.M1.memory[35]; 
  assign      word27 = Datapath.M1.memory[36]; 
  assign      word28 = Datapath.M1.memory[39]; 
  assign      word29 = Datapath.M1.memory[40]; 
  assign      word30 = Datapath.M1.memory[41]; 
  assign      word31 = Datapath.M1.memory[42]; 
  assign      word32 = Datapath.M1.memory[44]; 
  assign      word33 = Datapath.M1.memory[45]; 
  assign      word34 = Datapath.M1.memory[46]; 
  assign      word35 = Datapath.M1.memory[47]; 
  assign      word36 = Datapath.M1.memory[49]; 
  assign      word37 = Datapath.M1.memory[50]; 
  assign      word38 = Datapath.M1.memory[51]; 
  assign      word39 = Datapath.M1.memory[52]; 
  
  
  //VNLP VNLP(norm2, len, done, A1, A2, counter, D1, D2, Next, Before,Accumulator, add1_sel, add2_sel, before_sel, next_sel, acc_sel, A1_sel, A2_sel, load_before, load_next, load_acc,clk, start);
  
  
  //Flush memory
  initial
  begin: Flush
  start_op=0; clk=0; 
  for (k=0; k&lt;=52; k=k+1) Datapath.M1.memory[k] = 0; 
  end
  
  initial
  begin: Load
  #5
    #5 start_op=1; #5 start_op=0;
  Datapath.M1.memory[0] = 49; 
  Datapath.M1.memory[1] = 34; 
  Datapath.M1.memory[2] = -33;                  
  Datapath.M1.memory[3] = 23; 
  Datapath.M1.memory[5] = 17 ;
  Datapath.M1.memory[6]=40; 
  Datapath.M1.memory[7] = 19;
  Datapath.M1.memory[8]=102; 
  Datapath.M1.memory[11] = 22;
  Datapath.M1.memory[12]=18; 
  Datapath.M1.memory[13] = 25; 
  Datapath.M1.memory[14] = -93;         
  Datapath.M1.memory[17]=11; 
  Datapath.M1.memory[18] = 6; 
  Datapath.M1.memory[19] = 8 ;
  Datapath.M1.memory[20]=90; 
  Datapath.M1.memory[22] = 33; 
  Datapath.M1.memory[23] = 12; 
  Datapath.M1.memory[24] = 31; 
  Datapath.M1.memory[25] = 32; 
  Datapath.M1.memory[28] = 102; 
  Datapath.M1.memory[29] = 240; 
  
  Datapath.M1.memory[30]=47; 
  Datapath.M1.memory[31] = -11; 
  Datapath.M1.memory[33] = 0;         
  Datapath.M1.memory[34]=23; 
  Datapath.M1.memory[35] = 25; 
  Datapath.M1.memory[36] = 88;
  Datapath.M1.memory[39]=5; 
  Datapath.M1.memory[40] = 50; 
  Datapath.M1.memory[41] = 56; 
  Datapath.M1.memory[42] = 48; 
  Datapath.M1.memory[44] = 56; 
  Datapath.M1.memory[45] = 88; 
  Datapath.M1.memory[46] = 112; 
  
  Datapath.M1.memory[47] = 69; 
  Datapath.M1.memory[49] = 39; 
  Datapath.M1.memory[50] = 1; 
  Datapath.M1.memory[51] = 101; 
  Datapath.M1.memory[52] = 63; 
  
  end
  
  
  always forever #5 clk=~clk;
  
  endmodule
  </code></pre>
  
  <p>And this is an idea of the architecture if that helps:</p>
  
  <p><a href="http://i.stack.imgur.com/IiJ4D.png" rel="nofollow">Architecture Schematic for processor</a></p>