title: Implementing a counter in VHDL
body: <p>The following code implements a two digit counter and displays the output on seven segments. As can be seen, in each clock cycle, the value has to be changed but the simulation results doesn't show such thing. To reduce the code size, I only put 0 and 1 in the seven segment driver.</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity two_digit_counter is
      port( clk: in std_logic;
            x, y: out std_logic_vector( 6 downto 0 ));
  end;
  
  architecture x of two_digit_counter is
  begin
      process( clk )
          variable d1 : integer range 0 to 9 := 0;
          variable d2 : integer range 0 to 9 := 0;
      begin
          if (clk'event and clk = '1') then
              if d1 = 9 then
                  d1 := 0;
                  d2 := d2 + 1;
              elsif d2 = 9 then
                  d2 := 0;
                  d1 := 0;
              else
                  d1 := d1 + 1;
              end if;
          end if;
  
          case d1 is
              when 0   =&gt;    x &lt;= "1111110";  -- 7E
              when 1   =&gt;    x &lt;= "0110000";  -- 30
          end case;
          case d2 is
              when 0   =&gt;    x &lt;= "1111110";
              when 1   =&gt;    x &lt;= "0110000";
          end case;
      end process;
  end;
  </code></pre>
  
  <p><a href="https://i.stack.imgur.com/2gQdr.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2gQdr.jpg" alt="enter image description here"></a></p>