title: Implementing a FSM in VHDL
body: <p>Just wondering if I'm implementing a finite state machine in VHDL whether or not I need to state what <strong>all</strong> of the outputs are in every possible state? Even if I know that some outputs won't change from one state to the other and I know that the order of the states will also be in the same order?</p>
  
  <p>For example, in this (forced) example:</p>
  
  <pre><code>entity test is
      port (
          clk : in std_logic;
          a : in std_logic;
          b: out std_logic;
          c: out std_logic;
      );
  end test;
  
  architecture Behavioral of test is
  
  type executionStage is (s1,s2,s3);
  signal currentstate, nextstate: executionStage;
  
  begin
      process (clk)
      begin
            if(rising_edge(clk)) then
                   currentstate &lt;= nextstate;
            else 
                   currentstate &lt;= currentstate;
            end if;
      end process;
  
      process(currentstate)
      begin
          case currentstate is
              when s1 =&gt;
                  if (a = '1') then
                      b &lt;= '1';
                      c &lt;= '0';
                  else
                      b &lt;= '1';
                      c &lt;= '1';
                  end if;
  
                  nextstate &lt;= s2;
  
              when s2 =&gt;
                  -- b doesnt change state from s1 to here, do I need to define what it is here?
                  if (a = '1') then
                      b &lt;= '1';
                      c &lt;= '1';
                  else
                      b &lt;= '1';
                      c &lt;= '0';
                  end if;
  
                  nextstate &lt;= s3;
  
              when s3 =&gt;
                  if (a = '1') then
                      b &lt;= '0';
                      c &lt;= '0';
                  else
                      b &lt;= '1';
                      c &lt;= '1';
                  end if;
  
                  nextstate &lt;= s1;
          end case;
      end process;
  end Behavioral;
  </code></pre>
  
  <p>From my understanding if I don't do this then latches are created?</p>
  
  <p>It's not a big deal in something like that example but if I have a machine with more than 10 outputs and more than 10 states then my VHDL files start to look incredibly messy and I'm sure it must be bad practice to copy and paste the same thing over and over. Is there a better way of doing this?</p>
  
  <p>edit: Can I define a 'default' state for an ouput? IE set b to be 1 outside of all the processes and then only define what it is in the case statements where it is 0? Would that work?</p>