title: Link .h files and .c files from different directory using makefile
body: <p>I'm trying to compile a program called um from a current folder with um.c
  and include some external implementations. The .h files are in one directory but the .c files implementing these .h files are in a different directory. Below is my makefile. It seems that the compiler knows where to look for the .h file. However, the linker fails and produces the error: </p>
  
  <pre><code>ld: symbol(s) not found for architecture x86_64
  clang: fatal error: linker command failed with exit code 1
  </code></pre>
  
  <p>Makefile:</p>
  
  <pre><code># define the C compiler to use
  CC = gcc
  
  # define any compile-time flags
  CFLAGS = -g -O -Wall -Wextra -Werror -Wfatal-errors -std=c99 -pedantic
  
  # define any directories containing header files other than /usr/include
  INCLUDES = -I/Users/nguyenmanhduc/Documents/C\ library/cii/include
  
  # define library paths in addition to /usr/lib
  LFLAGS = -L/Users/nguyenmanhduc/Documents/C\ library/cii/src
  
  # define any libraries to link into executable:
  LIBS = -lm
  
  # define the C source files
  SRCS = um.c
  
  # define the C object files 
  OBJS = $(SRCS:.c=.o)
  
  # define the executable file 
  MAIN = um
  
  .PHONY: depend clean
  
  all:    $(MAIN)
      @echo  Simple compiler named um has been compiled
  
  $(MAIN): $(OBJS) 
      $(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
  
  .c.o:
      $(CC) $(CFLAGS) $(INCLUDES) -c $&lt;  -o $@
  
  clean:
      $(RM) *.o *~ $(MAIN)
  
  depend: $(SRCS)
      makedepend $(INCLUDES) $^
  </code></pre>
  
  <p>This question might seem weird because I have little experience with makefile but is there a way that I can link .h and .c files in different folders using makefile.</p>
  
  <p>Thanks!</p>