title: Two's complement in verilog
body: <p>I've been trying to build a module which returns the two's complement representation of the (3-bit) input (first bit being the sign). I think that the following code is correct conceptually, but I am probably missing something about it's structure: when I try to compile, I get the following errors:</p>
  
  <pre><code>(vlog-2110) Illegal reference to net "f_o".
  (vlog-2110) Illegal reference to net "f_o".
  (vlog-2110) Illegal reference to net "f_o".
  </code></pre>
  
  <p>Searching for that error showed it is usually seen when using a variable as input and output at the same time, but that's not my case. Could you point where the error is?</p>
  
  <pre><code>module ca2 (a_i,f_o);
    input  [2:0] a_i;
    output [2:0] f_o;
  
    always @(a_i[2:0] or f_o[2:0])
    begin
      if (a_i[2] == 1)
      begin
        f_o[2]   = a_i[2];
        f_o[1:0] = (~a_i[1:0] + 'b1);
      end
      else
      begin
        f_o = a_i;
      end
    end
  endmodule
  </code></pre>