title: vhdl expression has 2 elements, but must have 3 elements
body: <p>Quartus keeps telling me that "expression has 2 elements, but must have 3 elements" on the "result:= to_unsigned(1, 1) + unsigned(X) + unsigned(Y);" line. 
  below is my code for building a CLA</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  entity cla2 is
  port(
      X, Y : in std_logic_vector(1 downto 0);
      Cin : in std_logic;
      S, BP, BG  : out std_logic_vector(1 downto 0);
      Cout : out  std_logic
      );
  end cla2;
  
  architecture Behavior of cla2 is 
  
  begin 
  
  process(X, Y, Cin)
      variable result : unsigned (2 downto 0);
  
  begin
      if(Cin = '1') then
      result:= to_unsigned(1, 1) + unsigned(X) + unsigned(Y);
      else 
      result:= unsigned(X) + unsigned(Y);
      end if;
      S&lt;= std_logic_vector(result(1 downto 0));
      Cout&lt;= result(2);
      BP&lt;=X or Y;
      BG&lt;=X and Y;
  end process;
  end Behavior;
  </code></pre>