title: Implement FIR Filter in Verilog
body: <p>I am trying to implement an FIR filter in Verilog. I have predetermined the coefficients in MATLAB. But I am not sure whether the registers will propagate properly with this code.</p>
  
  <pre><code>module fir_filter(
    input clock,
    input reset,
    input wire[15:0] input_sample,
    output reg[15:0] output_sample);
  
  parameter N = 13;
  reg signed[15:0] coeffs[12:0];
  reg [15:0] holderBefore[12:0];
  wire [15:0] toAdd[12:0];
  
  always @(*)
  begin
      coeffs[0]=6375;
      coeffs[1]=1;
      coeffs[2]=-3656;
      coeffs[3]=3;
      coeffs[4]=4171;
      coeffs[5]=4;
      coeffs[6]=28404;
      coeffs[7]=4;
      coeffs[8]=4171;
      coeffs[9]=3;
      coeffs[10]=-3656;
      coeffs[11]=1;
      coeffs[12]=6375;
  end
  
  genvar i;
  
  generate
  for (i=0; i&lt;N; i=i+1)
      begin: mult
          multiplier mult1(
            .dataa(coeffs[i]),
            .datab(holderBefore[i]),
            .result(toAdd[i]));
      end
  endgenerate
  
  always @(posedge clock or posedge reset)
  begin
      if(reset)
          begin
              holderBefore[12]    &lt;= 0;
              holderBefore[11]    &lt;= 0;
              holderBefore[10]    &lt;= 0;
              holderBefore[9]     &lt;= 0;
              holderBefore[8]     &lt;= 0;
              holderBefore[7]     &lt;= 0;
              holderBefore[6]     &lt;= 0;
              holderBefore[5]     &lt;= 0;
              holderBefore[4]     &lt;= 0;
              holderBefore[3]     &lt;= 0;
              holderBefore[2]     &lt;= 0;
              holderBefore[1]     &lt;= 0;
              holderBefore[0]     &lt;= 0;
              output_sample       &lt;= 0;
          end
      else
          begin               
              holderBefore[12]    &lt;= holderBefore[11];
              holderBefore[11]    &lt;= holderBefore[10];
              holderBefore[10]    &lt;= holderBefore[9];
              holderBefore[9]     &lt;= holderBefore[8];
              holderBefore[8]     &lt;= holderBefore[7];
              holderBefore[7]     &lt;= holderBefore[6];
              holderBefore[6]     &lt;= holderBefore[5];
              holderBefore[5]     &lt;= holderBefore[4];
              holderBefore[4]     &lt;= holderBefore[3];
              holderBefore[3]     &lt;= holderBefore[2];
              holderBefore[2]     &lt;= holderBefore[1];
              holderBefore[1]     &lt;= holderBefore[0];
              holderBefore[0]     &lt;= input_sample;
              output_sample &lt;= (input_sample + toAdd[0] + toAdd[1] + 
                                toAdd[2] + toAdd[3] + toAdd[4] + toAdd[5] +
                                toAdd[6] + toAdd[7] + toAdd[8] + toAdd[9] + 
                                toAdd[10] + toAdd[11] + toAdd[12]);
          end
  end
  
  
  
  endmodule
  </code></pre>
  
  <p>Is this the best way to implement this? is there a better way to do the addition? </p>
  
  <p>Any help is greatly appreciated!</p>
  
  <p>Also resources that would help are also greatly appreciated.</p>