title: How can I read binary data in VHDL/modelsim whithout using special binary formats
body: <p>I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to the MAC from a binary file which I exported from wireshark.</p>
  <p>I'm writing in VHDL 2008 and I'm using a Mentor Graphics Model Technology ModelSim ALTERA vcom 10.0d Compiler.</p>
  <p>All solutions for reading binary data in VHDL/modelsim that I've found so far use special file formats where 1 bit of the <code>bit_vector</code> is represented by several bits in the file. I would like VHDL to read the binary file into 8 bit <code>bit_vector</code>s.</p>
  <p>Closest I've gotten so far was using a character type file, where I can write 8 bit ASCII characters directly in binary representation.</p>