title: Verilog register cannot be driven by primitives or continuous assignment
body: <p>I want to use a module in a test bench like this:</p>
  
  <pre><code>reg [31:0] OutputVal;
  reg [15:0] InputVal;
  sign theSignExtender(InputVal,OutputVal);
  </code></pre>
  
  <p>When I compile, I get the error:</p>
  
  <blockquote>
    <p>error:  reg OutputVal; cannot be driven by primitives or continuous
    assignment.</p>
  </blockquote>
  
  <p>Any suggestions?</p>