title: FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2
body: <p>I'm confused on how many flops per cycle per core can be done with Sandy-Bridge and Haswell.
  As I understand it with SSE it should be 4 flops per cycle per core for SSE and 8 flops per cycle per core for AVX/AVX2.  </p>
  
  <p>This seems to be verified here,
  <a href="https://stackoverflow.com/questions/8389648/how-to-achieve-4-flops-per-cycle">How do I achieve the theoretical maximum of 4 FLOPs per cycle?</a>
  ,and here,
  <a href="https://stackoverflow.com/questions/12027922/sandy-bridge-cpu-specification">Sandy-Bridge CPU specification</a>.</p>
  
  <p>However the link below seems to indicate that Sandy-bridge can do 16 flops per cycle per core and Haswell 32 flops per cycle per core
  <a href="http://www.extremetech.com/computing/136219-intels-haswell-is-an-unprecedented-threat-to-nvidia-amd" rel="noreferrer">http://www.extremetech.com/computing/136219-intels-haswell-is-an-unprecedented-threat-to-nvidia-amd</a>.</p>
  
  <p>Can someone explain this to me?</p>
  
  <p>Edit:
  I understand now why I was confused.  I thought the term FLOP only referred  to single floating point (SP).  I see now that the test at <a href="https://stackoverflow.com/questions/8389648/how-to-achieve-4-flops-per-cycle">How do I achieve the theoretical maximum of 4 FLOPs per cycle?</a> are actually on double floating point (DP) so they achieve 4 DP FLOPs/cycle for SSE and 8 DP FLOPs/cycle for AVX.  It would be interesting to redo these test on SP.</p>