title: Verilog multiple drivers
body: <p>I'm trying to make BCD Counter using Verilog that will be connected to 7-segment decoder.<br />After I synthesize it, the error occured like this: <br /><br />
  <strong><code>Multi-source in Unit &lt;BCDcountmod&gt; on signal &lt;BCD0&lt;3&gt;&gt;; this signal is connected to multiple drivers.&gt;</code>**And more.....<br /><br />***Any solution?*</strong> (<em>Here's my code below</em>)</p>
  
  <pre><code>module BCDcountmod(
    input Clock, Clear, up, down,
    output [3:0] BCD1_1, BCD0_0 );
  reg [3:0] BCD1, BCD0;
  //reg [3:0] BCD1_1, BCD0_0;
  always @(posedge Clock) begin
    if (Clear) begin
      BCD1 &lt;= 0;
      BCD0 &lt;= 0;
      end
  end
  
  
   always @(posedge up) begin
        if (BCD0 == 4'b1001) begin
          BCD0 &lt;= 0;
          if (BCD1 == 4'b1001)
            BCD1 &lt;= 0;
          else
            BCD1 &lt;= BCD1 + 1;
        end
        else
          BCD0 &lt;= BCD0 + 1;
      end
  
  
  always @(posedge down) begin
        if (BCD0 == 4'b0000) begin
          BCD0 &lt;= 4'b1001;
          if (BCD1 == 4'b1001)
            BCD1 &lt;= 4'b1001;
          else
            BCD1 &lt;= BCD1 - 1;
        end
        else
          BCD0 &lt;= BCD0 - 1;
      end
  
   assign BCD1_1 = BCD1;
   assign BCD0_0 = BCD0;
  
  endmodule
  </code></pre>