title: Data memory unit
body: <p>I started Verilog a few weeks ago and now I'm implementing MIPS pipelining on an FPGA board and I'm on the MEM part of the pipelining stage. I'm trying to code the Data memory unit (in picture -> Data memory Unit). </p>
  
  <p><a href="https://i.stack.imgur.com/Xzj0j.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Xzj0j.png" alt="Snapshot"></a></p>
  
  <p>I don't understand the use of memread. I understand that if memwrite is 1, the contents of the current address is passed to read data.</p>
  
  <p>So far, this is my code:</p>
  
  <pre><code>module data_memory (
  input wire [31:0] addr,             // Memory Address
  input wire [31:0] write_data,       // Memory Address Contents
  input wire memwrite, memread,
  output reg [31:0] read_data     // Output of Memory Address Contents
  );
  
  reg [31:0] MEMO[0:255];  // 256 words of 32-bit memory
  
  integer i;
  
  initial begin
  
     read_data &lt;= 0;
  
     for (i = 0; i &lt; 256; i = i + 1)
       MEMO[i] = i;
  
     end
  
  always @ (addr) begin
  
     //**I don't understand the use of memread**//
  
     if (memwrite == 1'b1)
         MEMO[addr] &lt;= write_data;
     end
  end
  
  assign read_data = MEMO[addr];
  
  endmodule 
  </code></pre>
  
  <p>Do I need another if statement for the memread? Any help is greatly appreciated. Thanks</p>