title: Use of For loop in always block
body: <p>I am writing a Verilog code for calculating the number of digits in a decimal number. In the code below I have initialised the value of c to be equal to a.
  I was able to get the simulation results correctly but unable to syntesise and the error is due to 'c=a'. How can I get rid of the error ? Is there any other logic to calculate the number of digits ?</p>
  
  <pre><code>Error: [Synth 8-3380] loop condition does not converge after 2000 iterations 
  </code></pre>
  
  <p>Code :-</p>
  
  <pre><code>module numdigits(a,b);
  parameter n=100;
  input [0:n-1] a;
  output reg [0:n-1]b;   //THIS MODULE COUNTS THE NUMBER OF DIGITS IN DECIMAL FORM
  reg [0:n-1] d,c;
  always @(*)
  begin 
      d=0;
      for(c=a;c&gt;0;c=c/10)
      begin
      d=d+1;
      end
      b=d;
  end 
  endmodule
  </code></pre>