title: Instantiation of a module in verilog
body: <p>I am getting an error in instantiating a module in verilog file. I am instantiating like this:</p>
  <pre><code>module lab3(input clk,set,reset,plus,minus,start,button,output reg [3:0]led,output reg [6:0]y);
  
  wire [3:0] indicesgu[3:0];
  reg [1:0] going;
  reg alsogoing,yes;
  
  
  if (going==1 &amp;&amp; alsogoing)
  begin
   up_counter up_0 
   indicesgu  ,
   indices    ,
   alsogoing
   );
  end
  </code></pre>
  <p>and my up_counter module starts as:</p>
  <pre><code>module up_counter(input [3:0] indices_in [3:0],output [3:0]indices[3:0],output alsogoing);
  
  reg [3:0]indices[3:0];
  reg [2:0]current,setting;
  </code></pre>
  <p>when I try to compile in Xilinx, it says unexpected token up_counter.
  Thanks in advance.</p>