title: Possible to build a 32bit adder from 32 1-bit adders?
body: <p>I am supposed to complete the module below,  by creating 32 assignment statements
  doesn't seem to be the right way of doing this.  I know that i have to carry the cout up, 
  but when create and test a yAdder using a client module, I get incorrect about like 1 + 1 =  4 billion.  lol.   I know what it should do, I just don't know how to do it in verilog.</p>
  
  <pre><code>    module yAdder(z,cout,a,b,cin);
  output [31:0] z;
  output cout;
  input[31:0] a, b;
  input cin;
  wire[31:0] in,out;
  yAdder1 mine[31:0](z,out,a,b,in);
  
  assign in[0] = cin;
  assign in[1] = out[0];
  assign in[2] = out[0];
  assign in[3] = out[0];
  assign in[4] = out[0];
  assign in[5] = out[0];
  assign in[6] = out[0];
  assign in[7] = out[0];
  assign in[8] = out[0];
  assign in[9] = out[0];
  assign in[10] = out[0];
  assign in[11] = out[0];
  assign in[12] = out[0];
  assign in[13] = out[0];
  assign in[14] = out[0];
  assign in[15] = out[0];
  assign in[16] = out[0];
  assign in[17] = out[0];
  assign in[18] = out[0];
  assign in[19] = out[0];
  assign in[20] = out[0];
  assign in[21] = out[0];
  assign in[22] = out[0];
  assign in[23] = out[0];
  assign in[24] = out[0];
  assign in[25] = out[0];
  assign in[26] = out[0];
  assign in[27] = out[0];
  assign in[28] = out[0];
  assign in[29] = out[0];
  assign in[30] = out[0];
  assign in[31] = out[0];
  assign cout = out[0];
  
  
  endmodule
  </code></pre>
  
  <p>and the 1 bit adder module.</p>
  
  <pre><code>module yAdder1(z,cout,a,b,cin);
  output z, cout;
  input a, b, cin;
  
  xor left_xor(tmp,a,b);
  xor right_xor(z,cin,tmp);
  and left_and(outL,a,b);
  and right_and(outR,tmp,cin);
  or my_or(cout,outR,outL);
  
  endmodule
  </code></pre>