title: Verilog Best Practice - Incrementing a variable
body: <p>I'm by no means a Verilog expert, and I was wondering if someone knew which of these ways to increment a value was better. Sorry if this is too simple a question.</p>
  
  <p>Way A:</p>
  
  <p>In a combinational logic block, probably in a state machine:</p>
  
  <pre><code>//some condition
  count_next = count + 1;
  </code></pre>
  
  <p>And then somewhere in a sequential block:</p>
  
  <pre><code>count &lt;= count_next;
  </code></pre>
  
  <p>Or Way B:<br>
  Combinational block:</p>
  
  <pre><code>//some condition
  count_en = 1;
  </code></pre>
  
  <p>Sequential block:</p>
  
  <pre><code>if (count_en == 1)
    count &lt;= count + 1;
  </code></pre>
  
  <p>I have seen Way A more often. One potential benefit of Way B is that if you are incrementing the same variable in many places in your state machine, perhaps it would use only one adder instead of many; or is that false?</p>
  
  <p>Which method is preferred and why? Do either have a significant drawback?</p>
  
  <p>Thank you.</p>