title: No constraints for the design eventhoug I have specified(marked as target) the constraint file
body: <p>I have a school project in which I need to create a communication between a USB HID keyboard and Nexys4DDR in VHDL using Vivado 2018.3 . I have used  the Nexys 4 keyboard demo from <a href="https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-keyboard-demo/start" rel="nofollow noreferrer">here</a> which I wrote in VHDL and to which I have added a DCD in order to decode the values and to output the correct letter. My issue is with the bit stream generation. The error I get is  only when running the bit stream generation and it does not appear in synthesis or implementation.</p>
  <blockquote>
  <p>WARNING: [Constraints 18-5210] No constraints selected for write.
  Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.</p>
  </blockquote>
  <p>I have used the same constraint file as it is specified on the program from diligent.
  I am unsure where the issue is.</p>
  <p>My constraint file is :</p>
  <pre><code>## Clock signal
  set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { Clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
  create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {Clk}];
  
  
  ##Switches
  
  #set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
  #set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
  #set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
  #set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
  #set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
  #set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
  #set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
  #set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
  #set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
  #set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
  #set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
  #set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
  #set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
  #set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
  #set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
  #set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
  
  
  ## LEDs
  
  #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
  #set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
  #set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
  #set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
  #set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
  #set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
  #set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
  #set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
  #set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
  #set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
  #set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
  #set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
  #set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
  #set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
  #set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
  #set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
  
  #set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
  #set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
  #set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
  #set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
  #set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
  #set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
  
  
  ##7 segment display
  
  set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { SEG[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
  set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { SEG[1] }]; #IO_25_14 Sch=cb
  set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { SEG[2] }]; #IO_25_15 Sch=cc
  set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { SEG[3] }]; #IO_L17P_T2_A26_15 Sch=cd
  set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { SEG[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
  set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { SEG[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
  set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { SEG[6] }]; #IO_L4P_T0_D04_14 Sch=cg
  
  set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
  
  set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
  set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
  set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
  set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
  set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
  set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
  set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
  set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
  
  
  ##Buttons
  
  #set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
  
  set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { Rst }]; #IO_L9P_T1_DQS_14 Sch=btnc(Rst)
  #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
  #set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
  #set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
  #set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
  
  
  ##Pmod Headers
  
  
  ##Pmod Header JA
  
  #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
  #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
  #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
  #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
  #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
  #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
  #set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
  #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
  
  
  ##Pmod Header JB
  
  #set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
  #set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
  #set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
  #set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
  #set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
  #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
  #set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
  #set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
  
  
  ##Pmod Header JC
  
  #set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
  #set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
  #set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
  #set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
  #set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
  #set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
  #set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
  #set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
  
  
  ##Pmod Header JD
  
  #set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
  #set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
  #set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
  #set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
  #set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
  #set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
  #set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
  #set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
  
  
  ##Pmod Header JXADC
  
  #set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVDS     } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
  #set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVDS     } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
  #set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVDS     } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
  #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVDS     } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
  #set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVDS     } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
  #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVDS     } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
  #set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVDS     } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
  #set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVDS     } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
  
  
  ##VGA Connector
  
  #set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
  #set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
  #set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
  #set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
  
  #set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
  #set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
  #set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
  #set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
  
  #set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
  #set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
  #set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
  #set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
  
  #set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
  #set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
  
  
  ##Micro SD Connector
  
  #set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
  #set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
  #set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
  #set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
  #set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
  #set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
  #set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
  #set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
  
  
  ##Accelerometer
  
  #set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
  #set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
  #set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
  #set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
  #set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
  #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
  
  
  ##Temperature Sensor
  
  #set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
  #set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
  #set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
  #set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
  
  ##Omnidirectional Microphone
  
  #set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
  #set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
  #set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
  
  
  ##PWM Audio Amplifier
  
  #set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
  #set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
  
  
  ##USB-RS232 Interface
  
  #set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
  set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
  #set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
  #set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
  
  ##USB HID (PS/2)
  
  set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
  set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
  </code></pre>
  <p>The main program is connected to a PS2 receiver, decoder and a 7 segment display.</p>
  <pre><code>entity top is
  Port ( 
  Clk: in std_logic;
  Rst: in std_logic;
  PS2_clk: in std_logic;
  PS2_data: in std_logic;
  SEG: out std_logic_vector(7 downto 0);
  AN: out std_logic_vector(7 downto 0);
  DP: out std_logic;
  UART_TXD: out std_logic
  );
  end top;
  
  architecture Behavioral of top is
  signal smallerCLK:std_logic:='0';
  signal keycode: std_logic_vector(31 downto 0);
  component PS2RECEIVER is 
  Port    ( clk : in STD_LOGIC;
             kclk : in STD_LOGIC;
             kdata : in STD_LOGIC;
             outData : out STD_LOGIC_VECTOR (31 downto 0));
  end component;
  
  component DCD is
   Port (
   input: in std_logic_vector(31 downto 0);
   CLK: in std_logic;
   output: out std_logic_vector(31 downto 0)
    );
  end component DCD;
  signal output:  std_logic_vector(31 downto 0);
  begin
  
  process(clk)
  begin
  smallerCLK&lt;=NOT smallerCLK;
  end process;
  PS2: PS2RECEIVER port map (smallerCLK,PS2_CLK,PS2_DATA,keycode);
  
  DC:DCD port map(keycode,smallerCLK,output);
  display: entity WORK.displ7seg
              port map(Clk =&gt; Clk,
                       Rst =&gt; Rst,
                       Data =&gt; output,
                       An =&gt; An,
                       Seg =&gt; Seg);
  
  end Behavioral;
  </code></pre>
  <p>The PS2 receiver which is connected to a debouncer:</p>
  <pre><code>entity PS2Receiver is
      Port ( clk : in STD_LOGIC;
             kclk : in STD_LOGIC;
             kdata : in STD_LOGIC;
             outData : out STD_LOGIC_VECTOR (31 downto 0));
  end PS2Receiver;
  
  architecture Behavioral of PS2Receiver is
  signal kclkf: std_logic;
  signal kdataf: std_logic;
  signal datacur: std_logic_vector(7 downto 0);
  signal dataprev: std_logic_vector(7 downto 0);
  signal cnt: std_logic_vector(3 downto 0):=&quot;0000&quot;; 
  signal keycode: std_logic_vector(31 downto 0):= (Others =&gt; '0');
  signal flag: std_logic:='0';
  
  component debouncer is
  port(CLK: in std_logic;
       I0: in std_logic;
       I1: in std_logic;
      O0: out std_logic;
      O1:out std_logic );
  end component;
  
  begin
  
  Deb: debouncer port map(clk=&gt;clk,I0=&gt;kclk,I1=&gt;kdata,O0=&gt;kclkf,O1=&gt;kdataf);
  
  
  
  process(clk)
  begin 
      if falling_edge(kclkf) then
         case cnt is 
                when &quot;0000&quot; =&gt; null ; --do nothing is the starting bit--0
              when &quot;0001&quot; =&gt; datacur&lt;=datacur(7 downto 1) &amp; kdataf;--1
           when &quot;0010&quot; =&gt; datacur&lt;=datacur(7 downto 2) &amp; kdataf &amp; datacur(0);--2
         when &quot;0011&quot; =&gt; datacur&lt;=datacur(7 downto 3) &amp; kdataf &amp; datacur(1 downto 0);--3
                when &quot;0100&quot; =&gt; datacur&lt;=datacur(7 downto 4) &amp; kdataf &amp; datacur(2 downto 0);--4
             when &quot;0101&quot; =&gt; datacur&lt;=datacur(7 downto 5) &amp; kdataf &amp; datacur(3 downto 0);---5
              when &quot;0110&quot; =&gt; datacur&lt;=datacur(7 downto 6) &amp; kdataf &amp; datacur(4 downto 0);--6
               when &quot;0111&quot; =&gt; datacur&lt;=datacur(7) &amp; kdataf &amp; datacur(5 downto 0);--7
              when &quot;1000&quot; =&gt; datacur&lt;= kdataf &amp; datacur(6 downto 0);--8
              when &quot;1001&quot; =&gt; flag&lt;='1';--9
              when &quot;1010&quot; =&gt; flag&lt;='0';--10
               when others=&gt; NULL;
         end case;
         if(cnt &lt;= 9) then cnt&lt;= cnt+1;
          elsif cnt=10 then cnt&lt;=(Others =&gt; '0');
        end if;
  end if; 
  end process;
  
  process(flag)
  begin 
      if rising_edge(flag) then 
          if NOT(dataprev = datacur) then 
             keycode(31 downto 24)&lt;= keycode(23 downto 16);
             keycode(23 downto 16)&lt;= keycode(15 downto 8);
             keycode(15 downto 8)&lt;= dataprev;
             keycode(7 downto 0)&lt;= datacur;
             dataprev&lt;= datacur;           
              end if;
          end if;
  end process;
  
  outData&lt;=keycode;
  
  
  end Behavioral;
  
  
  
  entity Debouncer is
   Port (
   CLK: in std_logic;
   I0: in std_logic;
   I1: in std_logic;
   O0: out std_logic;
   O1:out std_logic );
  end Debouncer;
  
  architecture Behavioral of Debouncer is
  signal cnt0: std_logic_vector(4 downto 0):=&quot;00000&quot;; 
  signal cnt1: std_logic_vector(4 downto 0):=&quot;00000&quot;; 
  signal Iv1: std_logic:='0';
  signal Iv0: std_logic:='0';
  signal out0:std_logic;
  signal out1: std_logic;
  
  begin
  
  process(clk)
  begin
     if rising_edge(clk) then
      if(I0=Iv0)then
          if cnt0=&quot;10011&quot; then O0&lt;=I0;
              else cnt0&lt;=cnt0+&quot;00001&quot;;
          end if;
          else 
              cnt0&lt;=&quot;00000&quot;;
              Iv0&lt;= I0;
          end if;
      if(I1=Iv1)then
          if cnt1=&quot;10011&quot; then O1&lt;=I1;
              else cnt1&lt;=cnt1+&quot;00001&quot;;
          end if;
          else 
              cnt1&lt;=&quot;00000&quot;;
              Iv1&lt;= I1;
          end if;    
           
         end if;
  end process;
  
  end Behavioral;
  </code></pre>
  <p>And the DCD is :</p>
  <pre><code>entity DCD is
   Port (
   input: in std_logic_vector(31 downto 0);
   CLK: in std_logic;
   output: out std_logic_vector(31 downto 0)
    );
  end DCD;
  
  architecture Behavioral of DCD is
  signal AUX : std_logic_vector(31 downto 0);
  begin
  
  process(clk)
  begin
  case input is 
          
           when &quot;00000000000000000000000001000101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011000000&quot;; --0
         when &quot;00000000000000000000000000010110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011111001&quot;; --1 
           when &quot;00000000000000000000000000011110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010100100&quot;; --2
           when &quot;00000000000000000000000000100110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010110000&quot;; --3
           when &quot;00000000000000000000000000100101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010011011&quot;; --4
       when &quot;00000000000000000000000000101110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010010010&quot;; --5
           when &quot;00000000000000000000000000110110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010000010&quot;; --6
          when &quot;00000000000000000000000000111101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011111000&quot;; --7
         when &quot;00000000000000000000000000111110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010000000&quot;; --8
         when &quot;00000000000000000000000001000110&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010010000&quot;; --9  
           when &quot;00000000000000000000000000011100&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010001000&quot;; --A     
           when &quot;00000000000000000000000000110010&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010000011&quot;; --b    
           when &quot;00000000000000000000000000100001&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011000110&quot;; --C        
           when &quot;00000000000000000000000000100011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010100001&quot;; --d
           when &quot;00000000000000000000000000100100&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010000110&quot;; --E
           when &quot;00000000000000000000000000101011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010001110&quot;; --F 
           when &quot;00000000000000000000000000110100&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010000010&quot;; --G    
           when &quot;00000000000000000000000000110011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010001001&quot;; --H     
           when &quot;00000000000000000000000001000011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011001111&quot;; --I     
           when &quot;00000000000000000000000000111011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011110001&quot;; --J
           when &quot;00000000000000000000000001000010&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010001111&quot;; --K    
           when &quot;00000000000000000000000001001011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011000111&quot;; --L    
           when &quot;00000000000000000000000000111010&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011001000&quot;; --M
           when &quot;00000000000000000000000000110001&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010101011&quot;; --N
           when &quot;00000000000000000000000001000100&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011000000&quot;; --O    
           when &quot;00000000000000000000000001001101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010001100&quot;; --P
           when &quot;00000000000000000000000000010101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010100001&quot;; --Q    
           when &quot;00000000000000000000000000101101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010101111&quot;; --r     
           when &quot;00000000000000000000000000011011&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010010010&quot;; --S
           when &quot;00000000000000000000000000101100&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010000111&quot;; --t
           when &quot;00000000000000000000000000111100&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011000001&quot;; --U
           when &quot;00000000000000000000000000101010&quot;=&gt; AUX &lt;=&quot;00000000000000000000000011010101&quot;; --V                      
           when &quot;00000000000000000000000000011101&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010011001&quot;; --Y
           when &quot;00000000000000000000000000011010&quot;=&gt; AUX &lt;=&quot;00000000000000000000000010100100&quot;; --Z
           when &quot;00000000000000000000000000101001&quot;=&gt; AUX &lt;=&quot;00000000000000000000000001110111&quot;; -- Spaceend case
           when others=&gt; NULL;
  end case;
  
  end process;
  output&lt;=AUX;
  
  end Behavioral;
  </code></pre>
  <p>Has somebody else run into this problem and has a solution  ?</p>
  <p>Thank you!</p>