title: Passing parameters to a Verilog function
body: <p>I want to pass a parameter to a function and use it as a parameter (e.g. to select bits) but I don't know how to tell the function that this input is a constant.</p>
  
  <p>For example, if I wanted to do this:</p>
  
  <pre><code>assign foo = bar[MY_PARAM:0];
  </code></pre>
  
  <p>I want to write <code>my_function</code> so that I could do this:</p>
  
  <pre><code>assign foo = my_function(bar, MY_PARAM);
  </code></pre>
  
  <p>In my case I need to do a little more that just select bits but not too much, and I'll want it to work for inputs of different bit widths. 
  If I just wanted to select a bit I could use the function below and I'd hope for a solution of similar form but I can't work out the syntax:</p>
  
  <pre><code>function my_function;
    input [3:0] data, my_bit;
    begin
      my_function = data[my_bit];
    end
  endfunction
  </code></pre>
  
  <hr>
  
  <p>As per Silicon1602's answer, the code I'd need for this would be:</p>
  
  <pre><code>virtual class myClass#(parameter LOCAL_PARAM);
    static function [LOCAL_PARAM:0] my_function;
      input [LOCAL_PARAM:0] data;
      begin
        my_function = data[LOCAL_PARAM:0];
      end
    endfunction
  endclass
  assign foo = myClass#(MY_PARAM)::my_function(bar);
  </code></pre>
  
  <p>At first I forgot about the <code>[LOCAL_PARAM]</code> part and was just getting 1-bit back.</p>