title: My stack (LIFO) memory overflows and prevents any further reading of memory
body: <p>I've been working on coding a simple stack memory. It has 4 address bits and thus can store 16 elements. Everything works fine, but the problem is that when all 16 memory elements have been written to, the counter that keeps track of the memory location overflows and resets it to 0000. I cannot find out the reason for this. All my registers are of correct width.</p>
  
  <p><code>reg_push</code> and <code>reg_pop</code> are incremented and decremented together, and these are the registers that keep track of the memory location.</p>
  
  <p>Here is the simulation showing the overflow.
  <img src="https://i.stack.imgur.com/4B45r.png" alt="stack simulation"></p>
  
  <p>Here is the code:</p>
  
  <pre><code>module stack # (parameter dbits = 3, abits = 4)(
  input clock,
  input reset,
  input push,
  input pop,
  input [dbits-1:0] din,
  output [dbits-1:0] dout,
  output full,
  output empty
  );
  
  reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
  reg [abits-1:0] reg_push, reg_pop, next_push, next_pop;
  reg full_reg, empty_reg, full_next, empty_next;
  reg [dbits-1:0] out;
  wire wr_en;
  
  wire db_push, db_pop;
  reg dffpop1, dffpop2, dffpush1, dffpush2;
  
  always @ (posedge clock) dffpush1 &lt;= push; 
  always @ (posedge clock) dffpush2 &lt;= dffpush1;
  
  assign db_push = ~dffpush2 &amp; dffpush1; //monostable multivibrator to detect only one pulse of the button
  
  always @ (posedge clock) dffpop1 &lt;= pop;
  always @ (posedge clock) dffpop2 &lt;= dffpop1;
  
  assign db_pop = ~dffpop2 &amp; dffpop1; //monostable multivibrator to detect only one pulse of the button
  
  assign wr_en = db_push &amp; ~full; //only push if write signal is high and stack is not full
  
  //always block for write operation
  always @ (posedge clock)
      if(wr_en) regarray[reg_push] = din;
  
  //always block for read operation   
  always @ (posedge clock)
  begin
      if(db_pop)
          out &lt;= regarray[reg_pop];
  end
  
  
  always @ (posedge clock or posedge reset)
  begin
      if(reset)
          begin
              full_reg &lt;= 0;
              empty_reg &lt;= 1;
              reg_push &lt;= 0;
              reg_pop &lt;= 0;
          end
      else
          begin
              full_reg &lt;= full_next;//created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
              empty_reg &lt;= empty_next;
              reg_push &lt;= next_push;
              reg_pop &lt;= next_pop;
          end
  end
  
  always @ (*)
  begin
      full_next = full_reg; //default values stay the same
      empty_next = empty_reg;
      next_push = reg_push;
      next_pop = reg_pop;
  
      if(db_push)
      begin
          if(~full) //if stack is not full continue
          begin
              empty_next = 0;
              next_push = reg_push + 1;
              next_pop = reg_pop + 1;
              if(reg_push == (2**abits - 1)) full_next = 1; //all registers have been written to
          end
      end
  
      else if (db_pop)
      begin
          if(~empty) //if stack is not empty continue
          begin
              full_next = 0;
              next_pop = reg_pop - 1;
              next_push = reg_push - 1;
              if(reg_pop == 0) empty_next = 1; //all data has been read
          end
      end
  end
  
  
  assign full = full_reg;
  assign empty = empty_reg;
  assign dout = out;
  
  endmodule
  </code></pre>
  
  <p><strong>Now</strong> if I use this stack without making it reach its full capacity, it will work perfectly. It's only when I store all 16 elements into it that the problem arises.</p>