title: Is indexing into an array with a signal synthesizable in verilog?
body: <p>Are there any problems with synthesizing the following?:</p>
  <pre><code> // Read entry
    assign entry[7:0] = my_array[read_address[10:0]][7:0];
  </code></pre>
  <p>Where <em>read_address</em> is a signal being used to read <em>my_array</em>.</p>
  <p>I'm used to AND-OR logic for reading an array but I was wondering if the above is 1) synthesizable and 2) what kind of logic it would create?</p>