title: Verilog: multidimensional registered outputs
body: <p>I have some Verilog module with multidimensional outputs (to 7-segment LED panels of my DE1-SoC). I want to make the outputs registered. To test it, I give some dummy code to one of LED digits. Its RTL simulation passes OK, it's even compiled by Quartus, but actually it does not work.</p>
  
  <pre><code>module Top
  (
      input CLK50,
      output [6:0] HEX[5:0]
  );
  
  reg[6:0] hex_regs[5:0];
  
  //assign HEX[0][6:0] = 7'b010_1010; //if use assign, it assigns value to output, but I want it registered
  
  initial
  begin
      hex_regs[5][6:0] = 7'b101_0101;
  end
  
  assign HEX = hex_regs;
  
  endmodule
  </code></pre>
  
  <p>Cannot you tell me, how to do this correctly and where is my mistake?</p>