title: wire equation in verilog
body: <p>If say I have the following wire set-ups, is the wire assignment all valid?</p>
  
  <pre><code>wire[3:1] w;
  wire w1;
  wire [1:0] w2;
  
  A) w1 = w[2];    
  B) w2 = w[1:0];  
  C) w2 = w[1:2];
  </code></pre>
  
  <p>I am guessing that everything is valid....</p>