title: SystemVerilog hierarchical reference in nonblocking assigment
body: <p>I'm seeing strange behavior in my testbench where a nonblocking assignment is acting as a continuous assignment instead of outputting the RHS delayed by one cycle.</p>
  <p>My testbench binds a module &quot;cov&quot; to the DUT at cpu.cache via <code>bind cache cov cov_top</code>, and inside the &quot;cov&quot; module I have this nonblocking assignment:</p>
  <pre><code>module cov
    import cachePkg::*;
  (
    input logic clk,
    input logic rst
  );
    clocking cclk @(posedge clk iff !rst); endclocking
  
    logic [1:0] LinkState_d1, LinkState_d2;
    always @(cclk) begin
      LinkState_d1 &lt;= cache.cntrl.LinkState;
      LinkState_d2 &lt;= LinkState_d1;
    end
  endmodule
  </code></pre>
  <p>And the cache.cntrl.LinkState in the DUT is the output of a nonblocking assignment, so I would expect LinkState_d1 to simply follow LinkState from the DUT just delayed by one cycle. However in the waveform viewer I see LinkState_d1 is exactly matching LinkState as if it were a continuous assignment, here's the clock diagram of what I'm seeing in the waveform:</p>
  <pre><code>             __    __    __
  clk       __|  |__|  |__|  |__
                     ________
  LinkState    _____|
                     ________
  LinkState_d1 _____|
                           __
  LinkState_d2 ___________|
  </code></pre>
  <p>Is there something different that happens when we use a hierarchical reference in the RHS of a continuous assignment? Or is this just a simulator bug? I'm using questasim 2019.4</p>