title: Parameterized net width in Verilog
body: <p>Is something like this possible ?</p>
  
  <p><code>parameter width; wire[width-1] a_net = (width)'b0;</code></p>
  
  <p>I basically need a variable to control the width of the right hand side. I am planning to use this in an test bench where I just have to change the <code>parameter width at the beginning of the file</code>, and this parameter sets the net width in all other occurrences of <code>'a_net'</code>.</p>
  
  <p>If this doesn't work - is there any other workaround ? </p>
  
  <p>Thanks, Jim</p>