title: Verilog : syntax error : unexpected SYSTEM_IDENTIFIER on using $display
body: <p>My aim is to write a test fixture that reads hex values from an input file and displays it to the screen. I am using the below code but i am getting a syntax error at line " $display ("%d:%h",j,srcPacketIn[j]);". The exact error is :</p>
  
  <p>** Error: C:\altera\13.0\test.v(32): near "$display": syntax error, unexpected SYSTEM_IDENTIFIER</p>
  
  <p>Could anybody please help me out?</p>
  
  <pre><code>module test_fixtures;
  parameter TestCycles = 12;
  parameter ClockPeriod = 10;
  
  
  reg [7:0] srcPacketIn [0:(5*TestCycles)-1];
  
  reg clock, reset;
  genvar j;
  
  
  initial
      begin
          $readmemh("input.h",srcPacketIn);
      end
  initial
      begin
          reset = 0;
          clock = 1;
      end
  
  always #ClockPeriod clock = ~clock;
  
  
  
          for (j=0; j &lt; 59; j=j+1)
            begin
            $display ("%d:%h",j,srcPacketIn[j]);
          end
  endmodule
  </code></pre>