title: Output of a module used as input of another in verilog
body: <p>While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate. Is it possible to link an output and input like this?</p>
  
  <p>I've been reading around and found <a href="http://www.asic-world.com/images/verilog/ports.gif" rel="nofollow" title="Verilog Module Ports">this image</a> particularly helpful - however, I don't quite understand the concept of nets or if they will be helpful. Would wiring the output of module B to a reg that's used as input to module C work? Thanks.</p>
  
  <p>EDIT:</p>
  
  <p>I'm looking for something like <a href="http://puu.sh/4NL3O.png" rel="nofollow">this</a> (involving 3 different modules) where I'm instantiating a module B and a module C within a module A. I want to connect B's output to C's input.</p>