title: XOR outputs one because of propagaton delay in (basic) counter (FPGA)
body: <p>I have a basic counter example, counter is 6-bits wide.</p>
  
  <pre><code>reg[5:0] currcounterval_reg;
  always @(posedge clk_g0)
      currcounterval_reg &lt;= currcounterval_reg+ 1'b1; 
  </code></pre>
  
  <p>My constraints
  Clock is running at 83 Mhz 912ns period) on Virtex 7 chip.  The counter has no reset and the output is connected to board pins. When I run the circuit, I see switching in the signals as shown in the attached (hardware run) o/p. In the attached screenshot, if you look at the counter, after 7(seven), I should get '8'...but it first switches to '12'  as bit-2 goes to zero later than the others. I have an xor gate downstream where I compare o/p of two counters. How to I avoid getting into this problem?</p>
  
  <p>Whatever I do for constraining, it doesn't go away. Please help me with some strategies to remove the switching.</p>
  
  <p>Please feel free to ask me if you have more questions.</p>
  
  <p>You can find a my waveform here
  <a href="http://i.imgur.com/btEMiFD.png?1" rel="nofollow">http://i.imgur.com/btEMiFD.png?1</a></p>
  
  <p>Thanks.</p>