title: system verilog - implementation of randomize()
body: <p>I have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn't support this function.</p>
  
  <p>I implemented a basic function in a class with the following member:</p>
  
  <pre><code>   bit [15:0]  data_xi;
     bit [15:0]  data_xq;
  </code></pre>
  
  <p>the basic random function:</p>
  
  <pre><code>   //function my_randomize
     function int my_randomize(int seed);
         int temp1, temp2;
         temp1 = (($urandom(seed)) + 1);
         data_xi = temp1 - 1;
         temp2 = (($urandom(seed)) + 1);
         data_xq = temp2 - 1;
         if(temp1 != 0 || temp2 != 0 )
           return 1;
         else
           return 0;
     endfunction: my_randomize
  </code></pre>
  
  <p>Now I have to change it to static function which suppose to behave like randomize() with constraints.</p>
  
  <p>How can I implement this?</p>