title: Assigning values in Verilog: difference between assign, <= and =
body: <p>I have just started learning Verilog and I've seen these three lines from different sources. I am confused about the difference between the three:</p>
  
  <ol>
  <li>c &lt;= a&b;</li>
  <li>assign c = ~a;</li>
  <li>c = 1'b0;</li>
  </ol>
  
  <p>These lines seem to assign a value to c but what's the difference? Thanks.</p>