title: vivado: unused sequential element was removed
body: <p>Let's suppose I have the following VHDL code that i'm synthesizing with Vivado:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  entity example1 is
      port (
          aclk     :in  std_logic; 
          aresetn  :in  std_logic; 
  
          ren      :in  std_logic; 
          wen      :in  std_logic;         
          count    :out std_logic_vector(7 downto 0)
      );
  end entity;
  
  architecture rtl of example1 is
     signal reg_count :unsigned(7 downto 0);
     signal sel       :std_logic_vector(1 downto 0);
  
  begin
  
  count &lt;= std_logic_vector(reg_count);
  sel   &lt;= ren &amp; wen;
  
  process(aclk, aresetn)
  begin
      if (aresetn = '0') then
          reg_count     &lt;= (others =&gt; '0');
  
      elsif (rising_edge(aclk)) then
  
          case sel is        
          when "00"   =&gt; reg_count &lt;= reg_count;            
          when "01"   =&gt; reg_count &lt;= (reg_count + 1);            
          when "10"   =&gt; reg_count &lt;= (reg_count - 1);
          when "11"   =&gt; reg_count &lt;= reg_count;            
          when others =&gt; null;        
          end case;
      end if;
  end process;
  
  end architecture;
  </code></pre>
  
  <p>How can I modify the above code to prevent the following  synthesis warning messages:</p>
  
  <pre><code>[Synth 8-6014] Unused sequential element reg_count_reg was removed.
  </code></pre>
  
  <p>Should I take this warning message seriously?  I looks like its valid code sythesizable VHDL code to me.  </p>