title: Referencing a C code-defined macro within its makefile
body: <p>I'm writing some embedded firmware using C with arm-gcc and Eclipse.
  Within my code is a FW version number defined as a macro.
  I want to have that version appended to the build target file automatically.</p>
  
  <p>For the sake of the example, let's say this is my main.h file:</p>
  
  <pre class="lang-c prettyprint-override"><code>#ifndef MAIN_H__
  #define MAIN_H__
  
  #define FW_MAJOR_VERSION   1
  #define FW_MINOR_VERSION   0
  </code></pre>
  
  <p>and the makefile:</p>
  
  <pre><code>TARGET     := fw_release
  OUTPUT_DIR := out
  ...
  generate_pkg:
     @gen_pkg $(OUTPUT_DIR)/$(TARGET)_pkg.zip
  </code></pre>
  
  <p>where <code>gen_pkg</code> is some script to generate a firmware update package.</p>
  
  <p>This would generate a file path like this: <code>out/fw_release_pkg.zip</code></p>
  
  <p>Ideally, I would like something like this:</p>
  
  <pre><code>generate_pkg:
     @gen_pkg $(OUTPUT_DIR)/$(TARGET)_pkg_v$(FW_MAJOR_VERSION).$(FW_MINOR_VERSION).zip
  </code></pre>
  
  <p>which would generate a file path like this: <code>out/fw_release_pkg_v1.0.zip</code></p>
  
  <p>Now I know I can define the version within the makefile and reference that within the code (basically the other way around), but that has 2 problems:</p>
  
  <ol>
  <li><p>Every time I change the makefile it triggers a compilation of the entire code which takes a few minutes.</p></li>
  <li><p>I have two separate build configurations (release and debug), each using its own makefile, and that would require me to update the two separately.</p></li>
  </ol>