title: What is the difference between "wait until rising_edge(clk)" vs "if rising_edge(clk)"?
body: <p>I came across two styles of process statements in VHDL.</p>
  <pre><code>process(clk)
  begin
      if rising_edge(clk)
  ...do something...
  </code></pre>
  <p>The other one is</p>
  <pre><code>process
  begin
      wait until rising_edge(clk)
      ...do something...
  </code></pre>
  <p>What are the pros and cons of each method?</p>