title: In SystemVerilog, what does (.*) mean?
body: <p>I have a testbench declared as</p>
  
  <pre><code>module test_circuit
      logic a,b,c;
      logic y;
  
      circuit UUT (.*);    //what does this line mean?
  
      initial begin
      //something here
      end
  endmodule
  </code></pre>
  
  <p>I haven't found any tutorials which tell me what it means. I have looked at the language reference manual and it says it is a 'wildcard pattern', but doesn't go into enough detail. </p>
  
  <p>Otherwise... it is difficult to search special character in any search engine, and results which I found seem to only be related to other languages. </p>