title: How to generate an asynchronous reset verilog always blocks with chisel
body: <p>Chisel generate always blocks with only clock in sensivity list :</p>
  
  <pre><code>always @posedge(clk) begin
    [...]
  end
  </code></pre>
  
  <p>Is it possible to configure Module to use an asynchronous reset and generate an always block like this ?</p>
  
  <pre><code>always @(posedge clk or posedge reset) begin
     [...]
  end
  </code></pre>