title: Comparing bits from std_logic_vector
body: <p>attempt #1</p>
  
  <pre><code>overflow_next &lt;= (op1_shifted(word_width - 1) = op2(word_width - 1)) and (result_var(word_width - 1) /= op2(word_width - 1));
  </code></pre>
  
  <p>Error (10327): VHDL error at alu.vhd(99): can't determine definition of operator ""="" -- found 0 possible definitions</p>
  
  <p>Error (10327): VHDL error at alu.vhd(99): can't determine definition of operator ""/="" -- found 0 possible definitions</p>
  
  <p>attempt #2</p>
  
  <pre><code>overflow_next &lt;= ((op1_shifted(word_width - 1) = '0') and (op2(word_width - 1) = '0') and (result_var(word_width - 1) = '1')) or ((op1_shifted(word_width - 1) = '1') and (op2(word_width - 1) = '1') and (result_var(word_width - 1) = '0'));
  </code></pre>
  
  <p>Error (10327): VHDL error at alu.vhd(99): can't determine definition of operator ""="" -- found 0 possible definitions</p>
  
  <p>All signals and variables are std_logic_vector except word_width which is an integer generic. What's the problem here? I can compare standalone std_logic signals but not parts of std_logic_vector signals? Is there any workaround if what I'm trying to do is impossible?</p>