title: SystemVerilog Error: variable written by continuous and procedural assignments
body: <p>I want to create a test bench for my ALU circuit. When i compile it, i get some errors:</p>
  
  <pre><code>module ALU_TB();
  logic [7:0] A, B, w;
  logic [2:0] s, n;
  logic co, ci, si;
  wire ov, neg, zero, gt, eq;
  
  ALU alu8(A, B, s, si, ci, n, co, ov, zero, neg, gt, eq, w);
  assign A = 8'b10000000, B = 8'b0, s = 3'b0, ci = 1'b0, si = 1'b0, n = 3'b011;
  initial begin
    integer i;
      for (i = 0; i &lt; 7; i = i + 1) begin 
          s = s + 3'b001;
          repeat(8) #59 A = {A[0], A[7:1]};
          #59 B = 8'b10000000; A = 8'b01011010;
          repeat(8) #59 B = {~B[0], B[7:1]};
      end
  end
  endmodule
  </code></pre>
  
  <p>These are the compile errors for lines 12, 13, 14, 14, 15:</p>
  
  <blockquote>
    <p>** Error: (vlog-3838) variable 's' written by continuous and procedural assignments. </p>
    
    <p>** Error: (vlog-3838) variable'A' written by continuous and procedural assignments.</p>
    
    <p>** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.</p>
    
    <p>** Error: (vlog-3838) Variable 'A' written by continuous and procedural assignments.</p>
    
    <p>** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.</p>
  </blockquote>
  
  <p>What these errors mean?</p>