title: FPGA synthesizable verilog code with floating point numbers
body: <p>I'm trying to implement a linear programming problem on FPGA. I have used real data type to generate floating point numbers. The program compiled fine, but when I'm trying to synthesize it for my Xilinx Spartan-3E FPGA board it shows error that real is not supported by verilog. It seems that we cannot use real for synthesizable codes.
  So any suggestions on how to remove this error.</p>