title: OR all elements of a std_logic_vector with a flexible size
body: <p>I have a vector that has a configurable size like</p>
  
  <pre><code>signal a_vector : std_logic_vector(size-1 downto 0);
  </code></pre>
  
  <p>where <code>size</code> is defined in a configuration file. What I now would like to do is to OR all elements of <code>a_vector</code> into a separate <code>std_logic</code> in a way like</p>
  
  <pre><code>signal result : std_logic;
  result &lt;= a_vector(0) or a_vector(1) or ... or a_vector(size-1)
  </code></pre>
  
  <p>Is there a way to do this with a <code>GENERATE</code> statement, I couldn't figure that out.</p>
  
  <p>scary_jeff's answer works like a charm for the given problem. Is there a similar way if I'd have </p>
  
  <pre><code>type byte_array is array (0 to size) of std_logic_vector(7 downto 0);
  signal a_vector : byte_array;
  </code></pre>
  
  <p>and I'd like to have</p>
  
  <pre><code>result &lt;= a_vector(0)(1) or a_vector(1)(1) or ... or a_vector(size-1)(1);
  </code></pre>