title: Out of order UV pipelines
body: <p>Here is an example of out of order pipeline from "The Intel Microprocessor Family" by James Antonakos. </p>
  
  <p>Consider this sequence of instructions. The number of clock cycles assigned to each instruction is fabricated for this example.</p>
  
  <pre><code>1: MOV AL, 2       ; 1 cycle
  2: MOV DL, [SI]    ; 3 cycles
  3: MUL DL          ; 2 cycles
  4: INC SI          ; 1 cycle
  5: SUB BX, 4       ; 1 cycle
  6: ADD AX, BX      ; 1 cycle
  7: MOV CX, 2000    ; 1 cycle
  </code></pre>
  
  <p>Scheduling instructions <strong>in order</strong> between two pipelines: (I know the basic concept of this.)</p>
  
  <pre><code>Clock Cycle     Pipeline # 1       Pipeline # 2
  
  1                MOV AL, 5         MOV DL, [SI]
  2                idle              busy
  3                idle              busy
  4                MUL DL            INC SI
  5                busy              SUB BX, 4
  6                ADD AX, BX        MOV CX, 2000
  </code></pre>
  
  <p>Scheduling instructions <strong>out of order</strong> between two pipelines:</p>
  
  <pre><code>Clock Cycle     Pipeline # 1       Pipeline # 2
  
  1                MOV AL, 5         MOV DL, [SI]
  2                INC SI            SUB BX, 4
  3                MOV CX, 2000      busy
  4                MUL DL            idle
  5                ADD AX, BX        idle
  </code></pre>
  
  <p>Can someone explain to me how out of order pipeline is done? Thank you!</p>