title: How system software access PCIe configuration space during bus enumeration?
body: <p>I have some questions regarding OS accessing PCIe memory mapped configuration space during bus enumeration.</p>
  <p><a href="https://i.stack.imgur.com/xwUJH.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xwUJH.jpg" alt="enter image description here" /></a></p>
  <p>Above is a sample config space memory map. From the first glance, it seems that as long as the OS knows the Base Address of <code>MMConfig</code> region (via &quot;firmware&quot; such as Device Tree or ACPI), it's straight forward to access config space of any B/D/F combination. But after reading the enumeration process, it seems this is not that straightforward, since before bus enumeration, the OS even does not know how many devices exists in the system, let alone their B/D/F combination.</p>
  <p>I guess that, based on the assumptions that:</p>
  <ul>
  <li>the <code>Base Address</code> correctly reflects the bus address of the Root Complex (at hardware level);</li>
  <li>the Root Complex IP implements enough registers for configuration space of bus <code>0</code> (i.e., the first 1/256 portion of the MMConfig space), since,
  <ul>
  <li>it knows how many bridges and/or embedded EPs are integrated into it;</li>
  <li>its internal bus number is usually hardcoded as <code>0</code>;</li>
  </ul>
  </li>
  </ul>
  <p>then the OS can at least access config space on bus <code>0</code>. But how OS access the configuraiton space beyond bus <code>0</code>? I guess that it's the Root Complex who &quot;translates&quot; the MMIO access from CPU to the target device downstream <em>somehow</em>, but I would like to know some details regarding that.</p>