title: SystemVerilog error with queue insert w/ another queue as argument
body: <p>I have some queues declared like so:</p>
  
  <pre><code>static bit [127:0]   same_addr_mem_model [int][$]; 
  static bit [127:0]   temp_addr_mem_model [int][$];
  </code></pre>
  
  <p>Then later on the line of code:</p>
  
  <pre><code>same_addr_mem_model[write_addr].insert(0,temp_addr_mem_model[write_addr]); // write_addr is some int
  </code></pre>
  
  <p>And that line gives me the compiler error with Cadence IES:</p>
  
  <blockquote>
    <p>assignment operator type check failed (expecting datatype compatible with 'packed array' but found 'queue of packed array [127:0] of bit' instead).</p>
  </blockquote>
  
  <p>But as I've found documentation online it looks like a queue is a perfectly valid argument for <code>insert()</code>. Any idea what is wrong here? This code compiles and runs with Synopsys VCS, by the way.</p>