title: Parsing error in VHDL
body: <p>I am having this problem in coding 3bit counter with JK flip flops, and I happen to have an error in 34 line, which is written automatically, by XILINX VHDL, so I am confused in what is actually wrong. </p>
  
  <pre><code>    LIBRARY ieee;
      USE ieee.std_logic_1164.ALL;
      USE ieee.std_logic_unsigned.all;
      USE ieee.numeric_std.ALL;
  
      ENTITY 3bitBrojacTest_vhd IS
      END 3bitBrojacTest_vhd;
  
      ARCHITECTURE behavior OF 3bitBrojacTest_vhd IS 
  
  -- Component Declaration for the Unit Under Test (UUT)
  COMPONENT Asinhroni3BitBrojacModule
  PORT(
      Clk : IN std_logic;
      High : IN std_logic;       
      Q0 : INOUT std_logic;
      Q1 : INOUT std_logic;
      Q2 : INOUT std_logic;
      Q2neg : INOUT std_logic
      );
  END COMPONENT;
  
  --Inputs
  SIGNAL Clk :  std_logic := '0';
  SIGNAL High :  std_logic := '0';
  
  --BiDirs
  SIGNAL Q0 :  std_logic;
  SIGNAL Q1 :  std_logic;
  SIGNAL Q2 :  std_logic;
  SIGNAL Q2neg :  std_logic;
  
      BEGIN
  
  -- Instantiate the Unit Under Test (UUT)
  uut: Asinhroni3BitBrojacModule PORT MAP(
      Clk =&gt; Clk,
      High =&gt; High,
      Q0 =&gt; Q0,
      Q1 =&gt; Q1,
      Q2 =&gt; Q2,
      Q2neg =&gt; Q2neg
  );
  
  clk_proc: process
  begin
      Clk &lt;= '1';
      wait for 10ns;
      Clk &lt;= '0';
  wait for 10ns;
  end process;
  
  
  tb : PROCESS
  BEGIN
  
      -- Wait 100 ns for global reset to finish
      wait for 100ns;
      High &lt;= '1';
      wait for 160ns;
      High &lt;= '0';
  
      wait; -- will wait forever
  END PROCESS;
  
      END;
  </code></pre>
  
  <p>So, the error says:</p>
  
  <p>ERROR:HDLParsers:164 - Line 34. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER
  Parsing "3bitBrojacTest_vhd_stx.prj": 1.27</p>
  
  <p>If anyone knows how to fix this I'd be really happy to get that answer from. 
  Thanks guys!</p>