title: Is event trigger synthesizable in verilog?
body: <p>I am trying to use event triggering in my code (->). Will this get synthesized? </p>
  
  <pre><code>always @(posedge clk) begin
  count &lt;= count + 1;
  -&gt; x;
  end
  
  always @(x) flag = 1;
  </code></pre>
  
  <p>This is just a sample code. What i want to do is when ever there is an event in the count I want to make the flag high, else it should remain low. In my case the count value increases after every 7 clock cycles. Can i use event triggering for this? If not what can I do to meet my requirement?</p>