title: Using a continous assignment in a Verilog procedure?
body: <p>Is it possible and/or useful to ever use a continuous assignment in a Verilog procedure?  For example, would there ever be any reason to put an <code>assign</code> inside of an <code>always</code> block?  </p>
  
  <p>For example this code:</p>
  
  <pre><code>always @(*) 
  begin 
    assign data_in = Data;
  end
  </code></pre>
  
  <p>Furthermore would it be possible to generate sequential logic with this approach?</p>
  
  <pre><code>always @(posedge clk) 
  begin 
    assign data_in = Data;
  end
  </code></pre>