title: Register Design in VHDL
body: <p>I'm having some troubles in designing a 1-bit and 32-bit register in VHDL. Main inputs of the register include clock (clk), clear (clr), load/enable(ld) signals and an n-bit data (d).
  The n-bit output is denoted by (q). So far I believe to have made a 1-bit register, here is my code:</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.std_logic_arith.ALL;
  USE ieee.std_logic_unsigned.ALL;
  ENTITY register32 IS
  PORT(
  d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- input.
  ld : IN STD_LOGIC; -- load/enable.
  clr : IN STD_LOGIC; -- async. clear.
  clk : IN STD_LOGIC; -- clock.
  q : OUT STD_LOGIC; -- output.
  END register32;
  ARCHITECTURE description OF register32 IS
  
  BEGIN
  
   process(clk, clr, ld)
     begin
        if clr = '1' then 
           q &lt;= '0';
        elsif d = '1' and ld = 1 and clk'event and clk='1' then
           q &lt;= '1';
        elsif d = '0' and ld = 1 and clk'event and clk='1' then
           q &lt;= '0';
        else
           q &lt;= '0';
        end if;
     end process;
  END description;
  </code></pre>
  
  <p>If this is correct for a 1-bit register, how would I make it into a 32 bit one. Some help would be greatly appreciated.</p>