title: How do I sign extend in SystemVerilog?
body: <p>Below is the code I have for my module:</p>
  
  <pre><code>module sext(input in[3:0], output out[7:0]);
  
      always_comb
          begin
              if(in[3]==1'b0)
                  assign out = {4'b0000,in};
              else
                  assign out = {4'b1111,in};
          end
  
  endmodule
  </code></pre>
  
  <p>For some reason this is not working. Instead of sign extending it is zero extending. Any ideas to why this might be the case?</p>