title: Using new variables inside Makefile loops
body: <p>After messing about with foreach loops, eval, and various combinations of dollar signs, brackets, semicolons and whatnot, I finally ended up getting the result I wanted with a bunch of shell commands within a Makefile.</p>
  
  <p>I have a directory structure:</p>
  
  <blockquote>
    <p>> . <br> > ./Makefile <br> > ./source
    <br> > ./source/a <br> > ./source/b <br> > ./source/c</p>
  </blockquote>
  
  <p>And a Makefile:</p>
  
  <pre><code>WORKDIR?=$(shell pwd)/builddir_$(SRCDIR)
  
  all: copy_sources test_var
  
  copy_sources:
      mkdir $(WORKDIR)
      mkdir $(WORKDIR)/logs
      @rsync -paqhC $(SRCDIR) $(WORKDIR)/
  
  test_var:
      cd $(WORKDIR)
      for TESTDIR in $(wildcard $(WORKDIR)/$(SRCDIR)/*); do \
          cd $$TESTDIR ; \
          TESTNAME=`basename $$TESTDIR`; \
          touch file_$${TESTNAME}_out.txt; \
          echo "done $${TESTNAME}" &gt; $(WORKDIR)/logs/$${TESTNAME}.log; \
          cd $(WORKDIR); \
      done
  </code></pre>
  
  <p>which I invoke with:</p>
  
  <blockquote>
    <p>make all SRCDIR=source</p>
  </blockquote>
  
  <p>It seems a bit convoluted, so I'm wondering if there's a way to do this using Makefile syntax instead of passing it all to the shell. I particularly had difficulty with assigning the basename to a variable and then using that variable.</p>