title: Why is the constant memory size limited in CUDA?
body: <p>According to <a href="http://developer.download.nvidia.com/compute/DevZone/docs/html/C/doc/CUDA_C_Programming_Guide.pdf" rel="noreferrer">&quot;CUDA C Programming Guide&quot;</a>, a constant memory access benefits only if a multiprocessor constant cache is hit (Section 5.3.2.4)<sup>1</sup>. Otherwise there can be even more memory requests for a half-warp than in case of the coalesced global memory read. So why the constant memory size is limited to 64 KB?</p>
  <p>One more question in order not to ask twice. As far as I understand, in the Fermi architecture the texture cache is combined with the L2 cache. Does texture usage still make sense or the global memory reads are cached in the same manner?</p>
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  <blockquote>
  <p><sup>1</sup><strong>Constant Memory (Section 5.3.2.4)</strong></p>
  <p>The constant memory space resides in device memory and is cached in the constant cache mentioned in Sections F.3.1 and F.4.1.</p>
  <p>For devices of compute capability 1.x, a constant memory request for a warp is first split into two requests, one for each half-warp, that are issued independently.</p>
  <p>A request is then split into as many separate requests as there are different memory addresses in the initial request, decreasing throughput by a factor equal to the number of separate requests.</p>
  <p>The resulting requests are then serviced at the throughput of the constant cache in case of a cache hit, or at the throughput of device memory otherwise.</p>
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