title: Xilinx:Reading from BRAM
body: <p>I have attemted to write a  Minimal, Complete, and Verifiable example below.</p>
  
  <p>I want to write 10 values to the first 10 addresses of the BRAM (single port Block RAM) and then read the values. After inspecting the results I find that </p>
  
  <ul>
  <li>there are no changes in the first 10 addresses while perfoming the write operation.</li>
  <li>While reading, the output changes after 3 clock cycles and stays constant when the 'address' signal stops changing.</li>
  </ul>
  
  <p>Can you give an explanation to this behaviour and how to get the desired result (write 10 values in the 10 addresses). I'm more interested in solving the second problem (reading the values from the first 10 addresses).</p>
  
  <p>Below is my verilog testbench and snapshot of the waveguide.</p>
  
  <pre><code>module BRAM_tb;
      // Inputs
      reg clk;
      reg [3:0] wea;                  // write enable signal
      reg [31:0] addra;               // address
      reg signed [31:0] dina;     // data in
  
      // Outputs
      wire [31:0] douta;          // data out
  
      // Instantiate the Unit Under Test (UUT)
      BLOCK_MEM uut (
          .clka(clk), 
          .wea(wea), 
          .addra(addra), 
          .dina(dina), 
          .douta(douta)
      );
  
      always begin
          #15 clk =~clk;
      end
  
      task writeStuff;    //write to address
          begin
              addra &lt;= addra + 1;
              dina &lt;= dina+1;
          end
      endtask
  
      task readStuff; // read the at address
          begin
              addra &lt;= addra + 1;
          end
      endtask
  
      reg [1:0] writing;
      integer counter;
      initial begin
          // Initialize Inputs
          clk = 0;
          addra = 0;
          dina = 16;
          counter = 0;
          writing = 2'b10; //idle state
          // Wait 100 ns for global reset to finish
          #100;
          wea &lt;= 1;
          writing &lt;=1;
      end
  
      always @(posedge clk)begin
          case(writing)
              1: if(counter&lt;10) begin
                      writeStuff;
                      counter &lt;=counter+1;
                  end else begin
                      writing &lt;=0;    // change state to reading
                      counter &lt;=0;
                      addra &lt;= 0;
                      wea &lt;=0;    // stop writing
                  end
              0:  if(counter&lt;10) begin
                      readStuff;
                      counter &lt;=counter+1;
                  end else begin // change addra to zero and do nothing
                      addra &lt;= 0;
                      writing &lt;=2'b10; //goto idle state
                  end
              2: if(1) begin
                      //do nothing
                  end
          endcase
      end
  </code></pre>
  
  <p><img src="https://ibin.co/2cqCtoVhFvCV.jpg" alt="BRAM">
  - The gray line is where the write operation begins.
  The blue line is where the read operation begins.</p>
  
  <p><img src="https://ibin.co/2cqDr8RGgCjf.jpg" alt="BRAM_2"></p>
  
  <p><a href="https://www.dropbox.com/sh/cczby8trjezmed8/AABBlzagSOpTKs5_0Kr56QODa?dl=0" rel="nofollow">BLOCK_MEM</a> is an IP-CORE that is generated by Xilinx.</p>