title: how to solve 4 bit full adder verilog
body: <p>I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the simulation.It give me z and x output.Which part of code I have to change to get an output in simulation</p>
  
  <pre><code>module my_full_adder( input A,
         input B,
         input CIN,
         output S,
         output COUT
         );
         assign S = A^B^CIN;
         assign COUT = (A&amp;B) | (CIN&amp;(A^B));
  
  endmodule
  </code></pre>
  
  <p>This is the one bit full adder verilog code</p>
  
  <p>I have check the schematic for this code and everything is correct.</p>
  
  <pre><code>module four_bit_adder( 
      input [3:0] A,
      input [3:0] B,
      input C0,
      output [3:0] S,
      output C4
      );
      wire C1,C2,C3;
  
      my_full_adder fa0 (A[0],B[0],C0,S[0],C1);
      my_full_adder fa1 (A[1],B[1],C1,S[1],C2);
      my_full_adder fa2 (A[2],B[2],C2,S[2],C3);
      my_full_adder fa3 (A[3],B[3],C3,S[3],C4);
  
  
  endmodule
  </code></pre>
  
  <blockquote>
    <h2>Test bench</h2>
  </blockquote>
  
  <pre><code>module test_4_bit(
  
      );
       reg [3:0] A;
       reg [3:0] B;
       reg C0;
       wire [3:0] S;
       wire C4;
       four_bit_adder dut(A,B,C0,S,C4);    
       initial begin
       A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
       A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
       A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
       end
  
  endmodule
  </code></pre>