title: Non-specific `include file name - System Verilog compiler directives
body: <p>I want to use the `include directive to call upon a non-specific file name. For example,
  there is this file name "name_defines.svh" in some other directory. Since the "name" of "name_defines.svh" changes(it can be eg, a_defines.svh, b_defines.svh.. etc), is it possible if I just use</p>
  
  <pre><code>`include "_defines.svh"
  </code></pre>
  
  <p>or</p>
  
  <pre><code>`include "*_defines.svh"
  </code></pre>
  
  <p>so that the system verilog compiler finds the file name and include it in my current .sv file, just as if I used</p>
  
  <pre><code>`include "name_defines.svh"
  </code></pre>
  
  <p>p.s. - assume that no other files in the working directory has the trailing  "_defines.svh" wordings and is unique to only "name_defines.svh"</p>