title: What is the use of transport in VHDL?
body: <p>I have seen an example written in a VHDL file</p>
  
  <p>Example snippet,</p>
  
  <pre><code>architecture  aaa of bbb is
  signal   ccc : std_logic
  
  begin
  
  ccc &lt;= transport global_en_lb;
  
  ....
  </code></pre>
  
  <p>I just want to know about transport in the above snippet.
  What does it means?</p>