title: Set Makefile variable inside target
body: <p>I have a target inside a makefile:</p>
  
  <pre><code>all: $(TARGETS)
  </code></pre>
  
  <p>I want a variant that differs from <code>all</code> only by the fact that it sets an environment variable. Something like:</p>
  
  <pre><code>all-abc: $(TARGETS)
      ABC=123
  </code></pre>
  
  <p>but that doesn't work because the dependencies are processed before the variable is set. I've thought about having another dependency before the real ones that just sets the environment variable but I don't think the environment persists across targets. That is to say that</p>
  
  <pre><code>abc:
      ABC=123
  all-abc: abc $(TARGETS)
  </code></pre>
  
  <p>doesn't work. What I ultimately want to be able to do is </p>
  
  <pre><code>$ make all-abc
  </code></pre>
  
  <p>instead of</p>
  
  <pre><code>$ ABC=123 make
  </code></pre>
  
  <p>Is it possible to set an environment variable like this ?</p>
  
  <p>(GNU Make 3.82)</p>