title: Input data is not being loaded into registers - issues only in post-synthesis timing simulation [VHDL][Vivado] (SOLVED)
body: <p><strong>What this is</strong></p>
  <p>I'm trying to create a simple FIR filter. What I'm going to present you may not exactly be a FIR filter as I'm gradually increasing complexity of my project for educational purpouses till it reaches desired functionality.</p>
  <p><strong>What it should be doing</strong></p>
  <p>Basically what it should be doing so far:</p>
  <ul>
  <li>load data to registers after applying load = 1,</li>
  <li>unload processed data (which is product of multiplication of samples with corresponding coefficients) after applying start = 1.</li>
  </ul>
  <p><strong>Where it fails</strong></p>
  <p>However from what I've noticed it fails to load data into registers. Seems to be working like a latch, as after <em>load</em> drops to 0, the last vector value at input port is being latched in the registers. But I may be wrong, it just appears to be working like this in simulation.
  <strong>Pre- and post-synthesis functional simulation is working! Only the post-synthesis timing is failing to work as desired!</strong></p>
  <p><strong>What I've tried</strong></p>
  <ul>
  <li>Adding DONT_TOUCH parameter to entity declaration in its .vhd file,</li>
  <li>Adding kind of buffer (unsigned variable) after data_in port from which the data is being transfered to  registers - but it did not even appear in schematic after synthesis, maybe the DONT_TOUCH did not work?</li>
  </ul>
  <p><strong>Simulations pictures</strong></p>
  <p>Pre-synth functional - <a href="https://imgur.com/0TaNQyn" rel="nofollow noreferrer">https://imgur.com/0TaNQyn</a></p>
  <p>Post-synth timing - <a href="https://imgur.com/mEOv67t" rel="nofollow noreferrer">https://imgur.com/mEOv67t</a></p>
  <p><strong>Program</strong></p>
  <p>I'm using Vivado 2020.2 webpack</p>
  <p><strong>Testbench</strong></p>
  <p>Testbench code here: <a href="https://pastebin.pl/view/d2f9a4ad" rel="nofollow noreferrer">https://pastebin.pl/view/d2f9a4ad</a></p>
  <p><strong>Main code</strong></p>
  <pre class="lang-vhdl prettyprint-override"><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.numeric_std.ALL;
  
  entity fir is
   Port ( 
   clk: in std_logic;
   data_in: in unsigned(7 downto 0);
   data_out: out unsigned(7 downto 0);
   en: in std_logic;
   load: in std_logic;
   start: in std_logic;
   reset: in std_logic
   );
  end fir;
  
  architecture Behavioral of fir is
  
  -- type coeff_array is array (0 to 7) of integer range 0 to 255;
  constant reg_size: integer := 8;
  constant filter_order: integer := 7;
  
  type samples_reg is array (0 to reg_size-1) of unsigned(7 downto 0);
  type coeffs_reg is array (0 to filter_order) of unsigned(7 downto 0);
  
  
  begin
  
  process(clk, reset)
       
      -- variable coeffs: coeff_array := (0,0,0,0,0,0,0,0);
      --variable b0: unsigned(7 downto 0) := 8D&quot;0&quot;;
      variable b0: unsigned(7 downto 0) := to_unsigned(1,8);
      variable b1: unsigned(7 downto 0) := to_unsigned(2,8);
      variable b2: unsigned(7 downto 0) := to_unsigned(3,8);
      variable b3: unsigned(7 downto 0) := to_unsigned(4,8);
      variable b4: unsigned(7 downto 0) := to_unsigned(5,8);
      variable b5: unsigned(7 downto 0) := to_unsigned(6,8);
      variable b6: unsigned(7 downto 0) := to_unsigned(7,8);
      variable b7: unsigned(7 downto 0) := to_unsigned(8,8);
      
      variable i: integer range 0 to reg_size := 0;
      
      variable samples: samples_reg := (others =&gt; (others =&gt; '0'));
      variable coeffs: coeffs_reg := (b0,b1,b2,b3,b4,b5,b6,b7);
      
      variable data_processed: unsigned(15 downto 0) := (others =&gt; '0');
      
         
      
      
      -- variable reg_element:
      
      -- signal s1 : signed(47 downto 0) := 48D&quot;46137344123&quot;;
      
      begin    
      
      if reset = '1' then
          -- data_out &lt;= (others =&gt; '0');
          samples := (others =&gt; (others =&gt; '0'));
          data_processed := (others =&gt; '0');
          i := 0;            
  
      -- synch part
      elsif rising_edge(clk) and en = '1' then
      
      samples := samples;
          
          -- loading data
          if load = '1' then
              samples(i) := data_in;
              
              i := i+1;
          else null;
          end if;                      
          
          -- deloading data
          if start = '1' then
              
          data_processed := samples(i)*coeffs(i);
          i := i+1;
          else null; 
          end if;
              
          -- reset counter after overflow
          if(i = reg_size) then
              i := 0;
          else null;
          end if;
          
          -- reset counter if no data is being transferred
          if load = '0' and start = '0' then
              i := 0;
              data_processed := (others =&gt; '0');
          else null;
          end if;    
                      
      end if;
      
      data_out &lt;= data_processed(7 downto 0);
      
   end process;
  
  
  end Behavioral;
  </code></pre>
  <p><strong>Other info</strong></p>
  <ul>
  <li>I just noticed that I'm holding load = 1 for one excessive cycle, which is why the highest number appears first.</li>
  <li>The coefficients are: 1, 2, 3, 4, 5, 6, 7, 8.</li>
  <li>In post-synth simulations after peeking into UUT, I've noticed that the samples registers are not loading the data (except for the last one, as I've mentioned earlier), the <em>i</em> is incrementing and the rest appears to be working properly.</li>
  <li>I'll be happy to hear about some improvements for my code in addition to the problem solution!</li>
  </ul>