title: VHDL Counter result giving X
body: <p>I am attempting to build a counter in VHDL. Eventual goal is to hook the "do_count" to a button. The total will be converted to BCD and displayed on a 7-segment display. Push the button, watch the numbers increment.</p>
  
  <p>I'm using ModelSim and I can see the internal "counter_value" correctly increment by 1. But the output signal "total" becomes "000X" then "00X0" during my two test "do_count"s. Why am I getting an X'd signal? </p>
  
  <p>I've moved the "output &lt;= current_value" around inside the process, outside the process, inside the 'if's, etc. Still the "000X".  </p>
  
  <p>I've tried using a variable 'tmp' inside the process.</p>
  
  <pre><code>count_up : process(clk) is
     variable tmp : unsigned (15 downto 0 );
  begin
     tmp := current_value;
     -- snip
     if do_count='1' then
        current_value &lt;= tmp + to_unsigned(1,16);
     end if;
  </code></pre>
  
  <p>Still I get the "000X".  </p>
  
  <p>Full code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.numeric_std.all;
  
  entity d_counter is
      port ( rst : in std_logic;
             clk : in std_logic;
             do_count : in std_logic;
             total : out unsigned (15 downto 0)
          );
    end entity d_counter;
  
  architecture counter_arch of d_counter is
    signal current_value : unsigned (15 downto 0) := (others=&gt;'0');
  begin
    count_up : process(clk) is
    begin
      if rst='1' then
        current_value &lt;= (others=&gt;'0');
        total &lt;= (others=&gt;'0');
      elsif rising_edge(clk) then
        if do_count='1' then
          current_value &lt;= current_value + to_unsigned(1,16);
        end if;
      end if;
    end process count_up;
    total &lt;= current_value;
  end architecture counter_arch;
  </code></pre>
  
  <p>Testbench:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.numeric_std.all;
  
  entity test_counter is 
    begin
    end entity test_counter;
  
  architecture run_test_counter of test_counter is
  
    signal t_rst : std_logic := '1';
    signal t_clk : std_logic := '0';
    signal t_do_count : std_logic;
    signal t_total : unsigned( 15 downto 0 );
  
    component d_counter is
      port ( rst : in std_logic;
             clk : in std_logic;
             do_count : in std_logic;
             total : out unsigned( 15 downto 0 )
          );
    end component d_counter;
  
  begin
    uut : d_counter
      port map( rst =&gt; t_rst,
        clk =&gt; t_clk,
        do_count =&gt; t_do_count,
        total =&gt; t_total );
  
      clock : process is 
      begin
  
          t_clk &lt;= '0'; wait for 10 ns;
          t_clk &lt;= '1'; wait for 10 ns;
      end process clock;
  
      stimulus : process is
      begin
        t_rst &lt;= '1';
        t_do_count &lt;= '0';
        t_total &lt;= (others =&gt;'0');
        wait for 15 ns;
  
        t_rst &lt;= '0';
        wait for 10 ns;
  
        t_do_count &lt;= '1';
        wait for 10 ns;
  
        t_do_count &lt;= '0';
        wait for 10 ns;
  
        t_do_count &lt;= '1';
        wait for 10 ns;
  
        t_do_count &lt;= '0';
        wait for 10 ns;
  
        wait;
  
      end process stimulus;
  end architecture run_test_counter;
  </code></pre>
  
  <p>Update 03-Oct-2012.
  BOTH the answers helped. Moving "total &lt;= current_value" inside the process (From @simon) and removing the extra "t_total &lt;= (others =>'0');" (From @peter-bennett) in my testbench was required. I had to do both to get rid of the X's. </p>