title: L1 caches usually have split design, but L2, L3 caches have unified design, why?
body: <p>I was reading the pros and cons of split design vs unified design of caches in <a href="https://stackoverflow.com/questions/55752699/what-does-a-split-cache-means-and-how-is-it-usefulif-it-is#:%7E:text=Unified%20L1%20Cache%20Partitioning&amp;text=mentioned%20in%20their%201974%20paper,cache%20between%20instructions%20and%20data.&amp;text=However%2C%20the%20combined%20impact%20on,one%20with%20the%20split%20cache.">this</a> thread.</p>
  <p>Based on my understanding the <strong>primary advantage of the split design</strong> is: <em>The split design enables us to place the instruction cache close to the instruction fetch unit and the data cache close to the memory unit, thereby simultaneously reducing the latencies of both.</em> And the <strong>primary disadvantage</strong> is: <em>Combined space of the instruction and data caches may not be efficiently utilized. Simulations have shown that a unified cache of the same total size has a higher hit rate.</em></p>
  <p>I, however, couldn't find an intuitive answer to the question &quot;Why (at-least in most modern processors) L1 caches follow the split design, but the L2/L3 caches follow the unified design.)&quot;</p>