title: Initializing arrays in Verilog
body: <p>How do I initialize the array Save_state? This statement is giving X value at the output:</p>
  
  <pre><code>reg [9:0] count 
   reg [9:0] Save_state [0: 1024]; 
  
   always @ (posedge Clock )
   Count &lt;=count+1 ;
   Save_state[count] &lt;=count ;
  </code></pre>