title: Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE Error in Modelmsim
body: <p>I am getting the following error : Warning: NUMERIC_STD."&lt;=": metavalue detected, returning FALSE, in Modelsim when I run my code. </p>
  
  <p>The error only happens when i am using reg_go and reg_n registers. If do not use the registers, the code works fine.</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  use work.config_pkg.all;
  use work.user_pkg.all;
  
  entity memory_map is
  port (
      clk     : in  std_logic;
      rst     : in  std_logic;
      wr_en   : in  std_logic;
      wr_addr : in  std_logic_vector(MMAP_ADDR_RANGE);
      wr_data : in  std_logic_vector(MMAP_DATA_RANGE);
      rd_en   : in  std_logic;
      rd_addr : in  std_logic_vector(MMAP_ADDR_RANGE);
      rd_data : out std_logic_vector(MMAP_DATA_RANGE);
  
      -- application-specific I/O
      go     : out std_logic;
      n      : out std_logic_vector(31 downto 0);
      result : in  std_logic_vector(31 downto 0);
      done   : in  std_logic
      );
  end memory_map;
  
  architecture BHV of memory_map is
  signal reg_go, reg_go1     :  std_logic;
  signal reg_n      :  std_logic_vector(31 downto 0);
  begin
  
  process(clk,rst)
  
  begin
  
  
      if(rst = '1') then
          reg_go &lt;= '0';
          reg_go &lt;= '0';
          reg_n &lt;= (others =&gt; '0');
          rd_data &lt;= (others =&gt; '0');
  
      elsif(clk'event and clk = '1') then
  
          if(wr_en='1') then
  
              if(wr_addr=std_logic_vector(to_unsigned(C_GO_ADDR,C_MMAP_ADDR_WIDTH))) then
  
                      reg_go &lt;= wr_data(0);
                      reg_go1 &lt;= '1';
  
              elsif(wr_addr=std_logic_vector(to_unsigned(C_N_ADDR,C_MMAP_ADDR_WIDTH))) then
                      reg_n &lt;=wr_data;
  
  
              end if;
          end if;
  
          reg_go1 &lt;= '0';
  
          if(rd_en='1') then
              if(rd_addr=std_logic_vector(to_unsigned( C_RESULT_ADDR,C_MMAP_ADDR_WIDTH))) then
                  rd_data &lt;= result;
              elsif(rd_addr=std_logic_vector(to_unsigned(C_DONE_ADDR,C_MMAP_ADDR_WIDTH))) then
  
                  rd_data(0) &lt;= done;
  
              end if;
          end if;
      end if;
  
  end process;
  
  
  
  go &lt;= reg_go and reg_go1;
  n  &lt;= reg_n;
  
  
  
  
  
  end BHV;
  </code></pre>