title: Can't manage to solve error ,VHDL, syntax error but I don't see it
body: <p>I can't manage to solve the error in this multiplier. I am new in VHDL so it may be a very stupid question(I tried to fix the problem but it didn't seems like i've succeded) it says: <code>Error: C:/modeltech_6.5/examples/pipe.vhd(41): near "label": syntax error</code></p>
  
  <p>I am trying to make a pipeline multiplier for my project</p>
  
  <pre><code>entity  mult_secv  is 
    generic(
      Na    : integer := 8;
      Nb    : integer := 8;
      Nscnt : integer := 4
     );
    port(
      iCLK  : in std_logic;
      iRST    : in std_logic;
      iDV   : in std_logic;
  
      ia      : in std_logic_vector(Na-1 downto 0);
      ib      : in std_logic_vector(Nb-1 downto 0);
  
      oDV     : out std_logic;
      oDATA   : out std_logic_vector(Na+Nb-2 downto 0)
      );
  end  mult_secv;
  
  architecture produs of mult_secv is
    type my_array1 is array(1 to 8)of std_logic_vector(Na+Nb-2 downto 0);
    type my_array2 is array(1 to 8) of std_logic_vector(Nb-1 downto 0);
    type my_array3 is  array(1 to 8) of std_logic;
  --8 stagii pentru a se calcula tot produsul
    signal sa, srez : my_array1;   
    signal sb : my_array2;
    signal dv : my_array3;
    constant scntmax : integer:=8 ;
  
  begin
    -- for each pipeline stage
  label : for scnt in 1 to scntmax generate ---&gt; CAUTA SINTAXA PENTRU GENERARE DE COMPONENTE IDENTICE
  
  process(iCLK,iRST)
  begin
    if iRST= '1' then
      sa &lt;= (others =&gt; (others =&gt; '0'));
    elsif rising_edge(iCLK) then
      -- first stage
      if (scnt = 1) then
        sa(scnt) &lt;= (Na+Nb-2 downto Na =&gt; ia(Na-1))  &amp; ia; ---se bordeaza cu bitul de semn daca e negativ
      -- other stages
      else
        sa(scnt) &lt;= sa(scnt-1)(Na+Nb-3 downto 0) &amp; '0';  --altfel se shifteaza sa
      end if;
    end if;
  end process;
  
  
  process(iCLK,iRST)
  begin
    if iRST='1' then
      sb &lt;= (others =&gt; (others =&gt; '0'));   
    elsif rising_edge(iCLK) then
      if (scnt = 1) then
        sb(scnt) &lt;= ib;
      else
        sb(scnt) &lt;= '0' &amp; sb(scnt-1)(Nb-1 downto 1); --se shifteaza sb
      end if;
    end if;
  end process;
  
  process(iCLK,iRST)
  begin
    if iRST='1' then
      srez &lt;= (others =&gt; (others =&gt; '0'));  
    elsif rising_edge(iCLK) then
      if (scnt = 1) then
        if ib(Nb-1)='1' then
     srez(scnt) &lt;= not (ia &amp; (Nb-2 downto 0 =&gt; '0')) + '1'; --daca este negativ
        else
          srez(scnt) &lt;= (others =&gt; '0'); --in primul stadiu
        end if;
      elsif sb(scnt-1)(0)='1' then        
        srez(scnt) &lt;= srez(scnt-1)+sa(scnt-1);
      else    
        srez(scnt) &lt;= srez(scnt-1);
      end if;
    end if;
  end process;    
  
  process(iCLK,iRST)
  begin
    if iRST='1' then
      dv &lt;= (others =&gt; '0');
    elsif rising_edge(iCLK) then
      if (scnt = 1) then
        dv(scnt) &lt;= iDV;
      else
        dv(scnt) &lt;= dv(scnt-1);
      end if;
    end if;
  end process;
  
  end generate label;
  
  oDATA &lt;= srez(scntmax);
  oDv &lt;= dv(scntmax);
  
  end;
  </code></pre>
  
  <p>Can anyone help?</p>