title: Verilog OR of array elements
body: <p>I want to OR a parameterized number of 32-bit buses as follows:
  out_bus = bus1 | bus2 | bus 3 | ... | bus N;</p>
  
  <p>I also want to declare the buses as an array (N is a fixed parameter, defined at compile time):</p>
  
  <p>reg [31:0] bus[N-1:0];</p>
  
  <p>The best I can figure how to do this is something like this:</p>
  
  <pre><code>parameter N;
  reg [N-1:0] temp;
  reg [31:0] out_bus;
  reg [31:0] bus[N-1:0];
  
  always @(*) begin       
     for (j=0; j&lt;32; j=j+1) begin : bits
       for (k=0; k &lt; N; k=k+1) begin : bus
         temp = bus[k][j];
       end
       out_bus[j] = |temp;
     end
  end
  </code></pre>
  
  <p>This need to be synthesizable.  There's got to be a cleaner/better way, no?</p>