title: Priority encoder in verilog
body: <p>I am somewhat new to verilog, I tried running this code but it gives me an error:</p>
  
  <pre><code>module enc(in,out);
    input [7:0] in;
    output [3:0] out;
    reg i;
    reg [3:0] out;
  
    always @*
      begin
        for (i=0;i&lt;7;i=i+1)
          begin
            if ((in[i]==1) &amp;&amp; (in[7:i+1]==0))
              out = i;
            else
              out = 0;
          end
      end
  endmodule
  </code></pre>
  
  <p>I think it complains about in[7:i+1] but i don't understand why ?
  Can someone please advise..</p>
  
  <p><strong>EDIT</strong>
  ok so I am reluctant to using the X due to their numerous problems.. I was thinking of modifying the code to something like this :</p>
  
  <pre><code>module enc(in,out);
    input [7:0] in;
    output [2:0] out;
    reg i;
    reg [2:0] out,temp;
  
    always @*
      begin
        temp = 0;
        for (i=0;i&lt;8;i=i+1)
          begin
            if (in[i]==1)
              temp = i;
          end
        out = temp;
      end
  endmodule
  </code></pre>
  
  <p>Do you think that will do the trick ? I currently don't have access to a simulator..</p>