title: ADDRESS WIDTH from RAM DEPTH
body: <p>I am implementing a configurable DPRAM where RAM DEPTH is the parameter.</p>
  
  <p>How to determine ADDRESS WIDTH from RAM DEPTH?</p>
  
  <p>I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH)</p>
  
  <p>i.e ADDRESS WIDTH = log (base 2) RAM DEPTH.</p>
  
  <p>How to implement the log (base 2) function in Verilog?</p>