title: How to parameterize a case statement with don't cares?
body: <p>I have a wire called input and I want to detect the number of leading 
  I am trying to create a module which uses the case statement below to change the output data depending on the number of leading zeros. However the size of the input is parameterizable.</p>
  
  <p>If X was a fixed value of 4, I would just create a case statement,</p>
  
  <pre><code>case (input)
    4'b0001  : o_data = {i_data[0]};
    4'b001x  : o_data = {i_data[1],1'b0};
    4'b01xx  : o_data = {i_data[2],2'b0};
    4'b1xxx  : o_data = {i_data[3],3'b0};
    default  : o_data = 4'b0000;
  endcase
  </code></pre>
  
  <p>But with variable X, how do I define all cases?</p>
  
  <p>This question is similar to this one: <a href="https://stackoverflow.com/questions/19875899/how-to-define-a-parameterized-multiplexer-using-systemverilog">How to define a parameterized multiplexer using SystemVerilog</a></p>