title: Half Adder and Full Adder logic?
body: <p>I'm Having trouble getting my half adder and full adder tests to pass, and I'm wondering whats wrong with my logic in the <code>FullAdder()</code> and <code>HalfAdder()</code> methods? None of my tests seem to be passing for some reason...</p>
  
  <p>Heres The code: </p>
  
  <pre><code>    # All wires that enter/exit the circuit need to be visible outside of the 
      # function: they are to be created in the enclosing scope and passed 
      # as parameters.
      # However, wires that connect the AND gates to the OR gates are 
      # _internal wires_, visible only inside the circuit: they need to be created
      xy = self.Wire('xy')
      xz = self.Wire('xz')
      yz = self.Wire('yz')
      xy_or_xz = self.Wire('xy_or_xz')
  
      self.AndGate(x, y, xy)  
      self.AndGate(x, z, xz)  
      self.Andgate(x, z, yz)
  
      # OR(xy,xz,yz) = OR( OR(xy,xz),  yz)
      self.OrGate(xy, xz, xy_or_xz)
      self.OrGate(xy_or_xz, yz, o)
  
      return 'ok'
  
  def TwoSwitches(self, x, y, o):
      """ An example: light controlled by 2 switches (Rosen, 12.3, Example 3,
          - Figure 6, p. 825)
  
          F(x, y) = xy + !x.!y
      """
      # Wires x, y, and o are passed as parameters.
      # Only the internal wires need to be created:
      xy = self.Wire('xy')
      not_x = self.Wire('not_x')
      not_y = self.Wire('not_y')
      notx_noty = self.Wire('notx_noty')
  
      self.AndGate(x,y,xy)
      self.Inverter(x, not_x)
      self.Inverter(y, not_y)
      self.AndGate(not_x, not_y, notx_noty)
      self.OrGate(xy, notx_noty, o)       
  
      return 'ok'
  
  # This function needs to be defined: parameter, body definition
  def HalfAdder(self, x, y, s, c):
              notx_and_y=self.wire('notx_and_y')
              x_and_noty=self.wire('x_and_noty')
              cwire=self.wire('cwire')
              allwire=self.wire(allwire)
              self.OrGate(self.AndGate(not x,y,notx_and_y),self.AndGate(x,not y,x_and_noty),allwire)
      cwire=self.AndGate(x,y,cwire)
      c=cwire
      s=allwire
      pass
  
  def FullAdder(self,x,y,c_i,s, c_out):
      #TODO
      pass
  </code></pre>