title: inputs without type in system verilog
body: <p>I've encountered in an example for a system verilog code decleration of inputs and outputs for a <code>module</code> without stating their type, e.g <code>logic</code>, <code>wire</code>...</p>
  
  <pre><code>module mat_to_stream (
    input [2:0] [2:0] [2:0] a,b,
    input newdata,
    input rst, clk,
    output [2:0] [7:0] A_out, B_out);
    ...rest of code...
  </code></pre>
  
  <p>What is the diffrence between stating <code>logic</code> and not stating any type?</p>