title: Non-constant indexing for a logic statement in systemverilog
body: <p>I am trying to create a for loop that assigns different values to a logic array given the iteration of the loop.</p>
  
  <p>So, for instance, let's say I am trying to instantiate two different bricks, both with a width of 10 and height of 5. Let's also say that each of these values are 10 bits. For two bricks, I have the code:</p>
  
  <pre><code>logic[19:0] Brick_Width;
  logic[19:0] Brick_Height;
  </code></pre>
  
  <p>Where the first brick's width and height will be assigned into the most significant 10 bits and the second's in the least significant 10 bits.</p>
  
  <p>This is the code that I currently have for this:</p>
  
  <pre><code>int i = 19;
  initial
  begin
   for(i=19; i&gt;=0; i=i-10)
   begin
    assign Brick_Width[i:i-9] = 10;
    assign Brick_Height[i:i-9] = 5;
   end
  end
  </code></pre>
  
  <p>However, I get an error saying that "i" is not a constant. Any ideas on how I can go about doing this?</p>