title: shortcut for makefile prerequisite file of the same name as target
body: <p>I have a collection of Markdown files, videos, graphviz dot files, etc. and I'd like to use make to process the files as necessary, and do this without having to repeat myself any more than necessary.</p>
  
  <p>In the Makefile, I'm writing build instructions for each individual file because a) there aren't so many, and b) each file could theoretically require a slightly different process to build. The standard <code>%.html: %.md</code> type of rules won't be useful because not all html files are build using the same commands, for example.</p>
  
  <p>However, I can't figure out how to abbreviate the prerequisite section of the rule syntax. Each target file depends on a file in the source directory with the same name. How do I avoid typing the name twice in a basic rule such as the following? I feel like I should be able to just specify the stem of the filename, the target suffix, and the source suffix, and that's it. This seems like it should be a very simple thing, so I'm probably just using the wrong terms to describe it and search for the solution.</p>
  
  <pre><code>./dist/00-introductions/overview.html: ./src/00-introductions/overview.md
         $(PANDOC) $(PANDOC_OPTIONS) $(PANDOC_REVEALJS) -o $@ $&lt;
  </code></pre>
  
  <p>In case it matters, </p>
  
  <pre><code>$ make -v
  GNU Make 4.1
  Built for x86_64-pc-linux-gnu
  </code></pre>