title: verilog error ... (vlog-2110) Illegal reference to net array
body: <p>Using Verilog, I want to make 4by4 multiplier, but there is one error:</p>
  <blockquote>
  <p>vlog-2110) Illegal reference to net array &quot;w11&quot;.</p>
  </blockquote>
  <p>about other variables w12, o1..... there is also error...</p>
  <p>I cannot understand the meaning of the error.  If you can solve this error, please tell me.</p>
  <pre><code>module half_adder (x,y,s,c);
    input x,y;
    output s,c;
  
    assign s=x^y;
    assign c=x&amp;y;   
  endmodule
  
  module full_adder (x,y,z,s,c);
    input x,y,z;
    output s,c;
    wire w1,w2,w3;
  
    half_adder h1(x,y,w1,w2);
    half_adder h2(w1,z,s,w3);
    assign c = w2|w3;
  endmodule   
  
  module  four_bit_adder (a, b, c0, s, c4);
    input [3:0]a;
    input [3:0]b;
    input c0;
    output [3:0]s;
    output c4;
    wire c1,c2,c3;
  
    full_adder fu1(a[0],b[0],c0,s[0],c1);
    full_adder fu2(a[1],b[1],c1,s[1],c2);
      
    full_adder fu3(a[2],b[2],c2,s[2],c3);
    full_adder fu4(a[3],b[3],c3,s[3],c4);
  endmodule
  </code></pre>
  <p>maybe there is error next code</p>
  <pre><code>// 4by4_multiplier
  module four_four_multi (A,B, zero, C);
    input [3:0]A;
    input [3:0]B;
    input zero;
    output [7:0]C;
    wire w11[3:0];
    wire w12[3:0];
    wire o1[3:0];
    wire w21[3:0];
    wire w22[3:0];
    wire o2[3:0];
    wire w31[3:0];
    wire w32[3:0];
    wire o3[3:0];
    wire o4;
    
    assign C[0] = A[0] &amp; B[0];
  
    assign w11[0] = A[0] &amp; B[1];
    assign w11[1] = A[0] &amp; B[2];
    assign w11[2] = A[0] &amp; B[3];
    assign w11[3] = 0;
    
    assign w12[0] = A[1] &amp; B[0];
    assign w12[1] = A[1] &amp; B[1];
    assign w12[2] = A[1] &amp; B[2];
    assign w12[3] = A[1] &amp; B[3];
  
    four_bit_adder four1(w11, w12, zero, o1 ,w21[3] );
  
    assign C[1] = o1[0];
    assign w21[0] = o1[1];
    assign w21[1] = o1[2];
    assign w21[2] = o1[3];
    
    assign w22[0] = A[2] &amp; B[0];
    assign w22[1] = A[2] &amp; B[1];
    assign w22[2] = A[2] &amp; B[2];
    assign w22[3] = A[2] &amp; B[3];
  
    four_bit_adder four2(w21, w22, zero, o2 ,w31[3] );
  
    assign C[2] = o2[0];
    assign w31[0] = o2[1];
    assign w31[1] = o2[2];
    assign w31[2] = o2[3];
    
    four_bit_adder four3(w31, w32, zero, o3 , o4 );
  
    assign C[3] = o3[0];
    assign C[4] = o3[1];
    assign C[5] = o3[2];
    assign C[6] = o3[3];
  endmodule
  </code></pre>