title: VHDL Synthesis - FF/Latch Constant Value
body: <p>I am trying to synthesize a vhdl module I have written.</p>
  
  <p>The code is below:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  use IEEE.NUMERIC_STD.ALL;
  
  entity ClockCounter is
      port(
          clk         : in std_logic;
          input       : in std_logic;
          enable      : in std_logic;
          output      : out std_logic := '0';
          bitReady    : out std_logic := '0';
          countError  : out std_logic := '0'
      );
  end ClockCounter;
  
  architecture Behavioral of ClockCounter is
  
  signal totalBitWidth     : integer := 4;
  signal majorityValue     : integer := 3;
  
  begin
  
  totalBitWidth &lt;= 4;
  majorityValue &lt;= 3;
  
  -- Process for recognizing a single input value from a  clock cycle
  -- wide input signal
  majority_proc: process(clk, input, enable)
  
      variable clkCount : integer := 0;
      variable Sum      : integer := 0;
  
      begin
  
      if rising_edge(clk) And enable = '1' then
          -- Reset bitReady after one clock cycle
          bitReady &lt;= '0';
  
          -- Check the input value and add it to the Sum variable
          if input = '1' then
              Sum := Sum + 1;
          else
              Sum := Sum + 0;
          end if;
  
          -- Increment the clock counter variable
          clkCount := clkCount + 1;
  
          -- Check if the clock count has reached the specified number of cycles
          if clkCount &gt;= totalBitWidth then
              -- Determine if the Sum variable has met the threshold for
              -- value of 1, set the output accordingly
              if Sum &gt;= majorityValue then
                  output &lt;= '1';
              else
                  output &lt;= '0';
              end if;
  
              -- This checks if the value for all clock cycles was the same and
              -- sets an error flag if not
              if Sum = totalBitWidth Or Sum = 0 then
                  countError &lt;= '0';
              else
                  countError &lt;= '1';
              end if;
  
              -- Reset the clock counter and sum value
              clkCount := 0;
              Sum := 0;
              -- Set the bit counter high to alert other midules that a new bit
              -- has been received
              bitReady &lt;= '1';
          end if;
          elsif enable = '0' then
          clkCount := 0;
          Sum := 0;
      end if;
  
      end process;
  
      end Behavioral;
  </code></pre>
  
  <p>The problem I am getting is this when trying to synthesize:</p>
  
  <blockquote>
    <p>WARNING:Xst:1293 - FF/Latch  has a constant
    value of 0 in block . This FF/Latch will be trimmed
    during the optimization process. WARNING:Xst:1896 - Due to other
    FF/Latch trimming, FF/Latch  has a constant
    value of 0 in block . This FF/Latch will be trimmed
    during the optimization process. WARNING:Xst:1896 - Due to other
    FF/Latch trimming, FF/Latch  has a constant
    value of 0 in block . This FF/Latch will be trimmed
    during the optimization process.</p>
  </blockquote>
  
  <p>The trimming goes all the way down to .</p>
  
  <p>What I don't get is that the clkCount variable is an integer that increments up to 6 at most, and then is reset to 0.</p>
  
  <p>Are these warnings something I can ignore?</p>
  
  <p>This module is apart of a larger system I am working on, and when I synthesize the larger system I get a lot of  </p>
  
  <blockquote>
    <p>Found 1-bit latch for signal</p>
  </blockquote>
  
  <p>So what I am trying to do is eliminate as many warning as possible in lower level modules before fixing the upper level module.</p>
  
  <p>Any help would be great.
  Thanks</p>
  
  <p>PS - I am using the Xilinx spartan 6 sp605 evaluation kit board, and the Project Navigator.</p>