title: Verilog Temporary Variable
body: <p>I tried to make a CMP instruction in Verilog. To keep the result of the substraction, I declared a wire. This is what the code looks like (It is executed in an <code>always</code> statement).</p>
  
  <pre><code>wire [data_width:0] tmp_wire = reg_accumulator - reg_x;
  
  f_zero &lt;= tmp_wire &amp; 'hFF == 0;
  f_carry &lt;= tmp_wire &amp; 'h100;
  </code></pre>
  
  <p>Now Icarus Verilog complains about a syntax error and that <code>reg_accumulator - reg_x</code> is not an <code>l-value</code>:</p>
  
  <pre><code>cpu.v:149: syntax error
  cpu.v:149: Syntax in assignment statement l-value.
  </code></pre>
  
  <p>And why does it complain? What would be the right approach to declare a temporary variable in a function / task?</p>
  
  <pre><code>module comparator(
      input clk,
      input [7:0] op_a,
      input [7:0] op_b
  );
  
  reg f_zero;
  reg f_carry;
  
  function compare;
      input [data_width-1:0] a;
      input [data_width-1:0] b;
  begin
      wire [7:0] tmp_wire = reg_accumulator - reg_x;
  
      f_zero &lt;= tmp_wire &amp; 'hFF == 0;
      f_carry &lt;= tmp_wire &amp; 'h100;
  end
  endfunction
  
  always @(posedge clk) begin
      compare(op_a, op_b);
  end
  
  endmodule // comparator
  </code></pre>