title: Specify empty variable on make command line
body: <p>I have some Makefiles that are flexible based on the existence of certain variables by using <code>ifdef</code> to check for them.  It is a bit annoying that I have to actually set the variable equal to something on the command line.  <code>make all DEBUG</code> does not trigger the <code>ifdef</code> but <code>make all DEBUG=1</code> does.  Perhaps I am just using the C pre-processor approach where it does not belong.</p>
  
  <p>Q1) Is it possible to specify a variable on the command line to be empty?  Without even more characters?
  Q2) What is the preferred approach for such boolean parameters to a make?</p>