title: SystemVerilog generic multiplexer
body: <p>I am trying to come up with a way to define a synthesizable generic multiplexer (either as a function or module) that can be used with wires, and typedefs (enums, structs) in SystemVerilog</p>
  
  <p>Is that possible in any way? 
  If not, what would be the cleanest approach to write such a multiplexer?</p>
  
  <p>Currently, I am using a multiplexer that takes a two-dimensional array of wires as input and selects one of the elements based on a select signal.</p>
  
  <p>This makes it rather painful as I am stuck casting my typed variables back and forth every time I need to connect them to the multiplexer module.
  And sadly, this is made even worse by the fact that a for loop is needed to assign a array of typed elements into an array of wires.</p>
  
  <p>Thanks,
  Sébastien.</p>