title: Valid-Ready handshake in Verilog
body: <p>I am trying to learn valid/ready handshake in verilog. In particular, I am interested to use ready as a flag that indicates the successful transaction of data (i.e., <code>ready_in</code> becomes high after <code>valid_out</code> goes high). I would like to explain my problem using a very simple Verilog example. I have written a convolutional encoder (code below)</p>
  
  <pre><code>module Conv_Encoder_Core(
      input wire clk,                 
      input wire reset,        
      input wire in_bit,
      output reg out_A,
      output reg out_B,
      input wire sleep,          
      input wire valid_in,
      input wire ready_in,
      output reg valid_out,
      output reg ready_out);
  
  reg [5:0] S;
  wire S_A, S_B, clkON;
  assign S_A = S[1] ^ S[2] ^ S[4] ^S[5];
  assign S_B = S[0] ^ S[1] ^ S[2] ^S[5];
  assign clkON = clk &amp; !sleep;
  
  always @(posedge clkON)begin
      if (reset) begin
          S &lt;=0;
          valid_out &lt;=0; 
          ready_out &lt;=0;
      end else if (valid_in) begin
          out_A &lt;= in_bit ^ S_A;
          out_B &lt;= in_bit ^ S_B;
          valid_out &lt;=1;
          if (ready_in)begin
              S&lt;= S&lt;&lt;1;
              S[0] &lt;=in_bit;
              ready_out &lt;=1;
          end else begin
              ready_out &lt;=0;
          end
  
      end else begin
          valid_out &lt;=0;
          ready_out &lt;=0;
      end
  
  
  end 
  endmodule
  </code></pre>
  
  <p>I am interested to use <code>ready_in</code> flag as an indicator that data <code>out_A</code> and <code>out_B</code> are received by the next block, so my block can accept the new data by setting <code>ready_out</code> flag high. I have written a testbench for this block, however, I am not getting the results I am expecting</p>
  
  <pre><code>`timescale 1 ns/1 ns
  module TB_Conv();
  reg  clk;
  //---------------clock generator-----------------------
  initial begin
      clk = 1'b0; 
      #5; 
      clk = 1'b1; 
      forever    begin
          #5 clk = ~clk;      
      end
  end
  //------------------ dump -----------------------
  initial begin
      $dumpfile("dumpVCD.vcd");
      $dumpvars(10);  
  end
  
  localparam N_DATA=10;
  reg in_bits_vec [0:N_DATA-1];
  initial begin
      in_bits_vec[0] = 1'b1;
      in_bits_vec[1] = 1'b0; 
      in_bits_vec[2] = 1'b0; 
      in_bits_vec[3] = 1'b0; 
      in_bits_vec[4] = 1'b0;
      in_bits_vec[5] = 1'b0;
      in_bits_vec[6] = 1'b0;
      in_bits_vec[7] = 1'b0;
      in_bits_vec[8] = 1'b0;
      in_bits_vec[9] = 1'b1;
  end
  reg in_bit, ready_in,reset, valid_in;
  Conv_Encoder_Core UUT(.clk(clk),
                          .reset(reset),
                          .in_bit(in_bit),
                          .out_A(out_A),
                          .out_B(out_B),
                          .sleep(1'b0),
                          .valid_in(valid_in),
                          .ready_in(ready_in),
                          .valid_out(valid_out),
                          .ready_out(ready_out));
  
  //---------------- code starts here -------------------//
  reg [3:0] addr;
  always @(posedge clk) begin
      if (reset)begin
          addr&lt;=0;
          valid_in &lt;=0;
          in_bit &lt;=0;
      end else if (addr &lt; 10) begin
          in_bit &lt;= in_bits_vec[addr];
          valid_in &lt;=1'b1;
          if (ready_out) begin
              addr &lt;= addr+1'b1;
          end
  
      end else  begin
          in_bit &lt;=0;
          valid_in &lt;=0;
      end
  
      if (valid_out==1) ready_in &lt;= 1;
      else              ready_in &lt;= 0;
  
  end 
  // ----------- reset logic -----------//
  reg [3:0] cnt;
  initial cnt=0;
  always @(negedge clk)begin
      if (cnt&lt;5) begin
          reset = 1;
          cnt=cnt+1;
      end else  reset =0;
  end
  
  initial begin
   #1000;
  $finish;
  end
  endmodule
  </code></pre>
  
  <p>if you look at the input data (in the testbech), you can see it is <code>1000000000</code>. I am expecting to see <code>1</code> being passed through <code>S</code> register as follows:</p>
  
  <pre><code>S = 000000 //at beginning
  S = 000001 // after ready_out=1
  S = 000010
  S = 000100
  </code></pre>
  
  <p>however, the results I get is entirely different(please see snapshot).
  Another problem I have is that <code>inbit=1</code> continues two clock cycles more than what I expect. in fact when <code>ready_out=1</code>, I expect to see that <code>in_bit</code> becomes zero but this happens two clock cycles later(yellow cursor in the snapshot ).</p>
  
  <p>I would be most grateful if someone could explain what I do wrong in this example. </p>
  
  <p><a href="https://i.stack.imgur.com/cYfRY.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cYfRY.jpg" alt="enter image description here"></a></p>