title: error in a vhdl code
body: <p>i am new to vhdl. i have a code with me as follows (the sub prog compiles very fine). i can't fix the following error</p>
  
  <p>** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(110): Illegal sequential statement.
  ** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(115): Illegal sequential statement.
  ** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(120): Illegal sequential statement.
  ** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): Illegal sequential statement.
  ** Warning: [14] C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): (vcom-1272) Length of formal "Remainder" is 4; length of actual is 8.</p>
  
  <p>** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(138): VHDL Compiler exiting</p>
  
  <p>the line nos are bold ones in the code here.they are the  <strong>portmap</strong> ones
  Can anyone please help me out with this. it would be very kind of you.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity ALU_VHDL is
     port
     (
        OperandA : in std_logic_vector(3 downto 0);
        OperandB : in std_logic_vector(3 downto 0);
        Operation: in std_logic_vector(2 downto 0);
          Startt    : in std_logic;
        Ready : out std_logic;
          Result_High : out std_logic_vector(3 downto 0);
          Result_Low : out  std_logic_vector(7 downto 0);
          Errorsig : out std_logic;
          Reset_n : in std_logic;
          Clkk : in std_logic);
  end entity ALU_VHDL;
  
  architecture Behavioral of ALU_VHDL is
  -- And gate
   component AND_gate
    port( 
      x,y  : IN std_logic_vector(3 downto 0);
      z    : OUT std_logic_vector(3 downto 0));
  end component;
  
  -- OR Gate
  component OR_gate
    port( 
      x,y  : IN std_logic_vector(3 downto 0);
      z    : OUT std_logic_vector(3 downto 0));
  end component;
  -- XOR gate
  
  component XOR_gate
    port( 
      x,y  : IN std_logic_vector(3 downto 0);
      z    : OUT std_logic_vector(3 downto 0));
  end component;
  -- Adder
  
  COMPONENT adder4 
  PORT
      (
      C : IN std_logic;
      x,y : IN std_logic_vector(3 DOWNTO 0);
      R   : OUT std_logic_vector(3 DOWNTO 0);
      C_out   : OUT std_logic);
  END COMPONENT;
  
  -- Subtractor
  COMPONENT Substractor4 
  PORT
         (
          br_in : IN std_logic;
          x,y : IN std_logic_vector(3 DOWNTO 0);
  
          R   : OUT std_logic_vector(3 DOWNTO 0);
          E   : out std_logic);
  END COMPONENT;
  
  -- Multiplier
  COMPONENT mult4by4 
      port(operA, operB: in std_logic_vector(3 downto 0);
       sumOut: out std_logic_vector(7 downto 0));
  END COMPONENT;
  
  -- Division
  COMPONENT Division 
  Port ( Dividend : in std_logic_vector(3 downto 0);
             Divisor : in std_logic_vector(3 downto 0);
             Start :   in std_logic;
             Clk :     in std_logic;
             Quotient :  out std_logic_vector(3 downto 0);
             Remainder :    out std_logic_vector(3 downto 0);
             Finish : out std_logic);
  END COMPONENT;  
  
   begin
  
     process(OperandA, OperandB, Startt, Operation) is
     begin
  
  
        case Operation is
  
               when "000" =&gt; 
                   Result_High &lt;= "XXXX";
  
  
               when "001" =&gt;
                   Result_High &lt;= OperandA and OperandB;
  
  
                   when "010" =&gt;
             Result_High &lt;= OperandA or OperandB;
  
  
             when "011" =&gt;
             Result_High &lt;= OperandA xor OperandB;
  
  
  
             when "100" =&gt; 
             -- Adder
                   **U05 : adder4 PORT MAP (C=&gt;Startt,x=&gt;OperandA,y=&gt;OperandB,R=&gt;Result_High,C_out=&gt;Ready);**
  
  
             when "101" =&gt;
             -- Substractor &amp; Error signal
                   **U06 : Substractor4 PORT MAP (br_in=&gt;Startt,x=&gt;OperandA,y=&gt;OperandB,R=&gt;Result_High,E=&gt;Errorsig);**
  
  
               when "110" =&gt;
                   -- multiplication
             **U07 : mult4by4 PORT MAP (operA=&gt;OperandA,operB=&gt;OperandB,sumOut=&gt;Result_Low);**
  
  
             when "111" =&gt;
                   -- Division
                   if (OperandB ="0000") then
                     Errorsig &lt;= '1';
                   else
               **U08 : Division PORT MAP (Dividend=&gt;OperandA,Divisor=&gt;OperandB,Start=&gt;Startt,Clk=&gt;Clkk,Quotient=&gt;Result_High,Remainder=&gt;Result_Low,Finish=&gt;Ready);**
                   end if;
  
                   when others =&gt;
                   Errorsig &lt;= '1';
  
        end case;
  
     end process;
  
  end architecture Behavioral;
  </code></pre>