title: VHDL illegal use of a signal declaraction
body: <p>The following is my code:</p>
  
  <pre><code>LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  ENTITY work4 IS
  PORT (  CS: IN STD_LOGIC;
          RD: IN STD_LOGIC;
          WR: IN STD_LOGIC;
          DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
   END work4; 
  ARCHITECTURE behav OF work4 IS BEGIN 
  
  PROCESS(CS, RD,WR) 
  SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
  
  BEGIN 
   IF CS'EVENT AND CS = '1' THEN 
      IF WR='1' AND RD='0' THEN DATA&lt;=T;
      ELSE IF WR='0' AND RD='1' THEN T&lt;=DATA;
      END IF;
  END IF;
  END IF; 
   END PROCESS; 
   END behav;
  </code></pre>
  
  <p>When I compile it, my compiler complains: </p>
  
  <pre><code>Error: found illegal use of signal declaration in process declarative part
  </code></pre>
  
  <p>I know I'm using the wrong signal, but do not know where it's wrong. </p>
  
  <p>Is there anyone can help? </p>