title: how do i initialize a std_logic_vector in VHDL?
body: <p>i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below:</p>
  
  <pre><code>architecture Behavioral of test is
  
      type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
      signal ram : ram_type;
      ram(0) := "0010000000000100";   
      ram(1) := "0001000000000101";
      ram(2) := "0011000000000110";
      ram(3) := "0111000000000001";
      ram(4) := "0000000000001100";
      ram(5) := "0000000000000011";
      ram(6) := "0000000000000000";
      ram(4095 downto 7) := (others =&gt; (others =&gt; '0'));
      begin
     "some code"
  end behavioral
  </code></pre>
  
  <p>for some reason i need to initialize it with these values (i can't assign these values to it , it has to be initialized)
  is there even any ways to do it? i tried the above code and it didn't work</p>