title: Ones count system-verilog
body: <p>I have a wire vector with 64 bits;</p>
  
  <pre><code>wire [63:0] sout;
  </code></pre>
  
  <p>I want to compute the sum of these bits or, equivalently, count the number of ones.</p>
  
  <p>What is the best way to do this? (it should be synthesizable)</p>