title: VHDL types mismatch during simulation MODELSIM
body: <p>I am getting this error :</p>
  
  <pre><code># Loading std.standard
  # Loading ieee.std_logic_1164(body)
  # Loading ieee.numeric_std(body)
  # Loading work.acc(behavioralreg)
  # Loading ieee.std_logic_arith(body)
  # Loading ieee.std_logic_unsigned(body)
  # Loading work.alu(arc)
  # Loading work.ar(behavioralreg)
  # Loading work.controlunit(arc)
  # Loading work.ir(behavioralreg)
  # Loading work.memory(behv)
  # Loading work.pc(behavioralreg)
  # Loading work.processor(arc)
  </code></pre>
  
  <p>-----------NOW COMES ERROR -------------    </p>
  
  <pre><code># ** Failure: (vsim-3807) Types do not match between component and entity for port "address".
  #    Time: 0 ns  Iteration: 0  Instance: /processor/memmap File: C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/memory.vhd Line: 10
  # ** Error: (vsim-3733) C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/processor.vhd(187): No default binding for component at 'memmap'.
  #  (Generic 'words' is not on the entity.)
  #         Region: /processor/memmap
  # ** Error: (vsim-3733) C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/processor.vhd(187): No default binding for component at 'memmap'.
  #  (Generic 'bits' is not on the entity.)
  #         Region: /processor/memmap
  # Fatal error in Process rea at C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/memory.vhd line 50
  #  while elaborating region: /processor/memmap
  # Fatal error in Process line__201 at C:/Users/dell/Desktop/PROESSORS/VHDL Codes_1/333CO10_Proc.vhdl/processor.vhd line 201
  #  while elaborating region: /processor
  </code></pre>
  
  <p>what is error ? i have checked it many times but not getting the wrong point. I am a beginner in VHDL .</p>
  
  <p>my code :</p>
  
  <pre><code>library ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;
  use IEEE.std_logic_unsigned.all;
  
  entity processor is
  end processor;
  
  architecture arc of processor is
  ---some code
  component memory
  
  generic( bits : INTEGER:=8;
           words :INTEGER:=256);  
  
  port (  
      enable      :   in std_logic;
          read        :   in std_logic;
          write       :   in std_logic;
          address :   in INTEGER range 0 to words-1;
          data_in :   in std_logic_vector(15 downto 0);
          data_out:   out std_logic_vector(15 downto 0)
  );
  end component;
  --some code
  signal MEMenable        : std_logic:='0';
  signal  MEMread     :   std_logic:='0';
  signal  MEMwrite        :   std_logic:='0';
  signal MEMaddr  :    INTEGER range 0 to 255;
  signal  MEMdata_in  :   std_logic_vector(15 downto 0):="0000000000000000";
  signal  MEMdata_out:     std_logic_vector(15 downto 0):="0000000000000000";
  signal clk: bit ;
    signal clocktime :integer range 0 to 10 :=0;
    signal rst : bit :='0';
  --now PORT MAPPING COMPONENTS-----
  begin
  --- some code
  MEMmap: memory port map(    
          enable=&gt;MEMenable   ,
          read=&gt;MEMread   ,
          write=&gt;MEMwrite,
          address=&gt;MEMaddr    ,
          data_in=&gt;MEMdata_in ,
          data_out=&gt;MEMdata_out
  );
  --- some code
  </code></pre>
  
  <p>and memory is :</p>
  
  <pre><code>library ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;
  use IEEE.std_logic_unsigned.all;
  entity memory is
  port (
      enable      :   in std_logic;
          read        :   in std_logic;
          write   :   in std_logic;
          address :   in std_logic_vector(7 downto 0);
          data_in :   in std_logic_vector(15 downto 0);
          data_out:   out std_logic_vector(15 downto 0)
  );
  end memory;
  
  architecture behv of memory is          
  
    type ram_type is array (0 to 255) of 
                  std_logic_vector(15 downto 0);
    signal tmp_ram: ram_type;
  
  begin
  
      writ: process(enable, read, address, data_in)
      begin
      ---some code
      end process;
  end behv;
  </code></pre>
  
  <p>all files : if you want full codes, please ask me.</p>