title: Error loading design modelsim PE student edition 10.4
body: <p>I'm creating a new project which i called alpha,then i create a new file test.vhd.</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity d_latch is 
  port(
  data_in:in std_logic;
  data_out:out std_logic;
  enable:in std_logic);
  end d_latch;
  
  architecture beh of d_latch is 
  begin
  process(data_in,enable)
      begin
       if(enable &lt;= '1') then 
          data_out &lt;= data_in;
        end if;
      end process;
  end beh;
  </code></pre>
  
  <p>I add test.vhd to the project alpha then i compile the file.After that i simulate->start simulate then i check [+] work library then the module presented in it,but an error's message appears </p>
  
  <pre><code>Error loading design
  </code></pre>