title: What steps are necessary to pipeline a processor in VHDL?
body: <p>This is a homework question, obviously. I'm trying to pipeline a simple, 5 stage (IF,ID,EX,MEM,WB), single-cycle MIPS processor in VHDL. I don't need to implement forwarding or hazard detection for it. I'm just unsure of what components I need to implement.</p>
  
  <ol>
  <li>Is it necessary to create D Flip-Flops for each signal?</li>
  <li>The pipeline implementation <a href="http://vhdlguru.blogspot.com/2011/01/what-is-pipelining-explanation-with.html" rel="nofollow">here</a> uses a for-loop for the outputs - is that something I should do?</li>
  </ol>
  
  <p>Any tips would be much appreciated, I can't seem to find much relevant information on pipelining in VHDL.</p>