title: verilog instantiate multiple registers
body: <p>I have writen an 8bit register module like this:</p>
  
  <pre><code>module ff_8 #(
       parameter q0=0
  )(
      input clk,
      input rst_n,
      input enable,
      input [7:0] d,
      output reg[7:0] q,
      );
  
  always @ (posedge clk)
  if (!rst_n) begin
      q &lt;= q0;
  end else if(enable) begin
      q &lt;= d;
  end
  
  endmodule
  </code></pre>
  
  <p>How can i have multiple (128) instances of ff_8 each with different q0 parameter without having to write the same code 128 times?</p>