title: Why am I getting this parenthesis error in Verilog?
body: <p>I am trying to initiate a module in a top level in Verilog (beginner).
  Here is the top Level code:</p>
  
  <pre><code>module top(
  
  //////////// SEG7 //////////
  output           [7:0]      HEX0,
  output           [7:0]      HEX1,
  output           [7:0]      HEX2,
  output           [7:0]      HEX3,
  output           [7:0]      HEX4,
  output           [7:0]      HEX5,
  
  //////////// LED //////////
  output           [9:0]      LEDR,
  
  //////////// SW //////////
  input            [1:0]      SW);
  always@(SW) begin
  
  
  
  testgen test(.select[1](SW[1]), .select[0](SW[0]), data0[3:0], data1    [3:0], data2[3:0], data2[3:0]);
  
  
  
  end
  
  endmodule
  </code></pre>
  
  <p>Here is testgen (the module I'm trying to initiate</p>
  
  <pre><code>module testgen (
  input      [1:0] select,
  output reg [3:0] data0,
  output reg [3:0] data1,
  output reg [3:0] data2,
  output reg [3:0] data3
  );
  
  always @(*) begin
    case (select)
       2'b00: begin
          data0 = 4'b0011;    // 3
          data1 = 4'b0010;    // 2
          data2 = 4'b0001;    // 1
          data3 = 4'b0000;    // 0
       end
       2'b01: begin
          data0 = 4'b1010;    // A
          data1 = 4'b1100;    // C
          data2 = 4'b1110;    // E
          data3 = 4'b1111;    // F
       end
       2'b10: begin
          data0 = 4'b0111;    // 7
          data1 = 4'b0001;    // 1
          data2 = 4'b0000;    // 0
          data3 = 4'b1010;    // A
       end
       2'b11: begin
          data0 = 4'b0101;    // 5
          data1 = 4'b1111;    // F
          data2 = 4'b1100;    // C
          data3 = 4'b0010;    // 2
       end
       default: begin
          data0 = 4'b0000;    // 0 should never be selected
          data1 = 4'b0000;    // 0 should never be selected
          data2 = 4'b0000;    // 0 should never be selected
          data3 = 4'b0000;    // 0 should never be selected
       end
    endcase
  end
  
  endmodule
  </code></pre>
  
  <p>There's a bunch of other modules I want to incorporate in the top level, but I just want to know why I'm getting the following error</p>
  
  <pre><code>Error (10170): Verilog HDL syntax error at top.v(29) near text: "[";    expecting "(". 
  </code></pre>
  
  <p>Am I instantiating incorrectly? Why is this happening? Line 29 is the line where I instantiate testgen. Any help would be appreciated, thanks!</p>