title: Generate statement inside verilog task
body: <p>I want to use generate statement inside a task. The following code is giving compile errors (iverilog).</p>
  
  <pre><code>task write_mem; //for generic use with 8, 16 and 32 bit mem writes
        input [WIDTH-1:0] data;
        input [WIDTH-1:0] addr;
        output [WIDTH-1:0] MEM;
        integer i;
  
        begin
           generate
              genvar j;
              for(j=0; j&lt;i;j++)
              MEM[addr+(i-j-1)] = data[(j*8):((j*8) + 8)-1];
           endgenerate
        end
  endtask // write_mem
  </code></pre>
  
  <p>I also tried putting <code>generate</code> just after the line <code>integer i</code>, but still its producing errors. Any thoughts?</p>
  
  <p>EDIT: I also tried putting <code>genvar</code> declaration between <code>begin</code> and <code>generate</code> statement in the above code. Its still producing compiler errors</p>
  
  <p>Thanks in advance,</p>
  
  <p>Jay Aurabind</p>