title: Quartus netlist optimization lost register fanout in a state machine
body: <p>Hi guys i'm trying to implement a state machine but i have the problem that during timing simulation i get an error saying that</p>
  <blockquote>
  <p>Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.</p>
  </blockquote>
  <blockquote>
  <p>Info: Register &quot;state.STATE_I&quot; lost all its fanouts during netlist optimizations.</p>
  </blockquote>
  <p>and in the waveform timing simulation the output works fine but if i try to check the actual state I only get an initial state (STATE I) and an &quot;UNDEFINED&quot; in the rest of places where the actual state should be shown, the code is:</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  --define entity
  entity pregunta1a is
    port(
      resetn  : in  std_logic;
      clock   : in  std_logic;
      w       : in  std_logic;
      z       : out std_logic
    );
  end pregunta1a;
  --define architecture
  architecture behavior of pregunta1a is
    type STATE_TYPE is (STATE_A,STATE_B,STATE_C,STATE_D,STATE_E,STATE_F,STATE_I); -- todos los estados
    signal state, next_state : STATE_TYPE;
  begin
    process(clock)
    begin
      if(rising_edge(clock)) then
        if (resetn='0') then
          state &lt;= STATE_I;                
        else
          state &lt;= next_state;
        end if;
      end if;
    end process;
    
    process(state,w) -- complete sensitivity list
    begin
      z&lt;='0';
      case state is
        when  STATE_A =&gt;
          if (w = '1') then
            next_state &lt;= STATE_B;
          else
            next_state &lt;= STATE_C;
          end if;
        when STATE_B =&gt;
          if (w = '1') then
            next_state &lt;= STATE_D;
          else
            next_state &lt;= STATE_A;
          end if;
        when STATE_C =&gt;
          if (w = '1') then
            next_state &lt;= STATE_B;
          else
            next_state &lt;= STATE_E;
          end if;
        when STATE_D =&gt;
          if (w = '1') then
            next_state &lt;= STATE_F;
          else
            next_state &lt;= STATE_A;
          end if;
        when STATE_E =&gt;
          if (w = '1') then
            next_state &lt;= STATE_B;
          else
            next_state &lt;= STATE_E;
            z&lt;='1';  
          end if;
        when STATE_F =&gt;
          if (w = '1') then
            next_state &lt;= STATE_F;
            z&lt;='1';        
          else
            next_state &lt;= STATE_A;
          end if;
        when STATE_I =&gt;
          if (w = '1') then
            next_state &lt;= STATE_B;
          else
            next_state &lt;= STATE_A;
          end if;
      end case;
    end process; 
  end behavior;
  </code></pre>
  <p><a href="https://i.stack.imgur.com/WjL0s.png" rel="nofollow noreferrer">This is a screenshot of the timing simulation</a>
  anyone known how to solve this ??</p>