title: MESI protocol understanding state transitions
body: <p>In the state transition diagram shown below for the Illinois MESI protocol, why is there a Flush' signal when transitioning from state S to state I and a Flush signal when going from state E to state I upon observing a BusRdX signal. Wouldn't the cache content for processors in these states be the same as the content in main memory? If so, what would be the point of these caches going to state I to flush their data? Also, what exactly is the difference between Flush and Flush'. Is it just that in Flush', data is exchanged transferred by one cache?</p>
  
  <p>Transition diagram:</p>
  
  <p><img src="https://i.stack.imgur.com/JqJbQ.png" alt="enter image description here"></p>