title: How do I get my wire name to show up when using dynamic indexing?
body: <p>When running something like</p>
  
  <pre><code>class Foo extends Module {
    val io = IO(new Bundle {
      val in = Input(Vec(4, Bool()))
      val idx = Input(UInt(2.W))
      val en = Input(Bool())
      val out = Output(Bool())
    })
  
    val x = io.in(io.idx)
    val y = x &amp;&amp; io.en
    io.out := y
  }
  </code></pre>
  
  <p>The generated Verilog loses the <code>x</code> name:</p>
  
  <pre><code>module Foo(
    input        clock,
    input        reset,
    input        io_in_0,
    input        io_in_1,
    input        io_in_2,
    input        io_in_3,
    input  [1:0] io_idx,
    input        io_en,
    output       io_out
  );
    wire  _GEN_1; // @[main.scala 15:13]
    wire  _GEN_2; // @[main.scala 15:13]
    wire  _GEN_3; // @[main.scala 15:13]
    assign _GEN_1 = 2'h1 == io_idx ? io_in_1 : io_in_0; // @[main.scala 15:13]
    assign _GEN_2 = 2'h2 == io_idx ? io_in_2 : _GEN_1; // @[main.scala 15:13]
    assign _GEN_3 = 2'h3 == io_idx ? io_in_3 : _GEN_2; // @[main.scala 15:13]
    assign io_out = _GEN_3 &amp; io_en; // @[main.scala 16:10]
  endmodule
  </code></pre>
  
  <p>How can I make sure the wire name shows up?</p>