title: Missing ROM files when building linux-on-litex
body: <p>To get familiar with my Lattice ECP5-evn and the LiteX toolchain I am trying to build <a href="https://github.com/litex-hub/linux-on-litex-vexriscv" rel="nofollow noreferrer">linux-on-litex</a>. But already in the simulation I'm running into trouble. I'm using virtual box with the latest ubuntu image (ubuntu-20.04.3-desktop-amd64).</p>
  <p>I installed the prerequisites and on top of that ninja-build, default-jdk and stb. Then I installed LiteX and downloaded the following RISC-V toolchain: riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14. Then I cloned the linux-on-litex repo and ran <code>./sim.py</code>. Everything is set correctly in my PATH variable and I'm getting no errors there.</p>
  <p>However, the simulation is complaining about missing images. And indeed, according to the boot.json which is provided there should be 4 files there:</p>
  <ul>
  <li>Image</li>
  <li>rv32.dtb</li>
  <li>rootfs.cpio</li>
  <li>opensbi.bin</li>
  </ul>
  <p>However, none of the files come with the git repo, so I guess I need to compile/collect them myself. I noticed that only  rv32.dtb is created when running <code>./sim.py</code>. Perhaps the other 3 files should also be created automatically. But I'm getting no errors there, only that the files are missing. Here is the terminal output of running <code>./sim.py</code>:</p>
  <pre><code>INFO:SoC:        __   _ __      _  __  
  INFO:SoC:       / /  (_) /____ | |/_/  
  INFO:SoC:      / /__/ / __/ -_)&gt;  &lt;    
  INFO:SoC:     /____/_/\__/\__/_/|_|  
  INFO:SoC:  Build your hardware, easily!
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoC:Creating SoC... (2022-01-12 23:25:20)
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoC:FPGA device : SIM.
  INFO:SoC:System clock: 100.000MHz.
  INFO:SoCBusHandler:Creating Bus Handler...
  INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
  INFO:SoCBusHandler:Adding reserved Bus Regions...
  INFO:SoCBusHandler:Bus Handler created.
  INFO:SoCCSRHandler:Creating CSR Handler...
  INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  INFO:SoCCSRHandler:Adding reserved CSRs...
  INFO:SoCCSRHandler:ctrl CSR added at Location 0.
  INFO:SoCCSRHandler:uart CSR added at Location 2.
  INFO:SoCCSRHandler:timer0 CSR added at Location 3.
  INFO:SoCCSRHandler:CSR Handler created.
  INFO:SoCIRQHandler:Creating IRQ Handler...
  INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
  INFO:SoCIRQHandler:Adding reserved IRQs...
  INFO:SoCIRQHandler:IRQ Handler created.
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoC:Initial SoC:
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
  INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  CSR Locations: (3)
  - ctrl   : 0
  - uart   : 2
  - timer0 : 3
  INFO:SoC:IRQ Handler (up to 32 Locations).
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
  INFO:SoC:CPU overriding rom mapping from 0x00000000 to 0x00000000.
  INFO:SoC:CPU overriding sram mapping from 0x01000000 to 0x10000000.
  INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
  INFO:SoC:CPU overriding csr mapping from 0xf0000000 to 0xf0000000.
  INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
  INFO:SoCBusHandler:plic Region added at Origin: 0xf0c00000, Size: 0x00400000, Mode: RW, Cached: False Linker: False.
  INFO:SoCBusHandler:plic added as Bus Slave.
  INFO:SoCBusHandler:clint Region added at Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
  INFO:SoCBusHandler:clint added as Bus Slave.
  INFO:SoCIRQHandler:uart IRQ added at Location 0.
  INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
  INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
  INFO:SoCBusHandler:rom added as Bus Slave.
  INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
  INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
  INFO:SoCBusHandler:sram added as Bus Slave.
  INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
  INFO:SoCIRQHandler:uart IRQ added at Location 0.
  INFO:SoCIRQHandler:timer0 IRQ added at Location 1.
  INFO:SoCBusHandler:opensbi Region added at Origin: 0x40f00000, Size: 0x00080000, Mode: RW, Cached: True Linker: True.
  INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x04000000, Mode: RW, Cached: True Linker: False.
  INFO:SoCBusHandler:main_ram added as Bus Slave.
  VexRiscv cluster : VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood
  INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
  INFO:SoCBusHandler:csr added as Bus Slave.
  INFO:SoCCSRHandler:bridge added as CSR Master.
  INFO:SoCBusHandler:Interconnect: InterconnectShared (1 &lt;-&gt; 6).
  INFO:SoCCSRHandler:sdram CSR allocated at Location 1.
  INFO:SoCCSRHandler:supervisor CSR allocated at Location 4.
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoC:Finalized SoC:
  INFO:SoC:--------------------------------------------------------------------------------
  INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
  IO Regions: (1)
  io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
  Bus Regions: (7)
  rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
  sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
  main_ram            : Origin: 0x40000000, Size: 0x04000000, Mode: RW, Cached: True Linker: False
  opensbi             : Origin: 0x40f00000, Size: 0x00080000, Mode: RW, Cached: True Linker: True
  csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
  clint               : Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
  plic                : Origin: 0xf0c00000, Size: 0x00400000, Mode: RW, Cached: False Linker: False
  Bus Masters: (1)
  - cpu_bus0
  Bus Slaves: (6)
  - plic
  - clint
  - rom
  - sram
  - main_ram
  - csr
  INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  CSR Locations: (5)
  - ctrl       : 0
  - sdram      : 1
  - uart       : 2
  - timer0     : 3
  - supervisor : 4
  INFO:SoC:IRQ Handler (up to 32 Locations).
  IRQ Locations: (2)
  - uart   : 0
  - timer0 : 1
  INFO:SoC:--------------------------------------------------------------------------------
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libc'
  make: Nothing to be done for 'all'.
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libc'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
  make: Nothing to be done for 'all'.
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libbase'
   CC       console.o
   CC       system.o
   CC       memtest.o
   CC       uart.o
   CC       spiflash.o
   CC       i2c.o
   AR       libbase.a
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libbase'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libfatfs'
  make: Nothing to be done for 'all'.
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libfatfs'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitespi'
   CC       spiflash.o
   AR       liblitespi.a
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitespi'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitedram'
   CC       sdram.o
   CC       bist.o
   CC       sdram_dbg.o
   AR       liblitedram.a
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitedram'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libliteeth'
   CC       udp.o
   CC       mdio.o
   AR       libliteeth.a
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/libliteeth'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitesdcard'
   CC       sdcard.o
   CC       spisdcard.o
   AR       liblitesdcard.a
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitesdcard'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitesata'
   CC       sata.o
   AR       liblitesata.a
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/liblitesata'
  make: Entering directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/bios'
   CC       isr.o
   CC       boot.o
   CC       cmd_bios.o
   CC       cmd_mem.o
   CC       cmd_boot.o
   CC       cmd_i2c.o
   CC       cmd_spiflash.o
   CC       cmd_litedram.o
   CC       cmd_liteeth.o
   CC       cmd_litesdcard.o
   CC       cmd_litesata.o
   CC       sim_debug.o
   CC       main.o
   CC       bios.elf
  chmod -x bios.elf
   OBJCOPY  bios.bin
  chmod -x bios.bin
  python3 -m litex.soc.software.mkmscimg bios.bin --little
  python3 -m litex.soc.software.memusage bios.elf /home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf
  readelf: Warning: Bogus end-of-siblings marker detected at offset 4c in .debug_info section
  readelf: Warning: Bogus end-of-siblings marker detected at offset 4d in .debug_info section
  readelf: Warning: DIE at offset 0x4e refers to abbreviation number 3 which does not exist
  
  ROM usage: 20.36KiB     (63.62%)
  RAM usage: 1.36KiB  (16.99%)
  
  make: Leaving directory '/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/bios'
  &gt;&gt;&gt;/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/bios/bios.bin&lt;&lt;&lt;
  &gt;&gt;&gt;/home/anteino/shared_work/litex/linux-on-litex-vexriscv/build/sim/software/bios/bios.bin&lt;&lt;&lt;
  INFO:SoC:Initializing ROM rom with contents (Size: 0x5180).
  INFO:SoC:Auto-Resizing ROM rom from 0x8000 to 0x5180.
  &gt;&gt;&gt;images/Image&lt;&lt;&lt;
  Traceback (most recent call last):
    File &quot;./sim.py&quot;, line 230, in &lt;module&gt;
      main()
    File &quot;./sim.py&quot;, line 202, in main
      soc = SoCLinux( i!=0,
    File &quot;./sim.py&quot;, line 105, in __init__
      ram_init = get_mem_data({
    File &quot;/home/anteino/shared_work/litex/litex/litex/soc/integration/common.py&quot;, line 46, in get_mem_data
      raise OSError(f&quot;Unable to find {filename} memory content file.&quot;)
  OSError: Unable to find images/Image memory content file.
  </code></pre>
  <p>I tried searching the LiteX wiki and using google but I cannot find a solution and I have also not figured out one myself. Can somebody who has experience with LiteX please assist me?</p>