title: What is the proper letter case to use in VHDL?
body: <p>The last few days I'm writing some VHDL code for my final project. I'm quite used to languages having a common-accepted syntax, for example, the letter case for variables, constants, keywords, etc. However, in VHDL, case-insensitivity makes the language quite easy to write when you're a newbie, but after a while your code looks a total mess!</p>
  
  <p>My confusion comes also from the fact that, for example, in <a href="https://rads.stackoverflow.com/amzn/click/com/0262162245" rel="nofollow noreferrer" rel="nofollow noreferrer">Volnei Pedroni's "Circuit Design with VHDL"</a> keywords like <strong>architecture</strong> or <strong>begin</strong> are written in capitals. On the other hand, when Xilinx tools autogenerate some code, these particular keywords are in lowercase.</p>
  
  <p><strong>The actual question:</strong></p>
  
  <p>Is there a "good-habit" or a common industry practice about the issue? I know that it isn't THAT important, but I'd like to know how the professionals manage this kind of issues.</p>