title: reg instantiate with 1 in verilog
body: <p>I'm making a simple project with leds blinking every second. Led 1 and 3 blink alternating to led 2 and 4. I've written the following Verilog code:</p>
  <pre><code>    module leds_blinking(input i_Clk,
  output o_LED_1,
  output o_LED_2,
  output o_LED_3,
  output o_LED_4);
  
  parameter c_CYCLESINSECOND = 50_000_000;
  
  reg r_LED_1 = 1;
  reg r_LED_2 = 0;
  reg r_LED_3 = 1;
  reg r_LED_4 = 0;
  reg [32:0] r_Count = 0;
  
  always @(posedge i_Clk)
  begin
      if (r_Count &lt; c_CYCLESINSECOND)
          r_Count &lt;= r_Count + 1;
      else if (r_Count == c_CYCLESINSECOND)
      begin
          r_LED_1 &lt;= ~r_LED_1;
          r_LED_2 &lt;= ~r_LED_2;
          r_LED_3 &lt;= ~r_LED_3;
          r_LED_4 &lt;= ~r_LED_4;
          r_Count &lt;= 0;
      end
      else 
          r_Count &lt;= 0;
  end
  
  assign o_LED_1 = r_LED_1;
  assign o_LED_2 = r_LED_2;
  assign o_LED_3 = r_LED_3;
  assign o_LED_4 = r_LED_4;
  
  endmodule
  </code></pre>
  <p>All LEDs are active at the same time, though I instantiated 1,3 other than 2,4.</p>