title: How do I fix "Error-[IBLHS-NT] Illegal behavioral left hand side"?
body: <p>I am trying to debug this code shown below. I can not get it to work at all. The attached Verilog file has two modues: 1)  "equality" which defines the Device Under Test (DUT) and 2) "test" which generates the inputs to test the DUT. The module "equality" has a coding error.  Let me know if you can give me a hint. Thanks!</p>
  
  <p>The errors I am receiving are:</p>
  
  <pre><code>Error-[IBLHS-NT] Illegal behavioral left hand side
  ECE413/src/Equality_bugs_Test_Bench.v, 7
    Net type cannot be used on the left side of this assignment.
    The offending expression is : Equal
    Source info: Equal = 1;
  
  Error-[IBLHS-NT] Illegal behavioral left hand side
  ECE413/src/Equality_bugs_Test_Bench.v, 9
    Net type cannot be used on the left side of this assignment.
    The offending expression is : Equal
    Source info: Equal = 0;
  </code></pre>
  
  <p>My SystemVerilog Code is:</p>
  
  <pre><code>module equality (Equal, a, b); // This module defines the DUT.
   input[3:0] a, b;
   output Equal;
   always @ (a or b)
     begin
        if (a == b)
           Equal = 1;
        else
           Equal = 0;
      end
  endmodule
  //
  //
  //
  module test; // This is the test bench. It specifies input signals to drive the DUT.
  
   reg [3:0] a, b;
   wire Equal;
  
  equality Eq1 (Equal, a, b); // This line instantiates the DUT.
  
  initial 
    begin
       a = 4'b0000; // Initialize "a" to 0.
       b = 4'b0000; // Initialize "b" to 0.
       #512 $finish; // Simulate for 32x16 = 512 time steps to exercise the entire truth table.
            // (32 steps/cycle x 16 cycles)
  
    end
  
  // The next four lines clock the bits of input "b" so as to count up from 0 to 15.
    always  #2 b[0] = ~b[0]; // (Note: all procedural blocks run concurrently.)
    always  #4 b[1] = ~b[1]; 
    always  #8 b[2] = ~b[2];
    always #16 b[3] = ~b[3]; // One complete cycle is 2x16 = 32 time steps.
  
    always #32 a = a+1; // "a" is incremented by one after each complete count of "b".  
  
  endmodule 
  </code></pre>