title: How can I create a latch in Verilog
body: <p>I have a CPLD with a digital input representing a reset button. When the reset button is pressed, the signal goes high. What I need to do is have a register whose value tells if the button has <em>ever</em> been pressed. Basically a latch. When the button goes high, a latch register goes high and stays high forever.</p>
  
  <p>I thought this would be straightforward, but I got a bunch of warnings when I tried to code it up. A little Googling showed "Don't make latches in HDL! Bad practice!", but I don't really see the alternative here.</p>
  
  <p>Here's my attempt. clk_10m is a fast free-running clock, pwr_off_req is the button input.</p>
  
  <pre><code>reg pwr_off_req_latched = 0;
  
  always @ (clk_10m or pwr_off_req) begin
  
     if (pwr_off_req == 1'b1)
        pwr_off_req_latched &lt;= 1'b1;   
     else
        pwr_off_req_latched &lt;= pwr_off_req_latched;
        // I tried this to make sure it's always set to something          
  end
  </code></pre>