title: VHDL - Object "x" is used but not declared
body: <p>Im new to VHDL and I'm doing some university exercises. It was all great until today when I got an error that I don't understand the reason of why it appears. Hope you could help me. (Software: Quartus Prime)</p>
  <p>Code:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  
  entity AddSub4 is
   port(a, b : in std_logic_vector(3 downto 0);
          sub  : in std_logic;
          s    : out std_logic_vector(3 downto 0);
          cout : out std_logic);
  end AddSub4;
  
  architecture Structural of AddSub4 is
  
    signal s_b : std_logic_vector (3 downto 0);
  
  begin
      
  sub_mux: s_b &lt;= b when (sub='0') else
              not b;
  
  final: entity work.Adder4(Structural)
           port map(cin  =&gt; sub,
                       a    =&gt; a,
                       b    =&gt; b,
                       cout =&gt; cout,
                       s    =&gt; s);
  end Structural;
  
  architecture Behave of AddSub4 is
  
      signal val1, val2, valFinal : unsigned(4 downto 0);
      
  begin
  
      val1     &lt;= '0' &amp; unsigned(a);
      val2     &lt;= '0' &amp; unsigned(b);
      valFinal &lt;= (val1 + val2) when (sub = '0') else (val1 - val2);
      s        &lt;= std_logic_vector(valFinal(3 downto 0));
      cout     &lt;= std_logic(valFinal(4));
  
  end Behave;
  </code></pre>
  <p>The error in the terminal:</p>
  <pre><code>Error (10482): VHDL error at AddSub4.vhd(30): object &quot;unsigned&quot; is used but not declared
  </code></pre>