title: Approach to design valid/ready handshake
body: <p>I have implemented valid/ready handshake signals in verilog. I just wanted to know if my approach is right or something is wrong. I shall be happy to know of any improvement.
  A simple counter is used as an input to fifo. So when fifo is almost full which is declared when used word of fifo is 8 (8 stacks of fifo are used out of 16), ready is zero. </p>
  
  <p>Here is the code.</p>
  
  <pre><code>module fifohandshake(
  input CLK,
  input RST,
  input [31:0] INPUT,
  output [31:0] OUTDATA,
  output [3:0] usedword,
  output Writereq,
  input RDReq,
  output Almost_full,
  output EMPty,
  output FUlL,
  output VALID,
  output READY
  );
  
  reg valid;
  reg ready;
  reg WRReq;
  
  assign VALID=valid;
  assign READY=ready;
  assign Writereq=WRReq;
  
  fifoip u0(
      .clock(CLK),
      .data(INPUT),
      .rdreq(RDReq),
      .sclr(RST),
      .wrreq(WRReq),
      .almost_full(Almost_full),
      .empty(EMPty),
      .full(FUlL),
      .q(OUTDATA),
      .usedw(usedword)
  );
  
  
  always @(posedge CLK)
      begin
              if(INPUT)
                  begin
                      valid&lt;=1;
                  end
              else
                  begin
                      valid&lt;=0;
                  end
      end
  
  always @(posedge CLK)
      begin
          if(Almost_full)
              begin
                  ready&lt;=0;
              end
          else
              begin
                  ready&lt;=1;
              end
      end
  
  always @(posedge CLK)
      begin
          if(ready)
              begin
                  WRReq&lt;=1;
              end
          else
              begin
                  WRReq&lt;=0;
              end
      end
  endmodule
  </code></pre>
  
  <p>Have I done it in a right way or is there something that I need to correct? Here are the waveform results.
  <a href="https://i.stack.imgur.com/2vHbX.gif" rel="nofollow noreferrer">enter image description here</a></p>