title: Verilog module instantiation
body: <p>I am having a bit of trouble instantiating a module in verilog. I am using the Altera Quartus platform to develop and simulate the verilog code.</p>
  
  <p>I have followed this example (among several others):
  <a href="http://www.asic-world.com/verilog/verilog_one_day4.html" rel="nofollow noreferrer">http://www.asic-world.com/verilog/verilog_one_day4.html</a></p>
  
  <p>I have written a module (maximum) which finds the maximum between two signed inputs. </p>
  
  <p>Another module I am developing is a systolic array for genetic sequence alignment. The details are not important, however when I try to instantiate a maximum module I get an error. </p>
  
  <p>This is my code so far:</p>
  
  <pre><code>module maximum (a, b, out);
  input signed [15:0] a;
  input signed [15:0] b;
  output reg signed [15:0] out;
    always @* begin
      if (a&gt;b)
        assign out = a;
      else
        assign out = b;
    end
  endmodule
  </code></pre>
  
  <p>and I instantiate in  another module systolic_PE (all of this is in the same file seqalign.v)</p>
  
  <pre><code>maximum m0(.a(tempB), .b(diag), .out(tempA));
  </code></pre>
  
  <p>And I get the error :</p>
  
  <blockquote>
    <p>'Verilog HDL syntax error at seqalign.v(139) near text "m0"; expecting
    "&lt;=" or "="'</p>
  </blockquote>
  
  <p>I checked everything I have done so far, and I cant seem to see anything I have missed out on.. could anyone be kind enough to guide me?</p>
  
  <p>Also on a side note:
  <a href="https://stackoverflow.com/questions/14522422/instantiation-of-a-module-in-verilog">Instantiation of a module in verilog</a></p>
  
  <p>I was trying to instantiate my module in a if statement, so I tried outside of the if statement in a always @(posedge clk) block, and I get the error</p>
  
  <blockquote>
    <p>HDL syntax error at seqalign.v(88) near text "("; expecting ";"</p>
  </blockquote>