title: Verilog : For loop inside an always
body: <p>I am trying to implement a module that use a for loop inside a always block
  We are using an array of 0 &amp; 1 in order to record the number of signal received during a certain time.</p>
  
  <p>Unfortunatly we received that kind of error :</p>
  
  <pre><code>ERROR:Xst:2636 - "Tourniquet.v" line 54: Loop has iterated 10000 times. Use "set -loop_iteration_limit XX" to iterate more.
  </code></pre>
  
  <p>It seems that the for loop isn't allowed inside a always block (The n doesn't seems to reset).
  I have looked at various website and forum but don't have found any solutions.</p>
  
  <p>Here is my code : </p>
  
  <pre><code>  module Tourniquet(
      input t0,
      input mvt,
       input clk,
      output init
      );
  
  reg initialisation;
  reg [0:99] memoire;
  reg count = 0;
  reg compteur = 0;
  reg n;
  
  assign init = initialisation;
  
  always @(posedge clk) 
  begin
      if (count==99) 
      begin 
              if (mvt)
              begin 
              memoire[count]=1;
              count=0;
              end
  
              else
              begin 
              memoire[count]=0;
              count=0;
              end
      end 
  
      else
      begin 
              if (mvt)
              begin 
              memoire[count]=1;
              count = count + 1;
              end
  
              else
              begin 
              memoire[count]=0;
              count = count + 1;
              end
      end
  end
  
  always @(posedge clk) 
  begin
  initialisation = 0;
  for (n=0; n&lt;99; n=n+1) compteur = compteur + memoire[n];
  if (compteur&gt;10) initialisation = 1;
  compteur = 0;
  end
  
  endmodule
  </code></pre>
  
  <p>I can't find the solution nor be sure of what is the problem, any tips or help is welcomed.
  Thank you very much !</p>