title: SystemVerilog: Parameter used in concatenation gives error with irun
body: <p>Cadence irun gives error for below code, where fifo_depth_base2 is parameter as below:</p>
  
  <blockquote>
    <p>ncvlog: *E,NONOWD (buff_mgr.v,17|46): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].</p>
  </blockquote>
  
  <p>I can understand this error, but my question is how would I otherwise assign it for parameterized design.</p>
  
  <pre><code>// rd pointer and read logic
  always @(posedge clk or posedge rst) begin
      if(rst) rd_ptr &lt;= 0;
  else begin  
      case({flush, rd})
          2'b10, 2'b11: rd_ptr &lt;= {fifo_depth_base2{'b0}}; // error here
          ...
   endcase
  end
  end
  </code></pre>