title: VHDL When statement with multiple conditions
body: <p>I am new to VHDL. I am trying to set a signals value based on the state of multiple conditions. It is outside of a process block. Is what I am trying to do even possible? If so, what am I doing wrong?</p>
  
  <p>This is what I have so far:</p>
  
  <pre><code>signal1&lt;= my_data
  WHEN ( bit_cond_true
  AND (my_array /= X"00000") 
  AND (my_array = another_array))
  ELSE
  other_data;
  </code></pre>
  
  <p>This is what happens when I try to compile it in ModelSim:</p>
  
  <pre><code>** Error: file.VHD(62): No feasible entries for infix operator "and".
  ** Error: file.VHD(62): Bad expression in left operand of infix expression "and".
  ** Error: file.VHD(62): Type error resolving infix expression "and" as type   std.standard.boolean.
  ** Error: file.VHD(67): No feasible entries for infix operator "and".
  ** Error: file.VHD(66): Bad expression in left operand of infix expression "and".
  ** Error: file.VHD(67): Type error resolving infix expression "and" as type std.standard.boolean.
  ** Error: file.VHD(100): VHDL Compiler exiting
  </code></pre>