title: What is the difference between == and === in Verilog?
body: <p>What is the difference between:</p>
  
  <pre><code>if (dataoutput[7:0] == 8'bx) begin
  </code></pre>
  
  <p>and</p>
  
  <pre><code>if (dataoutput[7:0] === 8'bx) begin 
  </code></pre>
  
  <p>After executing <code>dataoutput = 52'bx</code>, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)</p>