title: Displaying a bus in Verilog
body: <p>I'm writing a code in Verilog which would count till 15 on every edge of a clock and would go back to 0. However, I'm not able to display waveforms. All I can see is Z (high impedance).</p>
  
  <pre><code>`timescale 1ns / 1ps
  
  
  module Counter(
  input ck,
  output [3:0] a
  
  );
  
  reg a;
  
  reg [3:0] i = 4'b0000;
  always@(posedge ck)
  begin
      a = i;
  
      if(i==15)
      i = 0;
  
      else
      i = i+1;
  end
  
  endmodule
  </code></pre>
  
  <p>Here is the testbench to drive it:</p>
  
  <pre><code>module Counter_tb;
  
  wire clock;
  wire [3:0] ta;
  
  Clocker mygate(.clk(clock));
  
  Counter mygate2(.ck(clock), .a(ta));
  
  initial
  begin
      $display(ta, clock);
  
  end
  endmodule
  </code></pre>
  
  <p>The waveform of clock is displayed properly, but not ta. What could be the possible mistake?</p>