title: Makefile: Error during make
body: <p>I have the following two makefiles:</p>
  
  <p>Makefile1:</p>
  
  <pre><code>SUBDIRS = src
  SDIRS=src
  TOP?=.. 
  RECURSIVE_MAKE= [ -n "$(SDIRS)" ] &amp;&amp; for i in $(SDIRS) ; do \
              (cd $$i &amp;&amp; echo "making $$target in $(DIR)/$$i..." &amp;&amp; \
              $(MAKE) -e TOP=$(TOP)/.. $$target INCLUDES='$(INCLUDES)') || exit 1; \
          done;
  
  subdirs:
      @target=all; $(RECURSIVE_MAKE)
  
  all: subdirs
  
  include $(BUILD_TOP)/build_control/symstream/subdirs.mk
  </code></pre>
  
  <p>Makefile2 (subdirs.mk): </p>
  
  <pre><code>#   This is a stand-alone file to distribute targets to
  #   sub-directories. Include this file alone.  
  
  #  Make bug: It loses track of if/endif over a $(eval) call.
  ifndef __subdirs_include
  __subdirs_include = yes
  
  #   This only works for the standard targets defined in $(TARGETS)
  #   in utils.mk. However this list can be extended with +=.
  
  install:: install-hdrs 
  
  include $(BUILD_TOP)/build_control/symstream/utils.mk
  include $(BUILD_TOP)/build_control/symstream/platform.mk
  
  #  This creates a recursion rule for each pair of target and subdirectory.
  #  The target for doing T in directory D is named T+D. 
  #  If there is a "$(D_needs) = subdirs" then the subdirs become prerequisites
  #  of D.
  define __target_subdir
  .PHONY:: $(1)+$(2)
  $(1)+$(2) :: $(3); +$(MAKE) -C $(2) $(1)
  endef
  
  $(foreach t,$(TARGETS),\
      $(foreach d,$(strip $(SUBDIRS) $(SUBDIRS_y)),\
      $(eval $(call __target_subdir,$(t),$(d),$(patsubst %,$(t)+%,$($(d)_needs))))))
  
  $(foreach t,$(TARGETS),\
      $(foreach d,$(strip $(SUBDIRS) $(SUBDIRS_y)),$(eval $(t)::$(t)+$(d))))
  
  
  endif # __subdirs_include
  </code></pre>
  
  <p>I am getting the following error when Makefile1 is executed: </p>
  
  <pre><code>subdirs.mk:30: *** target file `all' has both : and :: entries.  Stop.
  </code></pre>
  
  <p>Could someone please help with this?</p>