title: simple pipelining and superscalar architecture
body: <p>consider this instruction flow diagram....</p>
  
  <blockquote>
    <p>instruction fetch->instruction decode->operands fetch->instruction execute->write back</p>
  </blockquote>
  
  <p>suppose a processor that supports </p>
  
  <blockquote>
    <p>both cisc and risc...like intel 486</p>
  </blockquote>
  
  <p>now if we issue a risc instruction it takes one clock cycle to execute and so there is no problem...but if a cisc instruction is issued its execution will take time...</p>
  
  <blockquote>
    <p>so let it takes three clock cycles to execute the cisc instruction and one clock cycle each is taken by the stages preceeding execution....</p>
  </blockquote>
  
  <p>now in a superscalar structure the two instructions issued while the first is being processed are diverted into other functional units available...but there is no such diversion possible in simple pipelining as only one functional unit is available for execution of instructions....</p>
  
  <blockquote>
    <p>so  what avoids the congestion of instructions in simple pipelining case? </p>
  </blockquote>