title: VHDL Need pin to stay high for (exactly) one second, then switch to low automatically. triggered manually ( not syncronized )
body: <p>So...i need an output pin to stay high for a second and switch back to low. It is triggered manually by a user pressing a button, changing state in a FSM with a much higher speeded clock. </p>
  
  <pre><code>entity red_green is
  
      port(
          clk      : in   std_logic;
          reset : in std_logic;
          in_red, in_green : in std_logic;
          out_green, out_red : out std_logic
  
      );
  
  end entity;
  
  architecture r_g of red_green is
  signal i_clk, trigger : std_logic;
  signal i_reset : std_logic;
  
  begin
  
  process(in_red, in_green, clk )
  begin
  
      if in_red = '1' then
          out_red &lt;= '1';
      elsif rising_edge(i_clk) then
          out_red &lt;= '0';
      end if;
  
      if in_green = '1' then
          out_green &lt;= '1';
      elsif rising_edge(i_clk) then
          out_green &lt;= '0';
      end if;
  
  end process;
  
  
  clock : entity work.clock_gen port map( clk =&gt; clk, reset =&gt; reset, speed =&gt; '0', clk_out =&gt; i_clk );
  
  end r_g;
  </code></pre>
  
  <p>The clock_gen component just divides a 50 MHz clock downto 1 Hz by a counter process.
  The code sort of Works, but the "lenght" of the high on the outputs alters from time to time. I guess depending on the counter value in the clock_gen component.</p>
  
  <p>How do i ensure that i get the same "high time" on my output every time?
  Using Altera DE2</p>