title: Pseudo Random Number Generator using LFSR in VHDL
body: <p>I'm having a bit of trouble creating a prng using the lfsr method. Here is my code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity pseudorng is
  Port ( clock : in STD_LOGIC;
         reset : in STD_LOGIC;
         Q : out STD_LOGIC_VECTOR (7 downto 0);
         check: out STD_LOGIC);
  
         constant seed: STD_LOGIC_VECTOR(7 downto 0) := "00000001";
  end pseudorng;
  
  architecture Behavioral of pseudorng is
  
  signal temp: STD_LOGIC;
  signal Qt: STD_LOGIC_VECTOR(7 downto 0);
  
  begin
  
  PROCESS(clock)
  BEGIN
  
  IF rising_edge(clock) THEN
  IF (reset='1') THEN Qt &lt;= "00000000";
  ELSE Qt &lt;= seed; 
  END IF;
  temp &lt;= Qt(4) XOR Qt(3) XOR Qt(2) XOR Qt(0);
  --Qt &lt;= temp &amp; Qt(7 downto 1);
  
  END IF;
  END PROCESS;
  
  check &lt;= temp;
  Q &lt;= Qt;
  
  end Behavioral;
  </code></pre>
  
  <p>Here is the simulation I have ran:
  <a href="https://i.stack.imgur.com/uqdeU.png" rel="nofollow noreferrer">prng sim</a></p>
  
  <p>Firstly, the check output is just there so I can monitor the output of the temp signal. Secondly, the line that is commented out is what is causing the problem.</p>
  
  <p>As can be seen from the simulation, on the first rising edge of the clock, the Qt signal reads the seed. However, and this is my question, for some reason the temp signal only XORs the bits of the Qt signal on the second rising edge of the clock. It remains undefined on the first clock pulse. Why is that? If it operated on the first rising edge right after the Qt signal reads the seed, then I could uncomment the line that shifts the bits and it would solve my problem. Any help would be much appreciated!</p>
  
  <p>Here is the test bench if anyone cares:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity tb_pseudorng is
  end tb_pseudorng;
  
  architecture bench of tb_pseudorng is
  
  COMPONENT pseudorng
        Port ( clock : in STD_LOGIC;
        reset : in STD_LOGIC;
        Q : out STD_LOGIC_VECTOR (7 downto 0);
        check: out STD_LOGIC);
  END COMPONENT;
  
  signal clock1: STD_LOGIC;
  signal reset1: STD_LOGIC;
  signal Q1: STD_LOGIC_VECTOR(7 downto 0);
  signal check1: STD_LOGIC;
  
  begin
  
  mapping: pseudorng PORT MAP(
  clock =&gt; clock1,
  reset =&gt; reset1,
  Q =&gt; Q1,
  check =&gt; check1);
  
  clock: PROCESS
  BEGIN
  clock1&lt;='0'; wait for 50ns;
  clock1&lt;='1'; wait for 50ns;
  END PROCESS;
  
  reset: PROCESS
  BEGIN
  reset1&lt;='0'; wait for 900ns;
  END PROCESS; 
  
  end bench;
  </code></pre>