title: Where is the Write-Combining Buffer located? x86
body: <p>How is the Write-Combine buffer physically hooked up? I have seen block diagrams illustrating a number of variants:</p>
  
  <ul>
  <li>Between L1 and Memory controller</li>
  <li>Between CPU's store buffer and Memory controller</li>
  <li>Between CPU's AGUs and/or store units</li>
  </ul>
  
  <p>Is it microarchitecture-dependent? </p>