title: How does the synthesizer decides on bitwdith for intermediate results?
body: <p>Consider the following module:</p>
  
  <pre><code> module power(input  [11-1:0] xi,xq,output [22-1:0] y);
      assign y = xi*xi + xq*xq;
    endmodule
  </code></pre>
  
  <p>I know that my single assignment is actually decomposed of 3 steps: 2 squares and one addition. My question is  how would the synthesizer decides on the bitwidth of the intermediate steps <code>xi*xi</code> and <code>xq*xq</code>? </p>
  
  <p>I noticed that when running <em>logic equivelance circuit (lec)</em> for the above code, it causes trouble and could only be solved by decomposing the single assignment into three assignments as follows:</p>
  
  <pre><code> module power(input  [11-1:0] xi,xq,output [22-1:0] yy);
      wire [21-1:0] pi,pq;
      assign pi = xi*xi;
      assign pq = xq*xq;
      assign yy = pi+pq;
    endmodule
  </code></pre>