title: How to 'assign' a value to an output reg in Verilog?
body: <p>( insert really basic question disclaimer here )</p>
  
  <p>More specifically, I have the following declaration:</p>
  
  <pre><code>output reg icache_ram_rw
  </code></pre>
  
  <p>And in some point of the code I need to put the zero value in this reg. Here's what I've tried and the outcomes:</p>
  
  <pre><code>assign icache_ram_rw = 1'b0;
  ( declarative lvalue or port sink reg icache_ram_rw must be a wire )
  
  icache_ram_rw &lt;= 1'b0;
  ( instance gate/name for type "icache_ram_rw" expected - &lt;= read )
  </code></pre>
  
  <p>How do I do it after all?!</p>