title: For-loop in Verilog
body: <p>I am new to Verilog so I am having some problems working with if</p>
  
  <p>Basically I have a 5 bit number, and a want to split it so I can have a 2 digits decimal number. For doing so I have this piece of code</p>
  
  <pre><code>reg [4:0] position, aux;
  reg [3:0] display1, display2;
  reg [2:0] secondDigit;
  
  always @(negedge iKEY[1] or negedge iKEY[2]) begin
      aux = position;
  
      for(secondDigit = 2'b0; aux &gt;= 5'b01010; secondDigit = secondDigit + 2'b01)
          aux = aux - 5'b01010;
  
      assign display1 = aux[3:0];
      assign display2 = {2'b0, secondDigit};
  
  end
  </code></pre>
  
  <p>The problem is I am getting this message of  </p>
  
  <pre><code>loop with non-constant loop condition must terminate within 250 iterations
  </code></pre>
  
  <p><br/>
  I also tried substituting the for loop for this while, but keep getting the same error</p>
  
  <pre><code>aux = position;
  secondDigit = 2'b0;
  while(aux &gt; 5'b01010) begin
      aux = aux - 5'b01010;
      secondDigit = secondDigit + 2'b01;
  end
  </code></pre>
  
  <p>Can somebody help me?
  Thank you</p>