title: Assigning entire array in verilog
body: <p>I am trying to copy a 2d array into another like so:</p>
  
  <pre><code>reg [11:0] input_matrix [0:array_width - 1] [0:array_height - 1]; 
  reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1];
  always @(posedge clk)
  begin
       if(&lt;some condition&gt;)
            output_matrix &lt;= input_matrix;
  end
  </code></pre>
  
  <p>So, we have two 2D arrays of 12-bit values. I'd like to copy one into the other. </p>
  
  <p>This doesn't seem to be possible. Does anyone know the correct way to do this? Or, if not, explain why it's not possible? I can't see any reason why this assignment wouldn't be able to synthesize. </p>
  
  <p>For loops generally don't synthesize well, for obvious reasons. However, is this one of the cases that a for loop can be used, because the loop is statically defined? </p>