title: Structural 4 bit ring counter with D flip flop. VHDL / GHDL
body: <p>I don't know how to do this with structural programming...</p>
  <p>&quot;A binary counter (with reset signal) of 4 bits made of 4 D flip flops.&quot;</p>
  <p>How to connect in/outs?</p>
  <p>Here is the entity declarations. The core of the problem is at the last lines.</p>
  <pre><code>                    --FFD
              entity FFD is
              port( CLK, D, reset : in STD_LOGIC;
                  Q : out STD_LOGIC
                 );
              end FFD;
              
              architecture behaviour of FFD is
              begin
                  process(CLK, reset)
                  begin
                  if reset='1' then Q&lt;='0';  
                  elsif (clk'event and clk='1') then Q&lt;=D;
                  else null;
                  end if;
                  end process;
              end behaviour;
          ----------------------------------------------------------  
              
          --counter
  
          library IEEE;
          use IEEE.std_logic_1164.all;
          use IEEE.numeric_std.all;
  
              entity counter is
              port(clk : in std_logic;
                 reset : in std_logic;
                 count : out std_logic_vector(3 downto 0));
              end entity counter;
  
                  architecture rtl of counter is
              
              --
              component FFD 
              port (CLK, D, reset : in STD_LOGIC;
                         Q : out STD_LOGIC);
              end component;
              
              signal q0,q1,q2: std_logic:='0';
              signal q3: std_logic:='1';
              
              begin
              -- 
  
              ---
              inst1: FFD port map (CLK=&gt;clk, D=&gt;q3, reset=&gt;reset, Q=&gt;q0);
              inst2: FFD port map (CLK=&gt;clk, D=&gt;q0, reset=&gt;reset, Q=&gt;q1);
              inst3: FFD port map (CLK=&gt;clk, D=&gt;q1, reset=&gt;reset, Q=&gt;q2);
              inst4: FFD port map (CLK=&gt;clk, D=&gt;q2, reset=&gt;reset, Q=&gt;q3);
              inst5: count&lt;=q3&amp;q2&amp;q1&amp;q0;
              end architecture rtl;
  </code></pre>
  <p>My problem is in this last lines.</p>