title: Using SystemVerilog structs that contain parameters as input/output ports to a module
body: <p>My struct contains parameters that vary per module. I'd like to use this struct to pass input/outputs to these modules. I'm using this for design so it has to be synthesizable and my toolchain doesn't support Interfaces unfortunately.</p>
  
  <p>For example:</p>
  
  <pre><code>`ifdef MY_STRUCTS
  `define MY_STRUCTS
  typedef struct packed {
    logic [PARAMETER_VAL-1:0] field1;
    logic [PARAMETER1_VAL-1:0] field2;
  } myStruct_t;
  `endif
  
  module top #(
    parameter PARAMETER_VAL = 8;
    parameter PARAMETER1_VAL = 16;
  ) (
    input myStruct_t in_packet,
    output myStruct_t out_packet,
  );
  </code></pre>
  
  <p>Unfortunately, this seems to be a chicken-or-egg problem. The struct definition can't be compiled because it relies on the module parameters to define it. However, the input/output declarations can't be declared because it relies on the struct to know what to declare.</p>
  
  <p>Does anyone have a solution to this? Would definitely appreciate suggestions.</p>