title: VHDL Saving input value into another signal
body: <p>I have a question for my VHDL code. My entire code has to do the following:</p>
  
  <ul>
  <li>input = Minutes + hours + clk</li>
  <li>output = AFTER 1 minute: minuten = minuten + 1 (and if needed hours += 1)</li>
  </ul>
  
  <p>So I built a counter, which counts (well for simulation easyness to 1/10th of a second instead of a minute) clock periods untill one minute is over. Then it raises the minute by 1, and send that to the output. I got one problem however: due to setup violation I can't simulate the synthesis well. I thought this violation was in the line: min_save = minutes. I think that it's impossible to save the input minutes immediately, so I thought: let's build another counter, which counts 1 clock period, and then saves it. </p>
  
  <p>So my 2 questions:</p>
  
  <ul>
  <li>Does this indeed solve the setup violation?</li>
  <li>If so: why does the signal setup have no value. It has a value of undefined. What do i do wrong?</li>
  <li>If not: why not, and how can I solve this then?</li>
  </ul>
  
  <p>CODE:</p>
  
  <pre><code>architecture behaviour of internclk_u is
  begin
  process (minuten)
  begin                -- switching input minutes to binary. 
    minintern(6) &lt;= minuten(0);
    minintern(5) &lt;= minuten(1);
    minintern(4) &lt;= minuten(2);
    minintern(3) &lt;= minuten(3);
    minintern(2) &lt;= minuten(4);
    minintern(1) &lt;= minuten(5);
    minintern(0) &lt;= minuten(6);
  end process;
  
  process (uren)
  begin                        -- switching input hours to binary
    uurintern(5) &lt;= uren(0);
    uurintern(4) &lt;= uren(1);
    uurintern(3) &lt;= uren(2);
    uurintern(2) &lt;= uren(3);
    uurintern(1) &lt;= uren(4);
    uurintern(0) &lt;= uren(5);
  end process;
  process (clk)
  begin   
      setup &lt;= '0';
      if(clk'event and clk = '1') then
              if(setup &lt; '1') then
                      setup &lt;= '1';
              else
                      setup &lt;= setup;
                      if(min_save = minutes) then
                      count &lt;= new_count;
                      else
                      min_save &lt;= minutes;
                      count &lt;= (others =&gt; '0');       
                      end if;
              end if;
      end if;
  end process;
  
  process (count, minintern)
  begin                   -- count one minute (now its 0.1 second)
  if(count &lt; F/10 ) then
      new_count &lt;= count + 1;
      intern_out &lt;= minintern;
      uurintern_out &lt;= uurintern;
  else
      case minintern is               -- Calculate new value for output
      when "0001001" =&gt; intern_out    &lt;= "0010000";
                        uurintern_out &lt;= uurintern;
      when "0011001" =&gt; intern_out    &lt;= "0100000";
                        uurintern_out &lt;= uurintern;
      when "0101001" =&gt; intern_out    &lt;= "0110000";
                        uurintern_out &lt;= uurintern;
      when "0111001" =&gt; intern_out    &lt;= "1000000";
                        uurintern_out &lt;= uurintern;
      when "1001001" =&gt; intern_out    &lt;= "1010000";
                        uurintern_out &lt;= uurintern;
      when "1011001" =&gt; intern_out    &lt;= "0000000";
                        case uurintern is
                          when "001001" =&gt; uurintern_out &lt;= "010000";
                          when "011001" =&gt; uurintern_out &lt;= "100000";
                          when others   =&gt; uurintern_out &lt;= uurintern + 1;
                          end case;
      when others       =&gt; intern_out    &lt;= minintern + 1;
                        uurintern_out &lt;= uurintern;
      end case;
      new_count &lt;= count;
      setup &lt;= '0';
  end if;
  end process;
  
  process (intern_out)   -- Reversing signals for next blocks in system
  begin
    interne_tijd_m(6) &lt;= intern_out(0);
    interne_tijd_m(5) &lt;= intern_out(1);
    interne_tijd_m(4) &lt;= intern_out(2);
    interne_tijd_m(3) &lt;= intern_out(3);
    interne_tijd_m(2) &lt;= intern_out(4);
    interne_tijd_m(1) &lt;= intern_out(5);
    interne_tijd_m(0) &lt;= intern_out(6);
  end process;
  
  process (uurintern_out)
  begin                     -- Reversing signals for next blocks in system
    interne_tijd_u(5) &lt;= uurintern_out(0);
    interne_tijd_u(4) &lt;= uurintern_out(1);
    interne_tijd_u(3) &lt;= uurintern_out(2);
    interne_tijd_u(2) &lt;= uurintern_out(3);
    interne_tijd_u(1) &lt;= uurintern_out(4);
    interne_tijd_u(0) &lt;= uurintern_out(5);
  end process;
  end behaviour;
  </code></pre>
  
  <p>Remarks:</p>
  
  <ul>
  <li>ignore the 2 case statements; this is because the inputsignals are not binary coded; they are reversed. Besides that: it doesnt count 1,2,4,8,16 etc; it counts: 1,2,4,8,10,20 etc.</li>
  </ul>
  
  <p>EDIT</p>
  
  <p>I put in the whole architecture now.
  The error message I received was something like: "Setup time violations occured(?)". So I believe I cant save the input minutes immediately when I receive minutes. Thats why I tried to program in the setup signal. Hope you guys can help. This error gave me a headache and lots of frustration already:(</p>
  
  <p>EDIT 2</p>
  
  <p>Forget about the whole "setup" signal. A student-assistent pointed out to me that the saving of the input doesnt make any sense. So my updated question is: How can I properly save the input signal/value into another signal?</p>