title: Global declarations are illegal in Verilog 2001 syntax!
body: <p>I have written something small in verilog:</p>
  
  <pre><code>`define LW 6'b100011
  
  `define SW 6'b101011
  
  parameter [3:0]
      i_fetch = 4'b0001,
      decode_rr = 4'b0010,
      mem_addr = 4'b0100,
      alu_exec = 4'b1000;
  </code></pre>
  
  <p>and i am getting this error: <strong>Error: test.v(5): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax.</strong></p>
  
  <p>What I am doing wrong? I am using ModelSim XE III/Starter 6.4b - Custom Xilinx Version!</p>