title: how to declare output array in verilog?
body: <p>I am trying to ADD two array and want output in array in verilog code. But error is occured. which is  ERROR:HDLCompiler:1335: Port sum must not be declared to be an array in verilog code  . can anyone tell me how to declare output array in verilog code. Thanks.</p>
  
  <pre><code>module array(clk,sum,reset);
              input clk,reset;
              //input [7:0] din;
              //input [7:0] A[3:0]; 
              //input [7:0] B[3:0];  
              output  sum[3:0];
              wire [7:0] sum[3:0];
              reg [7:0] A[3:0]; 
              reg [7:0] B[3:0];
              integer i;
              always@(posedge clk)
              begin 
                  if(reset==1'b1)
                      begin
                      A[0]&lt;=1;
                      A[1]&lt;=2;
                      A[2]&lt;=3;
                      A[3]&lt;=4;
                      B[0]&lt;=5;
                      B[1]&lt;=5;
                      B[2]&lt;=5;
                      B[3]&lt;=5;
                      sum[0]&lt;=0;                  
                     sum[1]&lt;=0;   
                      sum[2]&lt;=0;  
                      sum[3]&lt;=0;  
                      end 
                  else 
                      begin   
                          for(i=0;i&lt;4;i=i+1)
                              begin 
                                  sum[i]=(A[i] + B[i]);
                              end 
                   end 
                 end 
     endmodule
  </code></pre>