title: Syntax error near end in Verilog
body: <p>I'm writing a Verilog code to give all possible combinations of inputs to a 4:1 multiplexer. Here is the testbench for the same to test the code:</p>
  
  <pre><code>module FouthQuestion_tb;
  
  reg d0, d1, d2, d3, s0, s1;
  wire y;
  reg o;
  
  FourthQuestion mygate(.D0(d0), .D1(d1), .D2(d2), .D3(d3), .S0(s0), .S1(s1), .Y(y));
  
  initial
  begin
      $monitor(d0, d1, d2, d3, s0, s1, y);
      for(d0=0; d0&lt;=1; d0=d0+1)
      begin
          for(d1=0; d1&lt;=1; d1=d1+1)
          begin
              for(d2=0; d2&lt;=1; d2=d2+1)
              begin
                  for(d3=0; d3&lt;=1; d3=d3+1)
                  begin
                      for(s0=0; s0&lt;=1; s0=s0+1)
                      begin
                          for(s1=0; s1&lt;=1; s1=s1+1)
                          begin
                              #5
                          end
                      end
                  end
              end
          end
      end
  end
  
  endmodule
  </code></pre>
  
  <p>However, I'm always getting the error "syntax error near end". What could be the possible syntactical mistake that is being made here?</p>