title: Can a Port Share the Name of the Signal it's Being Mapped to in VHDL?
body: <p>Exactly as the title describes.
  There are asterisks surrounding the port and signal I am referring to. Is it conflicting in any way for a port to be named the same as the signal it is being mapped to? Or is it just good coding practice to have different names?</p>
  
  <pre><code>fml_fulladd_vhdl
      PORT MAP(
          C_in =&gt; C_in, -- this line
          x =&gt; x(3),
          y =&gt; y(3),
          s =&gt; s(3),
          C_out =&gt; C_out); -- and this line
  </code></pre>
  
  <p>Thanks to anyone who can offer help.</p>