title: What is the difference between using an initial block vs initializing a reg variable in systemverilog?
body: <p>What is the difference between the following two examples with regards to simulation?</p>
  
  <p>A)</p>
  
  <pre><code>reg a;
  initial a = 1'b0;
  </code></pre>
  
  <p>and </p>
  
  <p>B)</p>
  
  <pre><code>reg a = 1'b0;
  </code></pre>
  
  <p>Is it different for logic variables?</p>