title: How to implement a test bench file for a 8x1 Multiplexer with 32-bit line width?
body: <p>I'm writing a VHDL code to model an 8x1 multiplexer where each input has 32-bit width. So I created an array to model the MUX but now I'm stuck with the Test Bench, it's gotten so complicated. Here is my original file (I'm sure it has so many redundancies) How can I actually make the test bench to recognize my array (R_in) from the component's file and then how will I stimulate it?</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;
  
  ENTITY mux8_1 IS
     PORT(Rs  :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
      in0,in1,in2,in3,in4,in5,in6,in7 :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      R_out   :OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
         );
  END mux8_1;
  
  ARCHITECTURE behaviour OF mux8_1 IS
  
  type t_array_mux is array (0 to 7) of STD_LOGIC_VECTOR(31 DOWNTO 0);
  signal R_in:t_array_mux;
  
  BEGIN
  
  R_in(0) &lt;= in0;
  R_in(1) &lt;= in1;
  R_in(2) &lt;= in2;
  R_in(3) &lt;= in3;
  R_in(4) &lt;= in4;
  R_in(5) &lt;= in5;
  R_in(6) &lt;= in6;
  R_in(7) &lt;= in7;
  
  
  process(R_in, Rs)
  BEGIN
  
  CASE Rs IS
  
  WHEN "000"=&gt;R_out&lt;=R_in(0);
  WHEN "001"=&gt;R_out&lt;=R_in(1);
  WHEN "010"=&gt;R_out&lt;=R_in(2);
  WHEN "011"=&gt;R_out&lt;=R_in(3);
  WHEN "100"=&gt;R_out&lt;=R_in(4);
  WHEN "101"=&gt;R_out&lt;=R_in(5);
  WHEN "110"=&gt;R_out&lt;=R_in(6);
  WHEN "111"=&gt;R_out&lt;=R_in(7);
  WHEN OTHERS=&gt;R_out&lt;= (others =&gt; '0');
  
  END CASE;
  END process;
  END behaviour;
  </code></pre>
  
  <p>And here is my "in progress" test bench file. Just ignore the "stimulus process" part I know it's wrong I just couldn't figure out how to write it for a 32-bit signal.</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  use ieee.numeric_std.all;
  
  ENTITY mux8_1_TB IS
  END mux8_1_TB;
  
  ARCHITECTURE behaviour OF mux8_1_TB IS
  
  COMPONENT mux8_1
     PORT(Rs  :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
      in0,in1,in2,in3,in4,in5,in6,in7 :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      R_out   :OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
         );
  END COMPONENT;
  
  type t_array_mux is array (0 to 7) of STD_LOGIC_VECTOR(31 DOWNTO 0);
  
  --Inputs
  signal R_in:t_array_mux:=(others=&gt;'0');
  signal in0,in1,in2,in3,in4,in5,in6,in7 :STD_LOGIC_VECTOR(31 DOWNTO 0):=(others=&gt;'0');
  signal Rs  :STD_LOGIC_VECTOR(2 DOWNTO 0):=(others=&gt;'0');
  
  --Outputs
  signal R_out:STD_LOGIC_VECTOR(31 DOWNTO 0);
  
  -- Instantiate the Unit Under Test + connect the ports to my signal
  BEGIN
  
  R_in(0) &lt;= in0;
  R_in(1) &lt;= in1;
  R_in(2) &lt;= in2;
  R_in(3) &lt;= in3;
  R_in(4) &lt;= in4;
  R_in(5) &lt;= in5;
  R_in(6) &lt;= in6;
  R_in(7) &lt;= in7;
  
  uut: mux8_1 PORT MAP(
      Rs=&gt;Rs,
      R_in=&gt;R_in,
      R_out=&gt;R_out
         );
  
  -- Stimulus process (where the values -&gt; inputs are set) 
  
  PROCESS
  begin
  
  R_in&lt;="01010101";
      wait for 10 ns;
  Rs&lt;="001";
      wait for 10 ns;
  Rs&lt;="010";
      wait for 20 ns;
  Rs&lt;="011";
      wait for 30 ns;
  Rs&lt;="100";
      wait for 40 ns;
  Rs&lt;="101";
      wait for 50 ns;
  Rs&lt;="110";
      wait for 60 ns;
  Rs&lt;="111";
      wait for 70 ns;
  
  END PROCESS;
  END;
  </code></pre>