title: 4-bit register using D flip-flop with enable and asynchronous reset
body: <p>I am modelling a 4-bit register using D flip-flops with enable and asynchronous reset. It contains 4 D FF and 4 2:1 Mux. I used structural Verilog to model the circuit.</p>
  <p>My design is shown below.</p>
  <pre><code>module DFlipFlop(D,clk,reset,Q);
  input D; 
  input clk,reset; 
  output Q;
  reg Q;
  always @(posedge clk or posedge reset) 
  begin
   if(reset==1'b1)
    Q &lt;= 1'b0; 
   else 
    Q &lt;= D; 
  end 
  endmodule
  
  module m21(D0, D1, S, Y);
  output Y;
  input D0, D1, S;
  assign Y=(S)?D1:D0;
  endmodule
  
  module DFF_with_Enable(D,clk,enable,reset,Q);
    input D,clk,reset,enable;
    output Q;
    reg Q;
    wire in;
        m21 mux(D,in,enable,in);
        DFlipFlop DFF(in,clk,reset,Q); 
  endmodule
  
  module fourbitreg(D,clk,reset,enable, Q);
    input[0:3] D; // Data input
  input clk,reset,enable;
    output [3:0]Q;
    reg [3:0]Q;
    wire d0,d1,d2,d3;
    wire q0,q1,q2,q3;
    d0 = D[0];
    d1 = D[1];
    d2 = D[2];
    d3 = D[3];
    DFF_with_Enable df0(d0,clk,reset,enable,q0);
    DFF_with_Enable df1(d1,clk,reset,enable,q1);
    DFF_with_Enable df2(d2,clk,reset,enable,q2);
    DFF_with_Enable df3(d3,clk,reset,enable,q3);
          
         assign Q = {q0,q1,q2,q3};
  endmodule
  </code></pre>
  <p>I used <code>iverilog</code> for simulation. How do I fix the following errors during compilation?</p>
  <pre class="lang-none prettyprint-override"><code>design.sv:37: syntax error
  design.sv:37: error: Invalid module instantiation
  design.sv:38: error: Invalid module instantiation
  design.sv:39: error: Invalid module instantiation
  design.sv:40: error: Invalid module instantiation
  </code></pre>
  <p>The circuit of 1 DFF MUX pair is shown below.</p>
  <p><a href="https://i.stack.imgur.com/PmqzU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/PmqzU.png" alt="Circuit " /></a></p>