title: How does kernel know physical memory base address?
body: <p>I'm trying to understand 2 closely related issues.</p>
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  <li><p>Kernel code that runs post-bootloader and prior to enabling the MMU operates in physical/ identity mapped virtual memory. How is this code made portable between different CPU's might have DRAM in different physical address ranges?</p>
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  <li><p>For the kernel to manage the page table, it needs some awareness of what physical memory resources are available, including the physical memory base address and available physical memory, so it doesn't assign physical addresses that are out of DRAM range.</p>
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  <p>I imagine this is somewhat implementation dependent, but references to how different architectures handle this problem would be appreciated. Some ideas I have so far:</p>
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  <li><p>The physical address DRAM range, or at least the base address, is baked in at kernel compile time. This implies recompilation is needed for different CPU's even with the same ISA. This is inspired by this answer <a href="https://stackoverflow.com/questions/33578993/base-address-at-which-the-linux-kernel-is-loaded/57483615">here</a>, which, if I'm understanding correctly, describes the same solution for the kernel base address. Since the base address is known at compile time, kernel code references literal addresses rather than offsets from the DRAM/ kernel base address.</p>
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  <li><p>DRAM information is read and learned from the device tree with the rest of the physical memory map. This is my impression for at least Xilinx Zynq SoC's, based on forum posts like <a href="https://forums.xilinx.com/t5/Embedded-Linux/Zynq-Petalinux-reserve-a-DDR-memory-region/td-p/529237?fbclid=IwAR2zWvHtFjdb1QAOLK0y0qIMhRwzhfS6lGusZXR8S4vSOBqDALFaB0iGGlo" rel="nofollow noreferrer">this</a>. While this solution offers more flexibility and allows us to just recompile the boot loader rather than the whole kernel to port CPU's, it does leave me wondering how my X86 personal machine can detect at run-time how much DRAM I've installed. Code to manage the page table just references offsets from the DRAM base address and is portable without recompilation across CPU's with different DRAM physical address ranges.</p>
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