title: Verilog Falling Edge Detection
body: <p>I am writing the Verilog code for a UART to be implemented on a FPGA, and I have some trouble with synchronizing to the START bit of bytes after the first one.</p>
  
  <p>My manager suggested to synchronize my received signal and use some kind of interrupt as a mean of communicating to my FSM that a start has been recognized.</p>
  
  <p>I have read about techniques for rising edge detection, and I feel like I could do something like this:</p>
  
  <pre><code>module StartDetectionUnit (
      input clk, state, signal_in,
      output trigger
      );   
  
      reg signal_d;
  
      always @(posedge clk)
          begin
              signal_d &lt;= signal_in;
          end
      assign trigger = signal_in &amp; (!signal_d);
  
  endmodule    
  </code></pre>
  
  <p>In my understanding, a description like this detects a RISING edge, not a FALLING edge, but "START" is a logic '0' in RS-232 communications.</p>
  
  <p>Plus, I want to actually assign the flag just when in IDLE state [Hardcoded as 000] but doing crazy gating on the final assignments sounds non-hardwareish to me.</p>
  
  <p>tldr, two issues</p>
  
  <ol>
  <li>detecting a generic falling edge of an asynchronous input signal</li>
  <li>doing so in a single, specific state of a FSM</li>
  </ol>
  
  <p>thanks a bunch, i'm new to Verilog and kinda-new to HDL'ing</p>