title: Reaching clock regions using BUFIO and BUFG
body: <p>I need to realize a source-synchronous receiver in a Virtex 6 that receives data and a clock from a high speed ADC.
  For the SERDES Module I need two clocks, that are basically the incoming clock, buffered by BUFIO and BUFR (recommended). I hope my picture makes the situation clear.</p>
  
  <p><a href="https://i.stack.imgur.com/LSI2N.png" rel="nofollow noreferrer">Clock distribution</a></p>
  
  <p>My problem is, that I have some IOBs, that cannot be reached by the BUFIO because they are in a different, not adjacent clock region.
  A friend recommended using the MMCM and connecting the output to a BUFG, which can reach all IOBs.
  Is this a good idea? Can't I connect my LVDS clock buffer directly to a BUFG, without using the MMCM before?</p>
  
  <p>My knowledge about FPGA Architecture and clocking regions is still very limited, so it would be nice if anybody has some good ideas, wise words or has maybe worked out a solution to a similar problem in the past.</p>