title: Verilog: proper way of connecting ports
body: <p>Assume there are two different modules (<code>first_module</code>, <code>second_module</code>). Both of the modules are synchronized with clock signal. <code>first_module</code> has the following structure:</p>
  
  <pre><code>module first_module(
  input clk,
  input reset_n,
  input in1,
  output reg out1,
  output reg out2
  );
  
  //******** some verilog codes *********
  
  endmodule
  </code></pre>
  
  <p>And <code>second_module</code> has similar structure:</p>
  
  <pre><code>module second_module(
  input clk,
  input reset_n,
  input in1,
  input in2,
  output reg out1
  );
  
  //******** some verilog codes *********
  
  endmodule
  </code></pre>
  
  <p>And then there is a module called <code>top_module</code> which uses instances of both modules:</p>
  
  <pre><code>module top_module(
  input clk,
  input reset_n,
  input insignal1,
  input insignal2,
  output outsignal1,
  output outsignal2
  );
  
  first_module fm1(
    .clk(clk),
    .reset_n(reset_n),
    .in1(insignal1),
    .out1(outsignal1),
    .out2(&lt;connection1&gt;) // to be connected to the connection2 
  );
  
  second_module sm1(
    .clk(clk),
    .reset_n(reset_n),
    .in1(insignal2),
    .in2(&lt;connection2&gt;), // to be connected to the connection1
    .out1(outsignal2)
  );    
  
  endmodule
  </code></pre>
  
  <p>The aim is to connect <code>connection1</code> to <code>connection2</code>. According to my knowledge (if it is correct), we can either declare a single wire (let its name be <code>connection</code>) and replace both <code>&lt;connection1&gt;</code> and <code>&lt;connection2&gt;</code> with it, or we can declare two distinct wires <code>connection1</code> and <code>connection2</code>, then:</p>
  
  <pre><code>assign connection2 = connection1;
  </code></pre>
  
  <p>And connect them accordingly. </p>
  
  <ul>
  <li><strong>Are those two methods synthesized differently?</strong> If the answer is yes, I would be glad if you could explain how they are synthesized.</li>
  <li><strong>If the answer is no, can one of the methods be better than the other in different conditions?</strong> Not in terms of lines of code or simplicity, but in terms of synthesis.</li>
  </ul>