title: How to force a full recompilation of all files for every make?
body: <p>I'm hoping to create a basic makefile template for small-scale C apps.  In this scenario, I'm less concerned with performance than clarity and want to recompile everything - All .h and .c files, and third-party .so files.</p>
  
  <pre><code># Constants
  #===============================================================================
  
  # Specify the C complier
  CC = gcc
  
  # List the flags to pass to the compiler
  #  -ggdb       Compile with debug information for gdb
  #  -Wall       Give all diagnostic warnings
  #  -O0         Do NOT optimize generated code
  #  -m64        Generate code for a 64-bit environment
  CFLAGS = -ggdb -Wall -O0 -m64
  
  # Change the list of c source files into a list of object files by replacing
  # the .c suffix with .o
  OBJECTS := $(patsubst %.c,%.o,$(wildcard *.c))
  
  # List libraries
  # m    Math library
  LIBRARIES = -lm
  
  # Specify the build target
  TARGET = heyyou
  
  # Rules
  #===============================================================================
  # $@ = left side of the colon, the target
  $(TARGET) : $(OBJECTS)
      @echo "Compiling $@..."
      $(CC) -o $(TARGET) $(OBJECTS) $(CFLAGS) $(LIBRARIES)
  </code></pre>