title: Generating a 64-byte read PCIe TLP from an x86 CPU
body: <p>When writing data to a PCIe device, it is possible to use a write-combining mapping to hint the CPU that it should generate 64-byte TLPs towards the device.</p>
  
  <p>Is it possible to do something similar for reads? Somehow hint the CPU to read an entire cache line or a larger buffer instead of reading one word at a time?</p>