title: Verilog ,cannot be assigned more than one value
body: <p>I am New to Verilog, I am trying to make a CPLD power up protection logic, it actually use a bunch of Timer to validate the state machine. I have a CPLD with 1Mhz OSC, and I am trying to make a 15s timer, I figure the code, but it have compile error, says <strong>"cannot be assigned more than one value".</strong> I knew this mean the signal net has been control by two different signal, but it has a error line shows</p>
  
  <p>Error (12014): Net "Fifty_m_second_Devide_Clock_input", which fans out to "Timer[0]", cannot be assigned more than one value
      Error (12015): Net is fed by "clk_div:d|clk_out"
      Error (12015): Net is fed by "Fifty_m_second_Devide_Clock_input"</p>
  
  <p><strong><code>why "Fifty_m_second_Devide_Clock_input" is connected to itself??</code></strong></p>
  
  <pre><code>  module PowerUpProtection(
  
      //---------------------------------------------------------------------------
      // Inputs
      //---------------------------------------------------------------------------
      input wire Fifty_m_second_Devide_Clock_input,
      input wire Clock,
      input wire Reset,
      input wire Input1_Check_precharge_status,
      input wire Input2_MainPowerSwitch_relay_status_Check,
      input wire Input3_powerUp_validation,
  
      //---------------------------------------------------------------------------
  
      //---------------------------------------------------------------------------
      // Outputs
      //---------------------------------------------------------------------------
      output reg Output1_Relay_Swtich_For_Main_PowerSource,
      output reg Output2_Switch_On_and_Charge_CAP,
      output reg Output3_Switch_On_and_power_SoM,
      output reg Output4_Press_and_hold_the_powerSource,
      output reg Output5_Switch_on_relay_when_CPLD_powerup
      //---------------------------------------------------------------------------
      );
  
  
      // this is a Module Instantiation, connect the inputs and output from different module within CPLD.
      clk_div d(
          .Clock  (Clock),
          .reset(Reset),
          .clk_out(Fifty_m_second_Devide_Clock_input)
      );
      //---------------------------------------------------------------------------
  
  
      //---------------------------------------------------------------------------
      // State Encoding 
      //---------------------------------------------------------------------------
      localparam STATE_0_Initial = 4'd0,
                    STATE_1_Press_and_hold = 4'd1,
                    STATE_2_Power_up = 4'd2,
                    STATE_3_Check_Switches = 4'd3,
                   STATE_4_SwtichSafe_StartPreCharging = 4'd4,
                    STATE_5_ERROR = 4'd5,
                    STATE_6_CAP_is_Charging = 4'd6,
                    STATE_7_Charging_End_SwitchOn_MainPower = 4'd7,
                    STATE_8_PowerSupply_Ready = 4'd8,
                    ERROR_9_TIME_OUT = 4'd9,
                    STATE_10_Precharge_Switch_is_broken = 4'd10,
                    STATE_11_Main_power_switch_is_broken = 4'd11,
                    STATE_12_Both_switches_are_broken = 4'd12,
                    STATE_13_PlaceHolder = 4'd13,
                    STATE_14_PlaceHolder = 4'd14,
                    STATE_15_PlaceHolder = 4'd15;       
      //---------------------------------------------------------------------------
  
  
  
      //---------------------------------------------------------------------------
      // State reg Declarations
      //---------------------------------------------------------------------------
      reg [3:0] CurrentState = 4'd0;
      reg [3:0] NextState = 4'd0;
      //---------------------------------------------------------------------------
  
  
  
      //---------------------------------------------------------------------------
      // Timer reg Declarations
      //---------------------------------------------------------------------------
      reg [8:0] Timer = 0;
      reg enable_the_counter = 0;  // the boolean to enbale the counter.
      reg clear_the_counter = 0;
  
      //---------------------------------------------------------------------------   
  
      //---------------------------------------------------------------------------
      // Outputs
      //---------------------------------------------------------------------------   
      always@(*) begin
          // clear for the initial state.
          reg Output1_Relay_Swtich_For_Main_PowerSource = 0;
          reg Output2_Switch_On_and_Charge_CAP = 0;
          reg Output3_Switch_On_and_power_SoM = 0;
          reg Output4_Press_and_hold_the_powerSource = 0;
          reg Output5_Switch_on_relay_when_CPLD_powerup = 0;
  
          case (CurrentState)
              STATE_1_Press_and_hold : begin
                  Output4_Press_and_hold_the_powerSource = 1;
              end
  
              STATE_2_Power_up        : begin
                  Output5_Switch_on_relay_when_CPLD_powerup = 1;
              end
  
              STATE_3_Check_Switches   : begin
                  Output2_Switch_On_and_Charge_CAP = 1;
              end 
  
              STATE_4_SwtichSafe_StartPreCharging : begin
                  Output2_Switch_On_and_Charge_CAP = 1;
              end
  
              STATE_5_ERROR : begin
                  // to be determined
              end
  
              STATE_6_CAP_is_Charging :  begin 
                  // wait for the charging to be complete
              end
  
              STATE_7_Charging_End_SwitchOn_MainPower : begin
                  Output1_Relay_Swtich_For_Main_PowerSource =1;
              end
  
              STATE_8_PowerSupply_Ready : begin
                  Output5_Switch_on_relay_when_CPLD_powerup = 0;
                  Output3_Switch_On_and_power_SoM = 1;
              end
          endcase
      end
      //---------------------------------------------------------------------------   
  
  
  
      //---------------------------------------------------------------------------
      // Synchronous State-Transition always@(posedge Clock) block
      //---------------------------------------------------------------------------
      always@(posedge Clock) begin
          if (Reset) CurrentState &lt;= STATE_0_Initial;
          else CurrentState &lt;= NextState;
      end
      //---------------------------------------------------------------------------
  
  
      //---------------------------------------------------------------------------
      // conditional State-Trasnsition Always@(*) block
      //---------------------------------------------------------------------------
      always@(*) begin
          NextState = CurrentState;
          case (CurrentState)
  
              STATE_0_Initial :begin
                  NextState = STATE_1_Press_and_hold;
              end
  
              STATE_1_Press_and_hold : begin
                  if (Input3_powerUp_validation) NextState = STATE_2_Power_up;
              end
  
              STATE_2_Power_up : begin
                  if (Input3_powerUp_validation) NextState = STATE_3_Check_Switches;
              end
  
              STATE_3_Check_Switches : begin 
                  if (Input1_Check_precharge_status == 0 &amp;&amp; Input2_MainPowerSwitch_relay_status_Check == 1 )
                      begin
                      NextState = STATE_4_SwtichSafe_StartPreCharging;
                      enable_the_counter = 1; //Start to count the time.
                      end
  
                  else if (Input1_Check_precharge_status == 1 &amp;&amp; Input2_MainPowerSwitch_relay_status_Check == 1)
                      begin
                      NextState = STATE_10_Precharge_Switch_is_broken;
                      end
  
                  else if (Input1_Check_precharge_status == 0 &amp;&amp; Input2_MainPowerSwitch_relay_status_Check == 0)
                      begin
                      NextState = STATE_11_Main_power_switch_is_broken;
                      end
  
                  else
                      begin 
                      NextState = STATE_12_Both_switches_are_broken;
                      end
  
              end
  
              STATE_4_SwtichSafe_StartPreCharging : begin
  
                  if (Input1_Check_precharge_status == 1 &amp;&amp; Timer &lt;= 300) //equals to 15 seconds
                      NextState = STATE_6_CAP_is_Charging;
  
                  else if (Timer &gt; 300)
                      NextState = STATE_5_ERROR;  //Time out Error
                      clear_the_counter = 1;
                      enable_the_counter = 0;
              end
  
              STATE_6_CAP_is_Charging : begin
  
                  if (Input1_Check_precharge_status == 0 &amp;&amp; Timer &lt;= 300) 
                      begin
                          NextState = STATE_7_Charging_End_SwitchOn_MainPower;
                          clear_the_counter = 1; // timer is over, clear the  counter.
                          enable_the_counter =0;
                      end
                  else if (Timer &gt; 300)
                      begin
                          NextState = STATE_5_ERROR;  //Time out Error
                          clear_the_counter = 1;
                          enable_the_counter = 0;
                      end
              end 
  
              STATE_7_Charging_End_SwitchOn_MainPower : begin
  
                  //enable the counter again, and count for 50 m seconds.
                  enable_the_counter = 1;
                  if (Input2_MainPowerSwitch_relay_status_Check ==1)
                          begin
                          if (Timer &lt;=1)
                              NextState = STATE_7_Charging_End_SwitchOn_MainPower; // if time is not 50 ms yet, go back to itself current  state
                          else
                              NextState = STATE_5_ERROR;  //Time out Error
                              clear_the_counter = 1;
                              enable_the_counter = 0;
                          end
                  else if (Input2_MainPowerSwitch_relay_status_Check == 0)  // if the switch is ready right away, that is best.
  
                          begin
                          NextState = STATE_8_PowerSupply_Ready; 
                          end
                  else 
                          NextState = STATE_5_ERROR;  //Time out Error
                          clear_the_counter = 1;
                          enable_the_counter = 0;
              end
  
              //---------------------------------------------------------------------------
              // Place-Holder transition.
              //---------------------------------------------------------------------------
              STATE_13_PlaceHolder : begin
                  NextState = STATE_5_ERROR;
              end
  
              STATE_14_PlaceHolder : begin
                  NextState = STATE_5_ERROR;
              end
              STATE_15_PlaceHolder : begin
                  NextState = STATE_5_ERROR;
              end
  
  
          endcase
      end 
  
      //---------------------------------------------------------------------------
      // 50 m Seconds counter block, make the osc into 20 HZ by implement the counter
      //---------------------------------------------------------------------------
  
      always@(posedge Fifty_m_second_Devide_Clock_input or posedge Reset or posedge clear_the_counter ) begin
          if (Reset == 1 || clear_the_counter == 1) 
              begin
                  Timer = 0;
              end
          else
              begin 
                  if (enable_the_counter) 
                  Timer &lt;= Timer + 1'b1;
              end
      end
      //---------------------------------------------------------------------------
  
  
  
  endmodule
  
  
  
  
  
      //clock devider, the board has a 10 M hz osc, 
  //so I create this code to count 200000 times 
  //for each posedge and that equalle to 50 m-second.
  // if count until 50 m-second, this clk_out will output one positive edge.
  
  module clk_div(
      input Clock,
      input reset,
      output reg clk_out
      );
      parameter diver = 99999;
      reg [23:0] count;//just for 99999 or warning
  
      always@(posedge Clock or posedge reset)
      begin
          if(reset)
          begin
              count &lt;= 0;
              clk_out &lt;= 1'b0;
          end
          else if(count == diver)
          begin
              clk_out &lt;= ~clk_out;
              count &lt;= 0;
          end
          else
          begin
              count &lt;= count + 1'b1;
          end
      end
  
  endmodule
  </code></pre>