title: Is integer overflow defined in VHDL?
body: <p>I was wondering if integer overflow is defined in VHDL. I wasn't able to find anything in the 2002 Specification.</p>
  
  <p>As an example <em>(Note, this might not compile, it's just a generic example...)</em>:</p>
  
  <pre><code>entity foo is port (
      clk : std_logic
  );
  end entity;
  
  architecture rtl of foo is
      signal x : integer range 0 to 2 := 0;
  begin
      process (clk)
      begin
          if rising_edge(clk) then
              x &lt;= x + 1;
          end if;
      end process;
  end architecture;
  </code></pre>
  
  <p>It's clear that <code>x</code> will go from 0 to 1, and then to 2. Is it defined what will happen on the next increment? Is that undefined behavior?</p>