title: Intel Quartus Error 12002 Port does not exist in macrofunction
body: <p>Working with an Intel Cyclone 10 FPGA and running into a compile error I cannot seem to debug properly. The errors I get are:</p>
  <pre><code>Error (12002): Port &quot;out_msg&quot; does not exist in macrofunction &quot;inst6&quot;
  Error (12002): Port &quot;msg&quot; does not exist in macrofunction &quot;inst5&quot;
  Error: Quartus Prime Analysis &amp; Synthesis was unsuccessful. 2 errors, 68 warnings
      Error: Peak virtual memory: 4803 megabytes
      Error: Processing ended: Wed Jan 06 09:42:35 2021
      Error: Elapsed time: 00:00:09
      Error: Total CPU time (on all processors): 00:00:19
  Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 68 warnings
  </code></pre>
  <p>The two errors are of the same issue I believe.
  <a href="https://i.stack.imgur.com/b9BQB.png" rel="nofollow noreferrer">Here is the relevant .bdf layout image</a></p>
  <p>Here is the code in the &quot;inst6&quot; block, the one that is causing the first error</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;               -- Needed for shifts
  use work.can;
  
  entity can_pack is
    port(
      clk              : in  std_ulogic;
      rst              : in  std_ulogic;
      enbl             : in  std_ulogic;
       data_in         : in  std_logic_vector(7 downto 0);
       data_in1        : in  std_logic_vector(7 downto 0);
       data_in2        : in  std_logic_vector(7 downto 0);
       data_in3        : in  std_logic_vector(7 downto 0);
       data_in4        : in  std_logic_vector(7 downto 0);
       data_in5        : in  std_logic_vector(7 downto 0);
       data_in6        : in  std_logic_vector(7 downto 0);
       data_in7        : in  std_logic_vector(7 downto 0);
       out_msg         : out work.can.message;
       ready_out       : out std_ulogic;
      tx               : inout std_ulogic);
  end can_pack;
  
  architecture syn of can_pack is
  
    signal ready              : std_ulogic;
    signal msg                    : work.can.message;
    
  begin
    
    process(clk, rst, data_in)
  
    begin
        msg.id  &lt;= x&quot;355&quot;; --NOTE: With ID defined to be 12 bits, please be mindfull that you don't set the ID to be &gt;0x7FF
        msg.len &lt;= x&quot;8&quot;;
        msg.dat(63 downto 56) &lt;= data_in;
        msg.dat(55 downto 48) &lt;= data_in1;
        msg.dat(47 downto 40) &lt;= data_in2;
        msg.dat(39 downto 32) &lt;= data_in3;
        msg.dat(31 downto 24) &lt;= data_in4;
        msg.dat(23 downto 16) &lt;= data_in5;
        msg.dat(15 downto  8) &lt;= data_in6;
        msg.dat(7  downto  0) &lt;= data_in7;
        out_msg &lt;= msg;
  
    if rst = '1' then
      ready &lt;= '0';
    elsif rising_edge(clk) then
  
      --enbl is the clock rate for message broadcast
      if enbl = '0' then
          ready &lt;= '1';
          ready_out &lt;= '1';
      elsif enbl = '1' then   --not sure if this is the right way to do this
          ready &lt;= '0';
          ready_out &lt;= '0';
       end if;
     end if;
    end process;   
  end syn;
  </code></pre>
  <p>I believe the issue has something to do with the defined type of data being set as the output. The input of inst5 takes in the same type. When I change the type of out_msg to just a std_ulogic, the code compiles without an issue.</p>
  <p>Here is the defined record for the out_msg data type:</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  package can is
    type message is record
      id  : std_ulogic_vector(11 downto 0);
      len : std_ulogic_vector(3 downto 0);
      dat : std_logic_vector(63 downto 0);
    end record message;
  end package can;
  
  package body can is
  end package body can;
  </code></pre>
  <p>I am pretty new to VHDL and Quartus and such, so there may be something obvious I am missing.. but any help is appreciated.</p>