title: generate inside generate verilog + error near generate(veri - 1137)
body: <p>Writing verilog code from quite a few days and one question I have is 'Can we write generate block inside generate block'? I am writing an RTL something like this:</p>
  
  <pre><code>Where 'n' is a parameter.
  reg [DATA_WIDTH:0] flops [n-1:0];
  
  generate
    if (n &gt; 0) begin
      always @(posedge clk) begin
        if (en) begin
          flops[0] &lt;= mem[addr];
        end
       end
       generate
         genvar i;
         for (i = 1; i &lt;= n ; i = i + 1) begin
           always @(posedge clk) begin
             flops[i] &lt;= flops[i-1];
           end
         end
       endgenerate
       always @(flops[n - 1])
         douta = flops[n - 1];
     else
       always @(posedge clk) begin
         if (en) begin
           primary_output = mem[addr];
         end
       end
     end
  endgenerate
  </code></pre>
  
  <p>While compiling the above code, I am getting :</p>
  
  <pre><code>ERROR: syntax error near generate (VERI-1137)
  </code></pre>
  
  <p>Not sure why. Purpose of this RTL is to create an pipeline of 'n' flops at the output side of the design.</p>
  
  <p>Lets say n is 2, then circuit should become :</p>
  
  <pre><code>flop1-&gt; flop2-&gt; primary output of design
  </code></pre>
  
  <p>flop1 and flop2 are newly created flops.</p>