title: Verilog - how to negate an array?
body: <pre><code>reg a[4:0];
  reg inv_a[4:0];
  
  assign inv_a = ~a; //This doesn't work.
  </code></pre>
  
  <p>When I tried modelsim with above statement, it throw: "Illegal operation on unpacked types"</p>
  
  <p>Can someone please point out how to correctly negate an array in Verilog?</p>
  
  <hr>
  
  <p><strong>Edit: Give more information, does this change any recommendation?</strong></p>
  
  <pre><code>module router_main(
      input bustorouter_ready[4:0],
  );
  
    wire inv_bustorouter_ready[4:0];
  
    assign inv_bustorouter_ready = ~bustorouter_ready; //Still doesn't work.
  </code></pre>