title: Verilog: Why can I not invert a wire?
body: <pre><code>module hamming_code #( parameter TOTAL_LENGTH = 15,
                                 parameter PARITY_BITS = 4
                             )
                  (
                      //inputs
                      input [TOTAL_LENGTH-1:0] codeword,
  
                      //outputs
                      output [TOTAL_LENGTH-1:0] correctedWord
                  //  output reg badData
                  );
  wire b;
  assign  correctedWord = codeword;
  
  assign  b = ~codeword[0];
  assign correctedWord[0] = b;
  
  endmodule
  </code></pre>
  
  <p>I am trying to invert the value of a single wire in an array of wires. However, whenever I do, that position becomes an 'X' instead of a 0 or 1. Why is this the case?</p>