title: VHDL State Machine testbench
body: <p>Description:  </p>
  
  <p>I am trying to generate a test bench for a 5 state sequential state machine that detects 110 or any combination of (2) 1's and (1) 0. I already have written the code. see below. I am having trouble with the test bench which is wrong. I want to test for all possible sequences as well as input combinations that are off sequence.  </p>
  
  <p>Please give me examples of a good test bench to achieve what I need for a mealy machine.</p>
  
  <p>vhdl code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  
  entity state is
  port( clk, x : in std_logic;
        z : out std_logic
        );
  end entity;
  
  architecture behavioral of state is
  type state_type is (s0,s1,s2,s3,s4);
  signal state,next_s: state_type;
  
  ------------------------------------------------------------------------------
  
  begin
  process (state,x)
  begin
  if clk='1' and clk'event then
  
  case state is
   when s0 =&gt;
     if(x ='0') then
       z &lt;= '0';
       next_s &lt;= s4;
     else
       z &lt;= '0';
       next_s &lt;= s1;
     end if;
  
   when s1 =&gt; --when current state is "s1"
     if(x ='0') then
       z &lt;= '0';
       next_s &lt;= s3;
     else
       z &lt;= '0';
       next_s &lt;= s2;
     end if;
  
   when s2 =&gt;  --when current state is "s2"
     if(x ='0') then
       z &lt;= '1';
       next_s &lt;= s0;
     else
       z &lt;= '0';
       next_s &lt;= s0;
     end if;
  
   when s3 =&gt;  --when current state is "s3"
     if(x ='0') then
       z &lt;= '0';
       next_s &lt;= s0;
     else
       z &lt;= '1';
       next_s &lt;= s0;
     end if;
  
   when s4 =&gt; --when current state is s4
     if (x = '0') then
       z &lt;= '0';
       next_s &lt;= s0;
     else
       z &lt;= '0';
       next_s &lt;= s3;
     end if;
  end case;
  end if;
  
  end process;
  end behavioral;
  </code></pre>
  
  <p>Test Bench code:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  -- Add your library and packages declaration here ...
  
  entity state_tb is
  end state_tb;
  
  architecture TB_ARCHITECTURE of state_tb is
  -- Component declaration of the tested unit
  component state
  port(
      clk : in STD_LOGIC;
      x : in STD_LOGIC;
      z : out STD_LOGIC );
  end component;
  
  -- Stimulus signals - signals mapped to the input and inout ports of tested entity
  signal clk : STD_LOGIC;
  signal x : STD_LOGIC;
  -- Observed signals - signals mapped to the output ports of tested entity
  signal z : STD_LOGIC;
  
  -- Add your code here ...
  
  begin
  
  -- Unit Under Test port map
  UUT : state
      port map (
          clk =&gt; clk,
          x =&gt; x,
          z =&gt; z
      );
  
  -- CLOCK STIMULI
  CLOCK: process
  begin
  CLK &lt;= not clk after 20 ns;
  wait for 40 ns;
  end process; 
  
  -- X input STIMULI
  X_Stimuli: process
  begin
  X &lt;= not x after 40 ns;
  wait for 80 ns;
  end process;
  
  end TB_ARCHITECTURE;
  
  configuration TESTBENCH_FOR_state of state_tb is
  for TB_ARCHITECTURE
      for UUT : state
          use entity work.state(behavioral);
      end for;
  end for;
  end TESTBENCH_FOR_state;
  </code></pre>