title: Risc-V: Minimum CSR requirements for simple RV32I implementation capable of leveraging GCC
body: <p>What would be the bare minimum CSR requirements for a RV32I capable of running machine code generated with GCC?</p>
  <p>I'm thinking of a simple fpga-based (embedded) implementation. No virtual memory or linux support is required.</p>
  <p>Also, what GCC flags should I use in order to prevent it from using unimplemented CSR related instructions?</p>
  <p>I'm still quite confused after scanning through the RISCV Privileged ISA Specification.</p>
  <p>Thanks!</p>