title: VHDL: slowing clock down methods
body: <p>as a newbie to VHDL I wondered if there was any particular reason why I cannot slow my clock down using counters alone? In all the examples I looked at so far, people seem to have created an entity and separate process for the new clock.
  The code below is my attempt.</p>
  
  <pre><code>variable clk_counter : integer range 0 to 30 := 0;
  begin
  if rising_edge(clk) then
   clk_counter:=clk_counter+1;
     if clk_counter = 30 then
      clk_counter := 0;
      ...
  </code></pre>
  
  <p>Any help would be much appreciated.</p>