title: Adding SMT/HyperThreading to a Verilog design?
body: <p>I am wondering how it SMT/HyperThreading being added to a Verilog HDL design?</p>
  
  <p>The planned design(something similar):
  <a href="http://www.fpga4student.com/2017/01/verilog-code-for-single-cycle-MIPS-processor.html" rel="nofollow noreferrer">http://www.fpga4student.com/2017/01/verilog-code-for-single-cycle-MIPS-processor.html</a></p>
  
  <p>I am wondering, is there any special kind of syntax to add the SMT function, and if so, where?</p>
  
  <p>I haven't tried anything so far, because I don't know where to start and google doesn't help!</p>
  
  <p>Thanks!</p>