title: How to implement clock divider to universal shift register
body: <p>I'm trying to make a VHDL code for 4-bit universal shift register, where I want to load 4 bits and choose the shift-operation from the ctrl. I don't know how to implement a clock divider to run the outputs on a FPGA.</p>
  
  <p>Here is my code so far:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  
  entity shift_register is
    generic(N : integer := 4);
    port(
      clk, reset : in  std_logic;
      ctrl       : in  std_logic_vector(1 downto 0);
      d          : in  std_logic_vector((N-1) downto 0);
      q          : out std_logic_vector((N-1) downto 0)
      );
  end shift_register;
  
  architecture Behavioral of shift_register is
  
    signal r_reg  : std_logic_vector((N-1) downto 0);
    signal r_next : std_logic_vector((N-1) downto 0);
  begin
    process(clk, reset)
    begin
      if(reset = '1') then
        r_reg &lt;= (others =&gt; '0');
      elsif(clk'event and clk = '1') then
        r_reg &lt;= r_next;
      end if;
    end process;
  
    with ctrl select
      r_next &lt;=
      r_reg                      when "00",   --do nothing
      r_reg(N-2 downto 0) &amp; d(0) when "01",   --shift left
      d(N-1) &amp; r_reg(N-1 downto 1)when "10",  --shift right
                       d when others;         --load
  
    q &lt;= r_reg;
  end Behavioral;
  </code></pre>