title: Verilog reg assignment?
body: <p>I'm totally new to Verilog programming and I do not understand where to initialize <code>reg</code> variables?</p>
  
  <p>Let's have a look at the following snippets:
  Edit:
  <a href="https://i.stack.imgur.com/ifLMB.png" rel="nofollow noreferrer">Warning at synthesize</a></p>
  
  <pre><code>module test (
         output LED0 
         );   
  reg led = 1'b1;
  assign LED0 = led;
  endmodule   
  </code></pre>
  
  <p>or </p>
  
  <pre><code>module test (
         output LED0 
         );   
  
  reg led;
  initial begin
      reg led &lt;= 1'b1;
  end
  
  assign LED0 = led;
  endmodule
  </code></pre>
  
  <p>Give me: Using initial value of led since it is never assigned at the line: <code>reg led = 1'b1;</code></p>
  
  <p>Are <code>reg</code> types only assigned in always@ block?</p>
  
  <p>Another example:</p>
  
  <pre><code>module fourBitCounter
         (input clk,
          output [3:0]counter
          );
  
  wire clk;
  initial begin
  reg[3:0] counter = 4'b1;
  end
  
  always@ (posedge clk) begin
  
           if(counter &gt; 15)
                counter &lt;= 0;
           else
                counter &lt;= counter + 1;
           end endmodule
  </code></pre>
  
  <p>Here the reg has an initial value of 0 but I've set it before to 1... What's wrong? Thank you!</p>