title: Why does the ARM PC register point to the instruction after the next one to be executed?
body: <p>According to the ARM IC.</p>
  
  <blockquote>
    <p>In ARM state, the value of the PC is the address of the current instruction plus 8 bytes.</p>
    
    <p>In Thumb state:</p>
    
    <ul>
    <li>For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.</li>
    <li>For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.</li>
    </ul>
  </blockquote>
  
  <p>Simply saying, the value of the PC register points to the instruction after the next instruction. This is the thing I don't get. Usually (particularly on the x86) program counter register is used to point to the address of the next instruction to be executed.</p>
  
  <p>So, what are the premises underlying that? Conditional execution, maybe?</p>