title: For each file in a directory in a Makefile
body: <p>I have this project structure:</p>
  
  <pre><code>/project
      |
      |____/bin
      |
      |
      |____/obj
      |
      |
      |____/include
      |    |
      |    |____aaa.h
      |    |
      |    |____bbb.h
      |    |
      |    |____ccc.h
      |
      |
      |____/src
      |    |
      |    |____aaa.c
      |    |
      |    |____bbb.c
      |    |
      |    |____ccc.c
      |
      |
      |____/test
      |    |
      |    |____aaa_test.c
      |    |
      |    |____bbb_test.c
      |    |
      |    |____ccc_test.c
      |
      |
      |____Makefile
  </code></pre>
  
  <p>I need to write a Makefile to test every module in this project. For each file in the <code>test</code> folder I should compile the relative module (same name without "_test") in <code>src</code> folder and create the executable in the folder <code>bin</code>.</p>
  
  <p>List of commands to execute:</p>
  
  <pre><code>gcc -Wall -g -I include -c src/aaa.c -o obj/aaa.o
  gcc -Wall -g -I include -c test/aaa_test.c -o obj/aaa_test.o
  gcc obj/aaa.o obj/aaa_test.o -o bin/aaa_test.exe
  
  gcc -Wall -g -I include -c src/bbb.c -o obj/bbb.o
  gcc -Wall -g -I include -c test/bbb_test.c -o obj/bbb_test.o
  gcc obj/bbb.o obj/bbb_test.o -o bin/bbb_test.exe
  
  gcc -Wall -g -I include -c src/ccc.c -o obj/ccc.o
  gcc -Wall -g -I include -c test/ccc_test.c -o obj/ccc_test.o
  gcc obj/ccc.o obj/ccc_test.o -o bin/ccc_test.exe
  </code></pre>
  
  <p>My current Makefile:</p>
  
  <pre><code>CC := gcc
  CCFLAGS := -Wall -g
  INC := -I include
  BINDIR := bin
  OBJDIR := obj
  SRCDIR := src
  TESTDIR := test
  
  all: $(BINDIR)/aaa_test.exe $(BINDIR)/bbb_test.exe $(BINDIR)/ccc_test.exe
  
  NAME = aaa
  
  $(BINDIR)/$(NAME)_test.exe: $(OBJDIR)/$(NAME).o $(OBJDIR)/$(NAME)_test.o
      $(CC) $^ -o $@
  
  $(OBJDIR)/$(NAME).o: $(SRCDIR)/$(NAME).c
      $(CC) $(CCFLAGS) $(INC) -c $&lt; -o $@
  
  $(OBJDIR)/$(NAME)_test.o: $(TESTDIR)/$(NAME)_test.c
      $(CC) $(CCFLAGS) $(INC) -c $&lt; -o $@
  
  NAME = bbb
  
  $(BINDIR)/$(NAME)_test.exe: $(OBJDIR)/$(NAME).o $(OBJDIR)/$(NAME)_test.o
      $(CC) $^ -o $@
  
  $(OBJDIR)/$(NAME).o: $(SRCDIR)/$(NAME).c
      $(CC) $(CCFLAGS) $(INC) -c $&lt; -o $@
  
  $(OBJDIR)/$(NAME)_test.o: $(TESTDIR)/$(NAME)_test.c
      $(CC) $(CCFLAGS) $(INC) -c $&lt; -o $@
  
  NAME = ccc
  
  $(BINDIR)/$(NAME)_test.exe: $(OBJDIR)/$(NAME).o $(OBJDIR)/$(NAME)_test.o
      $(CC) $^ -o $@
  
  $(OBJDIR)/$(NAME).o: $(SRCDIR)/$(NAME).c
      $(CC) $(CCFLAGS) $(INC) -c $&lt; -o $@
  
  $(OBJDIR)/$(NAME)_test.o: $(TESTDIR)/$(NAME)_test.c
      $(CC) $(CCFLAGS) $(INC) -c $&lt; -o $@
  </code></pre>
  
  <p>Can I read the name of each file in the <code>test</code> folder and optimize my Makefile?</p>