title: FFT implemetation in Verilog: Assigning Wire input to Register type array
body: <p>I am trying to implement butterfly FFT algorithm in verilog.
  <img src="https://i.stack.imgur.com/y33GM.png" alt="DIT Butterfly Network" /></p>
  <p>I create K(Here 4) butterfly modules . I create modules like this.</p>
  <pre><code>localparam K = 4;
  genvar     i;
  generate 
  for(i=0;i&lt;N/2;i=i+1)
  begin:BN
      butterfly #(
      .M_WDTH   (3 + 2*1),
      .X_WDTH   (4)
      )
      bf (
      .clk(clk), 
      .rst_n(rst_n), 
      .m_in(min), 
      .w(w[i]), 
      .xa(IN[i]), 
      .xb(IN[i+2]), 
      .x_nd(x_ndd), 
      .m_out(mout[i]), 
      .ya(OUT[i]),
      .yb(OUT[i+2]),
      .y_nd(y_nddd[i])
  );
  end
  </code></pre>
  <p>Each level I have to change input Xa and Xb for each Module (Here Number of level 3).</p>
  <p>So I try to initialize reg type &quot;IN&quot;array and assign the array to input Xa and Xb. When I initialize &quot;IN&quot; array manually, it works perfectly.</p>
  <p>The problem I face now, I couldn't assign Main module input X to register type &quot;IN&quot; array.
  Main module input X ,</p>
  <pre><code>input wire signed [N*2*X_WDTH-1:0] X,
  </code></pre>
  <p>I have to assign this X into array &quot;IN&quot;,</p>
  <pre><code>reg signed  [2*X_WDTH-1:0] IN [0:N-1];
  </code></pre>
  <p>I assigned like this,</p>
  <pre><code>initial
  begin
  
  IN[0]= X[2*X_WDTH-1:0];
  IN[1]=X[4*X_WDTH-1:2*X_WDTH];
  IN[2]=X[6*X_WDTH-1:4*X_WDTH];
  IN[3]= X[8*X_WDTH-1:6*X_WDTH];
  IN[4]= X[10*X_WDTH-1:8*X_WDTH];
  IN[5]=X[12*X_WDTH-1:10*X_WDTH];
  IN[6]=X[14*X_WDTH-12*X_WDTH];
  IN[7]= X[16*X_WDTH-1:14*X_WDTH];
  
  end
  </code></pre>
  <p>I have gone through many tutorials and forums. No luck.</p>
  <p>Can't we assign wire type to reg type array? If so how I can solve this problem.</p>
  <p><strong>Here is the Main module where I initialize Butterfly modules</strong>,</p>
  <pre><code>module Network
  #(
  // N
  parameter N = 8,
  // K.
  parameter K = 3,
   parameter M_WDTH=5,
   parameter X_WDTH=4
   
  )
  (
  input wire                        clk,
  input wire                        rst_n,
  
  // X
  input wire signed [N*2*X_WDTH-1:0] X,
  //Y
  output wire signed  [N*2*X_WDTH-1:0] Y,
  
  output wire signed [K-1:0] y_ndd
  );
  
  
  wire   y_nddd    [K-1:0];
  assign y_ndd ={y_nddd[1],y_nddd[0]};
  
  
  reg [4:0] min=5'sb11111;
  wire [4:0] mout [0:K-1];
  
  
  reg   x_ndd;
  reg [2:0] count=3'b100;
  
  reg   [2*X_WDTH-1:0] w [K-1:0];
  reg [2*X_WDTH-1:0] IN [0:N-1];
  wire [2*X_WDTH-1:0] OUT [0:N-1];
  
  assign Y = {OUT[3],OUT[2],OUT[1],OUT[0]};
  
  reg [3:0] a;
  
  initial
  begin
  
  //TODO : Here is the problem. Assigning Wire to reg array. Synthesize ok. In Simulate &quot;red&quot; output.
  IN[0]= X[2*X_WDTH-1:0];
  IN[1]=X[4*X_WDTH-1:2*X_WDTH];
  IN[2]=X[6*X_WDTH-1:4*X_WDTH];
  IN[3]= X[8*X_WDTH-1:6*X_WDTH];
  IN[4]= X[10*X_WDTH-1:8*X_WDTH];
  IN[5]=X[12*X_WDTH-1:10*X_WDTH];
  IN[6]=X[14*X_WDTH-12*X_WDTH];
  IN[7]= X[16*X_WDTH-1:14*X_WDTH];
  
  //TODO :This is only a random values
  w[0]=8'sb01000100;
  w[1]=8'sb01000100;
  w[2]=8'sb01000100;
  w[3]=8'sb01000100;
  
  end
  
  
  /* levels */
  genvar i;
  
  generate 
  for(i=0;i&lt;N/2;i=i+1)
  begin:BN
      butterfly #(
      .M_WDTH   (3 + 2*1),
      .X_WDTH   (4)
      )
      bf (
      .clk(clk), 
      .rst_n(rst_n), 
      .m_in(min), 
      .w(w[i]), 
      .xa(IN[i]), 
      .xb(IN[i+N/2]), 
      .x_nd(x_ndd), 
      .m_out(mout[i]), 
      .ya(OUT[2*i]),
      .yb(OUT[2*i+1]),
      .y_nd(y_nddd[i])
  );
  end
  
  endgenerate
  
  
  always @ (posedge clk)
  begin
      if (count==3'b100)
      begin
          count=3'b001;
          x_ndd=1;
      end
      
      else
      begin
          count=count+1;
          x_ndd=0;
      end     
  end
  
  
  
  always@ (posedge y_ndd[0])
  begin
      //TODO 
      //Here I have to swap OUT--&gt;IN
  end
  
  
  
  endmodule
  </code></pre>
  <p>Any help is appreciated.
  Thanks in advance.</p>