title: Slicing a STD_LOGIC_VECTOR and putting back together?
body: <p>I have sliced a 16 bit STD_LOGIC_VECTOR into 3 parts. I want to leave the first 8 MSBs untouched and break the 8 LSBs into 2 nibbles to do some processing on them.
  I can do all this and the processing is all fine but when I try to put them all together into a 16 bit STD_LOGIC_VECTOR output it just stays UUUU. is there a special way that putting it back together should go?</p>
  
  <pre><code>    signal fullout : std_logic_vector(15 downto 0);
      signal Sbox1 : integer;
      signal Sbox2 : integer;
      signal tophalf : std_logic_vector(7 downto 0);
      signal secondnibble, firstnibble : std_logic_vector(3 downto 0); --break the LSH into 2 nibbles
  
    begin
     tophalf(7 downto 0) &lt;= LUTin(15 downto 8);
     secondnibble(3 downto 0) &lt;= LUTin(7 downto 4);
     -- Sbox1 &lt;= to_integer(unsigned(secondnibble));
     firstnibble(3 downto 0) &lt;= LUTin(3 downto 0);
     -- Sbox2 &lt;= to_integer(unsigned(firstnibble));
  
    p1: process(LUTin)
    begin
    fullout(15 downto 8) &lt;= tophalf(7 downto 0);
    fullout(7 downto 4) &lt;= secondnibble(3 downto 0);
    fullout(3 downto 0) &lt;= firstnibble(3 downto 0);
  </code></pre>