title: How to initialize contents of inferred Block RAM (BRAM) in Verilog
body: <p>I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as below:</p>
  
  <pre><code>module ram(
          input clock, // System clock
          input we, // When high RAM sets data in input lines to given address
          input [13:0] data_in, // Data lines to write to memory
          input [10:0] addr_in, // Address lines for saving data to memory
          input [10:0] addr_out, // Address for reading from ram
          output reg data_out // Data out
  );
  
  reg [13:0] ram[2047:0];
  
  // Initialize RAM from file
  // WHAT SHOULD GO HERE?
  
  always @(posedge clock) begin
      // Save data to RAM
      if (we) begin
          ram[addr_in] &lt;= data_in;
      end
  
      // Place data from RAM
      data_out &lt;= ram[addr_out];
  end        
  endmodule
  </code></pre>
  
  <p>I have run into the command $readmemh. However, documentation for it seems sparse. How should I format the file that contains the data? Also, how can I pass the file as argument when instantiating this module so that I can have different instances of this module load from different files?</p>
  
  <p>I want the initialized content to be available for both simulation and actual implementation. So that the FPGA already boots with this content in RAM.</p>
  
  <p>I am using Vivado 2015.4 to program a Kintex xc7k70 FPGA.</p>