title: Fundamental Verilog Concepts
body: <p>I have my first verilog assignment due in a few days and for whatever reason these concepts are escaping me. I don't think I'm thinking in terms of parallelism and hardware or something.</p>
  
  <p>My question is that I have to <code>and</code> a few switches and buttons together using <code>wire</code>s and turn on 3 LEDs in array of 7. I'm pretty sure I know how to do the computational logic, but I can't figure out how to use <code>assign</code> and <code>wire</code> to properly turn on all 3 LEDs without writing 3 separate lines. It feels wrong to do:</p>
  
  <pre><code>assign Led[0] = output;
  assign Led[1] = output;
  assign Led[2] = output;
  </code></pre>
  
  <p>Also, it's weird because there are 7 LEDs on the board and I'm picking on LEDs 0,2,4. </p>
  
  <p>Can someone walk me through how this is supposed to work the <em>proper</em> way? We don't have a textbook and I've been reading the basics online, but I just can't seem to figure out how this is supposed to work. Thanks!</p>
  
  <p>Edit: This is my current code, but I am getting errors that say nothing is "driven". What gives?</p>
  
  <pre><code>module Lab2_1(input [5:0] sw, input btns, output [7:0] Led );
  
      wire [2:0] leds; 
      wand out; 
  
      assign leds = {Led[0], Led[2], Led[4]};
  
      and U1   (out, sw[0], sw[1]);
      and U2   (out,~sw[2],~sw[3]);
      xor U3   (out,sw[4],sw[5]);
      assign   out = btns;
      assign leds[2:0] = {3{out}};
  
  endmodule
  </code></pre>
  
  <p>Errors: </p>
  
  <pre><code>ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;3&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;4&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;5&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;6&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;7&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;0&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;1&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:368 - The signal &lt;Led&lt;2&gt;_OBUF&gt; is incomplete. The signal
     is not driven by any source pin in the design.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;3&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;4&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;5&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;6&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;7&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;0&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;1&gt;_OBUF&gt; is completely unrouted.
  ERROR:PhysDesignRules:10 - The network &lt;Led&lt;2&gt;_OBUF&gt; is completely unrouted.
  ERROR:Bitgen:25 - DRC detected 16 errors and 0 warnings.  Please see the
     previously displayed individual error or warning messages for more details.
  </code></pre>