title: Using parameter for continuous assignment in verilog?
body: <p>Can you use a parameter value for assignment in verilog? Can I somehow define the width of a parameter variable?</p>
  
  <p>Ex:</p>
  
  <pre><code>module mymodule #(parameter type =2)
      (...
      output [(3+type)-1:0] out);
      wire [2:0] rate;
      ...
      assign out = {rate, {1'b0{type}} };
  endmodule
  </code></pre>
  
  <p>Lets just say type=2. Then I would want out to be of bit-length 5. rate is still of bit-length 3 (lets just say it is 3'b100), when I assign out I want it to be 100 000.</p>
  
  <p>Similarly if type=6. Then I would want out to be of bit-length 9. rate is still of bit-length 3 (again lets say its 3'b100), when I assign out I want it to be 100 000000.</p>
  
  <p>I don't get any syntax errors but when I try to simulate it I get:
  "error: Concatenation operand "type" has indefinite width"</p>
  
  <p>How would you guys approach a design problem like this one?</p>