title: In Verilog, I'm trying to use $readmemb to read .txt file but it only loads xxxxx (dont cares) on memory
body: <p>I need to load a memory with some data originally in binary. I read that $readmemb can be use for this, and there is even a method to make synthesizable.</p>
  
  <p>So, I created another module named RAM_IN (which is not the testbench module) and "connected" to the top module.</p>
  
  <p>Before knowing about $readmemb, I was using this code:</p>
  
  <pre><code>initial
  begin
  in_ram [0] &lt;= 32'b11111111_000000000000000000000000; 
  in_ram [1] &lt;= 32'b10010111_000000000000000000000000;
  in_ram [2] &lt;= 32'b00110110_000000000000000000000000;
  in_ram [3] &lt;= 32'b00111110_000000000000000000000000;
  in_ram [4] &lt;= 32'b00111111_000000000000000000000000;
  in_ram [5] &lt;= 32'b00111110_000000000000000000000000;
  end
  </code></pre>
  
  <p>But its too tiring for me to write 100 numbers like this, so implemented $readmemb like this:</p>
  
  <pre><code>module RAM_IN (pix_val, indx);
  
  
  input [0:5] indx;
  output [31:0] pix_val;
  
  
  reg [31:0] pix_val;
  reg [31:0] in_ram [0:4];
  
  always @ (indx)
  pix_val = in_ram [indx];
  
  initial
  begin
  $readmemb("in_ram.txt", in_ram);
  end
  </code></pre>
  
  <p>The purpose of reading this file, is to initially load 100 binary values (wich simulate the pixel intensity of a 10x10 image) one by one into the top module (which is going to process and spit a result later...) </p>
  
  <p>I created a .txt file which looks content exactly like this</p>
  
  <pre><code>11111111000000000000000000000000
  10010111000000000000000000000000
  00110110000000000000000000000000
  00111110000000000000000000000000
  00111111000000000000000000000000 
  </code></pre>
  
  <p>When I simulate, modelsim show me memory filled with xxxxxxxxxxxxxxxxx (dont care), it looks like isn't loading anything to the memory.</p>
  
  <p>I don't know what I'm doing wrong. Likely isnt the dispossition of the numbers in the .txt file. Maybe is because I'm intending to load file with $readmemb in another module which is not testbench?</p>
  
  <p>PD: The simulation of this process of filling the memory I'm doing only for practical purpose, the final intention is to put the Top module design into a full SoC which I think I will do using QSYS. But I'm very new at this so I'm still studying. Any help will be much appreciated!!!</p>