title: Sharing (including?) generics in VHDL between files?
body: <p>Assume I have this simple core with generics as <code>genertest.vhd</code>:</p>
  
  <pre><code>--------------------------------------------------------------------------
  library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    -- use IEEE.STD_LOGIC_ARITH.ALL;
    -- use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.NUMERIC_STD.ALL;
  
  
  ENTITY genertest IS
    GENERIC(
      numbits : natural := 8
    );
    PORT
    (
      clk   :  IN STD_LOGIC;
      d_OUT : OUT STD_LOGIC_VECTOR(numbits-1 downto 0);
      d_IN  :  IN STD_LOGIC_VECTOR(numbits-1 downto 0)
    );
  END genertest;
  
  
  ARCHITECTURE structure OF genertest IS
  BEGIN
  
    main_proc: PROCESS(clk)
    BEGIN
      IF rising_edge(clk) THEN -- posedge
        d_OUT &lt;= not(d_IN);
      END IF;
    END PROCESS main_proc;
  
  END structure;
  </code></pre>
  
  <p>... and I want to test it with following test workbench, <code>genertest_twb.vhd</code>:</p>
  
  <pre><code>----------------------------------------------------------------------------------
  
  library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    -- use IEEE.STD_LOGIC_ARITH.ALL;
    -- use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.NUMERIC_STD.ALL;
  
  ENTITY genertest_twb IS
  END genertest_twb;
  
  ARCHITECTURE testbench_arch OF genertest_twb IS
  
    COMPONENT genertest
      PORT(
        clk   :  IN STD_LOGIC;
        d_OUT : OUT STD_LOGIC_VECTOR(numbits-1 downto 0);
        d_IN  :  IN STD_LOGIC_VECTOR(numbits-1 downto 0)
      );
    END COMPONENT;
  
    SIGNAL wtCLK : std_logic := '0';
    SIGNAL wCntReg : STD_LOGIC_VECTOR(numbits-1 DOWNTO 0) := (others =&gt; 'Z');
    SIGNAL tmp_cnt : natural := 0 ;
  
    -- clock parameters
    constant PERIODN : natural := 20; -- can be real := 20.0;
    constant PERIOD : time := PERIODN * 1 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 100 ns;
  
  BEGIN
  
    UUT : genertest -- VHDL
    PORT MAP(
      clk =&gt; wtCLK,
      d_IN =&gt; wCntReg,
      d_OUT =&gt; OPEN
    );
  
    -- clock process for generating CLK
    -- (here, left as unnamed)
    PROCESS
    BEGIN
  
      WAIT for OFFSET;
  
      CLOCK_LOOP : LOOP
        wtCLK &lt;= '0';
        -- tmp_na - natural problems with bit width?
        -- wCntReg &lt;= std_logic_vector(to_unsigned(natural'pos(tmp_na), wCntReg'length));
        WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
        wtCLK &lt;= '1';
        WAIT FOR (PERIOD * DUTY_CYCLE);
      END LOOP CLOCK_LOOP;
    END PROCESS;
  
  
    count_proc: PROCESS(wtCLK)
    BEGIN
      IF rising_edge(wtCLK) THEN -- posedge
        tmp_cnt &lt;= tmp_cnt + 1;
        wCntReg &lt;= std_logic_vector(to_unsigned(natural'pos(tmp_cnt), wCntReg'length));
      END IF;
    END PROCESS count_proc;
  
  
  END testbench_arch;
  </code></pre>
  
  <p>Now, I would assume that by referencing the <code>genertest</code> component, the workbench would automatically know about the <code>numbits</code> generic, but unfortunately, that is not the case; behavioral simulation of the above workbench in ISE WebPack fails with:</p>
  
  <pre><code>ERROR:HDLCompiler:69 - "/genertest_tbw.vhd" Line 17: &lt;numbits&gt; is not declared.
  ERROR:HDLCompiler:69 - "/genertest_tbw.vhd" Line 18: &lt;numbits&gt; is not declared.
  ERROR:HDLCompiler:69 - "/genertest_tbw.vhd" Line 23: &lt;numbits&gt; is not declared.
  </code></pre>
  
  <p>By adding the generic part in the <code>genertest_tbw.vhd</code> here:</p>
  
  <pre><code>  COMPONENT genertest
      GENERIC(
        numbits : natural := 8
      );
      PORT(
        ...
  </code></pre>
  
  <p>... will fix generics references local to the component - unfortunately, the reference to the generic in the <code>SIGNAL wCntReg</code> declaration will still fail.</p>
  
  <p>Finally, adding the generic part in the <code>genertest_tbw.vhd</code> here:</p>
  
  <pre><code>ENTITY genertest_twb IS
    GENERIC(
      numbits : natural := 8
    );
  END genertest_twb;
  </code></pre>
  
  <p>... makes the generic available to the entire workbench file.</p>
  
  <p>However, that still means I have to manually copy/paste <code>numbits : natural := 8</code> sentence in the workbench file as well; which means it will figure two places, and I'd have to change both if I want to change the generic value :(</p>
  
  <p>So my question is - is there a way to share / include generics, such that they are written/defined in only one file - and other files can refer to these particular values?</p>
  
  <p>Thanks in advance for any answers,<br>
  Cheers!</p>