title: How many page tables do Intel x86-64 CPUs access to translate virtual memory?
body: <p>I am trying to understand the number of tables looked-up, when translating a virtual address to a physical address. The Intel manual seems to state numerous schemes:</p>
  
  <p><a href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf" rel="nofollow noreferrer">http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf</a></p>
  
  <p>(section 4)</p>
  
  <p>whereas Ulrich Drepper's paper says there are typically 4:</p>
  
  <p><a href="http://www.akkadia.org/drepper/cpumemory.pdf" rel="nofollow noreferrer">http://www.akkadia.org/drepper/cpumemory.pdf</a></p>
  
  <p>(page 38)</p>
  
  <p>Whereas I seem to find a lot of diagrams online only showing two:</p>
  
  <p><a href="https://i.stack.imgur.com/PolxM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/PolxM.png" alt="enter image description here"></a></p>
  
  <p>Could somebody explain which how many page tables are typically accessed on an Intel CPU, or whether it depends on OS configuration (like Huge memory pages etc)?</p>