<div class="description">
<dl><dd>Thesis advisor(s): Kirk, Donald E. ; Loomis, Herschel H</dd>
<dd>"March 1988."</dd>
<dd>Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 1988</dd>
<dd>Includes bibliographical references (p. 125-129)</dd>
<dd>An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor (CMOS) integrated circuit logic design using silicon gate enhancement mode Field-Effect Transistors (FET) is derived and implemented in software. The algorithm is applied to the mask level hardware design of a three micron minimum feature size p well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated (VLSI) circuits. Keywords: MacPITTS; Silicon compiler; CMOS; VLSI; Super buffer; Transistor sizing; and High-Speed CMOS. (rh)</dd>
<dd>US Marine Corps (USMC) author</dd></dl><br>Subjects: Electrical and computer engineering</div>
<div class="fn value">
Steele, Gordon R.</div>
Internet Archive identifier