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<p>The configurable fault-tolerant processor (CFTP) project was intended to develop the means for a system to operate in areas which include frequent single-effect events (SEEs) similar to those caused by ionized radiation colliding with logic gates. Such errors are capable of degrading the functionality of a system and completely changing a state machine, such as is at the heart of most spacecrafts’ processors. The method for this consisted of a field-programmable gate array (FPGA) being designed into a system which is capable of detecting and then correcting SEEs. The system was designed by many students. This project will take that design, which launched into space earlier this year, and reduce it to modules which can be uploaded individually, built around a core which will be part of the existing triple fault-tolerant design (TFTD). Modularizing the code allows more experiments to be simultaneously performed in the future by changing the architecture of the system to upload specific modules to specified addresses. This will allow smaller uploads and code tweaks, without incurring long upload times, and more frequent updates to run specific tests ad hoc. Research and development conducted for this thesis has demonstrated the capability to inject configuration errors into the current design and the TFTD’s ability to detect those and similar errors, contributing to a better understanding of the TFTD.
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<br>Subjects: configurable fault tolerant processor (CFTP); global triple-modular redundancy (GTMR); NPSAT-1; field-programmable gate array (FPGA); single event effect (SEE); cache; memory controller; error mitigation; hardware design; softcore design; triple fault-tolerant design (TFTD)</div>
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Archer, Stuart C.</div>
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