<div class="description">
<dl><dd>Thesis Advisor(s): Parker, Sydney R. ; Second Reader: Powers, V. Michael</dd>
<dd>September 1974</dd>
<dd>Author(s) subject terms: Digital Filter, Arithmetric Quantization Errors, Hardware Implementation</dd>
<dd>Description based on title screen as viewed on September 26, 2011</dd>
<dd>Portuguese Navy author</dd>
<dd>Thesis (Degree of Electrical Engineer)--Naval Postgraduate School, September 1974</dd>
<dd>Includes bibliographical references (leaves 139-141)</dd>
<dd>Design and implementation of recursive digital filters with f'ixed point arithmetic using special hardware are considered in detail and applied to a mechanization of a second order filter structure with variable coefficients. Two new methods of performing quantization after arithmetic operations within a digital filter are presented: quantization after addition and quantization before multiplication. Both methods are shown applicable to hardware implementation of digital filters and offer advantages over the usual quantization after multiplication. Error bounds are derived for these two quantization schemes and compared with the results previously obtained by other authors. It is concluded that the quantization before multiplication is the most suitable for hardware filter implementation. A design modification of the presently available hardware chips in order to permit round-off or truncation before multiplication is presented</dd>
<dd>Mode of access: World Wide Web</dd>
<dd>System requirements: Adobe Acrobat Reader</dd>
<dd>record upgraded 9/28/2011 daw</dd></dl><br>Subjects: Signal processing; Logic devices; Noise; Shift registers; Hardware</div>
<div class="fn value">
Rodolfo, Carlos JosΓe de Almeida Rodrigues.</div>
Internet Archive identifier