<div class="description">
<dl><dd>"March 1997."</dd>
<dd>Thesis advisor(s): Douglas J. Fouts</dd>
<dd>Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 1997</dd>
<dd>Includes bibliographical references (p. 233-235)</dd>
<dd>In the last 30 years, the world has become increasingly dependent on space-based systems. These systems require varying degrees of radiation tolerance to perform their missions. Current radiation hardening processes for integrated circuits are expensive and consume significant layout area, increase power consumption, and decrease the frequency of operation. Furthermore, it is becoming more difficult to find fabricators for radiation-hardened electronic devices. In this thesis, two new transistor designs using a bulk CMOS process are tested for radiation hardness and are compared to a standard design. Both show a degree of improvement in subthreshold leakage current and threshold voltage shift over the control transistors. The new designs demonstrate an ability to reduce the effects of radiation on transistor parameters by means of an applied voltage to a second layer of polysilicon material above the control gate material</dd>
<dd>Mode of access: World Wide Web</dd>
<dd>System requirements: Adobe Acrobat reader</dd></dl><br>Subjects:</div>
<div class="fn value">
Noe, Sidney Scott</div>
Internet Archive identifier