<Table> Parallel ATA <Tr> <Td colspan="4"> Two ATA motherboard sockets on the left , with an ATA connector on the right . </Td> </Tr> <Tr> <Th> Type </Th> <Td colspan="3"> Internal storage device connector </Td> </Tr> <Tr> <Th colspan="4"> Production history </Th> </Tr> <Tr> <Th> Designer </Th> <Td colspan="3"> Western Digital , subsequently amended by many others </Td> </Tr> <Tr> <Th> Designed </Th> <Td colspan="3"> 1986 </Td> </Tr> <Tr> <Th> Superseded by </Th> <Td colspan="3"> Serial ATA ( 2003 ) </Td> </Tr> <Tr> <Th colspan="4"> General specifications </Th> </Tr> <Tr> <Th> Hot pluggable </Th> <Td colspan="3"> No </Td> </Tr> <Tr> <Th> External </Th> <Td colspan="3"> No </Td> </Tr> <Tr> <Th> Cable </Th> <Td colspan="3"> 40 or 80 wires ribbon cable </Td> </Tr> <Tr> <Th> Pins </Th> <Td colspan="3"> 40 </Td> </Tr> <Tr> <Th colspan="4"> Data </Th> </Tr> <Tr> <Th> Width </Th> <Td colspan="3"> 16 bits </Td> </Tr> <Tr> <Th> Bitrate </Th> <Td colspan="3"> 16 MB / s originally later 33 , 66 , 100 and 133 MB / s </Td> </Tr> <Tr> <Th> Max . devices </Th> <Td colspan="3"> Two ( master / slave ) </Td> </Tr> <Tr> <Th> Protocol </Th> <Td colspan="3"> Parallel </Td> </Tr> <Tr> <Th colspan="4"> Pin out </Th> </Tr> <Tr> <Td colspan="4"> </Td> </Tr> <Tr> <Th> Pin 1 </Th> <Td> </Td> <Td> Reset </Td> </Tr> <Tr> <Th> Pin 2 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 3 </Th> <Td> </Td> <Td> Data 7 </Td> </Tr> <Tr> <Th> Pin 4 </Th> <Td> </Td> <Td> Data 8 </Td> </Tr> <Tr> <Th> Pin 5 </Th> <Td> </Td> <Td> Data 6 </Td> </Tr> <Tr> <Th> Pin 6 </Th> <Td> </Td> <Td> Data 9 </Td> </Tr> <Tr> <Th> Pin 7 </Th> <Td> </Td> <Td> Data 5 </Td> </Tr> <Tr> <Th> Pin 8 </Th> <Td> </Td> <Td> Data 10 </Td> </Tr> <Tr> <Th> Pin 9 </Th> <Td> </Td> <Td> Data 4 </Td> </Tr> <Tr> <Th> Pin 10 </Th> <Td> </Td> <Td> Data 11 </Td> </Tr> <Tr> <Th> Pin 11 </Th> <Td> </Td> <Td> Data 3 </Td> </Tr> <Tr> <Th> Pin 12 </Th> <Td> </Td> <Td> Data 12 </Td> </Tr> <Tr> <Th> Pin 13 </Th> <Td> </Td> <Td> Data 2 </Td> </Tr> <Tr> <Th> Pin 14 </Th> <Td> </Td> <Td> Data 13 </Td> </Tr> <Tr> <Th> Pin 15 </Th> <Td> </Td> <Td> Data 1 </Td> </Tr> <Tr> <Th> Pin 16 </Th> <Td> </Td> <Td> Data 14 </Td> </Tr> <Tr> <Th> Pin 17 </Th> <Td> </Td> <Td> Data 0 </Td> </Tr> <Tr> <Th> Pin 18 </Th> <Td> </Td> <Td> Data 15 </Td> </Tr> <Tr> <Th> Pin 19 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 20 </Th> <Td> </Td> <Td> Key or VCC_in </Td> </Tr> <Tr> <Th> Pin 21 </Th> <Td> </Td> <Td> DDRQ </Td> </Tr> <Tr> <Th> Pin 22 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 23 </Th> <Td> </Td> <Td> I / O write </Td> </Tr> <Tr> <Th> Pin 24 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 25 </Th> <Td> </Td> <Td> I / O read </Td> </Tr> <Tr> <Th> Pin 26 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 27 </Th> <Td> </Td> <Td> IOCHRDY </Td> </Tr> <Tr> <Th> Pin 28 </Th> <Td> </Td> <Td> Cable select </Td> </Tr> <Tr> <Th> Pin 29 </Th> <Td> </Td> <Td> DDACK </Td> </Tr> <Tr> <Th> Pin 30 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 31 </Th> <Td> </Td> <Td> IRQ </Td> </Tr> <Tr> <Th> Pin 32 </Th> <Td> </Td> <Td> No connect </Td> </Tr> <Tr> <Th> Pin 33 </Th> <Td> </Td> <Td> Addr 1 </Td> </Tr> <Tr> <Th> Pin 34 </Th> <Td> </Td> <Td> GPIO_DMA66_Detect </Td> </Tr> <Tr> <Th> Pin 35 </Th> <Td> </Td> <Td> Addr 0 </Td> </Tr> <Tr> <Th> Pin 36 </Th> <Td> </Td> <Td> Addr 2 </Td> </Tr> <Tr> <Th> Pin 37 </Th> <Td> </Td> <Td> Chip select 1P </Td> </Tr> <Tr> <Th> Pin 38 </Th> <Td> </Td> <Td> Chip select 3P </Td> </Tr> <Tr> <Th> Pin 39 </Th> <Td> </Td> <Td> Activity </Td> </Tr> <Tr> <Th> Pin 40 </Th> <Td> </Td> <Td> Ground </Td> </Tr> </Table>
<Table> Parallel ATA <Tr> <Td colspan="4"> Two ATA motherboard sockets on the left , with an ATA connector on the right . </Td> </Tr> <Tr> <Th> Type </Th> <Td colspan="3"> Internal storage device connector </Td> </Tr> <Tr> <Th colspan="4"> Production history </Th> </Tr> <Tr> <Th> Designer </Th> <Td colspan="3"> Western Digital , subsequently amended by many others </Td> </Tr> <Tr> <Th> Designed </Th> <Td colspan="3"> 1986 </Td> </Tr> <Tr> <Th> Superseded by </Th> <Td colspan="3"> Serial ATA ( 2003 ) </Td> </Tr> <Tr> <Th colspan="4"> General specifications </Th> </Tr> <Tr> <Th> Hot pluggable </Th> <Td colspan="3"> No </Td> </Tr> <Tr> <Th> External </Th> <Td colspan="3"> No </Td> </Tr> <Tr> <Th> Cable </Th> <Td colspan="3"> 40 or 80 wires ribbon cable </Td> </Tr> <Tr> <Th> Pins </Th> <Td colspan="3"> 40 </Td> </Tr> <Tr> <Th colspan="4"> Data </Th> </Tr> <Tr> <Th> Width </Th> <Td colspan="3"> 16 bits </Td> </Tr> <Tr> <Th> Bitrate </Th> <Td colspan="3"> 16 MB / s originally later 33 , 66 , 100 and 133 MB / s </Td> </Tr> <Tr> <Th> Max . devices </Th> <Td colspan="3"> Two ( master / slave ) </Td> </Tr> <Tr> <Th> Protocol </Th> <Td colspan="3"> Parallel </Td> </Tr> <Tr> <Th colspan="4"> Pin out </Th> </Tr> <Tr> <Td colspan="4"> </Td> </Tr> <Tr> <Th> Pin 1 </Th> <Td> </Td> <Td> Reset </Td> </Tr> <Tr> <Th> Pin 2 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 3 </Th> <Td> </Td> <Td> Data 7 </Td> </Tr> <Tr> <Th> Pin 4 </Th> <Td> </Td> <Td> Data 8 </Td> </Tr> <Tr> <Th> Pin 5 </Th> <Td> </Td> <Td> Data 6 </Td> </Tr> <Tr> <Th> Pin 6 </Th> <Td> </Td> <Td> Data 9 </Td> </Tr> <Tr> <Th> Pin 7 </Th> <Td> </Td> <Td> Data 5 </Td> </Tr> <Tr> <Th> Pin 8 </Th> <Td> </Td> <Td> Data 10 </Td> </Tr> <Tr> <Th> Pin 9 </Th> <Td> </Td> <Td> Data 4 </Td> </Tr> <Tr> <Th> Pin 10 </Th> <Td> </Td> <Td> Data 11 </Td> </Tr> <Tr> <Th> Pin 11 </Th> <Td> </Td> <Td> Data 3 </Td> </Tr> <Tr> <Th> Pin 12 </Th> <Td> </Td> <Td> Data 12 </Td> </Tr> <Tr> <Th> Pin 13 </Th> <Td> </Td> <Td> Data 2 </Td> </Tr> <Tr> <Th> Pin 14 </Th> <Td> </Td> <Td> Data 13 </Td> </Tr> <Tr> <Th> Pin 15 </Th> <Td> </Td> <Td> Data 1 </Td> </Tr> <Tr> <Th> Pin 16 </Th> <Td> </Td> <Td> Data 14 </Td> </Tr> <Tr> <Th> Pin 17 </Th> <Td> </Td> <Td> Data 0 </Td> </Tr> <Tr> <Th> Pin 18 </Th> <Td> </Td> <Td> Data 15 </Td> </Tr> <Tr> <Th> Pin 19 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 20 </Th> <Td> </Td> <Td> Key or VCC_in </Td> </Tr> <Tr> <Th> Pin 21 </Th> <Td> </Td> <Td> DDRQ </Td> </Tr> <Tr> <Th> Pin 22 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 23 </Th> <Td> </Td> <Td> I / O write </Td> </Tr> <Tr> <Th> Pin 24 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 25 </Th> <Td> </Td> <Td> I / O read </Td> </Tr> <Tr> <Th> Pin 26 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 27 </Th> <Td> </Td> <Td> IOCHRDY </Td> </Tr> <Tr> <Th> Pin 28 </Th> <Td> </Td> <Td> Cable select </Td> </Tr> <Tr> <Th> Pin 29 </Th> <Td> </Td> <Td> DDACK </Td> </Tr> <Tr> <Th> Pin 30 </Th> <Td> </Td> <Td> Ground </Td> </Tr> <Tr> <Th> Pin 31 </Th> <Td> </Td> <Td> IRQ </Td> </Tr> <Tr> <Th> Pin 32 </Th> <Td> </Td> <Td> No connect </Td> </Tr> <Tr> <Th> Pin 33 </Th> <Td> </Td> <Td> Addr 1 </Td> </Tr> <Tr> <Th> Pin 34 </Th> <Td> </Td> <Td> GPIO_DMA66_Detect </Td> </Tr> <Tr> <Th> Pin 35 </Th> <Td> </Td> <Td> Addr 0 </Td> </Tr> <Tr> <Th> Pin 36 </Th> <Td> </Td> <Td> Addr 2 </Td> </Tr> <Tr> <Th> Pin 37 </Th> <Td> </Td> <Td> Chip select 1P </Td> </Tr> <Tr> <Th> Pin 38 </Th> <Td> </Td> <Td> Chip select 3P </Td> </Tr> <Tr> <Th> Pin 39 </Th> <Td> </Td> <Td> Activity </Td> </Tr> <Tr> <Th> Pin 40 </Th> <Td> </Td> <Td> Ground </Td> </Tr> </Table>
how many pins are on a pata ide motherboard connector
how many pins are on a pata ide motherboard connector
40
40