I'm learning about superscalar processors and struggling with it a bit. I wrote an assembly program and now must move it through in-order in-issue completion and I have a question about instructions as they move through the latter stages of the pipeline.I have two instructions I1 and I2. I1 performs an operation on R1 and R2 and then loads the result in to R1. I2 needs read the new result of R1 and then overwrite R1, but obviously cannot do so until R1 is finished, otherwise I1 will be incorrect. At what point will I2 be able to correctly read the new result of R1? While I1 is in the WB stage or once I1 has finished the WB stage?Thanks! I also realize this may not be an ideal design, but it's what I have to work with. Also, if this is not CS related and belongs in a different stack exchange, please move. 
Can an instruction with a dependency read the register in same cycle as it's being written?
cpu pipelines