Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y,  R4 = R2 + XR1 = R2 + X,   X = R3 + Y,   Z = R1 + X. I've been a bit stuck in the problem involving instruction pipelining. Any strategy about where to start according to the table?
How to show potential pipeline hazards
computer architecture;cpu pipelines