I read that a supercalar processor has redundant functional units. One can read this e.g. on Wikipedia.How do such redundant units work? Is a complex instruction (for accelerating heavy process, for example Instructions used in Intel IPP, Integrated Performance Primitives) decomposed in micro operations befaure being dispatched among these redudant functional units?What about hardware instructions? Like AES-NI?I also read the Wikipedia article SMT and did not understand the following sentence:Superscalar means executing multiple instructions at the same time while thread-level parallelism (TLP) executes instructions from multiple threads within one processor chip at the same time.I don't understand very well the distinction between these two things. Can somebody explain the subtleties?
Superscalar processors and complex instructions
computer architecture;parallel computing;concurrency