It is well known that connecting NAND gates allows the construction of arbitrary circuits. Furthermore, a NAND gate can be represented as a digraph with four vertices (in order, the two inputs, the core of the gate, and the output) and adjacency matrix $\begin{pmatrix}0 & 0 & 1 & 0 \\ 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 1 \\ 0 & 0 & 0 & 0 \end{pmatrix}$.Gluing these together gives a bijective correspondence between a certain class of digraphs and circuits built from wires and NAND gates. With this in mind, is there a standard terminology for this correspondence/construction?  Are there common references where it is discussed?I am particularly interested in the extent to which topological features of the digraph (e.g., the non-trivial homotopy induced by flip-flops) can be or have been related to the computational features of the corresponding circuit.NB. This was cross posted from MSE after two days.
Boolean circuits and digraphs
graph theory;co.combinatorics;boolean functions