I am trying to find out specifics about caches (in particular which caches are shared between cores and which are not) and have stumpled onto a inconsistency.sudo lshw says*-cache:0     description: L1 cache     physical id: a     slot: Internal Cache     size: 64KiB     capacity: 64KiB     capabilities: synchronous internal write-back*-cache:1     description: L2 cache     physical id: b     slot: External Cache     size: 8MiB     capabilities: synchronous internal write-backbut lscpu claimsL1d cache:   32KL1i cache:   32KL2 cache:   256KL3 cache:  8192KI do not worry too much about instruction and data cache being added together, but where did L2 go?Observed on a machine running Ubuntu 10.10, or to let uname -a speak:Linux name 2.6.35-32-generic #66-Ubuntu SMP Mon Feb 13 21:04:32 UTC 2012 x86_64 GNU/LinuxThis is a general question, but note that neither the most precise manufacturer spec I could find nor Wikipedia do have the necessary detail.Unrelated bonus question: does External Cache mean the cache is shared between the (four) cores (and Internal Cache the opposite)?
lshw and lscpu disagree on caches - which is right?
cpu;cache;system information
Thank you for adding the extra information about the processor to your question. It helps to know that the examples you posted refer to an Intel Core i7-920 Processor.The information provided by lscpu is more accurate because it includes all three levels of cache, L1, L2, and L3. It appears that lshw was only minimally  modified to reflect Intel's addition of an L3 cache to their CPUs. Instead of displaying information about all three caches levels, the information about the size of the L3 cache is apparently reported as L2 cache.I assume that the specs you looked at did not include L1 and L2 cache because within a given microarchitecture they are all the same. For example, for Nehalem this is 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) and 256 KB L2 cache/core..I believe giving each core its own L1 and L2 with a single, much larger common L3 was first introduced as part of the Nehalem (microarchitecture) (in November 2008?).I do not know why lshw uses the term External Cache to refer to the L3. But it strikes me as misleading since the L3 cache is on the CPU die and not what I would consider external. Again, this feels like trying to use old software to describe newer hardware while only making minimal changes to the software.(Probably more could be learned by looking at the actual source code, but I did not have time to try to do that.)Finally, yes the L3 cache is shared among the cores/threads. The following quote is from the Wikipedia article linked above, Hyper-threading is reintroduced along with a reduction in L2, which has been incorporated as L3 Cache which is usable by all cores. 