I understand pipelining but after doing some problems now I am confused during which phase of pipelining the addresses of operands is calculated. I am following this, where it is clearly written that operand addresses is calculated during the Instruction decode phase but I am solving  following problem:ADD A[R0], @B The first operand (destination) A[R0] uses indexed  addressing mode with R0 as the index register. The second operand  (source) @B uses indirect addressing mode. A and B are memory  addresses residing at the second and the third words, respectively.  The first word of the instruction specifies the opcode, the index  register designation and the source and destination addressing modes.  During execution of ADD instruction, the two operands are added and  stored in the destination (first operand). The number of memory cycles  needed during the execution cycle of the instruction is?I think answer of this is 3 memory cycles bcz all addresses of operands will be calculated before the execute starts.but discussion over here They are saying answer will be 4.Why here they are computing addresses of operand during execute phase?
During which phase of instruction execution the addresses of operands is calculated?
computer architecture