Mixed-Mode BIST Using Embedded Processors.
In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements.In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.
Introduction
Integrating complex systems into single chips or implementing
them as multi-chip modules (MCMs) has become
a widespread approach. A variety of embedded processors
and other embedded coreware can be found on the
market, which allows to appropriately split the system
functionality into both hardware and software modules.
With this development, however, system testing has become
an enormous challenge: the complexity and the restricted
accessibility of hardware components require sophisticated
test strategies. Built-in self-test combined with
the IEEE 1149 standards can help to tackle the problem at
low costs [10].
For conventional ASIC testing, a number of powerful
BIST techniques have been developed in the past [1 - 3, 5,
example, it has been shown
that combining random and efficiently encoded deterministic
patterns can provide complete fault coverage while
This work has been supported by the DFG grant "Test und Synthese
schneller eingebetteter Systeme" (Wu 245/1-2).
keeping the costs for extra BIST hardware and the storage
requirements low [13, 14, 32]. In the case of embedded
systems such a high quality test is possible without any
extra hardware by just using the embedded processor to
generate the tests for all other components.
Usually, this kind of functional testing requires large
test programs, and a memory space not always available
on the system. In this paper it will be shown how small
test programs can be synthesized such that a complete
coverage of all non-redundant stuck-at faults in the combinational
parts of the system is obtained. The costs for extra
BIST hardware in conventional systems testing are reduced
to the costs for some hundred bytes of system memory
to store the test routines. The proposed BIST approach
can efficiently exploit design-for-testability structures of
the subcomponents. As shown in Figure 1 during serial
BIST the embedded processor executes a program which
generates test patterns and shifts them into the scan regis-
ter(s) of the component(s) to be tested. Even more effi-
ciently, the presented approach may be used to generate
test data for input registers of pipelined or combinational
subsystems.
embedded
processor
scan-
input
scan-
output
scan-
input
scan-
output
test data
(random &
deterministic
patterns)

Figure

1: Serial BIST approach.
The structure of the test program can be kept very sim-
ple, if only random patterns have to be generated, since
then some elementary processor instructions can be used
[12, 21, 25, 28].
Even a linear feedback shift register (LFSR) can be emulated
very efficiently: Figure 2 shows as an example a
modular LFSR and the corresponding program (for simplicity
the C-code is shown) to generate a fixed number of
state transitions.
void transition (int m, int n,
unsigned int polynomial,
unsigned int *state)
transitions of modular LFSR of degree n */
{
int
for (i=0; i<m; i++)
{
if (*state >> n-1)
{
*state <<=
*state ^= polynomial;
else
*state <<=

Figure

2: Modular LFSR and corresponding program for
generating state transitions.
But usually not all the subcomponents of a system will
be random pattern testable, and for the remaining faults deterministic
test patterns have to be applied. For this pur-
pose, compact test sets may be generated as described in
[16, 18, 22, 27] and reproduced by the test program, or a
hardware-based deterministic BIST scheme is emulated by
the test software [13 - 15, 32]. This kind of mixed-mode
testing may interleave deterministic and random testing or
perform it successively. In each case, the storage requirements
for the deterministic part of the test program are directly
related to the number of undetected faults after random
pattern generation. There is a great trade-off between
the run-time for random test and the memory requirements
of the mixed-mode program. Assume a small improvement
of the random test method which leads to an increase
of the fault coverage from 99.2% to 99.6%. This reduces
the number of undetected faults and the storage requirements
by the factor 1/2. Overall, the efficiency of a mixed-mode
test scheme can be improved to a much higher degree
by modifying its random part rather than its deterministic
part.
In this paper a highly efficient software-based random
BIST scheme is presented which is also used for generating
deterministic patterns. The rest of the paper is organized
as follows: In the next section, different random pattern
test schemes to be emulated by software are evaluated,
and in section 3 the extension to deterministic testing is
described. Subsequently, in section 4, a procedure for optimizing
the overall BIST scheme is presented, and section
5 describes the procedure for generating the mixed-mode
test program. Finally, section 6 gives some experimental
results based on the INTEL 80960CA processor as an example

Emulated Random Pattern Test
Test routines exploiting the arithmetic functions of a
processor can produce patterns with properties which are
sufficient for testing random pattern testable circuits [12,
25], even if they do not completely satisfy all the conditions
for randomness as stated in [11], e.g. However, for
other circuits, in particular for circuits considered as random
pattern resistant, arithmetic patterns may not perform
as well. Linear feedback shift registers (LFSRs) corresponding
to primitive feedback polynomials and cellular
automata are generally considered as stimuli generators
with good properties for random testing [9, 17, 20]. But
the generated sequences still show some linear dependen-
cies, such that different primitive polynomials perform differently
on the same circuit. In some cases, the linear dependencies
may support fault detection, for other circuits
they perform poorly. In the following, the fault coverage
obtained by several LFSR-based pattern generation
schemes will be discussed with some experimental data.
2.1 Feedback Polynomial
In contrast to hardware-based BIST, in a software-based
approach the number and the positions of the feedback taps
of the LFSR have no impact on the costs of the BIST im-
plementation. Thus, for a given length the achievable fault
coverage can be optimized without cost constraints.
Assuming a test per scan scheme as shown in Figure 3
the sensitivity of the fault coverage to the selected feed-back
polynomial has been studied by a series of experiments
for the combinational parts of the ISCAS85 and
ISCAS89 benchmark circuits [4, 6].
LFSR
feedback
scan path
CUT

Figure

3: Scan-based BIST.
Circuit PI F Degree LFSR1 LFSR2 LFSR3 LFSR4 LFSR5 LFSR6 Average
Table

1: Absolute and normalized (w. r. t. worst LFSR) percentage of undetected non-redundant faults after 10,000 patterns.
Fault simulation of 10,000 random patterns was performed
for each circuit using several different feedback
polynomials, all of the same degree. Some typical results
are shown in Table 1. The first four columns contain the
circuit name, the number of inputs, the number of non-redundant
faults, and the selected degree of the feedback
polynomial. 1 The remaining columns show the characteristics
for six different LFSRs. The first entry reports the
percentage of undetected non-redundant faults, and the second
entry normalizes this number to the corresponding
number for the worst LFSR (in %). The worst and best
performing LFSR are printed in bold, respectively. The
last column gives the average over all of the LFSRs.
It can be observed that there is a big variance in the performance
of different LFSRs of the same degree. For s641,
e.g., the best LFSR reduces the number of undetected
faults down to 27% of the faults left undetected by the
worst polynomial.
2.2 Multiple-Polynomial LFSRs
One explanation for the considerable differences in fault
coverage observed in section 2.1 is given by the fact, that
linear dependencies of scan positions may prevent certain
necessary bit combinations in the scan patterns independent
of the initial state of the LFSR [2]. For different
LFSRs the distribution of linear dependencies in the scan
chain is different and, depending on the structure of the
circuit, may have a different impact on the fault coverage.
As shown in Figure 4 the impact of linear dependencies
can be reduced if several polynomials are used. In this
small example the LFSR can operate according to two dif-
1 The degrees of the polynomials have been selected, such that they
were compatible with the requirements for the deterministic test
described in section 3.
ferent primitive feedback polynomials P
and are selected by the input of
the multiplexer. For any given initial state
LFSR produces a scan pattern (a 0 , . , a 7 ), such that,
depending on the selected polynomial, the shown equations
for hold for its components.
st-0
st-0
a 0
a 1
a 2
a 3
a 4
a 5
a 6
a 7
U
I

Figure

4: Scan-based BIST with multiple-polynomial LFSR.
For polynomial P 0 there is a linear relation a 3
which prevents the
combination (1, 1, 1) at the inputs of the AND-gate. This
implies that the polynomial P 0 (X) can never produce a test
for the stuck-at-0 fault at node o 2 . In contrast to that, for
polynomial the same input positions are linearly
independent and produce all possible nonzero bit combinations
and thus a test for the considered fault. Similarly, the
stuck-at-0 fault at node o 1 cannot be tested using polynomial
polynomial P 0 (X) can provide a test.
Using both polynomials, each for a certain number of
patterns, increases the chance of detecting both faults.
Such a multiple-polynomial LFSR can be implemented
efficiently in hardware by trying to share parts of the feed-back
for several polynomials. A software emulation is
also very simple, since the basic procedure to simulate an
LFSR has to be modified only slightly. To control the
selection of feedback polynomials several schemes are
possible. The first is shown in Figure 5 assuming N
random patterns to be generated by p different polynomials
denotes the LFSR operation
corresponding to feedback polynomial P i .
initialize (LFSR);
for
generate -N/p- patterns by LFSR(P i );

Figure

5: Successive multiple-polynomial scheme (SUC).
The polynomials are applied successively to generate
contiguous subsequences of -N/p- random patterns, the
scheme will therefore be referred to as scheme SUC. For
one polynomial the scheme degenerates to the conventional
single polynomial scheme. The possibility to
switch between different distributions of linear dependencies
is paid by the disadvantage that some patterns may
occur repeatedly up to p times. Hence, an overall increase
of the fault coverage cannot be expected, but experiments
have shown that there is indeed an improvement for some
circuits. Table 2 lists the results for the same set of circuits
as studied in the previous section.
Circuit Degree
Table

2: Absolute and normalized (w. r. t. worst and best
single LFSR) percentage of undetected non-redundant
faults for scheme SUC after 10,000 patterns.
For each circuit 10,000 patterns were simulated using p
polynomials. For each experiment the percentage
of undetected non-redundant faults is reported (1st
line), as well as the corresponding normalized numbers for
the worst (2nd line) and for the best single polynomial
(3rd line) of the same degree (in %).
Applying the successive scheme for example to the circuit
c2670 with reduces the number of undetected
faults down to 69.58% compared with the worst single
polynomial. Even more important is that the scheme also
outperforms the best single polynomial and the number of
remaining target faults for ATPG is less than 75%, i.e.
25% percent of the faults left by the best single polynomial
are additionally covered by this scheme.
The randomness of the sequence can be further in-
creased, if the polynomials are not used successively, but
selected randomly for each test pattern. This random selection
can be implemented by a second LFSR as shown in

Figure

6 and will be referred to as scheme RND.
U
feedback
CUT
scan chain

Figure

Hardware scheme for the random selection of feed-back
polynomials (RND).
The selection between p different feedback polynomials
for LFSR1 is controlled by -log 2 p- bits of the state register
of LFSR2. For a software implementation of the structure
of Figure 6, two additional registers are required for
storing the feedback polynomial and the state of LFSR2.
and LFSR2 can be emulated by the same proce-
dure, and the complete routine to generate a sequence of N
random patterns is shown in Figure 7.
initialize (LFSR1);
initialize (LFSR2);
for
{
select P based on state of LFSR2;
generate 1 pattern by LFSR1(P);
perform 1 state transition of LFSR2;

Figure

7: Software routine for the random pattern
generation scheme of Figure 6 (RND).

Table

3 shows the percentage of undetected non-redundant
faults and the corresponding normalized numbers obtained
by the scheme RND for

Circuit Degree
Table

3: Absolute and normalized (w. r. t. worst and best
single LFSR) percentage of undetected non-redundant
faults for scheme RND after 10,000 patterns.
For the randomly selected polynomials, there is a
higher chance of pattern repetitions, but randomly switching
between different distributions of linear dependencies
may improve the quality of the patterns. For some cir-
cuits, this results in an improvement of fault coverage, so
that the set of faults which remain for deterministic testing
is further reduced.
2 . 3 Multiple-Polynomial , Multiple-Seed
Another way of improving the efficiency of a random
test is repeatedly storing a new seed during pattern generation
as investigated for instance in [23]. This technique
can be combined with the use of multiple polynomials as
shown in Figure 8.
U
feedback
CUT
scan chain

Figure

8: Multiple-polynomial, multiple-seed LFSR.
As for the scheme RND, -log 2 p- bits of the state register
of LFSR2 are used to drive the selection between p different
feedback polynomials of degree k for LFSR1. The
remaining k bits provide the seed for LFSR1. In the sequel
this scheme will be referred to as the scheme RND 2 . The
structure of the corresponding test program is shown in

Figure

9.
initialize (LFSR2);
for
{
select seed S and polynomial P
based on state of LFSR2;
initialize LFSR1 with
generate 1 pattern by LFSR1(P);
perform 1 state transition of LFSR2;

Figure

9: Test program for the multiple-polynomial, multi-
ple-seed LFSR (RND 2 ).
Again, in this scheme patterns may occur repeatedly,
but in addition to the advantage of randomly changing the
distribution of linear dependencies this scheme is also able
to generate the all zero-vector which is often needed for
complete fault coverage.

Table

4 gives the results for
(percentage of undetected non-redundant faults and the corresponding
normalized numbers as in Tables 2 and 3).
Circuit Degree
Table

4: Absolute and normalized (w. r. t. worst and best
single LFSR) percentage of undetected non-redundant
faults for scheme RND 2 after 10,000 patterns.
As expected, not for all circuits the fault coverage
increases, but there are circuits where this technique leads
to significant improvements. For circuits s838.1 and
s9234 the best results are obtained compared with all the
experiments before.
3 Software-Based Deterministic BIST
The structure of the multiple-polynomial, multiple-seed
random BIST scheme of Figure 8 is very similar to the deterministic
BIST scheme based on reseeding of multiple-
polynomial LFSRs proposed in [13, 14], see Figure 10.
U
CUT
scan chain (m bits)
id seed

Figure

10: Deterministic BIST scheme based on a multiple-
polynomial LFSR by [14].
A deterministic pattern is encoded as a polynomial identifier
and a seed for the respective polynomial. During test
mode the pattern can be reproduced by emulating the
LFSR corresponding to the polynomial identifier, loading
the seed into the LFSR and performing m autonomous
transitions of the LFSR. After the m-th transition the scan
chain contains the desired pattern which is then applied to
the CUT.
To calculate the encoding systems of linear equations
have to be solved. For a fixed feedback polynomial
of degree k the LFSR produces
an output sequence (a i ) i-0 satisfying the feedback
equation a k. The
LFSR-sequence is compatible with a desired test pattern t
specified bits a holds. Recursively
applying the feedback equation provides a system of
linear equations in the seed variables a 0 , ., a k-1 . If no solution
can be found for the given polynomial, the next
available polynomial is tried, and in [14] it has been
shown that already for 16 polynomials there is a very high
probability of success that a deterministic pattern with s
specified bits can be encoded into an s-bit seed.
Hence, if p different polynomials are available and the
polynomial identifier is implemented as a "next bit", the
seed and the next bits for a deterministic test set
number of specified bits s max require
bits of storage. Minimizing
S(T) requires both minimizing the maximum number of
care bits s max and the number of patterns N. In [15] an
ATPG-algorithm was presented which generates test patterns
where the number of specified bits s max is mini-
mized. In a mixed-mode BIST approach the number N of
patterns is highly correlated to the number of faults left
undetected after random testing.
4 Synthesizing the BIST Scheme
Since the efficiency of a mixed-mode BIST scheme
strongly depends on the number of hard faults to be covered
by deterministic patterns, a major concern in synthesizing
the BIST scheme is optimizing the random test.
The experimental data of section 2 show that significant
variances in the fault efficiency achieved by different
LFSR schemes exist, and that there is no universal
scheme or polynomial working for all of the circuits. In
the sequel, a procedure is presented for determining an optimized
LFSR scheme. The selection of the LFSRs is
guided, such that the fault efficiency is maximized while
satisfying the requirements for an efficient encoding of deterministic
patterns for the random pattern resistant faults.
Assuming a table of primitive polynomials available the
proposed procedure consists of 4 steps:
Perform ATPG to eliminate the redundant faults and to
estimate the maximum number of specified bits, s max ,
to be expected in the test cubes for the hard faults.
Select M polynomials of degree s max randomly, and
perform fault simulation with the corresponding shift
register sequences. Rank the polynomials according to
the fault coverage achieved.
Select the P best polynomials and store the highest
fault coverage and the corresponding LFSR as
BEST_SCHEME.
Using polynomials, simulate the schemes
SUC, RND, and RND 2 . Update BEST_SCHEME to
the best solution obtained so far.
The number M is mainly determined by a limit of the
computing time to be spent. The number P is also restricted
by the computing time available, but in addition
to that each LFSR requires two registers of the processor
for pattern generation. So, the register file of the target
processor puts a limit on P, too.

Table

5 shows the results achieved by this procedure for
the same set of circuits as studied in section 2. For the
same degrees as used in section 2 sequences of 10,000
random patterns were applied.
Scheme
best UF worst

Table

5: Best schemes and relation to best and worst single
polynomial solution.
The second and third column show the best scheme and
the corresponding number of polynomials p, column 4
provides the fault efficiency FE (percentage of detected
non-redundant faults). The percentage of faults left undetected
by the best scheme is reported in column UF.
UF best normalizes this solution to the number obtained by
the best single polynomial, UF worst refers to the worst
single polynomial.

Table

5 indicates that the search for an appropriate random
test scheme can reduce the number of remaining
faults significantly. The procedure needs M
runs of fault simulations, but may decrease the storage
amount needed for deterministic patterns considerably.
These savings in memory for the mixed-mode test program
are particularly important, if the test program has to
be stored in a ROM for start-up and maintenance test.
Generating Mixed-Mode Test Programs
Test programs implementing the random test schemes
and the reseeding scheme for deterministic patterns were
generated for the INTEL 80960CA as a target processor.
Its large register set made a very compact coding possible.
Since the part of the test program which generates the
deterministic patterns is a superset of instructions required
for implementing any of the random schemes, only the
example for the most complex random scheme is shown.
The mixed-mode test program of Figure 11 generates
random test patterns by multiple-polynomial, multiple-
seed LFSR emulation, and switches to the reseeding
scheme afterwards.
The program of Figure 11 requires 27 words in memory
but assumes that all LFSRs fit into registers. This
steps1 equ . ; number of steps for lfsr1
steps2 equ . ; number of steps for lfsr2
steps_det equ . ; number of steps for deterministic test
len1 equ . ; position of msb of lfsr1
len2 equ . ; position of msb of lfsr2
testport equ . ; address of testport
no_poly_bits equ . ; number of bits for polynomial choice
mask equ . , define mask
start dq startvector ; define startvector for lfsr2
poly dq polynomials ; define polynomials for lfsr1
seeds dq seedvectors ; define seeds for det. test
seed_offset equ seeds - start ; define offset for seed table
begin: lda testport, r10 ; load address of testport
lda steps_det, r11 ; load loopcounter for lfsr1 in det. mode
lda steps1, r12 ; load loop counter for lfsr1
lda start, r14 ; load startvector address for lfsr1
ld (r14), r6 ; load startvector for lfsr2
ld 4(r14), r7 ; load polynomial for lfsr2
l0: mov r6, r4 ; initialize lfsr1 with contents of lfsr2
and mask, r4, r15 ; compute poly-id
ld 8(r14)[r15*4], r5 ; polynomial for lfsr1
lda no_poly_bits, r15 ; load number of bits for poly-id
l1: shro no_poly_bits, r4, r4 ; shift poly-bits
lda steps2, r13 ; load loop counter for lfsr1
l2: st r4, (r10) ; write testpattern to testport
mov r4, r8
shlo 1, r8, r4 ; shift left
bbc len2, r8, l3 ; branch if msb of lfsr2 equal zero
xor r4, r5, r4 ; xor
decrement loop counter
cmpibne r13, 0, l2 ; branch not equal zero
mov r6, r8
shlo 1, r8, r6 ; shift left
bbc len1, r8, l4 ; branch if msb of lfsr1 equal zero
xor r6, r7, r6 ; xor
l4: subi r12, 1, r12 ; decrement loop counter
cmpibg r12, r11, l0 ; branch if r12 > steps_det
ld seed_offset(r14)[r12*4],r6 ; load seed
cmpibne r12,0,l0

Figure

11: Mixed-mode BIST program.
is always possible for random pattern generation, but encoding
deterministic patterns may lead to LFSR lengths
exceeding bits. In this case, the program of Figure 11
has to be modified in a straightforward way, and requires
more memory. Table 6 gives the relation between memory
requirements and LFSR lengths.
LFSR length
Memory requirements
(words)

Table

length and memory requirements for the
mixed-mode test program.
In addition to the program size, memory has to be reserved
for storing the polynomials and the seeds in order to
decode the deterministic patterns. The experimental results
of the next section show that these data form by far the
major part of the memory requirements.
6 Experimental Results
The described strategy for generating mixed-mode test
programs was applied to all the benchmark circuits for M
e. for each circuit M 28
runs of fault simulation were performed to determine the
best random scheme. Tables 7 and 8 show the results.
Circuit PI Degree Best Scheme p

Table

7: Circuit characteristics and best random scheme.
The selected random schemes and their characteristic
data are reported in Table 7. Columns 2 and 3 list the
number of primary inputs PI and the degree of the poly-
nomials. The best random scheme and the number of polynomials
are reported in the subsequent columns.

Table

8 shows the detailed results. The number of non-redundant
faults for each circuit is given in column 2. The
efficiency of the random scheme is characterized again by
the fault efficiency FE, the percentage of undetected non-redundant
faults UF and the normalized numbers for UF
with respect to the best (UF best ) and the average (UF average )
single polynomial solution in columns 3 through 6.
Circuit F FE UF UF best UF average
s838.1 931 76.48 23.52 71.1 65.75

Table

8: Fault efficiency and percentage of undetected non-redundant
faults for the best random schemes after
10,000 patterns.
The reduction of the remaining faults obtained by the
best random test scheme is significant. For instance, the
circuit c7552 is known to be very random pattern resis-
tant, and a single polynomial solution in the average leads
to a fault efficiency of 95.79% leaving 4.21% of the faults
for deterministic encoding. For the same circuit, the RND 2
scheme achieves a fault efficiency of 98.87%, and only
1.13% or, absolutely, 84 faults are left. This corresponds
to a reduction of the remaining faults down to 27%.
For circuits s820 and s1423 a careful selection of the
random scheme even makes the deterministic test super-
fluous. Finally, it should be noted that for the larger cir
cuits already a small relative reduction means a considerable
number of faults which are additionally covered by the
random test and need not be considered during the deterministic
test. For example for circuit s38417 a reduction
down to 85.75% and 92.26%, respectively, means that additional
313 and 158, respectively, faults are eliminated
during random test.

Table

9 shows the resulting number of test patterns required
for the random pattern resistant faults and the
amount of test date storage (in bits) for the best random
scheme compared to a random test using an average single
polynomial. This includes the storage needed for the poly-
nomials, the initial LFSR states for the random test and
the encoded deterministic test set. Since the goal of this
work was to determine the impact of the random test on
the test data storage, a standard ATPG tool was selected to
perform the experiments [24]. For all circuits the fault efficiency
is 100% after the deterministic test.
Circuit
Deterministic
patterns
Test data storage
(bits)
scheme
Average
polynomial
scheme
Average
polynomial
s420.1 22 34 503 776
s1238 7 21 198 431
s5378 22 31 759 883

Table

9: Number of deterministic patterns and storage requirements
for the complete test data (in bits).
The results show that an optimized random test in fact
considerably reduces the number of deterministic patterns
and the overall test data storage. This is particularly true
for the circuits known as random pattern resistant. E.g. for
circuit c7552 the number of deterministic patterns is reduced
from 92 to 51 and the reduction in test data storage
is about 5K. For circuit s38417 the best scheme eliminates
137 deterministic patterns, which leads to a reduction
in test data storage of more than 14K. As shown in Table
already with standard ATPG the proposed technique
requires less test data storage than an approach based on
storing a compact test set (cf. [16, 18, 22, 27]).
Circuit
Deterministic
patterns
Test data storage
(bits)
scheme
Compact
Test
scheme
Compact
Test
s420.1 22 43 503 1505
s5378 22 104 759 22256

Table

10: Amount of test data storage for the proposed
approach and for storing a compact test set.
It can be expected, that the test data storage for the
presented approach could be reduced even further, if an
ATPG tool specially tailored for the encoding scheme were
used as described in [15].
7 Conclusion
A scheme for generating mixed-mode test programs for
embedded processors has been presented. The test program
uses both new, highly efficient random test schemes and a
new software-based encoding of deterministic patterns.
It has been shown that the careful selection of primitive
polynomials for LFSR-based random pattern generation
has a strong impact on the number of undetected faults,
and a multiple-polynomial random pattern scheme provides
significantly better results in many cases. The quality
0of the random scheme has the main impact on the
overall size of a mixed-mode test program. As an example,
for the processor INTEL 80960CA test programs were
generated, and for all the benchmark circuits a complete
coverage of all non-redundant faults was obtained.



--R

Test Embedding in a Built-in Self-Test Environment

Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator in

Combinational Profiles of Sequential Benchmark Circuits
A New Pattern Biasing Technique for BIST
BIST Hardware Generator for Mixed Test Scheme

Multichip Module Self-Test Provides Means to Test at Speed
Shift Register Sequences
Test Generation Based On Arithmetic Operations
Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

Pattern Generation for a Deterministic BIST Scheme
"Compaction of Test Sets Based on Symbolic Fault Simulation"
Cellular Automata-Based Pseudorandom Number Generators for Built-In Self-Test
"Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits"


Accumulator Built-In Self Test for High-Level Synthesis
"ROTCO: A Reverse Order Test Compaction Technique"
A Multiple Seed Linear Feed-back Shift Register
Advanced Automatic Test Generation and Redundancy Identification Techniques

Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Minimal Test Sets for Combinational Circuits

Circuits for Pseudo-Exhaus- tive Test Pattern Generation
Test Using Unequiprobable Random Patterns
Multiple Distributions for Biased Random Test Patterns
Decompression of Test Data Using Variable-Length Seed LFSRs
--TR

--CTR
Sybille Hellebrand , Hua-Guo Liang , Hans-Joachim Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, Journal of Electronic Testing: Theory and Applications, v.17 n.3-4, p.341-349, June-August 2001
Hua-Guo Liang , Sybille Hellebrand , Hans-Joachim Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST, Journal of Electronic Testing: Theory and Applications, v.18 n.2, p.159-170, April 2002
Rainer Dorsch , Hans-Joachim Wunderlich, Reusing Scan Chains for Test Pattern Decompression, Journal of Electronic Testing: Theory and Applications, v.18 n.2, p.231-240, April 2002
Liang Huaguo , Sybille Hellebrand , Hans-Joachim Wunderlich, A mixed-mode BIST scheme based on folding compression, Journal of Computer Science and Technology, v.17 n.2, p.203-212, March 2002
embedded systems;deterministic BIST;BIST;random pattern testing