Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.
Introduction
System-on-chip (SOC) integrated circuits composed of proces-
sors, memories, and peripheral interface devices in the form of embedded
cores, are now commonplace. Nevertheless, there remain
several roadblocks to rapid and efficient system integration. Test development
is now seen as a major bottleneck in SOC design, and
test challenges are a major contributor to the widening gap between
design and manufacturing capability [23].
The 1999 International Technology Roadmap for Semiconductors
[12] clearly identifies test access for SOC cores as one of the
challenges for the near future. Test access mechanisms (TAMs)
and test wrappers have been proposed as important components of
an SOC test access architecture [23]. TAMs deliver pre-computed
test sequences to cores on the SOC, while test wrappers translate
these test sequences into patterns that can be applied directly to the
cores.
Test wrapper and TAM design is of critical importance in SOC
system integration since it directly impacts the vector memory depth
required on the ATE, as well as testing time, and thereby affects
test cost. A TAM and wrapper design that minimizes the idle time
spent by TAMs and wrappers during test directly reduces the number
of don't-care bits in vectors stored on the tester, thereby reducing
vector memory depth. The design of efficient test access architectures
has become an important focus of research in core test integration
[1, 3, 4, 5, 6, 14, 17, 19]. This is especially timely and relevant,
This research was supported in part by the National Science Foundation
under grant number CCR-9875324.
since the proposed IEEE P1500 standard provides a lot of freedom in
optimizing its standardized, but scalable wrapper, and leaves TAM
optimization entirely to the system integrator [10, 18].
The general problem of SOC test integration includes the design
of TAM architectures, optimization of the core wrappers, and
test scheduling. The goal is to minimize the testing time, area
costs, and power consumption during testing. The wrapper/TAM
co-optimization problem that we address in this paper is as follows.
Given the test set parameters for the cores on the SOC, as well as
the total TAM width, determine an optimal number of TAMs for the
SOC, an optimal partition of the total TAM width among the TAMs,
an optimal assignment of cores to each TAM, and an optimal wrapper
design for each core, such that the overall system testing time is
minimized. In order to solve this problem, we examine a progression
of three incremental problems structured in order of increasing com-
plexity, such that they serve as stepping-stones to the more general
problem of wrapper/TAM design. The first problem PW is related
to test wrapper design. The next two problems PAW and PPAW are
related to wrapper/TAM co-optimization.
a wrapper for a given core, such that (a) the core
testing time is minimized, and (b) the TAM width required for the
core is minimized.
2. PAW : Determine (i) an assignment of cores to TAMs of given
widths and (ii) a wrapper design for each core, such that SOC testing
time is minimized. (Item (ii) equals PW .)
3. a partition of the total TAM width among
the given number of TAMs, (ii) an assignment of cores to the TAMs,
and (iii) a wrapper design for each core, such that SOC testing time
is minimized. (Items (ii) and (iii) together equal PAW .)
These three problems lead up to PNPAW , the more general problem
of wrapper/TAM co-optimization described as follows.
the number of TAMs for the SOC, (ii) a partition
of the total TAM width among the TAMs, (iii) an assignment
of cores to TAMs, and (iv) a wrapper design for each core, such that
testing time is minimized. (Items (ii), (iii) and (iv) together
equal
In the remainder of this paper, we formally define and analyze these
problems, and propose solutions for each.
In this paper, we assume the "test bus" model for TAMs. We
assume that the TAMs on the SOC operate independently of each
however, the cores on a single TAM are tested sequentially.
This can be implemented either by (i) multiplexing all the cores assigned
to a TAM, or (ii) by testing one of the cores on the TAM,
while the other cores on the TAM are bypassed. Furthermore, in this
paper, we are addressing the problem of core test only; hence, we
do not discuss issues related to test wrapper bypass and interconnect
test.
The organization of this paper is as follows. In Section 2, we
discuss prior work in the area of TAM and test wrapper design. In
Section 3, we present two SOCs that we use as running examples
throughout the paper. In Section 4, we address Problem PW . In
Section 5, we develop improved integer linear programming (ILP)
models for optimizing core assignment to TAMs (Problem PAW ).
In Section 6, we present new ILP models for TAM width partitioning
(Problem PPAW ). In Section 7, we present an enumerative method
that can often reduce the execution time required to solve PPAW
when the number of TAMs is small. Finally, in Section 8, we examine
PNPAW , the general problem of wrapper/TAM co-optimization.
Section 9 concludes the paper.
Prior work
Test wrappers provide a variety of operation modes, including
normal operation, core test, interconnect test, and (optional) by-pass
[16]. In addition, test wrappers need to be able to perform test
width adaptation if the width of the TAM is not equal to the number
of core terminals. The IEEE P1500 standard addresses the design of
a flexible, scalable wrapper to allow modular testing [10, 18]. This
wrapper is flexible and can be optimized to suit the type of TAM and
test requirements for the core.
A "test collar" was proposed in [21] to be used as a test wrapper
for cores. However, test width adaptation and interconnect test were
not addressed. The issue of efficient de-serialization of test data by
the use of balanced wrapper scan chains was discussed in [6]. Balanced
wrapper scan chains, consisting of chains of core I/Os and
internal scan chains, are desirable because they minimize the time
required to scan in test patterns from the TAM. However, no mention
was made of the method to be used to arrive at a balanced assignment
of core I/Os and internal scan chains to TAM lines. The
TESTSHELL proposed in [16] has provisions for the IEEE P1500
required modes of operation. Furthermore, heuristics for designing
balanced wrapper scan chains, based on approximation algorithms
for the well-known Bin Design problem [7], were presented in [17].
However the issue of reducing the TAM width required for a wrapper
was not addressed.
A number of TAM designs have been proposed in the literature.
These include multiplexed access [11], partial isolation rings [20],
core transparency [8], dedicated test bus [21], reuse of the existing
system bus [9], and a scalable bus-based architecture called
RAIL [16]. Bus-based TAMs, being flexible and scalable, appear
to be the most promising. However, their design has largely been
ad hoc and previous methods have seldom addressed the problem
of minimizing testing time under TAM width constraints. While [1]
presents several novel TAM architectures (i.e., multiplexing, daisy
chaining and distribution), it does not directly address the problem
of optimal sizing of TAMs in the SOC. In particular, only internal
scan chains are considered in [1], while wrappers and functional
I/Os are ignored. Moreover, the lengths of the internal scan chains
are not considered fixed, and therefore [1] does not directly address
the problem of designing test architectures for hard cores.
More recently, integrated TAM design and test scheduling has
been attempted in [14, 19]. However, in [14, 19], the problem of
optimizing test bus widths and arbitrating contention among cores
for test width was not addressed. In [19], the cost estimation for
TAMs was based on the number of bridges and multiplexers used;
the number of TAM wires was not taken into consideration. Fur-
thermore, in [14] the impact of TAM widths on testing time was not
included in the cost function. The relationship between testing time
and TAM widths using ILP was examined in [3, 5], and TAM width
optimization under power and routing constraints was studied in [4].
However, the problem of effective test width adaptation in the wrapper
was not addressed. This led to an overestimation of testing time
and TAM width. Improved wrapper designs and new ILP models for
TAM design are therefore necessary.
In this paper, we present a new wrapper/TAM co-optimization
methodology that overcomes the limitations of previous TAM design
approaches that have addressed TAM optimization and wrapper
design as independent problems. The new wrapper design algorithm
that we present improves upon previous approaches by minimizing
the core testing time, as well as reducing the TAM width required for
the core. We propose an approach based on ILP to solve the problems
of determining an optimal partition of the total TAM width
and determining an optimal core assignment to the TAMs. We also
address a new problem, that of determining the optimal number of
TAMs for an SOC. This problem gains importance with increasing
SOC size. This paper, to the best of our knowledge, is the first in
which a wrapper/TAM co-optimization methodology has been applied
to an industrial SOC.
3 Example SOCs
In order to illustrate the proposed wrapper/TAM co-optimization
methods presented in this paper, and to demonstrate their effective-
ness, we use two representative SOCs as running examples through-out
this paper. The first one is an academic SOC named d695 (de-
scribed as system S2 in [5]), and the second one is an industrial SOC
from Philips, named p93791. The number (e.g., 93791) in each SOC
name is a measure of its test complexity. This number is calculated
by considering the numbers of functional inputs n i , functional outputs
chains sc i , internal scan chain
lengths l i;1 ; l test patterns p i for each Core i, as
well as the total number of cores N in the SOC, all of which contribute
to the complexity of the wrapper/TAM co-optimization prob-
lem. We calculate the SOC test complexity number using the formula
l i;r ). The letters "d"
and "p" in d695 and p93791 refer to Duke University and Philips,
respectively.
SOC d695 consists of two combinational ISCAS'85 and eight sequential
benchmark circuits. Table 1 presents the test data
for each core in d695. We assume that the ISCAS'89 circuits contain
well-balanced internal scan chains. The proposed wrapper/TAM
co-optimization methodology is also applicable to SOCs containing
non-scanned sequential cores, since these cores can be treated as
combinational (having zero-length internal scan chains) for the purpose
of testing time calculation. SOC p93791 contains cores.
Of these, are memory cores embedded within hierarchical logic
cores.

Table

2 presents the data for the 14 logic cores and embedded
memories in SOC p93791. We do not describe each core
in p93791 individually due to insufficient space. Test data for each
individual core in p93791 is presented in [13].
The experimental results presented in this paper were obtained
using a Sun Ultra 80 with a 450 MHz processor and 4096 MB memory

Number of Scan chain
Circuit Test Functional Scan lengths
patterns I/Os chains Min Max

Table

1. Test data for the cores in d695 [5].
Number range Scan chain
Circuit Test Functional Scan lengths
patterns I/Os chains Min Max
Logic
cores 11-6127 109-813 11-46 1 521
Memory
cores 42-3085 21-396 -

Table

2. Ranges in test data for the 32 cores in p93791.
4 Test wrapper design
A standardized, but scalable test wrapper is an integral part of
the IEEE P1500 working group proposal [10]. A test wrapper is a
layer of DfT logic that connects a TAM to a core for the purpose of
test [23]. Test wrappers have four main modes of operation. These
are (i) Normal operation, (ii) Intest: core-internal testing, (iii) Extest:
core-external testing, i.e., interconnect test, and (iv) Bypass mode.
Wrappers may need to perform test width adaptation when the TAM
width is not equal to the number of core terminals. This will often
be required in practice, since large cores typically have hundreds of
core terminals, while the total TAM width is limited by the number
of SOC pins. In this paper, we address the problem of TAM design
for Intest, and therefore we do not discuss issues related to Bypass
and Extest.
The problem of designing an effective width adaptation mechanism
for Intest can be broken down into three problems [17]: (i)
partitioning the set of wrapper scan chain elements (internal scan
chains and wrapper cells) into several wrapper scan chains, which
are equal in number to the number of TAM lines, (ii) ordering the
scan elements on each wrapper chain, and (iii) providing optional
bypass paths across the core. The problems of ordering scan elements
on wrapper scan chains and providing bypass paths were
shown to be simple in [17], while that of partitioning wrapper scan
chain elements was shown to be NP-hard. Therefore, in this sec-
tion, we address only the problem of effectively partitioning wrapper
scan chain elements into wrapper scan chains.
Recent research on wrapper design has stressed the need for balanced
wrapper scan chains [6, 17]. Balanced wrapper scan chains
are those that are as equal in length to each other as possible. Balanced
wrapper scan chains are important because the number of
clock cycles to scan in (out) a test pattern to (from) a core is a function
of the length of the longest wrapper scan-in (scan-out) chain.
be the length of the longest wrapper scan-in (scan-out)
chain for a core. The time required to apply the entire test set to the
core is then given by
where p is the number of test patterns. This time T decreases as
both s i and so are reduced, i.e., as the wrapper scan-in (and scan-
out) chains become more equal in length.

Figure

1 illustrates the difference between balanced and unbalanced
wrapper scan chains; Bypass and Extest mechanisms are not
shown. In Figure 1(a), wrapper scan chain 1 consists of two input
cells and two output cells, while wrapper scan chain 2 consists of
three internal scan chains that contain 14 flip-flops in total. This
results in unbalanced wrapper scan-in/out chains and a scan-in and
scan-out time per test pattern of 14 clock cycles each. On the other
hand, with the same elements and TAM width, the wrapper scan
chains in Figure 1(b) are balanced. The scan-in and scan-out time
per test pattern is now 8 clock cycles.
Wrapper
scan chain 1
Wrapper
scan chain 2
Wrapper
scan chain 2
Wrapper
Wrapper
scan chain 1
Wrapper
(a) (b)

Figure

1. Wrapper chains: (a) unbalanced, (b) balanced.
The problem of partitioning wrapper scan chain elements into
balanced wrapper scan chains was shown to be equivalent to the
well-known Multiprocessor Scheduling and Bin Design problems
in [17]. In this paper, the authors presented two heuristic algorithms
for the Bin Design problem to solve the wrapper scan chain element
partitioning problem. Given k TAM lines and sc internal scan
chains, the authors assigned the scan elements to m wrapper scan
chains, such that maxfs i ; sog was minimized. This approach is effective
if the goal is to minimize only maxfs sog. However, we are
addressing the wrapper design problem as part of the more general
problem of wrapper/TAM co-optimization, and therefore we would
also like to minimize the number of wrapper chains created. This
can be explained as follows. Consider a core that has four internal
scan chains of lengths 32, 8, 8, and 8, respectively, 4 functional
inputs, and 2 functional outputs. Let the number of TAM lines provided
be 4. The algorithms in [17] will partition the scan elements
among four wrapper scan chains as shown in Figure 2(a), giving
However, the scan elements may also be assigned
to only 2 wrapper scan chains as shown in Figure 2(b), which
also gives maxfs 32. The second assignment, however, is
clearly more efficient in terms of TAM width utilization, and therefore
would be more useful for a wrapper/TAM co-optimization strategy

Consider Core 6, the largest logic core from p93791. Core 6
has 417 functional inputs, 324 functional outputs, 72 bidirectional
I/Os, and 46 internal scan chains of lengths: 7 scan chains  500
bits, scan chains  520 bits, and 9 scan chains  521 bits, re-
spectively. The Combine algorithm [17] was used to create wrapper
configurations for Core 6, for values of k between 1 and 64 bits.
Since the functional inputs in Core 6 outnumber the functional out-
puts, . The value of s i obtained for each value
of k is illustrated in Figure 3. From the graph, we observe that as
increases, s i decreases in a series of distinct steps. This is be-
Scan chain -
Scan chain - 8 FF
Scan chain - 8 FF
I O
I
I Scan chain - 8 FF O
I (a)
Scan chain -
O
I I I I Scan chain - 8 FF Scan chain - 8 FF Scan chain - 8 FF O
(b)

Figure

2. Wrapper design example using (a) four wrapper
scan chains, and (b) two wrapper scan chains.
cause as k increases, the core internal scan chains are redistributed
among a larger number of wrapper scan-in chains; thus s i decreases
only when the increase in k is sufficient to remove an internal scan
chain from the longest wrapper scan-in chain. For example, when
the internal scan chains in Core 6 are distributed among 24 wrapper
scan-in chains, s long. The value of s i remains at 1040
until k reaches 39, when s i drops to 1020. Hence, for 24  k  38,
only 24 wrapper scan-in chains need be designed. Our wrapper design
strategy is therefore to (i) minimize testing time by minimizing
identify the maximum number k 0 of wrapper
scan chains that actually need to be created to minimize testing time,
when k TAM lines are provided to the wrapper. The set of values of
corresponding to the values of 1  k  1 is known as the set of
pareto-optimal points for the graph.
TAM width (bits)
28
Longest
wrapper
scan-in
chain

Figure

3. Decrease in s i with increasing k for Core 6.
PW , the two-priority wrapper optimization problem that this section
addresses can now be formally stated as follows.
Given a core with n functional inputs, m functional out-
puts, sc internal scan chains of lengths l 1
tively, and TAM width k, assign the n +m+ sc wrapper scan
chain elements to k 0  k wrapper scan chains such that (i)
is the length of the
longest wrapper scan-in (scan-out) chain, and (ii) k 0 is minimum
subject to priority (i).
Priority (ii) of PW is based on the earlier observation that
can be minimized even when the number of wrapper
scan chains designed is less than k. This reduces the width of the
TAM required to connect to the wrapper. Problem PW is therefore
analogous to the problem of Bin Design (minimizing the size
of the bins), with the secondary priority of Bin Packing (minimiz-
ing the number of bins). If the value of kmax in Problem PW is
always fixed at k, then Problem PW reduces to the Partitioning of
Scan Chains (PSC) Problem [17], and is therefore clearly NP-hard,
since Problem PSC was shown to be NP-hard in [17].
We have developed an approximation algorithm based on the
Best Fit Decreasing (BFD) heuristic [7] to solve PW efficiently. The
algorithm has three main parts, similar to [17]: (i) partition the internal
scan chains among a minimal number of wrapper scan chains
to minimize the longest wrapper scan chain length, (ii) assign the
functional inputs to the wrapper scan chains created in part (i), and
(iii) assign the functional outputs to the wrapper scan chains created
in part (i). To solve part (i), the internal scan chains are sorted
in descending order. Each internal scan chain is then successively
assigned to the wrapper scan chain, whose length after this assignment
is closest to, but not exceeding the length of the current longest
wrapper scan chain. Intuitively, each internal scan chain is assigned
to the wrapper scan chain in which it achieves the best fit. If there is
no such wrapper scan chain available, then the internal scan chain is
assigned to the current shortest wrapper scan chain. Next the process
is repeated for part (ii) and part (iii), considering the functional inputs
and outputs as internal scan chains of length 1. The pseudocode
for our algorithm Design wrapper is illustrated in Figure 4.
Procedure Design wrapper
Part (i)
1. Sort the internal scan chains in descending order of length
2. For each internal scan chain l
3. Find wrapper scan chain Smax with current maximum length
4. Find wrapper scan chain Smin with current minimum length
5. Assign l to wrapper scan chain S, such that
6. If there is no such wrapper scan chain S then
7. Assign l to Smin
Part (ii)
8. Add the functional inputs to the wrapper chains created in part (i)
Part (iii)
9. Add the functional outputs to the wrapper chains created in part (i)

Figure

4. Algorithm for wrapper design that minimizes testing
time and number of wrapper scan chains.
We base our algorithm on the BFD heuristic mainly because BFD
utilizes a more sophisticated partitioning rule than First Fit Decreasing
since each scan element is assigned to the wrapper scan
chain in which it achieves the best fit [7]. FFD was used as a subroutine
to the wrapper design algorithm in [17]. In our algorithm,
a new wrapper scan chain is created only when it is not possible
to fit an internal scan chain into one of the existing wrapper scan
chains without exceeding the length of the current longest wrapper
scan chain. Thus, while the algorithms presented in [17] always
use k wrapper scan chains, Design wrapper uses as few wrapper
scan chains as possible, without compromising test application
time. The worst-case complexity of the Design wrapper algorithm
is O(sc log sc + sc  k), where sc is the number of internal scan
chains and k is the limit on the number of wrapper scan chains.
From

Figure

3, we further observe that as k is increased beyond
47, there is no further decrease in testing time, since the longest
internal scan chain of the core has been assigned to a dedicated
wrapper scan chain, and there is no other wrapper scan chain longer
than the longest internal scan chain. We next derive an expression
for this maximum value of TAM width kmax required to minimize
testing time for a core.
Theorem 1 If a core has n functional inputs, m functional outputs,
and sc internal scan chains of lengths l 1 respectively, an
upper bound kmax on the TAM width required to minimize testing
time is given by
Proof: The test application time for a core is given by
is the length
of the longest wrapper scan-in (scan-out) chain, and p is the number
of test patterns in the test set. A lower bound on T , for any
TAM width k, is therefore given by (1
sogg. The lowest value that maxfs i ; sog and
can attain, is given by the length of the core's longest
internal scan chain g. Therefore,
g. Let the upper bound on k at which
minfTg is reached be denoted as kmax . At this value of k, the number
of flip-flops assigned to each wrapper scan chain (either scan-in
or scan-out, whichever has more flip-flops) is at most max i g.
Therefore kmax is the smallest integer, such that kmax
is at least the sum of all the flip-flops on the wrapper scan chains,
l i . Thus, kmax is the
smallest integer, such that kmax  maxfn;mg+
. Therefore,
l i
. 2
The value of kmax for each core can further be used to determine
an upper bound on the TAM width for any TAM on the SOC. In Section
6, we show how kmax can be used to bound the TAM widths,
when obtaining an optimal partition of total test width among TAMs
on the SOC.

Table

3 presents results on the savings in TAM width obtained
using Design wrapper for Core 6. For larger values of k, the number
of TAM lines actually used is far less than the number of available
TAM lines; thus, with respect to TAM width utilization, Design
wrapper is considerably more efficient than the wrapper design
algorithms proposed in [17].
Available TAM Longest
TAM width wrapper
width utilized scan chain
9 9 3081
Available TAM Longest
TAM width wrapper
width utilized scan chain
22 22 1521
43-45 43 1000

Table

3. Design wrapper results for Core 6.
In the next section, we address PAW , the second problem of our
TAM/wrapper co-optimization framework-determining an assignment
of cores to TAMs of given widths and optimizing the wrapper
design for each core.
5 Optimal core assignment to TAMs
In this paper, we assume the "test bus" model for TAM design.
We assume that each of the B TAMs on the SOC are independent;
however, the cores on each TAM are tested in sequential order. This
can be implemented either by (i) multiplexing all the cores assigned
to a TAM as in Figure 5(a), or (ii) by testing one of the cores on the
TAM, while the other cores on the TAM are in Bypass mode as in

Figure

5(b). Furthermore, the core bypass may either be an internal
bypass within the wrapper or an external bypass. This paper does
not directly the address the design of hierarchical TAMs. The SOC
hierarchy is flattened for the purpose of TAM design and hierarchical
cores are considered as being at the same level in test mode.
Multiplexed cores
Core A
Core A
Internal bypass
External bypass
(a) (b)

Figure

5. Test bus model of TAM design: (a) multiplexed
cores, (b) cores with bypass on a test bus.
The problem that we examine in this section, that of minimizing
the system testing time by assigning cores to TAMs when TAM
widths are known, can be stated as follows.
Given N cores and B TAMs of test widths
determine an assignment of cores to the
TAMs and a wrapper design for each core, such that the testing
time is minimized.
This problem can be shown to be NP-hard using the techniques
presented in [5]. However, for realistic SOCs the sizes of the problem
instances were found to be small and could be solved exactly
using an ILP formulation in execution times less than a second.
To model this problem, consider an SOC consisting of N cores
and B TAMs of widths w1 ; assigned
to TAM j, let the time taken to test Core i be given by T i (w j )
clock cycles. The testing time T i (w j ) is calculated as T i (w
is the number of test
patterns for Core i and s i (so ) is the length of the longest wrapper
scan-in (scan-out) chain obtained from Design wrapper. We introduce
binary variables x ij (where 1  i  N and 1  j  B),
which are used to determine the assignment of cores to TAMs in the
SOC. Let x ij be a 0-1 variable defined as follows:
is assigned to TAM j
The time needed to test all cores on TAM j is given
by
Since all the TAMs can be used
simultaneously for testing, the system testing time equals
A mathematical programming model for this problem can be formulated
as follows.
Objective: Min.
subject to
every core is connected to exactly
one TAM.
Before we describe how a solution to PAW can be obtained, we
briefly describe ILP, and then present the ILP formulation based on
the above mathematical programming model to solve PAW . The
goal of ILP is to minimize a linear objective function on a set of
integer variables, while satisfying a set of linear constraints [22]. A
typical ILP model can described as follows:
minimize: Ax
subject to: Bx  C, such that x  0,
where A is an objective vector, B is a constraint matrix, C is a
column vector of constants, and x is a vector of integer variables.
Efficient ILP solvers are now readily available, both commercially
and in the public domain [2].
The minmax objective function of the mathematical programming
model for PAW can be easily linearized to obtain the following
ILP model.
Objective: Minimize T , subject to
1. T
is the maximum
testing time on any TAM
2.
every core is assigned to exactly
one TAM
We solved this simple ILP model to determine optimal assignments
of cores to TAMs for the SOCs introduced in Section 3. The
number of variables and constraints for this model (a measure of the
complexity of the problem) is given by NB, and N
respectively. The user time was less than a second in all cases. The
optimal assignments of cores to TAMs of given widths for SOC d695
are shown in Table 4. Note that the testing times shown are optimal
only for the given TAM widths; lower testing times can be achieved
if an optimal TAM width partition is chosen. For example, Table 5
in Section 6 shows that a testing time lower than 29451 cycles can be
achieved using two TAMs, if an optimal TAM width partition is cho-
sen. In Sections 6 and 7, we will address the problem of determining
optimal width partitions.
TAM TAM Testing time
widths assignment (clock cycles)

Table

4. Core assignment to TAMs for SOC d695.
Lower bounds on system testing time. For an SOC with N
cores and B TAMs of widths w1 ; respectively, a lower
bound on the total testing time T is given by
g. The testing time for Core i depends on the width
of the test bus to which it is assigned. Clearly, the testing time for
Core i is at least min j fT i (w j )g. Since the overall system testing
time is constrained by the core that has the largest test time, therefore
g. Intuitively, this value
is the time needed to test the core that has the largest testing time
when assigned to the widest TAM. For SOC d695 with two TAMs
of bits and 16 bits, respectively, the lower bound on the testing
time is 6215 cycles. This corresponds to the testing time needed for
Core 5 if it is assigned to TAM 1.
A lower bound on system testing time that does not depend on the
given TAM widths can further be determined. This bound is related
to the length of the longest internal scan chain of each core. The
lower bound becomes tighter as we increase the number of TAMs.
From Theorem 1, we know that for a Core i, where Core i has sc i
internal scan chains of lengths l i;1 ; l respectively, and
the test set for Core i has p i test patterns, a lower bound on the testing
time is given by (1+maxrfl i;r g)  p i +maxrfl i;r g. Therefore,
for an SOC with N cores, a lower bound on the system testing time
is given by gg. Intuitively,
this means that the system testing time is lower bounded by the time
required to test the core with the largest testing time.
6 Optimal partitioning of TAM width
In this section, we address PPAW : the problem of determining
(i) optimal widths of TAMs, and (ii) optimal assignments of cores to
TAMs, in conjunction with wrapper design. This is a generalization
of the core assignment problem PAW . We describe how testing
times computed using the Design wrapper algorithm in Section 4
are used to design the TAM architecture.
We assume that the total system TAM width can be at most W .
From Theorem 1 in Section 4, we know that the width of each TAM
need not exceed the maximum value of upper bound kmax for any
core on the SOC. We denote this upper bound on the width of an
individual TAM as wmax . For TAMs wider than wmax , there is
no further decrease in testing time. Problem PPAW of minimizing
testing time by optimal allocation of width among the TAMs can
now be stated as follows.
Given an SOC having N cores and B TAMs of total
width W , determine a partition of W among the B TAMs, an
assignment of cores to TAMs, and a wrapper design for each
core, such that the total testing time is minimized.
This problem can be shown to be NP-hard using the techniques presented
in [5]. However, for many realistic SOCs, including p93791,
the problem instance size is reasonable and can be solved exactly
using an ILP formulation. This is also because the complexity of
our solutions is related to the number of cores on the SOC and the
numbers of their I/O ports and scan chains, and not the number of
transistors or nets on the chip. A mathematical programming model
for PPAW is shown below.
Objective: Min.
subject to
1.
every core is connected to
exactly one TAM
2.
i.e., the sum of all TAM widths is
3. w j  wmax , 1  j  B, i.e., each TAM is at most wmax bits
wide
The objective function and constraints of this mathematical programming
model must now be linearized in order to express them in
the form of an ILP model that can be solved by an ILP solver. We
first express T i (w j ) as a sum: T i (w
adding new binary indicator variables - jk (where 1  j  B; 1
to the mathematical programming model, such that:
1, if TAM j is k bits wide
0, otherwise
In addition, the following constraints are included in the model:
1.
a TAM can have values of width
between 1 and wmax
2.
a TAM can have only one width
Intuitively, for every TAM j there is exactly one value of k for which
therefore, the new indicator variables determine the
width w j of each TAM. The objective function now becomes
g. The testing time T i (k) for
various values of TAM width k can be efficiently calculated using
the Design Wrapper algorithm as shown in Section 4, and stored in
the form of a look-up table for reference by the ILP solver.
Finally, the non-linear term - jk  x ij in the objective function can
be linearized by replacing it with the variable y ijk and the following
two constraints:
2.
This is explained as follows. Consider first the case when x
From Constraints 1 and 2, we have y ijk +1  - jk and 2y ijk  - jk ;
since - jk  1, therefore, y ijk must equal
The new variables and constraints yield the following ILP formulation

Objective: Minimize
subject to
2.
3.
4.
5.
6.
The number of variables and constraints for these ILP models
is given by B  (3N
respectively. We
solved the ILP model for PPAW for several values of W and B.

Table

5 and Figure 6 present the values of testing time for SOC d695
obtained with two TAMs. The total TAM width partition among the
two TAMs is shown and we also compare the testing times obtained
with the testing times obtained in [5]. The testing time using the
new wrapper design is at least an order of magnitude less than the
time required in [5] for all cases. This was to be expected since an
inefficient de-serialization model was used in [5]. The reductions in
testing time diminish with increasing W . A pragmatic choice of W
for the system might therefore be the point where the system testing
time begins to level off. In Figure 6, this occurs at
Total Results in [5] Current wrapper/TAM co-optimizaion
TAM Partition Testing Partition Testing Execution
28
36 4+32 2174501 16+20 22246 11.0
44 12+32 2123437 10+34 20094 13.0
48
reported in [5]

Table

5. Testing time for d695 for 2.
Total TAM width (bits)
28 6420406080100120140160Testing
time
(1000
clock
cycles)

Figure

6. Testing time for d695 for 2.

Table

6 presents the values of testing time obtained with three
TAMs. The testing times for are lower than the values obtained
in general. However, for W  14, the testing time
more than that for included in Table 6).
This is because for small values of W; a larger number of TAMs
makes the widths of individual TAMs very small. Once again, the
testing time begins to level off, this time at hence this is a
good choice for trading off TAM width with testing time.
Total TAM width Execution
TAM partition Core Testing time
28 4+8+16 (2,1,2,1,3,2,3,1,1,3) 24021 52.3
36 4+16+16 (2,2,2,1,2,3,2,1,2,3) 19573 85.0
44 4+18+22 (1,1,1,1,2,3,2,1,2,3) 16975
48 4+18+26 (1,1,1,1,2,3,2,1,2,3) 16975
lpsolve was halted after 180 minutes.

Table

6. Testing time for d695 obtained for 3.

Table

7 presents the system testing times for SOC p93791 obtained
using two TAMs. We halted the ILP solver after 1 hour for
each value of W and tabulated the best results obtained. This was
done to determine whether an efficient partition of TAM width and
the corresponding testing time can be obtained using the ILP model
within a reasonable execution time. In the next section, we present
the optimal testing times obtained for p93791 using a new enumerative
methodology, and show that the testing times obtained in Table
6 and Table 7 using the ILP model for PPAW are indeed either
optimal or close to optimal.
Testing
28 9+19 1119160
36 9+27 924909
Testing
44 9+35 873276
48 9+39 835526
52 9+43 807909

Table

7. Testing time for p93791 obtained with 2.
7 Enumerative TAM sizing
In Section 6, we showed that TAM optimization can be carried
out using an ILP model for the PPAW problem. However, ILP is
in itself an NP-hard problem, and execution times can get high for
large SOCs. A faster algorithm for TAM optimization that produces
optimal results in short execution times is clearly needed. In Section
5, it was observed that the execution time of the model for Problem
PAW was less than 1 second in all cases. We next demonstrate
how the short execution time of this ILP model can be exploited
to construct a series of PAW models that are solved to address the
PPAW problem.
The pseudocode for an enumerative algorithm for PPAW that explicitly
enumerates the unique partitions of W among the individual
TAMs is presented in Figure 7.
Procedure PPAW enumerate()
1. Let
2. number of TAMs
3. While all unique partitions of W have not been enumerated
4. For TAM
5. For TAM width w
(j 1)
6. Create an ILP model for PA for the TAM widths
using Design wrapper
7. Determine core assignment and testing time
8. Record the TAM design for the minimum testing time

Figure

7. Algorithm for enumerative TAM design.
The ILP models generated for each value of W in line 6 of
PPAW enumerate are solved and the TAM width partition and core
assignment delivering the best testing time are recorded. The solution
obtained using PPAW enumerate is always optimal, because
we generate all unique TAM width partitions, and then choose the
solution with the lowest cost. Since lines 6 and 7 each take less
than a second to execute, the execution time for PPAW enumerate
is at most 2  pB (W ) seconds, where pB (W ) is the number of partitions
of W among B TAMs enumerated in line 3. The problem of
determining the number of partitions pB (W ) for a given choice of
B TAMs can be addressed using partition theory in combinatorial
mathematics [15]. In [15], pB (W ) is shown to be approximately
B!(B 1)! for W 7! 1. For
W , since there are
only
W unique ways of dividing an integer W into two smaller
integers w1 and w2 . Thus PPAW enumerate obtains the optimal
solution for the PPAW problem for
than 64 seconds. For 3, the number of partitions work out
to p3(W
W (3i+1) . From the above formula, the
value of C for is found to be 341. There-
fore, the execution time of PPAW enumerate for
bounded by 682 seconds or 11.6 minutes. This execution time is
clearly reasonable, even for large W . In our experiments, we used a
Sun Ultra 80, which solved the PA models in well under a second of
execution time. The time taken for PPAW enumerate was therefore
significantly lower than the upper bound of 2  pB (W ) seconds even
for large values of W .
We used PPAW enumerate to obtain the optimal TAM width assignment
and minimal testing time for
d695 and p93791. Results for SOC d695 are presented in Table 8.
While the testing time for 3 is always less than the testing time
the difference between
widens for larger W . This can be explained as follows. For smaller
values of W , each individual TAM for
the testing time on each individual TAM increases sharply, as was
observed earlier in Figure 3.
Exec. Exec.
time
28
44 10+34 20094 2 4+18+22 16975
48

Table

8. Results for SOC d695 using PPAW enumerate.

Table

9 presents optimal results for enumerative TAM optimization
for the p93791 SOC. Comparing these results with those presented
in Table 7, we note that the results in Table 7 are indeed close
to optimal. For example, for the testing time presented in

Table

7 is only 5% higher than optimal. Note that for both SOCs,
the execution time for PAW is under 1 second. Hence similar execution
times for PPAW enumerate are obtained for SOCs d695 and
p93791. These execution times are significantly lower than those in

Tables

5 and 6.
Exec. Exec.
time
28 5+23 1031200 1 2+3+23 1030920 13
44 21+23 711256 2 5+16+23 659856 33
48 23+25 634488 2 9+16+23 602613 42

Table

9. Results for SOC p93791 using PPAW enumerate.
We compared the optimal testing times presented in Tables 8
and 9 with the testing times obtained using an equal partition of
W among the B TAMs. The testing time using an optimal partition
of W was significantly lower than that obtained using an equal
partition for all values of W . For example, for
a partition of (w1 ; testing time of
clock cycles, which is an increase of 28.6% over the testing
time of 475598 clock cycles obtained using an optimal partition of
The execution time of PPAW enumerate is smaller than that of
the ILP model in Section 6 because the number of enumerations for
two and three TAMs is reasonable. However, when TAM optimization
is carried out for a larger number of TAMs that have a larger
number of partitions of W , the ILP model for PPAW is likely to be
more efficient in terms of execution time. In addition, the ILP model
presented in Section 6 is likely to be more efficient when constraints
arising from place-and-route and power issues are included in TAM
optimization [4].
8 General problem of wrapper/TAM co-
optimization
In the previous sections, we presented a series of problems in test
wrapper and TAM design, each of which was a generalized version
of the problem preceding it. In this section, we present PNPAW , the
more general problem of wrapper/TAM optimization that the problems
of the preceding sections lead up to. We also show how solutions
to the previous problems can be used to formulate a solution
for this general problem.
The general problem can be stated as follows.
Given an SOC having N cores and a total TAM
width W , determine the number of TAMs, a partition of W
among the TAMs, an assignment of cores to TAMs, and a
wrapper design for each core, such that the total testing time is
minimized.
We use the method of restriction to prove that PNPAW is NP-
hard. We first define a new Problem PNPAW 1
, which consists of
only those instances of PNPAW for which (i)
cores on the SOC have a single internal scan chain and no functional
terminals. Hence, each core will have the same testing time on a
1-bit TAM as on a 2-bit TAM. An optimal solution to PNPAW 1
will
therefore always result in two TAMs of width one bit each. Problem
reduces to that of partitioning the set C of cores on
the SOC into two subsets C1 and C C1 , such that each subset
is assigned to a separate 1-bit TAM, and the difference between the
sum of the testing times of the cores (on the first 1-bit TAM) and
the sum of the testing times of the cores (on the 2nd 1-bit TAM) is
minimized. Formally, the optimization cost function for PNPAW 1
can be written as:
Objective: Minimize
is the testing
time of core c on a 1-bit TAM.
Next, consider the Partition problem [7], whose optimization
variant can be stated as follows.
Partition: Given a finite set A and a size s(a) 2 Z + for each
element a 2 A, determine a partition of A into two subsets A1
and A A1 , such that
s(a)
s(a) is minimized.
That Problem PNPAW 1
is equivalent to Partition can be established
by the following four mappings: (i) C  A, (ii) C1  A1 ,
s(a). Since Partition is
known to be NP-hard [7], PNPAW 1
and PNPAW must also be
NP-hard.
To solve PNPAW , we enumerate solutions for PPAW over several
values of B. For each value of W , the optimal number of TAMs,
TAM width partition, core assignment, and wrapper designs for the
cores are obtained. The solutions to PPAW for d695 for values of
B ranging from 2 to 8 are illustrated in Figures 8 (a) and 8 (b) for
W values of 12, and 16 bits, respectively. In each Figure, we observe
that as B is increased from 2, the testing time decreases until a
minimum value is reached at a particular value of B, after which the
testing time stops decreasing and starts increasing as B is increased
further. This is because for larger B, the width per TAM is small
and testing time on each TAM increases significantly.
Number of TAMs
Testing
time
(1000
clock
cycles)
Number of TAMs
842.547.552.557.5Testing
time
(1000
clock
cycles)
(a)

Figure

8. Testing time for d695 obtained with increasing
values of B.
We next present a conjecture that formalizes the observation
made in Figures 8(a) and 8(b).
Conjecture 1 Let T (S; W;B) denote the optimal testing time for
and a total TAM width of W . If
We conjecture that during the execution of PNPAW enumerate, if
at a certain value of B, the testing time is greater than or equal to the
testing time at the previous value of B for the same total TAM width
W , then the enumeration procedure can be halted and the optimal
value of B recorded. Therefore, Conjecture 1 can be used to prune
the search space for the optimal wrapper/TAM design. Since the
execution time of PNPAW enumerate is particularly high for large
values of B, we can achieve significant speed-ups in TAM optimization
by halting the enumeration as soon as the minimum value of T
is reached.
Based on Conjecture 1, we executed PNPAW enumerate for several
values of W . In Table 10, we present the best testing times
obtained for d695 for the values of W . For each value of W , the
number of TAMs, width partition, testing time, and core assignment
providing the minimum testing time is shown.
TAM Optimum Optimal Optimal Optimum
width number width core testing
W of TAMs partition asignment time
28 5 1+2+8+8+9 (4,2,4,2,3,5,4,1,5,4) 24197

Table

results obtained
for d695 for several values of W .
9 Conclusion
We have investigated the problem of test wrapper/TAM co-optimization
for SOCs, based on the test bus model of TAM design.
In particular, we have formally defined the problem of determining
the number of TAMs, a partition of the total TAM width among the
TAMs, an assignment of cores to TAMs, and a wrapper design for
each core, such that SOC testing time is minimized. To address
this problem, we have formulated three incremental problems in test
wrapper and TAM optimization that serve as stepping-stones to the
more general problem stated above. We have proposed an efficient
heuristic algorithm based on BFD for the wrapper design problem
PW that minimizes testing time and TAM width. For PAW , the
problem of determining core assignments and wrapper designs, we
have formulated an ILP model that results in optimal solutions in
short execution times. We have formulated an ILP model to solve
PPAW , the problem of TAM width partioning that PAW leads up
to. This ILP model was solved to obtain optimal TAM designs
for reasonably-sized problem instances. We have also presented a
new enumerative approach for PPAW that offers significant reductions
in the execution time. Finally, we have defined a new wrap-
per/TAM design problem, PNPAW , in which the number of TAMs
to be designed must be determined. PNPAW is the final step in
our progression of incremental wrapper/TAM design problems, and
it includes PW , PAW and PPAW . An enumerative algorithm to
solve PNPAW has been proposed, in which the search space can
be pruned significantly when no further improvement to testing time
would result.
We have applied our TAM optimization models to a realistic example
SOC as well as to an industrial SOC; the experimental results
demonstrate the feasibility of the proposed techniques. To the
best of our knowledge, this is the first reported attempt at integrated
wrapper/TAM co-optimization that has been applied to an industrial
SOC.
In future work, we intend to extend our TAM optimization models
to include several other TAM configurations, including daisy-chained
cores on TAMs [1] and "forked and merged" TAMs [5].
We intend to extend our models, such that multiple wrappers on the
same TAM are active in the test data transfer mode at the same time;
this will allow us to address the problems of both testing hierarchical
cores, as well as Extest. While ILP is a useful optimization
tool for reasonably-sized problem instances, execution times can increase
significantly for complex SOCs and large values of B. This
is also true of our enumerative approach to Problems PPAW and
PNPAW . We are in the process of designing heuristic algorithms
for each of the problems formulated in this paper that can efficiently
address wrapper/TAM co-optimization for large TAM widths as well
as large numbers of TAMs. Furthermore, we plan to add constraints
related to power dissipation, routing complexity and layout area to
our TAM optimization models.

Acknowledgements

The authors thank Harry van Herten and Erwin Waterlander for
their help with providing data for the Philips SOC p93791, Henk
Hollmann and Wil Schilders for their help with partition theory, and
Jan Korst for his help with the NP-hardness proof for PNPAW . We
also thank Sandeep Koranne and Harald Vranken for their constructive
review comments on earlier versions of this paper.



--R

Scan chain design for test time reduction in core-based ICs
lpsolve 3.0
Design of system-on-a-chip test access architectures using integer linear programming
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Optimal test access architectures for system-on-a- chip

Computers and Intractability: A Guide to the Theory of NP-Completeness
A fast and low cost testing technique for core-based system-on-chip
Testing re-usable IP: A case study
IEEE P1500 Standard for Embedded Core Test.
Direct access test scheme - Design of block and core cells for embedded ASICs

Test wrapper and test access mechanism co-optimization for system-on-chip
An integrated system-on-chip test framework
A course in combinatorics
A structured and scalable mechanism for test access to embedded reusable cores.
Wrapper design for embedded core test.
On using IEEE P1500 SECT for test plug-n-play
An ILP formulation to optimize test access mechanism in system-on-chip testing
Using partial isolation rings to test core-based designs
A structured test re-use methodology for core-based system chips
Model Building in Mathematical Programming.
Testing embedded-core-based system chips
--TR

--CTR
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embedded core testing;testing time;integer linear programming;test access mechanism TAM;test wrapper