Effects of delay models on peak power estimation of VLSI sequential circuits.
Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. However, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulation is expensive. Thus, we would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays. Results for four delay models are reported for the ISCAS85 combinational benchmark circuits, ISCAS89 sequential benchmark circuits, and several synthesized circuits.
Introduction
The continuing decrease in feature size and increase in chip
density in recent years give rise to concerns about excessive
power dissipation in VLSI chips. As pointed out in [1], large
instantaneous power dissipation can cause overheating (lo-
cal hot spots), and the failure rate for components roughly
doubles for every increase in operating temperature.
Knowledge of peak power dissipation can help to determine
the thermal and electrical limits of a design.
The power dissipated in CMOS logic circuits is a complex
function of the gate delays, clock frequency, process param-
eters, circuit topology and structure, and the input vectors
applied. Once the processing and structural parameters have
been fixed, the measure of power dissipation is dominated by
the switching activity (toggle counts) of the circuit. It has
been shown in [2] and [3] that, due to uneven circuit delay
paths, multiple switching events at internal nodes can result,
and power estimation can be extremely sensitive to different
gate delays. Both [2] and [3] computed the upper bound of
maximum transition (or switching) density of individual internal
nodes of a combinational circuit via propagation of
uncertainty waveforms across the circuit. However, these
measures cannot be used to compute a tight upper bound of
the overall power dissipation of the entire circuit.
Although maximum switching density of a given internal
node can be extremely sensitive to the delay model used,
it is unclear whether peak power dissipation of the entire
circuit is also equally sensitive to the delay model. Since
This research was conducted at the University of Illinois and
was supported in part by the Semiconductor Research Corporation
under contract SRC 96-DP-109, in part by DARPA under contract
DABT63-95-C-0069, and by Hewlett-Packard under an equipment
grant.
glitches and hazards are not taken into account in a zero-delay
framework, the power dissipation measures from the
zero-delay model may differ greatly from the actual powers.
Will the peak power be vastly different among various non-zero
delay models (where glitches and hazards are accounted
for) in sequential circuits? Moreover, the delays used for
internal gates in most simulators are mere estimates of the
actual gate delays. Can we still have confidence in the peak
power estimated using these delay measures considering that
the actual delays for the gates in the circuit may be different?
Since computing the exact gate delays for every gate in the
circuit during simulation is expensive, does there exist a simple
delay model such that the execution time for estimating
power is reduced and an accurate peak power estimate can
be obtained (i.e., the peak powers estimated will not vary
due to a variation in the gate delays)?
Several approaches to measuring maximum power in
CMOS VLSI circuits have been reported [4-10]. Unlike average
power estimations [11-17], where signal switching probabilities
are sufficient to compute the average power, peak
power is associated with a specific starting circuit state S and
a specific sequence of vectors Seq that produce the power.
Two issues are addressed in this paper. First, given a (S i ,
that generates peak power under delay model
DM i , is it possible to obtain another tuple (S
generates equal or higher dissipation under a different delay
model DM j ? Second, will the (S i ,
peak power under delay model DM i also produce near peak
power under a different delay model DM j ?
Four different delay models are studied in this work: zero
delay, unit delay, type-1 variable delay, and type-2
variable delay. The three delay models used in [9] are
the same as the first three delay models of this work. Measures
of peak power dissipation are estimated for all four
delay models over various time periods. Genetic algorithms
(GA's) are chosen as the optimization tool for this problem
as in [10]. GA's are used to find the vector sequences which
most accurately estimate the peak power under various delay
models as well as over various time durations. The estimates
obtained for each delay model are compared with the estimates
from randomly-generated sequences, and the results
for combinational circuits are compared with the automatic
test generation (ATG) based technique [9] as well. The GA-based
estimates will be shown to achieve much higher peak
power dissipation in short execution times when compared
with the random simulation.
The remainder of the paper is organized as follows. Section
2 explains the delay models, and Section 3 discusses the
peak power measures over various time periods. The GA
framework for power estimation is described in Section 4.
Experimental results on the effects of various delay models
are discussed in Section 5, and Section 6 concludes the paper.
Delay Models
Zero delay, unit delay, and two types of variable delay
models are studied here. The zero delay model assumes that
no delay is associated with any gate; no glitches or hazards
will occur under this model. The unit delay model assigns
identical delays to every gate in the circuit independent of
gate size and numbers of fanins and fanouts. The type-1
variable delay model assigns the delay of a given gate to be
proportional to the number of fanouts at the output of the
gate. This model is more accurate than the unit delay model;
however, fanouts that feed bigger gates are not taken into ac-
count, and inaccuracies may result. The fourth model is a
different variable delay model which is based on the number
of fanouts as well as the sizes of successor gates. The gate
delay data for various types and sizes of gates are obtained
from a VLSI library. The difference between the type-1 and
variable delay models for a typical gate is illustrated
in

Figure

1. From the figure, the output capacitance of gate
Type 1 variable:
G3
Delay for gate G1 is 2 units.
Delay for driving 2-input
Type 2 variable:
Delay for G1 is
Delay for driving 4-input units.

Figure

1: Variable Delay Models.
G1 is estimated to be 2 (the number of fanouts) in the type-
delay model, while the delay calculated using the
variable delay model is proportional to the delay associated
with driving the successor gates G2 and G3, or
simply 3. Since the type-1 variable delay model
does not consider the size of the succeeding gates, the delay
calculations may be less accurate.
3 Peak Power Measures
Three types of peak power are used in the context of sequential
circuits for comparing the effects of delay models.
An automatic procedure was implemented for various delay
models that obtains these measures and generates the actual
input vectors that attain them, as described in [10]. They
are Peak Single-Cycle Power, Peak n-Cycle Power, and Peak
Sustainable Power, covering time durations of one clock cy-
cle, several consecutive clock cycles, and an infinite number
of cycles, respectively. The unit of power used throughout
the paper is energy per clock cycle and will simply be referred
to as power. In a typical sequential circuit, the switching
activity is largely controlled by the state vectors and less influenced
by input vectors, because the number of flip-flops
far outweighs the number of primary inputs. In all three
cases, the power dissipated in the combinational portion of
the sequential circuit can be computed as
dd
2 \Theta cycle period \Theta
for all gates g
[toggles(g) \Theta C(g)];
where the summation is performed over all gates g, and
toggles(g) is the number of times gate g has switched from 0
to 1 or vice versa within a given clock cycle; C(g) represents
the output capacitance of gate g. In this work, we made
the assumption that the output capacitance for each gate
is equal to the number of fanouts for all four delay models;
however, assigned gate output capacitances can be handled
by our optimization technique as well.
Peak single-cycle switching activity generally occurs when
the greatest number of capacitive nodes are toggled between
two consecutive vectors. For combinational circuits, the task
is to search for a pair of vectors (V1 , V2 ) that generates the
most gate transitions. For sequential circuits, on the other
hand, the activity depends on the initial state as well as the
primary input vectors. The estimate for peak power dissipation
can be used as a lower-bound for worst-case power
dissipation in the circuit in any given time frame. Our goal
in this work is to find and compare such bounds for the peak
power dissipation of a circuit under different delay assumptions

Peak n-cycle switching activity is a measure of the peak
average power dissipation over a contiguous sequence of n
vectors. This measure serves as an upper-bound to peak
sustainable power, which is a measure of the peak average
power that can be sustained indefinitely. Both measures are
considered only for sequential circuits. The n-cycle power
dissipation varies with the sequence length n. When n is
equal to 2, the power dissipation is the same as the peak
single-cycle power dissipation, and as n increases, the average
power is expected to decrease if the peak single-cycle
power dissipation cannot be sustained over the n vectors in
the sequence.
We computed peak sustainable power by finding the synchronizing
sequence for the circuit that produces greatest
power [10]. Unlike the approach proposed in [7], where symbolic
transition counts based on binary decision diagrams
(BDD's) were used to compute maximum power cycles, no
state transition diagrams are needed in our approach. Ba-
sically, the method used in [7] was to find the maximal average
length cycle in the state transition graph, where the
edge weights in the STG indicate the power dissipation in
the combinational portion of the circuit between two adjacent
states. However, the huge sizes of STG's and BDD's
in large circuits make the approach infeasible and impracti-
cal. Our approach restricts the search for peak power loops
to be a synchronizing sequence, thereby limiting the search
to a subset of all loops, and the resulting peak power may
not be a very tight lower bound. However, our experiments
have shown that this approach still yields peaks higher than
extensive random search [10].
4 GA Framework for Power Estimation
The GA framework used in this work is similar to the simple
GA described by Goldberg [18]. The GA contains a population
of strings, also called chromosomes or individuals, in
which each individual represents a sequence of vectors. Peak
n-cycle power estimation requires a search for the (n
tuple (S1 , V1 , ., Vn+1) that maximizes power dissipation.
This (n + 2)-tuple is encoded as a single binary string, as
illustrated in Figure 2. The population size used is a function
of the string length, which depends on the number of
primary inputs, the number of flip-flops, and the vector sequence
length n. Larger populations are needed to accommodate
longer vector sequences in order to maintain diversity.
Figure

2: Encoding of an Individual.
The population size is set equal to 32 \Theta
sequence length
when the number of primary inputs is less than 16 and
128 \Theta
sequence length when the number of primary inputs
is greater than or equal to 16. Each individual has an
associated fitness, which measures the quality of the vector
sequence in terms of switching activity, indicated by the total
number of capacitive nodes toggled by the individual. The
delay model and the amount of capacitive-node switching
are taken into account during the evolutionary processes of
the GA via the fitness function. The fitness function is a
simple counting function that measures the power dissipated
in terms of amount of capacitive-node switching in a given
time period.
The population is first initialized with random strings. A
variable-delay logic simulator is then used to compute the
fitness of each individual. The evolutionary processes of se-
lection, crossover, and mutation are used to generate an entirely
new population from the existing population. This
process continues for 32 generations, and the best individual
in any generation is chosen as the solution. We use tournament
selection without replacement and uniform crossover,
and mutation is done by simply flipping a bit. In tournament
selection without replacement, two individuals are randomly
chosen and removed from the population, and the
best is selected; the two individuals are not replaced into
the original population until all other individuals have also
been removed. Thus, it takes two passes through the parent
population to completely fill the new population. In uniform
crossover, bits from the two parents are swapped with
probability 0.5 at each string position in generating the two
offspring. A crossover probability of 1 is used; i.e., the two
parents are always crossed in generating the two offspring.
Since the majority of time spent by the GA is in the fitness
evaluation, parallelism among the individuals can be
exploited. Parallel-pattern simulation [19] is used to speed
up the process in which candidate sequences from the population
are simulated simultaneously, with values bit-packed
into 32-bit words.
5 Experimental Results
Peak powers for four different delay models were estimated
for ISCAS85 combinational benchmark circuits, ISCAS89 sequential
benchmark circuits, and several synthesized circuits.
Functions of the synthesized circuits are as follows: am2910
is a 12-bit microprogram sequencer [20]; mult16 is a 16-bit
two's complement shift-and-add multiplier; div16 is a 16-bit
divider using repeated subtraction; and proc16 is a 16-bit
microprocessor with 373 flip-flops. Table 1 lists the total
number of gates and capacitive nodes for all circuits. The
total number of capacitive nodes in a circuit is computed
as the total number of gate inputs. All computations were
performed on an HP 9000 J200 with 256 MB RAM.
The GA-based power estimates are compared against the
best estimates obtained from randomly generated vector se-
quences, and the powers are expressed in peak switching
frequency per node (PSF), which is the average frequency
of peak switching activity of the nodes (ratio of the

Table

1: Numbers of Capacitive Nodes in Circuits
Circuit Gates Cap Circuit Gates Cap
Nodes Nodes
c7552 3828 6252 s5378 3043 4440
s526 224 472
number of transitions on all nodes to the total number of
capacitive nodes) in the circuit. Notice that for the non-zero
delay models, PSF's greater than 1.0 are possible due
to repeated switching on the internal nodes within one clock
cycle.
We have previously shown that estimates made by our
GA-based technique are indeed good estimates of peak
power, and that if random-based methods were to achieve
similar levels of peak power estimates, execution times are
several orders of magnitude higher than for the GA-based
technique [10]. Peak power estimation results will now be
presented for the various delay models, and correlations between
the delay models will be discussed.
5.1 Effects of the four delay models
For the ISCAS85 combinational circuits, Table 2 compares
the GA-based results against the randomly-generated
sequences as well as those reported in [9]. For each circuit,
results for all four delay models are reported. The estimates
obtained from the best of randomly-generated vector-pairs,
an ATG-based approach [9], and the GA-based technique are
shown. The ATG-based approach used in [9] attempts to optimize
the total number of nodes switching in the expanded
combinational circuit; its results were compared against the
best of only 10,000 random simulations. In our work, on
the other hand, the number of random simulations depends
on the GA population size, which is a function of the number
of primary inputs in the circuit. Typically, the number
of random simulations exceeds 64,000. The GA-based estimates
are the highest for all of the circuits and for all delay
models, except for one zero-delay estimate in c1355, where
a 1.1% lower power was obtained. The average improvements
made by the GA-based technique over the random
simulations are 10.8%, 27.4%, 38.5%, and 35.5%, for the
four delay models, respectively. Since [9] estimated power
on the expanded circuits, backtrace using zero-delay techniques
was used. Consequently, only hazards were captured;
zero-width pulses were not taken into account in the non-zero
delay models. For this reason, our GA-based estimates are
higher than all the estimates obtained in [9]. Furthermore,
results from [9] suggested that peak power estimated from
the unit-delay model consistently gave higher values than
both zero-delay and type-1 variable-delay estimates. We do
not see such consistency from our results in Table 2. The estimated
powers from random simulations do not show such
a trend either. Nevertheless, it is observed that peak powers

Table

2: Peak Single-Cycle Power for ISCAS85 Combinational Circuits
Circuit Zero Unit Type-1 Variable Type-2 Variable
Rnd [9] GA Rnd [9] GA Rnd [9] GA Rnd [9] GA
c432 0.636 0.536 0.805 1.985 1.985 2.362 2.557 1.181 3.399 2.286 - 2.522
Impr 10.8% 27.4% 38.5% 35.5%
Impr: Average improvements over the best random estimates
for some circuits are very sensitive to the underlying delay
model. For instance, in circuit c3540, the peak power estimates
are 0.600, 2.684, 3.555, and 4.678 for zero, unit, type-1
variable, and type-2 variable delay models.
The results for sequential circuits using the four delay
models are shown in Table 3. The length of the sequence
in each case is set to 10 for N-cycle and sustainable power
estimates. Results for best of the random simulations are
not shown; however, the average improvements made by the
GA-based estimates are shown at the bottom of the table.
The number of random simulations is also the same as the
number of simulations required in the GA-based technique.
For the small circuits, the number of simulations is around
64,000. The GA-based estimates surpass the best random
estimates for all circuits for all three peak power measures
under all four delay models. The average improvements of
the GA-based estimates for each delay model are shown in
the bottom row of Table 3. Up to 32.5% improvement is
obtained on the average for peak N-cycle powers.
Across the four delay models, estimates made from the
zero-delay model consistently gave significantly lower power,
since glitches and hazards were not accounted for. However,
there is not a clear trend as to which of the other three delay
models will consistently give peak or near peak power esti-
mates. In circuits such as s641, s713, and am2910, the peak
powers are very sensitive to the delay model. Over 100% increase
in power dissipation can result when a different delay
model is used. For some other circuits, such as s400, s444,
s526, and s1238, the peak powers estimated are quite insensitive
to the underlying delay model; less than 5% difference
in the estimates is observed from the three delay models.
The execution times needed for the zero-delay estimates
are typically smaller, since few events need to be evaluated,
while execution times for the other three delay models are
comparable. Table 4 shows the execution times for the GA
optimization technique for the unit-delay model. The execution
times are directly proportional to the number of events
generated in the circuit during the course of estimation. For
this reason, peak n-cycle power estimates do not take 10
times as much computation as peak single-cycle power for
since the amount of activity across the 10 cycles is
not 10 times that of the peak single cycle. For circuits in
which peak power estimates differ significantly among various
delay models, the computation costs will also differ significantly
according to the number of activated events. The
execution times required for the random simulations are very
close to the GA-based technique since identical numbers of
simulations are performed.
5.2 Cross-effects of delay models
Although peak powers are sensitive to the underlying delay
model, it would be interesting to study if the vectors
optimized under one delay model will produce peak or near-peak
power under the other delay models. If we can find a
delay model in which derived sequences consistently generate
near peak powers under the other delay models, we can
conclude that, although peak power estimation is sensitive
to the underlying delay model, there exists a delay model by
which optimized sequences generate high powers regardless
of the delay model used.
Experiments were therefore carried out to study these
cross-effects of delay models. Table 5 shows the results for
the combinational circuits. For each circuit, the previously
optimized peak power measures for various delay models (the
same as those in Table 2) are shown in the Opt columns.
The power produced from applying vectors optimized for a
given delay model on the other three delay models are listed
in the adjacent (Eff) columns. For example, in circuit c2670
under the zero-delay model (upper-left quadrant of the ta-
ble), the original peak single-cycle switching frequency per
node (PSF) for the unit-delay model was 2.251 (Opt); how-
ever, when vectors optimized for the zero-delay model are
simulated using the unit-delay model, the measured PSF is
1.150 (Eff). The Eff measures that exceed the optimized
(Opt) measures are italicized. At the bottom of the table,
Dev shows the average amount that the Eff values deviated
from the average Opt values. For instance, when the optimized
vectors on the unit-delay model are simulated using
the zero-delay assumption, an average deviation of 18.9%
results from the GA-optimized zero-delay powers. On the
average, the Eff peak powers deviated from the optimized
values for all delay models as indicated by the Dev values.
However, the vectors optimized for the zero-delay model produced
significantly lower power when they were simulated in
the non-zero delay environments; over 60% drops were observed
from the GA-optimized powers, as indicated by the
Dev metric. The vectors that were optimized on the remaining
three delay models, on the other hand, deviated
less significantly when simulated using other non-zero delay
models, all less than 10% deviations.
For sequential circuits, we will first look at the vectors optimized
under the zero-delay assumption. Table 6 shows the
results. The Opt and Eff values are defined the same way
as before. For example, in circuit s382, the peak single-cycle
switching frequency per node (PSF) under unit delay was
however, when the vector sequence optimized for the
zero-delay model is simulated using the unit-delay model, the

Table

3: GA-Based Power Estimates for ISCAS89 Sequential Circuits
Circuit Single Cycle N-Cycle Sustainable
Z U V1 V2 Z U V1 V2 Z U V1 V2
Impr 11.9% 12.3% 20.4% 22.3% 17.4% 32.5% 26.7% 32.0% 12.3% 23.8% 24.4% 30.2%
Z: Zero U: Unit V1: Type-1 Variable V2: Type-2 Variable
Impr: Average improvements over the best random estimates

Table

4: Execution Times for the GA-Based Technique (seconds)
Circuit Single N- Sustain Circuit Single N- Sustain Circuit Single N- Sustain
cycle cycle able cycle cycle able cycle cycle able
measured PSF is 0.952. A similar format is used for the n-cycle
and sustainable powers. Average deviation values Dev
are also displayed at the bottom of the table. On average,
the Eff peak powers deviated significantly from the powers
optimized by the GA for both unit and type-1 variable delay
models, as indicated in the Dev row. When examining
the results for each circuit individually, none of the single-cycle
vectors derived under the zero-delay model exceed the
previously optimized peak powers for unit and type-1 variable
delay models. However, several occasions of slightly
higher peak n-cycle and sustainable powers have been obtained
by the zero-delay-optimized vectors because of the
difficulty in finding the optimum in the huge search space
for the (n+2)-tuple needed for the peak n-cycle and sustainable
powers. Nevertheless, the number of these occasions is
quite small. For the small circuits s298 to s526, the results
show that the zero-delay-optimized vectors produced peak or
near-peak powers for the unit and type-1 variable delay models
as well. One plausible explanation for this phenomenon
is that the peak switching frequencies (PSF's) for these circuits
are small, typically less than 1.2, indicating that most
nodes in the circuit do not toggle multiple times in a single
clock cycle. For the other circuits, especially for circuits
where high PSF's are obtained, the vectors obtained which
generated high peak powers under zero-delay assumptions do
not provide peak powers under non-zero delay assumptions.
The last four synthesized circuits, am2910, mult16, div16,
and proc16, showed widened gaps. The effects on type-2
variable delay are similar to those on type-1 variable delay.
Similarly, vectors optimized under the non-zero-delay
models were simulated using other delay models, and the
results are shown in Table 7 for type-2 variable delay. The
trends for the unit-delay and type-1 variable delay models
are similar to those seen for the type-2 variable delay model.
The results are not compared with the zero-delay model here,
since their trends are similar to those for the combinational
circuits, where large deviations exist. When the optimized
powers are great, i.e., PSF's are greater than 2, a greater deviation
is observed. Such cases can be seen in circuits s641,
s713, am2910, and div16. For instance, the optimized peak
single-cycle unit-delay power for s713 is 2.815, but the power
produced by applying the vectors optimized for the type-2
variable delay model is only 1.273. On the contrary, less
significant deviation is observed in circuits for which smaller
PSF's are obtained. For the n-cycle and sustainable pow-
ers, although deviations still exist when compared with the
GA-optimized vectors (shown in Dev), they are small devi-
ations. Furthermore, deviations between type-1 and type-2
delay models are smaller when compared with the unit-delay
model, suggesting that the two variable delay models are
more correlated.
6 Conclusions
When estimating peak power under one delay model, it
is crucial to have confidence that the estimate will not vary
significantly when the actual delays in the circuit differ from

Table

5: Effects of Various Delay Models for ISCAS85 Combinational Circuits
Effects of Zero-delay Vectors On. Effects of Unit-delay Vectors On.
Circuit Unit Type-1 Var Type-2 Var Zero Type-1 Var Type-2 Var
Opt Eff Opt Eff Opt Eff Opt Eff Opt Eff Opt Eff
c432 2.362 2.035 3.399 2.181 2.522 2.192 0.636 0.455 3.399 2.904 2.522 3.032
c1355 3.260 1.000 2.707 1.011 2.676 1.042 0.533 0.441 2.707 2.391 2.676 3.143
c2670 2.251 1.150 2.750 1.294 2.825 1.320 0.623 0.572 2.750 2.364 2.825 2.355
c7552 2.821 1.619 2.833 1.757 3.238 1.788 0.602 0.537 2.833 3.089 3.238 3.012
Effects of Type-1 Var-delay Vectors On. Effects of Type-2 Var-delay Vectors On.
Circuit Zero Unit Type-2 Var Zero Unit Type-1 Var
Opt Eff Opt Eff Opt Eff Opt Eff Opt Eff Opt Eff
c432 0.636 0.496 2.362 2.373 2.522 3.399 0.636 0.411 2.362 1.776 3.399 2.155
Dev: Average deviation of Eff from Opt.
the delay model assumed. Peak power estimation under four
different delay models for single-cycle, n-cycle, and sustainable
power dissipation has been presented. For most circuits,
vector sequences optimized under the zero-delay assumption
do not produce peak or near-peak powers when they are simulated
under a non-zero delay model. Similarly, the vectors
optimized under non-zero delay models do not produce peak
or near-peak zero-delay powers. However, vector sequences
optimized under non-zero delay models provide good measures
for other non-zero delay models, with only a slight
deviation, for most combinational circuits. For sequential
circuits, small deviations are observed when the optimized
peak powers are small, but when the optimized peak powers
are large, i.e., nodes switch multiple times in a single cycle
on the average, the estimated peak powers will be sensitive
to the underlying delay model.



--R

"Shrinking devices put the squeeze on system packag- ing,"
"Extreme delay sensitivity and the worst-case switching activity in VLSI circuits,"
"Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits,"
"Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation,"
"Worst case voltage drops in power and ground busses of CMOS VLSI circuits,"
"Resolving signal correlations for estimating maximum currents in CMOS combinational circuits,"
"Computing the maximum power cycles of a sequential circuit,"
"Maximum power estimation for sequential circuits using a test generation based technique,"
"Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model,"
"K2: An estimator for peak sustainable power of VLSI circuits,"
"Estimation of average switching activity in combinational and sequential circuits,"
"A survey of power estimation techniques in VLSI circuits,"
"Statistical estimation of sequential circuit activity,"
"Accurate power estimation of CMOS sequential circuits,"
"Switching activity analysis using boolean approximation method,"
"Power estimation methods for sequential logic circuits,"
"Power estimation in sequential circuits,"
Genetic Algorithms in Search
Digital Systems Testing and Testable Design.
"The AM2910, a complete 12-bit microprogram sequence controller,"
--TR
Estimation of average switching activity in combinational and sequential circuits
Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
Worst case voltage drops in power and ground buses of CMOS VLSI circuits
A survey of power estimation techniques in VLSI circuits
Power estimation methods for sequential logic circuits
Computing the maximum power cycles of a sequential circuit
Extreme delay sensitivity and the worst-case switching activity in VLSI circuits
Power estimation in sequential circuits
Switching activity analysis using Boolean approximation method
Statistical estimation of sequential circuit activity
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits
Accurate power estimation of CMOS sequential circuits
K2
Genetic Algorithms in Search, Optimization and Machine Learning
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

--CTR
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n-cycle power;sustainable power;variable delay;peak power;genetic optimization