Analytical delay models for VLSI interconnects under ramp input.
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However, for typical RLC interconnections with ramp input, Elmore delay can deviate by up to 100% or more from SPICE-computed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4% of SPICE-computed delay, and models based on both first and second moments are within 2.3% of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of source-sink delays in arbitrary interconnect trees.
Introduction
Accurate calculation of propagation delay in VLSI interconnects is critical
to the design of high speed systems, and transmission line effects
now play an important role in determining interconnect delays and system
performance. Existing techniques are basedon either simulation or
analytical formulas. Simulation methods such as SPICE
give the most accurate insight into arbitrary interconnect structures, but
are computationally expensive. Faster methodsbasedonmoment matching
techniques are proposed in [12, 13, 14, 17], but are still too expensive
to be used during layout optimization. Thus, Elmore delay [2], a
first order approximation of delay under step input, is still the most widely
used delay model in the performance-driven synthesis of clock distribution
and Steiner global routing topologies. However, Elmore delay
cannot be applied to estimate the delay for interconnect lines with ramp
input source; this inaccuracy is harmful to current performance-driven
routing methods which try to determine optimal interconnect segment
lengths and widths (as well as driver sizes). Previous moment-based
approaches [12, 14, 17] can compute a response for interconnects under
ramp input within a simulation-based methodology, but no previous
work has given analytical delay estimation modelsbasedon the first few
moments.
Recently, [3] presented lower and upper bounds for the ramp input
their delay model is the same as the Elmore model for ramp
input (we refer to this model as analytical ramp input model (T AD ) in
this paper). Delay estimates for the analytical ramp input model are off
by as much as 50% from SPICE-computed delays for 50% threshold
voltage, and the analytical ramp input model cannot be used to obtain
threshold delay for various threshold voltages. The authors of [5] used
Elmore delay as an upper bound on the 50% threshold delay for RC interconnection
lines under arbitrary input waveforms. However, we find
that Elmore delay is not at all close to SPICE-computed 50% threshold
delay and, depending on the input slew time and driver resistance,
can be either greater or less than SPICE-computed delay (see Section 7
below). This paper gives a new and accurate analytical delay estimate
for distributed RLC interconnects under ramp input. To experimentally
validate our analysis and delay formula, we model VLSI interconnect
lines having various combinations of source, and load parameters, ap-
Principal author, to whom correspondence should be addressed: Sudhakar Muddu
(muddu@mti.sgi.com). Andrew B. Kahng is currently on Sabbatical leave at Cadence Design
Systems, ak@cadence.com.
ply different input rise times, and obtain delay estimates from SPICE,
Elmore delay and the proposed analytical delay model. Over our range
of test cases, Elmore delay estimates can vary by as much as 100% from
SPICE-computed delays. As the input rise time increases, Elmore delay
deviates even further from SPICE-computed delays. In contrast, our
single-pole delay estimates are within 4% of SPICE delays and our two-pole
delay estimates are within 2:3% of SPICE delays. 1 Since our analytical
models have the same time complexity of evaluation as the Elmore
model, we believe that they are very useful for performance-driven
routing methodologies.
The organization of our paper is as follows. In Section 2 we discuss
delay models which have been previously proposed for interconnect
lines under step input. Section 3 presents a new analytical delay
definition for interconnect lines under ramp input. Section 4 discusses
various threshold delay models for single-pole approximation of the interconnect
transfer function; Section 5 gives various threshold delay models
for two-pole approximation; and Section 6 extends our delay modeling
approach to interconnection trees. Section 7 concludes with experimental
results for various combinations of input rise times and interconnect
parameters.
Previous Delay Models Under Step Input
The transfer function of an RLC interconnect line with source and load
impedance (Figure 1) can be obtained using ABCD parameters [1] as
cosh(qh)+ Z S
sinh(qh)
(1)
sl)sc is the propagation constant and Z
R+sL
is the characteristic impedance;
h are resistance, in-
ductance, and capacitance per unit length and h is the length of the line.
The variables b k are called the coefficients of the transfer function and
are directly related to the moments of the transfer function [8]. Expanding
the transfer function into a Maclaurin series of s around
to an infinite series, and to compute the response the series is truncated
to desired order. The method of Pad -
e approximation has been widely
used to compute the response from the transfer function [11, 12]. For
the case of resistive source (R S ) and capacitive load (C L ) impedances,
the coefficient of s in the transfer function can be obtained as [8] b
Efficient delay estimates for interconnect lines are typically derived
by considering a single interconnect line with resistive source and capacitive
load impedances; delay formulas for an interconnect tree come
from recursive application of the formula for a single line. Elmore delay
[2] is a first order delay estimate for interconnect lines under step input.
It is equal to the first moment of the system impulse response, i.e., the
coefficient of s or the first moment in the system transfer function H(s).
Applying this definition to H(s) in Equation (1), we see that the Elmore
delay is equal to the coefficient b 1 .
We use threshold delay to refer to delay measured from the point when the input signal
is zero. To compute delay relative to the input signal, subtract the corresponding threshold
delay of the input signal (e.g., for 50% threshold voltage, the delay for the input ramp is T R
Z
Distributed RLC line

Figure

1: 2-port model of a distributed RLC line with source
impedance Z S and load impedance Z T .
By considering only one pole in the transfer function, i.e, approximating
the denominator polynomial to only the first moment, the single
pole response can be obtained as in [4, 15]. The single pole of the
transfer function is equal to the inverse of the Elmore delay T ED . Hence,
the delay at arbitrary thresholds of the single pole response can be directly
related to Elmore delay (Elmore delay actually correspondsto the
63:2% threshold voltage of the single pole response). For example, delay
at 50% threshold voltage is 0:69b 1 , and delay at 90% threshold voltage
is 2:3b 1 . Although Elmore delay has been widely used for interconnect
timing analysis, it cannot accurately estimate the delay for RLC interconnect
lines, which are the appropriate representation for interconnects
whose inductive impedance cannot be neglected [6]. 2 More crit-
ically, Elmore delay cannot estimate delays when the input signal is a
ramp.
3 Analytical Ramp Delay Definitions
In practice, the input at any gate or root of a tree is a ramp with finite
rise (or fall) time, and there are no published analytical delay models
for ramp input. Wenow propose various ramp delay definitions and also
compute analytical delay expressionsusing the first one or two moments
of the transfer function. We discuss delay models for rising ramp input
only, since our analyses can be easily extended for falling ramp input
[9].
Time
Voltage
Time
Voltage
(a) (b)

Figure

2: A ramp input function: (a) finite ramp with rise time T R ,
and (b) finite ramp decomposed into two shifted infinite ramps.
Rising Ramp Input
The finite rising ramp input shown in Figure 2 can be expressed in
the time domain as
v in
denotes the step function. The finite ramp input in the transform
domain is V in
In the transform domain, the
output response is
Recently, [8] havedevelopeda more accurate analytical delay model consideringinduc-
tive effects basedon the first andsecondmoments of the transfer function. Their model gives
accurate estimates compared to SPICE-computed delays, but is valid only for step inputs.
We now give two distinct derivations of an analytical ramp delay estimate

Elmore Definition.
Applying Elmore's original definition of delay for step input [2] yields
an analytical delay T AD for ramp input, i.e.,
out (t) is the derivative of the output response under finite ramp
input. Taking the Laplace transform of v 0 out (t),
out
Z -tv out
Equation (2) then implies that the analytical ramp input delay T AD in
the time domain is equal to the first moment of the derivative of the re-
sponse. In the transform domain, T AD is equal to the first moment (or
coefficient of s) of the function V out
, which is equal to s \Delta V out
. The
derivative of the response in the transform domain is
out
Therefore, the analytical ramp input delay is
where T ED is the Elmore delay for a step input (i.e., the first moment of
the transfer function). Another definition of delay based on the formula
given in [10] yields the same result of Equation (3) [9].
Group Delay Definition.
The concept of group delay was initially defined for step input by
Vlach et al. [18]. We now give a group delay definition for computing
ramp input delay similar to that in [18], and show that it converges to
the same analytical expression of Equation (3).
Recall that group delay is definedas the negative of the rate of change
of the phase characteristic f of the output responseV out (w) with respect
to frequency, at zero frequency, i.e., T
-w . To compute
the phase characteristic of the output response, we first compute the output
responseV out (s) in the transform domain and then substitute for the
Laplace variable
R
R
R
are the real and imaginary parts of the input ramp
function. Writing the transfer function in terms of numerator and denominator
polynomials,
Then, the phase characteristic of the output response is
tan
. We obtain the group delay as
-f
4 Single-Pole Analysis
If we approximate the system transfer function up to the first moment (or
coefficient of s), H(s)- 1
. Then, the output response under infinite
ramp is 3
U out
with corresponding time-domain response
\Gammat
The time-domain response for a finite ramp is therefore
\Gammat
\Gamma(t \GammaT R )
Note that as t ! -, v out (t) tends to a final value of V 0 as expected. [16]
useda similar single-pole analysis to compute delay and transition times
solving the above response equations by applying Newton-Raphson iteration

4.1 Analytical Delay Model
It turns out that using the analytical ramp delay computed using the definition
in Section 3 and the output response given in Equations (4) and
(5) leads to the same result:
out (t)dt +V 0
out (t)dt
Threshold Voltage Corresponding To Analytical Ramp Delay.
Section 3 gave two different methods for computing an analytical
ramp input delay from the output response. The threshold voltage corresponding
to this analytical delay is not known, and must be computed
by substituting T AD for time in either the infinite or the finite ramp responses

Computing the threshold voltage for the infinite ramp response in Equation
2 , we get
In the limit as 2b 1
0 the threshold voltage reduces to u out
. Hence, for large rise-times or small first moment of the transfer function
the analytical delay T AD correspondsto 50% threshold voltage. When
using the finite ramp response in Equation (5) gives
2e
In the limit as 2b 1
!- the threshold voltage reduces to v out
. Hence, for small rise-times or large first moment
of the transfer function the analytical delay T AD corresponds to
63:2% threshold voltage. We see that for any choice of T R and b 1 the
threshold voltage corresponding to the analytical delay T AD will be between
50% and 63:2%.
3 In the transform and time domains, we respectively use U(x;s) and u(x;t) to indicate
the response for infinite ramp input, and V(x;s) and v(x;t) to indicate the response for finite
ramp input.
4.2 Threshold Delay Models
Condition for Computing Threshold Delay Using Finite or Infinite
Ramp Response.
The ramp input delay at any threshold voltage can be computed using
the infinite ramp response in Equation (4) if the ramp delay is less
than the rise time T R , or using the finite ramp response in Equation (5)
if the ramp delay is greater than T R . For example, the delay at threshold
Th1 in

Figure

3 is computed using the infinite ramp response, and the
delay at threshold Th2 is computed using the finite ramp response. To
determine when the infinite ramp response should be used, we write the
threshold voltage corresponding to the rise-time T R in terms of interconnect
and rise time parameters:
Time
Voltage
Th2
Th1

Figure

3: Ramp input delay at various threshold voltages.
Here, v T R is the threshold voltage at which the delay through the inter-connect
is equal to T R . Let v th be the threshold voltage of interest for the
finite ramp response, expressed as a fraction of the steady state voltage
delay is calculated using Equation (4), and if v th ? v T R ,
delay is calculated using Equation (5).
th
Figure

4: Variation of threshold voltage at delay equal to rise-time T R
with respect to the factor b 1
Observe that Equation (6) can be rearranged to obtain a condition on
for any given threshold voltage v th : the condition for delay calculation
using infinite ramp response is
and the condition for delay calculation using finite ramp response is

Figure

4 shows the variation of v T R with respect to the factor b 1
. At
the threshold voltage v T R
is 0:368V 0 , i.e., 36:8%. Since most
sub-micron interconnect networks have small rise-times and large propagation
delays, the delays at threshold voltages of interest (50% or 90%)
will likely be computed by considering the finite ramp response as developed
in Equation
Threshold Delay Using Infinite Ramp Response.
Model 1. For the infinite ramp response of Equation (4), the threshold
delay is
\GammaT RD1
where u th is the threshold voltage of interest for the infinite ramp re-
sponse. We can solve such a recursive equation in less than 10 iterations
of simple back-substitution (with T AD as the starting value) for all
the interconnect configurations we considered. To obtain a closed-form
delay formula, we approximate T RD1 in the exponential term with some
f (T AD ), which yields
Here, f (T AD ) dependson the threshold voltage and T AD . 5 The above delay
estimate can be improved by expressing T RD1 as u th T R +t RD1 , since
the threshold delay for the infinite ramp responseT RD1 is greater than the
threshold delay for the infinite ramp input u th T R . Making this change in
delay variable in Equation (4), we get
Expanding
1 as a Taylor series and considering only the first three
terms yields
th T R
th T R
Solving for t RD1 in the above equation, the threshold delay can be expressed
as
th T R
e
th T R
Using this T RD1 value for f (T AD ) in the exponential term of the Equation
(7), we obtain delay values that are very close to the values obtained by
solving the equation through iteration.
Threshold Delay Using Finite Ramp Response.
Model 2. For the finite ramp response of Equation (5),
th =T R
\GammaT RD2
\Gamma(T RD2 \GammaT R )
Collecting the threshold delay T RD2 terms, we obtain
th )A
4 At 50% threshold, the condition for delay calculation using infinite ramp response is
- 0:625, with delay calculated using finite ramp response otherwise. Similarly, at 90%
threshold, the condition for delay calculation using infinite ramp response is b 1
0:1.
5 In [9] the function f (T AD ) is approximatedby f (T AD
th ), which is threshold
delay for the system with analytical delay as the time constant. The delay estimates using
this approximation are reasonably close to SPICE-computed delays.
where the factor F
such a large variation in F 1 , it is very difficult to fit the threshold delay
against the corresponding SPICE delay.
Model 3. Since the threshold delay computed from the finite ramp response
is greater than T R , an alternative formula for the threshold delay
can be obtained by expressing T RD3 as T Substituting
into Equation (5) yields
th =T R
\GammaT R
\Gammat RD3
\Gammat RD3
Therefore, the delay is
The factor F
as shown in

Figure

5. For this factor is F R we can
find a good approximation for F 2 by fitting against SPICE-computed de-
lays, since the variation in F 2 values is very small. However, for the
range of interconnect configurations studied both Model 2 and Model
3 gave essentially identical results and hence Section 7 reports results
from Model 2 only.50.00250.00450.00650.00850.000.00 2.00 4.00 6.00 8.00 10.00

Figure

5: Variation of factor F
respect to b 1
5 Two-Pole Analysis
The two-pole methodology for interconnect response computation under
step input has been discussed in [4, 7, 20]. For interconnect trees
(or lines) the transfer function has a special form in which the numerator
polynomial is a constant, i.e., approximating to s 2 term yields H(s)-1+sb 1 +s 2 b 2
. For the case of resistive source (R S ) and capacitive load (C L )
impedances, the transfer function coefficients are given by [8]
RC
For this form of the transfer function, the output response under infinite
ramp input is
U out
and the corresponding time-domain response is
where U(t) is the unit step function. The time-domain response for a
finite ramp is
Note that the first and second moments of the transfer function can be
obtained from the coefficients b 1 and b 2 , i.e.,
We use the coefficient notation and the moment notation
interchangeably according to the simplicity of the expression.
5.1 Threshold Delay Models
Depending on the sign of b 2
the poles of the transfer function
can be either real or complex. However, for most cases of interest the
poles turn out to be real, and we now discuss delay models for the case
of real poles. The condition for the poles to be real is (b 2
the magnitude js 2 j is greater than js 1 j, the second
term in the time-domain responsedecreasesrapidly compared to the
first term. Hence, the two-pole infinite ramp response can be approximated
as
and the finite ramp response as
v out (t) -
Note that the residue k
is a positive quantity, and that the pole
s 1 has to be negative in value for the response to converge.
Threshold Delay for Infinite Ramp Response.
Model 4. The delay T RD4 at threshold voltage u th can be obtained as
Again, we can solve such a recursive equation in less than 10 iterations
of simple back-substitution (with T AD as the starting value) for all the
interconnect configurationswe considered. Another way to evaluate the
above iterative equation is by substituting some f (T AD ) for T RD4 in the
exponential term, which yields
depends on the threshold voltage and T AD . For example,
for 50% threshold voltage f (T AD threshold voltage
We found that the delay values using Equation
are close to the values obtained by solving the equation through it-
eration. Similar to the analysis of Model 1, a better approximation for
the f (T AD ) term can be obtained by expressing T RD4 as u th
since T RD4 is greater than the threshold delay for the infinite ramp input
th T R ).
Threshold Delay for Finite Ramp Response.
Model 5. The delay T RD5 at threshold voltage v th can be obtained from
the response as
th
Since the value of the pole s 1 is negative, the quantity (e \Gammas 1
positive and the residue 1+b 1 s 2
is also positive. Thus, the delay expression
reduces to
where the factor F
can vary widely.
Model 6. Since the threshold delay computed from the finite ramp response
is greater than T R , an alternative formula for the threshold delay
can be obtained by assuming the form T Substituting
into Equation (15) yields
th
Therefore, the delay is
where the factor F
varies over only a small range.
For the range of interconnect configurations studied both Model 5 and
Model 6 gave essentially identical results, and hence Section 7 reports
results from Model 5 only. [9] gives a detailed discussion of two-pole
models for the case of complex poles.
6 Interconnection Trees
Finally, we describe how to extend our analytical models to estimate delays
in arbitrary interconnect trees. An RLC network is called an RLC
tree if it does not contain a closed path of resistors and inductors, i.e., all
resistors and inductors are floating with respect to ground, and all capacitors
are connected to ground. Consider an RLC interconnect tree with
root (or source) S and set of sinks (or leaves) ng. The unique
path from root S to the sink node i is denoted by p(i) and is referred to
as the main path. The edges/nodes not on the main path are referred to
as the off-path edges/nodes. We model each edge on the main path of
the tree using a lumped RLC segment, e.g., an L, T, or p model. 6
We approximate the off-path subtree rooted at node i with its admit-
tance. At any node i, the admittance Y i is equal to (i) the capacitance of
node i (C i ) if there is no subtree at node i, or (ii) to the sum of the capacitance
of node i (C i ) and the subtree admittance Y T(i) otherwise. In
other words,
node i has no off-path subtree
node i has an off-path subtree
With this approximation, the main path reduces to an RLY equivalent
circuit. Only two admittance moments need to be computed for an
exact transfer function moment computation for the main path. The k th
6 Our model is not limited to traditional segment models, and accuracy of our results
would likely improve if we use non-uniform segment models [7, 19] designed to perfectly
match the low-order moments of the distributed RLC line.
R L N

Figure

Representation of the main path in the tree, where each distributed
line is modeled using RLC segments. Y i indicates the off-path
subtree admittance at node i.
coefficient b k of the transfer function for the general RLY circuit of Figure
6 can be obtained using the recursive equation given in [7]. The first
and second coefficients of the transfer function are
The first and second moments are expressed in terms of coefficients as
. For any given source-sink pair the coefficients
can be computed in linear time by traversing the main
path and using Equation (19) to obtain transfer function coefficients.
7 Experimental Results
We evaluate the above models by simulating various RLC interconnect
lines with different source/loadimpedancesand different input rise times.
We consider typical interconnect parameters encountered in single-chip
interconnects [8], with the length of the interconnect being 2000 -m.
The source resistance is varied between 100 to 1000 W and the load capacitance
is varied from 0:1 to 1:0 p f . We also consider 100 ps and 500
ps rise times for the input ramp.
For all our experiments, we compute exact 50% and 90% delays
from the response at the load using the SPICE3e simulator. The step
input delay is computed using the Elmore delay formula and then multiplying
it with the appropriate constant for the given threshold voltage.
For example, Elmore delay at 50% threshold voltage is 0:69b 1 and at
90% threshold voltage is 2:3b 1 . Unlike [5], we find that Elmore delay
is not at all close to SPICE-computed 50% threshold delays and, depending
on the rise time of the signal and driver resistance, can be either
greater or less than SPICE-computed delays (e.g., when the rise time is
500 ps the Elmore delay is for most cases less than the SPICE-computed
delays). Also, increased rise time of the input signal causes the Elmore
delay to deviate further from SPICE-computed delays (see Tables 1 and
3).
For comparison, we also present delay estimates using the analytical
ramp delay model T AD . When the rise time of the ramp input is increased
from 100 ps to 500 ps the SPICE delays at 50% threshold are increased
by approximately 200 ps, which suggests that delay at 50% threshold
voltage is proportional to T R
2 . This effect of the rise time is well modeled
in the analytical ramp delay model T AD . To compute ramp input
delays using the single-pole methodology we use either the Model 1 or
Model 2, depending on the value of the first moment b 1 and the threshold
voltage of interest. Similarly, to compute ramp input delays using
the two-pole methodology we use either Model 4 or Model 5, again depending
on the value of b 1 and the threshold voltage of interest. (If the
delay is computed using the infinite ramp response then we mark those
delays in the Table with (   ).) Tables 1 and 2 give 50% and90% delay estimates
for ramp input with 100 ps rise time. Tables 3 and 4 give 50%
and 90% delay estimates for ramp input with 500 ps rise time. Over
our range of test cases, Elmore delay estimates can be as much as 100%
away from the SPICE-computed delays. In contrast, our single-pole delay
estimates are within 4% of SPICE delays and the two-pole delay estimates
are within 2:3% of SPICE delays.
Conclusions
Fast delay estimation methods, as opposedto simulation techniques, are
needed for incremental performance-driven layout synthesis. Estimation
methods based on Elmore delay for a step input, although efficient,
cannot accurately estimate the delay for RLC interconnect lines. We
have obtained new analytical delay models under ramp input, based on
the first and second moments of RLC interconnection lines. The resulting
delay estimates are significantly more accurate than Elmore delay
estimates. We also describe how to extend our delay models to estimate
source-sink delays in arbitrary interconnect trees.



--R

Modern Transmission Line Theory and Applications
"The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers"
"Ramp Input Response of RC Tree Networks"
"TimingModels forMOS Circuits"
"The Elmore Delay as a Bound for RC Trees with Generalized Input Signals"
"Signal DegradationThroughModule Pins in VLSI Pack- aging"
"Two-poleAnalysis of InterconnectionTrees"
"Accurate Analytical Delay Models for VLSI Intercon- nects"
"Analytical Delay Model for VLSI Interconnects Under Ramp Input"
"Signal Delay in General RC Networks"
" Waveform Moment Methods for Improved Interconnection Analysis"
"Asymptotic Waveform Evaluation for Timing Analy- sis"
"AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems"
"RICE: Rapid Interconnect Circuit Evalu- ator"
"Signal Delay in RC Tree Networks"
"Simple Expressions for Interconnect Delay and Input Transition Time"
"Fast Approximationof The Transient Response of Lossy Transmission Line Trees"
"Group Delay as an Estimate of Delay in Logic"
"Exact MomentMatching Model of Transmission Lines and Application to Interconnect Delay Estimation"
"A Simplified Synthesis of Transmission Lines with A Tree Structure"
--TR
Signal degradation through module pins in VLSI packaging
AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
Waveform moment methods for improved interconnection analysis
Fast approximation of the transient response of Lossy Transmision Line Trees
A simplified synthesis of transmission lines with a tree structure
Exact moment matching model of transmission lines and application to interconnect delay estimation
The Elmore delay as bound for RC trees with generalized input signals

--CTR
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interconnect transfer function;ramp input;analytical delay models;VLSI routing topologies layout;RLC interconnections;performance-driven synthesis;source-sink delays;elmore delay;SPICE-computed delay;interconnect delays;VLSI;VLSI interconnects;arbitrary interconnect trees