An efficient approach to simultaneous transistor and interconnect sizing.
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs. We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an efficient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 16.1%, and more significantly, reduces the power consumption by a factor of 1.63X, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-off. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304 /spl mu/m-long wire in 120 seconds, and a 32-bit adder with 1026 transistors in 66 seconds on a SPARC-5 workstation.
INTRODUCTION
The interconnect delay has become the dominating factor
in determining the circuit performance in deep submicron
designs. We believe that the most effective approach to
performance optimization in deep submicron designs is to
consider both logic and interconnect designs throughout the
entire design process (from RTL level to layout design). As
part of our effort to develop a unified methodology and
platform for simultaneous logic and interconnect design and
optimization, we study the simultaneous transistor and interconnect
sizing (STIS) problem in this paper.
Most previous works on layout optimization size transistor
and interconnect separately, which may lead to suboptimal
designs. The transistor sizing problem is to find the
optimal width for each transistor under certain objective
functions as studied in [14, 18], while the gate sizing problem
is to find the optimal width for each gate by assuming
all transistor sizes within a gate increase or decrease by a
uniform factor [1, 5, 2]. The interconnect sizing problem,
also called the wiresizing problem, was first introduced in
[10, 11] to determine the optimal width for each wire segment
in interconnects and the first polynomial-time optimal
algorithm was developed. Later on, alternative wiresizing
algorithms were proposed in [17, 23, 25, 6, 3].
Recently, several studies considered simultaneous transistor
and interconnect sizing for some special cases. The
This work is partially supportedby ARPA/CSTO under contract
J-FBI-93-112, the NSF Young Investigator Award MIP-
9357582 and a grant from Intel Corporation.
authors of [8] proposed an efficient algorithm for the simultaneous
driver and wire sizing problem. The authors of
[16] solved the simultaneous buffer insertion and wire sizing
problem by a dynamic programming approach. The authors
of [19] studied the simultaneous gate and wire sizing problem
and solved it by the sequential quadratic programming
technique. Most recently, the authors of [20] solved the
simultaneous buffer insertion, wiresizing and tree construction
problem. Their gate sizing formulation, however, may
lead to suboptimal designs, especially in the full-custom
layout. In order to achieve better designs, our STIS formulation
is able to optimize the size of every transistor and the
width of every wire segment (under a non-uniform wire seg-
mentation). A very efficient algorithm has been developed
based on the general dominance property. It can be used
either as a global planning tool after initial floorplan, place-
ment, and global routing to determine the sizes of global
interconnects and inter-block drivers/buffers, or as a block-level
optimization tool to compute the optimal sizes of all
transistors, gates, and wires within a functional block.
The remainder of this paper is organized as follows. In
Section 2, we present the formulation of the STIS prob-
lem. In Section 3, we reveal the dominance property for a
class of optimization problems named CH-posynomial programs
and show that our STIS problems under a number of
transistor models are CH-posynomial programs. In Section
4, we propose a polynomial-time algorithm to compute a
set of lower and upper bounds of the optimal solution to
the STIS problem. In Section 5, experimental results show
the algorithm often achieves the identical lower and upper
bounds, which lead to the optimal solution. Thus, it is a
near-optimal algorithm in practice. A novel contribution
of our work is that the algorithm is applicable to any optimization
problem if it is a CH-posynomial program. Proofs
of theorems are given in a technical report [7].
2. FORMULATIONS
2.1. Delay model for Transistors and Interconnect

We model a transistor by the source-drain effective resistance
rd , and the gate, source and drain capacitances cg ; cs
and cd . Let x be the transistor width, rd ; cg ; cs and cd can
be written as the following:
where cg0 ; cs0 and cd0 , as well as cg1 ; cs1 and cd1 are constants
determined by the technology. In addition, rd0 is the
unit effective resistance as defined in the following: assuming
an n-type transistor is driven by a rising input. If the
transistor size is x, the capacitance loading CL , and the
50% delay - , we define the effective resistance rd and the
unit effective resistance rd0 of the transistor as:
The unit effective resistance of a p-type transistor can
be defined similarly under the falling input. Let
xng denote the sizes for all transistors and wires.
We point out that, in general, rd0 is a function of X (i.e.,
the unit effective resistance of a transistor depends on the
sizes of all transistors and wires in the design). We use rd0
instead of rd0 (X) for the simplicity of presentation.
We model a routing tree as a distributed RC tree, similar
to [11, 6]. Each wire segment is divided into a sequence
of uni-segments. A uni-segment is treated as a -type RC
circuit and the wire width is assumed uniform within a uni-
segment. For simplicity, we assume that all uni-segments
have the same wire length and the unit-width uni-segment
has wire resistance r0 , wire area capacitance c0 and wire
fringing capacitance c1 . Then, the resistance r and the
capacitance c for a uni-segment with width x are
Our delay computation is similar to that in the switch
level timing analysis tool Crystal [21]. The delay will be
computed based on a stage, which is a DC-current path
from a signal source (either the Vdd or the ground) to the
gate of a transistor, including both transistors and wires.
The delay of a stage P (Ns ; N t ) where Ns is its source and
N t is its sink can be written as Eqn. (9) according to the
Elmore delay formulation in [24].
f st
f st
st (i) \Deltax i
st
st
where x i is the width for either a transistor or a wire, and
f st
st
st ; h st
st
are coefficient functions, which can
be determined in a similar way as in [11, 6]. We point
out that the unit effective resistance rd0 for the transistor
always appears as a multiplying factor in these coefficient
functions. Furthermore, rd0 is multiplied by constants
which can be determined before the sizing procedure. This
fact is helpful to prove the dominance property for STIS
problems in Section 3. Similar delay formulations for transistors
have been used in both [21] and [14] except that both
model the interconnect as a lumped capacitance instead of
a distributed RC tree model as used in our formulation.
Note that the unit effective resistance rd0 of a transistor in
both our formulation and [21] is a function of X. However,
it was formulated as a constant independent of X in [14].
2.2. STIS Problem to Minimize Delay for Multiple
In order to minimize delays along multiple critical paths in a
circuit simultaneously, we propose to minimize the weighted
delay t(X) of all stages in the set of critical paths, which is
denoted as P:
st
where the penalty weight - st indicates the criticality of
stage which can be provided either by the designer
(after timing simulation) or computed iteratively using
the Lagrangian-relaxation method as in [3] to minimize
the maximum delay. Note that although the number of critical
paths in a circuit may grow exponentially with respect
to the number of logic gates, the number of critical stages
grows almost linearly. Let
st st
st st
st \Delta g st (i) (13)
st \Delta h st
and eliminate those terms independent of X, Eqn. (10)
becomes
With respect to Eqn. (15), we define the following STIS
problem to minimize delay through multiple critical paths:
Formulation 1 Given a circuit and the lower and upper
bounds for the width of each transistor and wire, the STIS
problem is to determine the width for each transistor and
wire (or equivalently, a sizing solution X) such that the
weighted delay through multiple critical paths given by Eqn.
(15) is minimized.
In practice, it is often the case that we want to size
the transistors and wires without increase in the layout
area (using the free space in the current layout) or with
bounded increase in the layout area. Therefore, there is
an upper bound associated with each transistor and wire
during the optimization. On the other hand, there is a
lower bound associated with each device and wire due to
the technology feature sizes and reliability concerns (such
as electro-migration). Thus, the lower and upper bounds
are used to handle these constraints. It will
be seen later on that the lower and upper bounds are the
starting point for our STIS algorithm. It is easy to see that
the STIS problem is equivalent to the wiresizing problem
when the identical lower and upper bounds are given for
the widths of all transistors, or equivalent to the transistor
sizing problem when identical lower and upper bounds are
given for the wire widths of all wires.
3. THE DOMINANCE PROPERTY
Instead of developing ad hoc heuristic methods for the STIS
problem, we define a class of optimization problems named
CH-posynomial programs and reveal the dominance property
for all CH-posynomial programs. Then, we show that
the STIS problems under several delay models are CH-
posynomial programs and an efficient STIS algorithm will
be developed based on the dominance property.
3.1. Dominance Property for CH-posynomial Program

A function f(X) is defined as a general CH-posynomial if
it is of the following form:
where api
and the coefficient functions satisfy the following conditions:
a function of x i . It monotonically increases
with respect to an increase of x i , but a pi
still monotonically
decreases with respect to an increase of x i . (ii)
a function of x j . It monotonically decreases with
respect to an increase of x j , but bqj
still monotonically
increases with respect to an increase of x i . When the
coefficient functions in Eqn. (16) are constants, the function
f(X) is called a simple CH-posynomial. The class of simple
CH-posynomials is a subset of posynomial functions defined
in [13]. We call an optimization problem to minimize a simple
or general CH-posynomial subject to L - X - U as a
simple or general CH-posynomial program, and introduce
the following concepts of dominance relation and local refinement
operation.
Definition 1 For two vectors X and X 0 , we define that X
dominates (denoted as
i for all i.
2 The local refinement operation of a solution
vector X, with respect to any particular variable x i and
function f(X), is to minimize f(X) subject to changing only
keeping the values of other x j (j 6= i) unchanged.
We say that the resulting solution vector is the local refinement
of X (with respect to x i ). For simplicity, we also
use term solution instead of solution vector. Let X   be the
optimal solution minimizing f(X). We say that the problem
of optimizing f(X) satisfies the dominance property if
dominates X   implies that a local refinement of X still
dominates X   , and X is dominated by X   implies that a
local refinement of X is still dominated by X
We showed the following important theorem which is the
foundation of our STIS algorithm to be presented in Section
4.
Theorem 1 The dominance property holds for both simple
and general CH-posynomial programs.
The authors of [11] first proposed the dominance property
for the single-source wiresizing problem. Our results greatly
generalize the concept of the dominance property and reveal
that the dominance property holds for a much larger class
of optimization problems. One can show that the single-source
wiresizing problem [11], the multi-source wiresizing
problem [6] and the simultaneous driver and wire sizing
problem [8] are instances of the simple CH-posynomial pro-
gram. The dominance property will lead to an efficient
polynomial-time algorithm in Section 4. We will show that
STIS problems are CH-posynomial programs in order to use
the algorithm.
3.2. Dominance Property for STIS Problems
Recall that the unit effective resistance rd0 for the transistor
is always a multiplying factor in coefficient functions
and H1 in Eqn. (15). It in fact determines
whether Eqn. (15) is a CH-posynomial. There are two
types of models for the unit effective resistance rd0 . The
step model assumes that the input to the transistor is always
a step so that rd0 is a constant independent of the
sizing solution X. As a result, all coefficients of Eqn. (15)
are positive constants independent of X. We have the following
theorem:
Theorem 2 The STIS problem under the step model is a
simple CH-posynomial program with the dominance property

The step model has been used in [14] for transistor sizing
and in wiresizing works [11, 17, 6] and simultaneous driver
and wire sizing work [8] to model the driver. However, the
step input is just an ideal assumption. For an inverter, let
-0 be the delay under the step input and - the delay under
the slope input whose transition time is s. The following
relation was given in [15]:
where fi is a constant determined by the technology. It
shows that the delay is an increasing function of the input
transition time. Recalling the definition of the effective
resistance (Eqn. (5)), the larger the input transition time,
the larger the effective resistance and the unit effective resis-
tance. Furthermore, we associate the input transition time
with the transistor size as the following: since increasing
the size of a transistor M i always increases the gate capacitance
of M i , the output of the previous stage, which is the
input to M i , will become slower because M i contributes a
larger loading capacitance. In turn, the slower input to M i
increases its unit effective resistance. To be more precise,
we define the following DP-slope model:
Definition 3 The DP-slope model is a transistor model
where the unit effective resistance for the transistor is an
increasing function of its size.
Given the definitions, we also have the following theorem:
Theorem 3 The STIS problem under a DP-slope model
is a general CH-posynomial program with the dominance
property.
It worthwhile to mention that if Eqn. (17) is used to
compute a gate delay by assuming that the input transition
time is twice the Elmore delay of the previous stage as the
transistor sizing formulation in [18], the path delay is a simple
CH-posynomial and the STIS problem under this delay
model is a simple CH-posynomial program. Nevertheless,
Theorem 3 is more general in the sense that it is applicable
to the DP-slope model of any form or even without a
closed form. A DP-slope model without a closed form will
be discussed in Section 4.
4. THE STIS ALGORITHM
4.1. Optimization Using Dominance Property
For a CH-posynomial f(X) where L - X - U, a local refinement
based algorithm (LRA algorithm) can be used to
compute a set of lower and upper bounds for the optimal solution
to minimize f(X). It is a greedy algorithm based
on iterative local refinement operations. Beginning with a
solution L, we traverse every x i in a specific order
to perform a local refinement operation on it. Because X
is dominated by X   , its local refinement is still dominated
by X   . This process is repeated and X becomes increasingly
closer to but always dominated by X   . This process
produces a set of lower bounds of X   and is stopped when
no improvement is achieved in the last round of traversal.
Similarly, a set of upper bounds for X   can be obtained
by performing local refinement operations beginning with
In essence, the LRA algorithm generalizes the greedy
wiresizing algorithm GWSA [11]. We define that a lower or
upper bound of X   is LR-tight if it can not be tightened by
any local refinement operation. Then, the LRA algorithm
computes the LR-tight lower and upper bounds of X   in the
polynomial time O(r r is the average number
of the possible evaluations for all x
and l is the cost of a single local refinement operation, which
be discussed in the next subsection. In practice, we usually
find that the LR-tight lower and upper bounds meet, which
leads to the optimal solution immediately.
4.2. Computation of Coefficient Functions and Local
Refinements
In order to initialize the coefficient functions efficiently,
all transistors and interconnects are pre-partitioned into
DCCs. A DCC is a set of transistors and wires which are
connected by DC-current paths containing only transistor
channels or wires, and the DC current can not cross the
boundary of a DCC. In most cases, a DCC is just a gate G
and a routing tree connecting the output of G to the inputs
of all gates driven by G. Since these coefficients defined in
Eqn. are computed basically within a DCC, the
computation can be finished in O(
is the total number of DCC's in a circuit and m i is the total
number of transistors and wire uni-segments in the i-th
(roughly,
number of variables
in X).
The cost of the local refinement operation is related to the
delay model. We use both the step model and a table-based
slope model for comparison. Since the STIS problem under
the step model is a simple CH-posynomial program with
constant coefficients in its objective function, the local refinement
operation can be finished in O(m i ) time, where m i
is still the total number of transistors and wire uni-segments
in the i-th DCC. We assume a DP-slope model of the most
general form; only unit effective resistance rd0 for each transistor
size is given. Since the STIS problem under this type
of slope model is a general CH-posynomial program, the
coefficients of Eqn. (15) in fact are functions of the sizing
solution X. When there is no closed form to associate
X with the unit effective resistance (in general, no closed
form relation between the variables and the coefficients in
the general CH-posynomial), the local refinement operation
becomes very expensive or even impossible. We propose the
following the starting solution is first
1 The complexity of brute-force enumeration is O(r n ).
update the the coefficient functions with respect to X 0 and
then compute "local refinement" with respect to these co-efficient
functions. A novel contribution of this work is that
we proved that the dominance property still holds for a
general CH-posynomial program with respect to this type
of "local refinement". Since the update of coefficient functions
before the local refinement operation can be finished
in O(m i ) time, the local refinement operation for a general
CH-posynomial program still can be finished in O(m i ) time.
Instead of the simple analytical model in Eqn. (17), a
lookup table is pre-computed for values of the unit effective
resistance rd0 for a transistor. In general, rd0 of a transistor
depends on its size, its input transition time and its capacitance
loading so that a three-dimensional table is needed in
a straightforward implementation. The three parameters,
however, can be combined into one factor called the slope ratio
to determine rd0 solely [22, 21]. Thus, a one-dimensional
table is used instead of a three-dimensional table and a table
is built for every type of transistors based on SPICE
simulations.
4.3. Overview of Near-Optimal STIS Algorithm
The overall STIS algorithm includes three steps: (i) initialization
of the coefficient functions, (ii) computation of
LR-tight lower and upper bounds of the optimal solution,
and (iii) computation of the optimal solution between the
LR-tight lower and upper bounds. Note that the coefficient
functions will be updated during the sizing procedure because
the unit effective resistance rd0 under the DP-slope
model depends on the sizing solution X.
Furthermore, we proved that there exists an optimal STIS
solution such that the optimal wire widths are monotonic
within each wire segment, which enable us to generalize
the concept of the bundled refinement operation and the
bundled-refinement based wiresizing algorithm (OWBR al-
gorithm) [6] to our STIS formulation. It was shown in [6]
that the OWBR algorithm runs 100x time faster than the
local-refinement based wiresizing algorithm [11].
Finally, if the LR-tight lower and upper bounds are identical
for every transistor and wire, the optimal solution is
achieved immediately. We observed that the identical LR-
tight lower and upper bounds are often achieved in our ex-
periments. In this case, since the coefficients and the LR-
tight lower and upper bounds are computed in polynomial
times O(
respectively, the
optimal STIS solution is achieved in the polynomial-time.
Moreover, when the LR-tight lower and upper bounds do
not meet, the gap between them is very small, often just
of one discrete width in our experiments, and the percent
of non-identical lower and upper bounds is also very small,
thus enumeration can be carried out in reasonable time.
During the enumeration of the width for a transistor or
wire between its LR-tight lower and upper bounds, widths
of other transistors and wires can be determined by local
refinement operations rather than enumeration. Thus, the
optimal solution can be achieved efficiently in practice. It
is worthwhile to mention that an LR-tight lower or upper
bound has zero sensitivity, thus the sensitivity based
method can not be used to obtain a solution better than an
LR-tight lower or upper bound.
5. EXPERIMENTAL RESULTS
5.1. Simultaneous Driver/Buffer and Wire Sizing
We have implemented the near-optimal STIS algorithm in
a SUN SPARC-5 workstation and tested the algorithm on a
# of length max delay (ns) device area (-m 2 ) wire area (-m 2 ) average power (mW) runtime
drivers (-m) CDWS STIS CDWS STIS CDWS STIS CDWS STIS
net1 15 3600 1.063 0.876(-17.7%) 563.0 188.6 4320 3240 31.9 2.17 0.08
net2
net3 36 10070 1.326 1.225(-7.6%) 8773.2 3222.4 23967 19242 45.8 14.2 0.77
net4
net5
total 129 179800 28046.8 11934.3 227661 192570 210.4 80.59 7.18

Table

1. Simultaneous driver and wire sizing for multi-source nets.
net # of wire length max delay (ns) average power (mW) runtime
drivers (-m) original SBWS STIS original SBWS STIS
clk 367 59304.0 6.2016 6.1578(-0.7%) 5.9035(-4.8%) 499.7 286.8(-42.6%) 285.6(-42.8%) 120.79

Table

2. Comparison of buffer and wire sizing for clock nets.
transistors 16bit adder, 514 transistors 32bit adder, 1026 transistors

Table

3. Delay-area trade-off for transistor sizing.
number of examples for advanced IC technologies. First, we
use the STIS algorithm to solve the simultaneous driver and
wire sizing (SDWS) problem for multi-source nets. 2 These
nets are extracted from an Intel high-performance micro-processor
design and were used in [12, 6] for topology construction
and wiresizing optimization. We assume that a
chain of cascade drivers is used for each source and the first
stage is a minimum-size (1x) driver. We compare our STIS
method with the CDWS method. The CDWS method uses
a constant stage ratio is the
gate capacitance of the 1x driver, and CL the total loading
capacitance when the wires have the minimum width. The
stage number N is chosen such that ff is around e, the base
of natural logarithms, for performance optimization. Then,
the CDWS method applies the OWBR algorithm [6] to obtain
the optimal wiresizing solution. The STIS method uses
the same stage number N and assumes the first stage is also
a 1x driver, but the sizes of both wires and transistors in
other stages are determined by the STIS algorithm. We use
parameters of MCNC 0:5-m CMOS technology, the same as
was used in [6]. We assume the nets are driven by a clock of
20MHz and report the HSPICE simulation results in Table
1. Even though the OWBR algorithm achieves the optimal
wiresizing solutions under the given driver sizing solutions,
the STIS formulation consistently outperforms CDWS: the
maximum delay is reduced by up to 17.7%, and more signif-
icantly, the total device area and the total power dissipation
are reduced by 57.4% and 61.7%, respectively. Although we
compute the optimal width for every transistor and every
10-m-long wire, the total runtime of the STIS algorithm is
just 7.18 seconds. Furthermore, we point out that our STIS
algorithm can be used to find even better sizing solutions
by trying different stage number, as we already observed
during our experiments.
2 The SDWS formulation in [8] is applicable only to single-source
nets.
Then, we use the STIS algorithm to solve the simultaneous
buffer and wire sizing (SBWS) problem. A spread spectrum
IF transceiver chip is designed recently [4] where the
1.2 -m 2-layer metal SCMOS technology is used. There are
two clock nets, named DCLK and CLK. Each uses a chain
of 4 cascade drivers in the clock signal source and chains
of 4 cascade buffers in order to drive long interconnects
and register files. All clock source drivers and buffers are
tuned manually in the original design. We retain the sizes
for both the first stage drivers and the input ports for the
register files, and apply the STIS algorithm to optimize the
sizes for every 0:6-m-long wire and every transistor in other
drivers/buffers. The STIS algorithm optimizes the two designs
in 61.24 and 120.79 seconds, respectively. We report
HSPICE simulation results in Table 2. When compared
with the original designs for the two clock nets, the STIS
designs reduce the maximum delay by 14.4% and 4.8%, re-
spectively, and more significantly, reduce the power consumption
by 24.2% and 42.8%, respectively. Moreover, we
compare our results with those in a recent work [9], where
the SBWS problem is studied based on the gate sizing formulation
and the step model for transistors. For compari-
son, both STIS and SBWS algorithms use same step model
in this experiment. The STIS algorithm achieves more delay
reduction under almost same power dissipation. Since
same model is used, the gain comes from the transistor sizing
formulation.
5.2. Area-Delay Trade-off for Transistor Sizing
In order to achieve the area-delay trade-off, we introduce
the following objective function:
It is the scaled weighted sum of area and delays, and fl
(0 - can be adjusted for area-delay trade-off. One
can easily verify that Eqn. (18) is still a CH-posynomial.
Again, we can apply the STIS algorithm efficiently.
We use the STIS algorithm to solve the transistor sizing
problem for area-delay trade-off 3 . We sized 8bit, 16bit
and ripple-adders, respectively, and report the total
device areas and the maximum delays in Table 3. We
still use parameters of MCNC 0:5-m CMOS technology,
and assume that each primary input to these adders comes
from a 2x inverter and each primary output drives a 2x
inverter. The STIS algorithm optimizes the 32bit adder
with 1,026 transistors in 66 seconds. A smooth delay-area
trade-off is observed and the maximum delay is reduced
by up to 30.8% with about 2x times area when compared
with the minimum-size design. We point out that these
adders are implemented in CMOS complex gates and we
simply assume that every transistor has the same timing
criticality and the same weight penalty. We plan to use
the Lagrangian relaxation method [3] to obtain the optimal
weight penalty assignment and study the impact of weight
penalty assignment. Comparison with previous transistor
sizing works [14, 18] is also planned. Besides, the area-delay
trade-off formulation can be easily extended for power-delay
trade-off.
6. CONCLUSIONS
The major contribution of this work is to reveal the dominance
property for all CH-posynomial programs and show
that the STIS problems under a number of delay models are
CH-posynomial programs. Based on the dominance prop-
erty, a polynomial time algorithm is proposed to compute
the lower and upper bounds of the optimal solution to CH-
posynomial programs. The algorithm often achieves identical
lower and upper bounds, which leads to the optimal solution
of the STIS problems. It is a near-optimal algorithm
in practice and is observed to achieve large delay and power
reductions when applied to real designs. Furthermore, the
algorithm is applicable to any optimization problem that
can be formulated as a CH-posynomial program.

ACKNOWLEDGMENTS

The authors would like to thank Professor C.-J. Richard Shi
at University of Iowa, Cheng-Kok Koh and Patrick Madden
at UCLA for their helpful discussions.



--R

"Gate Sizing in MOS Digital Circuits with Linear Programming"
"An Iterative Gate Sizing Approach with Accurate Delay Evaluation"
"Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation,"
"A 12.7Mchip/s All-Digital BPSK Direct Sequence Spread-Spectrum IF Transceiver in 1.2-m CMOS,"
"Timing and Area Optimization for Standard-Cell VLSI Circuit Design"
"Optimal Wiresizing for Interconnects with Multiple Sources"
"Simultaneous Transistor and Inter-connect Sizing Based on the General Dominance Prop- erty"
"Simulataneous Driver and Wire Sizing for Performance and Power Optimization"
"Simulataneous Buffer and Wire Sizing for Performance and Power Optimization"
"Performance- Driven Interconnect Design Based on Distributed RC Delay Model"
"Optimal Wiresizing Under the Distributed Elmore Delay Model"
"Performance Driven Routing with Multiple Sources,"
"Geometric Programming: Methods, Computations and Appicaltions"
"TILOS: A Psoynomial Programming Approach to Transistor Sizing"
"CMOS Circuit Speed and Buffer Optimization"
"Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model"
"RC Interconnect OptimizationUnder the Elmore Delay Model"
"An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization"
"A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing"
"Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimiza- tion,"
"A Switch-Level Timing Verifier for Digital MOS VLSI, "
"A Circuit Model for Predicting Transient Delays in LSI Logic Systems"
"RC Interconnect Synthesis - A Moment Fitting Approach"
"Signal Delay in RC Tree Networks"
"Post Routing Performance Optimization via Multi-Link Insertion and Non-Uniform Wire- sizing,"
--TR
Performance-driven interconnect design based on distributed RC delay model
RC interconnect synthesisMYAMPERSANDmdash;a moment fitting approach
Simultaneous driver and wire sizing for performance and power optimization
RC interconnect optimization under the Elmore delay model
Optimal wire sizing and buffer insertion for low power and a generalized delay model
A sequential quadratic programming approach to concurrent gate and wire sizing
An iterative gate sizing approach with accurate delay evaluation
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
Optimal wiresizing for interconnects with multiple sources
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Simultaneous buffer and wire sizing for performance and power optimization
Gate sizing in MOS digital circuits with linear programming

--CTR
Jason Cong , Lei He, An efficient technique for device and interconnect optimization in deep submicron designs, Proceedings of the 1998 international symposium on Physical design, p.45-51, April 06-08, 1998, Monterey, California, United States
Chris C. N. Chu , D. F. Wong, Greedy wire-sizing is linear time, Proceedings of the 1998 international symposium on Physical design, p.39-44, April 06-08, 1998, Monterey, California, United States
Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States
Chung-Ping Chen , Chris C. N. Chu , D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.617-624, November 08-12, 1998, San Jose, California, United States
Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
C. C. N. Chu , D. F. Wong, A polynomial time optimal algorithm for simultaneous buffer and wire sizing, Proceedings of the conference on Design, automation and test in Europe, p.479-487, February 23-26, 1998, Le Palais des Congrs de Paris, France
Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.478-511, Oct. 1996
Jason Cong , Lei He , Cheng-Kok Koh , Zhigang Pan, Global interconnect sizing and spacing with consideration of coupling capacitance, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.628-633, November 09-13, 1997, San Jose, California, United States
Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
STIS;driver/buffer;CH-posynomial programs;transistor sizing;circuit CAD;transistor and interconnect sizing;wire sizing problem