class_docstr: For verilog source code with preprocessor directives.
  
  .. versionadded:: 1.4
docstr: Verilog code will use one of reg/wire/assign for sure, and that
  is not common elsewhere.
code: def analyse_text(text):
      """Verilog code will use one of reg/wire/assign for sure, and that
      is not common elsewhere."""
      result = 0
      if "reg" in text:
          result += 0.1
      if "wire" in text:
          result += 0.1
      if "assign" in text:
          result += 0.1
  
      return result
  
file_path: catboost/contrib/python/Pygments/py3/pygments/lexers/hdl.py
imports: import re
  from pygments.lexer import RegexLexer, bygroups, include, using, this, words
  from pygments.token import Text, Comment, Operator, Keyword, Name, String, Number, Punctuation, Whitespace
label_desc: Use image node_id 1 for calling the VerilogLexer obj's underlying member method code with example usage: obj.analyse_text(text) and returns: result