title: Chip Design for Submicron VLSI: CMOS Layout and Simulation
author:  John P. Uyemura 
description: John P. Uyemura is Professor of Electrical and Computer Engineering, late of Georgia Institute of Technology.
zlib_text: SILICON PROCESSING FOR THE VLSI ERA
  Vol. 4 - Deep-Submicron Process Technology
  DETAILED TABLE OF CONTENTS
  PREFACE
  Chap. 1 - THE EVOLUTION OF THE STRUCTURE OF MOSFETS 1
  1.1 THE STRUCTURE OF DEEP-SUBMICRON MOSFETS:
  (0.25-^m to 0.13-^m) - COMPARED TO THE STRUCTURE OF
  “CONVENTIONAL” MOSFETS (2.0-^m to 0.5-^m) 
  2
  1.1.1 Evolution of the MOSFET Gate Stack and Contact Structure
  1.1.2 Gate Dielectric Materials in Deep-Submicron MOSFETs
  1.1.3 Doping-Concentration Profiles of the MOSFET Channel
  1.1.4 Evolution of the Drain Structure of MOSFETs
  1.2 DEEP-SUBMICRON CMOS STRUCTURES 10
  1.2.1 Substrate Issues for Deep-Submicron CMOS
  1.2.2 Well Formation in Deep-Submicron CMOS
  1.2.3 Dual-Doped Poly in Deep-Submicron CMOS
  1.2.4 Shallow Trench Isolation for Deep-Submicron CMOS
  1.2.5 Silicon-On-Insulator (SOI) Technology
  1.3 LIMITS TO CONVENTIONAL MOSFET SCALING 15
  REFERENCES 16
  Chap. 2 - 300-MM SILICON WAFERS 
  17
  2.1 300-mm SILICON CRYSTAL GROWTH 17
  2.2 GROWN-IN SILICON DEFECTS: 21
  CRYSTAL-ORIGINATED-PART