<fim-prefix> int UC_CPU_ARM_1176 = 5;
   public static final int UC_CPU_ARM_11MPCORE = 6;
   public static final int UC_CPU_ARM_CORTEX_M0 = 7;
   public static final int UC_CPU_ARM_CORTEX_M3 = 8;
   public static final int UC_CPU_ARM_CORTEX_M4 = 9;
   public static final int UC_CPU_ARM_CORTEX_M7 = 10;
   public static final int UC_CPU_ARM_CORTEX_M33 = 11;
   public static final int UC_CPU_ARM_CORTEX_R5 = 12;
   public static final int UC_CPU_ARM_CORTEX_R5F = 13;
   public static final int UC_CPU_ARM_CORTEX_A7 = 14;
   public static final int UC_CPU_ARM_CORTEX_A8 = 15;
   public static final int UC_CPU_ARM_CORTEX_A9 = 16;
   public static final int UC_CPU_ARM_CORTEX_A15 = 17;
   public static final int UC_CPU_ARM_TI925T = 18;
   public static final int UC_CPU_ARM_SA1100 = 19;
   public static final int UC_CPU_ARM_SA1110 = 20;
   public static final int UC_CPU_ARM_PXA250 = 21;
   public static final int UC_CPU_ARM_PXA255 = 22;
   public static final int UC_CPU_ARM_PXA260 = 23;
   public static final int UC_CPU_ARM_PXA261 = 24;
   public static final int UC_CPU_ARM_PXA262 = 25;
   public static final int UC_CPU_ARM_PXA270 = 26;
   public static final int UC_CPU_ARM_PXA270A0 = 27;
   public static final int UC_CPU_ARM_PXA270A1 = 28;
   public static final int UC_CPU_ARM_PXA270B0 = 29;
   public static final int UC_CPU_ARM_PXA270B1 = 30;
   public static final int UC_CPU_ARM_PXA270C0 = 31;
   public static final int UC_CPU_ARM_PXA270C5 = 32;
   public static final int UC_CPU_ARM_MAX = 33;
   // BUG: CWE-665 Improper Initialization
   // 
   // FIXED: 
<fim-middle>   public static final int UC_CPU_ARM_ENDING = 34;

// ARM registers

   public static final int UC_ARM_REG_INVALID = 0;
   public static final int UC_ARM_REG_APSR = 1;
   public static final int UC_AR<fix-suffix>M_REG_APSR_NZCV = 2;
   public static final int UC_ARM_REG_CPSR = 3;
   public static final int UC_ARM_REG_FPEXC = 4;
   public static final int UC_ARM_REG_FPINST = 5;
   public static final int UC_ARM_REG_FPSCR = 6;
   public static final int UC_ARM_REG_FPSCR_NZCV = 7;
   public static final int UC_ARM_REG_FPSID = 8;
   public static final int UC_ARM_REG_ITSTATE = 9;
   public static final int UC_ARM_REG_LR = 10;
   public static final int UC_ARM_REG_PC = 11;
   public static final int UC_ARM_REG_SP = 12;
   public static final int UC_ARM_REG_SPSR = 13;
   public static final int UC_ARM_REG_D0 = 14;
   public static final int UC_ARM_REG_D1 = 15;
   public static final int UC_ARM_REG_D2 = 16;
   public static final int UC_ARM_REG_D3 = 17;
   public static final int UC_ARM_REG_D4 = 18;
   public static final int UC_ARM_REG_D5 = 19;
   public static final int UC_ARM_REG_D6 = 20;
   public static final int UC_ARM_REG_D7 = 21;
   public static final int UC_ARM_REG_D8 = 22;
   public static<|endoftext|>