A battery charger designed in a single-inductor single-input dual-output architecture with charge balancing among battery cells will be introduced. Charge balancing methods to reduce the charging time and slow down the aging process of batteries will be discussed. An artificial neural network is proposed to detect the state of health (SOH) of battery cells and improve the accuracy of the state of charge (SOC) estimation. A prototype implemented in TSMC 0.35-μm process and TensorFlow tools will be used as a design example.
Tsung-Heng Tsai (Senior Member, IEEE) received the B.S. degree in control engineering from the National Chiao Tung University in 1994, the M.S. degree in electrical engineering from the University of Southern California in 1998, and the Ph.D. degree in electrical and computer engineering from the University of California at Davis in 2005. In 2005, he joined the Department of Electrical Engineering, National Chung Cheng University. Since 2022, he has been with the faculty of National Yang Ming Chiao Tung University, Hsinchu, Taiwan. Dr. Tsai has been a member of the Technical Program Committee of the IEEE Asian Solid-State Circuits Conference in 2014-2021. He was a recipient of the Yang Scholar Award from the National Chung Cheng University in 2017. He also serves as the IEEE Solid-State Circuit Society Tainan Chapter Chairperson for the term (2017-2020). His main research interests are in CMOS mixed-signal integrated-circuit designs for energy harvesting systems and microsensing systems.
Novel methods for frequency tracking are presented for referenceless clock and data recovery circuit applications. An approach based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. In order to minimize the loop delay and thereby improve the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly controlling the phase of the oscillator with the output signal of the phase detector. The design is all-digital, including digital filters that simplify the design. The CDR occupies an active area of 0.031 mm2, implemented in a 28-nm CMOS process. The receiver operates up to 12.5 Gb/s. The frequency locking time, measured as the time required for every 1-Gb/s change in the input data, is 320 ns. The power consumption is only 21.13 mW, corresponding to an energy efficiency of 2.11 pJ/bit.
Jinwook Burm received the B.S. degree in physics from Seoul National University, Seoul, Korea, M.S. degree in physics from the University of Michigan, Ann Arbor, and the Ph.D. degree in applied physics from Cornell University, Ithaca, NY. After postdoctoral works at Cornell University and Bell Labs, Lucent Technologies, Murray Hill, NJ, he joined the Department of Electronics Engineering at Sogang University, Seoul, Korea, as an Assistant Professor in 1998, where he is now a Professor. He also worked as a Principal Scientist at Pixelplus Semiconductor, Inc., in San Jose, CA, USA for one year starting in August 2006. He worked on millimeter wave ICs and high speed GaN transistors at Cornell, and high speed optoelectronic circuits at Bell Labs. At Sogang University, his current research interests include high speed interface circuits and CMOS implementation of various sensors.
Integrated sensor fusion system-on-chips require a high-accuracy low-latency analog-to-digital converter (ADC) to interface a wide input range signal and multiplex among multiple sensor channels. Incremental analog-to-digital converters (IADCs), by adding a simultaneous reset in analog modulators and digital filters, are Nyquist-rate ADCs which retain most advantages of the ΔΣ ADCs, and are much easier to be multiplexed with shorter latency and simpler digital filters.
In this talk, IADC operation will be reviewed. Hybrid IADC to continue the residue fine quantization to improve the energy efficiency will be discussed: (1) extended counting with a second SAR ADC, (2) hardware reusing to perform multi-slope counting, (3) two-step operation to boost up the noise shaping order, and (4) multi-stage multi-step operation to boost up the noise shaping order and extend the input range.
Chia-Hung Chen received his Ph.D. in Oregon State University, Corvallis, OR, in 2013. He is currently an assistant professor at Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. He has been serving as a member of the technical program committee (TPC) for the IEEE Custom Integrated Circuits Conference (CICC) since 2021 and VLSI Symposium on Technology, Systems and Automation (VLSI-TSA) since 2022. His research interests are in the design of precision analog circuits and energy-efficient data converters.