Add doxygen comments to xmmintrin.h's intrinsics.
Only half of the intrinsics in this file is documented here. The patch for the o
ther half will be sent out later.

The doxygen comments are automatically generated based on Sony's intrinsics docu
ment.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

git-svn-id: ffe668792ed300d6c2daa1f6eba2e0aa28d7ec6c@272121 91177308-0d34-0410-b5e6-96231b3b80d8

--- lib/Headers/xmmintrin.h
+++ lib/Headers/xmmintrin.h
@@ -1406,12 +1406,39 @@
   return (__m64)__builtin_ia32_cvttps2pi((__v4sf)__a);
 }

+/// \brief Converts two low-order float values in a 128-bit vector of [4 x
+///    float] into a 64-bit vector of [2 x i32], truncating the result when it
+///    is inexact.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTTPS2PI instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+/// \returns A 64-bit integer vector containing the converted values.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_cvtt_ps2pi(__m128 __a)
 {
   return _mm_cvttps_pi32(__a);
 }

+/// \brief Converts a 32-bit signed integer value into a floating point value
+///    and writes it to the lower 32 bits of the destination. The remaining
+///    higher order elements of the destination vector are copied from the
+///    corresponding elements in the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTSI2SS / CVTSI2SS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+/// \param __b
+///    A 32-bit signed integer operand containing the value to be converted.
+/// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the
+///    converted value of the second operand. The upper 96 bits are copied from
+///    the upper 96 bits of the first operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtsi32_ss(__m128 __a, int __b)
 {
@@ -1419,6 +1446,22 @@
   return __a;
 }

+/// \brief Converts a 32-bit signed integer value into a floating point value
+///    and writes it to the lower 32 bits of the destination. The remaining
+///    higher order elements of the destination are copied from the
+///    corresponding elements in the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTSI2SS / CVTSI2SS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+/// \param __b
+///    A 32-bit signed integer operand containing the value to be converted.
+/// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the
+///    converted value of the second operand. The upper 96 bits are copied from
+///    the upper 96 bits of the first operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvt_si2ss(__m128 __a, int __b)
 {
@@ -1427,6 +1470,22 @@

 #ifdef __x86_64__

+/// \brief Converts a 64-bit signed integer value into a floating point value
+///    and writes it to the lower 32 bits of the destination. The remaining
+///    higher order elements of the destination are copied from the
+///    corresponding elements in the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTSI2SS / CVTSI2SS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+/// \param __b
+///    A 64-bit signed integer operand containing the value to be converted.
+/// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the
+///    converted value of the second operand. The upper 96 bits are copied from
+///    the upper 96 bits of the first operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtsi64_ss(__m128 __a, long long __b)
 {
@@ -1436,24 +1495,84 @@

 #endif

+/// \brief Converts two elements of a 64-bit vector of [2 x i32] into two
+///    floating point values and writes them to the lower 64-bits of the
+///    destination. The remaining higher order elements of the destination are
+///    copied from the corresponding elements in the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+/// \param __b
+///    A 64-bit vector of [2 x i32]. The elements in this vector are converted
+///    and written to the corresponding low-order elements in the destination.
+/// \returns A 128-bit vector of [4 x float] whose lower 64 bits contain the
+///    converted value of the second operand. The upper 64 bits are copied from
+///    the upper 64 bits of the first operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtpi32_ps(__m128 __a, __m64 __b)
 {
   return __builtin_ia32_cvtpi2ps((__v4sf)__a, (__v2si)__b);
 }

+/// \brief Converts two elements of a 64-bit vector of [2 x i32] into two
+///    floating point values and writes them to the lower 64-bits of the
+///    destination. The remaining higher order elements of the destination are
+///    copied from the corresponding elements in the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+/// \param __b
+///    A 64-bit vector of [2 x i32]. The elements in this vector are converted
+///    and written to the corresponding low-order elements in the destination.
+/// \returns A 128-bit vector of [4 x float] whose lower 64 bits contain the
+///    converted value from the second operand. The upper 64 bits are copied
+///    from the upper 64 bits of the first operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvt_pi2ps(__m128 __a, __m64 __b)
 {
   return _mm_cvtpi32_ps(__a, __b);
 }

+/// \brief Extracts a float value contained in the lower 32 bits of a vector of
+///    [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
+///    used in the extraction.
+/// \returns A 32-bit float containing the extracted value.
 static __inline__ float __DEFAULT_FN_ATTRS
 _mm_cvtss_f32(__m128 __a)
 {
   return __a[0];
 }

+/// \brief Loads two packed float values from the address __p into the
+///     high-order bits of a 128-bit vector of [4 x float]. The low-order bits
+///     are copied from the low-order bits of the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVHPD / MOVHPD instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float]. Bits [63:0] are written to bits [63:0]
+///    of the destination.
+/// \param __p
+///    A pointer to two packed float values. Bits [63:0] are written to bits
+///    [127:64] of the destination.
+/// \returns A 128-bit vector of [4 x float] containing the moved values.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_loadh_pi(__m128 __a, const __m64 *__p)
 {
@@ -1466,6 +1585,21 @@
   return __builtin_shufflevector(__a, __bb, 0, 1, 4, 5);
 }

+/// \brief Loads two packed float values from the address __p into the low-order
+///    bits of a 128-bit vector of [4 x float]. The high-order bits are copied
+///    from the high-order bits of the first operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVLPD / MOVLPD instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float]. Bits [127:64] are written to bits
+///    [127:64] of the destination.
+/// \param __p
+///    A pointer to two packed float values. Bits [63:0] are written to bits
+///    [63:0] of the destination.
+/// \returns A 128-bit vector of [4 x float] containing the moved values.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_loadl_pi(__m128 __a, const __m64 *__p)
 {
@@ -1478,6 +1612,21 @@
   return __builtin_shufflevector(__a, __bb, 4, 5, 2, 3);
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float]. The lower
+///    32 bits of the vector are initialized with the single-precision
+///    floating-point value loaded from a specified memory location. The upper
+///    96 bits are set to zero.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction.
+///
+/// \param __p
+///    A pointer to a 32-bit memory location containing a single-precision
+///    floating-point value.
+/// \returns An initialized 128-bit floating-point vector of [4 x float]. The
+///    lower 32 bits contain the value loaded from the memory location. The
+///    upper 96 bits are set to zero.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_load_ss(const float *__p)
 {
@@ -1488,6 +1637,18 @@
   return (__m128){ __u, 0, 0, 0 };
 }

+/// \brief Loads a 32-bit float value and duplicates it to all four vector
+///    elements of a 128-bit vector of [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVSS / MOVSS + \c shuffling
+///    instruction.
+///
+/// \param __p
+///    A pointer to a float value to be loaded and duplicated.
+/// \returns A 128-bit vector of [4 x float] containing the loaded
+///    and duplicated values.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_load1_ps(const float *__p)
 {
@@ -1500,12 +1661,34 @@

 #define        _mm_load_ps1(p) _mm_load1_ps(p)

+/// \brief Loads a 128-bit floating-point vector of [4 x float] from an aligned
+///    memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location. The address of the memory
+///    location has to be 128-bit aligned.
+/// \returns A 128-bit vector of [4 x float] containing the loaded valus.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_load_ps(const float *__p)
 {
   return *(__m128*)__p;
 }

+/// \brief Loads a 128-bit floating-point vector of [4 x float] from an
+///    unaligned memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVUPS / MOVUPS instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location. The address of the memory
+///    location does not have to be aligned.
+/// \returns A 128-bit vector of [4 x float] containing the loaded values.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_loadu_ps(const float *__p)
 {
@@ -1515,6 +1698,19 @@
   return ((struct __loadu_ps*)__p)->__v;
 }

+/// \brief Loads four packed float values, in reverse order, from an aligned
+///    memory location to 32-bit elements in a 128-bit vector of [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS + \c shuffling
+///    instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location. The address of the memory
+///    location has to be 128-bit aligned.
+/// \returns A 128-bit vector of [4 x float] containing the moved values, loaded
+///    in reverse order.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_loadr_ps(const float *__p)
 {
@@ -1522,18 +1718,52 @@
   return __builtin_shufflevector((__v4sf)__a, (__v4sf)__a, 3, 2, 1, 0);
 }

+/// \brief Create a 128-bit vector of [4 x float] with undefined values.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic has no corresponding instruction.
+///
+/// \returns A 128-bit vector of [4 x float] containing undefined values.
+
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_undefined_ps()
 {
   return (__m128)__builtin_ia32_undef128();
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float]. The lower
+///    32 bits of the vector are initialized with the specified single-precision
+///    floating-point value. The upper 96 bits are set to zero.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction.
+///
+/// \param __w
+///    A single-precision floating-point value used to initialize the lower 32
+///    bits of the result.
+/// \returns An initialized 128-bit floating-point vector of [4 x float]. The
+///    lower 32 bits contain the value provided in the source operand. The
+///    upper 96 bits are set to zero.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_set_ss(float __w)
 {
   return (__m128){ __w, 0, 0, 0 };
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float], with each
+///    of the four single-precision floating-point vector elements set to the
+///    specified single-precision floating-point value.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction.
+///
+/// \param __w
+///    A single-precision floating-point value used to initialize each vector
+///    element of the result.
+/// \returns An initialized 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_set1_ps(float __w)
 {
@@ -1541,42 +1771,139 @@
 }

 /* Microsoft specific. */
+/// \brief Constructs a 128-bit floating-point vector of [4 x float], with each
+///    of the four single-precision floating-point vector elements set to the
+///    specified single-precision floating-point value.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction.
+///
+/// \param __w
+///    A single-precision floating-point value used to initialize each vector
+///    element of the result.
+/// \returns An initialized 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_set_ps1(float __w)
 {
     return _mm_set1_ps(__w);
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float]
+///    initialized with the specified single-precision floating-point values.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic is a utility function and does not correspond to a specific
+///    instruction.
+///
+/// \param __z
+///    A single-precision floating-point value used to initialize bits [127:96]
+///    of the result.
+/// \param __y
+///    A single-precision floating-point value used to initialize bits [95:64]
+///    of the result.
+/// \param __x
+///    A single-precision floating-point value used to initialize bits [63:32]
+///    of the result.
+/// \param __w
+///    A single-precision floating-point value used to initialize bits [31:0]
+///    of the result.
+/// \returns An initialized 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_set_ps(float __z, float __y, float __x, float __w)
 {
   return (__m128){ __w, __x, __y, __z };
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float],
+///    initialized in reverse order with the specified 32-bit single-precision
+///    float-point values.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic is a utility function and does not correspond to a specific
+///    instruction.
+///
+/// \param __z
+///    A single-precision floating-point value used to initialize bits [31:0]
+///    of the result.
+/// \param __y
+///    A single-precision floating-point value used to initialize bits [63:32]
+///    of the result.
+/// \param __x
+///    A single-precision floating-point value used to initialize bits [95:64]
+///    of the result.
+/// \param __w
+///    A single-precision floating-point value used to initialize bits [127:96]
+///    of the result.
+/// \returns An initialized 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_setr_ps(float __z, float __y, float __x, float __w)
 {
   return (__m128){ __z, __y, __x, __w };
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float] initialized
+///    to zero.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VXORPS / XORPS instruction.
+///
+/// \returns An initialized 128-bit floating-point vector of [4 x float] with
+///    all elements set to zero.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_setzero_ps(void)
 {
   return (__m128){ 0, 0, 0, 0 };
 }

+/// \brief Stores the upper 64 bits of a 128-bit vector of [4 x float] to a
+///    memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VPEXTRQ / MOVQ instruction.
+///
+/// \param __p
+///    A pointer to a 64-bit memory location.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the values to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_storeh_pi(__m64 *__p, __m128 __a)
 {
   __builtin_ia32_storehps((__v2si *)__p, (__v4sf)__a);
 }

+/// \brief Stores the lower 64 bits of a 128-bit vector of [4 x float] to a
+///     memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVLPS / MOVLPS instruction.
+///
+/// \param __p
+///    A pointer to a memory location that will receive the float values.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the values to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_storel_pi(__m64 *__p, __m128 __a)
 {
   __builtin_ia32_storelps((__v2si *)__p, (__v4sf)__a);
 }

+/// \brief Stores the lower 32 bits of a 128-bit vector of [4 x float] to a
+///     memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction.
+///
+/// \param __p
+///    A pointer to a 32-bit memory location.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the value to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_store_ss(float *__p, __m128 __a)
 {
@@ -1586,6 +1913,18 @@
   ((struct __mm_store_ss_struct*)__p)->__u = __a[0];
 }

+/// \brief Stores float values from a 128-bit vector of [4 x float] to an
+///    unaligned memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVUPS / MOVUPS instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location. The address of the memory
+///    location does not have to be aligned.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the values to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_storeu_ps(float *__p, __m128 __a)
 {
@@ -1595,12 +1934,38 @@
   ((struct __storeu_ps*)__p)->__v = __a;
 }

+/// \brief Stores the lower 32 bits of a 128-bit vector of [4 x float] into
+///    four contiguous elements in an aligned memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to \c VMOVAPS / MOVAPS + \c shuffling
+///    instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location.
+/// \param __a
+///    A 128-bit vector of [4 x float] whose lower 32 bits are stored to each
+///    of the four contiguous elements pointed by __p.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_store_ps(float *__p, __m128 __a)
 {
   *(__m128*)__p = __a;
 }

+/// \brief Stores the lower 32 bits of a 128-bit vector of [4 x float] into
+///    four contiguous elements in an aligned memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to \c VMOVAPS / MOVAPS + \c shuffling
+///    instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location.
+/// \param __a
+///    A 128-bit vector of [4 x float] whose lower 32 bits are stored to each
+///    of the four contiguous elements pointed by __p.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_store1_ps(float *__p, __m128 __a)
 {
@@ -1608,12 +1973,37 @@
   _mm_store_ps(__p, __a);
 }

+/// \brief Stores float values from a 128-bit vector of [4 x float] to an
+///    aligned memory location.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location. The address of the memory
+///    location has to be 128-bit aligned.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the values to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_store_ps1(float *__p, __m128 __a)
 {
   return _mm_store1_ps(__p, __a);
 }

+/// \brief Stores float values from a 128-bit vector of [4 x float] to an
+///    aligned memory location in reverse order.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVAPS / MOVAPS + \c shuffling
+///    instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit memory location. The address of the memory
+///    location has to be 128-bit aligned.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the values to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_storer_ps(float *__p, __m128 __a)
 {
@@ -1630,27 +2020,100 @@
 /* FIXME: We have to #define this because "sel" must be a constant integer, and
    Sema doesn't do any form of constant propagation yet. */

+/// \brief Loads one cache line of data from the specified address to a location
+///    closer to the processor.
+///
+/// \headerfile <x86intrin.h>
+///
+/// \code
+/// void _mm_prefetch(const void * a, const int sel);
+/// \endcode
+///
+/// This intrinsic corresponds to the \c PREFETCHNTA instruction.
+///
+/// \param a
+///    A pointer to a memory location containing a cache line of data.
+/// \param sel
+///    A predefined integer constant specifying the type of prefetch operation:
+///    _MM_HINT_NTA: Move data using the non-temporal access (NTA) hint.
+///    The PREFETCHNTA instruction will be generated.
+///    _MM_HINT_T0: Move data using the T0 hint. The PREFETCHT0 instruction will
+///    be generated.
+///    _MM_HINT_T1: Move data using the T1 hint. The PREFETCHT1 instruction will
+///    be generated.
+///    _MM_HINT_T2: Move data using the T2 hint. The PREFETCHT2 instruction will
+///    be generated.
 #define _mm_prefetch(a, sel) (__builtin_prefetch((void *)(a), 0, (sel)))
 #endif

+/// \brief Stores a 64-bit integer in the specified aligned memory location. To
+///    minimize caching, the data is flagged as non-temporal (unlikely to be
+///    used again soon).
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c MOVNTQ instruction.
+///
+/// \param __p
+///    A pointer to an aligned memory location used to store the register value.
+/// \param __a
+///    A 64-bit integer containing the value to be stored.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_stream_pi(__m64 *__p, __m64 __a)
 {
   __builtin_ia32_movntq(__p, __a);
 }

+/// \brief Moves packed float values from a 128-bit vector of [4 x float] to a
+///    128-bit aligned memory location. To minimize caching, the data is flagged
+///    as non-temporal (unlikely to be used again soon).
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVNTPS / MOVNTPS instruction.
+///
+/// \param __p
+///    A pointer to a 128-bit aligned memory location that will receive the
+///    integer values.
+/// \param __a
+///    A 128-bit vector of [4 x float] containing the values to be moved.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_stream_ps(float *__p, __m128 __a)
 {
   __builtin_ia32_movntps(__p, (__v4sf)__a);
 }

+/// \brief Forces strong memory ordering (serialization) between store
+///    instructions preceding this instruction and store instructions following
+///    this instruction, ensuring the system completes all previous stores
+///    before executing subsequent stores.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c SFENCE instruction.
+///
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_sfence(void)
 {
   __builtin_ia32_sfence();
 }

+/// \brief Extracts 16-bit element from a 64-bit vector of [4 x i16] and
+///    returns it, as specified by the immediate integer operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VPEXTRW / PEXTRW instruction.
+///
+/// \param __a
+///    A 64-bit vector of [4 x i16].
+/// \param __n
+///    An immediate integer operand that determines which bits are extracted:
+///    0: Bits [15:0] are copied to the destination.
+///    1: Bits [31:16] are copied to the destination.
+///    2: Bits [47:32] are copied to the destination.
+///    3: Bits [63:48] are copied to the destination.
+/// \returns A 16-bit integer containing the extracted 16 bits of packed data.
 static __inline__ int __DEFAULT_FN_ATTRS
 _mm_extract_pi16(__m64 __a, int __n)
 {
@@ -1658,6 +2121,30 @@
   return (unsigned short)__b[__n & 3];
 }

+/// \brief Copies data from the 64-bit vector of [4 x i16] to the destination,
+///    and inserts the lower 16-bits of an integer operand at the 16-bit offset
+///    specified by the immediate operand __n.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VPINSRW / PINSRW instruction.
+///
+/// \param __a
+///    A 64-bit vector of [4 x i16].
+/// \param __d
+///    An integer. The lower 16-bit value from this operand is written to the
+///    destination at the offset specified by operand __n.
+/// \param __n
+///    An immediate integer operant that determines which the bits to be used
+///    in the destination.
+///    0: Bits [15:0] are copied to the destination.
+///    1: Bits [31:16] are copied to the destination.
+///    2: Bits [47:32] are copied to the destination.
+///    3: Bits [63:48] are copied to the destination.
+///    The remaining bits in the destination are copied from the corresponding
+///    bits in operand __a.
+/// \returns A 64-bit integer vector containing the copied packed data from the
+///    operands.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_insert_pi16(__m64 __a, int __d, int __n)
 {
@@ -1666,117 +2153,474 @@
    return (__m64)__b;
 }

+/// \brief Compares each of the corresponding packed 16-bit integer values of
+///    the 64-bit integer vectors, and writes the greater value to the
+///    corresponding bits in the destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PMAXSW instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the comparison results.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_max_pi16(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pmaxsw((__v4hi)__a, (__v4hi)__b);
 }

+/// \brief Compares each of the corresponding packed 8-bit unsigned integer
+///    values of the 64-bit integer vectors, and writes the greater value to the
+///    corresponding bits in the destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PMAXUB instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the comparison results.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_max_pu8(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pmaxub((__v8qi)__a, (__v8qi)__b);
 }

+/// \brief Compares each of the corresponding packed 16-bit integer values of
+///    the 64-bit integer vectors, and writes the lesser value to the
+///    corresponding bits in the destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PMINSW instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the comparison results.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_min_pi16(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pminsw((__v4hi)__a, (__v4hi)__b);
 }

+/// \brief Compares each of the corresponding packed 8-bit unsigned integer
+///    values of the 64-bit integer vectors, and writes the lesser value to the
+///    corresponding bits in the destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PMINUB instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the comparison results.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_min_pu8(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pminub((__v8qi)__a, (__v8qi)__b);
 }

+/// \brief Takes the most significant bit from each 8-bit element in a 64-bit
+///    integer vector to create a 16-bit mask value. Zero-extends the value to
+///    32-bit integer and writes it to the destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PMOVMSKB instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing the values with bits to be extracted.
+/// \returns The most significant bit from each 8-bit element in the operand,
+///    written to bits [15:0].
 static __inline__ int __DEFAULT_FN_ATTRS
 _mm_movemask_pi8(__m64 __a)
 {
   return __builtin_ia32_pmovmskb((__v8qi)__a);
 }

+/// \brief Multiplies packed 16-bit unsigned integer values and writes the
+///    high-order 16 bits of each 32-bit product to the corresponding bits in
+///    the destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PMULHUW instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the products of both operands.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_mulhi_pu16(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pmulhuw((__v4hi)__a, (__v4hi)__b);
 }

+/// \brief Shuffles the 4 16-bit integers from a 64-bit integer vector to the
+///    destination, as specified by the immediate value operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PSHUFW instruction.
+///
+/// \code
+/// __m64 _mm_shuffle_pi16(__m64 a, const int n);
+/// \endcode
+///
+/// \param a
+///    A 64-bit integer vector containing the values to be shuffled.
+/// \param n
+///    An immediate value containing an 8-bit value specifying which elements to
+///    copy from a. The destinations within the 64-bit destination are assigned
+///    values as follows:
+///    Bits [1:0] are used to assign values to bits [15:0] in the destination.
+///    Bits [3:2] are used to assign values to bits [31:16] in the destination.
+///    Bits [5:4] are used to assign values to bits [47:32] in the destination.
+///    Bits [7:6] are used to assign values to bits [63:48] in the destination.
+///    Bit value assignments:
+///    00: assigned from bits [15:0] of a.
+///    01: assigned from bits [31:16] of a.
+///    10: assigned from bits [47:32] of a.
+///    11: assigned from bits [63:48] of a.
+/// \returns A 64-bit integer vector containing the shuffled values.
 #define _mm_shuffle_pi16(a, n) __extension__ ({ \
   (__m64)__builtin_ia32_pshufw((__v4hi)(__m64)(a), (n)); })

+/// \brief Conditionally copies the values from each 8-bit element in the first
+///    64-bit integer vector operand to the specified memory location, as
+///    specified by the most significant bit in the corresponding element in the
+///    second 64-bit integer vector operand. To minimize caching, the data is
+///    flagged as non-temporal (unlikely to be used again soon).
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c MASKMOVQ instruction.
+///
+/// \param __d
+///    A 64-bit integer vector containing the values with elements to be copied.
+/// \param __n
+///    A 64-bit integer vector operand. The most significant bit from each 8-bit
+///    element determines whether the corresponding element in operand __d is
+///    copied. If the most significant bit of a given element is 1, the
+///    corresponding element in operand __d is copied.
+/// \param __p
+///    A pointer to a 64-bit memory location that will receive the conditionally
+///    copied integer values. The address of the memory location does not have
+///    to be aligned.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_maskmove_si64(__m64 __d, __m64 __n, char *__p)
 {
   __builtin_ia32_maskmovq((__v8qi)__d, (__v8qi)__n, __p);
 }

+/// \brief Computes the rounded averages of the packed unsigned 8-bit integer
+///    values and writes the averages to the corresponding bits in the
+///    destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PAVGB instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the averages of both operands.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_avg_pu8(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pavgb((__v8qi)__a, (__v8qi)__b);
 }

+/// \brief Computes the rounded averages of the packed unsigned 16-bit integer
+///    values and writes the averages to the corresponding bits in the
+///    destination.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PAVGW instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector containing the averages of both operands.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_avg_pu16(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_pavgw((__v4hi)__a, (__v4hi)__b);
 }

+/// \brief Subtracts the corresponding 8-bit unsigned integer values of the two
+///    64-bit vector operands and computes the absolute value for each of the
+///    difference. Then sum of the 8 absolute differences is written to the
+///    bits [15:0] of the destination; the remaining bits [63:16] are cleared.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c PSADBW instruction.
+///
+/// \param __a
+///    A 64-bit integer vector containing one of the source operands.
+/// \param __b
+///    A 64-bit integer vector containing one of the source operands.
+/// \returns A 64-bit integer vector whose lower 16 bits contain the sums of the
+///    sets of absolute differences between both operands. The upper bits are
+///    cleared.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_sad_pu8(__m64 __a, __m64 __b)
 {
   return (__m64)__builtin_ia32_psadbw((__v8qi)__a, (__v8qi)__b);
 }

+/// \brief Returns the contents of the MXCSR register as a 32-bit unsigned
+///    integer value. There are several groups of macros associated with this
+///    intrinsic, including:
+///    * For checking exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO,
+///      _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW,
+///      _MM_EXCEPT_INEXACT. There is a convenience wrapper
+///      _MM_GET_EXCEPTION_STATE().
+///    * For checking exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW,
+///      _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_INEXACT.
+///      There is a convenience wrapper _MM_GET_EXCEPTION_MASK().
+///    * For checking rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN,
+///      _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO. There is a convenience wrapper
+///      _MM_GET_ROUNDING_MODE(x) where x is one of these macros.
+///    * For checking flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF.
+///      There is a convenience wrapper _MM_GET_FLUSH_ZERO_MODE().
+///    * For checking denormals-are-zero mode: _MM_DENORMALS_ZERO_ON,
+///      _MM_DENORMALS_ZERO_OFF. There is a convenience wrapper
+///      _MM_GET_DENORMALS_ZERO_MODE().
+///
+///    For example, the expression below checks if an overflow exception has
+///    occurred:
+///      ( _mm_getcsr() & _MM_EXCEPT_OVERFLOW )
+///
+///    The following example gets the current rounding mode:
+///      _MM_GET_ROUNDING_MODE()
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VSTMXCSR / STMXCSR instruction.
+///
+/// \returns A 32-bit unsigned integer containing the contents of the MXCSR
+///    register.
 static __inline__ unsigned int __DEFAULT_FN_ATTRS
 _mm_getcsr(void)
 {
   return __builtin_ia32_stmxcsr();
 }

+/// \brief Sets the MXCSR register with the 32-bit unsigned integer value. There
+///    are several groups of macros associated with this intrinsic, including:
+///    * For setting exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO,
+///      _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW,
+///      _MM_EXCEPT_INEXACT. There is a convenience wrapper
+///      _MM_SET_EXCEPTION_STATE(x) where x is one of these macros.
+///    * For setting exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW,
+///      _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_INEXACT.
+///      There is a convenience wrapper _MM_SET_EXCEPTION_MASK(x) where x is one
+///      of these macros.
+///    * For setting rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN,
+///      _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO. There is a convenience wrapper
+///      _MM_SET_ROUNDING_MODE(x) where x is one of these macros.
+///    * For setting flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF.
+///      There is a convenience wrapper _MM_SET_FLUSH_ZERO_MODE(x) where x is
+///      one of these macros.
+///    * For setting denormals-are-zero mode: _MM_DENORMALS_ZERO_ON,
+///      _MM_DENORMALS_ZERO_OFF. There is a convenience wrapper
+///      _MM_SET_DENORMALS_ZERO_MODE(x) where x is one of these macros.
+///
+///    For example, the following expression causes subsequent floating-point
+///    operations to round up:
+///      _mm_setcsr(_mm_getcsr() | _MM_ROUND_UP)
+///
+///    The following example sets the DAZ and FTZ flags:
+///      void setFlags() {
+///        _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON)
+///        _MM_SET_DENORMALS_ZERO_MODE(_MM_DENORMALS_ZERO_ON)
+///      }
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VLDMXCSR / LDMXCSR instruction.
+///
+/// \param __i
+///    A 32-bit unsigned integer value to be written to the MXCSR register.
 static __inline__ void __DEFAULT_FN_ATTRS
 _mm_setcsr(unsigned int __i)
 {
   __builtin_ia32_ldmxcsr(__i);
 }

+/// \brief Selects 4 float values from the 128-bit operands of [4 x float], as
+///    specified by the immediate value operand.
+///
+/// \headerfile <x86intrin.h>
+///
+/// \code
+/// __m128 _mm_shuffle_ps(__m128 a, __m128 b, const int mask);
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHUFPS / SHUFPS instruction.
+///
+/// \param a
+///    A 128-bit vector of [4 x float].
+/// \param b
+///    A 128-bit vector of [4 x float].
+/// \param mask
+///    An immediate value containing an 8-bit value specifying which elements to
+///    copy from a and b.
+///    Bits [3:0] specify the values copied from operand a.
+///    Bits [7:4] specify the values copied from operand b. The destinations
+///    within the 128-bit destination are assigned values as follows:
+///    Bits [1:0] are used to assign values to bits [31:0] in the destination.
+///    Bits [3:2] are used to assign values to bits [63:32] in the destination.
+///    Bits [5:4] are used to assign values to bits [95:64] in the destination.
+///    Bits [7:6] are used to assign values to bits [127:96] in the destination.
+///    Bit value assignments:
+///    00: Bits [31:0] copied from the specified operand.
+///    01: Bits [63:32] copied from the specified operand.
+///    10: Bits [95:64] copied from the specified operand.
+///    11: Bits [127:96] copied from the specified operand.
+/// \returns A 128-bit vector of [4 x float] containing the shuffled values.
 #define _mm_shuffle_ps(a, b, mask) __extension__ ({ \
   (__m128)__builtin_shufflevector((__v4sf)(__m128)(a), (__v4sf)(__m128)(b), \
                                   (mask) & 0x3, ((mask) & 0xc) >> 2, \
                                   (((mask) & 0x30) >> 4) + 4, \
                                   (((mask) & 0xc0) >> 6) + 4); })

+/// \brief Unpacks the high-order (index 2,3) values from two 128-bit vectors of
+///    [4 x float] and interleaves them into a 128-bit vector of [4 x
+///    float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VUNPCKHPS / UNPCKHPS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+///    Bits [95:64] are written to bits [31:0] of the destination.
+///    Bits [127:96] are written to bits [95:64] of the destination.
+/// \param __b
+///    A 128-bit vector of [4 x float].
+///    Bits [95:64] are written to bits [63:32] of the destination.
+///    Bits [127:96] are written to bits [127:96] of the destination.
+/// \returns A 128-bit vector of [4 x float] containing the interleaved values.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_unpackhi_ps(__m128 __a, __m128 __b)
 {
   return __builtin_shufflevector((__v4sf)__a, (__v4sf)__b, 2, 6, 3, 7);
 }

+/// \brief Unpacks the low-order (index 0,1) values from two 128-bit vectors of
+///    [4 x float] and interleaves them into a 128-bit vector of [4 x
+///    float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VUNPCKLPS / UNPCKLPS instruction.
+///
+/// \param __a
+///    A 128-bit vector of [4 x float].
+///    Bits [31:0] are written to bits [31:0] of the destination.
+///    Bits [63:32] are written to bits [95:64] of the destination.
+/// \param __b
+///    A 128-bit vector of [4 x float].
+///    Bits [31:0] are written to bits [63:32] of the destination.
+///    Bits [63:32] are written to bits [127:96] of the destination.
+/// \returns A 128-bit vector of [4 x float] containing the interleaved values.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_unpacklo_ps(__m128 __a, __m128 __b)
 {
   return __builtin_shufflevector((__v4sf)__a, (__v4sf)__b, 0, 4, 1, 5);
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float]. The lower
+///    32 bits are set to the lower 32 bits of the second parameter. The upper
+///    96 bits are set to the upper 96 bits of the first parameter.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVSS / MOVSS instruction.
+///
+/// \param __a
+///    A 128-bit floating-point vector of [4 x float]. The upper 96 bits are
+///    written to the upper 96 bits of the result.
+/// \param __b
+///    A 128-bit floating-point vector of [4 x float]. The lower 32 bits are
+///    written to the lower 32 bits of the result.
+/// \returns A 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_move_ss(__m128 __a, __m128 __b)
 {
   return __builtin_shufflevector((__v4sf)__a, (__v4sf)__b, 4, 1, 2, 3);
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float]. The lower
+///    64 bits are set to the upper 64 bits of the second parameter. The upper
+///    64 bits are set to the upper 64 bits of the first parameter.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VUNPCKHPD / UNPCKHPD instruction.
+///
+/// \param __a
+///    A 128-bit floating-point vector of [4 x float]. The upper 64 bits are
+///    written to the upper 64 bits of the result.
+/// \param __b
+///    A 128-bit floating-point vector of [4 x float]. The upper 64 bits are
+///    written to the lower 64 bits of the result.
+/// \returns A 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_movehl_ps(__m128 __a, __m128 __b)
 {
   return __builtin_shufflevector((__v4sf)__a, (__v4sf)__b, 6, 7, 2, 3);
 }

+/// \brief Constructs a 128-bit floating-point vector of [4 x float]. The lower
+///    64 bits are set to the lower 64 bits of the first parameter. The upper
+///    64 bits are set to the lower 64 bits of the second parameter.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VUNPCKLPD / UNPCKLPD instruction.
+///
+/// \param __a
+///    A 128-bit floating-point vector of [4 x float]. The lower 64 bits are
+///    written to the lower 64 bits of the result.
+/// \param __b
+///    A 128-bit floating-point vector of [4 x float]. The lower 64 bits are
+///    written to the upper 64 bits of the result.
+/// \returns A 128-bit floating-point vector of [4 x float].
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_movelh_ps(__m128 __a, __m128 __b)
 {
   return __builtin_shufflevector((__v4sf)__a, (__v4sf)__b, 0, 1, 4, 5);
 }

+/// \brief Converts a 64-bit vector of [4 x i16] into a 128-bit vector of [4 x
+///    float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction.
+///
+/// \param __a
+///    A 64-bit vector of [4 x i16]. The elements of the destination are copied
+///    from the corresponding elements in this operand.
+/// \returns A 128-bit vector of [4 x float] containing the copied and converted
+///    values from the operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtpi16_ps(__m64 __a)
 {
@@ -1795,6 +2639,18 @@
   return __r;
 }

+/// \brief Converts a 64-bit vector of 16-bit unsigned integer values into a
+///    128-bit vector of [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction.
+///
+/// \param __a
+///    A 64-bit vector of 16-bit unsigned integer values. The elements of the
+///    destination are copied from the corresponding elements in this operand.
+/// \returns A 128-bit vector of [4 x float] containing the copied and converted
+///    values from the operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtpu16_ps(__m64 __a)
 {
@@ -1812,6 +2668,18 @@
   return __r;
 }

+/// \brief Converts the lower four 8-bit values from a 64-bit vector of [8 x i8]
+///    into a 128-bit vector of [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction.
+///
+/// \param __a
+///    A 64-bit vector of [8 x i8]. The elements of the destination are copied
+///    from the corresponding lower 4 elements in this operand.
+/// \returns A 128-bit vector of [4 x float] containing the copied and converted
+///    values from the operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtpi8_ps(__m64 __a)
 {
@@ -1824,6 +2692,19 @@
   return _mm_cvtpi16_ps(__b);
 }

+/// \brief Converts the lower four unsigned 8-bit integer values from a 64-bit
+///    vector of [8 x u8] into a 128-bit vector of [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction.
+///
+/// \param __a
+///    A 64-bit vector of unsigned 8-bit integer values. The elements of the
+///    destination are copied from the corresponding lower 4 elements in this
+///    operand.
+/// \returns A 128-bit vector of [4 x float] containing the copied and converted
+///    values from the source operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtpu8_ps(__m64 __a)
 {
@@ -1835,6 +2716,22 @@
   return _mm_cvtpi16_ps(__b);
 }

+/// \brief Converts the two 32-bit signed integer values from each 64-bit vector
+///    operand of [2 x i32] into a 128-bit vector of [4 x float].
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPI2PS + \c COMPOSITE instruction.
+///
+/// \param __a
+///    A 64-bit vector of [2 x i32]. The lower elements of the destination are
+///    copied from the elements in this operand.
+/// \param __b
+///    A 64-bit vector of [2 x i32]. The upper elements of the destination are
+///    copied from the elements in this operand.
+/// \returns A 128-bit vector of [4 x float] whose lower 64 bits contain the
+///    copied and converted values from the first operand. The upper 64 bits
+///    contain the copied and converted values from the second operand.
 static __inline__ __m128 __DEFAULT_FN_ATTRS
 _mm_cvtpi32x2_ps(__m64 __a, __m64 __b)
 {
@@ -1847,6 +2744,22 @@
   return _mm_cvtpi32_ps(__c, __a);
 }

+/// \brief Converts each single-precision floating-point element of a 128-bit
+///    floating-point vector of [4 x float] into a 16-bit signed integer, and
+///    packs the results into a 64-bit integer vector of [4 x i16]. If the
+///    floating-point element is NaN or infinity, or if the floating-point
+///    element is greater than 0x7FFFFFFF or less than -0x8000, it is converted
+///    to 0x8000. Otherwise if the floating-point element is greater
+///    than 0x7FFF, it is converted to 0x7FFF.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPS2PI + \c COMPOSITE instruction.
+///
+/// \param __a
+///    A 128-bit floating-point vector of [4 x float].
+/// \returns A 64-bit integer vector of [4 x i16] containing the converted
+///    values.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_cvtps_pi16(__m128 __a)
 {
@@ -1859,6 +2772,23 @@
   return _mm_packs_pi32(__b, __c);
 }

+/// \brief Converts each single-precision floating-point element of a 128-bit
+///    floating-point vector of [4 x float] into an 8-bit signed integer, and
+///    packs the results into the lower 32 bits of a 64-bit integer vector of
+///    [8 x i8]. The upper 32 bits of the vector are set to 0. If the
+///    floating-point element is NaN or infinity, or if the floating-point
+///    element is greater than 0x7FFFFFFF or less than -0x80, it is converted
+///    to 0x80. Otherwise if the floating-point element is greater
+///    than 0x7F, it is converted to 0x7F.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c CVTPS2PI + \c COMPOSITE instruction.
+///
+/// \param __a
+///    128-bit floating-point vector of [4 x float].
+/// \returns A 64-bit integer vector of [8 x i8]. The lower 32 bits contain the
+///    converted values and the uppper 32 bits are set to zero.
 static __inline__ __m64 __DEFAULT_FN_ATTRS
 _mm_cvtps_pi8(__m128 __a)
 {
@@ -1870,6 +2800,20 @@
   return _mm_packs_pi16(__b, __c);
 }

+/// \brief Extracts the sign bits from each single-precision floating-point
+///    element of a 128-bit floating-point vector of [4 x float] and returns the
+///    sign bits in bits [0:3] of the result. Bits [31:4] of the result are set
+///    to zero.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c VMOVMSKPS / MOVMSKPS instruction.
+///
+/// \param __a
+///    A 128-bit floating-point vector of [4 x float].
+/// \returns A 32-bit integer value. Bits [3:0] contain the sign bits from each
+///    single-precision floating-point element of the parameter. Bits [31:4] are
+///    set to zero.
 static __inline__ int __DEFAULT_FN_ATTRS
 _mm_movemask_ps(__m128 __a)
 {


stdbool.c

stdbool.c

--- tests/stdbool.c
+++ tests/stdbool.c
@@ -1,18 +1,52 @@
 #include <stdio.h>
 #include <stdbool.h>
+#include "tests.h"

 int main()
 {
+    plan(6);
+
     bool trueBool = true;
     bool falseBool = false;

+    is_true(trueBool);
+    is_false(falseBool);
+
     if (trueBool)
     {
-        printf("true bool\n");
+        pass("%s", "true")
+    }
+    else
+    {
+        fail("%s", "should not reach here")
+    }
+
+    if (!trueBool)
+    {
+        fail("%s", "should not reach here")
+    }
+    else
+    {
+        pass("%s", "true")
+    }
+
+    if (falseBool)
+    {
+        fail("%s", "should not reach here")
+    }
+    else
+    {
+        pass("%s", "false")
     }

     if (!falseBool)
     {
-        printf("reversed false bool\n");
+        pass("%s", "false")
     }
+    else
+    {
+        fail("%s", "should not reach here")
+    }
+
+    done_testing();
 }


The sparse version now, let's start with psi computation

--- src/wapiti.c
+++ src/wapiti.c
@@ -2624,6 +2624,72 @@
 	xvm_expma((double *)psi, (double *)psi, 0.0, (size_t)T * Y * Y);
 }

+/* grd_spdopsi:
+ *  For the sparse version, we keep the two sum separate so we will have
+ *  separate Ψ_t(y,x) and Ψ_t(y',y,x). The first one define a vector for unigram
+ *  at each position, and the second one a matrix for bigrams.  This is where
+ *  the trick is as we will store Ψ_t(y',y,x) - 1. If the sum is nul, his
+ *  exponential will be 1.0 and so we have to store 0.0.  As most of the sum are
+ *  expected to be nul the resulting matrix will be very sparse and we will save
+ *  computation in the forward-backward.
+ *
+ *  So we compute Ψ differently here
+ *    1/ we sum the unigrams features weights by looping over actives
+ *         unigrams observations and store them in |psiuni|.
+ *    2/ we sum the bigrams features weights by looping over actives
+ *         bigrams observations (we don't have to do this for t=0 since
+ *         there is no bigrams here) and we store the non-nul one in the
+ *         sparse matrix.
+ *    3/ we take the component-wise exponential of the unigrams vectors,
+ *         and the component-wise exponential of the sparse matrix minus
+ *         one. (here also this can be done efficiently with vector
+ *         maths)
+ */
+static void grd_spdopsi(grd_t *grd, const seq_t *seq) {
+	const mdl_t *mdl = grd->mdl;
+	const double *x = mdl->theta;
+	const size_t  Y = mdl->nlbl;
+	const int     T = seq->len;
+	double (*psiuni)[T][Y] = (void *)grd->psiuni;
+	double  *psival        =         grd->psi;
+	size_t  *psiyp         =         grd->psiyp;
+	size_t (*psiidx)[T][Y] = (void *)grd->psiidx;
+	size_t  *psioff        =         grd->psioff;
+	for (int t = 0; t < T; t++) {
+		const pos_t *pos = &(seq->pos[t]);
+		for (size_t y = 0; y < Y; y++) {
+			double sum = 0.0;
+			for (size_t n = 0; n < pos->ucnt; n++) {
+				const size_t o = pos->uobs[n];
+				sum += x[mdl->uoff[o] + y];
+			}
+			(*psiuni)[t][y] = sum;
+		}
+	}
+	size_t off = 0;
+	for (int t = 1; t < T; t++) {
+		const pos_t *pos = &(seq->pos[t]);
+		psioff[t] = off;
+		for (size_t y = 0, nnz = 0; y < Y; y++) {
+			for (size_t yp = 0; yp < Y; yp++) {
+				double sum = 0.0;
+				for (size_t n = 0; n < pos->bcnt; n++) {
+					const size_t o = pos->bobs[n];
+					sum += x[mdl->boff[o] + yp * Y + y];
+				}
+				if (sum == 0.0)
+					continue;
+				psiyp [off] = yp;
+				psival[off] = sum;
+				nnz++, off++;
+			}
+			(*psiidx)[t][y] = nnz;
+		}
+	}
+	xvm_expma((double *)psiuni, (double *)psiuni, 0.0, (size_t)T * Y);
+	xvm_expma((double *)psival, (double *)psival, 1.0, off);
+}
+
 /* grd_flfwdbwd:
  *  Now, we go to the forward-backward algorithm. As this part of the code rely
  *  on a lot of recursive sums and products of exponentials, we have to take
@@ -2848,83 +2914,19 @@
 	const double *x = mdl->theta;
 	const size_t  Y = mdl->nlbl;
 	const int     T = seq->len;
-	double (*psiuni)[T][Y] = (void *)grd->psiuni;
-	double  *psival        =         grd->psi;
-	size_t  *psiyp         =         grd->psiyp;
-	size_t (*psiidx)[T][Y] = (void *)grd->psiidx;
-	size_t  *psioff        =         grd->psioff;
-	double (*alpha)[T][Y]  = (void *)grd->alpha;
-	double (*beta )[T][Y]  = (void *)grd->beta;
-	double  *scale         =         grd->scale;
-	double  *uz            =         grd->unorm;
-	double  *bz            =         grd->bnorm;
-	// We first have to compute the Ψ_t(y',y,x) weights defined as
-	//   Ψ_t(y',y,x) = \exp( ∑_k θ_k f_k(y',y,x_t) )
-	// So at position 't' in the sequence, for each couple (y',y) we have
-	// to sum weights of all features.
-	//
-	// Only the observations present at this position will have a non-nul
-	// weight so we can sum only on thoses.
-	//
-	// As we use only two kind of features: unigram and bigram, we can
-	// rewrite this as
-	//   \exp (  ∑_k μ_k(y, x_t)     f_k(y, x_t)
-	//         + ∑_k λ_k(y', y, x_t) f_k(y', y, x_t) )
-	// Where the first sum is over the unigrams features and the second is
-	// over bigrams ones.
-	//
-	// For the sparse version, we keep the two sum separate so we will have
-	// separate Ψ_t(y,x) and Ψ_t(y',y,x). The first one define a vector for
-	// unigram at each position, and the second one a matrix for bigrams.
-	// This is where the trick is as we will store Ψ_t(y',y,x) - 1. If the
-	// sum is nul, his exponential will be 1.0 and so we have to store 0.0.
-	// As most of the sum are expected to be nul the resulting matrix will
-	// be very sparse and we will save computation in the forward-backward.
-	//
-	// So we compute Ψ differently here
-	//   1/ we sum the unigrams features weights by looping over actives
-	//        unigrams observations and store them in |psiuni|.
-	//   2/ we sum the bigrams features weights by looping over actives
-	//        bigrams observations (we don't have to do this for t=0 since
-	//        there is no bigrams here) and we store the non-nul one in the
-	//        sparse matrix.
-	//   3/ we take the component-wise exponential of the unigrams vectors,
-	//        and the component-wise exponential of the sparse matrix minus
-	//        one. (here also this can be done efficiently with vector
-	//        maths)
-	for (int t = 0; t < T; t++) {
-		const pos_t *pos = &(seq->pos[t]);
-		for (size_t y = 0; y < Y; y++) {
-			double sum = 0.0;
-			for (size_t n = 0; n < pos->ucnt; n++) {
-				const size_t o = pos->uobs[n];
-				sum += x[mdl->uoff[o] + y];
-			}
-			(*psiuni)[t][y] = sum;
-		}
-	}
-	size_t off = 0;
-	for (int t = 1; t < T; t++) {
-		const pos_t *pos = &(seq->pos[t]);
-		psioff[t] = off;
-		for (size_t y = 0, nnz = 0; y < Y; y++) {
-			for (size_t yp = 0; yp < Y; yp++) {
-				double sum = 0.0;
-				for (size_t n = 0; n < pos->bcnt; n++) {
-					const size_t o = pos->bobs[n];
-					sum += x[mdl->boff[o] + yp * Y + y];
-				}
-				if (sum == 0.0)
-					continue;
-				psiyp [off] = yp;
-				psival[off] = sum;
-				nnz++, off++;
-			}
-			(*psiidx)[t][y] = nnz;
-		}
-	}
-	xvm_expma((double *)psiuni, (double *)psiuni, 0.0, (size_t)T * Y);
-	xvm_expma((double *)psival, (double *)psival, 1.0, off);
+	const double (*psiuni)[T][Y] = (void *)grd->psiuni;
+	const double  *psival        =         grd->psi;
+	const size_t  *psiyp         =         grd->psiyp;
+	const size_t (*psiidx)[T][Y] = (void *)grd->psiidx;
+	const size_t  *psioff        =         grd->psioff;
+	double (*alpha)[T][Y] = (void *)grd->alpha;
+	double (*beta )[T][Y] = (void *)grd->beta;
+	double  *scale        =         grd->scale;
+	double  *uz           =         grd->unorm;
+	double  *bz           =         grd->bnorm;
+
+	grd_spdopsi(grd, seq);
+
 	// Now, we go to the forward-backward algorithm. The numerical problems
 	// are solved with scaling as explained in the dense gradient
 	// computation.


darwin: rename iPid to ifd (this is an fd, not a pid...)

--- ext/darwin_fdinfo.c
+++ ext/darwin_fdinfo.c
@@ -40,12 +40,12 @@
     int i;
     for(i = 0; i < numberOfProcFDs; i++) {
         //printf("FD #%d: %d\n", procFDInfo[i].proc_fd, procFDInfo[i].proc_fdtype);
-        PyObject *iPid = Py_BuildValue("i", procFDInfo[i].proc_fd);
-        if (!iPid) {
+        PyObject *ifd = Py_BuildValue("i", procFDInfo[i].proc_fd);
+        if (!ifd) {
             goto cleanup_error;
         }
-        int append_result = PyList_Append(result, iPid);
-        Py_DECREF(iPid);
+        int append_result = PyList_Append(result, ifd);
+        Py_DECREF(ifd);
         if (append_result == -1) {
             goto cleanup_error;
         }
@@ -69,7 +69,6 @@
 };

-
 PyMODINIT_FUNC
 init_fdinfo(void)
 {


Fixed a warning in control_write_transfer and made it return nil.

--- ext/device_handle.c
+++ ext/device_handle.c
@@ -98,9 +98,9 @@
     }
     buffer = RSTRING_PTR(oData);
     wLength = RSTRING_LEN(oData);
-    if (wLength < 0 || wLength > 0xFFFF)
+    if (wLength > 0xFFFF)
     {
-      rb_raise(rb_eRangeError, "Expected length of data to be between 0 and 65535.");
+      rb_raise(rb_eRangeError, "Expected length of data to be at most 65535.");
     }
   }
   int result = libusb_control_transfer
@@ -109,7 +109,7 @@
 		 FIX2INT(owValue), FIX2INT(owIndex),
 		 buffer, wLength, timeout);
   if (result < 0){ raise_usb_exception(result); }
-  return rb_str_new(buffer, result);
+  return Qnil;
 }

 void Init_device_handle()


update docs on public Windows pdb files

update docs on public Windows pdb files

git-svn-id: ed337ca7cdb08c0ba29d8fe58632bb7686892c2d@1987 49cc7528-f6fd-11dd-9d1a-b59b2e1864b6

--- ext/drsyms/drsyms.h
+++ ext/drsyms/drsyms.h
@@ -283,6 +283,9 @@
  * \note This function is currently implemented only for Windows PDB
  * symbols (DRSYM_PDB).
  *
+ * \note The public Windows symbol files typically do not contain type
+ * information for function parameters.
+ *
  * \note Despite the name, this routine will retrieve type information
  * for non-functions as well.
  *
@@ -317,6 +320,9 @@
  *
  * \note This function is currently implemented only for Windows PDB
  * symbols (DRSYM_PDB).
+ *
+ * \note The public Windows symbol files typically do not contain type
+ * information for function parameters.
  *
  * @param[in] modpath    The full path to the module to be queried.
  * @param[in] type_id    The type index, acquired from a prior call to


Format

Format

--- ext/image/adapter.h
+++ ext/image/adapter.h
@@ -122,25 +122,25 @@

 PHALCON_INIT_FUNCS(phalcon_image_adapter_method_entry){
 	PHP_ME(Phalcon_Image_Adapter, __construct, arginfo_phalcon_image_adapter___construct, ZEND_ACC_PUBLIC|ZEND_ACC_CTOR)
-	PHP_ME(Phalcon_Image_Adapter, getRealPath, NULL, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, getWidth, NULL, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, getHeight, NULL, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, getType, NULL, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, getMime, NULL, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, getImage, NULL, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, resize, arginfo_phalcon_image_adapter_resize, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, liquidRescale, arginfo_phalcon_image_adapter_liquidrescale, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, crop, arginfo_phalcon_image_adapter_crop, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, rotate, arginfo_phalcon_image_adapter_rotate, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, flip, arginfo_phalcon_image_adapter_flip, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, sharpen, arginfo_phalcon_image_adapter_sharpen, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, reflection, arginfo_phalcon_image_adapter_reflection, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, watermark, arginfo_phalcon_image_adapter_watermark, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, text, arginfo_phalcon_image_adapter_text, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, mask, arginfo_phalcon_image_adapter_mask, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, background, arginfo_phalcon_image_adapter_background, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, save, arginfo_phalcon_image_adapter_save, ZEND_ACC_PUBLIC)
-	PHP_ME(Phalcon_Image_Adapter, render, arginfo_phalcon_image_adapter_render, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, getRealPath, NULL, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, getWidth, NULL, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, getHeight, NULL, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, getType, NULL, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, getMime, NULL, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, getImage, NULL, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, resize, arginfo_phalcon_image_adapter_resize, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, liquidRescale, arginfo_phalcon_image_adapter_liquidrescale, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, crop, arginfo_phalcon_image_adapter_crop, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, rotate, arginfo_phalcon_image_adapter_rotate, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, flip, arginfo_phalcon_image_adapter_flip, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, sharpen, arginfo_phalcon_image_adapter_sharpen, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, reflection, arginfo_phalcon_image_adapter_reflection, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, watermark, arginfo_phalcon_image_adapter_watermark, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, text, arginfo_phalcon_image_adapter_text, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, mask, arginfo_phalcon_image_adapter_mask, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, background, arginfo_phalcon_image_adapter_background, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, save, arginfo_phalcon_image_adapter_save, ZEND_ACC_PUBLIC)
+	PHP_ME(Phalcon_Image_Adapter, render, arginfo_phalcon_image_adapter_render, ZEND_ACC_PUBLIC)
 	PHP_FE_END
 };


Fix incorrect Ptr/ConstPtr typedefs in MovingLeastSquaresOMP

--- surface/include/pcl/surface/mls.h
+++ surface/include/pcl/surface/mls.h
@@ -743,8 +743,8 @@
   class MovingLeastSquaresOMP: public MovingLeastSquares<PointInT, PointOutT>
   {
     public:
-      typedef boost::shared_ptr<MovingLeastSquares<PointInT, PointOutT> > Ptr;
-      typedef boost::shared_ptr<const MovingLeastSquares<PointInT, PointOutT> > ConstPtr;
+      typedef boost::shared_ptr<MovingLeastSquaresOMP<PointInT, PointOutT> > Ptr;
+      typedef boost::shared_ptr<const MovingLeastSquaresOMP<PointInT, PointOutT> > ConstPtr;

       using MovingLeastSquares<PointInT, PointOutT>::VOXEL_GRID_DILATION;
       using MovingLeastSquares<PointInT, PointOutT>::DISTINCT_CLOUD;


Adds another test

Adds another test

--- tests/test_op.c
+++ tests/test_op.c
@@ -337,22 +337,22 @@

       newop_program(&A,
           newop_proc(&A,
-            oplabel, "entry",
+            oplabel, "entry_0",
             newop_instr(&A, JVST_OP_TOKEN),
             newop_cmp(&A, JVST_OP_IEQ, oparg_tt(), oparg_tok(SJP_NUMBER)),
-            newop_br(&A, JVST_OP_CBT, "L_1"),
-
-            oplabel, "invalid_1",
+            newop_br(&A, JVST_OP_CBT, "true_2"),
+
+            oplabel, "invalid_1_9",
             newop_invalid(&A, 1),

-            oplabel, "L_1",
+            oplabel, "true_2",
             newop_cmp(&A, JVST_OP_FINT, oparg_tnum(), oparg_none()),
-            newop_br(&A, JVST_OP_CBT, "valid"),
-
-            oplabel, "invalid_2",
+            newop_br(&A, JVST_OP_CBT, "valid_5"),
+
+            oplabel, "invalid_2_7",
             newop_invalid(&A, 2),

-            oplabel, "valid",
+            oplabel, "valid_5",
             newop_instr(&A, JVST_OP_VALID),

             NULL
@@ -2623,8 +2623,8 @@
   test_op_empty_schema();
   test_op_type_constraints();

+  test_op_type_integer();
   /*
-  test_op_type_integer();
   test_op_minimum();

   test_op_properties();


ncd/modules/sys_watch_directory.c: open directory after setting up inotify to avoid race condition

--- ncd/modules/sys_watch_directory.c
+++ ncd/modules/sys_watch_directory.c
@@ -252,34 +252,34 @@
     }
     o->dir = NCDValue_StringValue(dir_arg);

-    // open directory
-    if (!(o->dir_handle = opendir(o->dir))) {
-        ModuleLog(o->i, BLOG_ERROR, "opendir failed");
-        goto fail1;
-    }
-
     // open inotify
     if ((o->inotify_fd = inotify_init()) < 0) {
         ModuleLog(o->i, BLOG_ERROR, "inotify_init failed");
-        goto fail2;
+        goto fail1;
     }

     // add watch
     if (inotify_add_watch(o->inotify_fd, o->dir, IN_CREATE | IN_DELETE | IN_MODIFY | IN_MOVED_FROM | IN_MOVED_TO) < 0) {
         ModuleLog(o->i, BLOG_ERROR, "inotify_add_watch failed");
-        goto fail3;
+        goto fail2;
     }

     // set non-blocking
     if (!badvpn_set_nonblocking(o->inotify_fd)) {
         ModuleLog(o->i, BLOG_ERROR, "badvpn_set_nonblocking failed");
-        goto fail3;
+        goto fail2;
     }

     // init BFileDescriptor
     BFileDescriptor_Init(&o->bfd, o->inotify_fd, (BFileDescriptor_handler)inotify_fd_handler, o);
     if (!BReactor_AddFileDescriptor(o->i->reactor, &o->bfd)) {
         ModuleLog(o->i, BLOG_ERROR, "BReactor_AddFileDescriptor failed");
+        goto fail2;
+    }
+
+    // open directory
+    if (!(o->dir_handle = opendir(o->dir))) {
+        ModuleLog(o->i, BLOG_ERROR, "opendir failed");
         goto fail3;
     }

@@ -291,11 +291,10 @@
     return;

 fail3:
+    // free BFileDescriptor
+    BReactor_RemoveFileDescriptor(o->i->reactor, &o->bfd);
+fail2:
     ASSERT_FORCE(close(o->inotify_fd) == 0)
-fail2:
-    if (closedir(o->dir_handle) < 0) {
-        ModuleLog(o->i, BLOG_ERROR, "closedir failed");
-    }
 fail1:
     free(o);
 fail0:
@@ -307,18 +306,18 @@
 {
     NCDModuleInst *i = o->i;

-    // free BFileDescriptor
-    BReactor_RemoveFileDescriptor(o->i->reactor, &o->bfd);
-
-    // close inotify
-    ASSERT_FORCE(close(o->inotify_fd) == 0)
-
     // close directory
     if (o->dir_handle) {
         if (closedir(o->dir_handle) < 0) {
             ModuleLog(o->i, BLOG_ERROR, "closedir failed");
         }
     }
+
+    // free BFileDescriptor
+    BReactor_RemoveFileDescriptor(o->i->reactor, &o->bfd);
+
+    // close inotify
+    ASSERT_FORCE(close(o->inotify_fd) == 0)

     // free instance
     free(o);


Fix decimal lexing

Fix decimal lexing

--- iv/lexer.h
+++ iv/lexer.h
@@ -933,14 +933,8 @@

     if (type == DECIMAL) {
-      if (is_decimal_integer) {
-        numeric_ = ParseIntegerOverflow(buffer8_.data(),
-                                        buffer8_.data() + buffer8_.size(),
-                                        10);
-      } else {
-        const std::string buf(buffer8_.begin(), buffer8_.end());
-        numeric_ = std::atof(buf.c_str());
-      }
+      const std::string buf(buffer8_.begin(), buffer8_.end());
+      numeric_ = std::atof(buf.c_str());
     } else if (type == HEX) {
       assert(buffer8_.size() > 2);  // first 0x
       numeric_ = ParseIntegerOverflow(buffer8_.data() + 2,


quick hack to make the cldmask binary work with roi masks.

The problem is that roi masks contain only one polygon, which covers
almost the entire image.

--- c/cldmask.c
+++ c/cldmask.c
@@ -304,7 +304,8 @@

 	// identify the connected components that are background
-	int background_ids[m->n], n_background_ids = 0;
+	//int background_ids[m->n], n_background_ids = 0;
+	int background_ids[(int) fmax(1000, m->n)], n_background_ids = 0;
 	for (int j = 0; j < h; j++)
 	for (int i = 0; i < w; i++)
 	{
@@ -315,11 +316,11 @@
 			if (!r) {
 				background_ids[n_background_ids] = idx;
 				n_background_ids += 1;
-				if (n_background_ids >= m->n)
-					fail("bad heuristic of background"
-						       " components %d %d",
-						       n_background_ids, m->n
-						       );
+//				if (n_background_ids >= m->n)
+//					fail("bad heuristic of background"
+//						       " components %d %d",
+//						       n_background_ids, m->n
+//						       );
 			}
 		}
 	}


core: fix a mistake in the caca_set_color_ansi() documentation.

git-svn-id: 3f9eced0add15b5a9fa491ea3f7f263c10f60fd6@4843 92316355-f0b4-4df1-b90c-862c8a59935f

--- caca/attr.c
+++ caca/attr.c
@@ -223,7 +223,7 @@
  *  Color values are those defined in caca.h, such as CACA_RED
  *  or CACA_TRANSPARENT.
  *
- *  If an error occurs, 0 is returned and \b errno is set accordingly:
+ *  If an error occurs, -1 is returned and \b errno is set accordingly:
  *  - \c EINVAL At least one of the colour values is invalid.
  *
  *  \param cv A handle to the libcaca canvas.


Enabled the use of fixed dimensions from within a cuda kernel.

--- unsupported/Eigen/CXX11/src/Tensor/TensorDimensions.h
+++ unsupported/Eigen/CXX11/src/Tensor/TensorDimensions.h
@@ -110,14 +110,14 @@
     return internal::arg_prod(Indices...);
   }

-  Sizes() { }
+  EIGEN_DEVICE_FUNC Sizes() { }
   template <typename DenseIndex>
-  explicit Sizes(const array<DenseIndex, Base::count>& /*indices*/) {
+  explicit EIGEN_DEVICE_FUNC Sizes(const array<DenseIndex, Base::count>& /*indices*/) {
     // todo: add assertion
   }
 #ifdef EIGEN_HAS_VARIADIC_TEMPLATES
-  template <typename... DenseIndex> Sizes(DenseIndex...) { }
-  explicit Sizes(std::initializer_list<std::ptrdiff_t> /*l*/) {
+  template <typename... DenseIndex> EIGEN_DEVICE_FUNC Sizes(DenseIndex...) { }
+  explicit EIGEN_DEVICE_FUNC Sizes(std::initializer_list<std::ptrdiff_t> /*l*/) {
     // todo: add assertion
   }
 #endif


add zfs oid to bsnmpd

add zfs oid to bsnmpd

PR: bin/129360
Submitted by:	Ulrich Spoerlein

--- usr.sbin/bsnmpd/modules/snmp_hostres/hostres_fs_tbl.c
+++ usr.sbin/bsnmpd/modules/snmp_hostres/hostres_fs_tbl.c
@@ -131,6 +131,7 @@
 	const struct asn_oid	*oid;	/* the OID to return */
 } fs_type_map[] = {
 	{ "ufs",	&OIDX_hrFSBerkeleyFFS_c },
+	{ "zfs",        &OIDX_hrFSOther_c },
 	{ "cd9660",	&OIDX_hrFSiso9660_c },
 	{ "nfs",	&OIDX_hrFSNFS_c },
 	{ "ext2fs",	&OIDX_hrFSLinuxExt2_c },


Use /dev/null in invalidate_fd to avoid infinite loop in OpenSSL

Thanks to Andy Bakun / @thwarted for identifying the issue and
suggesting the /dev/null workaround.

--- ext/mysql2/client.c
+++ ext/mysql2/client.c
@@ -169,26 +169,30 @@

 #ifndef _WIN32
 /*
- * Redirect clientfd to a dummy socket for mysql_close to
- * write, shutdown, and close on as a no-op.
- * We do this hack because we want to call mysql_close to release
- * memory, but do not want mysql_close to drop connections in the
- * parent if the socket got shared in fork.
+ * Redirect clientfd to /dev/null for mysql_close and SSL_close to write,
+ * shutdown, and close. The hack is needed to prevent shutdown() from breaking
+ * a socket that may be in use by the parent or other processes after fork.
+ *
+ * /dev/null is used to absorb writes; previously a dummy socket was used, but
+ * it could not abosrb writes and caused openssl to go into an infinite loop.
+ *
  * Returns Qtrue or Qfalse (success or failure)
+ *
+ * Note: if this function is needed on Windows, use "nul" instead of "/dev/null"
  */
 static VALUE invalidate_fd(int clientfd)
 {
 #ifdef SOCK_CLOEXEC
   /* Atomically set CLOEXEC on the new FD in case another thread forks */
-  int sockfd = socket(AF_UNIX, SOCK_STREAM | SOCK_CLOEXEC, 0);
+  int sockfd = open("/dev/null", O_RDWR | O_CLOEXEC);
   if (sockfd < 0) {
     /* Maybe SOCK_CLOEXEC is defined but not available on this kernel */
-    int sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
+    int sockfd = open("/dev/null", O_RDWR);
     fcntl(sockfd, F_SETFD, FD_CLOEXEC);
   }
 #else
   /* Well we don't have SOCK_CLOEXEC, so just set FD_CLOEXEC quickly */
-  int sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
+  int sockfd = open("/dev/null", O_RDWR);
   fcntl(sockfd, F_SETFD, FD_CLOEXEC);
 #endif


Removed unused variable

Removed unused variable

--- ext/wkhtml/wkhtml.c
+++ ext/wkhtml/wkhtml.c
@@ -5,7 +5,7 @@
 #define INT2BOOL(v) ((int)v) ? Qtrue : Qfalse
 #define BOOL2INT(v) ((VALUE)v) ? 1 : 0

-void Init_wkhtml() {
+void Init_wkhtml_native() {
   int use_graphics;
   #ifdef USE_GRAPHICS
   use_graphics = 1;
@@ -137,7 +137,6 @@
 VALUE wkhtml_topdf_converter_create(VALUE self, VALUE settings) {
   wkhtmltopdf_global_settings* global_settings;
   wkhtmltopdf_converter* converter;
-  VALUE obj;

   if(rb_obj_is_kind_of(settings, cWkHtmlToPdfGlobalSettings) == Qfalse) {
     rb_raise(rb_eArgError, "Wrong argument type, must be a GlobalSettings");
@@ -250,7 +249,6 @@
 VALUE wkhtml_toimage_converter_create(VALUE self, VALUE settings, VALUE data) {
   wkhtmltoimage_global_settings* global_settings;
   wkhtmltoimage_converter* converter;
-  VALUE obj;
   char* data_cstr = NULL;

   if(rb_obj_is_kind_of(settings, cWkHtmlToImageGlobalSettings) == Qfalse) {


register pthread_atfork handlers to try and ensure the global mutex survives

--- ext/zookeeper_lib.c
+++ ext/zookeeper_lib.c
@@ -48,6 +48,24 @@
   if (rv != 0) log_err("global_mutex_unlock error");
   return rv;
 }
+
+void atfork_prepare() {
+  global_mutex_lock();
+}
+
+void atfork_parent() {
+  global_mutex_unlock();
+}
+
+void atfork_child() {
+  global_mutex_unlock();
+}
+
+// set up handlers to make sure the thread being forked holds the lock at the
+// time the process is copied, then immediately unlock the mutex in both parent
+// and children
+pthread_atfork(atfork_prepare, atfork_parent, atfork_child);
+

 void zkrb_enqueue(zkrb_queue_t *q, zkrb_event_t *elt) {
   if (q == NULL) {


Don't error when saving addons config in test

--- extensions/addons.c
+++ extensions/addons.c
@@ -1632,7 +1632,8 @@
     config_file = g_build_filename (config_dir, "addons", NULL);
     katze_mkdir_with_parents (config_dir, 0700);
     sokoke_key_file_save_to_file (keyfile, config_file, &error);
-    if (error)
+    /* If the folder is /, this is a test run, thus no error */
+    if (error && !g_str_equal (config_dir, "/"))
     {
         g_warning (_("The configuration of the extension '%s' couldn't be saved: %s\n"),
                     _("User addons"), error->message);


Fixing delayMicroseconds()

Fixing delayMicroseconds()

--- cores/arduino/delay.h
+++ cores/arduino/delay.h
@@ -60,39 +60,42 @@
  *
  * \param dwUs the number of microseconds to pause (uint32_t)
  */
-static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));
-static inline void delayMicroseconds(uint32_t usec){
-    if (usec == 0) return;
-    uint32_t n = usec * (VARIANT_MCK / 3000000);
-#if 0
-    __asm__ volatile(
-        "L_%=_delayMicroseconds:"       "\n\t"
-        "subs   %0, %0, #1"                 "\n\t"
-        "bne    L_%=_delayMicroseconds" "\n"
-        : "+r" (n) :
-    );
-#else
-  for ( ; n != 0 ; n-- )
+static __inline__ void delayMicroseconds( uint32_t ) __attribute__((always_inline, unused)) ;
+static __inline__ void delayMicroseconds( uint32_t ul_usec )
+{
+  if ( ul_usec == 0 )
   {
+    return ;
   }
-#endif
-}
+
+  uint32_t ul = ul_usec * (VARIANT_MCK / 3000000); // = ul_usec * 16 with VARIANT_MCK @ 48MHz
+
+/* following 'for' loop will generate this:
+ * loop:
+ * subs r3, #1 // 1 Core cycle
+ * bne.n loop // 1 or 2 Core cycles, depends on pipeline break (50/50?)
+
+  for ( ; ul != 0 ; ul-- )
+  {
+    __asm__ volatile("");
+  }
+*/

 /*
-__attribute__((naked)) static void delay_loop(unsigned n)
-{
-	__asm volatile ("1: subs r0, r0, #1");
-	__asm volatile (" bne 1b");
-	__asm volatile (" bx lr");
+ * __asm__ [__volatile__] ( AssemblerTemplate : [OutputOperands] [ : [InputOperands] [ : [Clobbers] ] ] )
+ *
+ * __asm__ documentation for GCC: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html
+ * __volatile__ documentation for GCC: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Volatile
+ *
+ */
+  __asm__ __volatile__( "1:      \n"
+                        "sub %0, #1              \n" /* substract 1 from %0 (ul) */
+                        "bne 1b   \n"
+                        : /* no outputs */
+                        : "r" (ul) /* 'ul' variable is '%0', '+' means R/W constraint on this variable/register, 'r' means 'register' (versus 'm' for 'memory' */
+                        : /* no clobber, ie nothing should be damaged by this asm code */
+                      ) ;
 }
-
-void delay_microseconds(unsigned n)
-{
-	// Bogus assumption:
-	// Assume 8 cycles/iteration and running at 80MHz
-	delay_loop(n * 10);
-}
-*/

 #ifdef __cplusplus
 }


patch was applied with typo, now correct


remove warning

remove warning

--- cpp_utils/yas_flow_private.h
+++ cpp_utils/yas_flow_private.h
@@ -147,7 +147,6 @@

 template <typename Out, typename In, typename Begin>
 node<Out, In, Begin> node<Out, In, Begin>::guard(std::function<bool(In const &value)> guard_handler) {
-#warning todo handlerを切り替えて呼ばなくできるようにする？
     auto imp = impl_ptr<impl>();
     flow::sender<Begin> &sender = imp->_sender;
     auto weak_sender = to_weak(sender);


cpu/stm32: fix FLASHPAGE_ERASE_STATE for stm32l4

--- cpu/stm32/include/cpu_conf.h
+++ cpu/stm32/include/cpu_conf.h
@@ -116,8 +116,7 @@
 #define FLASHPAGE_SIZE                  (128U)
 #endif

-#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
-    defined(CPU_FAM_STM32L4)
+#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
 #define FLASHPAGE_ERASE_STATE           (0x00U)
 #endif

@@ -188,7 +187,6 @@

 #endif

-
 /* The minimum block size which can be written depends on the family.
  * However, the erase block is always FLASHPAGE_SIZE.
  */


stm32/periph/flashpage: Reset cache

stm32/periph/flashpage: Reset cache

Co-authored-by: Francisco <7a34699ecf731639b526e9ef254901fef43cf878@uc.cl>

--- cpu/stm32/periph/flashpage.c
+++ cpu/stm32/periph/flashpage.c
@@ -236,6 +236,12 @@
     bool instruction_cache = FLASH->ACR & FLASH_ACR_ICEN;
     if (instruction_cache) {
         FLASH->ACR &= ~FLASH_ACR_ICEN;
+#if defined(CPU_FAM_STM32WL)
+        /* Reset the instruction cache after it has been disabled. This
+           operation is required as the cpu stalls after a flash write operation
+           for unknown reasons in STM32WL55JC */
+        FLASH->ACR |= FLASH_ACR_ICRST;
+#endif
     }
 #endif


add Mac OS specific clock_gettime() clocks

Signed-off-by: Steven Noonan <4068f0880b399410602d694b3cc711c8a8f4727e@uplinklabs.net>

--- clockperf.c
+++ clockperf.c
@@ -252,8 +252,17 @@
 #ifdef CLOCK_MONOTONIC_RAW
     { {CPERF_GETTIME, CLOCK_MONOTONIC_RAW},          &ref_clock },
 #endif
+#ifdef CLOCK_MONOTONIC_RAW_APPROX // OS X
+    { {CPERF_GETTIME, CLOCK_MONOTONIC_RAW_APPROX},   &ref_clock },
+#endif
 #ifdef CLOCK_BOOTTIME
     { {CPERF_GETTIME, CLOCK_BOOTTIME},               &ref_clock },
+#endif
+#ifdef CLOCK_UPTIME_RAW // OS X
+    { {CPERF_GETTIME, CLOCK_UPTIME_RAW},             &ref_clock },
+#endif
+#ifdef CLOCK_UPTIME_RAW_APPROX // OS X
+    { {CPERF_GETTIME, CLOCK_UPTIME_RAW_APPROX},      &ref_clock },
 #endif
 #ifdef CLOCK_PROCESS_CPUTIME_ID
     { {CPERF_GETTIME, CLOCK_PROCESS_CPUTIME_ID},     &ref_clock },
@@ -563,9 +572,21 @@
         case CLOCK_MONOTONIC_RAW:
             return "monotonic_raw";
 #endif
+#ifdef CLOCK_MONOTONIC_RAW_APPROX // OS X
+        case CLOCK_MONOTONIC_RAW_APPROX:
+            return "monotonic_raw_approx";
+#endif
 #ifdef CLOCK_BOOTTIME
         case CLOCK_BOOTTIME:
             return "boottime";
+#endif
+#ifdef CLOCK_UPTIME_RAW // OS X
+        case CLOCK_UPTIME_RAW:
+            return "uptime_raw";
+#endif
+#ifdef CLOCK_UPTIME_RAW_APPROX // OS X
+        case CLOCK_UPTIME_RAW_APPROX:
+            return "uptime_raw_approx";
 #endif
 #ifdef CLOCK_PROCESS_CPUTIME_ID
         case CLOCK_PROCESS_CPUTIME_ID:


Fix segfault in Phalcon\Db\Column

Fix segfault in Phalcon\Db\Column

--- ext/db/column.c
+++ ext/db/column.c
@@ -115,9 +115,8 @@
 PHP_METHOD(Phalcon_Db_Column, __construct){

 	zval *column_name, *definition, *type, *not_null;
-	zval *primary, *size, *is_numeric = NULL, *scale, *dunsigned;
+	zval *primary, *size, *is_numeric, *scale, *dunsigned;
 	zval *auto_increment, *first, *after, *bind_type;
-	zval *t0 = NULL, *t1 = NULL;

 	PHALCON_MM_GROW();

@@ -165,30 +164,12 @@
 	 * Check if the column has a decimal scale
 	 */
 	if (phalcon_array_isset_string(definition, SS("scale"))) {
-
-		PHALCON_INIT_VAR(t0);
-		ZVAL_LONG(t0, 3);
-		PHALCON_INIT_VAR(is_numeric);
-		is_equal_function(is_numeric, type, t0 TSRMLS_CC);
-		if (PHALCON_IS_NOT_TRUE(is_numeric)) {
-			PHALCON_INIT_VAR(t1);
-			ZVAL_LONG(t1, 7);
-			is_equal_function(is_numeric, type, t1 TSRMLS_CC);
-		}
-
-		if (PHALCON_IS_NOT_TRUE(is_numeric)) {
-			PHALCON_INIT_NVAR(t1);
-			ZVAL_LONG(t1, 9);
-			is_equal_function(is_numeric, type, t1 TSRMLS_CC);
-		}
-
-		if (PHALCON_IS_TRUE(is_numeric)) {
+		int i_type = phalcon_get_intval(type);
+
+		if (i_type == 3 || i_type == 7 || i_type == 9) {
 			PHALCON_OBS_VAR(scale);
 			phalcon_array_fetch_string(&scale, definition, SL("scale"), PH_NOISY);
 			phalcon_update_property_this(this_ptr, SL("_scale"), scale TSRMLS_CC);
-		} else {
-			PHALCON_THROW_EXCEPTION_STR(phalcon_db_exception_ce, "Column type does not support scale parameter");
-			return;
 		}
 	}

@@ -205,7 +186,7 @@
 	 * Check if the field is numeric
 	 */
 	if (phalcon_array_isset_string(definition, SS("isNumeric"))) {
-		PHALCON_OBS_NVAR(is_numeric);
+		PHALCON_OBS_VAR(is_numeric);
 		phalcon_array_fetch_string(&is_numeric, definition, SL("isNumeric"), PH_NOISY);
 		phalcon_update_property_this(this_ptr, SL("_isNumeric"), is_numeric TSRMLS_CC);
 	}
@@ -407,8 +388,7 @@

 	zval *data, *definition, *column_name, *column_type;
 	zval *not_null, *primary, *size, *scale, *dunsigned, *after;
-	zval *is_numeric = NULL, *first, *bind_type;
-	zval *t0 = NULL, *t1 = NULL;
+	zval *is_numeric, *first, *bind_type;

 	PHALCON_MM_GROW();

@@ -421,6 +401,7 @@

 	PHALCON_INIT_VAR(definition);
 	array_init(definition);
+
 	if (!phalcon_array_isset_string(data, SS("_columnName"))) {
 		PHALCON_THROW_EXCEPTION_STR(phalcon_db_exception_ce, "Column name is required");
 		return;
@@ -428,76 +409,65 @@

 	PHALCON_OBS_VAR(column_name);
 	phalcon_array_fetch_string(&column_name, data, SL("_columnName"), PH_NOISY);
+
 	if (phalcon_array_isset_string(data, SS("_type"))) {
 		PHALCON_OBS_VAR(column_type);
 		phalcon_array_fetch_string(&column_type, data, SL("_type"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("type"), &column_type, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("type"), &column_type, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_notNull"))) {
 		PHALCON_OBS_VAR(not_null);
 		phalcon_array_fetch_string(&not_null, data, SL("_notNull"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("notNull"), &not_null, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("notNull"), &not_null, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_primary"))) {
 		PHALCON_OBS_VAR(primary);
 		phalcon_array_fetch_string(&primary, data, SL("_primary"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("primary"), &primary, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("primary"), &primary, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_size"))) {
 		PHALCON_OBS_VAR(size);
 		phalcon_array_fetch_string(&size, data, SL("_size"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("size"), &size, PH_COPY | PH_SEPARATE);
-	}
-
-        if (phalcon_array_isset_string(data, SS("_scale"))) {
-                PHALCON_INIT_VAR(t0);
-                ZVAL_LONG(t0, 3);
-                PHALCON_INIT_VAR(is_numeric);
-                is_equal_function(is_numeric, column_type, t0 TSRMLS_CC);
-                if (PHALCON_IS_NOT_TRUE(is_numeric)) {
-                        PHALCON_INIT_VAR(t1);
-                        ZVAL_LONG(t1, 7);
-                        is_equal_function(is_numeric, column_type, t1 TSRMLS_CC);
-                }
-
-                if (PHALCON_IS_TRUE(is_numeric)) {
-                        PHALCON_OBS_VAR(scale);
-                        phalcon_array_fetch_string(&scale, data, SL("_scale"), PH_NOISY);
-                        phalcon_array_update_string(&definition, SL("scale"), &scale, PH_COPY | PH_SEPARATE);
-                }
-        }
+		phalcon_array_update_string(&definition, SL("size"), &size, PH_COPY);
+	}
+
+	if (phalcon_array_isset_string(data, SS("_scale"))) {
+		PHALCON_OBS_VAR(scale);
+		phalcon_array_fetch_string(&scale, data, SL("_scale"), PH_NOISY);
+		phalcon_array_update_string(&definition, SL("scale"), &scale, PH_COPY);
+	}

 	if (phalcon_array_isset_string(data, SS("_unsigned"))) {
 		PHALCON_OBS_VAR(dunsigned);
 		phalcon_array_fetch_string(&dunsigned, data, SL("_unsigned"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("unsigned"), &dunsigned, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("unsigned"), &dunsigned, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_after"))) {
 		PHALCON_OBS_VAR(after);
 		phalcon_array_fetch_string(&after, data, SL("_after"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("after"), &after, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("after"), &after, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_isNumeric"))) {
-		PHALCON_OBS_NVAR(is_numeric);
+		PHALCON_OBS_VAR(is_numeric);
 		phalcon_array_fetch_string(&is_numeric, data, SL("_isNumeric"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("isNumeric"), &is_numeric, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("isNumeric"), &is_numeric, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_first"))) {
 		PHALCON_OBS_VAR(first);
 		phalcon_array_fetch_string(&first, data, SL("_first"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("first"), &first, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("first"), &first, PH_COPY);
 	}

 	if (phalcon_array_isset_string(data, SS("_bindType"))) {
 		PHALCON_OBS_VAR(bind_type);
 		phalcon_array_fetch_string(&bind_type, data, SL("_bindType"), PH_NOISY);
-		phalcon_array_update_string(&definition, SL("bindType"), &bind_type, PH_COPY | PH_SEPARATE);
+		phalcon_array_update_string(&definition, SL("bindType"), &bind_type, PH_COPY);
 	}

 	object_init_ex(return_value, phalcon_db_column_ce);


field: Fixed ib_field_convert() for bytestr

--- util/field.c
+++ util/field.c
@@ -1250,33 +1250,34 @@
         if (rc != IB_OK){
             return rc;
         }
+        str = (const char *)ib_bytestr_const_ptr(bstr);
         sz = ib_bytestr_length(bstr);

         /* Convert byte str. */
         switch(desired_type) {
         case IB_FTYPE_NULSTR:
-            str = ib_mpool_memdup_to_str(mp, bstr, sz);
+            str = ib_mpool_memdup_to_str(mp, str, sz);
             if (!str) {
                 return rc;
             }
             new_field_value = ib_ftype_nulstr_in(str);
             break;
         case IB_FTYPE_TIME:
-            rc = ib_string_to_time_ex((char *)bstr, sz, &tme);
+            rc = ib_string_to_time_ex(str, sz, &tme);
             if (rc != IB_OK) {
                 return rc;
             }
             new_field_value = ib_ftype_time_in(&tme);
             break;
         case IB_FTYPE_NUM:
-            rc = ib_string_to_num_ex((char *)bstr, sz, 0, &num);
+            rc = ib_string_to_num_ex(str, sz, 0, &num);
             if (rc != IB_OK) {
                 return rc;
             }
             new_field_value = ib_ftype_num_in(&num);
             break;
         case IB_FTYPE_FLOAT:
-            rc = ib_string_to_float_ex((char *)bstr, sz, &flt);
+            rc = ib_string_to_float_ex(str, sz, &flt);
             if (rc != IB_OK) {
                 return rc;
             }


crypto: jitterentropy - remove unnecessary information from a comment

The clocksource does not provide clocksource_register() function since
f893598 commit (clocksource: Mostly kill clocksource_register()), so
let's remove unnecessary information about this function from a comment.

Signed-off-by: Alexander Kuleshov <1e54dc1c299571bb7a58e37a7ea31ffd91d38f4e@gmail.com>
Suggested-by: Herbert Xu <ef65de1c7be0aa837fe7b25ba9a7739905af6a55@gondor.apana.org.au>
Signed-off-by: Herbert Xu <ef65de1c7be0aa837fe7b25ba9a7739905af6a55@gondor.apana.org.au>

--- crypto/jitterentropy-kcapi.c
+++ crypto/jitterentropy-kcapi.c
@@ -98,10 +98,6 @@
 	 * If random_get_entropy does not return a value (which is possible on,
 	 * for example, MIPS), invoke __getnstimeofday
 	 * hoping that there are timers we can work with.
-	 *
-	 * The list of available timers can be obtained from
-	 * /sys/devices/system/clocksource/clocksource0/available_clocksource
-	 * and are registered with clocksource_register()
 	 */
 	if ((0 == tmp) &&
 	   (0 == __getnstimeofday(&ts))) {


tests: net: ethernet_mgmt: Don't recalculate deltaBW with no link

Fixes #9462

Coverity ID: 187670

Attempts to recalculate deltaBandwidth with no link lead to division by
zero.

Signed-off-by: Tomasz Gorochowik <265c7c25eca9aa9127910457b0aea7e793d329f1@antmicro.com>

--- tests/net/ethernet_mgmt/src/main.c
+++ tests/net/ethernet_mgmt/src/main.c
@@ -89,8 +89,14 @@
 	bw = eth_fake_get_total_bandwidth(ctx);

 	for (i = 0; i < ARRAY_SIZE(ctx->priority_queues); ++i) {
-		ctx->priority_queues[i].delta_bandwidth =
-			(ctx->priority_queues[i].idle_slope * 100) / bw;
+		if (bw == 0) {
+			ctx->priority_queues[i].delta_bandwidth = 0;
+		} else {
+			ctx->priority_queues[i].delta_bandwidth =
+				(ctx->priority_queues[i].idle_slope * 100);
+
+			ctx->priority_queues[i].delta_bandwidth /= bw;
+		}
 	}
 }


mm, slab: release slab_mutex earlier in kmem_cache_destroy()

Commit 1331e7a1bbe1 ("rcu: Remove _rcu_barrier() dependency on
__stop_machine()") introduced slab_mutex -> cpu_hotplug.lock dependency
through kmem_cache_destroy() -> rcu_barrier() -> _rcu_barrier() ->
get_online_cpus().

Lockdep thinks that this might actually result in ABBA deadlock,
and reports it as below:

=== [ cut here ] ===
 ======================================================
 [ INFO: possible circular locking dependency detected ]
 3.6.0-rc5-00004-g0d8ee37 #143 Not tainted
 -------------------------------------------------------
 kworker/u:2/40 is trying to acquire lock:
  (rcu_sched_state.barrier_mutex){+.+...}, at: [<ffffffff810f2126>] _rcu_barrier+0x26/0x1e0

 but task is already holding lock:
  (slab_mutex){+.+.+.}, at: [<ffffffff81176e15>] kmem_cache_destroy+0x45/0xe0

 which lock already depends on the new lock.

 the existing dependency chain (in reverse order) is:

 -> #2 (slab_mutex){+.+.+.}:
        [<ffffffff810ae1e2>] validate_chain+0x632/0x720
        [<ffffffff810ae5d9>] __lock_acquire+0x309/0x530
        [<ffffffff810ae921>] lock_acquire+0x121/0x190
        [<ffffffff8155d4cc>] __mutex_lock_common+0x5c/0x450
        [<ffffffff8155d9ee>] mutex_lock_nested+0x3e/0x50
        [<ffffffff81558cb5>] cpuup_callback+0x2f/0xbe
        [<ffffffff81564b83>] notifier_call_chain+0x93/0x140
        [<ffffffff81076f89>] __raw_notifier_call_chain+0x9/0x10
        [<ffffffff8155719d>] _cpu_up+0xba/0x14e
        [<ffffffff815572ed>] cpu_up+0xbc/0x117
        [<ffffffff81ae05e3>] smp_init+0x6b/0x9f
        [<ffffffff81ac47d6>] kernel_init+0x147/0x1dc
        [<ffffffff8156ab44>] kernel_thread_helper+0x4/0x10

 -> #1 (cpu_hotplug.lock){+.+.+.}:
        [<ffffffff810ae1e2>] validate_chain+0x632/0x720
        [<ffffffff810ae5d9>] __lock_acquire+0x309/0x530
        [<ffffffff810ae921>] lock_acquire+0x121/0x190
        [<ffffffff8155d4cc>] __mutex_lock_common+0x5c/0x450
        [<ffffffff8155d9ee>] mutex_lock_nested+0x3e/0x50
        [<ffffffff81049197>] get_online_cpus+0x37/0x50
        [<ffffffff810f21bb>] _rcu_barrier+0xbb/0x1e0
        [<ffffffff810f22f0>] rcu_barrier_sched+0x10/0x20
        [<ffffffff810f2309>] rcu_barrier+0x9/0x10
        [<ffffffff8118c129>] deactivate_locked_super+0x49/0x90
        [<ffffffff8118cc01>] deactivate_super+0x61/0x70
        [<ffffffff811aaaa7>] mntput_no_expire+0x127/0x180
        [<ffffffff811ab49e>] sys_umount+0x6e/0xd0
        [<ffffffff81569979>] system_call_fastpath+0x16/0x1b

 -> #0 (rcu_sched_state.barrier_mutex){+.+...}:
        [<ffffffff810adb4e>] check_prev_add+0x3de/0x440
        [<ffffffff810ae1e2>] validate_chain+0x632/0x720
        [<ffffffff810ae5d9>] __lock_acquire+0x309/0x530
        [<ffffffff810ae921>] lock_acquire+0x121/0x190
        [<ffffffff8155d4cc>] __mutex_lock_common+0x5c/0x450
        [<ffffffff8155d9ee>] mutex_lock_nested+0x3e/0x50
        [<ffffffff810f2126>] _rcu_barrier+0x26/0x1e0
        [<ffffffff810f22f0>] rcu_barrier_sched+0x10/0x20
        [<ffffffff810f2309>] rcu_barrier+0x9/0x10
        [<ffffffff81176ea1>] kmem_cache_destroy+0xd1/0xe0
        [<ffffffffa04c3154>] nf_conntrack_cleanup_net+0xe4/0x110 [nf_conntrack]
        [<ffffffffa04c31aa>] nf_conntrack_cleanup+0x2a/0x70 [nf_conntrack]
        [<ffffffffa04c42ce>] nf_conntrack_net_exit+0x5e/0x80 [nf_conntrack]
        [<ffffffff81454b79>] ops_exit_list+0x39/0x60
        [<ffffffff814551ab>] cleanup_net+0xfb/0x1b0
        [<ffffffff8106917b>] process_one_work+0x26b/0x4c0
        [<ffffffff81069f3e>] worker_thread+0x12e/0x320
        [<ffffffff8106f73e>] kthread+0x9e/0xb0
        [<ffffffff8156ab44>] kernel_thread_helper+0x4/0x10

 other info that might help us debug this:

 Chain exists of:
   rcu_sched_state.barrier_mutex --> cpu_hotplug.lock --> slab_mutex

  Possible unsafe locking scenario:

        CPU0                    CPU1
        ----                    ----
   lock(slab_mutex);
                                lock(cpu_hotplug.lock);
                                lock(slab_mutex);
   lock(rcu_sched_state.barrier_mutex);

  *** DEADLOCK ***
=== [ cut here ] ===

This is actually a false positive. Lockdep has no way of knowing the fact
that the ABBA can actually never happen, because of special semantics of
cpu_hotplug.refcount and its handling in cpu_hotplug_begin(); the mutual
exclusion there is not achieved through mutex, but through
cpu_hotplug.refcount.

The "neither cpu_up() nor cpu_down() will proceed past cpu_hotplug_begin()
until everyone who called get_online_cpus() will call put_online_cpus()"
semantics is totally invisible to lockdep.

This patch therefore moves the unlock of slab_mutex so that rcu_barrier()
is being called with it unlocked. It has two advantages:

- it slightly reduces hold time of slab_mutex; as it's used to protect
  the cachep list, it's not necessary to hold it over kmem_cache_free()
  call any more
- it silences the lockdep false positive warning, as it avoids lockdep ever
  learning about slab_mutex -> cpu_hotplug.lock dependency

Reviewed-by: Paul E. McKenney <1e0ce936bb9b355d257bf5790d2513c3f28be22b@linux.vnet.ibm.com>
Reviewed-by: Srivatsa S. Bhat <5b23f8226e886b22344fc642373ea657dd596b63@linux.vnet.ibm.com>
Acked-by: David Rientjes <d8cd2994e15bc61ddb2b113030bda55eebc3a0fe@google.com>
Signed-off-by: Jiri Kosina <ed58f755cc8caaf10c3e8c731a8b86fb8f13d6cb@suse.cz>
Signed-off-by: Pekka Enberg <add4fcd06328a394f0ad91feda7ee057316dc5ed@kernel.org>

--- mm/slab_common.c
+++ mm/slab_common.c
@@ -168,6 +168,7 @@
 		list_del(&s->list);

 		if (!__kmem_cache_shutdown(s)) {
+			mutex_unlock(&slab_mutex);
 			if (s->flags & SLAB_DESTROY_BY_RCU)
 				rcu_barrier();

@@ -175,12 +176,14 @@
 			kmem_cache_free(kmem_cache, s);
 		} else {
 			list_add(&s->list, &slab_caches);
+			mutex_unlock(&slab_mutex);
 			printk(KERN_ERR "kmem_cache_destroy %s: Slab cache still has objects\n",
 				s->name);
 			dump_stack();
 		}
+	} else {
+		mutex_unlock(&slab_mutex);
 	}
-	mutex_unlock(&slab_mutex);
 	put_online_cpus();
 }
 EXPORT_SYMBOL(kmem_cache_destroy);


[MISC] Added missed brackets in if/else statement in ril_request_screen_state

Change-Id: I5e7e13ce940147b8f75cacaf190c93e821e7c8dc

--- mocha-ril/misc.c
+++ mocha-ril/misc.c
@@ -55,8 +55,10 @@
 	if (((int *)data)[0] == 0 )
 		ipc_power_mode(0);
 	else
+	{
 		drv_send_packet(BATT_GAUGE_STATUS_REQ, (uint8_t*)&status, 4);
 		ipc_power_mode(6);
+	}
 	ril_request_complete(t, RIL_E_SUCCESS, NULL, 0);
 }


Incomplete - task : speed everything up

Incomplete - task : speed everything up

git-svn-id: a36550da1b6493884efebfb740573981a7433be5@6850 a8237c23-d22b-0410-ac1a-db40f18c2caa

--- api/tests/cactusFlowerTest.c
+++ api/tests/cactusFlowerTest.c
@@ -202,7 +202,7 @@
                     void *)) flower_getNextSequence,
             (void *(*)(void *)) flower_getPreviousSequence,
             (void *(*)(void *)) flower_copySequenceIterator,
-            (void *)sequence, (void *)sequence2);
+            sequence, sequence2);
 }

 void testFlower_cap(CuTest* testCase) {