cpu/stm32f0: optimized isr vector definitions

--- cpu/stm32f0/vectors.c
+++ cpu/stm32f0/vectors.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014-2015 Freie Universität Berlin
+ * Copyright (C) 2014-2017 Freie Universität Berlin
  *
  * This file is subject to the terms and conditions of the GNU Lesser General
  * Public License v2.1. See the file LICENSE in the top level directory for more
@@ -18,11 +18,7 @@
  * @}
  */

-#include <stdint.h>
 #include "vectors_cortexm.h"
-
-/* get the start of the ISR stack as defined in the linkerscript */
-extern uint32_t _estack;

 /* define a local dummy handler as it needs to be in the same compilation unit
  * as the alias definition */
@@ -31,225 +27,182 @@
 }

 /* STM32F0 specific interrupt vectors */
-WEAK_DEFAULT void isr_wwdg(void);
+WEAK_DEFAULT void isr_adc1(void);
+WEAK_DEFAULT void isr_adc1_comp(void);
+WEAK_DEFAULT void isr_cec_can(void);
+WEAK_DEFAULT void isr_dma1_ch1(void);
+WEAK_DEFAULT void isr_dma1_ch2_3_dma2_ch1_2(void);
+WEAK_DEFAULT void isr_dma1_ch4_7_dma2_ch3_5(void);
+WEAK_DEFAULT void isr_dma1_channel1(void);
+WEAK_DEFAULT void isr_dma1_channel2_3(void);
+WEAK_DEFAULT void isr_dma1_channel4_5(void);
+WEAK_DEFAULT void isr_dma1_channel4_5_6_7(void);
+WEAK_DEFAULT void isr_exti(void);
+WEAK_DEFAULT void isr_flash(void);
+WEAK_DEFAULT void isr_i2c1(void);
+WEAK_DEFAULT void isr_i2c2(void);
 WEAK_DEFAULT void isr_pvd(void);
+WEAK_DEFAULT void isr_pvd_vddio2(void);
+WEAK_DEFAULT void isr_rcc(void);
+WEAK_DEFAULT void isr_rcc_crs(void);
 WEAK_DEFAULT void isr_rtc(void);
-WEAK_DEFAULT void isr_flash(void);
-WEAK_DEFAULT void isr_rcc(void);
-WEAK_DEFAULT void isr_exti(void);
-WEAK_DEFAULT void isr_ts(void);
-WEAK_DEFAULT void isr_dma1_ch1(void);
-WEAK_DEFAULT void isr_dma1_ch2_3(void);
-WEAK_DEFAULT void isr_dma1_ch4_5(void);
-WEAK_DEFAULT void isr_adc1_comp(void);
+WEAK_DEFAULT void isr_spi1(void);
+WEAK_DEFAULT void isr_spi2(void);
+WEAK_DEFAULT void isr_tim14(void);
+WEAK_DEFAULT void isr_tim15(void);
+WEAK_DEFAULT void isr_tim16(void);
+WEAK_DEFAULT void isr_tim17(void);
 WEAK_DEFAULT void isr_tim1_brk_up_trg_com(void);
 WEAK_DEFAULT void isr_tim1_cc(void);
 WEAK_DEFAULT void isr_tim2(void);
 WEAK_DEFAULT void isr_tim3(void);
+WEAK_DEFAULT void isr_tim6(void);
 WEAK_DEFAULT void isr_tim6_dac(void);
 WEAK_DEFAULT void isr_tim7(void);
-WEAK_DEFAULT void isr_tim14(void);
-WEAK_DEFAULT void isr_tim15(void);
-WEAK_DEFAULT void isr_tim16(void);
-WEAK_DEFAULT void isr_tim17(void);
-WEAK_DEFAULT void isr_i2c1(void);
-WEAK_DEFAULT void isr_i2c2(void);
-WEAK_DEFAULT void isr_spi1(void);
-WEAK_DEFAULT void isr_spi2(void);
+WEAK_DEFAULT void isr_tsc(void);
 WEAK_DEFAULT void isr_usart1(void);
 WEAK_DEFAULT void isr_usart2(void);
+WEAK_DEFAULT void isr_usart3_4(void);
 WEAK_DEFAULT void isr_usart3_8(void);
-WEAK_DEFAULT void isr_cec(void);
 WEAK_DEFAULT void isr_usb(void);
+WEAK_DEFAULT void isr_wwdg(void);

 /* CPU specific interrupt vector table */
 ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
-    isr_wwdg,                /* [0] windowed watchdog */
+    /* shared vectors for all family members */
+    [ 0] = isr_wwdg,                 /* [ 0] Window WatchDog Interrupt */
+    [ 2] = isr_rtc,                  /* [ 2] RTC Interrupt through EXTI Lines 17, 19 and 20 */
+    [ 3] = isr_flash,                /* [ 3] FLASH global Interrupt */
+    [14] = isr_tim1_cc,              /* [14] TIM1 Capture Compare Interrupt */
+    [16] = isr_tim3,                 /* [16] TIM3 global Interrupt */
+    [19] = isr_tim14,                /* [19] TIM14 global Interrupt */
+    [21] = isr_tim16,                /* [21] TIM16 global Interrupt */
+    [22] = isr_tim17,                /* [22] TIM17 global Interrupt */
+    [25] = isr_spi1,                 /* [25] SPI1 global Interrupt */
+
 #if defined(CPU_MODEL_STM32F030R8)
-    (0UL),                   /* [1] reserved */
-    isr_rtc,                 /* [2] real time clock */
-    isr_flash,               /* [3] flash memory controller */
-    isr_rcc,                 /* [4] reset and clock control */
-    isr_exti,                /* [5] external interrupt lines 0 and 1 */
-    isr_exti,                /* [6] external interrupt lines 2 and 3 */
-    isr_exti,                /* [7] external interrupt lines 4 to 15 */
-    (0UL),                   /* [8] reserved */
-    isr_dma1_ch1,            /* [9] direct memory access controller 1, channel 1*/
-    isr_dma1_ch2_3,          /* [10] direct memory access controller 1, channel 2 and 3*/
-    isr_dma1_ch4_5,          /* [11] direct memory access controller 1, channel 4 and 5*/
-    isr_adc1_comp,           /* [12] analog digital converter */
-    isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
-    isr_tim1_cc,             /* [14] timer 1 capture compare */
-    isr_tim2,                /* [15] timer 2 */
-    isr_tim3,                /* [16] timer 3 */
-    isr_tim6_dac,            /* [17] timer 6 and digital to analog converter */
-    (0UL),                   /* [18] reserved */
-    isr_tim14,               /* [19] timer 14 */
-    isr_tim15,               /* [20] timer 15 */
-    isr_tim16,               /* [21] timer 16 */
-    isr_tim17,               /* [22] timer 17 */
-    isr_i2c1,                /* [23] I2C 1 */
-    isr_i2c2,                /* [24] I2C 2 */
-    isr_spi1,                /* [25] SPI 1 */
-    isr_spi2,                /* [26] SPI 2 */
-    isr_usart1,              /* [27] USART 1 */
-    isr_usart2               /* [28] USART 2 */
+    [ 4] = isr_rcc,                  /* [ 4] RCC global Interrupt */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupt */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupt */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupt */
+    [ 9] = isr_dma1_channel1,        /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_channel2_3,      /* [10] DMA1 Channel 2 and Channel 3 Interrupt */
+    [11] = isr_dma1_channel4_5,      /* [11] DMA1 Channel 4 and Channel 5 Interrupt */
+    [12] = isr_adc1,                 /* [12] ADC1 Interrupt */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */
+    [17] = isr_tim6,                 /* [17] TIM6 global Interrupt */
+    [20] = isr_tim15,                /* [20] TIM15 global Interrupt */
+    [23] = isr_i2c1,                 /* [23] I2C1 Event Interrupt */
+    [24] = isr_i2c2,                 /* [24] I2C2 Event Interrupt */
+    [26] = isr_spi2,                 /* [26] SPI2 global Interrupt */
+    [27] = isr_usart1,               /* [27] USART1 global Interrupt */
+    [28] = isr_usart2,               /* [28] USART2 global Interrupt */
 #elif defined(CPU_MODEL_STM32F031K6)
-    isr_pvd,                 /* [1] power control */
-    isr_rtc,                 /* [2] real time clock */
-    isr_flash,               /* [3] flash memory controller */
-    isr_rcc,                 /* [4] reset and clock control */
-    isr_exti,                /* [5] external interrupt lines 0 and 1 */
-    isr_exti,                /* [6] external interrupt lines 2 and 3 */
-    isr_exti,                /* [7] external interrupt lines 4 to 15 */
-    (0UL),                   /* [8] reserved */
-    isr_dma1_ch1,            /* [9] direct memory access controller 1, channel 1*/
-    isr_dma1_ch2_3,          /* [10] direct memory access controller 1, channel 2 and 3*/
-    isr_dma1_ch4_5,          /* [11] direct memory access controller 1, channel 4 and 5*/
-    isr_adc1_comp,           /* [12] analog digital converter */
-    isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
-    isr_tim1_cc,             /* [14] timer 1 capture compare */
-    isr_tim2,                /* [15] timer 2 */
-    isr_tim3,                /* [16] timer 3 */
-    (0UL),                   /* [17] reserved */
-    (0UL),                   /* [18] reserved */
-    isr_tim14,               /* [19] timer 14 */
-    (0UL),                   /* [20] reserved */
-    isr_tim16,               /* [21] timer 16 */
-    isr_tim17,               /* [22] timer 17 */
-    isr_i2c1,                /* [23] I2C 1 */
-    (0UL),                   /* [24] reserved */
-    isr_spi1,                /* [25] SPI 1 */
-    (0UL),                   /* [26] reserved */
-    isr_usart1               /* [27] USART 1 */
+    [ 1] = isr_pvd,                  /* [ 1] PVD Interrupt through EXTI Lines 16 */
+    [ 4] = isr_rcc,                  /* [ 4] RCC global Interrupt */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupt */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupt */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupt */
+    [ 9] = isr_dma1_channel1,        /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_channel2_3,      /* [10] DMA1 Channel 2 and Channel 3 Interrupt */
+    [11] = isr_dma1_channel4_5,      /* [11] DMA1 Channel 4 and Channel 5 Interrupt */
+    [12] = isr_adc1,                 /* [12] ADC1 Interrupt */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */
+    [15] = isr_tim2,                 /* [15] TIM2 global Interrupt */
 #elif defined(CPU_MODEL_STM32F042K6)
-    isr_pvd,                 /* [1] power control */
-    isr_rtc,                 /* [2] real time clock */
-    isr_flash,               /* [3] flash memory controller */
-    isr_rcc,                 /* [4] reset and clock control */
-    isr_exti,                /* [5] external interrupt lines 0 and 1 */
-    isr_exti,                /* [6] external interrupt lines 2 and 3 */
-    isr_exti,                /* [7] external interrupt lines 4 to 15 */
-    isr_ts,                  /* [8] touch sensing input*/
-    isr_dma1_ch1,            /* [9] direct memory access controller 1, channel 1*/
-    isr_dma1_ch2_3,          /* [10] direct memory access controller 1, channel 2 and 3*/
-    isr_dma1_ch4_5,          /* [11] direct memory access controller 1, channel 4 and 5*/
-    isr_adc1_comp,           /* [12] analog digital converter */
-    isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
-    isr_tim1_cc,             /* [14] timer 1 capture compare */
-    isr_tim2,                /* [15] timer 2 */
-    isr_tim3,                /* [16] timer 3 */
-    (0UL),                   /* [17] reserved */
-    (0UL),                   /* [18] reserved */
-    isr_tim14,               /* [19] timer 14 */
-    (0UL),                   /* [20] reserved */
-    isr_tim16,               /* [21] timer 16 */
-    isr_tim17,               /* [22] timer 17 */
-    isr_i2c1,                /* [23] I2C 1 */
-    (0UL),                   /* [24] reserved */
-    isr_spi1,                /* [25] SPI 1 */
-    isr_spi2,                /* [26] SPI 2 */
-    isr_usart1,              /* [27] USART 1 */
-    isr_usart2,              /* [28] USART 2 */
-    (0UL),                   /* [29] reserved */
-    isr_cec,                 /* [30] consumer electronics control */
-    isr_usb                  /* [31] USB global Interrupts & EXTI Line18 Interrup */
+    [ 1] = isr_pvd_vddio2,           /* [ 1] PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
+    [ 4] = isr_rcc_crs,              /* [ 4] RCC & CRS Global Interrupts */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupts */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupts */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupts */
+    [ 8] = isr_tsc,                  /* [ 8] Touch Sensing Controller Interrupts */
+    [ 9] = isr_dma1_channel1,        /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_channel2_3,      /* [10] DMA1 Channel 2 and Channel 3 Interrupts */
+    [11] = isr_dma1_channel4_5,      /* [11] DMA1 Channel 4 and Channel 5 Interrupts */
+    [12] = isr_adc1,                 /* [12] ADC1 Interrupt */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */
+    [15] = isr_tim2,                 /* [15] TIM2 global Interrupt */
+    [26] = isr_spi2,                 /* [26] SPI2 global Interrupt */
+    [28] = isr_usart2,               /* [28] USART2 global Interrupt */
+    [30] = isr_cec_can,              /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
+    [31] = isr_usb,                  /* [31] USB global Interrupts & EXTI Line18 Interrupt */
 #elif defined(CPU_MODEL_STM32F051R8)
-    isr_pvd,                 /* [1] power control */
-    isr_rtc,                 /* [2] real time clock */
-    isr_flash,               /* [3] flash memory controller */
-    isr_rcc,                 /* [4] reset and clock control */
-    isr_exti,                /* [5] external interrupt lines 0 and 1 */
-    isr_exti,                /* [6] external interrupt lines 2 and 3 */
-    isr_exti,                /* [7] external interrupt lines 4 to 15 */
-    isr_ts,                  /* [8] touch sensing input*/
-    isr_dma1_ch1,            /* [9] direct memory access controller 1, channel 1*/
-    isr_dma1_ch2_3,          /* [10] direct memory access controller 1, channel 2 and 3*/
-    isr_dma1_ch4_5,          /* [11] direct memory access controller 1, channel 4 and 5*/
-    isr_adc1_comp,           /* [12] analog digital converter */
-    isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
-    isr_tim1_cc,             /* [14] timer 1 capture compare */
-    isr_tim2,                /* [15] timer 2 */
-    isr_tim3,                /* [16] timer 3 */
-    isr_tim6_dac,            /* [17] timer 6 and digital to analog converter */
-    (0UL),                   /* [18] reserved */
-    isr_tim14,               /* [19] timer 14 */
-    isr_tim15,               /* [20] timer 15 */
-    isr_tim16,               /* [21] timer 16 */
-    isr_tim17,               /* [22] timer 17 */
-    isr_i2c1,                /* [23] I2C 1 */
-    isr_i2c2,                /* [24] I2C 2 */
-    isr_spi1,                /* [25] SPI 1 */
-    isr_spi2,                /* [26] SPI 2 */
-    isr_usart1,              /* [27] USART 1 */
-    isr_usart2,              /* [28] USART 2 */
-    (0UL),                   /* [29] reserved */
-    isr_cec,                 /* [30] consumer electronics control */
+    [ 1] = isr_pvd,                  /* [ 1] PVD Interrupt through EXTI Lines 16 */
+    [ 4] = isr_rcc,                  /* [ 4] RCC global Interrupt */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupts */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupts */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupts */
+    [ 8] = isr_tsc,                  /* [ 8] Touch Sensing Controller Interrupts */
+    [ 9] = isr_dma1_channel1,        /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_channel2_3,      /* [10] DMA1 Channel 2 and Channel 3 Interrupts */
+    [11] = isr_dma1_channel4_5,      /* [11] DMA1 Channel 4 and Channel 5 Interrupts */
+    [12] = isr_adc1_comp,            /* [12] ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */
+    [15] = isr_tim2,                 /* [15] TIM2 global Interrupt */
+    [17] = isr_tim6_dac,             /* [17] TIM6 global and DAC channel underrun error Interrupts */
+    [20] = isr_tim15,                /* [20] TIM15 global Interrupt */
+    [24] = isr_i2c2,                 /* [24] I2C2 Event Interrupt */
+    [26] = isr_spi2,                 /* [26] SPI2 global Interrupt */
+    [28] = isr_usart2,               /* [28] USART2 global Interrupt */
+    [30] = isr_cec_can,              /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
 #elif defined(CPU_MODEL_STM32F070RB)
-    (0UL),                   /* [1] reserved */
-    isr_rtc,                 /* [2] real time clock */
-    isr_flash,               /* [3] flash memory controller */
-    isr_rcc,                 /* [4] reset and clock control */
-    isr_exti,                /* [5] external interrupt lines 0 and 1 */
-    isr_exti,                /* [6] external interrupt lines 2 and 3 */
-    isr_exti,                /* [7] external interrupt lines 4 to 15 */
-    isr_ts,                  /* [8] touch sensing input*/
-    isr_dma1_ch1,            /* [9] direct memory access controller 1, channel 1*/
-    isr_dma1_ch2_3,          /* [10] direct memory access controller 1, channel 2 and 3*/
-    isr_dma1_ch4_5,          /* [11] direct memory access controller 1, channel 4 and 5*/
-    isr_adc1_comp,           /* [12] analog digital converter */
-    isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
-    isr_tim1_cc,             /* [14] timer 1 capture compare */
-    (0UL),                   /* [15] reserved */
-    isr_tim3,                /* [16] timer 3 */
-    isr_tim6_dac,            /* [17] timer 6 and digital to analog converter */
-    isr_tim7,                /* [18] timer 7 */
-    isr_tim14,               /* [19] timer 14 */
-    isr_tim15,               /* [20] timer 15 */
-    isr_tim16,               /* [21] timer 16 */
-    isr_tim17,               /* [22] timer 17 */
-    isr_i2c1,                /* [23] I2C 1 */
-    isr_i2c2,                /* [24] I2C 2 */
-    isr_spi1,                /* [25] SPI 1 */
-    isr_spi2,                /* [26] SPI 2 */
-    isr_usart1,              /* [27] USART 1 */
-    isr_usart2,              /* [28] USART 2 */
-    isr_usart3_8,            /* [29] USART 3 to 8 */
-    (0UL),                   /* [30] reserved */
-    isr_usb                  /* [31] USB global Interrupts & EXTI Line18 Interrup */
-#else /* CPU_MODEL_STM32_F072RB, CPU_MODEL_STM32F091RC*/
-    isr_pvd,                 /* [1] power control */
-    isr_rtc,                 /* [2] real time clock */
-    isr_flash,               /* [3] flash memory controller */
-    isr_rcc,                 /* [4] reset and clock control */
-    isr_exti,                /* [5] external interrupt lines 0 and 1 */
-    isr_exti,                /* [6] external interrupt lines 2 and 3 */
-    isr_exti,                /* [7] external interrupt lines 4 to 15 */
-    isr_ts,                  /* [8] touch sensing input*/
-    isr_dma1_ch1,            /* [9] direct memory access controller 1, channel 1*/
-    isr_dma1_ch2_3,          /* [10] direct memory access controller 1, channel 2 and 3*/
-    isr_dma1_ch4_5,          /* [11] direct memory access controller 1, channel 4 and 5*/
-    isr_adc1_comp,           /* [12] analog digital converter */
-    isr_tim1_brk_up_trg_com, /* [13] timer 1 break, update, trigger and communication */
-    isr_tim1_cc,             /* [14] timer 1 capture compare */
-    isr_tim2,                /* [15] timer 2 */
-    isr_tim3,                /* [16] timer 3 */
-    isr_tim6_dac,            /* [17] timer 6 and digital to analog converter */
-    isr_tim7,                /* [18] timer 7 */
-    isr_tim14,               /* [19] timer 14 */
-    isr_tim15,               /* [20] timer 15 */
-    isr_tim16,               /* [21] timer 16 */
-    isr_tim17,               /* [22] timer 17 */
-    isr_i2c1,                /* [23] I2C 1 */
-    isr_i2c2,                /* [24] I2C 2 */
-    isr_spi1,                /* [25] SPI 1 */
-    isr_spi2,                /* [26] SPI 2 */
-    isr_usart1,              /* [27] USART 1 */
-    isr_usart2,              /* [28] USART 2 */
-    isr_usart3_8,            /* [29] USART 3 to 8 */
-    isr_cec,                 /* [30] consumer electronics control */
-#if defined(CPU_MODEL_STM32F072RB)
-    isr_usb                  /* [31] USB global Interrupts & EXTI Line18 Interrup */
-#endif
+    [ 4] = isr_rcc,                  /* [ 4] RCC global Interrupt */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupt */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupt */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupt */
+    [ 9] = isr_dma1_channel1,        /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_channel2_3,      /* [10] DMA1 Channel 2 and Channel 3 Interrupt */
+    [11] = isr_dma1_channel4_5,      /* [11] DMA1 Channel 4 and Channel 5 Interrupt */
+    [12] = isr_adc1,                 /* [12] ADC1 Interrupt */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */
+    [17] = isr_tim6,                 /* [17] TIM6 global Interrupt */
+    [18] = isr_tim7,                 /* [18] TIM7 global Interrupt */
+    [20] = isr_tim15,                /* [20] TIM15 global Interrupt */
+    [24] = isr_i2c2,                 /* [24] I2C2 Event Interrupt */
+    [26] = isr_spi2,                 /* [26] SPI2 global Interrupt */
+    [27] = isr_usart1,               /* [27] USART1 global Interrupt */
+    [28] = isr_usart2,               /* [28] USART2 global Interrupt */
+    [29] = isr_usart3_4,             /* [29] USART3 and USART4 global Interrupt */
+    [31] = isr_usb,                  /* [31] USB global Interrupt  & EXTI Line18 Interrupt */
+#elif defined(CPU_MODEL_STM32F072RB)
+    [ 1] = isr_pvd_vddio2,           /* [ 1] PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */
+    [ 4] = isr_rcc_crs,              /* [ 4] RCC & CRS global Interrupt */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupt */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupt */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupt */
+    [ 8] = isr_tsc,                  /* [ 8] Touch Sensing Controller Interrupts */
+    [ 9] = isr_dma1_channel1,        /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_channel2_3,      /* [10] DMA1 Channel 2 and Channel 3 Interrupt */
+    [11] = isr_dma1_channel4_5_6_7,  /* [11] DMA1 Channel 4 to Channel 7 Interrupt */
+    [12] = isr_adc1_comp,            /* [12] ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */
+    [15] = isr_tim2,                 /* [15] TIM2 global Interrupt */
+    [17] = isr_tim6_dac,             /* [17] TIM6 global and DAC channel underrun error Interrupt */
+    [18] = isr_tim7,                 /* [18] TIM7 global Interrupt */
+    [20] = isr_tim15,                /* [20] TIM15 global Interrupt */
+    [24] = isr_i2c2,                 /* [24] I2C2 Event Interrupt */
+    [26] = isr_spi2,                 /* [26] SPI2 global Interrupt */
+    [29] = isr_usart3_4,             /* [29] USART3 and USART4 global Interrupt */
+    [30] = isr_cec_can,              /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
+    [31] = isr_usb,                  /* [31] USB global Interrupt  & EXTI Line18 Interrupt */
+#elif defined(CPU_MODEL_STM32F091RC)
+    [ 1] = isr_pvd_vddio2,           /* [ 1] PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
+    [ 4] = isr_rcc_crs,              /* [ 4] RCC & CRS global Interrupts */
+    [ 5] = isr_exti,                 /* [ 5] EXTI Line 0 and 1 Interrupts */
+    [ 6] = isr_exti,                 /* [ 6] EXTI Line 2 and 3 Interrupts */
+    [ 7] = isr_exti,                 /* [ 7] EXTI Line 4 to 15 Interrupts */
+    [ 8] = isr_tsc,                  /* [ 8] Touch Sensing Controller Interrupts */
+    [ 9] = isr_dma1_ch1,             /* [ 9] DMA1 Channel 1 Interrupt */
+    [10] = isr_dma1_ch2_3_dma2_ch1_2,/* [10] DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */
+    [11] = isr_dma1_ch4_7_dma2_ch3_5,/* [11] DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */
+    [13] = isr_tim1_brk_up_trg_com,  /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */
+    [15] = isr_tim2,                 /* [15] TIM2 global Interrupt */
+    [17] = isr_tim6_dac,             /* [17] TIM6 global and DAC channel underrun error Interrupts */
+    [18] = isr_tim7,                 /* [18] TIM7 global Interrupt */
+    [20] = isr_tim15,                /* [20] TIM15 global Interrupt */
+    [24] = isr_i2c2,                 /* [24] I2C2 Event Interrupt */
+    [26] = isr_spi2,                 /* [26] SPI2 global Interrupt */
+    [29] = isr_usart3_8,             /* [29] USART3 to USART8 global Interrupts */
+    [30] = isr_cec_can,              /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */
 #endif
 };


i#1551 port to ARM: fix bug in A32 rotated-immed encoding

Fixes a bug where A32 rotated-immed encoding wasn't handling the case of no
rotation at all properly.

Review-URL: https://codereview.appspot.com/200170043

--- core/arch/arm/encode.c
+++ core/arch/arm/encode.c
@@ -672,6 +672,8 @@
                 return false;
         }
     }
+    LOG(THREAD_GET, LOG_EMIT, ENC_LEVEL, "%s: val=%d, initial A=%d-%d, B=%d-%d\n",
+        __FUNCTION__, val, startA, stopA, startB, stopB);
     /* Clamp to the edges */
     if (startB != -1) {
         startA = 31;
@@ -680,8 +682,12 @@
     /* Clamp to even bits (rotation value is x2) */
     if (startB != -1)
         startB = ALIGN_FORWARD(startB + 1, 2) - 1;
-    if (startA != -1)
-        stopA = ALIGN_BACKWARD(stopA - 1, 2) + 1;
+    if (startA != -1) {
+        startA = ALIGN_FORWARD(startA + 1, 2) - 1;
+        stopA = ALIGN_BACKWARD(stopA, 2);
+    }
+    LOG(THREAD_GET, LOG_EMIT, ENC_LEVEL, "%s: val=%d, clamped A=%d-%d, B=%d-%d\n",
+        __FUNCTION__, val, startA, stopA, startB, stopB);
     if ((startA != -1 && startB != -1 && (stopA - startA) + (stopB - startB) > 8) ||
         (startA != -1 && (stopA - startA)) > 8)
         return false;
@@ -690,8 +696,13 @@
         rot = 7 - startB;
         val8 = ((val & 0xff000000) >> (32 - rot)) | ((val & 0xff) << rot);
     } else if (startA != -1) {
-        rot = 8 + (31 - startA);
-        val8 = val & (0xff << (startA -7));
+        if (startA < 8) {
+            rot = 0;
+            val8 = val & 0xff;
+        } else {
+            rot = 8 + (31 - startA);
+            val8 = val & (0xff << (startA -7));
+        }
     } else {
         rot = 0;
         val8 = 0;


Deprecate category methods. Fixes #159

Deprecate category methods. Fixes #159

--- Classes/NSObject+SBJson.h
+++ Classes/NSObject+SBJson.h
@@ -42,8 +42,11 @@
  @return the receiver encoded in JSON, or nil on error.

  @see @ref objc2json
+
+ @deprecated in Version 3.2; will be removed in 4.0
+
  */
-- (NSString *)JSONRepresentation;
+- (NSString *)JSONRepresentation __attribute__ ((deprecated));

 @end

@@ -59,8 +62,11 @@
  @return the NSDictionary or NSArray represented by the receiver, or nil on error.

  @see @ref json2objc
+
+ @deprecated in Version 3.2; will be removed in 4.0
+
  */
-- (id)JSONValue;
+- (id)JSONValue __attribute__ ((deprecated));

 @end

@@ -73,7 +79,10 @@
  @return the NSDictionary or NSArray represented by the receiver, or nil on error.

  @see @ref json2objc
+
+ @deprecated in Version 3.2; will be removed in 4.0
+
  */
-- (id)JSONValue;
+- (id)JSONValue __attribute__ ((deprecated));

 @end


Create updateTimeAndPercentages.c

Create updateTimeAndPercentages.c

error: pathspec 'FMER/scripts/plan/main/updateTimeAndPercentages.c' did not match any file(s) known to git

--- FMER/scripts/plan/main/updateTimeAndPercentages.c
+++ FMER/scripts/plan/main/updateTimeAndPercentages.c
@@ -0,0 +1,10 @@
+plan: main: updateTimeAndPercentages
+Set Variable [ $object; Value:Get ( ActiveLayoutObjectName ) ]
+Set Variable [ $record; Value:Get ( RecordNumber) ]
+Commit Records/Requests
+Go to Record/Request/Page
+[ Next ]
+Go to Record/Request/Page [ $record ]
+[ No dialog ]
+Go to Object [ Object Name: $object ]
+January 8, 平成26 12:23:39 Fat and Muscle Efﬁciency Research.fp7 - updateTimeAndPercentages -1-


Bluetooth: Controller: Fix assert on LL BIG terminate

Fix assert on LL BIG terminate call before BIG sync is
established. Assert was caused due to duplicate calls to
release stream contexts, once in LL BIG terminate function
then when releasing the HCI BIG sync failed to be
established node rx was being released.

Use iso_broadcast and iso_receive samples, power cycle the
iso_broadcast device when iso_receive sample is waiting for
BIG sync to be established, iso_receive sample will perform
a BIG sync terminate that leads to the assert.

Signed-off-by: Vinayak Kariappa Chettimada <e780c9f87dc729ad454f47292ad82c8652353064@nordicsemi.no>

--- subsys/bluetooth/controller/ll_sw/ull_sync_iso.c
+++ subsys/bluetooth/controller/ll_sw/ull_sync_iso.c
@@ -185,8 +185,6 @@
 			return BT_HCI_ERR_CMD_DISALLOWED;
 		}
 		sync->iso.sync_iso = NULL;
-
-		ull_sync_iso_stream_release(sync_iso);

 		node_rx = (void *)sync->iso.node_rx_estab;
 		link_sync_estab = node_rx->hdr.link;


Work on completion events: t+

Work on completion events: t+

--- cpan/libmarpa/dev/marpa.w
+++ cpan/libmarpa/dev/marpa.w
@@ -5077,7 +5077,7 @@
 	  irl->t_event_isyids =
 	  ISYID_is_Completion_Event (lhs_isyid) ? cil_singleton (&g->t_cilar,
 								 lhs_isyid) :
-	  cil_empty ();
+	  cil_empty (&g->t_cilar);
 	  continue;
 	}
       {
@@ -13635,17 +13635,17 @@
 @<Function definitions@> =
 PRIVATE CIL cil_empty(CILAR cilar)
 {
-    CIL new_cil = cil_reserve(&g->t_cilar, 0);
-    return cil_finish (&g->t_cilar);
+    cil_reserve(cilar, 0);
+    return cil_finish (cilar);
 }

 @ Return a singleton CIL from a CILAR.
 @<Function definitions@> =
 PRIVATE CIL cil_singleton(CILAR cilar, int element)
 {
-    CIL new_cil = cil_reserve (&g->t_cilar, 1);
-    Item_of_CIL (new_cil, 0) = element;
-    return cil_finish (&g->t_cilar);
+  CIL new_cil = cil_reserve (cilar, 1);
+  Item_of_CIL (new_cil, 0) = element;
+  return cil_finish (cilar);
 }

 @ @<Function definitions@> =


Follow-up to r1326307: undo change that accidentally slipped in. * subversion/tests/libsvn_subr/named_atomic-test.c   (calibrate_concurrency): remove long run test

--- subversion/tests/libsvn_subr/named_atomic-test.c
+++ subversion/tests/libsvn_subr/named_atomic-test.c
@@ -290,13 +290,6 @@
 {
   if (hw_thread_count == 0)
     {
-      int i = 0;
-      for (i = 0; i < 100000; ++i)
-        {
-          printf("%8d", i);
-          SVN_ERR(init_concurrency_test_shm(pool, 2));
-          SVN_ERR(run_procs(pool, TEST_PROC, 2, 100000));
-        }
       SVN_ERR(calibrate_iterations(pool, 2));
       for (hw_thread_count = 2; hw_thread_count < 32; hw_thread_count *= 2)
         {


stw: fix potential uninitialized use of curctx

--- src/gallium/state_trackers/wgl/shared/stw_context.c
+++ src/gallium/state_trackers/wgl/shared/stw_context.c
@@ -348,7 +348,7 @@
    struct stw_framebuffer *fb;
    GLuint width = 0;
    GLuint height = 0;
-   struct stw_context *curctx;
+   struct stw_context *curctx = NULL;

    if (!stw_dev)
       return FALSE;


Add mvn_reg_t1, needed for exam

Add mvn_reg_t1, needed for exam

git-svn-id: e9aaea719848b42ed38d9b0b9912e64e15002afd@157 40ecb139-3c61-4c5f-bdaf-cae60a0fc81e

--- cpu/operations/logical.c
+++ cpu/operations/logical.c
@@ -272,6 +272,17 @@
 	DBG2("mvn_reg did stuff\n");
 }

+void mvn_reg_t1(uint32_t inst) {
+	uint8_t rd = inst & 0x7;
+	uint8_t rm = (inst >> 3) & 0x7;
+
+	bool setflags = !in_ITblock();
+	enum SRType shift_t = LSL;
+	uint8_t shift_n = 0;
+
+	return mvn_reg(setflags, rd, rm, shift_t, shift_n);
+}
+
 void mvn_reg_t2(uint32_t inst) {
 	uint8_t rm = (inst & 0xf);
 	uint8_t type = (inst & 0x30) >> 4;
@@ -428,6 +439,9 @@
 	// lsl_reg_t2: 1111 1010 000x xxxx 1111 xxxx 0000 xxxx
 	register_opcode_mask(0xfa00f000, 0x05e000f0, lsl_reg_t2);

+	// mvn_reg_t1: 0100 0011 11xx xxxx
+	register_opcode_mask(0x43c0, 0xffffbc00, mvn_reg_t1);
+
 	// mvn_reg_t2: 1110 1010 011x 1111 0<x's>
 	register_opcode_mask(0xea6f0000, 0x15808000, mvn_reg_t2);


[sw/silicon_creator] Add MockOtp

[sw/silicon_creator] Add MockOtp

Signed-off-by: Alphan Ulusoy <23b245cc5a07aacf75a9db847b24c67dee1707bf@google.com>

error: pathspec 'sw/device/silicon_creator/lib/drivers/mock_otp.h' did not match any file(s) known to git

--- sw/device/silicon_creator/lib/drivers/mock_otp.h
+++ sw/device/silicon_creator/lib/drivers/mock_otp.h
@@ -0,0 +1,46 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_MOCK_OTP_H_
+#define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_MOCK_OTP_H_
+
+#include "sw/device/lib/testing/mask_rom_test.h"
+#include "sw/device/silicon_creator/lib/drivers/otp.h"
+
+namespace mask_rom_test {
+namespace internal {
+
+/**
+ * Mock class for otp.c.
+ */
+class MockOtp {
+ public:
+  MOCK_METHOD(uint32_t, read32, (uint32_t address));
+  MOCK_METHOD(uint32_t, read64, (uint32_t address));
+  MOCK_METHOD(void, read, (uint32_t address, uint32_t *data, size_t num_words));
+  virtual ~MockOtp() {}
+};
+
+}  // namespace internal
+
+using MockOtp = GlobalMock<testing::StrictMock<internal::MockOtp>>;
+
+extern "C" {
+
+uint32_t otp_read32(uint32_t address) {
+  return MockOtp::Instance().read32(address);
+}
+
+uint64_t otp_read64(uint32_t address) {
+  return MockOtp::Instance().read64(address);
+}
+
+void otp_read(uint32_t address, uint32_t *data, size_t num_words) {
+  return MockOtp::Instance().read(address, data, num_words);
+}
+
+}  // extern "C"
+}  // namespace mask_rom_test
+
+#endif  // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_MOCK_OTP_H_


Work on CILAR buffer

Work on CILAR buffer

--- cpan/libmarpa/dev/marpa.w
+++ cpan/libmarpa/dev/marpa.w
@@ -14643,7 +14643,7 @@
 @<Function definitions@> =
 PRIVATE void * dstack_resize(struct s_dstack* this, size_t type_bytes, int new_size)
 {
-  if (new_size < this->t_capacity)
+  if (new_size > this->t_capacity)
     {				/* We do not shrink the stack
 				   in this method */
       this->t_capacity = new_size;


nouveau: dup fd before passing it to device

nouveau screens are reused for the same device node. However in the
scenario where we create screen 1, screen 2, and then delete screen 1,
the surrounding code might also close the original device node. To
protect against this, dup the fd and use the dup'd fd in the
nouveau_device. Also tell the nouveau_device that it is the owner of the
fd so that it will be closed on destruction.

Also make sure to free the nouveau_device in case of any failure.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79823
Signed-off-by: Ilia Mirkin <bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu>
Cc: "10.2" <59f39c0db42d4479a46b02d4d2bc11120e37bb44@lists.freedesktop.org>
Reviewed-by: Maarten Lankhorst <743c2818a341d71b99ed2b566f9f80c2fc288f93@ubuntu.com>

--- src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
+++ src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
@@ -1,4 +1,5 @@
 #include <sys/stat.h>
+#include <unistd.h>
 #include "pipe/p_context.h"
 #include "pipe/p_state.h"
 #include "util/u_format.h"
@@ -59,7 +60,7 @@
 	struct nouveau_device *dev = NULL;
 	struct pipe_screen *(*init)(struct nouveau_device *);
 	struct nouveau_screen *screen;
-	int ret;
+	int ret, dupfd = -1;

 	pipe_mutex_lock(nouveau_screen_mutex);
 	if (!fd_tab) {
@@ -75,7 +76,17 @@
 		return &screen->base;
 	}

-	ret = nouveau_device_wrap(fd, 0, &dev);
+	/* Since the screen re-use is based on the device node and not the fd,
+	 * create a copy of the fd to be owned by the device. Otherwise a
+	 * scenario could occur where two screens are created, and the first
+	 * one is shut down, along with the fd being closed. The second
+	 * (identical) screen would now have a reference to the closed fd. We
+	 * avoid this by duplicating the original fd. Note that
+	 * nouveau_device_wrap does not close the fd in case of a device
+	 * creation error.
+	 */
+	dupfd = dup(fd);
+	ret = nouveau_device_wrap(dupfd, 1, &dev);
 	if (ret)
 		goto err;

@@ -115,6 +126,10 @@
 	return &screen->base;

 err:
+	if (dev)
+		nouveau_device_del(&dev);
+	else if (dupfd >= 0)
+		close(dupfd);
 	pipe_mutex_unlock(nouveau_screen_mutex);
 	return NULL;
 }


saml21/gpio: Enable EXTI0 on PB00

saml21/gpio: Enable EXTI0 on PB00

Signed-off-by: dylad <d56dfe611c7cd6204525c7c9b6afc5e84aed0f5d@mesotic.com>


messy

messy

--- cpneural/cp-layer-tests.h
+++ cpneural/cp-layer-tests.h
@@ -139,8 +139,9 @@
     MatrixN y=*((*pcache)["y"]);
     if (var=="x") pm=&x;
     else pm = params[var];
-    MatrixN grad((*pm).rows(), (*pm).cols());
-
+    MatrixN grad(pm->rows(), pm->cols());
+    cout << var << "/dx-shape:" << shape(grad) << endl;
+
     floatN pxold;
     for (unsigned int i=0; i<grad.size(); i++) {
         t_cppl cache;


stm32l1: Basic implementation of spi_acquire(), spi_release()

Signed-off-by: Joakim Gebart <d097f2c6c8fee73e3ea75e1d62412e3886346faa@eistec.se>

--- cpu/stm32l1/periph/spi.c
+++ cpu/stm32l1/periph/spi.c
@@ -17,11 +17,13 @@
  * @author      Hauke Petersen <mail@haukepetersen.de>
  * @author      Fabian Nack <nack@inf.fu-berlin.de>
  * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ * @author      Joakim Gebart <joakim.gebart@eistec.se>
  *
  * @}
  */

 #include "cpu.h"
+#include "mutex.h"
 #include "periph/spi.h"
 #include "periph_conf.h"
 #include "thread.h"
@@ -29,6 +31,21 @@

 /* guard file in case no SPI device is defined */
 #if SPI_NUMOF
+
+/**
+ * @brief Array holding one pre-initialized mutex for each SPI device
+ */
+static mutex_t locks[] =  {
+#if SPI_0_EN
+    [SPI_0] = MUTEX_INIT,
+#endif
+#if SPI_1_EN
+    [SPI_1] = MUTEX_INIT,
+#endif
+#if SPI_2_EN
+    [SPI_2] = MUTEX_INIT
+#endif
+};

 int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
 {
@@ -135,6 +152,24 @@
         port->AFR[hl] |= (af << ((pin[i] - (hl * 8)) * 4));
     }

+    return 0;
+}
+
+int spi_acquire(spi_t dev)
+{
+    if (dev >= SPI_NUMOF) {
+        return -1;
+    }
+    mutex_lock(&locks[dev]);
+    return 0;
+}
+
+int spi_release(spi_t dev)
+{
+    if (dev >= SPI_NUMOF) {
+        return -1;
+    }
+    mutex_unlock(&locks[dev]);
     return 0;
 }


Add test function for _splice function

Add test function for _splice function

--- tests/test-mdict.c
+++ tests/test-mdict.c
@@ -430,6 +430,11 @@

     //assert (dict_oa_int_hash (d2) != 0);
   }
+  M_LET( (d1, (1, 2), (2, 3), (4, 5)), (d2, (1, 3), (4, 7), (10, 14)), (r1, (1, 5), (2, 3), (4, 12), (10, 14) ), DICT_OPLIST(dict_oa_int, M_DEFAULT_OPLIST, M_DEFAULT_OPLIST)) {
+    dict_oa_int_splice(d1, d2);
+    assert(dict_oa_int_equal_p(d1, r1));
+    assert(dict_oa_int_empty_p(d2));
+  }
 }

 static void test_it_oa(void)


INTEGRATION: CWS changefileheader (1.7.132); FILE MERGED 2008/03/31 07:23:18 rt 1.7.132.1: #i87441# Change license header to LPGL v3.

--- cppu/inc/uno/threadpool.h
+++ cppu/inc/uno/threadpool.h
@@ -1,35 +1,30 @@
 /*************************************************************************
  *
- *  OpenOffice.org - a multi-platform office productivity suite
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
- *  $RCSfile: threadpool.h,v $
+ * Copyright 2008 by Sun Microsystems, Inc.
  *
- *  $Revision: 1.7 $
+ * OpenOffice.org - a multi-platform office productivity suite
  *
- *  last change: $Author: rt $ $Date: 2005-09-08 08:42:34 $
+ * $RCSfile: threadpool.h,v $
+ * $Revision: 1.8 $
  *
- *  The Contents of this file are made available subject to
- *  the terms of GNU Lesser General Public License Version 2.1.
+ * This file is part of OpenOffice.org.
  *
+ * OpenOffice.org is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 3
+ * only, as published by the Free Software Foundation.
  *
- *    GNU Lesser General Public License Version 2.1
- *    =============================================
- *    Copyright 2005 by Sun Microsystems, Inc.
- *    901 San Antonio Road, Palo Alto, CA 94303, USA
+ * OpenOffice.org is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License version 3 for more details
+ * (a copy is included in the LICENSE file that accompanied this code).
  *
- *    This library is free software; you can redistribute it and/or
- *    modify it under the terms of the GNU Lesser General Public
- *    License version 2.1, as published by the Free Software Foundation.
- *
- *    This library is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- *    Lesser General Public License for more details.
- *
- *    You should have received a copy of the GNU Lesser General Public
- *    License along with this library; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- *    MA  02111-1307  USA
+ * You should have received a copy of the GNU Lesser General Public License
+ * version 3 along with OpenOffice.org.  If not, see
+ * <http://www.openoffice.org/license.html>
+ * for a copy of the LGPLv3 License.
  *
  ************************************************************************/


get_ext tests added

get_ext tests added

--- tests/test-utils.c
+++ tests/test-utils.c
@@ -26,11 +26,20 @@
         LONGTEST(str2dec_positive(""), -1);
         LONGTEST(str2dec_positive(NULL), -1);
 }
+void get_ext_tests(void) {
+        STRTEST(get_ext("foo.bar"), "bar");
+        STRTEST(get_ext("foo.bar.baz"), "baz");
+        STRTEST(get_ext("foo.42"), "42");
+        STRTEST(get_ext("foo."), "");
+        STRTEST(get_ext("foobar"), NULL);
+        STRTEST(get_ext(NULL), NULL);
+}

 int main(void) {
         START_TESTS();

         ADD_SUITE(str2dec_positive);
+        ADD_SUITE(get_ext);

         END_OF_TESTS();
         return 0;


fix 'setInterval' that stopped after 512 seconds

--- targets/nrf5x/jshardware.c
+++ targets/nrf5x/jshardware.c
@@ -56,7 +56,7 @@

 /*  S110_SoftDevice_Specification_2.0.pdf

-  RTC0 not usable
+  RTC0 not usable (SoftDevice)
   RTC1 used by app_timer.c
   TIMER0 (32 bit) not usable (softdevice)
   TIMER1 (16 bit on nRF51, 32 bit on nRF52) used by jshardware util timer
@@ -270,15 +270,25 @@
   return true;
 }

+/// Hack because we *really* don't want to mess with RTC0 :)
+JsSysTime baseSystemTime = 0;
+uint32_t lastSystemTime = 0;
+
 /// Get the system time (in ticks)
 JsSysTime jshGetSystemTime() {
+  // Detect RTC overflows
+  uint32_t systemTime = NRF_RTC0->COUNTER;
+  if (lastSystemTime > systemTime)
+    baseSystemTime += 0x1000000; // it's a 24 bit counter
+  lastSystemTime = systemTime;
   // Use RTC0 (also used by BLE stack) - as app_timer starts/stops RTC1
-  return (JsSysTime)NRF_RTC0->COUNTER;
+  return baseSystemTime + (JsSysTime)systemTime;
 }

 /// Set the system time (in ticks) - this should only be called rarely as it could mess up things like jsinteractive's timers!
 void jshSetSystemTime(JsSysTime time) {
-
+  baseSystemTime = 0;
+  baseSystemTime = time - jshGetSystemTime();
 }

 /// Convert a time in Milliseconds to one in ticks.
@@ -899,6 +909,14 @@
 bool jshSleep(JsSysTime timeUntilWake) {
   /* Wake ourselves up if we're supposed to, otherwise if we're not waiting for
    any particular time, just sleep. */
+  /* Wake up minimum every 4 minutes, to ensure that we notice if the
+   * RTC is going to overflow. On nRF51 we can only easily use RTC0 for time
+   * (RTC1 gets started and stopped by app timer), and we can't get an IRQ
+   * when it overflows, so we'll have to check for overflows (which means always
+   * waking up with enough time to detect an overflow).
+   */
+  if (timeUntilWake > jshGetTimeFromMilliseconds(240))
+    timeUntilWake = jshGetTimeFromMilliseconds(240);
   if (timeUntilWake < JSSYSTIME_MAX) {
 #ifdef BLUETOOTH
     uint32_t ticks = APP_TIMER_TICKS(jshGetMillisecondsFromTime(timeUntilWake), APP_TIMER_PRESCALER);
@@ -914,6 +932,7 @@
     jsiSetSleep(JSI_SLEEP_ASLEEP);
     sd_app_evt_wait(); // Go to sleep, wait to be woken up
     jsiSetSleep(JSI_SLEEP_AWAKE);
+    jshGetSystemTime(); // check for RTC overflows
   }
 #ifdef BLUETOOTH
   // we don't care about the return codes...


dfu: Include the reset timeout as wValue to fix some hardware

--- plugins/dfu/dfu-device.c
+++ plugins/dfu/dfu-device.c
@@ -1048,6 +1048,7 @@
 dfu_device_detach (DfuDevice *device, GCancellable *cancellable, GError **error)
 {
 	DfuDevicePrivate *priv = GET_PRIVATE (device);
+	const guint16 timeout_reset_ms = 1000;
 	g_autoptr(GError) error_local = NULL;

 	g_return_val_if_fail (DFU_IS_DEVICE (device), FALSE);
@@ -1097,7 +1098,7 @@
 					    G_USB_DEVICE_REQUEST_TYPE_CLASS,
 					    G_USB_DEVICE_RECIPIENT_INTERFACE,
 					    DFU_REQUEST_DETACH,
-					    0,
+					    timeout_reset_ms,
 					    priv->iface_number,
 					    NULL, 0, NULL,
 					    priv->timeout_ms,