Diagnostic message when openning hostdb file fails

--- iocore/hostdb/P_RefCountCache.h
+++ iocore/hostdb/P_RefCountCache.h
@@ -577,7 +577,8 @@

   int fd = open(filepath.c_str(), O_RDONLY);
   if (fd < 0) {
-    return -1; // specific code for missing?
+    Warning("Unable to open file %s; [Error]: %s", filepath.c_str(), strerror(errno));
+    return -1;
   }

   // read in the header


Fixed a compile error. Apparently this code is not being used anymore.

git-svn-id: a341ccba1312b2efdbe34f40faf90581f48aa49f@21036 08b38cba-cd3b-11de-854e-f91c5b6e4272

--- modules/vapor/vpr/md/DARWIN/DynLoad/LibraryDYLD.h
+++ modules/vapor/vpr/md/DARWIN/DynLoad/LibraryDYLD.h
@@ -111,13 +111,7 @@
    /**
     * Unloads the library if one has been loaded.
     */
-   ~LibraryDYLD()
-   {
-      if ( NULL != mLibrary )
-      {
-         unload();
-      }
-   }
+   ~LibraryDYLD();

    /**
     * Overlaoded assignment operator.


another way

another way

--- opencog/query/AttentionalFocusCB.h
+++ opencog/query/AttentionalFocusCB.h
@@ -25,6 +25,8 @@

 #include "PatternMatchCallback.h"
+#include "DefaultPatternMatchCB.h"
+

 #include "DefaultPatternMatchCB.h"

@@ -33,6 +35,7 @@

 class AttentionalFocusCB: public virtual DefaultPatternMatchCB {
+

 private:
@@ -48,6 +51,7 @@
 	bool link_match(LinkPtr& lpat, LinkPtr& lsoln);
 	IncomingSet get_incoming_set(Handle h);

+
 };
 } //namespace opencog
 #endif /* _ATTENTIONALFOCUSCB_H */


codepage.c: Define functions codepageMap and codepageConvert no more than once

--- expat/xmlwf/codepage.c
+++ expat/xmlwf/codepage.c
@@ -38,9 +38,11 @@
 #  define WIN32_LEAN_AND_MEAN 1

 #  include <windows.h>
+#endif /* defined(_WIN32) */

 int
 codepageMap(int cp, int *map) {
+#if defined(_WIN32)
   int i;
   CPINFO info;
   if (! GetCPInfo(cp, &info) || info.MaxCharSize > 2)
@@ -68,32 +70,25 @@
     }
   }
   return 1;
+#else
+  UNUSED_P(cp);
+  UNUSED_P(map);
+  return 0;
+#endif
 }

 int
 codepageConvert(int cp, const char *p) {
+#if defined(_WIN32)
   unsigned short c;
   if (MultiByteToWideChar(cp, MB_PRECOMPOSED | MB_ERR_INVALID_CHARS, p, 2, &c,
                           1)
       == 1)
     return c;
   return -1;
-}
-
-#else /* not _WIN32 */
-
-int
-codepageMap(int cp, int *map) {
-  UNUSED_P(cp);
-  UNUSED_P(map);
-  return 0;
-}
-
-int
-codepageConvert(int cp, const char *p) {
+#else
   UNUSED_P(cp);
   UNUSED_P(p);
   return -1;
+#endif
 }
-
-#endif /* not _WIN32 */


baseparse: bitrate mechanics should not deal with duration update

... since that is already handled by _update_duration, or should not be done
altogether if the duration is determined by non-estimated means.

Fixes #669502.

--- libs/gst/base/gstbaseparse.c
+++ libs/gst/base/gstbaseparse.c
@@ -1433,14 +1433,6 @@
   if ((update_min || update_avg || update_max))
     gst_base_parse_post_bitrates (parse, update_min, update_avg, update_max);

-  /* If average bitrate changes that much and no valid (time) duration provided,
-   * then post a new duration message so applications can update their cached
-   * values */
-  if (update_avg && !(parse->priv->duration_fmt == GST_FORMAT_TIME &&
-          GST_CLOCK_TIME_IS_VALID (parse->priv->duration)))
-    gst_element_post_message (GST_ELEMENT (parse),
-        gst_message_new_duration (GST_OBJECT (parse), GST_FORMAT_TIME, -1));
-
 exit:
   return;
 }


Suppress GCC anonymous struct warning

Suppress GCC anonymous struct warning

--- HandmadeMath.h
+++ HandmadeMath.h
@@ -178,6 +178,10 @@
 #pragma warning(disable:4201)
 #endif

+#ifdef __GNUC__
+#pragma GCC diagnostic ignored "-Wgnu-anonymous-struct"
+#endif
+
 #ifdef __cplusplus
 extern "C"
 {


max32660: put slave-only code in `#ifdef`s

This fixes a bunch of "<method> defined but not used" build warnings
when working with a board that only uses the I2C master and not the
slave.

Also fixed various checkpatch.pl errors and warnings that appeared in
the lines that were moved.

BRANCH=none
BUG=chromium:1008568
TEST=Build a MAX32660 board that only uses the I2C master and check that
     it succeeds with no warnings. Modify it to use the slave as well
     and check that host commands still work.

Change-Id: Icee04ad6d7b641f934e56b670be8770710a41e64
Signed-off-by: Harry Cutts <1d9acf085666736c25fb5139ba37ad9d917ae7f5@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1832892
Reviewed-by: Jes Klinke <d7a45737f2d52b53995e6ff74608c5989a9d5d52@chromium.org>
Reviewed-by: Randall Spangler <62698fdbb84d1779579ee80c3f39fac22017e5bc@chromium.org>

--- chip/max32660/i2c_chip.c
+++ chip/max32660/i2c_chip.c
@@ -144,7 +144,6 @@
 };

 static i2c_req_state_t states[MXC_I2C_INSTANCES];
-static int slave_rx_remain = 0, slave_tx_remain = 0;

 /**
  * struct i2c_port_data
@@ -172,24 +171,22 @@
 static struct i2c_port_data pdata[I2C_PORT_COUNT];

 /* **** Function Prototypes **** */
-static void i2c_free_callback(int i2c_num, int error);
-static void init_i2cs(int port);
 static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed);
 static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 			    int stop, const uint8_t *data, int len,
 			    int restart);
 static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 			   int stop, uint8_t *data, int len, int restart);
+
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+static void i2c_free_callback(int i2c_num, int error);
+static void init_i2cs(int port);
 static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req);
-static void i2c_handler(mxc_i2c_regs_t *i2c);
+static void i2c_slave_handler(mxc_i2c_regs_t *i2c);
+#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */

 /* Port address for each I2C */
 static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1};
-
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
-/* IRQ for each I2C */
-static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
-#endif

 /**
  * chip_i2c_xfer() - Low Level function for I2C Master Reads and Writes.
@@ -291,6 +288,9 @@
  */
 #ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS

+/* IRQ for each I2C */
+static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
+
 /**
  * Buffer for received host command packets (including prefix byte on request,
  * and result/size on response).  After any protocol-specific headers, the
@@ -301,6 +301,7 @@
 static uint8_t *const host_buffer = host_buffer_padded + 2;
 static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
 static struct host_packet i2c_packet;
+static int slave_rx_remain, slave_tx_remain;

 static i2c_req_t req_slave;
 volatile int ec_pending_response = 0;
@@ -328,7 +329,7 @@
 	req_slave.tx_len = size + 2;

 	/* Call the handler for transmition of response packet. */
-	i2c_handler(i2c_bus_ports[I2C_PORT_EC]);
+	i2c_slave_handler(i2c_bus_ports[I2C_PORT_EC]);
 }

 /**
@@ -395,7 +396,7 @@
  */
 void I2C0_IRQHandler(void)
 {
-	i2c_handler(i2c_bus_ports[0]);
+	i2c_slave_handler(i2c_bus_ports[0]);
 }

 /**
@@ -403,485 +404,11 @@
  */
 void I2C1_IRQHandler(void)
 {
-	i2c_handler(i2c_bus_ports[1]);
+	i2c_slave_handler(i2c_bus_ports[1]);
 }

 DECLARE_IRQ(EC_I2C0_IRQn, I2C0_IRQHandler, 1);
 DECLARE_IRQ(EC_I2C1_IRQn, I2C1_IRQHandler, 1);
-
-/**
- * init_i2cs() - Async Handler for I2C Slave driver.
- * @port: I2C port number to initialize.
- */
-void init_i2cs(int port)
-{
-	int error;
-
-	if ((error = i2c_init_peripheral(i2c_bus_ports[port], I2C_STD_MODE)) !=
-	    EC_SUCCESS) {
-		while (1)
-			;
-	}
-	/* Prepare SlaveAsync */
-	req_slave.addr = CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS;
-	req_slave.tx_data = host_buffer; /* transmitted to host */
-	req_slave.tx_len = -1;		 /* Nothing to send. */
-	req_slave.rx_data = host_buffer; /* received from host */
-	req_slave.rx_len = I2C_MAX_HOST_PACKET_SIZE;
-	req_slave.restart = 0;
-	req_slave.callback = i2c_chip_callback;
-
-	if ((error = i2c_slave_async(i2c_bus_ports[port], &req_slave)) !=
-	    EC_SUCCESS) {
-		while (1)
-			;
-	}
-
-	task_enable_irq(i2c_bus_irqs[port]);
-}
-
-#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
-
-/**
- * i2c_set_speed() - Set the transfer speed of the selected I2C.
- * @i2c: Pointer to I2C peripheral.
- * @i2cspeed: Speed to set.
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
-{
-	uint32_t ticks;
-	uint32_t ticks_lo;
-	uint32_t ticks_hi;
-	uint32_t time_pclk;
-	uint32_t target_bus_freq;
-	uint32_t time_scl_min;
-	uint32_t clock_low_min;
-	uint32_t clock_high_min;
-	uint32_t clock_min;
-
-	if (i2cspeed == I2C_HS_MODE) {
-		/* Compute dividers for high speed mode. */
-		time_pclk = 1000000 / (PeripheralClock / 1000);
-
-		target_bus_freq = i2cspeed;
-		if (target_bus_freq < 1000) {
-			return EC_ERROR_INVAL;
-		}
-
-		time_scl_min = 1000000 / (target_bus_freq / 1000);
-		clock_low_min =
-			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
-			 time_pclk) - 1;
-		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
-				  T_AF_MIN) /
-				  time_pclk) - 1;
-		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
-
-		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
-				   ? (clock_low_min)
-				   : (clock_min - clock_high_min);
-		ticks_hi = clock_high_min;
-
-		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
-				 MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
-		    (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >>
-				 MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
-			return EC_ERROR_INVAL;
-		}
-
-		/* Write results to destination registers. */
-		i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) |
-			      (ticks_hi << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
-
-		/* Still need to load dividers for the preamble that each
-		 * high-speed transaction starts with. Switch setting to fast
-		 * mode and fall out of if statement.
-		 */
-		i2cspeed = I2C_FAST_MODE;
-	}
-
-	/* Get the number of periph clocks needed to achieve selected speed. */
-	ticks = PeripheralClock / i2cspeed;
-
-	/* For a 50% duty cycle, half the ticks will be spent high and half will
-	 * be low.
-	 */
-	ticks_hi = (ticks >> 1) - 1;
-	ticks_lo = (ticks >> 1) - 1;
-
-	/* Account for rounding error in odd tick counts. */
-	if (ticks & 1) {
-		ticks_hi++;
-	}
-
-	/* Will results fit into 9 bit registers?  (ticks_hi will always be >=
-	 * ticks_lo.  No need to check ticks_lo.)
-	 */
-	if (ticks_hi > 0x1FF) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* 0 is an invalid value for the destination registers. (ticks_hi will
-	 * always be >= ticks_lo.  No need to check ticks_hi.)
-	 */
-	if (ticks_lo == 0) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Write results to destination registers. */
-	i2c->clk_lo = ticks_lo;
-	i2c->clk_hi = ticks_hi;
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_init_peripheral() - Initialize and enable I2C.
- * @i2c:      Pointer to I2C peripheral registers.
- * @i2cspeed: Desired speed (I2C mode).
- * @sys_cfg:  System configuration object.
- *
- * Return EC_SUCCESS, or non-zero if error.
- */
-static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
-{
-	/**
-	 * Always disable the HW autoflush on data NACK and let the SW handle
-	 * the flushing.
-	 */
-	i2c->tx_ctrl0 |= 0x20;
-
-	states[MXC_I2C_GET_IDX(i2c)].num_wr = 0;
-
-	i2c->ctrl = 0; /* clear configuration bits */
-	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C */
-	i2c->master_ctrl = 0; /* clear master configuration bits */
-	i2c->status = 0; /* clear status bits */
-
-	i2c->ctrl = 0; /* clear configuration bits */
-	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C */
-	i2c->master_ctrl = 0; /* clear master configuration bits */
-	i2c->status = 0; /* clear status bits */
-
-	/* Check for HS mode */
-	if (i2cspeed == I2C_HS_MODE) {
-		i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; /* Enable HS mode */
-	}
-
-	/* Disable and clear interrupts */
-	i2c->int_en0 = 0;
-	i2c->int_en1 = 0;
-	i2c->int_fl0 = i2c->int_fl0;
-	i2c->int_fl1 = i2c->int_fl1;
-
-	i2c->timeout = 0x0; /* set timeout */
-	i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; /* clear the RX FIFO */
-	i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; /* clear the TX FIFO */
-
-	return i2c_set_speed(i2c, i2cspeed);
-}
-
-/**
- * i2c_master_write()
- * @i2c:  Pointer to I2C regs.
- * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1.
- *        Only supports 7-bit addressing. LSb of the given address
- *        will be used as the read/write bit, the \p addr <b>will
- *        not be shifted. Used for both master and
- *        slave transactions.
- * @data: Data to be written.
- * @len:  Number of bytes to Write.
- * @restart: 0 to send a stop bit at the end of the transaction,
- *	     otherwise send a restart.
- *
- * Will block until transaction is complete.
- *
- * Return  EC_SUCCESS, or non-zero if error.
- */
-static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len, int restart)
-{
-	if (len == 0) {
-		return EC_SUCCESS;
-	}
-
-	/* Clear the interrupt flag */
-	i2c->int_fl0 = i2c->int_fl0;
-
-	/* Make sure the I2C has been initialized */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable master mode */
-	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
-
-	/* Load FIFO with slave address for WRITE and as much data as we can */
-	while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
-	}
-
-	if (start) {
-		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
-		 * to the left and make room for the write bit.
-		 */
-		i2c->fifo = (addr << 1) & ~(0x1);
-	}
-
-	while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-		i2c->fifo = *data++;
-		len--;
-	}
-	/* Generate Start signal */
-	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
-	}
-
-	/* Write remaining data to FIFO */
-	while (len > 0) {
-		/* Check for errors */
-		if (i2c->int_fl0 & I2C_ERROR) {
-			/* Set the stop bit */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-			return EC_ERROR_UNKNOWN;
-		}
-
-		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
-			i2c->fifo = *data++;
-			len--;
-		}
-	}
-	/* Check if Repeated Start requested */
-	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
-	} else {
-		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-		}
-	}
-
-	if (stop) {
-		/* Wait for Done */
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear Done interrupt flag */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
-	}
-
-	/* Wait for Stop if requested and there is no restart. */
-	if (stop && !restart) {
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear stop interrupt flag */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
-	}
-
-	/* Check for errors */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_master_read()
- * @i2c:        Pointer to I2C regs.
- * @addr:       I2C 7-bit Address right aligned, bit 6 to bit 0.
- * @data:       Data to be written.
- * @len:        Number of bytes to Write.
- * @restart:    0 to send a stop bit at the end of the transaction,
- * 	       otherwise send a restart.
- *
- * Will block until transaction is complete.
- *
- * Return:     EC_SUCCESS if successful, otherwise returns a common error code
- */
-static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart)
-{
-	volatile int length = len;
-	int interactive_receive_mode;
-
-	if (len == 0) {
-		return EC_SUCCESS;
-	}
-
-	if (len > 255) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Clear the interrupt flag */
-	i2c->int_fl0 = i2c->int_fl0;
-
-	/* Make sure the I2C has been initialized */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* Enable master mode */
-	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
-
-	if (stop) {
-		/* Set receive count */
-		i2c->ctrl &= ~MXC_F_I2C_CTRL_RX_MODE;
-		i2c->rx_ctrl1 = len;
-		interactive_receive_mode = 0;
-	} else {
-		i2c->ctrl |= MXC_F_I2C_CTRL_RX_MODE;
-		i2c->rx_ctrl1 = 1;
-		interactive_receive_mode = 1;
-	}
-
-	/* Load FIFO with slave address */
-	if (start) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
-		while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
-		}
-		/**
-		 * The slave address is right-aligned, bits 6 to 0, shift
-		 * to the left and make room for the read bit.
-		 */
-		i2c->fifo = ((addr << 1) | 1);
-	}
-
-	/* Wait for all data to be received or error. */
-	while (length > 0) {
-		/* Check for errors */
-		if (i2c->int_fl0 & I2C_ERROR) {
-			/* Set the stop bit */
-			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-			return EC_ERROR_UNKNOWN;
-		}
-
-		/* if in interactive receive mode then ack each received byte */
-		if (interactive_receive_mode) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
-				;
-			if (i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE) {
-				/* read the data */
-				*data++ = i2c->fifo;
-				length--;
-				/* clear the bit */
-				if (length != 1) {
-					i2c->int_fl0 =
-						MXC_F_I2C_INT_EN0_RX_MODE;
-				}
-			}
-		} else {
-			if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
-				*data++ = i2c->fifo;
-				length--;
-			}
-		}
-	}
-
-	if (restart) {
-		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
-	} else {
-		if (stop) {
-			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-		}
-	}
-
-	/* Wait for Done */
-	if (stop) {
-		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
-			/* Check for errors */
-			if (i2c->int_fl0 & I2C_ERROR) {
-				/* Set the stop bit */
-				i2c->master_ctrl &=
-					~(MXC_F_I2C_MASTER_CTRL_RESTART);
-				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
-				return EC_ERROR_UNKNOWN;
-			}
-		}
-		/* Clear Done interrupt flag */
-		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
-	}
-
-	/* Wait for Stop */
-	if (!restart) {
-		if (stop) {
-			while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
-				/* Check for errors */
-				if (i2c->int_fl0 & I2C_ERROR) {
-					/* Set the stop bit */
-					i2c->master_ctrl &= ~(
-						MXC_F_I2C_MASTER_CTRL_RESTART);
-					i2c->master_ctrl |=
-						MXC_F_I2C_MASTER_CTRL_STOP;
-					return EC_ERROR_UNKNOWN;
-				}
-			}
-			/* Clear Stop interrupt flag */
-			i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
-		}
-	}
-
-	/* Check for errors */
-	if (i2c->int_fl0 & I2C_ERROR) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/**
- * i2c_slave_async() - Slave Read and Write Asynchronous.
- * @i2c:   Pointer to I2C regs.
- * @req:   Request for an I2C transaction.
- *
- * Return EC_SUCCESS if successful, otherwise returns a common error code.
- */
-static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
-{
-	/* Make sure the I2C has been initialized. */
-	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
-		return EC_ERROR_UNKNOWN;
-	}
-
-	states[MXC_I2C_GET_IDX(i2c)].req = req;
-
-	/* Disable master mode */
-	i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST);
-	/* Set the Slave Address in the I2C peripheral register. */
-	i2c->slave_addr = req->addr;
-
-	/* Clear the byte counters */
-	req->tx_num = 0;
-	req->rx_num = 0;
-
-	/* Disable and clear the interrupts. */
-	i2c->int_en0 = 0;
-	i2c->int_en1 = 0;
-	i2c->int_fl0 = i2c->int_fl0;
-	i2c->int_fl1 = i2c->int_fl1;
-	/* Only enable the I2C Address match interrupt. */
-	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
-
-	return EC_SUCCESS;
-}

 /**
  * i2c_slave_read() - Handles async read request from the I2c master.
@@ -960,9 +487,8 @@
 		 * Fulfill the EC HOST reading of extra bytes by sending the
 		 * EC_PADDING_BYTE.
 		 */
-		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL))
 			i2c->fifo = EC_PADDING_BYTE;
-		}
 		/* set tx threshold to zero */
 		i2c->tx_ctrl0 =
 			((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
@@ -1056,6 +582,15 @@
 	return EC_SUCCESS;
 }

+/**
+ * i2c_slave_handler() - I2C interrupt handler.
+ * @i2c: Base address of the I2C module.
+ *
+ * This function should be called by the application from the interrupt
+ * handler if I2C interrupts are enabled. Alternately, this function
+ * can be periodically called by the application if I2C interrupts are
+ * disabled.
+ */
 static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
 {
 	uint32_t int_flags;
@@ -1113,11 +648,10 @@

 	slave_rx_remain = req->rx_len - req->rx_num;
 	/* determine if there is any data ready to transmit to the EC HOST */
-	if (req->tx_len != -1) {
+	if (req->tx_len != -1)
 		slave_tx_remain = req->tx_len - states[i2c_num].num_wr;
-	} else {
+	else
 		slave_tx_remain = 0;
-	}

 	/* Check for Stop interrupt */
 	if (int_flags & MXC_F_I2C_INT_FL0_STOP) {
@@ -1189,38 +723,21 @@
 		return;
 	}

-	if (states[i2c_num].slave_state != I2C_SLAVE_ADDR_MATCH) {
+	if (states[i2c_num].slave_state != I2C_SLAVE_ADDR_MATCH)
 		return;
-	}
 	/**
 	 * Check if Master Read has been called and if there is a
 	 * tx_data buffer
 	 */
 	if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
 		status = i2c_slave_read(i2c, req, int_flags);
-		if (status != EC_SUCCESS) {
+		if (status != EC_SUCCESS)
 			return;
-		}
 	} else {
 		status = i2c_slave_write(i2c, req, int_flags);
-		if (status != EC_SUCCESS) {
+		if (status != EC_SUCCESS)
 			return;
-		}
-	}
-}
-
-/**
- * i2c_handler() - I2C interrupt handler.
- * @i2c: Base address of the I2C module.
- *
- * This function should be called by the application from the interrupt
- * handler if I2C interrupts are enabled. Alternately, this function
- * can be periodically called by the application if I2C interrupts are
- * disabled.
- */
-static void i2c_handler(mxc_i2c_regs_t *i2c)
-{
-	i2c_slave_handler(i2c);
+	}
 }

 static void i2c_free_callback(int i2c_num, int error)
@@ -1229,7 +746,482 @@
 	i2c_req_t *temp_req = states[i2c_num].req;

 	/* Callback if not NULL */
-	if (temp_req->callback != NULL) {
+	if (temp_req->callback != NULL)
 		temp_req->callback(temp_req, error);
-	}
-}
+}
+
+/**
+ * init_i2cs() - Async Handler for I2C Slave driver.
+ * @port: I2C port number to initialize.
+ */
+void init_i2cs(int port)
+{
+	int error;
+
+	slave_rx_remain = 0;
+	slave_tx_remain = 0;
+
+	error = i2c_init_peripheral(i2c_bus_ports[port], I2C_STD_MODE);
+	if (error != EC_SUCCESS) {
+		while (1)
+			;
+	}
+	/* Prepare SlaveAsync */
+	req_slave.addr = CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS;
+	req_slave.tx_data = host_buffer; /* transmitted to host */
+	req_slave.tx_len = -1;		 /* Nothing to send. */
+	req_slave.rx_data = host_buffer; /* received from host */
+	req_slave.rx_len = I2C_MAX_HOST_PACKET_SIZE;
+	req_slave.restart = 0;
+	req_slave.callback = i2c_chip_callback;
+
+	error = i2c_slave_async(i2c_bus_ports[port], &req_slave);
+	if (error != EC_SUCCESS) {
+		while (1)
+			;
+	}
+
+	task_enable_irq(i2c_bus_irqs[port]);
+}
+
+/**
+ * i2c_slave_async() - Slave Read and Write Asynchronous.
+ * @i2c:   Pointer to I2C regs.
+ * @req:   Request for an I2C transaction.
+ *
+ * Return EC_SUCCESS if successful, otherwise returns a common error code.
+ */
+static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+{
+	/* Make sure the I2C has been initialized. */
+	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN))
+		return EC_ERROR_UNKNOWN;
+
+	states[MXC_I2C_GET_IDX(i2c)].req = req;
+
+	/* Disable master mode */
+	i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST);
+	/* Set the Slave Address in the I2C peripheral register. */
+	i2c->slave_addr = req->addr;
+
+	/* Clear the byte counters */
+	req->tx_num = 0;
+	req->rx_num = 0;
+
+	/* Disable and clear the interrupts. */
+	i2c->int_en0 = 0;
+	i2c->int_en1 = 0;
+	i2c->int_fl0 = i2c->int_fl0;
+	i2c->int_fl1 = i2c->int_fl1;
+	/* Only enable the I2C Address match interrupt. */
+	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
+
+	return EC_SUCCESS;
+}
+
+#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
+
+/**
+ * i2c_set_speed() - Set the transfer speed of the selected I2C.
+ * @i2c: Pointer to I2C peripheral.
+ * @i2cspeed: Speed to set.
+ *
+ * Return EC_SUCCESS, or non-zero if error.
+ */
+static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
+{
+	uint32_t ticks;
+	uint32_t ticks_lo;
+	uint32_t ticks_hi;
+	uint32_t time_pclk;
+	uint32_t target_bus_freq;
+	uint32_t time_scl_min;
+	uint32_t clock_low_min;
+	uint32_t clock_high_min;
+	uint32_t clock_min;
+
+	if (i2cspeed == I2C_HS_MODE) {
+		/* Compute dividers for high speed mode. */
+		time_pclk = 1000000 / (PeripheralClock / 1000);
+
+		target_bus_freq = i2cspeed;
+		if (target_bus_freq < 1000) {
+			return EC_ERROR_INVAL;
+		}
+
+		time_scl_min = 1000000 / (target_bus_freq / 1000);
+		clock_low_min =
+			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
+			 time_pclk) - 1;
+		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
+				  T_AF_MIN) /
+				  time_pclk) - 1;
+		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
+
+		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
+				   ? (clock_low_min)
+				   : (clock_min - clock_high_min);
+		ticks_hi = clock_high_min;
+
+		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
+				 MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
+		    (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >>
+				 MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
+			return EC_ERROR_INVAL;
+		}
+
+		/* Write results to destination registers. */
+		i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) |
+			      (ticks_hi << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
+
+		/* Still need to load dividers for the preamble that each
+		 * high-speed transaction starts with. Switch setting to fast
+		 * mode and fall out of if statement.
+		 */
+		i2cspeed = I2C_FAST_MODE;
+	}
+
+	/* Get the number of periph clocks needed to achieve selected speed. */
+	ticks = PeripheralClock / i2cspeed;
+
+	/* For a 50% duty cycle, half the ticks will be spent high and half will
+	 * be low.
+	 */
+	ticks_hi = (ticks >> 1) - 1;
+	ticks_lo = (ticks >> 1) - 1;
+
+	/* Account for rounding error in odd tick counts. */
+	if (ticks & 1) {
+		ticks_hi++;
+	}
+
+	/* Will results fit into 9 bit registers?  (ticks_hi will always be >=
+	 * ticks_lo.  No need to check ticks_lo.)
+	 */
+	if (ticks_hi > 0x1FF) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* 0 is an invalid value for the destination registers. (ticks_hi will
+	 * always be >= ticks_lo.  No need to check ticks_hi.)
+	 */
+	if (ticks_lo == 0) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Write results to destination registers. */
+	i2c->clk_lo = ticks_lo;
+	i2c->clk_hi = ticks_hi;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_init_peripheral() - Initialize and enable I2C.
+ * @i2c:      Pointer to I2C peripheral registers.
+ * @i2cspeed: Desired speed (I2C mode).
+ * @sys_cfg:  System configuration object.
+ *
+ * Return EC_SUCCESS, or non-zero if error.
+ */
+static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
+{
+	/**
+	 * Always disable the HW autoflush on data NACK and let the SW handle
+	 * the flushing.
+	 */
+	i2c->tx_ctrl0 |= 0x20;
+
+	states[MXC_I2C_GET_IDX(i2c)].num_wr = 0;
+
+	i2c->ctrl = 0; /* clear configuration bits */
+	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C */
+	i2c->master_ctrl = 0; /* clear master configuration bits */
+	i2c->status = 0; /* clear status bits */
+
+	i2c->ctrl = 0; /* clear configuration bits */
+	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C */
+	i2c->master_ctrl = 0; /* clear master configuration bits */
+	i2c->status = 0; /* clear status bits */
+
+	/* Check for HS mode */
+	if (i2cspeed == I2C_HS_MODE) {
+		i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; /* Enable HS mode */
+	}
+
+	/* Disable and clear interrupts */
+	i2c->int_en0 = 0;
+	i2c->int_en1 = 0;
+	i2c->int_fl0 = i2c->int_fl0;
+	i2c->int_fl1 = i2c->int_fl1;
+
+	i2c->timeout = 0x0; /* set timeout */
+	i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; /* clear the RX FIFO */
+	i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; /* clear the TX FIFO */
+
+	return i2c_set_speed(i2c, i2cspeed);
+}
+
+/**
+ * i2c_master_write()
+ * @i2c:  Pointer to I2C regs.
+ * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *        Only supports 7-bit addressing. LSb of the given address
+ *        will be used as the read/write bit, the \p addr <b>will
+ *        not be shifted. Used for both master and
+ *        slave transactions.
+ * @data: Data to be written.
+ * @len:  Number of bytes to Write.
+ * @restart: 0 to send a stop bit at the end of the transaction,
+ *	     otherwise send a restart.
+ *
+ * Will block until transaction is complete.
+ *
+ * Return  EC_SUCCESS, or non-zero if error.
+ */
+static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			    int stop, const uint8_t *data, int len, int restart)
+{
+	if (len == 0) {
+		return EC_SUCCESS;
+	}
+
+	/* Clear the interrupt flag */
+	i2c->int_fl0 = i2c->int_fl0;
+
+	/* Make sure the I2C has been initialized */
+	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Enable master mode */
+	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+	/* Load FIFO with slave address for WRITE and as much data as we can */
+	while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
+	}
+
+	if (start) {
+		/**
+		 * The slave address is right-aligned, bits 6 to 0, shift
+		 * to the left and make room for the write bit.
+		 */
+		i2c->fifo = (addr << 1) & ~(0x1);
+	}
+
+	while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+		i2c->fifo = *data++;
+		len--;
+	}
+	/* Generate Start signal */
+	if (start) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+	}
+
+	/* Write remaining data to FIFO */
+	while (len > 0) {
+		/* Check for errors */
+		if (i2c->int_fl0 & I2C_ERROR) {
+			/* Set the stop bit */
+			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			return EC_ERROR_UNKNOWN;
+		}
+
+		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+			i2c->fifo = *data++;
+			len--;
+		}
+	}
+	/* Check if Repeated Start requested */
+	if (restart) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+	} else {
+		if (stop) {
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+		}
+	}
+
+	if (stop) {
+		/* Wait for Done */
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
+			/* Check for errors */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit */
+				i2c->master_ctrl &=
+					~(MXC_F_I2C_MASTER_CTRL_RESTART);
+				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
+			}
+		}
+		/* Clear Done interrupt flag */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
+	}
+
+	/* Wait for Stop if requested and there is no restart. */
+	if (stop && !restart) {
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
+			/* Check for errors */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit */
+				i2c->master_ctrl &=
+					~(MXC_F_I2C_MASTER_CTRL_RESTART);
+				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
+			}
+		}
+		/* Clear stop interrupt flag */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
+	}
+
+	/* Check for errors */
+	if (i2c->int_fl0 & I2C_ERROR) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_master_read()
+ * @i2c:        Pointer to I2C regs.
+ * @addr:       I2C 7-bit Address right aligned, bit 6 to bit 0.
+ * @data:       Data to be written.
+ * @len:        Number of bytes to Write.
+ * @restart:    0 to send a stop bit at the end of the transaction,
+ * 	       otherwise send a restart.
+ *
+ * Will block until transaction is complete.
+ *
+ * Return:     EC_SUCCESS if successful, otherwise returns a common error code
+ */
+static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			   int stop, uint8_t *data, int len, int restart)
+{
+	volatile int length = len;
+	int interactive_receive_mode;
+
+	if (len == 0) {
+		return EC_SUCCESS;
+	}
+
+	if (len > 255) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Clear the interrupt flag */
+	i2c->int_fl0 = i2c->int_fl0;
+
+	/* Make sure the I2C has been initialized */
+	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Enable master mode */
+	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+	if (stop) {
+		/* Set receive count */
+		i2c->ctrl &= ~MXC_F_I2C_CTRL_RX_MODE;
+		i2c->rx_ctrl1 = len;
+		interactive_receive_mode = 0;
+	} else {
+		i2c->ctrl |= MXC_F_I2C_CTRL_RX_MODE;
+		i2c->rx_ctrl1 = 1;
+		interactive_receive_mode = 1;
+	}
+
+	/* Load FIFO with slave address */
+	if (start) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+		while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
+		}
+		/**
+		 * The slave address is right-aligned, bits 6 to 0, shift
+		 * to the left and make room for the read bit.
+		 */
+		i2c->fifo = ((addr << 1) | 1);
+	}
+
+	/* Wait for all data to be received or error. */
+	while (length > 0) {
+		/* Check for errors */
+		if (i2c->int_fl0 & I2C_ERROR) {
+			/* Set the stop bit */
+			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			return EC_ERROR_UNKNOWN;
+		}
+
+		/* if in interactive receive mode then ack each received byte */
+		if (interactive_receive_mode) {
+			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
+				;
+			if (i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE) {
+				/* read the data */
+				*data++ = i2c->fifo;
+				length--;
+				/* clear the bit */
+				if (length != 1) {
+					i2c->int_fl0 =
+						MXC_F_I2C_INT_EN0_RX_MODE;
+				}
+			}
+		} else {
+			if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+				*data++ = i2c->fifo;
+				length--;
+			}
+		}
+	}
+
+	if (restart) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+	} else {
+		if (stop) {
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+		}
+	}
+
+	/* Wait for Done */
+	if (stop) {
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
+			/* Check for errors */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit */
+				i2c->master_ctrl &=
+					~(MXC_F_I2C_MASTER_CTRL_RESTART);
+				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
+			}
+		}
+		/* Clear Done interrupt flag */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
+	}
+
+	/* Wait for Stop */
+	if (!restart) {
+		if (stop) {
+			while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
+				/* Check for errors */
+				if (i2c->int_fl0 & I2C_ERROR) {
+					/* Set the stop bit */
+					i2c->master_ctrl &= ~(
+						MXC_F_I2C_MASTER_CTRL_RESTART);
+					i2c->master_ctrl |=
+						MXC_F_I2C_MASTER_CTRL_STOP;
+					return EC_ERROR_UNKNOWN;
+				}
+			}
+			/* Clear Stop interrupt flag */
+			i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
+		}
+	}
+
+	/* Check for errors */
+	if (i2c->int_fl0 & I2C_ERROR) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}


Get the exec children back in our progress group/session, and unblock signals to them.

--- adsbus/exec.c
+++ adsbus/exec.c
@@ -117,8 +117,6 @@
 }

 static void __attribute__ ((noreturn)) exec_child(const struct exec *exec, int data_fd, int log_fd) {
-	assert(setsid() != -1);
-	// We leave stderr open from child to parent
 	// Other than that, fds should have CLOEXEC set
 	if (data_fd != STDIN_FILENO) {
 		assert(dup2(data_fd, STDIN_FILENO) == STDIN_FILENO);
@@ -133,6 +131,11 @@
 		assert(dup2(log_fd, STDERR_FILENO) == STDERR_FILENO);
 		assert(!close(log_fd));
 	}
+
+	sigset_t sigmask;
+	assert(!sigemptyset(&sigmask));
+	assert(!sigprocmask(SIG_SETMASK, &sigmask, NULL));
+
 	assert(!execl("/bin/sh", "sh", "-c", exec->command, NULL));
 	abort();
 }


Fix C warning

Fix C warning

--- ext/appsignal_extension.c
+++ ext/appsignal_extension.c
@@ -18,9 +18,9 @@
 }

 static VALUE get_server_state(VALUE self, VALUE key) {
-  Check_Type(key, T_STRING);
-
   char * ptr = appsignal_get_server_state(StringValueCStr(key));
+
+  Check_Type(key, T_STRING);

   if (ptr) {
     return rb_str_new2(ptr);


remove elan_mmcr, I'm not sure I understand what it did here in the first place.

--- sys/amd64/include/md_var.h
+++ sys/amd64/include/md_var.h
@@ -47,7 +47,6 @@
 extern	u_int	cpu_id;
 extern	u_int	cpu_procinfo;
 extern	char	cpu_vendor[];
-extern	uint16_t *elan_mmcr;
 extern	char	kstack[];
 extern	char	sigcode[];
 extern	int	szsigcode;


Update plot_data when resuming

Update plot_data when resuming

--- afl-fuzz.c
+++ afl-fuzz.c
@@ -7494,18 +7494,36 @@

   /* Gnuplot output file. */

+  int oflag = O_WRONLY | O_BINARY | O_CREAT;
   tmp = alloc_printf("%s\\plot_data", out_dir);
-  fd = open(tmp, O_WRONLY | O_BINARY | O_CREAT | O_EXCL, DEFAULT_PERMISSION);
-  if (fd < 0) PFATAL("Unable to create '%s'", tmp);
-  ck_free(tmp);
-
-  plot_file = fdopen(fd, "w");
-  if (!plot_file) PFATAL("fdopen() failed");
-
-  fprintf(plot_file, "# unix_time, cycles_done, cur_path, paths_total, "
+
+  if(!in_place_resume) {
+
+    fd = _open(tmp, oflag | O_EXCL, DEFAULT_PERMISSION);
+    if (fd < 0) PFATAL("Unable to create '%s'", tmp);
+    ck_free(tmp);
+
+    plot_file = fdopen(fd, "w");
+    if (!plot_file) PFATAL("fdopen() failed");
+
+    fprintf(plot_file, "# unix_time, cycles_done, cur_path, paths_total, "
                      "pending_total, pending_favs, map_size, unique_crashes, "
                      "unique_hangs, max_depth, execs_per_sec\n");
                      /* ignore errors */
+  } else {
+
+    fd = _open(tmp, oflag, DEFAULT_PERMISSION);
+    if (fd < 0) PFATAL("Unable to create '%s'", tmp);
+    ck_free(tmp);
+
+    plot_file = fdopen(fd, "w");
+    if (!plot_file) PFATAL("fdopen() failed");
+
+    fseek(plot_file, 0, SEEK_END);
+
+  }
+
+  fflush(plot_file);

   tmp = alloc_printf("%s\\drcache", out_dir);
   if (mkdir(tmp)) PFATAL("Unable to create '%s'", tmp);


implemented callbacks

implemented callbacks

--- opencog/query/AttentionalFocusCB.h
+++ opencog/query/AttentionalFocusCB.h
@@ -37,6 +37,7 @@
 	bool node_match(Handle& node1, Handle& node2);
 	bool link_match(LinkPtr& lpat, LinkPtr& lsoln);
 	IncomingSet get_incoming_set(Handle h);
+
 };
 } //namespace opencog
 #endif /* _ATTENTIONALFOCUSCB_H */


Get it starting...

Get it starting...

--- KERN/usrsctp/usrsctplib/netinet/sctp_callout.c
+++ KERN/usrsctp/usrsctplib/netinet/sctp_callout.c
@@ -37,7 +37,7 @@
 /*
  * Callout/Timer routines for OS that doesn't have them
  */
-#ifdef __APPLE__
+#if defined(__APPLE__) || defined(__Userspace__)
 int ticks = 0;
 #else
 extern int ticks;