[mini2440]fix no down event problem, ugly implement,need consider move event

git-svn-id: 839522a79b1d56a78fa446d2fd3a0c499f8e535e@539 bbd45198-f89e-11dd-88c7-29a3b14d5316

--- bsp/mini2440/touch.c
+++ bsp/mini2440/touch.c
@@ -69,20 +69,20 @@
 #include <rtgui/event.h>
 void report_touch_input(int updown)
 {
-	long tmp;
+	long xp, yp;
 	struct rtgui_event_mouse emouse;

-	ts.xp >>= ts.shift;
-	ts.yp >>= ts.shift;
-
-	ts.xp = 240 * (ts.xp-X_MIN)/(X_MAX-X_MIN);
-	ts.yp = 320 - (320*(ts.yp-Y_MIN)/(Y_MAX-Y_MIN));
+	xp = ts.xp >> ts.shift;
+	yp = ts.yp >> ts.shift;
+
+	xp = 240 * (xp-X_MIN)/(X_MAX-X_MIN);
+	yp = 320 - (320*(yp-Y_MIN)/(Y_MAX-Y_MIN));

 	emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
 	emouse.parent.sender = RT_NULL;

-	emouse.x = ts.xp;
-	emouse.y = ts.yp;
+	emouse.x = xp;
+	emouse.y = yp;

 	/* set emouse button */
 	if (updown)
@@ -95,7 +95,7 @@
 	}

 	/* rt_kprintf("touch %s: ts.x: %d, ts.y: %d, count:%d\n", updown? "down" : "up",
-		ts.xp, ts.yp, ts.count); */
+		xp, yp, ts.count); */

 	emouse.button |= RTGUI_MOUSE_BUTTON_LEFT;

@@ -170,6 +170,7 @@
 		if (ts.xp >= 0 && ts.yp >= 0)
 		{
 		#ifdef RT_USING_RTGUI
+			report_touch_input(1);
 			report_touch_input(0);
 			first_down_report = 1;
 		#endif


cpufreq: Remove cpufreq_update_policy()

cpufreq: Remove cpufreq_update_policy()

cpufreq_update_policy() was kept as a separate routine earlier as it was
handling migration of sysfs directories, which isn't the case anymore.
It is only updating policy->cpu now and is called by a single caller.

The WARN_ON() isn't really required anymore, as we are just updating the
cpu now, not moving the sysfs directories.

Signed-off-by: Viresh Kumar <5ff32272b3d9f86512eddc8e0af523fc6f7924e5@linaro.org>
Signed-off-by: Rafael J. Wysocki <27ffc44a8ec6a212fba98cfc3246c6ce8ab131e0@intel.com>

--- drivers/cpufreq/cpufreq.c
+++ drivers/cpufreq/cpufreq.c
@@ -1129,6 +1129,10 @@
 	if (likely(policy)) {
 		/* Policy should be inactive here */
 		WARN_ON(!policy_is_inactive(policy));
+
+		down_write(&policy->rwsem);
+		policy->cpu = cpu;
+		up_write(&policy->rwsem);
 	}

 	return policy;
@@ -1223,16 +1227,6 @@
 	free_cpumask_var(policy->related_cpus);
 	free_cpumask_var(policy->cpus);
 	kfree(policy);
-}
-
-static void update_policy_cpu(struct cpufreq_policy *policy, unsigned int cpu)
-{
-	if (WARN_ON(cpu == policy->cpu))
-		return;
-
-	down_write(&policy->rwsem);
-	policy->cpu = cpu;
-	up_write(&policy->rwsem);
 }

 /**
@@ -1286,15 +1280,6 @@
 		if (!policy)
 			goto nomem_out;
 	}
-
-	/*
-	 * In the resume path, since we restore a saved policy, the assignment
-	 * to policy->cpu is like an update of the existing policy, rather than
-	 * the creation of a brand new one. So we need to perform this update
-	 * by invoking update_policy_cpu().
-	 */
-	if (recover_policy && cpu != policy->cpu)
-		update_policy_cpu(policy, cpu);

 	cpumask_copy(policy->cpus, cpumask_of(cpu));


cpufreq: Fix white space in __cpufreq_remove_dev()

Align closing brace '}' of an if block.

[rjw: Subject and changelog]
Signed-off-by: Viresh Kumar <5ff32272b3d9f86512eddc8e0af523fc6f7924e5@linaro.org>
Signed-off-by: Rafael J. Wysocki <27ffc44a8ec6a212fba98cfc3246c6ce8ab131e0@intel.com>
Git-commit: edab2fbc21b9eb37007ad8bffe1159d536bbb451
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Junjie Wu <bb05168246ed1a6b66d0e7b1ffb0c5e3707764ca@codeaurora.org>

--- drivers/cpufreq/cpufreq.c
+++ drivers/cpufreq/cpufreq.c
@@ -1282,7 +1282,7 @@
 						__func__);
 				return ret;
 			}
-	}
+		}

 		if (!frozen) {
 			lock_policy_rwsem_read(cpu);


remove undefined function

remove undefined function

--- apps/exampleViewer/widgets/imgui_impl_glfw_gl3.h
+++ apps/exampleViewer/widgets/imgui_impl_glfw_gl3.h
@@ -24,5 +24,4 @@
 void ImGui_ImplGlfwGL3_MouseButtonCallback(GLFWwindow* window, int button, int action, int mods);
 void ImGui_ImplGlfwGL3_ScrollCallback(GLFWwindow* window, double xoffset, double yoffset);
 void ImGui_ImplGlfwGL3_KeyCallback(GLFWwindow* window, int key, int scancode, int action, int mods);
-void ImGui_ImplGlfwGL3_CharCallback(GLFWwindow* window, unsigned int c);


[CPUFREQ] Fix missing cpufreq_cpu_put() call in ->store

refactor to use gotos instead of explicit exit paths

Signed-off-by: Dave Jones <d5ec0d24602845f6f4b6a35ef729998d1fba5507@redhat.com>

--- drivers/cpufreq/cpufreq.c
+++ drivers/cpufreq/cpufreq.c
@@ -696,13 +696,13 @@
 {
 	struct cpufreq_policy * policy = to_policy(kobj);
 	struct freq_attr * fattr = to_attr(attr);
-	ssize_t ret;
+	ssize_t ret = -EINVAL;
 	policy = cpufreq_cpu_get(policy->cpu);
 	if (!policy)
-		return -EINVAL;
+		goto no_policy;

 	if (lock_policy_rwsem_write(policy->cpu) < 0)
-		return -EINVAL;
+		goto fail;

 	if (fattr->store)
 		ret = fattr->store(policy, buf, count);
@@ -710,8 +710,9 @@
 		ret = -EIO;

 	unlock_policy_rwsem_write(policy->cpu);
-
+fail:
 	cpufreq_cpu_put(policy);
+no_policy:
 	return ret;
 }


amd64_edac: add driver header

amd64_edac: add driver header

Borislav:
- remove register bit descriptions (complete text in BKDG)
- cleanup and remove excessive/superfluous comments

Reviewed-by: Mauro Carvalho Chehab <ad86ba2154032c9f55743a190faa2459a9d61d42@redhat.com>
Signed-off-by: Doug Thompson <35920ba1a7821e73308e9ec6cecac34ddd29c0c4@xmission.com>
Signed-off-by: Borislav Petkov <2b4cb5acba6b5321acd37371d9b73a646c388783@amd.com>

error: pathspec 'drivers/edac/amd64_edac.h' did not match any file(s) known to git

--- drivers/edac/amd64_edac.h
+++ drivers/edac/amd64_edac.h
@@ -0,0 +1,628 @@
+/*
+ * AMD64 class Memory Controller kernel module
+ *
+ * Copyright (c) 2009 SoftwareBitMaker.
+ * Copyright (c) 2009 Advanced Micro Devices, Inc.
+ *
+ * This file may be distributed under the terms of the
+ * GNU General Public License.
+ *
+ *	Originally Written by Thayne Harbaugh
+ *
+ *      Changes by Douglas "norsk" Thompson  <dougthompson@xmission.com>:
+ *		- K8 CPU Revision D and greater support
+ *
+ *      Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
+ *		- Module largely rewritten, with new (and hopefully correct)
+ *		code for dealing with node and chip select interleaving,
+ *		various code cleanup, and bug fixes
+ *		- Added support for memory hoisting using DRAM hole address
+ *		register
+ *
+ *	Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
+ *		-K8 Rev (1207) revision support added, required Revision
+ *		specific mini-driver code to support Rev F as well as
+ *		prior revisions
+ *
+ *	Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
+ *		-Family 10h revision support added. New PCI Device IDs,
+ *		indicating new changes. Actual registers modified
+ *		were slight, less than the Rev E to Rev F transition
+ *		but changing the PCI Device ID was the proper thing to
+ *		do, as it provides for almost automactic family
+ *		detection. The mods to Rev F required more family
+ *		information detection.
+ *
+ *	Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
+ *		- misc fixes and code cleanups
+ *
+ * This module is based on the following documents
+ * (available from http://www.amd.com/):
+ *
+ *	Title:	BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
+ *		Opteron Processors
+ *	AMD publication #: 26094
+ *`	Revision: 3.26
+ *
+ *	Title:	BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
+ *		Processors
+ *	AMD publication #: 32559
+ *	Revision: 3.00
+ *	Issue Date: May 2006
+ *
+ *	Title:	BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
+ *		Processors
+ *	AMD publication #: 31116
+ *	Revision: 3.00
+ *	Issue Date: September 07, 2007
+ *
+ * Sections in the first 2 documents are no longer in sync with each other.
+ * The Family 10h BKDG was totally re-written from scratch with a new
+ * presentation model.
+ * Therefore, comments that refer to a Document section might be off.
+ */
+
+#include <linux/module.h>
+#include <linux/ctype.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/slab.h>
+#include <linux/mmzone.h>
+#include <linux/edac.h>
+#include "edac_core.h"
+
+#define amd64_printk(level, fmt, arg...) \
+	edac_printk(level, "amd64", fmt, ##arg)
+
+#define amd64_mc_printk(mci, level, fmt, arg...) \
+	edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg)
+
+/*
+ * Throughout the comments in this code, the following terms are used:
+ *
+ *	SysAddr, DramAddr, and InputAddr
+ *
+ *  These terms come directly from the amd64 documentation
+ * (AMD publication #26094).  They are defined as follows:
+ *
+ *     SysAddr:
+ *         This is a physical address generated by a CPU core or a device
+ *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
+ *         a virtual to physical address translation by the CPU core's address
+ *         translation mechanism (MMU).
+ *
+ *     DramAddr:
+ *         A DramAddr is derived from a SysAddr by subtracting an offset that
+ *         depends on which node the SysAddr maps to and whether the SysAddr
+ *         is within a range affected by memory hoisting.  The DRAM Base
+ *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
+ *         determine which node a SysAddr maps to.
+ *
+ *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
+ *         is within the range of addresses specified by this register, then
+ *         a value x from the DHAR is subtracted from the SysAddr to produce a
+ *         DramAddr.  Here, x represents the base address for the node that
+ *         the SysAddr maps to plus an offset due to memory hoisting.  See
+ *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
+ *         sys_addr_to_dram_addr() below for more information.
+ *
+ *         If the SysAddr is not affected by the DHAR then a value y is
+ *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
+ *         base address for the node that the SysAddr maps to.  See section
+ *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
+ *         information.
+ *
+ *     InputAddr:
+ *         A DramAddr is translated to an InputAddr before being passed to the
+ *         memory controller for the node that the DramAddr is associated
+ *         with.  The memory controller then maps the InputAddr to a csrow.
+ *         If node interleaving is not in use, then the InputAddr has the same
+ *         value as the DramAddr.  Otherwise, the InputAddr is produced by
+ *         discarding the bits used for node interleaving from the DramAddr.
+ *         See section 3.4.4 for more information.
+ *
+ *         The memory controller for a given node uses its DRAM CS Base and
+ *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
+ *         sections 3.5.4 and 3.5.5 for more information.
+ */
+
+#define EDAC_AMD64_VERSION		" Ver: 3.2.0 " __DATE__
+#define EDAC_MOD_STR			"amd64_edac"
+
+/* Extended Model from CPUID, for CPU Revision numbers */
+#define OPTERON_CPU_LE_REV_C		0
+#define OPTERON_CPU_REV_D		1
+#define OPTERON_CPU_REV_E		2
+
+/* NPT processors have the following Extended Models */
+#define OPTERON_CPU_REV_F		4
+#define OPTERON_CPU_REV_FA		5
+
+/* Hardware limit on ChipSelect rows per MC and processors per system */
+#define CHIPSELECT_COUNT		8
+#define DRAM_REG_COUNT			8
+
+
+/*
+ * PCI-defined configuration space registers
+ */
+
+
+/*
+ * Function 1 - Address Map
+ */
+#define K8_DRAM_BASE_LOW		0x40
+#define K8_DRAM_LIMIT_LOW		0x44
+#define K8_DHAR				0xf0
+
+#define DHAR_VALID			BIT(0)
+#define F10_DRAM_MEM_HOIST_VALID	BIT(1)
+
+#define DHAR_BASE_MASK			0xff000000
+#define dhar_base(dhar)			(dhar & DHAR_BASE_MASK)
+
+#define K8_DHAR_OFFSET_MASK		0x0000ff00
+#define k8_dhar_offset(dhar)		((dhar & K8_DHAR_OFFSET_MASK) << 16)
+
+#define F10_DHAR_OFFSET_MASK		0x0000ff80
+					/* NOTE: Extra mask bit vs K8 */
+#define f10_dhar_offset(dhar)		((dhar & F10_DHAR_OFFSET_MASK) << 16)
+
+
+/* F10 High BASE/LIMIT registers */
+#define F10_DRAM_BASE_HIGH		0x140
+#define F10_DRAM_LIMIT_HIGH		0x144
+
+
+/*
+ * Function 2 - DRAM controller
+ */
+#define K8_DCSB0			0x40
+#define F10_DCSB1			0x140
+
+#define K8_DCSB_CS_ENABLE		BIT(0)
+#define K8_DCSB_NPT_SPARE		BIT(1)
+#define K8_DCSB_NPT_TESTFAIL		BIT(2)
+
+/*
+ * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
+ * the address
+ */
+#define REV_E_DCSB_BASE_BITS		(0xFFE0FE00ULL)
+#define REV_E_DCS_SHIFT			4
+#define REV_E_DCSM_COUNT		8
+
+#define REV_F_F1Xh_DCSB_BASE_BITS	(0x1FF83FE0ULL)
+#define REV_F_F1Xh_DCS_SHIFT		8
+
+/*
+ * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
+ * to form the address
+ */
+#define REV_F_DCSB_BASE_BITS		(0x1FF83FE0ULL)
+#define REV_F_DCS_SHIFT			8
+#define REV_F_DCSM_COUNT		4
+#define F10_DCSM_COUNT			4
+#define F11_DCSM_COUNT			2
+
+/* DRAM CS Mask Registers */
+#define K8_DCSM0			0x60
+#define F10_DCSM1			0x160
+
+/* REV E: select [29:21] and [15:9] from DCSM */
+#define REV_E_DCSM_MASK_BITS		0x3FE0FE00
+
+/* unused bits [24:20] and [12:0] */
+#define REV_E_DCS_NOTUSED_BITS		0x01F01FFF
+
+/* REV F and later: select [28:19] and [13:5] from DCSM */
+#define REV_F_F1Xh_DCSM_MASK_BITS	0x1FF83FE0
+
+/* unused bits [26:22] and [12:0] */
+#define REV_F_F1Xh_DCS_NOTUSED_BITS	0x07C01FFF
+
+#define DBAM0				0x80
+#define DBAM1				0x180
+
+/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
+#define DBAM_DIMM(i, reg)		((((reg) >> (4*i))) & 0xF)
+
+#define DBAM_MAX_VALUE			11
+
+
+#define F10_DCLR_0			0x90
+#define F10_DCLR_1			0x190
+#define REVE_WIDTH_128			BIT(16)
+#define F10_WIDTH_128			BIT(11)
+
+
+#define F10_DCHR_0			0x94
+#define F10_DCHR_1			0x194
+
+#define F10_DCHR_FOUR_RANK_DIMM		BIT(18)
+#define F10_DCHR_Ddr3Mode		BIT(8)
+#define F10_DCHR_MblMode		BIT(6)
+
+
+#define F10_DCTL_SEL_LOW		0x110
+
+#define dct_sel_baseaddr(pvt)    \
+	((pvt->dram_ctl_select_low) & 0xFFFFF800)
+
+#define dct_sel_interleave_addr(pvt)    \
+	(((pvt->dram_ctl_select_low) >> 6) & 0x3)
+
+enum {
+	F10_DCTL_SEL_LOW_DctSelHiRngEn	= BIT(0),
+	F10_DCTL_SEL_LOW_DctSelIntLvEn	= BIT(2),
+	F10_DCTL_SEL_LOW_DctGangEn	= BIT(4),
+	F10_DCTL_SEL_LOW_DctDatIntLv	= BIT(5),
+	F10_DCTL_SEL_LOW_DramEnable	= BIT(8),
+	F10_DCTL_SEL_LOW_MemCleared	= BIT(10),
+};
+
+#define    dct_high_range_enabled(pvt)    \
+	(pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn)
+
+#define dct_interleave_enabled(pvt)	   \
+	(pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn)
+
+#define dct_ganging_enabled(pvt)        \
+	(pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn)
+
+#define dct_data_intlv_enabled(pvt)    \
+	(pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv)
+
+#define dct_dram_enabled(pvt)    \
+	(pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable)
+
+#define dct_memory_cleared(pvt)    \
+	(pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared)
+
+
+#define F10_DCTL_SEL_HIGH		0x114
+
+
+/*
+ * Function 3 - Misc Control
+ */
+#define K8_NBCTL			0x40
+
+/* Correctable ECC error reporting enable */
+#define K8_NBCTL_CECCEn			BIT(0)
+
+/* UnCorrectable ECC error reporting enable */
+#define K8_NBCTL_UECCEn			BIT(1)
+
+#define K8_NBCFG			0x44
+#define K8_NBCFG_CHIPKILL		BIT(23)
+#define K8_NBCFG_ECC_ENABLE		BIT(22)
+
+#define K8_NBSL				0x48
+
+
+#define EXTRACT_HIGH_SYNDROME(x)	(((x) >> 24) & 0xff)
+#define EXTRACT_EXT_ERROR_CODE(x)	(((x) >> 16) & 0x1f)
+
+/* Family F10h: Normalized Extended Error Codes */
+#define F10_NBSL_EXT_ERR_RES		0x0
+#define F10_NBSL_EXT_ERR_CRC		0x1
+#define F10_NBSL_EXT_ERR_SYNC		0x2
+#define F10_NBSL_EXT_ERR_MST		0x3
+#define F10_NBSL_EXT_ERR_TGT		0x4
+#define F10_NBSL_EXT_ERR_GART		0x5
+#define F10_NBSL_EXT_ERR_RMW		0x6
+#define F10_NBSL_EXT_ERR_WDT		0x7
+#define F10_NBSL_EXT_ERR_ECC		0x8
+#define F10_NBSL_EXT_ERR_DEV		0x9
+#define F10_NBSL_EXT_ERR_LINK_DATA	0xA
+
+/* Next two are overloaded values */
+#define F10_NBSL_EXT_ERR_LINK_PROTO	0xB
+#define F10_NBSL_EXT_ERR_L3_PROTO	0xB
+
+#define F10_NBSL_EXT_ERR_NB_ARRAY	0xC
+#define F10_NBSL_EXT_ERR_DRAM_PARITY	0xD
+#define F10_NBSL_EXT_ERR_LINK_RETRY	0xE
+
+/* Next two are overloaded values */
+#define F10_NBSL_EXT_ERR_GART_WALK	0xF
+#define F10_NBSL_EXT_ERR_DEV_WALK	0xF
+
+/* 0x10 to 0x1B: Reserved */
+#define F10_NBSL_EXT_ERR_L3_DATA	0x1C
+#define F10_NBSL_EXT_ERR_L3_TAG		0x1D
+#define F10_NBSL_EXT_ERR_L3_LRU		0x1E
+
+/* K8: Normalized Extended Error Codes */
+#define K8_NBSL_EXT_ERR_ECC		0x0
+#define K8_NBSL_EXT_ERR_CRC		0x1
+#define K8_NBSL_EXT_ERR_SYNC		0x2
+#define K8_NBSL_EXT_ERR_MST		0x3
+#define K8_NBSL_EXT_ERR_TGT		0x4
+#define K8_NBSL_EXT_ERR_GART		0x5
+#define K8_NBSL_EXT_ERR_RMW		0x6
+#define K8_NBSL_EXT_ERR_WDT		0x7
+#define K8_NBSL_EXT_ERR_CHIPKILL_ECC	0x8
+#define K8_NBSL_EXT_ERR_DRAM_PARITY	0xD
+
+#define EXTRACT_ERROR_CODE(x)		((x) & 0xffff)
+#define	TEST_TLB_ERROR(x)		(((x) & 0xFFF0) == 0x0010)
+#define	TEST_MEM_ERROR(x)		(((x) & 0xFF00) == 0x0100)
+#define	TEST_BUS_ERROR(x)		(((x) & 0xF800) == 0x0800)
+#define	EXTRACT_TT_CODE(x)		(((x) >> 2) & 0x3)
+#define	EXTRACT_II_CODE(x)		(((x) >> 2) & 0x3)
+#define	EXTRACT_LL_CODE(x)		(((x) >> 0) & 0x3)
+#define	EXTRACT_RRRR_CODE(x)		(((x) >> 4) & 0xf)
+#define	EXTRACT_TO_CODE(x)		(((x) >> 8) & 0x1)
+#define	EXTRACT_PP_CODE(x)		(((x) >> 9) & 0x3)
+
+/*
+ * The following are for BUS type errors AFTER values have been normalized by
+ * shifting right
+ */
+#define K8_NBSL_PP_SRC			0x0
+#define K8_NBSL_PP_RES			0x1
+#define K8_NBSL_PP_OBS			0x2
+#define K8_NBSL_PP_GENERIC		0x3
+
+
+#define K8_NBSH				0x4C
+
+#define K8_NBSH_VALID_BIT		BIT(31)
+#define K8_NBSH_OVERFLOW		BIT(30)
+#define K8_NBSH_UNCORRECTED_ERR		BIT(29)
+#define K8_NBSH_ERR_ENABLE		BIT(28)
+#define K8_NBSH_MISC_ERR_VALID		BIT(27)
+#define K8_NBSH_VALID_ERROR_ADDR	BIT(26)
+#define K8_NBSH_PCC			BIT(25)
+#define K8_NBSH_CECC			BIT(14)
+#define K8_NBSH_UECC			BIT(13)
+#define K8_NBSH_ERR_SCRUBER		BIT(8)
+#define K8_NBSH_CORE3			BIT(3)
+#define K8_NBSH_CORE2			BIT(2)
+#define K8_NBSH_CORE1			BIT(1)
+#define K8_NBSH_CORE0			BIT(0)
+
+#define EXTRACT_LDT_LINK(x)		(((x) >> 4) & 0x7)
+#define EXTRACT_ERR_CPU_MAP(x)		((x) & 0xF)
+#define EXTRACT_LOW_SYNDROME(x)		(((x) >> 15) & 0xff)
+
+
+#define K8_NBEAL			0x50
+#define K8_NBEAH			0x54
+#define K8_SCRCTRL			0x58
+
+#define F10_NB_CFG_LOW			0x88
+#define	F10_NB_CFG_LOW_ENABLE_EXT_CFG	BIT(14)
+
+#define F10_NB_CFG_HIGH			0x8C
+
+#define F10_ONLINE_SPARE		0xB0
+#define F10_ONLINE_SPARE_SWAPDONE0(x)	((x) & BIT(1))
+#define F10_ONLINE_SPARE_SWAPDONE1(x)	((x) & BIT(3))
+#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
+#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
+
+#define F10_NB_ARRAY_ADDR		0xB8
+
+#define F10_NB_ARRAY_DRAM_ECC		0x80000000
+
+/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
+#define SET_NB_ARRAY_ADDRESS(section)	(((section) & 0x3) << 1)
+
+#define F10_NB_ARRAY_DATA		0xBC
+
+#define SET_NB_DRAM_INJECTION_WRITE(word, bits)  \
+					(BIT(((word) & 0xF) + 20) | \
+					BIT(17) |  \
+					((bits) & 0xF))
+
+#define SET_NB_DRAM_INJECTION_READ(word, bits)  \
+					(BIT(((word) & 0xF) + 20) | \
+					BIT(16) |  \
+					((bits) & 0xF))
+
+#define K8_NBCAP			0xE8
+#define K8_NBCAP_CORES			(BIT(12)|BIT(13))
+#define K8_NBCAP_CHIPKILL		BIT(4)
+#define K8_NBCAP_SECDED			BIT(3)
+#define K8_NBCAP_8_NODE			BIT(2)
+#define K8_NBCAP_DUAL_NODE		BIT(1)
+#define K8_NBCAP_DCT_DUAL		BIT(0)
+
+/*
+ * MSR Regs
+ */
+#define K8_MSR_MCGCTL			0x017b
+#define K8_MSR_MCGCTL_NBE		BIT(4)
+
+#define K8_MSR_MC4CTL			0x0410
+#define K8_MSR_MC4STAT			0x0411
+#define K8_MSR_MC4ADDR			0x0412
+
+/* AMD sets the first MC device at device ID 0x18. */
+static inline int get_mc_node_id_from_pdev(struct pci_dev *pdev)
+{
+	return PCI_SLOT(pdev->devfn) - 0x18;
+}
+
+enum amd64_chipset_families {
+	K8_CPUS = 0,
+	F10_CPUS,
+	F11_CPUS,
+};
+
+/*
+ * Structure to hold:
+ *
+ * 1) dynamically read status and error address HW registers
+ * 2) sysfs entered values
+ * 3) MCE values
+ *
+ * Depends on entry into the modules
+ */
+struct amd64_error_info_regs {
+	u32 nbcfg;
+	u32 nbsh;
+	u32 nbsl;
+	u32 nbeah;
+	u32 nbeal;
+};
+
+/* Error injection control structure */
+struct error_injection {
+	u32	section;
+	u32	word;
+	u32	bit_map;
+};
+
+struct amd64_pvt {
+	/* pci_device handles which we utilize */
+	struct pci_dev *addr_f1_ctl;
+	struct pci_dev *dram_f2_ctl;
+	struct pci_dev *misc_f3_ctl;
+
+	int mc_node_id;		/* MC index of this MC node */
+	int ext_model;		/* extended model value of this node */
+
+	struct low_ops *ops;	/* pointer to per PCI Device ID func table */
+
+	int channel_count;
+
+	/* Raw registers */
+	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
+	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
+	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
+	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
+	u32 nbcap;		/* North Bridge Capabilities */
+	u32 nbcfg;		/* F10 North Bridge Configuration */
+	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
+	u32 dhar;		/* DRAM Hoist reg */
+	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
+	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */
+
+	/* DRAM CS Base Address Registers F2x[1,0][5C:40] */
+	u32 dcsb0[CHIPSELECT_COUNT];
+	u32 dcsb1[CHIPSELECT_COUNT];
+
+	/* DRAM CS Mask Registers F2x[1,0][6C:60] */
+	u32 dcsm0[CHIPSELECT_COUNT];
+	u32 dcsm1[CHIPSELECT_COUNT];
+
+	/*
+	 * Decoded parts of DRAM BASE and LIMIT Registers
+	 * F1x[78,70,68,60,58,50,48,40]
+	 */
+	u64 dram_base[DRAM_REG_COUNT];
+	u64 dram_limit[DRAM_REG_COUNT];
+	u8  dram_IntlvSel[DRAM_REG_COUNT];
+	u8  dram_IntlvEn[DRAM_REG_COUNT];
+	u8  dram_DstNode[DRAM_REG_COUNT];
+	u8  dram_rw_en[DRAM_REG_COUNT];
+
+	/*
+	 * The following fields are set at (load) run time, after CPU revision
+	 * has been determined, since the dct_base and dct_mask registers vary
+	 * based on revision
+	 */
+	u32 dcsb_base;		/* DCSB base bits */
+	u32 dcsm_mask;		/* DCSM mask bits */
+	u32 num_dcsm;		/* Number of DCSM registers */
+	u32 dcs_mask_notused;	/* DCSM notused mask bits */
+	u32 dcs_shift;		/* DCSB and DCSM shift value */
+
+	u64 top_mem;		/* top of memory below 4GB */
+	u64 top_mem2;		/* top of memory above 4GB */
+
+	u32 dram_ctl_select_low;	/* DRAM Controller Select Low Reg */
+	u32 dram_ctl_select_high;	/* DRAM Controller Select High Reg */
+	u32 online_spare;               /* On-Line spare Reg */
+
+	/* temp storage for when input is received from sysfs */
+	struct amd64_error_info_regs ctl_error_info;
+
+	/* place to store error injection parameters prior to issue */
+	struct error_injection injection;
+
+	/* Save old hw registers' values before we modified them */
+	u32 nbctl_mcgctl_saved;		/* When true, following 2 are valid */
+	u32 old_nbctl;
+	u32 *old_mcgctl;		/* per core on this node */
+
+	/* MC Type Index value: socket F vs Family 10h */
+	u32 mc_type_index;
+
+	/* misc settings */
+	struct flags {
+		unsigned long cf8_extcfg:1;
+	} flags;
+};
+
+struct scrubrate {
+       u32 scrubval;           /* bit pattern for scrub rate */
+       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
+};
+
+extern struct scrubrate scrubrates[23];
+extern u32 revf_quad_ddr2_shift[16];
+extern const char *tt_msgs[4];
+extern const char *ll_msgs[4];
+extern const char *rrrr_msgs[16];
+extern const char *to_msgs[2];
+extern const char *pp_msgs[4];
+extern const char *ii_msgs[4];
+extern const char *ext_msgs[32];
+extern const char *htlink_msgs[8];
+
+/*
+ * Each of the PCI Device IDs types have their own set of hardware accessor
+ * functions and per device encoding/decoding logic.
+ */
+struct low_ops {
+	int (*probe_valid_hardware)(struct amd64_pvt *pvt);
+	int (*early_channel_count)(struct amd64_pvt *pvt);
+
+	u64 (*get_error_address)(struct mem_ctl_info *mci,
+			struct amd64_error_info_regs *info);
+	void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram);
+	void (*read_dram_ctl_register)(struct amd64_pvt *pvt);
+	void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci,
+					struct amd64_error_info_regs *info,
+					u64 SystemAddr);
+	int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map);
+};
+
+struct amd64_family_type {
+	const char *ctl_name;
+	u16 addr_f1_ctl;
+	u16 misc_f3_ctl;
+	struct low_ops ops;
+};
+
+static struct amd64_family_type amd64_family_types[];
+
+static inline const char *get_amd_family_name(int index)
+{
+	return amd64_family_types[index].ctl_name;
+}
+
+static inline struct low_ops *family_ops(int index)
+{
+	return &amd64_family_types[index].ops;
+}
+
+/*
+ * For future CPU versions, verify the following as new 'slow' rates appear and
+ * modify the necessary skip values for the supported CPU.
+ */
+#define K8_MIN_SCRUB_RATE_BITS	0x0
+#define F10_MIN_SCRUB_RATE_BITS	0x5
+#define F11_MIN_SCRUB_RATE_BITS	0x6
+
+int amd64_process_error_info(struct mem_ctl_info *mci,
+			     struct amd64_error_info_regs *info,
+			     int handle_errors);
+int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
+			     u64 *hole_offset, u64 *hole_size);


e7xxx_edac: Report CE events properly

e7xxx_edac: Report CE events properly

Fix CE event being reported as HW_EVENT_ERR_UNCORRECTED.

Signed-off-by: Jason Baron <af9bd1db766a43cb09b647251c97dbddcd2e59dc@akamai.com>
Cc: 4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org
Link: http://lkml.kernel.org/r/e6dd616f2cd51583a7e77af6f639b86313c74144.1413405053.git.af9bd1db766a43cb09b647251c97dbddcd2e59dc@akamai.com
Signed-off-by: Borislav Petkov <0691a664b24b6f15b20cd5aee64b72271db08be1@suse.de>

--- drivers/edac/e7xxx_edac.c
+++ drivers/edac/e7xxx_edac.c
@@ -226,7 +226,7 @@
 static void process_ce_no_info(struct mem_ctl_info *mci)
 {
 	edac_dbg(3, "\n");
-	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
+	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
 			     "e7xxx CE log register overflow", "");
 }


i7300_edac: Add a code to cleanup error registers

Signed-off-by: Mauro Carvalho Chehab <ad86ba2154032c9f55743a190faa2459a9d61d42@redhat.com>

--- drivers/edac/i7300_edac.c
+++ drivers/edac/i7300_edac.c
@@ -470,9 +470,34 @@
  */
 static void i7300_clear_error(struct mem_ctl_info *mci)
 {
-	struct i7300_error_info info;
-
-	i7300_get_error_info(mci, &info);
+	struct i7300_pvt *pvt = mci->pvt_info;
+	u32 value;
+	/*
+	 * All error values are RWC - we need to read and write 1 to the
+	 * bit that we want to cleanup
+	 */
+
+	/* Clear global error registers */
+	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+			      FERR_GLOBAL_HI, &value);
+	pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+			      FERR_GLOBAL_HI, value);
+
+	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+			      FERR_GLOBAL_LO, &value);
+	pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+			      FERR_GLOBAL_LO, value);
+
+	/* Clear FBD error registers */
+	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+			      FERR_FAT_FBD, &value);
+	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+			      FERR_FAT_FBD, value);
+
+	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+			      FERR_NF_FBD, &value);
+	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+			      FERR_NF_FBD, value);
 }

 /*


drm/gem: Be more friendly with locking checks

BUG_ON kills the driver, WARN_ON is much friendlier. And usually nothing
bad happens when the locking is slightly busted.

v2: Fix typos in commit message Thierry spotted.

Reviewed-by: Thierry Reding <3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com>
Signed-off-by: Daniel Vetter <c1b6782c4af8f0673da8923a0702a1832e5940f4@intel.com>

--- drivers/gpu/drm/drm_gem.c
+++ drivers/gpu/drm/drm_gem.c
@@ -766,7 +766,7 @@
 	struct drm_gem_object *obj = (struct drm_gem_object *) kref;
 	struct drm_device *dev = obj->dev;

-	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
+	WARN_ON(!mutex_is_locked(&dev->struct_mutex));

 	if (dev->driver->gem_free_object != NULL)
 		dev->driver->gem_free_object(obj);


HID: picolcd: correct ordering of framebuffer freeing

Fix the free() ordering (which was never reached due to wrong check).

Signed-off-by: Bruno Prémont <07d37993a092409e6c5d6be7073d31d94250624b@linux-vserver.org>
Signed-off-by: Jiri Kosina <ed58f755cc8caaf10c3e8c731a8b86fb8f13d6cb@suse.cz>

--- drivers/hid/hid-picolcd.c
+++ drivers/hid/hid-picolcd.c
@@ -550,8 +550,8 @@
 	may_release = !*ref_cnt;
 	mutex_unlock(&info->lock);
 	if (may_release) {
+		vfree((u8 *)info->fix.smem_start);
 		framebuffer_release(info);
-		vfree((u8 *)info->fix.smem_start);
 	}
 }


Someone report  me small  bug in contrib/pg_dumplo  today. It's problem
with a little dirty snprintf() usage which I used some years ago:

    snprintf(path, BUFSIZ, "%s/lo_dump.index", path);

Karel Zak

--- contrib/pg_dumplo/utils.c
+++ contrib/pg_dumplo/utils.c
@@ -1,7 +1,7 @@
 /* -------------------------------------------------------------------------
  * pg_dumplo
  *
- * $Header: /cvsroot/pgsql/contrib/pg_dumplo/Attic/utils.c,v 1.6 2002/09/05 21:01:16 tgl Exp $
+ * $Header: /cvsroot/pgsql/contrib/pg_dumplo/Attic/utils.c,v 1.7 2003/10/09 13:38:05 momjian Exp $
  *
  *					Karel Zak 1999-2000
  * -------------------------------------------------------------------------
@@ -30,6 +30,7 @@
 index_file(LODumpMaster * pgLO)
 {
 	char		path[BUFSIZ];
+	int		sz;

 	if (pgLO->action == ACTION_SHOW)
 		return;
@@ -49,7 +50,8 @@
 			}
 		}

-		snprintf(path, BUFSIZ, "%s/lo_dump.index", path);
+		sz = strlen(path);
+		strncat(path, "/lo_dump.index", BUFSIZ-sz);

 		if ((pgLO->index = fopen(path, "w")) == NULL)
 		{
@@ -60,8 +62,8 @@
 	}
 	else if (pgLO->action != ACTION_NONE)
 	{
-
-		snprintf(path, BUFSIZ, "%s/lo_dump.index", path);
+		sz = strlen(path);
+		strncat(path, "/lo_dump.index", BUFSIZ-sz);

 		if ((pgLO->index = fopen(path, "r")) == NULL)
 		{


Drivers: hv: vmbus: fix init_vp_index() for reloading hv_netvsc

This fixes the recent commit 3b71107d73b16074afa7658f3f0fcf837aabfe24:
Drivers: hv: vmbus: Further improve CPU affiliation logic

Without the fix, reloading hv_netvsc hangs the guest.

Signed-off-by: Dexuan Cui <cd5c9304120b3aad8158bbc6888849d74dea1dde@microsoft.com>
Signed-off-by: K. Y. Srinivasan <bcbf172338421f26297a2592698edf8cc84ecbef@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <4645f7897fd33786a2ee1264d590b3c400559d85@linuxfoundation.org>

--- drivers/hv/channel_mgmt.c
+++ drivers/hv/channel_mgmt.c
@@ -204,6 +204,8 @@
 		spin_lock_irqsave(&vmbus_connection.channel_lock, flags);
 		list_del(&channel->listentry);
 		spin_unlock_irqrestore(&vmbus_connection.channel_lock, flags);
+
+		primary_channel = channel;
 	} else {
 		primary_channel = channel->primary_channel;
 		spin_lock_irqsave(&primary_channel->lock, flags);
@@ -211,6 +213,14 @@
 		primary_channel->num_sc--;
 		spin_unlock_irqrestore(&primary_channel->lock, flags);
 	}
+
+	/*
+	 * We need to free the bit for init_vp_index() to work in the case
+	 * of sub-channel, when we reload drivers like hv_netvsc.
+	 */
+	cpumask_clear_cpu(channel->target_cpu,
+			  &primary_channel->alloced_cpus_in_node);
+
 	free_channel(channel);
 }

@@ -458,6 +468,13 @@
 			continue;
 		}

+		/*
+		 * NOTE: in the case of sub-channel, we clear the sub-channel
+		 * related bit(s) in primary->alloced_cpus_in_node in
+		 * hv_process_channel_removal(), so when we reload drivers
+		 * like hv_netvsc in SMP guest, here we're able to re-allocate
+		 * bit from primary->alloced_cpus_in_node.
+		 */
 		if (!cpumask_test_cpu(cur_cpu,
 				&primary->alloced_cpus_in_node)) {
 			cpumask_set_cpu(cur_cpu,


Well, the correct code - that corresponds to current
encode - is below.  I even got the linefeed stuff wrong.

--
marko

--- contrib/pgcrypto/encode.c
+++ contrib/pgcrypto/encode.c
@@ -26,7 +26,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $Id: encode.c,v 1.5 2001/05/13 02:17:09 momjian Exp $
+ * $Id: encode.c,v 1.6 2001/05/15 04:45:15 momjian Exp $
  */

 #include "postgres.h"
@@ -349,7 +349,8 @@
 uint
 b64_enc_len(uint srclen)
 {
-	return srclen + (srclen + 2 / 3) + (srclen / (76 / 2)) + 2;
+	/* 3 bytes will be converted to 4, linefeed after 76 chars */
+	return (srclen + 2) * 4 / 3 + srclen / (76 * 3 / 4);
 }

 uint


drivers: i2s_sam_ssc.c: store *dev_dma in flash

The DMA module the i2s_sam_ssc relies on cannot change during the
runtime. Store pointer to dev_dma in flash, not in RAM. The new
implementation saves 40 bytes of flash and 32 bytes of RAM.

Signed-off-by: Piotr Mienkowski <be7d9ab625d3cb5e3a4a3202f3529b954dba084c@gmail.com>

--- drivers/i2s/i2s_sam_ssc.c
+++ drivers/i2s/i2s_sam_ssc.c
@@ -64,6 +64,7 @@

 /* Device constant configuration parameters */
 struct i2s_sam_dev_cfg {
+	const struct device *dev_dma;
 	Ssc *regs;
 	void (*irq_config)(void);
 	const struct soc_gpio_pin *pin_list;
@@ -92,7 +93,6 @@

 /* Device run time data */
 struct i2s_sam_dev_data {
-	const struct device *dev_dma;
 	struct stream rx;
 	struct stream tx;
 };
@@ -235,7 +235,7 @@
 		goto rx_disable;
 	}

-	ret = start_dma(dev_data->dev_dma, stream->dma_channel, &stream->dma_cfg,
+	ret = start_dma(dev_cfg->dev_dma, stream->dma_channel, &stream->dma_cfg,
 			(void *)&(ssc->SSC_RHR), stream->mem_block,
 			stream->cfg.block_size);
 	if (ret < 0) {
@@ -246,7 +246,7 @@
 	return;

 rx_disable:
-	rx_stream_disable(stream, ssc, dev_data->dev_dma);
+	rx_stream_disable(stream, ssc, dev_cfg->dev_dma);
 }

 /* This function is executed in the interrupt context */
@@ -296,7 +296,7 @@
 	/* Assure cache coherency before DMA read operation */
 	DCACHE_CLEAN(stream->mem_block, mem_block_size);

-	ret = start_dma(dev_data->dev_dma, stream->dma_channel, &stream->dma_cfg,
+	ret = start_dma(dev_cfg->dev_dma, stream->dma_channel, &stream->dma_cfg,
 			stream->mem_block, (void *)&(ssc->SSC_THR),
 			mem_block_size);
 	if (ret < 0) {
@@ -307,7 +307,7 @@
 	return;

 tx_disable:
-	tx_stream_disable(stream, ssc, dev_data->dev_dma);
+	tx_stream_disable(stream, ssc, dev_cfg->dev_dma);
 }

 static int set_rx_data_format(const struct i2s_sam_dev_cfg *const dev_cfg,
@@ -777,7 +777,7 @@

 		__ASSERT_NO_MSG(stream->mem_block == NULL);

-		ret = stream->stream_start(stream, ssc, dev_data->dev_dma);
+		ret = stream->stream_start(stream, ssc, dev_cfg->dev_dma);
 		if (ret < 0) {
 			LOG_DBG("START trigger failed %d", ret);
 			return ret;
@@ -815,7 +815,7 @@
 			LOG_DBG("DROP trigger: invalid state");
 			return -EIO;
 		}
-		stream->stream_disable(stream, ssc, dev_data->dev_dma);
+		stream->stream_disable(stream, ssc, dev_cfg->dev_dma);
 		stream->queue_drop(stream);
 		stream->state = I2S_STATE_READY;
 		break;
@@ -929,8 +929,8 @@
 	k_sem_init(&dev_data->tx.sem, CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT,
 		   CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT);

-	if (!device_is_ready(dev_data->dev_dma)) {
-		LOG_ERR("%s device not ready", dev_data->dev_dma->name);
+	if (!device_is_ready(dev_cfg->dev_dma)) {
+		LOG_ERR("%s device not ready", dev_cfg->dev_dma->name);
 		return -ENODEV;
 	}

@@ -975,6 +975,7 @@
 static const struct soc_gpio_pin i2s0_pins[] = ATMEL_SAM_DT_PINS(0);

 static const struct i2s_sam_dev_cfg i2s0_sam_config = {
+	.dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(0, tx)),
 	.regs = (Ssc *)DT_INST_REG_ADDR(0),
 	.irq_config = i2s0_sam_irq_config,
 	.periph_id = DT_INST_PROP(0, peripheral_id),
@@ -987,7 +988,6 @@
 struct queue_item tx_0_ring_buf[CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT + 1];

 static struct i2s_sam_dev_data i2s0_sam_data = {
-	.dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(0, tx)),
 	.rx = {
 		.dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, rx, channel),
 		.dma_cfg = {


ide: fix crash at boot with siimage driver

Some change to the IDE layer are causing the siimage driver to crash
at boot with a NULL dereference. This is due to the sil_dma_ops not
containing all the necessary pointers. I suppose it used to just
"override" the defaults while now, it needs to contain everything.

[bart: while at it: sil_dma_ops should be const now (pointed out by Sergei)]

Signed-off-by: Benjamin Herrenschmidt <a7089bb6e7e92505d88aaff006cbdd60cc9120b6@kernel.crashing.org>
Cc: Sergei Shtylyov <38a867ea26f35d3eeb42270f1bc7b9d1d135e6a2@ru.mvista.com>,
Signed-off-by: Bartlomiej Zolnierkiewicz <248de9df611a028e5eceb9d893a2ed6c24c89ef4@gmail.com>

--- drivers/ide/pci/siimage.c
+++ drivers/ide/pci/siimage.c
@@ -737,8 +737,15 @@
 	.cable_detect		= sil_cable_detect,
 };

-static struct ide_dma_ops sil_dma_ops = {
+static const struct ide_dma_ops sil_dma_ops = {
+	.dma_host_set		= ide_dma_host_set,
+	.dma_setup		= ide_dma_setup,
+	.dma_exec_cmd		= ide_dma_exec_cmd,
+	.dma_start		= ide_dma_start,
+	.dma_end		= __ide_dma_end,
 	.dma_test_irq		= siimage_dma_test_irq,
+	.dma_timeout		= ide_dma_timeout,
+	.dma_lost_irq		= ide_dma_lost_irq,
 };

 #define DECLARE_SII_DEV(name_str, p_ops)		\


Convert reviewed_receipts to get_page_pagination

Use the common results setting pagination code.

Signed-off-by: Andrew Clayton <02e0a999c50b1f88df7a8f5a04e1b76b35ea6a88@opentechlabs.co.uk>

--- www/url_handlers.c
+++ www/url_handlers.c
@@ -1769,13 +1769,9 @@
 	if (!(current_session->capabilities & APPROVER))
 		return;

-	if (qvars) {
-		page_no = atoi(get_var(qvars, "page_no"));
-		if (page_no < 1)
-			page_no = 1;
-		/* Determine the LIMIT offset to start from in the SQL */
-		from = page_no * GRID_SIZE - GRID_SIZE;
-	}
+	if (qvars)
+		get_page_pagination(get_var(qvars, "page_no"), GRID_SIZE,
+							&page_no, &from);

 	if (current_session->capabilities & APPROVER)
 		ml = TMPL_add_var(ml, "approver", "yes", NULL);


iommu/amd: Fix section warning for prealloc_protection_domains

Fix the following section warning in drivers/iommu/amd_iommu.c :

WARNING: vmlinux.o(.text+0x526e77): Section mismatch in reference from the function prealloc_protection_domains() to the function .init.text:alloc_passthrough_domain()
The function prealloc_protection_domains() references
the function __init alloc_passthrough_domain().
This is often because prealloc_protection_domains lacks a __init
annotation or the annotation of alloc_passthrough_domain is wrong.

Cc: 4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org
Signed-off-by: Steffen Persvold <e8c5e5be4d4926e3acc74ed8dd3beb18fa6b1593@numascale.com>
Signed-off-by: Joerg Roedel <ebd221a096cbc71dd9e1991db28795933c85f380@amd.com>

--- drivers/iommu/amd_iommu.c
+++ drivers/iommu/amd_iommu.c
@@ -2804,7 +2804,7 @@
  * we don't need to preallocate the protection domains anymore.
  * For now we have to.
  */
-static void prealloc_protection_domains(void)
+static void __init prealloc_protection_domains(void)
 {
 	struct iommu_dev_data *dev_data;
 	struct dma_ops_domain *dma_dom;


Fix another POLA breakage in a new tar: in diff mode presence of file
in the archive, but its absence in the file system should be reported
as difference, not as error.

Reported by:	bde

--- contrib/tar/src/compare.c
+++ contrib/tar/src/compare.c
@@ -406,10 +406,14 @@
   if (status != 0)
     {
       if (errno == ENOENT)
-	stat_warn (file_name);
+	{
+	  report_difference (_("does not exist"));
+	}
       else
-	stat_error (file_name);
-      report_difference (0);
+	{
+	  stat_error (file_name);
+          report_difference (0);
+	}
       return 0;
     }


url_handlers: Convert admin_pending_activations() to IS_APPROVER()

Signed-off-by: Andrew Clayton <02e0a999c50b1f88df7a8f5a04e1b76b35ea6a88@opentechlabs.co.uk>

--- www/url_handlers.c
+++ www/url_handlers.c
@@ -768,7 +768,7 @@

 	ml = TMPL_add_var(ml, "admin", "yes", NULL);

-	if (user_session.capabilities & APPROVER)
+	if (IS_APPROVER())
 		ml = TMPL_add_var(ml, "approver", "yes", (char *)NULL);

 	ml = TMPL_add_var(ml, "user_hdr", user_session.user_hdr, (char *)NULL);


UBI: fastmap: fix backward compatibility with image_seq

Some old UBI implementations (e.g. U-Boot) have not implemented the image
sequence feature.
So, when erase blocks are written, the image sequence in the ec header
is lost (set to zero).
UBI scan_all() takes this case into account (commits
32bc4820287a1a03982979515949e8ea56eac641 and
2eadaad67b2b6bd132eda105128d2d466298b8e3)

But fastmap scan functions (ubi_scan_fastmap() and scan_pool()) didn't.

This patch fixes the issue.

Signed-off-by: Richard Genoud <9cfb506ffc11a9bdfddeea4cef2a4c9d35dfe20c@gmail.com>
Signed-off-by: Richard Weinberger <320bca71fc381a4a025636043ca86e734e31cf8b@nod.at>
Signed-off-by: Artem Bityutskiy <2f96f8cd3e2780a209d0ab27d1b44624d0019d3f@linux.intel.com>

--- drivers/mtd/ubi/fastmap.c
+++ drivers/mtd/ubi/fastmap.c
@@ -407,6 +407,7 @@
 	 */
 	for (i = 0; i < pool_size; i++) {
 		int scrub = 0;
+		int image_seq;

 		pnum = be32_to_cpu(pebs[i]);

@@ -425,7 +426,13 @@
 		} else if (ret == UBI_IO_BITFLIPS)
 			scrub = 1;

-		if (be32_to_cpu(ech->image_seq) != ubi->image_seq) {
+		/*
+		 * Older UBI implementations have image_seq set to zero, so
+		 * we shouldn't fail if image_seq == 0.
+		 */
+		image_seq = be32_to_cpu(ech->image_seq);
+
+		if (image_seq && (image_seq != ubi->image_seq)) {
 			ubi_err("bad image seq: 0x%x, expected: 0x%x",
 				be32_to_cpu(ech->image_seq), ubi->image_seq);
 			ret = UBI_BAD_FASTMAP;
@@ -923,6 +930,8 @@
 	}

 	for (i = 0; i < used_blocks; i++) {
+		int image_seq;
+
 		pnum = be32_to_cpu(fmsb->block_loc[i]);

 		if (ubi_io_is_bad(ubi, pnum)) {
@@ -940,10 +949,17 @@
 		} else if (ret == UBI_IO_BITFLIPS)
 			fm->to_be_tortured[i] = 1;

+		image_seq = be32_to_cpu(ech->image_seq);
 		if (!ubi->image_seq)
-			ubi->image_seq = be32_to_cpu(ech->image_seq);
-
-		if (be32_to_cpu(ech->image_seq) != ubi->image_seq) {
+			ubi->image_seq = image_seq;
+
+		/*
+		 * Older UBI implementations have image_seq set to zero, so
+		 * we shouldn't fail if image_seq == 0.
+		 */
+		if (image_seq && (image_seq != ubi->image_seq)) {
+			ubi_err("wrong image seq:%d instead of %d",
+				be32_to_cpu(ech->image_seq), ubi->image_seq);
 			ret = UBI_BAD_FASTMAP;
 			goto free_hdr;
 		}


fixed character set translation in dbd_get_encoding()

--- drivers/mysql/dbd_mysql.c
+++ drivers/mysql/dbd_mysql.c
@@ -200,6 +200,10 @@

 	if (!mycon) return NULL;

+	/* this function apparently returns the collation rather than
+	   the character set, as the name would imply. However, the
+	   collation name starts with the character set name that it
+	   belongs to, so we can extract the latter */
 	my_enc = mysql_character_set_name(mycon);

 	if (!my_enc) {
@@ -210,7 +214,7 @@

 	  /* loop over all even entries in hash and compare to my_enc */
 	  while (*mysql_encoding_hash[i]) {
-	    if (!strcmp(mysql_encoding_hash[i], my_enc)) {
+	    if (!strncmp(mysql_encoding_hash[i], my_enc, strlen(mysql_encoding_hash[i]))) {
 	      /* return corresponding odd entry */
 	      return mysql_encoding_hash[i+1];
 	    }


can: ti_hecc: fix endianness related sparse warning

This patch fixes the following sparse warning, which occurs in casts when
accessing the data in the CAN frames (struct can_frame) in the RX and TX
routines:

drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32
drivers/net/can/ti_hecc.c:572:28: warning: incorrect type in assignment (different base types)
drivers/net/can/ti_hecc.c:572:28:    expected unsigned int [unsigned] [usertype] <noident>
drivers/net/can/ti_hecc.c:572:28:    got restricted __be32 [usertype] <noident>
drivers/net/can/ti_hecc.c:575:40: warning: incorrect type in assignment (different base types)
drivers/net/can/ti_hecc.c:575:40:    expected unsigned int [unsigned] [usertype] <noident>
drivers/net/can/ti_hecc.c:575:40:    got restricted __be32 [usertype] <noident>

As the data is indeed big endian, use "__be32" instead of "u32", when casting
it.

Signed-off-by: Marc Kleine-Budde <4a0ea1158d3cc63151119c05b1bff00c0bdbf421@pengutronix.de>

--- drivers/net/can/ti_hecc.c
+++ drivers/net/can/ti_hecc.c
@@ -518,10 +518,10 @@
 		data = (cf->can_id & CAN_SFF_MASK) << 18;
 	hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
 	hecc_write_mbx(priv, mbxno, HECC_CANMDL,
-		be32_to_cpu(*(u32 *)(cf->data)));
+		be32_to_cpu(*(__be32 *)(cf->data)));
 	if (cf->can_dlc > 4)
 		hecc_write_mbx(priv, mbxno, HECC_CANMDH,
-			be32_to_cpu(*(u32 *)(cf->data + 4)));
+			be32_to_cpu(*(__be32 *)(cf->data + 4)));
 	else
 		*(u32 *)(cf->data + 4) = 0;
 	can_put_echo_skb(skb, ndev, mbxno);
@@ -569,12 +569,10 @@
 		cf->can_id |= CAN_RTR_FLAG;
 	cf->can_dlc = get_can_dlc(data & 0xF);
 	data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
-	*(u32 *)(cf->data) = cpu_to_be32(data);
+	*(__be32 *)(cf->data) = cpu_to_be32(data);
 	if (cf->can_dlc > 4) {
 		data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
-		*(u32 *)(cf->data + 4) = cpu_to_be32(data);
-	} else {
-		*(u32 *)(cf->data + 4) = 0;
+		*(__be32 *)(cf->data + 4) = cpu_to_be32(data);
 	}
 	spin_lock_irqsave(&priv->mbx_lock, flags);
 	hecc_clear_bit(priv, HECC_CANME, mbx_mask);


ixgbe: change default ring size

ixgbe: change default ring size

decrease the memory utilization of the tx / rx queue allocation
by changing the default ring size to 512 (from 1024).  At
1024 rx entries of 2KB each (from 4kB slab) with 16 queues
ixgbe was using 64 MB of memory per port, which is not
necessary.

Users can still change queue lengths with ethtool -k.

Signed-off-by: Jesse Brandeburg <e6047e445db6578741afb14ef640164ef6b65e4f@intel.com>
Acked-by: Peter P Waskiewicz Jr <019ca817bcedb2fce0c539efa1b71c24f7a6c1c1@intel.com>
Signed-off-by: Jeff Kirsher <87e35f5be20bb3e67f4ba6b86f5f6be3085b1b3a@intel.com>
Signed-off-by: David S. Miller <fe08d3c717adf2ae63592e4c9aec6e3e404d8e3e@davemloft.net>

--- drivers/net/ixgbe/ixgbe.h
+++ drivers/net/ixgbe/ixgbe.h
@@ -51,11 +51,11 @@
 		__func__ , ## args)))

 /* TX/RX descriptor defines */
-#define IXGBE_DEFAULT_TXD		   1024
+#define IXGBE_DEFAULT_TXD		    512
 #define IXGBE_MAX_TXD			   4096
 #define IXGBE_MIN_TXD			     64

-#define IXGBE_DEFAULT_RXD		   1024
+#define IXGBE_DEFAULT_RXD		    512
 #define IXGBE_MAX_RXD			   4096
 #define IXGBE_MIN_RXD			     64


mv643xx_eth: potential null dereference

mv643xx_eth: potential null dereference

We assume that "pd" can be null on the previous line, and throughout the
function so we should check it here as well.  This was introduced by
9b2c2ff7a1c0 "mv643xx_eth: use sw csum for big packets"

Signed-off-by: Dan Carpenter <72501f147b2753e6660fdce744d9ac3084854f5e@gmail.com>
Acked-by: Lennert Buytenhek <8858498612e3a522354216649776e3032dcb7e5b@wantstofly.org>
Signed-off-by: David S. Miller <fe08d3c717adf2ae63592e4c9aec6e3e404d8e3e@davemloft.net>

--- drivers/net/mv643xx_eth.c
+++ drivers/net/mv643xx_eth.c
@@ -2675,7 +2675,8 @@
 	 * Detect hardware parameters.
 	 */
 	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
-	msp->tx_csum_limit = pd->tx_csum_limit ? pd->tx_csum_limit : 9 * 1024;
+	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
+					pd->tx_csum_limit : 9 * 1024;
 	infer_hw_params(msp);

 	platform_set_drvdata(pdev, msp);


Fix mv643xx_eth compilation.

Fix mv643xx_eth compilation.

Commit 908b637fe793165b6aecdc875cdca67c4959a1ad removed ETH_DMA_ALIGN
but missed a usage of it in a macro, which broke the build.

Signed-off-by: Dave Jones <d5ec0d24602845f6f4b6a35ef729998d1fba5507@redhat.com>
Signed-off-by: Jeff Garzik <f3e731dfa293c7a83119d8aacfa41b5d2d780be9@garzik.org>

--- drivers/net/mv643xx_eth.h
+++ drivers/net/mv643xx_eth.h
@@ -8,6 +8,8 @@
 #include <linux/mii.h>

 #include <linux/mv643xx.h>
+
+#include <asm/dma-mapping.h>

 /* Checksum offload for Tx works for most packets, but
  * fails if previous packet sent did not use hw csum
@@ -47,7 +49,7 @@
 #define ETH_HW_IP_ALIGN		2		/* hw aligns IP header */
 #define ETH_WRAPPER_LEN		(ETH_HW_IP_ALIGN + ETH_HLEN + \
 					ETH_VLAN_HLEN + ETH_FCS_LEN)
-#define ETH_RX_SKB_SIZE		(dev->mtu + ETH_WRAPPER_LEN + ETH_DMA_ALIGN)
+#define ETH_RX_SKB_SIZE		(dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment())

 #define ETH_RX_QUEUES_ENABLED	(1 << 0)	/* use only Q0 for receive */
 #define ETH_TX_QUEUES_ENABLED	(1 << 0)	/* use only Q0 for transmit */


intel-iommu: trivially inline DMA PTE macros

Signed-off-by: Mark McLoughlin <c437454578aa740e24bc1bc37b06380de7125486@redhat.com>
Signed-off-by: David Woodhouse <b460d66aaf00c296a3db1c1d9eeafc081d5f7d70@intel.com>

--- drivers/pci/intel-iommu.c
+++ drivers/pci/intel-iommu.c
@@ -164,16 +164,41 @@
 struct dma_pte {
 	u64 val;
 };
-#define dma_clear_pte(p)	do {(p).val = 0;} while (0)
-
-#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
-#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
-#define dma_set_pte_prot(p, prot) \
-		do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
-#define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK)
-#define dma_set_pte_addr(p, addr) do {\
-		(p).val |= ((addr) & VTD_PAGE_MASK); } while (0)
-#define dma_pte_present(p) (((p).val & 3) != 0)
+
+static inline void dma_clear_pte(struct dma_pte *pte)
+{
+	pte->val = 0;
+}
+
+static inline void dma_set_pte_readable(struct dma_pte *pte)
+{
+	pte->val |= DMA_PTE_READ;
+}
+
+static inline void dma_set_pte_writable(struct dma_pte *pte)
+{
+	pte->val |= DMA_PTE_WRITE;
+}
+
+static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
+{
+	pte->val = (pte->val & ~3) | (prot & 3);
+}
+
+static inline u64 dma_pte_addr(struct dma_pte *pte)
+{
+	return (pte->val & VTD_PAGE_MASK);
+}
+
+static inline void dma_set_pte_addr(struct dma_pte *pte, u64 addr)
+{
+	pte->val |= (addr & VTD_PAGE_MASK);
+}
+
+static inline bool dma_pte_present(struct dma_pte *pte)
+{
+	return (pte->val & 3) != 0;
+}

 struct dmar_domain {
 	int	id;			/* domain id */
@@ -487,7 +512,7 @@
 		if (level == 1)
 			break;

-		if (!dma_pte_present(*pte)) {
+		if (!dma_pte_present(pte)) {
 			tmp_page = alloc_pgtable_page();

 			if (!tmp_page) {
@@ -497,16 +522,16 @@
 			}
 			__iommu_flush_cache(domain->iommu, tmp_page,
 					PAGE_SIZE);
-			dma_set_pte_addr(*pte, virt_to_phys(tmp_page));
+			dma_set_pte_addr(pte, virt_to_phys(tmp_page));
 			/*
 			 * high level table always sets r/w, last level page
 			 * table control read/write
 			 */
-			dma_set_pte_readable(*pte);
-			dma_set_pte_writable(*pte);
+			dma_set_pte_readable(pte);
+			dma_set_pte_writable(pte);
 			__iommu_flush_cache(domain->iommu, pte, sizeof(*pte));
 		}
-		parent = phys_to_virt(dma_pte_addr(*pte));
+		parent = phys_to_virt(dma_pte_addr(pte));
 		level--;
 	}

@@ -529,9 +554,9 @@
 		if (level == total)
 			return pte;

-		if (!dma_pte_present(*pte))
+		if (!dma_pte_present(pte))
 			break;
-		parent = phys_to_virt(dma_pte_addr(*pte));
+		parent = phys_to_virt(dma_pte_addr(pte));
 		total--;
 	}
 	return NULL;
@@ -546,7 +571,7 @@
 	pte = dma_addr_level_pte(domain, addr, 1);

 	if (pte) {
-		dma_clear_pte(*pte);
+		dma_clear_pte(pte);
 		__iommu_flush_cache(domain->iommu, pte, sizeof(*pte));
 	}
 }
@@ -593,8 +618,8 @@
 			pte = dma_addr_level_pte(domain, tmp, level);
 			if (pte) {
 				free_pgtable_page(
-					phys_to_virt(dma_pte_addr(*pte)));
-				dma_clear_pte(*pte);
+					phys_to_virt(dma_pte_addr(pte)));
+				dma_clear_pte(pte);
 				__iommu_flush_cache(domain->iommu,
 						pte, sizeof(*pte));
 			}
@@ -1421,9 +1446,9 @@
 		/* We don't need lock here, nobody else
 		 * touches the iova range
 		 */
-		BUG_ON(dma_pte_addr(*pte));
-		dma_set_pte_addr(*pte, start_pfn << VTD_PAGE_SHIFT);
-		dma_set_pte_prot(*pte, prot);
+		BUG_ON(dma_pte_addr(pte));
+		dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
+		dma_set_pte_prot(pte, prot);
 		__iommu_flush_cache(domain->iommu, pte, sizeof(*pte));
 		start_pfn++;
 		index++;
@@ -2584,7 +2609,7 @@
 	pte = addr_to_dma_pte(domain, iova);

 	if (pte)
-		pfn = dma_pte_addr(*pte);
+		pfn = dma_pte_addr(pte);

 	return pfn >> VTD_PAGE_SHIFT;
 }


ab8500_fg: Remove pointless round_jiffies() call

As HZ is a full-second, there is little point in rounding it.
Let's save a few cycles by using HZ directly.

Signed-off-by: Lee Jones <630e34333487a351a857f6b705e04d30b37c1629@linaro.org>
Signed-off-by: Anton Vorontsov <14deb5e5e417133e888bf47bb6a3555c9bb7d81c@enomsg.org>

--- drivers/power/ab8500_fg.c
+++ drivers/power/ab8500_fg.c
@@ -1854,7 +1854,7 @@
 		}
 		/* Not yet recovered from ovv, reschedule this test */
 		queue_delayed_work(di->fg_wq, &di->fg_check_hw_failure_work,
-				   round_jiffies(HZ));
+				   HZ);
 		} else {
 			dev_dbg(di->dev, "Battery recovered from OVV\n");
 			di->flags.bat_ovv = false;


rtc: rtc-max8998: remove unnecessary platform_set_drvdata()

The driver core clears the driver data to NULL after device_release or
on probe failure, since commit 0998d063100 ("device-core: Ensure drvdata
= NULL when no driver is bound").  Thus, it is not needed to manually
clear the device driver data to NULL.

Signed-off-by: Jingoo Han <fc379137a64feb86ce38ec5811a14280acc1ccfc@samsung.com>
Signed-off-by: Andrew Morton <5c1e68b099950c134891f0b6e179498a8ebe9cf9@linux-foundation.org>
Signed-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org>

--- drivers/rtc/rtc-max8998.c
+++ drivers/rtc/rtc-max8998.c
@@ -274,7 +274,7 @@
 	if (IS_ERR(info->rtc_dev)) {
 		ret = PTR_ERR(info->rtc_dev);
 		dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
-		goto out_rtc;
+		return ret;
 	}

 	ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
@@ -292,10 +292,6 @@
 	}

 	return 0;
-
-out_rtc:
-	platform_set_drvdata(pdev, NULL);
-	return ret;
 }

 static int max8998_rtc_remove(struct platform_device *pdev)


Fix for: Swap name/type in table macros

Fix for: Swap name/type in table macros

--- src/tightdb/objc/tightdb.h
+++ src/tightdb/objc/tightdb.h
@@ -24,7 +24,7 @@
 #import <tightdb/objc/helper_macros.h>

-#define TIGHTDB_TABLE_DEF_1(TableName, CType1, CName1) \
+#define TIGHTDB_TABLE_DEF_1(TableName, CName1, CType1) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 @end \
@@ -57,7 +57,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_1(TableName, CType1, CName1) \
+#define TIGHTDB_TABLE_IMPL_1(TableName, CName1, CType1) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -232,7 +232,7 @@
 TIGHTDB_TABLE_IMPL_1(TableName, CType1, CName1)

-#define TIGHTDB_TABLE_DEF_2(TableName, CType1, CName1, CType2, CName2) \
+#define TIGHTDB_TABLE_DEF_2(TableName, CName1, CType1, CName2, CType2) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -269,7 +269,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_2(TableName, CType1, CName1, CType2, CName2) \
+#define TIGHTDB_TABLE_IMPL_2(TableName, CName1, CType1, CName2, CType2) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -457,7 +457,7 @@
 TIGHTDB_TABLE_IMPL_2(TableName, CType1, CName1, CType2, CName2)

-#define TIGHTDB_TABLE_DEF_3(TableName, CType1, CName1, CType2, CName2, CType3, CName3) \
+#define TIGHTDB_TABLE_DEF_3(TableName, CName1, CType1, CName2, CType2, CName3, CType3) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -498,7 +498,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_3(TableName, CType1, CName1, CType2, CName2, CType3, CName3) \
+#define TIGHTDB_TABLE_IMPL_3(TableName, CName1, CType1, CName2, CType2, CName3, CType3) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -699,7 +699,7 @@
 TIGHTDB_TABLE_IMPL_3(TableName, CType1, CName1, CType2, CName2, CType3, CName3)

-#define TIGHTDB_TABLE_DEF_4(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4) \
+#define TIGHTDB_TABLE_DEF_4(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -744,7 +744,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_4(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4) \
+#define TIGHTDB_TABLE_IMPL_4(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -958,7 +958,7 @@
 TIGHTDB_TABLE_IMPL_4(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4)

-#define TIGHTDB_TABLE_DEF_5(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5) \
+#define TIGHTDB_TABLE_DEF_5(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -1007,7 +1007,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_5(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5) \
+#define TIGHTDB_TABLE_IMPL_5(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -1234,7 +1234,7 @@
 TIGHTDB_TABLE_IMPL_5(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5)

-#define TIGHTDB_TABLE_DEF_6(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6) \
+#define TIGHTDB_TABLE_DEF_6(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -1287,7 +1287,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_6(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6) \
+#define TIGHTDB_TABLE_IMPL_6(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -1527,7 +1527,7 @@
 TIGHTDB_TABLE_IMPL_6(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6)

-#define TIGHTDB_TABLE_DEF_7(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7) \
+#define TIGHTDB_TABLE_DEF_7(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -1584,7 +1584,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_7(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7) \
+#define TIGHTDB_TABLE_IMPL_7(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -1837,7 +1837,7 @@
 TIGHTDB_TABLE_IMPL_7(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7)

-#define TIGHTDB_TABLE_DEF_8(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8) \
+#define TIGHTDB_TABLE_DEF_8(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -1898,7 +1898,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_8(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8) \
+#define TIGHTDB_TABLE_IMPL_8(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -2164,7 +2164,7 @@
 TIGHTDB_TABLE_IMPL_8(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8)

-#define TIGHTDB_TABLE_DEF_9(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9) \
+#define TIGHTDB_TABLE_DEF_9(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -2229,7 +2229,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_9(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9) \
+#define TIGHTDB_TABLE_IMPL_9(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -2508,7 +2508,7 @@
 TIGHTDB_TABLE_IMPL_9(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9)

-#define TIGHTDB_TABLE_DEF_10(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10) \
+#define TIGHTDB_TABLE_DEF_10(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -2577,7 +2577,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_10(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10) \
+#define TIGHTDB_TABLE_IMPL_10(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -2869,7 +2869,7 @@
 TIGHTDB_TABLE_IMPL_10(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10)

-#define TIGHTDB_TABLE_DEF_11(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11) \
+#define TIGHTDB_TABLE_DEF_11(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -2942,7 +2942,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_11(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11) \
+#define TIGHTDB_TABLE_IMPL_11(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -3247,7 +3247,7 @@
 TIGHTDB_TABLE_IMPL_11(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11)

-#define TIGHTDB_TABLE_DEF_12(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12) \
+#define TIGHTDB_TABLE_DEF_12(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -3324,7 +3324,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_12(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12) \
+#define TIGHTDB_TABLE_IMPL_12(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -3642,7 +3642,7 @@
 TIGHTDB_TABLE_IMPL_12(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12)

-#define TIGHTDB_TABLE_DEF_13(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13) \
+#define TIGHTDB_TABLE_DEF_13(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12, CName13, CType13) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -3723,7 +3723,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_13(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13) \
+#define TIGHTDB_TABLE_IMPL_13(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12, CName13, CType13) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -4054,7 +4054,7 @@
 TIGHTDB_TABLE_IMPL_13(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13)

-#define TIGHTDB_TABLE_DEF_14(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13, CType14, CName14) \
+#define TIGHTDB_TABLE_DEF_14(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12, CName13, CType13, CName14, CType14) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -4139,7 +4139,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_14(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13, CType14, CName14) \
+#define TIGHTDB_TABLE_IMPL_14(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12, CName13, CType13, CName14, CType14) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \
@@ -4483,7 +4483,7 @@
 TIGHTDB_TABLE_IMPL_14(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13, CType14, CName14)

-#define TIGHTDB_TABLE_DEF_15(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13, CType14, CName14, CType15, CName15) \
+#define TIGHTDB_TABLE_DEF_15(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12, CName13, CType13, CName14, CType14, CName15, CType15) \
 @interface TableName##_Cursor : CursorBase \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName1, CType1) \
 TIGHTDB_CURSOR_PROPERTY_DEF(CName2, CType2) \
@@ -4572,7 +4572,7 @@
 -(TableName##_Cursor *)objectAtIndex:(size_t)ndx; \
 @end

-#define TIGHTDB_TABLE_IMPL_15(TableName, CType1, CName1, CType2, CName2, CType3, CName3, CType4, CName4, CType5, CName5, CType6, CName6, CType7, CName7, CType8, CName8, CType9, CName9, CType10, CName10, CType11, CName11, CType12, CName12, CType13, CName13, CType14, CName14, CType15, CName15) \
+#define TIGHTDB_TABLE_IMPL_15(TableName, CName1, CType1, CName2, CType2, CName3, CType3, CName4, CType4, CName5, CType5, CName6, CType6, CName7, CType7, CName8, CType8, CName9, CType9, CName10, CType10, CName11, CType11, CName12, CType12, CName13, CType13, CName14, CType14, CName15, CType15) \
 @implementation TableName##_Cursor \
 { \
     OCAccessor *_##CName1; \


rtc: pcf2127: use OFS flag to detect unreliable date and warn the user

The PCF2127 datasheet states that it's wrong to say that the date in
unreliable if BLF (battery low flag) is set but instead, OSF (seconds
register) should be used to check if oscillator, for any reason, stopped.
Battery may be low (usually below 2V5 threshold) but the date may be anyway
correct (typically date is unreliable when input voltage is below 1V2).

Signed-off-by: Andrea Scian <d5ec5ea7a1fff989df0c72af236e965c3e13ddde@dave.eu>
Signed-off-by: Alexandre Belloni <a7228e626ecf0022ac91fc1cd8db88e71d0e5e0e@free-electrons.com>

--- drivers/rtc/rtc-pcf2127.c
+++ drivers/rtc/rtc-pcf2127.c
@@ -33,11 +33,14 @@
 #define PCF2127_REG_MO          (0x08)
 #define PCF2127_REG_YR          (0x09)

+#define PCF2127_OSF             BIT(7)  /* Oscillator Fail flag */
+
 static struct i2c_driver pcf2127_driver;

 struct pcf2127 {
 	struct rtc_device *rtc;
 	int voltage_low; /* indicates if a low_voltage was detected */
+	int oscillator_failed; /* OSF was detected and date is unreliable */
 };

 /*
@@ -59,7 +62,18 @@
 	if (buf[PCF2127_REG_CTRL3] & 0x04) {
 		pcf2127->voltage_low = 1;
 		dev_info(&client->dev,
-			"low voltage detected, date/time is not reliable.\n");
+			"low voltage detected, check/replace RTC battery.\n");
+	}
+
+	if (buf[PCF2127_REG_SC] & PCF2127_OSF) {
+		/*
+		 * no need clear the flag here,
+		 * it will be cleared once the new date is saved
+		 */
+		pcf2127->oscillator_failed = 1;
+		dev_warn(&client->dev,
+			 "oscillator stop detected, date/time is not reliable\n");
+		return -EINVAL;
 	}

 	dev_dbg(&client->dev,
@@ -93,6 +107,7 @@

 static int pcf2127_set_datetime(struct i2c_client *client, struct rtc_time *tm)
 {
+	struct pcf2127 *pcf2127 = i2c_get_clientdata(client);
 	unsigned char buf[8];
 	int i = 0, err;

@@ -106,7 +121,7 @@
 	buf[i++] = PCF2127_REG_SC;

 	/* hours, minutes and seconds */
-	buf[i++] = bin2bcd(tm->tm_sec);
+	buf[i++] = bin2bcd(tm->tm_sec);	/* this will also clear OSF flag */
 	buf[i++] = bin2bcd(tm->tm_min);
 	buf[i++] = bin2bcd(tm->tm_hour);
 	buf[i++] = bin2bcd(tm->tm_mday);
@@ -126,6 +141,9 @@
 		return -EIO;
 	}

+	/* clear OSF flag in client data */
+	pcf2127->oscillator_failed = 0;
+
 	return 0;
 }

@@ -138,7 +156,9 @@
 	switch (cmd) {
 	case RTC_VL_READ:
 		if (pcf2127->voltage_low)
-			dev_info(dev, "low voltage detected, date/time is not reliable.\n");
+			dev_info(dev, "low voltage detected, check/replace battery\n");
+		if (pcf2127->oscillator_failed)
+			dev_info(dev, "oscillator stop detected, date/time is not reliable\n");

 		if (copy_to_user((void __user *)arg, &pcf2127->voltage_low,
 					sizeof(int)))


drivers/rtc/rtc-sirfsoc.c: add alarm_irq_enable support

Add missed alarm_irq_enable() callback for CSR SiRFSoC RTCs.

[5c1e68b099950c134891f0b6e179498a8ebe9cf9@linux-foundation.org: remove unneeded cast]
Signed-off-by: hao liu <bf823d8c48e9e584a59644747b77f6388b7fbbc9@csr.com>
Signed-off-by: Barry Song <a856445693a373abed3e477bd705f7011cbd8a1d@csr.com>
Cc: Alessandro Zummo <f0b9bd96bf07bfecc189c62159960134588fafe5@towertech.it>
Signed-off-by: Andrew Morton <5c1e68b099950c134891f0b6e179498a8ebe9cf9@linux-foundation.org>
Signed-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org>

--- drivers/rtc/rtc-sirfsoc.c
+++ drivers/rtc/rtc-sirfsoc.c
@@ -209,12 +209,37 @@
 	}
 }

+static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
+		unsigned int enabled)
+{
+	unsigned long rtc_status_reg = 0x0;
+	struct sirfsoc_rtc_drv *rtcdrv;
+
+	rtcdrv = dev_get_drvdata(dev);
+
+	local_irq_disable();
+
+	rtc_status_reg = sirfsoc_rtc_iobrg_readl(
+				rtcdrv->rtc_base + RTC_STATUS);
+	if (enabled)
+		rtc_status_reg |= SIRFSOC_RTC_AL0E;
+	else
+		rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
+
+	sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
+	local_irq_enable();
+
+	return 0;
+
+}
+
 static const struct rtc_class_ops sirfsoc_rtc_ops = {
 	.read_time = sirfsoc_rtc_read_time,
 	.set_time = sirfsoc_rtc_set_time,
 	.read_alarm = sirfsoc_rtc_read_alarm,
 	.set_alarm = sirfsoc_rtc_set_alarm,
-	.ioctl = sirfsoc_rtc_ioctl
+	.ioctl = sirfsoc_rtc_ioctl,
+	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
 };

 static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)


s390/zcore: Fix HSA copy length for last block

Currently always one page is copied to a user buffer for the last
HSA block in memcpy_hsa(). Now the correct length is used.

Signed-off-by: Michael Holzheu <db4757c56f54651f568cc7cda79cd93c781b1605@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <52616596d8f5df0d597e85ab515377f92f939c68@de.ibm.com>

--- drivers/s390/char/zcore.c
+++ drivers/s390/char/zcore.c
@@ -127,7 +127,7 @@
 	}
 	if (mode == TO_USER) {
 		if (copy_to_user((__force __user void*) dest + offs, buf,
-				 PAGE_SIZE))
+				 count - offs))
 			return -EFAULT;
 	} else
 		memcpy(dest + offs, buf, count - offs);


[S390] cio: Remember to initialize recovery_lock.

Signed-off-by: Cornelia Huck <94980dd689360e06f79e918bf71ea5fed7a2bc63@de.ibm.com>
Signed-off-by: Martin Schwidefsky <52616596d8f5df0d597e85ab515377f92f939c68@de.ibm.com>

--- drivers/s390/cio/device.c
+++ drivers/s390/cio/device.c
@@ -32,7 +32,7 @@
 #include "io_sch.h"

 static struct timer_list recovery_timer;
-static spinlock_t recovery_lock;
+static DEFINE_SPINLOCK(recovery_lock);
 static int recovery_phase;
 static const unsigned long recovery_delay[] = { 3, 30, 300 };


[transliteration] New data file

[transliteration] New data file


serial: bfin_5xx: always include DMA headers

On Blackfin systems, peripherals that have optional DMA support always
route their interrupts through the corresponding DMA channel -- even
when DMA is not being used.  So in PIO mode, we still need to request
the DMA channel (so interrupts are delivered) which means we need to
always include the DMA header for the DMA defines/functions.

Signed-off-by: Sonic Zhang <c93d368f28096020dd845c4879a931e9d13ab23f@analog.com>
Signed-off-by: Mike Frysinger <8f3f75c74bd5184edcfa6534cab3c13a00a2f794@gentoo.org>
Signed-off-by: Greg Kroah-Hartman <4645f7897fd33786a2ee1264d590b3c400559d85@suse.de>

--- drivers/serial/bfin_5xx.c
+++ drivers/serial/bfin_5xx.c
@@ -23,6 +23,7 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/serial_core.h>
+#include <linux/dma-mapping.h>

 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
 	defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
@@ -33,12 +34,10 @@
 #include <asm/gpio.h>
 #include <mach/bfin_serial_5xx.h>

-#ifdef CONFIG_SERIAL_BFIN_DMA
-#include <linux/dma-mapping.h>
+#include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
-#endif

 #ifdef CONFIG_SERIAL_BFIN_MODULE
 # undef CONFIG_EARLY_PRINTK
@@ -688,6 +687,13 @@

 # ifdef CONFIG_BF54x
 	{
+		/*
+		 * UART2 and UART3 on BF548 share interrupt PINs and DMA
+		 * controllers with SPORT2 and SPORT3. UART rx and tx
+		 * interrupts are generated in PIO mode only when configure
+		 * their peripheral mapping registers properly, which means
+		 * request corresponding DMA channels in PIO mode as well.
+		 */
 		unsigned uart_dma_ch_rx, uart_dma_ch_tx;

 		switch (uart->port.irq) {


spi: Keep chipselect assertion during one message

During all transfers in one message, the device will not be chagned.
So we don't need to deassert chipselect during one message.

Signed-off-by: Kyoungil Kim <d62bf96249e9a6d21b1ade31463a8375562db13f@samsung.com>
Signed-off-by: Grant Likely <9069e6f5a2b566e2674a0ba1e2bf39c12c195fad@secretlab.ca>

--- drivers/spi/spi-s3c64xx.c
+++ drivers/spi/spi-s3c64xx.c
@@ -771,8 +771,6 @@
 			if (list_is_last(&xfer->transfer_list,
 						&msg->transfers))
 				cs_toggle = 1;
-			else
-				disable_cs(sdd, spi);
 		}

 		msg->actual_length += xfer->len;


serial: icom: fix casting warning

serial: icom: fix casting warning

icom_port->uart_port.membase is (unsigned char __iomem *); thus,
casting (unsigned char __iomem *) is necessary to fix the
following warning. Also, local symbols are staticized.

drivers/tty/serial/icom.c:108:26: warning: symbol 'start_proc' was not declared. Should it be static?
drivers/tty/serial/icom.c:116:26: warning: symbol 'stop_proc' was not declared. Should it be static?
drivers/tty/serial/icom.c:123:25: warning: symbol 'int_mask_tbl' was not declared. Should it be static?
drivers/tty/serial/icom.c:1569:54: warning: incorrect type in assignment (different address spaces)
drivers/tty/serial/icom.c:1569:54:    expected unsigned char [noderef] <asn:2>*membase
drivers/tty/serial/icom.c:1569:54:    got char *<noident>
drivers/tty/serial/icom.c:1090:9: warning: cast truncates bits from constant value (ffffff7f becomes 7f)

Signed-off-by: Jingoo Han <fc379137a64feb86ce38ec5811a14280acc1ccfc@samsung.com>
Signed-off-by: Greg Kroah-Hartman <4645f7897fd33786a2ee1264d590b3c400559d85@linuxfoundation.org>

--- drivers/tty/serial/icom.c
+++ drivers/tty/serial/icom.c
@@ -105,7 +105,7 @@
 	{}
 };

-struct lookup_proc_table start_proc[4] = {
+static struct lookup_proc_table start_proc[4] = {
 	{NULL, ICOM_CONTROL_START_A},
 	{NULL, ICOM_CONTROL_START_B},
 	{NULL, ICOM_CONTROL_START_C},
@@ -113,14 +113,14 @@
 };

-struct lookup_proc_table stop_proc[4] = {
+static struct lookup_proc_table stop_proc[4] = {
 	{NULL, ICOM_CONTROL_STOP_A},
 	{NULL, ICOM_CONTROL_STOP_B},
 	{NULL, ICOM_CONTROL_STOP_C},
 	{NULL, ICOM_CONTROL_STOP_D}
 };

-struct lookup_int_table int_mask_tbl[4] = {
+static struct lookup_int_table int_mask_tbl[4] = {
 	{NULL, ICOM_INT_MASK_PRC_A},
 	{NULL, ICOM_INT_MASK_PRC_B},
 	{NULL, ICOM_INT_MASK_PRC_C},
@@ -1087,8 +1087,7 @@

 	/* stop receiver */
 	cmdReg = readb(&ICOM_PORT->dram->CmdReg);
-	writeb(cmdReg & (unsigned char) ~CMD_RCV_ENABLE,
-	       &ICOM_PORT->dram->CmdReg);
+	writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);

 	shutdown(ICOM_PORT);

@@ -1567,7 +1566,7 @@
 			icom_port->uart_port.type = PORT_ICOM;
 			icom_port->uart_port.iotype = UPIO_MEM;
 			icom_port->uart_port.membase =
-					       (char *) icom_adapter->base_addr_pci;
+				(unsigned char __iomem *)icom_adapter->base_addr_pci;
 			icom_port->uart_port.fifosize = 16;
 			icom_port->uart_port.ops = &icom_ops;
 			icom_port->uart_port.line =


USB: more autosuspend timer stuff

USB: more autosuspend timer stuff

This patch (as879) ties up some loose ends from an earlier patch.
These are things I didn't think to include at the time but which
clearly belonged there.

	If an autosuspend fails because driver activity races with
	the autosuspend call, restart the autosuspend timer.

	When a device is resumed by an external request, it counts
	as device activity and should update the last_busy time so
	that the next autoresume won't occur immediately.

Signed-off-by: Alan Stern <75ea6bb7bfc1186f92d26164de5f9268c9a45b59@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <4645f7897fd33786a2ee1264d590b3c400559d85@suse.de>

--- drivers/usb/core/driver.c
+++ drivers/usb/core/driver.c
@@ -983,7 +983,10 @@

 #else

-#define autosuspend_check(udev)		0
+static inline int autosuspend_check(struct usb_device *udev)
+{
+	return 0;
+}

 #endif	/* CONFIG_USB_SUSPEND */

@@ -1041,7 +1044,6 @@
 		if (status < 0)
 			goto done;
 	}
-	cancel_delayed_work(&udev->autosuspend);

 	/* Suspend all the interfaces and then udev itself */
 	if (udev->actconfig) {
@@ -1062,9 +1064,16 @@
 			usb_resume_interface(intf);
 		}

+		/* Try another autosuspend when the interfaces aren't busy */
+		if (udev->auto_pm)
+			autosuspend_check(udev);
+
 	/* If the suspend succeeded, propagate it up the tree */
-	} else if (parent)
-		usb_autosuspend_device(parent);
+	} else {
+		cancel_delayed_work(&udev->autosuspend);
+		if (parent)
+			usb_autosuspend_device(parent);
+	}

  done:
 	// dev_dbg(&udev->dev, "%s: status %d\n", __FUNCTION__, status);
@@ -1475,6 +1484,7 @@
 	usb_pm_lock(udev);
 	udev->auto_pm = 0;
 	status = usb_resume_both(udev);
+	udev->last_busy = jiffies;
 	usb_pm_unlock(udev);

 	/* Now that the device is awake, we can start trying to autosuspend


usb: dwc2: gadget: force gadget initialization in dev mode

When booting with id pin grounded, dwc2 default to host mode.
Thus, force device mode prior initializing gadget part.
Else fifo init will fail since fifo values are not correct
in host mode.

Tested-by: Robert Baldyga <72b1db3d98bf139199de36aba5da00140727c571@samsung.com>
Acked-by: Paul Zimmerman <e1f0d1b12051c0d55589ba9a6d7c10e383763d34@synopsys.com>
Signed-off-by: Gregory Herrero <869cc571e08bd1797a017f1a62bfeeab83fe5bd7@intel.com>
Signed-off-by: Felipe Balbi <94dddeeef08b001e003cce128ddc162a4e2c6cd2@ti.com>

--- drivers/usb/dwc2/gadget.c
+++ drivers/usb/dwc2/gadget.c
@@ -3675,6 +3675,19 @@
 	/* usb phy enable */
 	s3c_hsotg_phy_enable(hsotg);

+	/*
+	 * Force Device mode before initialization.
+	 * This allows correctly configuring fifo for device mode.
+	 */
+	__bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE);
+	__orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
+
+	/*
+	 * According to Synopsys databook, this sleep is needed for the force
+	 * device mode to take effect.
+	 */
+	msleep(25);
+
 	s3c_hsotg_corereset(hsotg);
 	ret = s3c_hsotg_hw_cfg(hsotg);
 	if (ret) {
@@ -3683,6 +3696,9 @@
 	}

 	s3c_hsotg_init(hsotg);
+
+	/* Switch back to default configuration */
+	__bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);

 	hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
 			DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);


[PATCH] USB: usb-net: new device ID passed through module parameter

adds new module parameter "devid" that points to a string with format
"device_name:vendor_id:device_id:flags".  if provided at module load
time, this string is being parsed and a new entry is created in
usb_dev_id[] and pegasus_ids[] so the new device can later be recognized
by the probe routine.  this might be helpful for someone who don't
know/wish to build new module/kernel, but want to use his new usb-to-eth
device that is not yet listed in pegasus.h

Signed-off-by:	Petko Manolov <d4514ba4777cbc4e6ca7a218e6abf096dacd974a@nucleusys.com>
Signed-off-by: Greg Kroah-Hartman <4645f7897fd33786a2ee1264d590b3c400559d85@suse.de>

--- drivers/usb/net/pegasus.c
+++ drivers/usb/net/pegasus.c
@@ -57,12 +57,14 @@

 static int loopback = 0;
 static int mii_mode = 0;
+static char *devid=NULL;

 static struct usb_eth_dev usb_dev_id[] = {
 #define	PEGASUS_DEV(pn, vid, pid, flags)	\
 	{.name = pn, .vendor = vid, .device = pid, .private = flags},
 #include "pegasus.h"
 #undef	PEGASUS_DEV
+	{NULL, 0, 0, 0},
 	{NULL, 0, 0, 0}
 };

@@ -71,6 +73,7 @@
 	{.match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = vid, .idProduct = pid},
 #include "pegasus.h"
 #undef	PEGASUS_DEV
+	{},
 	{}
 };

@@ -79,8 +82,10 @@
 MODULE_LICENSE("GPL");
 module_param(loopback, bool, 0);
 module_param(mii_mode, bool, 0);
+module_param(devid, charp, 0);
 MODULE_PARM_DESC(loopback, "Enable MAC loopback mode (bit 0)");
 MODULE_PARM_DESC(mii_mode, "Enable HomePNA mode (bit 0),default=MII mode = 0");
+MODULE_PARM_DESC(devid, "The format is: 'DEV_name:VendorID:DeviceID:Flags'");

 /* use ethtool to change the level for any given device */
 static int msg_level = -1;
@@ -1410,9 +1415,42 @@
 	.resume = pegasus_resume,
 };

+static void parse_id(char *id)
+{
+	unsigned int vendor_id=0, device_id=0, flags=0, i=0;
+	char *token, *name=NULL;
+
+	if ((token = strsep(&id, ":")) != NULL)
+		name = token;
+	/* name now points to a null terminated string*/
+	if ((token = strsep(&id, ":")) != NULL)
+		vendor_id = simple_strtoul(token, NULL, 16);
+	if ((token = strsep(&id, ":")) != NULL)
+		device_id = simple_strtoul(token, NULL, 16);
+	flags = simple_strtoul(id, NULL, 16);
+	pr_info("%s: new device %s, vendor ID 0x%04x, device ID 0x%04x, flags: 0x%x\n",
+	        driver_name, name, vendor_id, device_id, flags);
+
+	if (vendor_id > 0x10000 || vendor_id == 0)
+		return;
+	if (device_id > 0x10000 || device_id == 0)
+		return;
+
+	for (i=0; usb_dev_id[i].name; i++);
+	usb_dev_id[i].name = name;
+	usb_dev_id[i].vendor = vendor_id;
+	usb_dev_id[i].device = device_id;
+	usb_dev_id[i].private = flags;
+	pegasus_ids[i].match_flags = USB_DEVICE_ID_MATCH_DEVICE;
+	pegasus_ids[i].idVendor = vendor_id;
+	pegasus_ids[i].idProduct = device_id;
+}
+
 static int __init pegasus_init(void)
 {
 	pr_info("%s: %s, " DRIVER_DESC "\n", driver_name, DRIVER_VERSION);
+	if (devid)
+		parse_id(devid);
 	pegasus_workqueue = create_singlethread_workqueue("pegasus");
 	if (!pegasus_workqueue)
 		return -ENOMEM;


fixes issue 501
+ in Vista an extra arg was added in the middle of the
  params to NtGdiOpenDCW so needs special handling

SVN-Revision: 404

--- drmemory/syscall_wingdi.c
+++ drmemory/syscall_wingdi.c
@@ -486,6 +486,7 @@
 static int sysnum_GdiHfontCreate = -1;
 static int sysnum_GdiDoPalette = -1;
 static int sysnum_GdiExtTextOutW = -1;
+static int sysnum_GdiOpenDCW = -1;

 syscall_info_t syscall_gdi32_info[] = {
     {0,"NtGdiInit", OK, 0, },
@@ -701,7 +702,7 @@
     {0,"NtGdiGetColorAdjustment", OK, 8, {{1,sizeof(COLORADJUSTMENT),W,}, }},
     {0,"NtGdiSetColorAdjustment", OK, 8, {{1,sizeof(COLORADJUSTMENT),R,}, }},
     {0,"NtGdiCancelDC", OK, 4, },
-    {0,"NtGdiOpenDCW", OK, 32, {{0,sizeof(UNICODE_STRING),R|CT,SYSARG_TYPE_UNICODE_STRING,}, {1,sizeof(DEVMODEW)/*really var-len*/,R|CT,SYSARG_TYPE_DEVMODEW}, {2,sizeof(UNICODE_STRING),R|CT,SYSARG_TYPE_UNICODE_STRING,}, {6,sizeof(DRIVER_INFO_2W),R,}, {7,sizeof(PUMDHPDEV *),W,}, }},
+    {0,"NtGdiOpenDCW", OK, 28/*32 on Vista+*/, {{0,sizeof(UNICODE_STRING),R|CT,SYSARG_TYPE_UNICODE_STRING,}, {1,sizeof(DEVMODEW)/*really var-len*/,R|CT,SYSARG_TYPE_DEVMODEW}, {2,sizeof(UNICODE_STRING),R|CT,SYSARG_TYPE_UNICODE_STRING,}, /*arg added in middle in Vista so special-cased*/}, &sysnum_GdiOpenDCW},
     {0,"NtGdiGetDCDword", OK, 12, {{2,sizeof(DWORD),W,}, }},
     {0,"NtGdiGetDCPoint", OK, 12, {{2,sizeof(POINTL),W,}, }},
     {0,"NtGdiScaleViewportExtEx", OK, 24, {{5,sizeof(SIZE),W,}, }},
@@ -2086,6 +2087,32 @@
     return true;
 }

+static bool
+handle_GdiOpenDCW(bool pre, void *drcontext, int sysnum, per_thread_t *pt,
+                  dr_mcontext_t *mc)
+{
+    /* An extra arg "BOOL bDisplay" was added as arg #4 in Vista so
+     * we have to special-case the subsequent args, which for Vista+ are:
+     *   {6,sizeof(DRIVER_INFO_2W),R,}, {7,sizeof(PUMDHPDEV *),W,},
+     */
+    uint num_driver = 5;
+    uint num_pump = 6;
+    if (running_on_Vista_or_later()) {
+        check_sysparam_defined(sysnum, 7, mc, sizeof(reg_t));
+        num_driver = 6;
+        num_pump = 7;
+    }
+    if (pre) {
+        check_sysmem(MEMREF_CHECK_DEFINEDNESS, sysnum,
+                     (byte *) pt->sysarg[num_driver], sizeof(DRIVER_INFO_2W),
+                     mc, "DRIVER_INFO_2W");
+    }
+    check_sysmem(pre ? MEMREF_CHECK_ADDRESSABLE : MEMREF_WRITE, sysnum,
+                 (byte *) pt->sysarg[num_pump], sizeof(PUMDHPDEV *),
+                 mc, "PUMDHPDEV*");
+    return true;
+}
+
 bool
 wingdi_process_syscall(bool pre, void *drcontext, int sysnum, per_thread_t *pt,
                        dr_mcontext_t *mc)
@@ -2147,6 +2174,8 @@
             check_sysmem(MEMREF_CHECK_DEFINEDNESS, sysnum, ((byte *)pdx) + cwc*sizeof(INT),
                          cwc*sizeof(INT), mc, "pdx extra size from ETO_PDY");
         }
+    } else if (sysnum == sysnum_GdiOpenDCW) {
+        return handle_GdiOpenDCW(pre, drcontext, sysnum, pt, mc);
     }

     return true; /* execute syscall */


fixup atomic_queue_demo for new print address

--- bp_common/test/src/demos/src/atomic_queue_demo.c
+++ bp_common/test/src/demos/src/atomic_queue_demo.c
@@ -88,7 +88,6 @@
 // the item is returned in dequeue_item
 uint64_t dequeue(uint64_t core_id, queue_item *dequeue_item) {
     uint64_t status = 0;
-    uint64_t print_addr = (uint64_t)(0x000000008FFFFFFF);
     uint64_t print_item;

     // we actually don't care if the tail index changes between
@@ -111,7 +110,9 @@
     // enqueue, the item will have already been copied out
     queue.head_index = (queue.head_index + 1) % QUEUE_LENGTH;
     print_item = *dequeue_item;
-    //printf("Core %d dequeued %d\n", core_id, *dequeue_item);
+    uint64_t mhartid;
+    __asm__ volatile("csrr %0, mhartid": "=r"(mhartid): :);
+    uint64_t print_addr = (uint64_t)0x03000000 + (mhartid << 3);
     __asm__ volatile("sb %0, 0(%1)": : "r"(print_item), "r"(print_addr):);

 done_dequeue: