add parenthesis around full_reg_value for safety

--- TRDB_D5M_camera_interface/quartus/software/camera_software/TRDB_D5M.h
+++ TRDB_D5M_camera_interface/quartus/software/camera_software/TRDB_D5M.h
@@ -22,42 +22,42 @@
 #define TRDB_D5M_ROW_START_REG_MASK                                                                       (0xffff)
 #define TRDB_D5M_ROW_START_REG_SHIFT_AMOUNT                                                               (0)
 #define TRDB_D5M_ROW_START_REG_READ(full_reg_value)                                                       (((full_reg_value) & TRDB_D5M_ROW_START_REG_MASK) >> TRDB_D5M_ROW_START_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_ROW_START_REG_WRITE(full_reg_value, write_value)                                         ((full_reg_value & (~TRDB_D5M_ROW_START_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_START_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_START_REG_MASK))
+#define TRDB_D5M_ROW_START_REG_WRITE(full_reg_value, write_value)                                         (((full_reg_value) & (~TRDB_D5M_ROW_START_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_START_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_START_REG_MASK))

 // RW
 #define TRDB_D5M_COLUMN_START_REG                                                                         (0x02)
 #define TRDB_D5M_COLUMN_START_REG_MASK                                                                    (0xffff)
 #define TRDB_D5M_COLUMN_START_REG_SHIFT_AMOUNT                                                            (0)
 #define TRDB_D5M_COLUMN_START_REG_READ(full_reg_value)                                                    (((full_reg_value) & TRDB_D5M_COLUMN_START_REG_MASK) >> TRDB_D5M_COLUMN_START_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_COLUMN_START_REG_WRITE(full_reg_value, write_value)                                      ((full_reg_value & (~TRDB_D5M_COLUMN_START_REG_MASK)) | (((write_value) << TRDB_D5M_COLUMN_START_REG_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_START_REG_MASK))
+#define TRDB_D5M_COLUMN_START_REG_WRITE(full_reg_value, write_value)                                      (((full_reg_value) & (~TRDB_D5M_COLUMN_START_REG_MASK)) | (((write_value) << TRDB_D5M_COLUMN_START_REG_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_START_REG_MASK))

 // RW
 #define TRDB_D5M_ROW_SIZE_REG                                                                             (0x03)
 #define TRDB_D5M_ROW_SIZE_REG_MASK                                                                        (0xffff)
 #define TRDB_D5M_ROW_SIZE_REG_SHIFT_AMOUNT                                                                (0)
 #define TRDB_D5M_ROW_SIZE_REG_READ(full_reg_value)                                                        (((full_reg_value) & TRDB_D5M_ROW_SIZE_REG_MASK) >> TRDB_D5M_ROW_SIZE_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_ROW_SIZE_REG_WRITE(full_reg_value, write_value)                                          ((full_reg_value & (~TRDB_D5M_ROW_SIZE_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_SIZE_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_SIZE_REG_MASK))
+#define TRDB_D5M_ROW_SIZE_REG_WRITE(full_reg_value, write_value)                                          (((full_reg_value) & (~TRDB_D5M_ROW_SIZE_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_SIZE_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_SIZE_REG_MASK))

 // RW
 #define TRDB_D5M_COLUMN_SIZE_REG                                                                          (0x04)
 #define TRDB_D5M_COLUMN_SIZE_REG_MASK                                                                     (0xffff)
 #define TRDB_D5M_COLUMN_SIZE_REG_SHIFT_AMOUNT                                                             (0)
 #define TRDB_D5M_COLUMN_SIZE_REG_READ(full_reg_value)                                                     (((full_reg_value) & TRDB_D5M_COLUMN_SIZE_REG_MASK) >> TRDB_D5M_COLUMN_SIZE_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_COLUMN_SIZE_REG_WRITE(full_reg_value, write_value)                                       ((full_reg_value & (~TRDB_D5M_COLUMN_SIZE_REG_MASK)) | (((write_value) << TRDB_D5M_COLUMN_SIZE_REG_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_SIZE_REG_MASK))
+#define TRDB_D5M_COLUMN_SIZE_REG_WRITE(full_reg_value, write_value)                                       (((full_reg_value) & (~TRDB_D5M_COLUMN_SIZE_REG_MASK)) | (((write_value) << TRDB_D5M_COLUMN_SIZE_REG_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_SIZE_REG_MASK))

 // RW
 #define TRDB_D5M_HORIZONTAL_BLANK_REG                                                                     (0x05)
 #define TRDB_D5M_HORIZONTAL_BLANK_REG_MASK                                                                (0xffff)
 #define TRDB_D5M_HORIZONTAL_BLANK_REG_SHIFT_AMOUNT                                                        (0)
 #define TRDB_D5M_HORIZONTAL_BLANK_REG_READ(full_reg_value)                                                (((full_reg_value) & TRDB_D5M_HORIZONTAL_BLANK_REG_MASK) >> TRDB_D5M_HORIZONTAL_BLANK_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_HORIZONTAL_BLANK_REG_WRITE(full_reg_value, write_value)                                  ((full_reg_value & (~TRDB_D5M_HORIZONTAL_BLANK_REG_MASK)) | (((write_value) << TRDB_D5M_HORIZONTAL_BLANK_REG_SHIFT_AMOUNT) & TRDB_D5M_HORIZONTAL_BLANK_REG_MASK))
+#define TRDB_D5M_HORIZONTAL_BLANK_REG_WRITE(full_reg_value, write_value)                                  (((full_reg_value) & (~TRDB_D5M_HORIZONTAL_BLANK_REG_MASK)) | (((write_value) << TRDB_D5M_HORIZONTAL_BLANK_REG_SHIFT_AMOUNT) & TRDB_D5M_HORIZONTAL_BLANK_REG_MASK))

 // RW
 #define TRDB_D5M_VERTICAL_BLANK_REG                                                                       (0x06)
 #define TRDB_D5M_VERTICAL_BLANK_REG_MASK                                                                  (0xffff)
 #define TRDB_D5M_VERTICAL_BLANK_REG_SHIFT_AMOUNT                                                          (0)
 #define TRDB_D5M_VERTICAL_BLANK_REG_READ(full_reg_value)                                                  (((full_reg_value) & TRDB_D5M_VERTICAL_BLANK_REG_MASK) >> TRDB_D5M_VERTICAL_BLANK_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_VERTICAL_BLANK_REG_WRITE(full_reg_value, write_value)                                    ((full_reg_value & (~TRDB_D5M_VERTICAL_BLANK_REG_MASK)) | (((write_value) << TRDB_D5M_VERTICAL_BLANK_REG_SHIFT_AMOUNT) & TRDB_D5M_VERTICAL_BLANK_REG_MASK))
+#define TRDB_D5M_VERTICAL_BLANK_REG_WRITE(full_reg_value, write_value)                                    (((full_reg_value) & (~TRDB_D5M_VERTICAL_BLANK_REG_MASK)) | (((write_value) << TRDB_D5M_VERTICAL_BLANK_REG_SHIFT_AMOUNT) & TRDB_D5M_VERTICAL_BLANK_REG_MASK))

 // RW
 #define TRDB_D5M_OUTPUT_CONTROL_REG                                                                       (0x07)
@@ -76,25 +76,25 @@
 #define TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_READ(full_reg_value)                               (((full_reg_value) & TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_MASK) >> TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_SHIFT_AMOUNT)
 #define TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_READ(full_reg_value)                                      (((full_reg_value) & TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_MASK) >> TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_SHIFT_AMOUNT)
 #define TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_READ(full_reg_value)                              (((full_reg_value) & TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_MASK) >> TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_SHIFT_AMOUNT)
-#define TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_WRITE(full_reg_value, write_value)                   ((full_reg_value & (~TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_MASK))
-#define TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_WRITE(full_reg_value, write_value)                   ((full_reg_value & (~TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_MASK))
-#define TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_WRITE(full_reg_value, write_value)                 ((full_reg_value & (~TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_MASK))
-#define TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_WRITE(full_reg_value, write_value)                        ((full_reg_value & (~TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_MASK))
-#define TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_WRITE(full_reg_value, write_value)                ((full_reg_value & (~TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_MASK))
+#define TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_WRITE(full_reg_value, write_value)                   (((full_reg_value) & (~TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_OUTPUT_SLEW_RATE_MASK))
+#define TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_WRITE(full_reg_value, write_value)                   (((full_reg_value) & (~TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_PIXCLK_SLEW_RATE_MASK))
+#define TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_WRITE(full_reg_value, write_value)                 (((full_reg_value) & (~TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_FIFO_PARALLEL_DATA_MASK))
+#define TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_WRITE(full_reg_value, write_value)                        (((full_reg_value) & (~TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_CHIP_ENABLE_MASK))
+#define TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_WRITE(full_reg_value, write_value)                (((full_reg_value) & (~TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_MASK)) | (((write_value) << TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_SHIFT_AMOUNT) & TRDB_D5M_OUTPUT_CONTROL_REG_SYNCHRONIZE_CHANGES_MASK))

 // RW
 #define TRDB_D5M_SHUTTER_WIDTH_UPPER_REG                                                                  (0x08)
 #define TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_MASK                                                             (0xffff)
 #define TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_SHIFT_AMOUNT                                                     (0)
 #define TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_READ(full_reg_value)                                             (((full_reg_value) & TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_MASK) >> TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_WRITE(full_reg_value, write_value)                               ((full_reg_value & (~TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_MASK)) | (((write_value) << TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_SHIFT_AMOUNT) & TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_MASK))
+#define TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_WRITE(full_reg_value, write_value)                               (((full_reg_value) & (~TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_MASK)) | (((write_value) << TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_SHIFT_AMOUNT) & TRDB_D5M_SHUTTER_WIDTH_UPPER_REG_MASK))

 // RW
 #define TRDB_D5M_SHUTTER_WIDTH_LOWER_REG                                                                  (0x09)
 #define TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_MASK                                                             (0xffff)
 #define TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_SHIFT_AMOUNT                                                     (0)
 #define TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_READ(full_reg_value)                                             (((full_reg_value) & TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_MASK) >> TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_WRITE(full_reg_value, write_value)                               ((full_reg_value & (~TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_MASK)) | (((write_value) << TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_SHIFT_AMOUNT) & TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_MASK))
+#define TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_WRITE(full_reg_value, write_value)                               (((full_reg_value) & (~TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_MASK)) | (((write_value) << TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_SHIFT_AMOUNT) & TRDB_D5M_SHUTTER_WIDTH_LOWER_REG_MASK))

 // RW
 #define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG                                                                  (0x0a)
@@ -107,9 +107,9 @@
 #define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_READ(full_reg_value)                          (((full_reg_value) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_MASK) >> TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_SHIFT_AMOUNT)
 #define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_READ(full_reg_value)                           (((full_reg_value) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_MASK) >> TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_SHIFT_AMOUNT)
 #define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_READ(full_reg_value)                          (((full_reg_value) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_MASK) >> TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_SHIFT_AMOUNT)
-#define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_WRITE(full_reg_value, write_value)            ((full_reg_value & (~TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_MASK)) | (((write_value) << TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_SHIFT_AMOUNT) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_MASK))
-#define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_WRITE(full_reg_value, write_value)             ((full_reg_value & (~TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_MASK)) | (((write_value) << TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_SHIFT_AMOUNT) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_MASK))
-#define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_WRITE(full_reg_value, write_value)            ((full_reg_value & (~TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_MASK)) | (((write_value) << TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_SHIFT_AMOUNT) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_MASK))
+#define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_WRITE(full_reg_value, write_value)            (((full_reg_value) & (~TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_MASK)) | (((write_value) << TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_SHIFT_AMOUNT) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_INVERT_PIXEL_CLOCK_MASK))
+#define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_WRITE(full_reg_value, write_value)             (((full_reg_value) & (~TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_MASK)) | (((write_value) << TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_SHIFT_AMOUNT) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_SHIFT_PIXEL_CLOCK_MASK))
+#define TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_WRITE(full_reg_value, write_value)            (((full_reg_value) & (~TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_MASK)) | (((write_value) << TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_SHIFT_AMOUNT) & TRDB_D5M_PIXEL_CLOCK_CONTROL_REG_DIVIDE_PIXEL_CLOCK_MASK))

 // RW
 #define TRDB_D5M_RESTART_REG                                                                              (0x0b)
@@ -122,23 +122,23 @@
 #define TRDB_D5M_RESTART_REG_TRIGGER_READ(full_reg_value)                                                 (((full_reg_value) & TRDB_D5M_RESTART_REG_TRIGGER_MASK) >> TRDB_D5M_RESTART_REG_TRIGGER_SHIFT_AMOUNT)
 #define TRDB_D5M_RESTART_REG_PAUSE_RESTART_READ(full_reg_value)                                           (((full_reg_value) & TRDB_D5M_RESTART_REG_PAUSE_RESTART_MASK) >> TRDB_D5M_RESTART_REG_PAUSE_RESTART_SHIFT_AMOUNT)
 #define TRDB_D5M_RESTART_REG_RESTART_READ(full_reg_value)                                                 (((full_reg_value) & TRDB_D5M_RESTART_REG_RESTART_MASK) >> TRDB_D5M_RESTART_REG_RESTART_SHIFT_AMOUNT)
-#define TRDB_D5M_RESTART_REG_TRIGGER_WRITE(full_reg_value, write_value)                                   ((full_reg_value & (~TRDB_D5M_RESTART_REG_TRIGGER_MASK)) | (((write_value) << TRDB_D5M_RESTART_REG_TRIGGER_SHIFT_AMOUNT) & TRDB_D5M_RESTART_REG_TRIGGER_MASK))
-#define TRDB_D5M_RESTART_REG_PAUSE_RESTART_WRITE(full_reg_value, write_value)                             ((full_reg_value & (~TRDB_D5M_RESTART_REG_PAUSE_RESTART_MASK)) | (((write_value) << TRDB_D5M_RESTART_REG_PAUSE_RESTART_SHIFT_AMOUNT) & TRDB_D5M_RESTART_REG_PAUSE_RESTART_MASK))
-#define TRDB_D5M_RESTART_REG_RESTART_WRITE(full_reg_value, write_value)                                   ((full_reg_value & (~TRDB_D5M_RESTART_REG_RESTART_MASK)) | (((write_value) << TRDB_D5M_RESTART_REG_RESTART_SHIFT_AMOUNT) & TRDB_D5M_RESTART_REG_RESTART_MASK))
+#define TRDB_D5M_RESTART_REG_TRIGGER_WRITE(full_reg_value, write_value)                                   (((full_reg_value) & (~TRDB_D5M_RESTART_REG_TRIGGER_MASK)) | (((write_value) << TRDB_D5M_RESTART_REG_TRIGGER_SHIFT_AMOUNT) & TRDB_D5M_RESTART_REG_TRIGGER_MASK))
+#define TRDB_D5M_RESTART_REG_PAUSE_RESTART_WRITE(full_reg_value, write_value)                             (((full_reg_value) & (~TRDB_D5M_RESTART_REG_PAUSE_RESTART_MASK)) | (((write_value) << TRDB_D5M_RESTART_REG_PAUSE_RESTART_SHIFT_AMOUNT) & TRDB_D5M_RESTART_REG_PAUSE_RESTART_MASK))
+#define TRDB_D5M_RESTART_REG_RESTART_WRITE(full_reg_value, write_value)                                   (((full_reg_value) & (~TRDB_D5M_RESTART_REG_RESTART_MASK)) | (((write_value) << TRDB_D5M_RESTART_REG_RESTART_SHIFT_AMOUNT) & TRDB_D5M_RESTART_REG_RESTART_MASK))

 // RW
 #define TRDB_D5M_SHUTTER_DELAY_REG                                                                        (0x0c)
 #define TRDB_D5M_SHUTTER_DELAY_REG_MASK                                                                   (0xffff)
 #define TRDB_D5M_SHUTTER_DELAY_REG_SHIFT_AMOUNT                                                           (0)
 #define TRDB_D5M_SHUTTER_DELAY_REG_READ(full_reg_value)                                                   (((full_reg_value) & TRDB_D5M_SHUTTER_DELAY_REG_MASK) >> TRDB_D5M_SHUTTER_DELAY_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_SHUTTER_DELAY_REG_WRITE(full_reg_value, write_value)                                     ((full_reg_value & (~TRDB_D5M_SHUTTER_DELAY_REG_MASK)) | (((write_value) << TRDB_D5M_SHUTTER_DELAY_REG_SHIFT_AMOUNT) & TRDB_D5M_SHUTTER_DELAY_REG_MASK))
+#define TRDB_D5M_SHUTTER_DELAY_REG_WRITE(full_reg_value, write_value)                                     (((full_reg_value) & (~TRDB_D5M_SHUTTER_DELAY_REG_MASK)) | (((write_value) << TRDB_D5M_SHUTTER_DELAY_REG_SHIFT_AMOUNT) & TRDB_D5M_SHUTTER_DELAY_REG_MASK))

 // RW
 #define TRDB_D5M_RESET_REG                                                                                (0x0d)
 #define TRDB_D5M_RESET_REG_MASK                                                                           (0xffff)
 #define TRDB_D5M_RESET_REG_SHIFT_AMOUNT                                                                   (0)
 #define TRDB_D5M_RESET_REG_READ(full_reg_value)                                                           (((full_reg_value) & TRDB_D5M_RESET_REG_MASK) >> TRDB_D5M_RESET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_RESET_REG_WRITE(full_reg_value, write_value)                                             ((full_reg_value & (~TRDB_D5M_RESET_REG_MASK)) | (((write_value) << TRDB_D5M_RESET_REG_SHIFT_AMOUNT) & TRDB_D5M_RESET_REG_MASK))
+#define TRDB_D5M_RESET_REG_WRITE(full_reg_value, write_value)                                             (((full_reg_value) & (~TRDB_D5M_RESET_REG_MASK)) | (((write_value) << TRDB_D5M_RESET_REG_SHIFT_AMOUNT) & TRDB_D5M_RESET_REG_MASK))

 // RW
 #define TRDB_D5M_PLL_CONTROL_REG                                                                          (0x10)
@@ -148,8 +148,8 @@
 #define TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_SHIFT_AMOUNT                                                   (0)
 #define TRDB_D5M_PLL_CONTROL_REG_USE_PLL_READ(full_reg_value)                                             (((full_reg_value) & TRDB_D5M_PLL_CONTROL_REG_USE_PLL_MASK) >> TRDB_D5M_PLL_CONTROL_REG_USE_PLL_SHIFT_AMOUNT)
 #define TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_READ(full_reg_value)                                           (((full_reg_value) & TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_MASK) >> TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_SHIFT_AMOUNT)
-#define TRDB_D5M_PLL_CONTROL_REG_USE_PLL_WRITE(full_reg_value, write_value)                               ((full_reg_value & (~TRDB_D5M_PLL_CONTROL_REG_USE_PLL_MASK)) | (((write_value) << TRDB_D5M_PLL_CONTROL_REG_USE_PLL_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONTROL_REG_USE_PLL_MASK))
-#define TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_WRITE(full_reg_value, write_value)                             ((full_reg_value & (~TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_MASK)) | (((write_value) << TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_MASK))
+#define TRDB_D5M_PLL_CONTROL_REG_USE_PLL_WRITE(full_reg_value, write_value)                               (((full_reg_value) & (~TRDB_D5M_PLL_CONTROL_REG_USE_PLL_MASK)) | (((write_value) << TRDB_D5M_PLL_CONTROL_REG_USE_PLL_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONTROL_REG_USE_PLL_MASK))
+#define TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_WRITE(full_reg_value, write_value)                             (((full_reg_value) & (~TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_MASK)) | (((write_value) << TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONTROL_REG_POWER_PLL_MASK))

 // RW
 #define TRDB_D5M_PLL_CONFIG_1_REG                                                                         (0x11)
@@ -159,15 +159,15 @@
 #define TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_SHIFT_AMOUNT                                              (0)
 #define TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_READ(full_reg_value)                                       (((full_reg_value) & TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_MASK) >> TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_SHIFT_AMOUNT)
 #define TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_READ(full_reg_value)                                      (((full_reg_value) & TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_MASK) >> TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_SHIFT_AMOUNT)
-#define TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_MASK)) | (((write_value) << TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_MASK))
-#define TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_WRITE(full_reg_value, write_value)                        ((full_reg_value & (~TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_MASK)) | (((write_value) << TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_MASK))
+#define TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_MASK)) | (((write_value) << TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONFIG_1_REG_PLL_M_FACTOR_MASK))
+#define TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_WRITE(full_reg_value, write_value)                        (((full_reg_value) & (~TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_MASK)) | (((write_value) << TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONFIG_1_REG_PLL_N_DIVIDER_MASK))

 // RW
 #define TRDB_D5M_PLL_CONFIG_2_REG                                                                         (0x12)
 #define TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_MASK                                                     (0x001f)
 #define TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_SHIFT_AMOUNT                                             (0)
 #define TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_READ(full_reg_value)                                     (((full_reg_value) & TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_MASK) >> TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_SHIFT_AMOUNT)
-#define TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_WRITE(full_reg_value, write_value)                       ((full_reg_value & (~TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_MASK)) | (((write_value) << TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_MASK))
+#define TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_WRITE(full_reg_value, write_value)                       (((full_reg_value) & (~TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_MASK)) | (((write_value) << TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_SHIFT_AMOUNT) & TRDB_D5M_PLL_CONFIG_2_REG_PLL_P1_DIVIDER_MASK))

 // RW
 #define TRDB_D5M_READ_MODE_1_REG                                                                          (0x1e)
@@ -201,16 +201,16 @@
 #define TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_READ(full_reg_value)                                       (((full_reg_value) & TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_MASK) >> TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_SHIFT_AMOUNT)
 #define TRDB_D5M_READ_MODE_1_REG_STROBE_START_READ(full_reg_value)                                        (((full_reg_value) & TRDB_D5M_READ_MODE_1_REG_STROBE_START_MASK) >> TRDB_D5M_READ_MODE_1_REG_STROBE_START_SHIFT_AMOUNT)
 #define TRDB_D5M_READ_MODE_1_REG_STROBE_END_READ(full_reg_value)                                          (((full_reg_value) & TRDB_D5M_READ_MODE_1_REG_STROBE_END_MASK) >> TRDB_D5M_READ_MODE_1_REG_STROBE_END_SHIFT_AMOUNT)
-#define TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_WRITE(full_reg_value, write_value)                        ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_WRITE(full_reg_value, write_value)                 ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_WRITE(full_reg_value, write_value)                        ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_WRITE(full_reg_value, write_value)                              ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_WRITE(full_reg_value, write_value)                          ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_STROBE_START_WRITE(full_reg_value, write_value)                          ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_STROBE_START_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_STROBE_START_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_STROBE_START_MASK))
-#define TRDB_D5M_READ_MODE_1_REG_STROBE_END_WRITE(full_reg_value, write_value)                            ((full_reg_value & (~TRDB_D5M_READ_MODE_1_REG_STROBE_END_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_STROBE_END_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_STROBE_END_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_WRITE(full_reg_value, write_value)                        (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_XOR_LINE_VALID_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_WRITE(full_reg_value, write_value)                 (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_CONTINUOUS_LINE_VALID_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_WRITE(full_reg_value, write_value)                        (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_INVERT_TRIGGER_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_WRITE(full_reg_value, write_value)                              (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_SNAPSHOT_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_WRITE(full_reg_value, write_value)                          (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_GLOBAL_RESET_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_BULB_EXPOSURE_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_INVERT_STROBE_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_STROBE_ENABLE_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_STROBE_START_WRITE(full_reg_value, write_value)                          (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_STROBE_START_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_STROBE_START_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_STROBE_START_MASK))
+#define TRDB_D5M_READ_MODE_1_REG_STROBE_END_WRITE(full_reg_value, write_value)                            (((full_reg_value) & (~TRDB_D5M_READ_MODE_1_REG_STROBE_END_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_1_REG_STROBE_END_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_1_REG_STROBE_END_MASK))
 #define TRDB_D5M_READ_MODE_1_REG_STROBE_START_FIRST_TRIGGER                                               (0)
 #define TRDB_D5M_READ_MODE_1_REG_STROBE_START_START_OF_SIMULTANEOUS_EXPOSURE                              (1)
 #define TRDB_D5M_READ_MODE_1_REG_STROBE_START_SHUTTER_WIDTH                                               (2)
@@ -236,12 +236,12 @@
 #define TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_READ(full_reg_value)                                      (((full_reg_value) & TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_MASK) >> TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_SHIFT_AMOUNT)
 #define TRDB_D5M_READ_MODE_2_REG_ROW_BLC_READ(full_reg_value)                                             (((full_reg_value) & TRDB_D5M_READ_MODE_2_REG_ROW_BLC_MASK) >> TRDB_D5M_READ_MODE_2_REG_ROW_BLC_SHIFT_AMOUNT)
 #define TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_READ(full_reg_value)                                          (((full_reg_value) & TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_MASK) >> TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_SHIFT_AMOUNT)
-#define TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_WRITE(full_reg_value, write_value)                            ((full_reg_value & (~TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_MASK))
-#define TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_MASK))
-#define TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_WRITE(full_reg_value, write_value)                     ((full_reg_value & (~TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_MASK))
-#define TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_WRITE(full_reg_value, write_value)                        ((full_reg_value & (~TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_MASK))
-#define TRDB_D5M_READ_MODE_2_REG_ROW_BLC_WRITE(full_reg_value, write_value)                               ((full_reg_value & (~TRDB_D5M_READ_MODE_2_REG_ROW_BLC_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_ROW_BLC_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_ROW_BLC_MASK))
-#define TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_WRITE(full_reg_value, write_value)                            ((full_reg_value & (~TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_MASK))
+#define TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_WRITE(full_reg_value, write_value)                            (((full_reg_value) & (~TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_MIRROR_ROW_MASK))
+#define TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_MIRROR_COLUMN_MASK))
+#define TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_WRITE(full_reg_value, write_value)                     (((full_reg_value) & (~TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_COLUMNS_MASK))
+#define TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_WRITE(full_reg_value, write_value)                        (((full_reg_value) & (~TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_SHOW_DARK_ROWS_MASK))
+#define TRDB_D5M_READ_MODE_2_REG_ROW_BLC_WRITE(full_reg_value, write_value)                               (((full_reg_value) & (~TRDB_D5M_READ_MODE_2_REG_ROW_BLC_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_ROW_BLC_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_ROW_BLC_MASK))
+#define TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_WRITE(full_reg_value, write_value)                            (((full_reg_value) & (~TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_MASK)) | (((write_value) << TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_SHIFT_AMOUNT) & TRDB_D5M_READ_MODE_2_REG_COLUMN_SUM_MASK))

 // RW
 #define TRDB_D5M_ROW_ADDRESS_MODE_REG                                                                     (0x22)
@@ -251,8 +251,8 @@
 #define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_SHIFT_AMOUNT                                               (0)
 #define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_READ(full_reg_value)                                        (((full_reg_value) & TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_MASK) >> TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_SHIFT_AMOUNT)
 #define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_READ(full_reg_value)                                       (((full_reg_value) & TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_MASK) >> TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_SHIFT_AMOUNT)
-#define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_WRITE(full_reg_value, write_value)                          ((full_reg_value & (~TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_MASK)) | (((write_value) << TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_SHIFT_AMOUNT) & TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_MASK))
-#define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_MASK)) | (((write_value) << TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_SHIFT_AMOUNT) & TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_MASK))
+#define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_WRITE(full_reg_value, write_value)                          (((full_reg_value) & (~TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_MASK)) | (((write_value) << TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_SHIFT_AMOUNT) & TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_BIN_MASK))
+#define TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_MASK)) | (((write_value) << TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_SHIFT_AMOUNT) & TRDB_D5M_ROW_ADDRESS_MODE_REG_ROW_SKIP_MASK))

 // RW
 #define TRDB_D5M_COLUMN_ADDRESS_MODE_REG                                                                  (0x23)
@@ -262,8 +262,8 @@
 #define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_SHIFT_AMOUNT                                         (0)
 #define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_READ(full_reg_value)                                  (((full_reg_value) & TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_MASK) >> TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_SHIFT_AMOUNT)
 #define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_READ(full_reg_value)                                 (((full_reg_value) & TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_MASK) >> TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_SHIFT_AMOUNT)
-#define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_WRITE(full_reg_value, write_value)                    ((full_reg_value & (~TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_MASK)) | (((write_value) << TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_MASK))
-#define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_WRITE(full_reg_value, write_value)                   ((full_reg_value & (~TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_MASK)) | (((write_value) << TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_MASK))
+#define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_WRITE(full_reg_value, write_value)                    (((full_reg_value) & (~TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_MASK)) | (((write_value) << TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_BIN_MASK))
+#define TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_WRITE(full_reg_value, write_value)                   (((full_reg_value) & (~TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_MASK)) | (((write_value) << TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_SHIFT_AMOUNT) & TRDB_D5M_COLUMN_ADDRESS_MODE_REG_COLUMN_SKIP_MASK))

 // RW
 #define TRDB_D5M_GREEN_1_GAIN_REG                                                                         (0x2b)
@@ -276,9 +276,9 @@
 #define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_READ(full_reg_value)                               (((full_reg_value) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_MASK) >> TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_SHIFT_AMOUNT)
 #define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_READ(full_reg_value)                          (((full_reg_value) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_MASK) >> TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_SHIFT_AMOUNT)
 #define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_READ(full_reg_value)                                (((full_reg_value) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_MASK) >> TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_SHIFT_AMOUNT)
-#define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                 ((full_reg_value & (~TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_MASK))
-#define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)            ((full_reg_value & (~TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_MASK))
-#define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_WRITE(full_reg_value, write_value)                  ((full_reg_value & (~TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_MASK))
+#define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                 (((full_reg_value) & (~TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_DIGITAL_GAIN_MASK))
+#define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)            (((full_reg_value) & (~TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_MULTIPLIER_MASK))
+#define TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_WRITE(full_reg_value, write_value)                  (((full_reg_value) & (~TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_GAIN_REG_GREEN_1_ANALOG_GAIN_MASK))

 // RW
 #define TRDB_D5M_BLUE_GAIN_REG                                                                            (0x2c)
@@ -291,9 +291,9 @@
 #define TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_READ(full_reg_value)                                     (((full_reg_value) & TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_MASK) >> TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_SHIFT_AMOUNT)
 #define TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_READ(full_reg_value)                                (((full_reg_value) & TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_MASK) >> TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_SHIFT_AMOUNT)
 #define TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_READ(full_reg_value)                                      (((full_reg_value) & TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_MASK) >> TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_SHIFT_AMOUNT)
-#define TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                       ((full_reg_value & (~TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_MASK))
-#define TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)                  ((full_reg_value & (~TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_MASK))
-#define TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_WRITE(full_reg_value, write_value)                        ((full_reg_value & (~TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_MASK))
+#define TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                       (((full_reg_value) & (~TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_BLUE_GAIN_REG_BLUE_DIGITAL_GAIN_MASK))
+#define TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)                  (((full_reg_value) & (~TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_MULTIPLIER_MASK))
+#define TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_WRITE(full_reg_value, write_value)                        (((full_reg_value) & (~TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_BLUE_GAIN_REG_BLUE_ANALOG_GAIN_MASK))

 // RW
 #define TRDB_D5M_RED_GAIN_REG                                                                             (0x2d)
@@ -306,9 +306,9 @@
 #define TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_READ(full_reg_value)                                       (((full_reg_value) & TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_MASK) >> TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_SHIFT_AMOUNT)
 #define TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_READ(full_reg_value)                                  (((full_reg_value) & TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_MASK) >> TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_SHIFT_AMOUNT)
 #define TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_READ(full_reg_value)                                        (((full_reg_value) & TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_MASK) >> TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_SHIFT_AMOUNT)
-#define TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_MASK))
-#define TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)                    ((full_reg_value & (~TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_MASK))
-#define TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_WRITE(full_reg_value, write_value)                          ((full_reg_value & (~TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_MASK))
+#define TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_RED_GAIN_REG_RED_DIGITAL_GAIN_MASK))
+#define TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)                    (((full_reg_value) & (~TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_RED_GAIN_REG_RED_ANALOG_MULTIPLIER_MASK))
+#define TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_WRITE(full_reg_value, write_value)                          (((full_reg_value) & (~TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_RED_GAIN_REG_RED_ANALOG_GAIN_MASK))

 // RW
 #define TRDB_D5M_GREEN_2_GAIN_REG                                                                         (0x2e)
@@ -321,37 +321,37 @@
 #define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_READ(full_reg_value)                               (((full_reg_value) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_MASK) >> TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_SHIFT_AMOUNT)
 #define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_READ(full_reg_value)                          (((full_reg_value) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_MASK) >> TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_SHIFT_AMOUNT)
 #define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_READ(full_reg_value)                                (((full_reg_value) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_MASK) >> TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_SHIFT_AMOUNT)
-#define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                 ((full_reg_value & (~TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_MASK))
-#define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)            ((full_reg_value & (~TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_MASK))
-#define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_WRITE(full_reg_value, write_value)                  ((full_reg_value & (~TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_MASK))
+#define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_WRITE(full_reg_value, write_value)                 (((full_reg_value) & (~TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_DIGITAL_GAIN_MASK))
+#define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_WRITE(full_reg_value, write_value)            (((full_reg_value) & (~TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_MULTIPLIER_MASK))
+#define TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_WRITE(full_reg_value, write_value)                  (((full_reg_value) & (~TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_GAIN_REG_GREEN_2_ANALOG_GAIN_MASK))

 // WO
 #define TRDB_D5M_GLOBAL_GAIN_REG                                                                          (0x35)
 #define TRDB_D5M_GLOBAL_GAIN_REG_MASK                                                                     (0xffff)
 #define TRDB_D5M_GLOBAL_GAIN_REG_SHIFT_AMOUNT                                                             (0)
 #define TRDB_D5M_GLOBAL_GAIN_REG_READ(full_reg_value)                                                     (((full_reg_value) & TRDB_D5M_GLOBAL_GAIN_REG_MASK) >> TRDB_D5M_GLOBAL_GAIN_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_GLOBAL_GAIN_REG_WRITE(full_reg_value, write_value)                                       ((full_reg_value & (~TRDB_D5M_GLOBAL_GAIN_REG_MASK)) | (((write_value) << TRDB_D5M_GLOBAL_GAIN_REG_SHIFT_AMOUNT) & TRDB_D5M_GLOBAL_GAIN_REG_MASK))
+#define TRDB_D5M_GLOBAL_GAIN_REG_WRITE(full_reg_value, write_value)                                       (((full_reg_value) & (~TRDB_D5M_GLOBAL_GAIN_REG_MASK)) | (((write_value) << TRDB_D5M_GLOBAL_GAIN_REG_SHIFT_AMOUNT) & TRDB_D5M_GLOBAL_GAIN_REG_MASK))

 // RW
 #define TRDB_D5M_ROW_BLACK_TARGET_REG                                                                     (0x49)
 #define TRDB_D5M_ROW_BLACK_TARGET_REG_MASK                                                                (0xffff)
 #define TRDB_D5M_ROW_BLACK_TARGET_REG_SHIFT_AMOUNT                                                        (0)
 #define TRDB_D5M_ROW_BLACK_TARGET_REG_READ(full_reg_value)                                                (((full_reg_value) & TRDB_D5M_ROW_BLACK_TARGET_REG_MASK) >> TRDB_D5M_ROW_BLACK_TARGET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_ROW_BLACK_TARGET_REG_WRITE(full_reg_value, write_value)                                  ((full_reg_value & (~TRDB_D5M_ROW_BLACK_TARGET_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_BLACK_TARGET_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_BLACK_TARGET_REG_MASK))
+#define TRDB_D5M_ROW_BLACK_TARGET_REG_WRITE(full_reg_value, write_value)                                  (((full_reg_value) & (~TRDB_D5M_ROW_BLACK_TARGET_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_BLACK_TARGET_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_BLACK_TARGET_REG_MASK))

 // RW
 #define TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG                                                             (0x4b)
 #define TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_MASK                                                        (0xffff)
 #define TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_SHIFT_AMOUNT                                                (0)
 #define TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_READ(full_reg_value)                                        (((full_reg_value) & TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_MASK) >> TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_WRITE(full_reg_value, write_value)                          ((full_reg_value & (~TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_MASK))
+#define TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_WRITE(full_reg_value, write_value)                          (((full_reg_value) & (~TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_ROW_BLACK_DEFAULT_OFFSET_REG_MASK))

 // RW
 #define TRDB_D5M_BLC_SAMPLE_SIZE_REG                                                                      (0x5b)
 #define TRDB_D5M_BLC_SAMPLE_SIZE_REG_MASK                                                                 (0xffff)
 #define TRDB_D5M_BLC_SAMPLE_SIZE_REG_SHIFT_AMOUNT                                                         (0)
 #define TRDB_D5M_BLC_SAMPLE_SIZE_REG_READ(full_reg_value)                                                 (((full_reg_value) & TRDB_D5M_BLC_SAMPLE_SIZE_REG_MASK) >> TRDB_D5M_BLC_SAMPLE_SIZE_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_BLC_SAMPLE_SIZE_REG_WRITE(full_reg_value, write_value)                                   ((full_reg_value & (~TRDB_D5M_BLC_SAMPLE_SIZE_REG_MASK)) | (((write_value) << TRDB_D5M_BLC_SAMPLE_SIZE_REG_SHIFT_AMOUNT) & TRDB_D5M_BLC_SAMPLE_SIZE_REG_MASK))
+#define TRDB_D5M_BLC_SAMPLE_SIZE_REG_WRITE(full_reg_value, write_value)                                   (((full_reg_value) & (~TRDB_D5M_BLC_SAMPLE_SIZE_REG_MASK)) | (((write_value) << TRDB_D5M_BLC_SAMPLE_SIZE_REG_SHIFT_AMOUNT) & TRDB_D5M_BLC_SAMPLE_SIZE_REG_MASK))

 // RW
 #define TRDB_D5M_BLC_TUNE_1_REG                                                                           (0x5c)
@@ -361,8 +361,8 @@
 #define TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_SHIFT_AMOUNT                                        (0)
 #define TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_READ(full_reg_value)                                    (((full_reg_value) & TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_MASK) >> TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_SHIFT_AMOUNT)
 #define TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_READ(full_reg_value)                                (((full_reg_value) & TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_MASK) >> TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_SHIFT_AMOUNT)
-#define TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_WRITE(full_reg_value, write_value)                      ((full_reg_value & (~TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_MASK))
-#define TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_WRITE(full_reg_value, write_value)                  ((full_reg_value & (~TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_MASK))
+#define TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_WRITE(full_reg_value, write_value)                      (((full_reg_value) & (~TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_1_REG_BLC_DELTA_DAMPING_MASK))
+#define TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_WRITE(full_reg_value, write_value)                  (((full_reg_value) & (~TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_1_REG_BLC_DAC_SETTLING_TIME_MASK))

 // RW
 #define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG                                                                 (0x5d)
@@ -372,8 +372,8 @@
 #define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_SHIFT_AMOUNT                            (0)
 #define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_READ(full_reg_value)                   (((full_reg_value) & TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_MASK) >> TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_SHIFT_AMOUNT)
 #define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_READ(full_reg_value)                    (((full_reg_value) & TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_MASK) >> TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_SHIFT_AMOUNT)
-#define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_WRITE(full_reg_value, write_value)     ((full_reg_value & (~TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_MASK))
-#define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_WRITE(full_reg_value, write_value)      ((full_reg_value & (~TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_MASK))
+#define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_WRITE(full_reg_value, write_value)     (((full_reg_value) & (~TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_HIGH_DELTA_THRESHOLD_MASK))
+#define TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_WRITE(full_reg_value, write_value)      (((full_reg_value) & (~TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_DELTA_THRESHOLDS_REG_BLC_LOW_DELTA_THRESHOLD_MASK))

 // RW
 #define TRDB_D5M_BLC_TUNE_2_REG                                                                           (0x5e)
@@ -383,8 +383,8 @@
 #define TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_SHIFT_AMOUNT                                               (0)
 #define TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_READ(full_reg_value)                                        (((full_reg_value) & TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_MASK) >> TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_SHIFT_AMOUNT)
 #define TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_READ(full_reg_value)                                       (((full_reg_value) & TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_MASK) >> TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_SHIFT_AMOUNT)
-#define TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_WRITE(full_reg_value, write_value)                          ((full_reg_value & (~TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_MASK))
-#define TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_WRITE(full_reg_value, write_value)                         ((full_reg_value & (~TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_MASK))
+#define TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_WRITE(full_reg_value, write_value)                          (((full_reg_value) & (~TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_2_REG_BLC_STEP_SIZE_MASK))
+#define TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_WRITE(full_reg_value, write_value)                         (((full_reg_value) & (~TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_MASK)) | (((write_value) << TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_SHIFT_AMOUNT) & TRDB_D5M_BLC_TUNE_2_REG_BLC_MAX_ADJUST_MASK))

 // RW
 #define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG                                                                (0x5f)
@@ -394,22 +394,22 @@
 #define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_SHIFT_AMOUNT                          (0)
 #define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_READ(full_reg_value)                 (((full_reg_value) & TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_MASK) >> TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_SHIFT_AMOUNT)
 #define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_READ(full_reg_value)                  (((full_reg_value) & TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_MASK) >> TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_SHIFT_AMOUNT)
-#define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_WRITE(full_reg_value, write_value)   ((full_reg_value & (~TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_MASK))
-#define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_WRITE(full_reg_value, write_value)    ((full_reg_value & (~TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_MASK))
+#define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_WRITE(full_reg_value, write_value)   (((full_reg_value) & (~TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_HIGH_TARGET_THRESHOLD_MASK))
+#define TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_WRITE(full_reg_value, write_value)    (((full_reg_value) & (~TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_MASK)) | (((write_value) << TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_SHIFT_AMOUNT) & TRDB_D5M_BLC_TARGET_THRESHOLDS_REG_BLC_LOW_TARGET_THRESHOLD_MASK))

 // RW
 #define TRDB_D5M_GREEN_1_OFFSET_REG                                                                       (0x60)
 #define TRDB_D5M_GREEN_1_OFFSET_REG_MASK                                                                  (0xffff)
 #define TRDB_D5M_GREEN_1_OFFSET_REG_SHIFT_AMOUNT                                                          (0)
 #define TRDB_D5M_GREEN_1_OFFSET_REG_READ(full_reg_value)                                                  (((full_reg_value) & TRDB_D5M_GREEN_1_OFFSET_REG_MASK) >> TRDB_D5M_GREEN_1_OFFSET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_GREEN_1_OFFSET_REG_WRITE(full_reg_value, write_value)                                    ((full_reg_value & (~TRDB_D5M_GREEN_1_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_OFFSET_REG_MASK))
+#define TRDB_D5M_GREEN_1_OFFSET_REG_WRITE(full_reg_value, write_value)                                    (((full_reg_value) & (~TRDB_D5M_GREEN_1_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_GREEN_1_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_GREEN_1_OFFSET_REG_MASK))

 // RW
 #define TRDB_D5M_GREEN_2_OFFSET_REG                                                                       (0x61)
 #define TRDB_D5M_GREEN_2_OFFSET_REG_MASK                                                                  (0xffff)
 #define TRDB_D5M_GREEN_2_OFFSET_REG_SHIFT_AMOUNT                                                          (0)
 #define TRDB_D5M_GREEN_2_OFFSET_REG_READ(full_reg_value)                                                  (((full_reg_value) & TRDB_D5M_GREEN_2_OFFSET_REG_MASK) >> TRDB_D5M_GREEN_2_OFFSET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_GREEN_2_OFFSET_REG_WRITE(full_reg_value, write_value)                                    ((full_reg_value & (~TRDB_D5M_GREEN_2_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_OFFSET_REG_MASK))
+#define TRDB_D5M_GREEN_2_OFFSET_REG_WRITE(full_reg_value, write_value)                                    (((full_reg_value) & (~TRDB_D5M_GREEN_2_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_GREEN_2_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_GREEN_2_OFFSET_REG_MASK))

 // RW
 #define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG                                                              (0x62)
@@ -434,27 +434,27 @@
 #define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_READ(full_reg_value)                   (((full_reg_value) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_MASK) >> TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_SHIFT_AMOUNT)
 #define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_READ(full_reg_value)                     (((full_reg_value) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_MASK) >> TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_SHIFT_AMOUNT)
 #define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_READ(full_reg_value)                              (((full_reg_value) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_MASK) >> TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_SHIFT_AMOUNT)
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_WRITE(full_reg_value, write_value)       ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_MASK))
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_WRITE(full_reg_value, write_value)    ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_MASK))
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_WRITE(full_reg_value, write_value) ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_MASK))
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_WRITE(full_reg_value, write_value)   ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_MASK))
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_WRITE(full_reg_value, write_value)     ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_MASK))
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_WRITE(full_reg_value, write_value)       ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_MASK))
-#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_WRITE(full_reg_value, write_value)                ((full_reg_value & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_WRITE(full_reg_value, write_value)       (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_FAST_SAMPLE_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_WRITE(full_reg_value, write_value)    (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_GREEN_CALIBRATION_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_WRITE(full_reg_value, write_value) (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_LOCK_RED_BLUE_CALIBRATION_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_WRITE(full_reg_value, write_value)   (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_RECALCULATE_BLACK_LEVEL_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_WRITE(full_reg_value, write_value)     (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_BINARY_SEARCH_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_WRITE(full_reg_value, write_value)       (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_DISABLE_CALIBRATION_MASK))
+#define TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_WRITE(full_reg_value, write_value)                (((full_reg_value) & (~TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_MASK)) | (((write_value) << TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_SHIFT_AMOUNT) & TRDB_D5M_BLACK_LEVEL_CALIBRATION_REG_MANUAL_BLC_MASK))

 // RW
 #define TRDB_D5M_RED_OFFSET_REG                                                                           (0x63)
 #define TRDB_D5M_RED_OFFSET_REG_MASK                                                                      (0xffff)
 #define TRDB_D5M_RED_OFFSET_REG_SHIFT_AMOUNT                                                              (0)
 #define TRDB_D5M_RED_OFFSET_REG_READ(full_reg_value)                                                      (((full_reg_value) & TRDB_D5M_RED_OFFSET_REG_MASK) >> TRDB_D5M_RED_OFFSET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_RED_OFFSET_REG_WRITE(full_reg_value, write_value)                                        ((full_reg_value & (~TRDB_D5M_RED_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_RED_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_RED_OFFSET_REG_MASK))
+#define TRDB_D5M_RED_OFFSET_REG_WRITE(full_reg_value, write_value)                                        (((full_reg_value) & (~TRDB_D5M_RED_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_RED_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_RED_OFFSET_REG_MASK))

 // RW
 #define TRDB_D5M_BLUE_OFFSET_REG                                                                          (0x64)
 #define TRDB_D5M_BLUE_OFFSET_REG_MASK                                                                     (0xffff)
 #define TRDB_D5M_BLUE_OFFSET_REG_SHIFT_AMOUNT                                                             (0)
 #define TRDB_D5M_BLUE_OFFSET_REG_READ(full_reg_value)                                                     (((full_reg_value) & TRDB_D5M_BLUE_OFFSET_REG_MASK) >> TRDB_D5M_BLUE_OFFSET_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_BLUE_OFFSET_REG_WRITE(full_reg_value, write_value)                                       ((full_reg_value & (~TRDB_D5M_BLUE_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_BLUE_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_BLUE_OFFSET_REG_MASK))
+#define TRDB_D5M_BLUE_OFFSET_REG_WRITE(full_reg_value, write_value)                                       (((full_reg_value) & (~TRDB_D5M_BLUE_OFFSET_REG_MASK)) | (((write_value) << TRDB_D5M_BLUE_OFFSET_REG_SHIFT_AMOUNT) & TRDB_D5M_BLUE_OFFSET_REG_MASK))

 // RW / WO not specified in datasheet
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG                                                                 (0xa0)
@@ -464,8 +464,8 @@
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_SHIFT_AMOUNT                                (0)
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_READ(full_reg_value)                       (((full_reg_value) & TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_MASK) >> TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_SHIFT_AMOUNT)
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_READ(full_reg_value)                        (((full_reg_value) & TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_MASK) >> TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_SHIFT_AMOUNT)
-#define TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_WRITE(full_reg_value, write_value)         ((full_reg_value & (~TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_MASK))
-#define TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_WRITE(full_reg_value, write_value)          ((full_reg_value & (~TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_MASK))
+#define TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_WRITE(full_reg_value, write_value)         (((full_reg_value) & (~TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_MASK))
+#define TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_WRITE(full_reg_value, write_value)          (((full_reg_value) & (~TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_CONTROL_REG_ENABLE_TEST_PATTERN_MASK))
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_COLOR_FIELD                                (0x0000)
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_HORIZONTAL_GRADIENT                        (0x0008)
 #define TRDB_D5M_TEST_PATTERN_CONTROL_REG_TEST_PATTERN_CONTROL_VERTICAL_GRADIENT                          (0x0010)
@@ -481,28 +481,28 @@
 #define TRDB_D5M_TEST_PATTERN_GREEN_REG_MASK                                                              (0xffff)
 #define TRDB_D5M_TEST_PATTERN_GREEN_REG_SHIFT_AMOUNT                                                      (0)
 #define TRDB_D5M_TEST_PATTERN_GREEN_REG_READ(full_reg_value)                                              (((full_reg_value) & TRDB_D5M_TEST_PATTERN_GREEN_REG_MASK) >> TRDB_D5M_TEST_PATTERN_GREEN_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_TEST_PATTERN_GREEN_REG_WRITE(full_reg_value, write_value)                                ((full_reg_value & (~TRDB_D5M_TEST_PATTERN_GREEN_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_GREEN_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_GREEN_REG_MASK))
+#define TRDB_D5M_TEST_PATTERN_GREEN_REG_WRITE(full_reg_value, write_value)                                (((full_reg_value) & (~TRDB_D5M_TEST_PATTERN_GREEN_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_GREEN_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_GREEN_REG_MASK))

 // RW / WO not specified in datasheet
 #define TRDB_D5M_TEST_PATTERN_RED_REG                                                                     (0xa2)
 #define TRDB_D5M_TEST_PATTERN_RED_REG_MASK                                                                (0xffff)
 #define TRDB_D5M_TEST_PATTERN_RED_REG_SHIFT_AMOUNT                                                        (0)
 #define TRDB_D5M_TEST_PATTERN_RED_REG_READ(full_reg_value)                                                (((full_reg_value) & TRDB_D5M_TEST_PATTERN_RED_REG_MASK) >> TRDB_D5M_TEST_PATTERN_RED_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_TEST_PATTERN_RED_REG_WRITE(full_reg_value, write_value)                                  ((full_reg_value & (~TRDB_D5M_TEST_PATTERN_RED_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_RED_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_RED_REG_MASK))
+#define TRDB_D5M_TEST_PATTERN_RED_REG_WRITE(full_reg_value, write_value)                                  (((full_reg_value) & (~TRDB_D5M_TEST_PATTERN_RED_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_RED_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_RED_REG_MASK))

 // RW / WO not specified in datasheet
 #define TRDB_D5M_TEST_PATTERN_BLUE_REG                                                                    (0xa3)
 #define TRDB_D5M_TEST_PATTERN_BLUE_REG_MASK                                                               (0xffff)
 #define TRDB_D5M_TEST_PATTERN_BLUE_REG_SHIFT_AMOUNT                                                       (0)
 #define TRDB_D5M_TEST_PATTERN_BLUE_REG_READ(full_reg_value)                                               (((full_reg_value) & TRDB_D5M_TEST_PATTERN_BLUE_REG_MASK) >> TRDB_D5M_TEST_PATTERN_BLUE_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_TEST_PATTERN_BLUE_REG_WRITE(full_reg_value, write_value)                                 ((full_reg_value & (~TRDB_D5M_TEST_PATTERN_BLUE_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_BLUE_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_BLUE_REG_MASK))
+#define TRDB_D5M_TEST_PATTERN_BLUE_REG_WRITE(full_reg_value, write_value)                                 (((full_reg_value) & (~TRDB_D5M_TEST_PATTERN_BLUE_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_BLUE_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_BLUE_REG_MASK))

 // RW / WO not specified in datasheet
 #define TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG                                                               (0xa4)
 #define TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_MASK                                                          (0xffff)
 #define TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_SHIFT_AMOUNT                                                  (0)
 #define TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_READ(full_reg_value)                                          (((full_reg_value) & TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_MASK) >> TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_SHIFT_AMOUNT)
-#define TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_WRITE(full_reg_value, write_value)                            ((full_reg_value & (~TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_MASK))
+#define TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_WRITE(full_reg_value, write_value)                            (((full_reg_value) & (~TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_MASK)) | (((write_value) << TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_SHIFT_AMOUNT) & TRDB_D5M_TEST_PATTERN_BAR_WIDTH_REG_MASK))

 // RO
 #define TRDB_D5M_CHIP_VERSION_ALT_REG                                                                     (0xff)


not calling get_frame_type anymore, replaced the value 1 with the macro FF_I_TYPE for tests on the frame type

--- libsjindex/sj_search_index.c
+++ libsjindex/sj_search_index.c
@@ -135,14 +135,14 @@
 {
     // if the next I_frame has a dts inferior to the searched dts then this I_frame is the related key_frame
     for (int i = sj_ic.index_pos; i < sj_ic.index_num; i++){
-        if (sj_ic.indexes[i].pic_type == 1 && sj_ic.indexes[i].dts < sj_ic.indexes[sj_ic.index_pos].dts) {
+        if (sj_ic.indexes[i].pic_type == FF_I_TYPE && sj_ic.indexes[i].dts < sj_ic.indexes[sj_ic.index_pos].dts) {
             *key_frame = sj_ic.indexes[i];
             return 0;
         }
     }
     // otherwise, look before the searched frame
     for (int i = sj_ic.index_pos; i >= 0; i--) {
-        if (sj_ic.indexes[i].pic_type == 1) {
+        if (sj_ic.indexes[i].pic_type == FF_I_TYPE) {
             *key_frame = sj_ic.indexes[i];
             return 0;
         }
@@ -174,8 +174,7 @@
             res = search_frame_dts(sj_ic, idx);
         }
     }
-    char frame = sj_index_get_frame_type(*idx);
-    if (frame != 'I') {
+    if (idx->pic_type != FF_I_TYPE) {
         find_relative_key_frame(key_frame, *sj_ic);
     }


Disable declarations for NPTL.

Disable declarations for NPTL.

--- libc/sysdeps/linux/common/bits/uClibc_pthread.h
+++ libc/sysdeps/linux/common/bits/uClibc_pthread.h
@@ -37,12 +37,14 @@
 extern int weak_function __pthread_mutex_unlock (pthread_mutex_t *__mutex);
 extern void __uclibc_mutex_unlock (void *) attribute_hidden;
 extern int weak_function __pthread_mutex_trylock (pthread_mutex_t *__mutex);
+# ifndef __UCLIBC_HAS_THREADS_NATIVE__
 extern void weak_function _pthread_cleanup_push_defer (
 		struct _pthread_cleanup_buffer *__buffer,
 		void (*__routine) (void *), void *__arg);
 extern void weak_function _pthread_cleanup_pop_restore (
 		struct _pthread_cleanup_buffer *__buffer,
 		int __execute);
+# endif
 #endif

 #endif


Better docs and missing functionality.

Better docs and missing functionality.

--- ext/chipmunk/rb_cpSpace.c
+++ ext/chipmunk/rb_cpSpace.c
@@ -572,6 +572,14 @@
 }

+/** in chipmunk 6
+static VALUE
+rb_cpSpaceUseSpatialHash(VALUE self, VALUE dim, VALUE count) {
+  cpSpaceUseSpatialHash(SPACE(self), NUM2DBL(dim), NUM2INT(count));
+  return Qnil;
+}
+*/
+

 void


Poprawilem operator-

Poprawilem operator-

--- aghIterator.h
+++ aghIterator.h
@@ -259,7 +259,7 @@
 template<typename T>
 aghIterator<T> aghIterator<T>::operator-(int i) {
     aghIterator<T> tmp=*this;
-    tmp.setPosition(this->position+i);
+    tmp.setPosition(this->position-i);
     return tmp;
 }


--- final_platform_layer.h
+++ final_platform_layer.h
@@ -169,6 +169,7 @@
 	- New: [Win32] Implemented fplGetThreadPriority
 	- New: [Win32] Implemented fplSetThreadPriority
 	- Fixed: [Win32] Fixed missing WINAPI keyword for fpl__Win32MonitorCountEnumProc/fpl__Win32MonitorInfoEnumProc/fpl__Win32PrimaryMonitorEnumProc
+	- Fixed: [X11] Software video output was broken

 	## v0.9.3.0 beta
 	- Changed: Renamed fplSetWindowFullscreen to fplSetWindowFullscreenSize
@@ -14251,9 +14252,9 @@
 		colormap = x11Api->XCreateColormap(windowState->display, windowState->root, visual, AllocNone);
 	} else {
 		FPL_LOG_DEBUG(FPL__MODULE_X11, "Using default colormap, visual, color depth");
-		visual = x11Api->XDefaultVisual(windowState->display, windowState->root);
-		colorDepth = x11Api->XDefaultDepth(windowState->display, windowState->root);
-		colormap = x11Api->XDefaultColormap(windowState->display, windowState->root);
+		visual = x11Api->XDefaultVisual(windowState->display, windowState->screen);
+		colorDepth = x11Api->XDefaultDepth(windowState->display, windowState->screen);
+		colormap = x11Api->XDefaultColormap(windowState->display, windowState->screen);
 	}
 	int flags = CWColormap | CWBackPixel | CWBorderPixel | CWEventMask |  CWBitGravity | CWWinGravity;

@@ -14309,8 +14310,17 @@
 	}
 	FPL_LOG_DEBUG(FPL__MODULE_X11, "Successfully created window with (Display='%p', Root='%d', Size=%dx%d, Colordepth='%d', visual='%p', colormap='%d': %d", windowState->display, (int)windowState->root, windowWidth, windowHeight, colorDepth, visual, (int)swa.colormap, (int)windowState->window);

-	// Force keyboard and button events
-	x11Api->XSelectInput(windowState->display, windowState->window, KeyPressMask | KeyReleaseMask | ButtonPressMask | ButtonReleaseMask | PointerMotionMask | ButtonMotionMask);
+	// Force keyboard and button events + paint and resize events
+	int inputMasks =
+	        KeyPressMask |
+	        KeyReleaseMask |
+	        ButtonPressMask |
+	        ButtonReleaseMask |
+	        PointerMotionMask |
+	        ButtonMotionMask |
+	        ExposureMask |
+	        StructureNotifyMask;
+	x11Api->XSelectInput(windowState->display, windowState->window, inputMasks);

 	windowState->visual = visual;

@@ -14431,8 +14441,8 @@

 	switch (ev->type) {
 		case ConfigureNotify:
-		{
-#			if defined(FPL__ENABLE_VIDEO_SOFTWARE)
+		{
+#		if defined(FPL__ENABLE_VIDEO_SOFTWARE)
 			if (appState->currentSettings.video.driver == fplVideoDriverType_Software) {
 				if (appState->initSettings.video.isAutoSize) {
 					uint32_t w = (uint32_t)ev->xconfigure.width;
@@ -14440,7 +14450,7 @@
 					fplResizeVideoBackBuffer(w, h);
 				}
 			}
-#			endif
+#		endif

 			// Window resized
 			fpl__PushWindowSizeEvent(fplWindowEventType_Resized, (uint32_t)ev->xconfigure.width, (uint32_t)ev->xconfigure.height);
@@ -16309,6 +16319,7 @@
 	XImage *buffer;
 } fpl__X11VideoSoftwareState;

+#if 0
 fpl_internal bool fpl__X11SetPreWindowSetupForSoftware(const fpl__X11Api *x11Api, const fpl__X11WindowState *windowState, const fpl__X11VideoSoftwareState *softwareState, fpl__X11PreWindowSetupResult *outResult) {
 	XVisualInfo vinfo = fplZeroInit;
 	if (!x11Api->XMatchVisualInfo(windowState->display, windowState->screen, 32, DirectColor, &vinfo)) {
@@ -16323,6 +16334,7 @@
 	outResult->colorDepth = vinfo.depth;
 	return true;
 }
+#endif

 fpl_internal void fpl__X11ReleaseVideoSoftware(const fpl__X11SubplatformState *subplatform, const fpl__X11WindowState *windowState, fpl__X11VideoSoftwareState *softwareState) {
 	const fpl__X11Api *x11Api = &subplatform->api;
@@ -18398,25 +18410,25 @@
 #			if defined(FPL_SUBPLATFORM_X11)
 				if (fpl__X11InitFrameBufferConfigVideoOpenGL(&appState->x11.api, &appState->window.x11, &initSettings->video, &videoState->x11.opengl)) {
 					result = fpl__X11SetPreWindowSetupForOpenGL(&appState->x11.api, &appState->window.x11, &videoState->x11.opengl, &outResult->x11);
-			}
+				}
 #			endif
-		} break;
+			} break;
 #		endif // FPL__ENABLE_VIDEO_OPENGL

 #		if defined(FPL__ENABLE_VIDEO_SOFTWARE)
 			case fplVideoDriverType_Software:
 			{
-#			if defined(FPL_SUBPLATFORM_X11)
-				result = fpl__X11SetPreWindowSetupForSoftware(&appState->x11.api, &appState->window.x11, &videoState->x11.software, &outResult->x11);
+#			if defined(FPL_SUBPLATFORM_X11) && 0
+			    result = fpl__X11SetPreWindowSetupForSoftware(&appState->x11.api, &appState->window.x11, &videoState->x11.software, &outResult->x11);
 #			endif
-	} break;
+			} break;
 #		endif // FPL__ENABLE_VIDEO_OPENGL

-			default:
-			{
-			} break;
-}
-		}
+		default:
+		{
+		} break;
+	}
+}
 #	endif // FPL__ENABLE_VIDEO

 	return(result);


Avoid unnecessary sign extension when promoted to a 64-bit integer.

This was benign because the interruption info field is a 32-bit quantity and
the hardware guarantees that the upper 32-bits are all zeros. But it did make
reading the objdump output very confusing.


make the use of brace consistent.

make the use of brace consistent.

--- iijpta/ngx_http_secure_token_iijpta.c
+++ iijpta/ngx_http_secure_token_iijpta.c
@@ -71,8 +71,10 @@
 	ngx_conf_num_bounds_t  *bounds = post;
 	ngx_str_t  *sp = data;

-	if (bounds->high == -1) {
-		if (sp->len >= (size_t)bounds->low) {
+	if (bounds->high == -1)
+	{
+		if (sp->len >= (size_t)bounds->low)
+		{
 			return NGX_CONF_OK;
 		}

@@ -83,7 +85,8 @@
 		return NGX_CONF_ERROR;
 	}

-	if (sp->len >= (size_t)bounds->low && sp->len <= (size_t)bounds->high) {
+	if (sp->len >= (size_t)bounds->low && sp->len <= (size_t)bounds->high)
+	{
 		return NGX_CONF_OK;
 	}

@@ -127,27 +130,31 @@
 	memcpy(hdr->crc, &crc, sizeof(crc));

 	ctx = EVP_CIPHER_CTX_new();
-	if (ctx == NULL) {
+	if (ctx == NULL)
+	{
 	    ngx_log_error(NGX_LOG_ERR, r->connection->log, 0,
 			  "ngx_secure_token_iijpta_get_var: EVP_CIPHER_CTX_new failed");
 	    return NGX_ERROR;
 	}

-	if (!EVP_EncryptInit(ctx, EVP_aes_128_cbc(), token->key.data, token->iv.data)) {
+	if (!EVP_EncryptInit(ctx, EVP_aes_128_cbc(), token->key.data, token->iv.data))
+	{
 	    ngx_log_error(NGX_LOG_ERR, r->connection->log, 0,
 			  "ngx_secure_token_iijpta_get_var: EVP_EncryptInit failed");
 	    goto error;
 	}

 	outp = out;
-	if (!EVP_EncryptUpdate(ctx, outp, &out_len, in, in_len)) {
+	if (!EVP_EncryptUpdate(ctx, outp, &out_len, in, in_len))
+	{
 	    ngx_log_error(NGX_LOG_ERR, r->connection->log, 0,
 			  "ngx_secure_token_iijpta_get_var: EVP_EncryptUpdate failed");
 	    goto error;
 	}
 	outp += out_len;

-	if (!EVP_EncryptFinal(ctx, outp, &out_len)) {
+	if (!EVP_EncryptFinal(ctx, outp, &out_len))
+	{
 	    ngx_log_error(NGX_LOG_ERR, r->connection->log, 0,
 			  "ngx_secure_token_iijpta_get_var: EVP_EncryptFinal failed");
 	    goto error;


adfs: improve timestamp precision

adfs: improve timestamp precision

ADFS (FileCore) storage complies with the RISC OS timestamp specification
(40-bit centiseconds since 01 Jan 1900 00:00:00).  It is desirable that
stored timestamp precision be maintained to facilitate a precise copy of
data and metadata from a hard disc (or image thereof) into a RISC OS
emulator (such as RPCEmu).

This patch implements a full-precision conversion from ADFS to Unix
timestamp as the existing driver, for ease of calculation with old 32-bit
compilers, uses the common trick of shifting the 40-bits representing
centiseconds around into 32-bits representing seconds thereby losing
precision.

Signed-off-by: Stuart Swales<242ae9b078593025215718eef07ea2cd0f9023d2@gmail.com>
Cc: Russell King <c2093e01fa868776d7876ac617ce6d2ac30cb904@arm.linux.org.uk>
Signed-off-by: Andrew Morton <5c1e68b099950c134891f0b6e179498a8ebe9cf9@linux-foundation.org>
Signed-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org>

--- fs/adfs/inode.c
+++ fs/adfs/inode.c
@@ -174,49 +174,47 @@

 /*
  * Convert an ADFS time to Unix time.  ADFS has a 40-bit centi-second time
- * referenced to 1 Jan 1900 (til 2248)
+ * referenced to 1 Jan 1900 (til 2248) so we need to discard 2208988800 seconds
+ * of time to convert from RISC OS epoch to Unix epoch.
  */
 static void
 adfs_adfs2unix_time(struct timespec *tv, struct inode *inode)
 {
 	unsigned int high, low;
+	/* 01 Jan 1970 00:00:00 (Unix epoch) as nanoseconds since
+	 * 01 Jan 1900 00:00:00 (RISC OS epoch)
+	 */
+	static const s64 nsec_unix_epoch_diff_risc_os_epoch =
+							2208988800000000000LL;
+	s64 nsec;

 	if (ADFS_I(inode)->stamped == 0)
 		goto cur_time;

-	high = ADFS_I(inode)->loadaddr << 24;
-	low  = ADFS_I(inode)->execaddr;
-
-	high |= low >> 8;
-	low  &= 255;
+	high = ADFS_I(inode)->loadaddr & 0xFF; /* top 8 bits of timestamp */
+	low  = ADFS_I(inode)->execaddr;    /* bottom 32 bits of timestamp */
+
+	/* convert 40-bit centi-seconds to 32-bit seconds
+	 * going via nanoseconds to retain precision
+	 */
+	nsec = (((s64) high << 32) | (s64) low) * 10000000; /* cs to ns */

 	/* Files dated pre  01 Jan 1970 00:00:00. */
-	if (high < 0x336e996a)
+	if (nsec < nsec_unix_epoch_diff_risc_os_epoch)
 		goto too_early;

-	/* Files dated post 18 Jan 2038 03:14:05. */
-	if (high >= 0x656e9969)
-		goto too_late;
-
-	/* discard 2208988800 (0x336e996a00) seconds of time */
-	high -= 0x336e996a;
-
-	/* convert 40-bit centi-seconds to 32-bit seconds */
-	tv->tv_sec = (((high % 100) << 8) + low) / 100 + (high / 100 << 8);
-	tv->tv_nsec = 0;
+	/* convert from RISC OS to Unix epoch */
+	nsec -= nsec_unix_epoch_diff_risc_os_epoch;
+
+	*tv = ns_to_timespec(nsec);
 	return;

  cur_time:
-	*tv = CURRENT_TIME_SEC;
+	*tv = CURRENT_TIME;
 	return;

  too_early:
 	tv->tv_sec = tv->tv_nsec = 0;
-	return;
-
- too_late:
-	tv->tv_sec = 0x7ffffffd;
-	tv->tv_nsec = 0;
 	return;
 }


Moved the rotateQ. I wish I had a reason, but I don't

--- threads/sem.h
+++ threads/sem.h
@@ -35,10 +35,10 @@
 void sem_yield(semaphore_t* sem)
 {
     T_TRACE();
+    RotateQ(&sem->WaitQ);
     AddQ(&sem->WaitQ, DelQ(&RunQ));
     S_TRACE();
     swapcontext(&sem->WaitQ.curr->ctx, &RunQ.curr->ctx);
-    RotateQ(&sem->WaitQ);
 }

 void P(semaphore_t* sem)


Replaced fopen() calls with FileOpen2().

--- InOut/winEPS.c
+++ InOut/winEPS.c
@@ -87,6 +87,7 @@

 typedef struct winEPS_globals_ {
     FILE    *psFile;
+    void    *psfd;                      /* CSFILE* returned by FileOpen2()  */
     char    ps_date[40];                /* Print time & date on every plot  */
     int     currentPage;                /* Current page number              */
 } winEPS_globals_t;
@@ -95,7 +96,6 @@
 {
     winEPS_globals_t  *pp;
     char      *filenam;
-    char      *pathnam_;
     char      pathnam[1024];
     char      *t;
     time_t    lt;
@@ -126,13 +126,9 @@
     t = strrchr(pathnam, '.');
     if (t != NULL) *t = '\0';
     strcat(pathnam, ".eps");
-    pathnam_ = csoundFindOutputFile(csound, pathnam, "SFDIR");
-    pp->psFile = NULL;
-    if (pathnam_ != NULL) {
-      pp->psFile = fopen(pathnam_, "w");
-      mfree(csound, pathnam_);
-    }
-    if (pp->psFile == NULL) {
+    pp->psfd = csound->FileOpen2(csound, &(pp->psFile), CSFILE_STD, pathnam,
+                                   "w", "SFDIR", CSFTYPE_POSTSCRIPT, 0);
+    if (pp->psfd == NULL) {
       csound->Message(csound, Str("** Warning **  PostScript file %s "
                                   "cannot be opened\n"), pathnam);
       csound->winEPS_globals = NULL;
@@ -453,7 +449,7 @@
       fprintf(pp->psFile, "%%%%Trailer \n");
       fprintf(pp->psFile, "%%%%Pages: %d  \n", pp->currentPage);
       fprintf(pp->psFile, "%%%%EOF\n");
-      fclose(pp->psFile);
+      csound->FileClose(csound, pp->psfd);
       csound->winEPS_globals = NULL;
       csound->Free(csound, (void *) pp);
     }


Avoid 0 byte allocation call when statement takes no parameters

--- ext/mysql2/statement.c
+++ ext/mysql2/statement.c
@@ -266,9 +266,6 @@
   // Get count of ordinary arguments, and extract hash opts/keyword arguments
   c = rb_scan_args(argc, argv, "*:", NULL, &opts);

-  // Scratch space for string encoding exports, allocate on the stack
-  params_enc = alloca(sizeof(VALUE) * c);
-
   stmt = stmt_wrapper->stmt;

   bind_count = mysql_stmt_param_count(stmt);
@@ -278,6 +275,8 @@

   // setup any bind variables in the query
   if (bind_count > 0) {
+    // Scratch space for string encoding exports, allocate on the stack
+    params_enc = alloca(sizeof(VALUE) * c);
     bind_buffers = xcalloc(bind_count, sizeof(MYSQL_BIND));
     length_buffers = xcalloc(bind_count, sizeof(unsigned long));