anchor.diff:     
      let verbose = False;
      
  +   RegFile#(Bit#(5),Bit#(BurstLenSize)) clientBurstLen <- mkRegFileFull();
      Reg#(Bit#(BurstLenSize)) burstReg <- mkReg(0);
      Reg#(Bool)               firstReg <- mkReg(True);
      Reg#(Bool)                lastReg <- mkReg(False);
  
positive.code: 	    ,Add#(b__, TLog#(numTags), 6)
  	    ,Add#(beatShift, c__, BurstLenSize)
  	    );
     
     
     // stopping/killing infra
     Vector#(4,Reg#(Bool)) killv <- replicateM(mkReg(False));
  
negative.code:       Bit#(MemTagSize) response_tag = response.tag;
        let drq <- serverProcessing.portA.response.get;
        let otag = drq.req_tag;
        let burstLen = clientBurstLen.sub(truncate(response.tag));
        let first   = firstReg;
        let last    = response.last;
        if (first) begin
  	 last = drq.last;
  	 dynamicAssert(last == (burstLen==1), "Last incorrect");
        end
        Bit#(TLog#(numTags)) tt = truncate(response_tag);
        clientData.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last},
  					       address:{tt,truncate(burstLen)}});
        if (last) begin
  	 tag_gen.returnTag(truncate(response_tag));
        end
        last_readData <= cycle_cnt;
        if (verbose) $display("mkMemReadInternal::read_data cyclediff %d", cycle_cnt-last_readData);
        clientBurstLen.upd(truncate(response.tag), burstLen-1);
        firstReg <= last;
        lastReg  <= burstLen-1 == 1;
     endrule
  
  