anchor.diff:  `endif
   `ifndef PinType
   `define PinType Empty
  -`endif
  -
  -typedef (function Module#(PortalTop#(40, dsz, ipins, `NumberOfMasters)) mkPortalTop()) MkPortalTop#(numeric type dsz, type ipins);
  +
  +typedef `DataBusWidth DataBusWidth;
  +typedef `NumberOfMasters NumberOfMasters;
  +typedef `PinType PinType;
   
   interface PcieTop#(type ipins);
      (* prefix="PCIE" *)
  
positive.code:    interface pins = portalTop.pins;
  endmodule: mkPcieTopFromPortal
  
  (* synthesize *)
  module mkSynthesizeablePortalTop(PortalTop#(40, `DataBusWidth, Empty, `NumberOfMasters));
     let top <- mkPortalTop();
     interface masters = top.masters;
     interface slave = top.slave;
     interface interrupt = top.interrupt;
     interface leds = top.leds;
     interface pins = top.pins;
  endmodule
  
  module mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pci_sys_reset_n)
     (PcieTop#(`PinType));
     let top <- mkPcieTopFromPortal(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n,mkSynthesizeablePortalTop);
     return top;
  endmodule: mkPcieTop
  
negative.code:    interface interruptRequest = mvec[portPortal].interruptRequest;
  endmodule: mkPcieHost
  
  
  (* synthesize *)
  module mkSynthesizeablePortalTop(PortalTop#(40, DataBusWidth, Empty, NumberOfMasters));
     let top <- mkPortalTop();
     interface masters = top.masters;
     interface slave = top.slave;
     interface interrupt = top.interrupt;
     interface leds = top.leds;
     interface pins = top.pins;
  endmodule
  
  (* no_default_clock, no_default_reset *)
  module [Module] mkPcieTopFromPortal #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pci_sys_reset_n)
     (PcieTop#(PinType));
  
     Clock sys_clk_200mhz <- mkClockIBUFDS(sys_clk_p, sys_clk_n);
     Clock sys_clk_200mhz_buf <- mkClockBUFG(clocked_by sys_clk_200mhz);
  