anchor.diff:     // stage 4 (latnecy == 1)
      Vector#(2,FIFOF#(Bit#(addrWidth))) pageResponseFifos <- replicateM(mkFIFOF);
         
  +   FIFO#(DmaError) dmaErrorFifo <- mkFIFO();
  +   rule dmaError;
  +      let error <- toGet(dmaErrorFifo).get();
  +      dmaIndication.dmaError(extend(pack(error.errorType)), error.pref, -1, 0);
  +   endrule
  +
  +
      let page_shift0 = fromInteger(valueOf(SGListPageShift0));
      let page_shift4 = fromInteger(valueOf(SGListPageShift4));
      let page_shift8 = fromInteger(valueOf(SGListPageShift8));
  
positive.code:    Bit#(8) idxOffset;
     } Region deriving (Eq,Bits,FShow);
  
  // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  module mkSGListMMU#(DmaIndication dmaIndication)(SGListMMU#(addrWidth))
     provisos(Log#(MaxNumSGLists, listIdxSize),
  
negative.code: 	 if (off.pageSize == 0) begin
  	    //FIXME offset
  	    //$display("mkSGListMMU.addr[%d].request.put: ERROR   ptr=%h off=%h\n", i, ptr, off);
  	    dmaErrorFifo.enq(DmaError { errorType: DmaErrorBadAddrTrans, pref: extend(ptr) });
  	 end
  	 //$display("p ages[%d].read %h", i, rp[i].first());
  	 portsel(pages, i).request.put(BRAMRequest{write:False, responseOnWrite:False,
  