anchor.diff:      Reg#(Bit#(32)) writeAddrReg <- mkReg(0);
       Reg#(Bit#(32)) readAddrReg <- mkReg(0);
   
  -    Reg#(Bit#(32)) writeCountReg <- mkReg(0);
  -    Reg#(Bit#(32)) readCountReg <- mkReg(0);
  -    Reg#(Bit#(32)) numWordsReg <- mkReg(0);
  +    Reg#(Bit#(16)) writeCountReg <- mkReg(0);
  +    Reg#(Bit#(16)) readCountReg <- mkReg(0);
  +    Reg#(Bit#(16)) numWordsReg <- mkReg(0);
       Reg#(Bit#(busWidth)) valueReg <- mkReg(13);
   
       RegFile#(Bit#(32), Bit#(busWidth)) testDataRegFile <- mkRegFile(0, numWords);
   
       rule enqTestData if (state == EnqWrites && writeCountReg < numWordsReg);
  -        let v = valueReg << 3 + 17;
  +        let v = ((valueReg << 8) + extend(writeCountReg));
           valueReg <= v;
           testDataRegFile.upd(writeAddrReg/fromInteger(valueOf(busWidthBytes)), v);
           writeAddrReg <= writeAddrReg + fromInteger(valueOf(busWidthBytes));
           if (writeCountReg == numWordsReg-1)
               state <= WaitForWriteCompletion;
           writeCountReg <= writeCountReg + 1;
  +	$display("enq v %h", v);
           fifoToAxi.enq(v);
       endrule
   
  
positive.code:     method ActionValue#(Bool) completed();
  endinterface
  
  module mkAxiTester#(FifoToAxi#(busWidth, busWidthBytes) fifoToAxi,
                      FifoFromAxi#(busWidth) fifoFromAxi,
                      Bit#(32) numWords)
                     (AxiTester);
  
      let verbose = False;
      Reg#(TbState) state <- mkReg(Idle);
  
negative.code:         writeCountReg <= 0;
          readCountReg <= 0;
          valueReg <= 13;
          numWordsReg <= truncate(numWords);
  
          fifoToAxi.base <= base;
          fifoFromAxi.base <= base;
  