anchor.diff:     Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) copyReadAddr <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) copyWriteAddr <- mkReg(0);
  -   Reg#(DmaPointer) copyReadHandle <- mkReg(0);
  -   Reg#(DmaPointer) copyWriteHandle <- mkReg(0);
  +   Reg#(DmaPointer) copyReadPointer <- mkReg(0);
  +   Reg#(DmaPointer) copyWritePointer <- mkReg(0);
      Reg#(Bit#(32)) copyTag <- mkReg(0);
      Reg#(Bool) copyBusy <- mkReg(False);
      Reg#(Bit#(4)) cmdCtr <- mkReg(0);
  
positive.code: // The interface to the copyengine is a pair of fifos which supply and accept
  // blocks of 8 64 bit words
  // A Command:
  //  word 0: COPY[63:56] TAG[31:0]
  //  word 1: readMemHandle[63:32]
  //  word 1: readAddress[23:0]
  //  word 2  writeMemHandle[63:32]
  //  word 2: writeAddress[23:0]
  //  word 3: bytecount[15:0]
  //  word 4-7 unused
  // Status
  //  word0-6 all 0
  //  word7  TAG[31:0]
  
negative.code:     rule copyReadWriteRule (copyBusy);
         let data <- copy_read_chan.readData.get;
         //$display("copyReadWrite addr %h", copyWriteAddr);
         copy_write_chan.writeReq.put(DmaRequest{pointer: copyWritePointer, address: copyWriteAddr, burstLen: 1, tag: copyWriteAddr[8:3]});
         copy_write_chan.writeData.put(DmaData{data: data.data, tag: copyWriteAddr[8:3]});
         copyWriteAddr <= copyWriteAddr + 8;
      endrule
  