anchor.diff:          serdest, serdest_inverted.slowClock, clocked_by serdes_clock);
       Wire#(Bit#(1)) bvi_delay_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
  +    SyncBitIfc#(Bit#(1)) bvi_resets_reg <- mkSyncBitToCC(serdes_clock, serdes_reset);
       Wire#(Bit#(1)) bvi_fifo_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
  
positive.code:         let sbs = 0;
    
          dc = dc - 1;
          dreqpipe0 <= serbvi.itemreq();
          dreqpipe1 <= dreqpipe0;
          dfifo_reset_r <= serbvi.ctrl_fifo_reset();
          fifo_reset <= dfifo_reset_r;
  
negative.code: endmodule: mkFIFO18
  
  typedef enum { DIdle, DValid, DLow} DState deriving (Bits,Eq);
  typedef enum { HIdle, HHigh, HLow} HState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden)(IserdesDatadeser);
  