anchor.diff:      method Bit#(3)          ctrl_reset_inc_ce();
       method Action           endhandshake(Bit#(1) v);
       method Bit#(1)          starthandshake();
  +    method Bit#(1)          busy_align_i();
  +    method Action           start_align_i(Bit#(1) v);
   endinterface: Iserdesbvi
   
   import "BVI" iserdes_datadeser = 
  
positive.code:     Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      ReadOnly#(Bit#(3)) samplein_null <- mkNullCrossingWire(serdes_clock, serbvi.samplein());
  
      SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);
  
negative.code:             fwsync = bvi_fifo_wren_wire;
          fifo_wren_sync.send(fwsync);
          iodelay_reset_inc_ce <= sync_reset_inc_ce;
      endrule
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
  