anchor.diff:        rg_sstatus_SUM <= sstatus_SUM;
         rg_mstatus_MXR <= mstatus_MXR;
         rg_satp        <= satp;
  +      rg_tval        <= addr;
         WordXL even_addr = { addr [xlen-1:2], 2'b_00 };
         imem32.req (f3, even_addr, priv, sstatus_SUM, mstatus_MXR, satp);
         if (verbosity > 0) begin
  
positive.code:    Reg #(Bit #(1))  rg_sstatus_SUM <- mkRegU;
     Reg #(Bit #(1))  rg_mstatus_MXR <- mkRegU;
     Reg #(WordXL)    rg_satp        <- mkRegU;
  
     // ----------------------------------------------------------------
  
  
negative.code:    method Instr    instr    = instr_out;
     method Bool     exc      = imem32.exc;
     method Exc_Code exc_code = imem32.exc_code;
     method WordXL   tval     = rg_tval;        // Can be different from rg_pc
  
  endmodule
  
  