anchor.diff:  
      rule updateRule if (bscan.sel() == 1 && bscan.update() == 1 && bscan.capture() == 0);
          requestWire <= tagged Valid (BRAMRequest {write:True, responseOnWrite:False, address:unpack(addrReg), datain:unpack(shiftReg)});
  -       addrReg <= addrReg + 1;
  +       let addr = addrReg + 1;
  +       if (!selected_delay)
  +	  addr = 0;  // first time USER1 selected, reset address
  +       addrReg <= addr;
      endrule
   
      method Bit#(4) debug;
  
positive.code:    Reg#(Bit#(width)) shiftReg <- mkReg(0, clocked_by tck, reset_by rst);
     SyncFIFOIfc#(Bit#(width)) infifo <- mkSyncFIFO(2, defaultClock, defaultReset, tck);
     SyncFIFOIfc#(Bit#(width)) outfifo <- mkSyncFIFO(2, tck, rst, defaultClock);
  
     rule captureRule if (bscan.capture() == 1 && bscan.sel() == 1);
        if (infifo.notEmpty()) begin
  	 //shiftReg <= tagged Valid infifo.first();
  	 infifo.deq();
        end
        //else
        //shiftReg <= 0;
     endrule
     rule shift if (bscan.shift() == 1 && bscan.sel() == 1);
        bscan.tdo(shiftReg[0]);
        let v = (shiftReg >> 1);
        v[width-1] = bscan.tdi();
        shiftReg <= v;
  
negative.code: 	  let d = fromMaybe(unpack(0), m);
  	  shift = pack(d);
         end
         tdow <= shift[0];
         let v = (shift >> 1);
         v[dsz-1] = bscan.tdi();
         shiftReg <= v;
  