anchor.diff:     function Bit#(aw) asel(Bit#(addrWidth) a);
         return a[(port_sel_low-1):0];
      endfunction
  +   function Get#(ObjectData#(dataWidth)) getMemPortalReadData(MemSlave#(aw,dataWidth) x) = x.read_server.readData;
  +   function Put#(ObjectData#(dataWidth)) getMemPortalWriteData(MemSlave#(aw,dataWidth) x) = x.write_server.writeData;
      
      FIFO#(MemRequest#(aw)) req_ars <- mkSizedFIFO(1);
      FIFO#(void) req_ar_fifo <- mkSizedFIFO(1);
      FIFO#(Bit#(TLog#(numInputs))) rs <- mkFIFO();
  -   function Get#(ObjectData#(dataWidth)) bar0(MemSlave#(aw,dataWidth) x) = x.read_server.readData;
  -   Vector#(numInputs, PipeOut#(ObjectData#(dataWidth))) foo0 <- mapM(mkPipeOut, map(bar0,ifcs)); 
  -   FunnelPipe#(1, numInputs, ObjectData#(dataWidth), bpc) read_data_funnel <- mkFunnelPipesPipelined(foo0);
  +   Vector#(numInputs, PipeOut#(ObjectData#(dataWidth))) readDataPipes <- mapM(mkPipeOut, map(getMemPortalReadData,portalIfcs));
  +   FunnelPipe#(1, numInputs, ObjectData#(dataWidth), bpc) read_data_funnel <- mkFunnelPipesPipelined(readDataPipes);
         
      FIFO#(MemRequest#(aw)) req_aws <- mkSizedFIFO(1);
      FIFO#(void) req_aw_fifo <- mkSizedFIFO(1);
      FIFO#(Bit#(TLog#(numInputs))) ws <- mkFIFO();
      FIFOF#(Tuple2#(Bit#(TLog#(numInputs)), ObjectData#(dataWidth))) write_data <- mkFIFOF;
      UnFunnelPipe#(1, numInputs, ObjectData#(dataWidth), bpc) write_data_unfunnel <- mkUnFunnelPipesPipelined(cons(toPipeOut(write_data),nil));
  -   function Put#(ObjectData#(dataWidth)) bar1(MemSlave#(aw,dataWidth) x) = x.write_server.writeData;
  -   Vector#(numInputs, PipeIn#(ObjectData#(dataWidth))) foo1 <- mapM(mkPipeIn, map(bar1,ifcs)); 
  -   zipWithM(mkConnection, write_data_unfunnel, foo1);
  +   Vector#(numInputs, PipeIn#(ObjectData#(dataWidth))) writeDataPipes <- mapM(mkPipeIn, map(getMemPortalWriteData,portalIfcs));
  +   zipWithM(mkConnection, write_data_unfunnel, writeDataPipes);
    
      rule req_aw;
         let req <- toGet(req_aws).get;
  -      ifcs[ws.first].write_server.writeReq.put(req);
  +      portalIfcs[ws.first].write_server.writeReq.put(req);
      endrule
            
      rule req_ar;
         let req <- toGet(req_ars).get;
  -      ifcs[rs.first].read_server.readReq.put(req);
  +      portalIfcs[rs.first].read_server.readReq.put(req);
      endrule
      
      interface MemWriteServer write_server;
  
positive.code:       endinterface
        interface Get readData;
  	 method ActionValue#(ObjectData#(dataWidth)) get();
  	    let rv <- ifcs[rs.first].read_server.readData.get();
  	    //$display("mkMemSlaveMux.readData aw=%d rs=%d data=%h", valueOf(aw), rs.first, rv.data);
  	    //if (rv.last) begin
  	       req_ar_fifo.deq;
  
negative.code: 
     rule req_aw;
        let req <- toGet(req_aws).get;
        portalIfcs[ws.first].write_server.writeReq.put(req);
     endrule
  
     rule req_ar;
        let req <- toGet(req_ars).get;
        portalIfcs[rs.first].read_server.readReq.put(req);
     endrule
  
     interface MemWriteServer write_server;
  