anchor.diff:  import AxiBits::*;
   import AxiStream::*;
   import AxiEthBufferBvi::*;
  -import GetPutWithClocks::*;
   import TriModeMacBvi::*;
   import GigEthPcsPmaBvi::*;
   import AxiEth1000BaseX::*;
  
positive.code:    endmodule
  endinstance
  
  instance ConnectableWithClocks#(AxiStreamMaster#(32), TrimodemacTx_axis_mac);
     module mkConnectionWithClocks#(AxiStreamMaster#(32) from, TrimodemacTx_axis_mac to, Clock fromClock, Reset fromReset, Clock toClock, Reset toReset)(Empty);
        let sfifo <- mkSyncAxisFifo32x1024(fromClock, fromReset, toClock, toReset);
  
        Reg#(Bit#(2)) phaseReg <- mkReg(0, clocked_by toClock, reset_by toReset);
  
        Probe#(Bit#(32)) fromDataProbe <- mkProbe(clocked_by toClock, reset_by toReset);
        Probe#(Bit#(4)) fromKeepProbe <- mkProbe(clocked_by toClock, reset_by toReset);
        Probe#(Bit#(1)) fromLastProbe <- mkProbe(clocked_by toClock, reset_by toReset);
  
        Probe#(Bit#(8)) toDataProbe <- mkProbe(clocked_by toClock, reset_by toReset);
        Probe#(Bit#(4)) toKeepProbe <- mkProbe(clocked_by toClock, reset_by toReset);
        Probe#(Bit#(1)) toLastProbe <- mkProbe(clocked_by toClock, reset_by toReset);
        Probe#(Bit#(1)) toValidProbe <- mkProbe(clocked_by toClock, reset_by toReset);
  
        Probe#(Bit#(2)) phaseProbe    <- mkProbe(clocked_by toClock, reset_by toReset);
        Probe#(Bit#(4)) moreDataProbe <- mkProbe(clocked_by toClock, reset_by toReset);
  
        let fromCnx <- mkConnection(from, sfifo.s_axis);
  
        Wire#(Bool) doDeq <- mkDWire(False, clocked_by toClock, reset_by toReset);
        rule rl_expand if (to.tready() == 1 && sfifo.m_axis.tvalid() == 1);
  
  	 fromDataProbe <= sfifo.m_axis.tdata();
  	 fromKeepProbe <= sfifo.m_axis.tkeep();
  	 fromLastProbe <= sfifo.m_axis.tlast();
  
  	 Vector#(4,Bit#(8)) data = unpack(sfifo.m_axis.tdata());
  	 let keep = sfifo.m_axis.tkeep();
  	 let last = sfifo.m_axis.tlast();
  	 //match { .data, .keep, .last } = sfifo.first();
  	 let phase = phaseReg;
  	 Bool lastPhase = (phaseReg == 3);
  	 Bit#(4) moreData = keep[3:phase+1];
  	 if (!lastPhase)
  	    lastPhase = (moreData == 0);
  
  	 to.tdata(data[phase]);
  	 //to.tkeep(keep[phase]);
  	 to.tlast(pack(last == 1 && lastPhase));
  
  	 toDataProbe <= data[phase];
  	 toLastProbe <= pack(last == 1 && lastPhase);
  
  	 if (lastPhase) begin
  	    //sfifo.deq();
  	    doDeq <= True;
  	    phase = 0;
  	 end
  	 else begin
  	    phase = phase + 1;
  	 end
  	 phaseReg <= phase;
  
  	 phaseProbe <= phase;
  	 moreDataProbe <= moreData;
        endrule
  
        rule rl_to_handshake;
  	 to.tvalid(sfifo.m_axis.tvalid());
  	 toValidProbe <= sfifo.m_axis.tvalid();
  	 sfifo.m_axis.tready(pack(doDeq));
        endrule
     endmodule
  endinstance
  
  instance ConnectableWithClocks#(TrimodemacRx_axis_mac, AxiStreamSlave#(32));
     module mkConnectionWithClocks#(TrimodemacRx_axis_mac from, AxiStreamSlave#(32) to, Clock fromClock, Reset fromReset, Clock toClock, Reset toReset)(Empty);
        Reg#(Bit#(2)) phaseReg <- mkReg(0, clocked_by fromClock, reset_by fromReset);
        Vector#(4,Reg#(Bit#(8))) dataReg <- replicateM(mkReg(0), clocked_by fromClock, reset_by fromReset);
        Reg#(Bit#(4)) keepReg <- mkReg(0, clocked_by fromClock, reset_by fromReset);
        let sfifo <- mkSyncAxisFifo32x1024(fromClock, fromReset, toClock, toReset);
  
        Wire#(Bool) doEnq <- mkDWire(False, clocked_by fromClock, reset_by fromReset);
  
        Probe#(Bool) probeOverrun <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(1)) fromValidProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(8)) fromDataProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(1)) fromLastProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(32)) toDataProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(4)) toKeepProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(2)) phaseProbe    <- mkProbe(clocked_by fromClock, reset_by fromReset);
        Probe#(Bit#(1)) toReadyProbe <- mkProbe(clocked_by toClock, reset_by toReset);
  
        rule rl_overrun if (from.tvalid() == 1 && sfifo.s_axis.tready() == 0);
  	 probeOverrun <= True;
        endrule
  
        rule rl_from_valid;
  	 fromValidProbe <= from.tvalid();
        endrule
  
        rule rl_combine if (unpack(from.tvalid()));
  	 phaseProbe <= phaseReg;
  
  	 Bool last = unpack(from.tlast());
  	 let phase = phaseReg;
  	 Vector#(4,Bit#(8)) data = readVReg(dataReg);
  	 let keep = keepReg;
  	 keep[phase] = 1; //from.tkeep();
  	 data[phase] = from.tdata();
  
  	 sfifo.s_axis.tdata(pack(data));
  	 sfifo.s_axis.tkeep(keep);
  	 sfifo.s_axis.tlast(pack(last));
  
  	 if (last || (phaseReg == 3)) begin
  
  	    toDataProbe <= pack(data);
  	    fromLastProbe <= pack(last); //from.tlast();
  
  	    phase = 0;
  	    data  = unpack(0);
  	    keep  = 0;
  	    doEnq <= True;
  	    //sfifo.enq(tuple3(pack(data), keep, pack(last)));
  	 end
  	 else begin
  	    phase = phase + 1;
  	 end
  
  	 phaseReg <= phase;
  	 writeVReg(dataReg, data);
  	 keepReg  <= keep;
  
  	 fromDataProbe <= from.tdata();
  	 toKeepProbe <= keep;
  
        endrule
  
        rule rl_from_handshake;
  	 //from.tready(pack(sfifo.s_axis.tready())); // scary -- no backpressure
  	 sfifo.s_axis.tvalid(pack(doEnq));
        endrule
  
        rule rl_to_ready_probe;
  	 toReadyProbe <= to.tready();
        endrule	 
  
        let toCnx <- mkConnection(sfifo.m_axis, to);
     endmodule
  endinstance
  
  (* synthesize *)
  module mkAxiEthBvi#(Clock axis_clk, Clock ref_clk)(AxiEthSubsystem);
  
negative.code: 
     // packet data and status from the ethernet
     let rxResetInverted <- mkResetInverter(trimodemac.rx.reset, clocked_by trimodemac.rx.mac_aclk);
     let rxCnx <- mkStreamStatusConnection(trimodemac.rx_axis_mac, axiDmaBvi.s_axis_s2mm, axiDmaBvi.s_axis_s2mm_sts,
  					 trimodemac.rx.mac_aclk, rxResetInverted, clock, reset);
     //mkConnection(axiEthBvi.m_axis_rxs, axiDmaBvi.s_axis_s2mm_sts);
  
     // packet data and control to the ethernet
     let txResetInverted <- mkResetInverter(trimodemac.tx.reset, clocked_by trimodemac.tx.mac_aclk);
     let txCnx <- mkStreamControlConnection(axiDmaBvi.m_axis_mm2s, axiDmaBvi.m_axis_mm2s_cntrl,
  					  trimodemac.tx_axis_mac,
  					  clock, reset, trimodemac.tx.mac_aclk, txResetInverted);
     //mkConnection(axiDmaBvi.m_axis_mm2s_cntrl, axiEthBvi.s_axis_txc);
     interface   mm2s_dma = axiDmaBvi.mm2s;
     interface   s2mm_dma = axiDmaBvi.s2mm;
  