anchor.diff:  	    780: tlpDataScratchpad[4] <= dword;
   	    781: tlpDataScratchpad[5] <= dword;
   
  -	    792: tlpDataBramWrAddrReg <= dword;
  -	    793: tlpTraceLimitReg <= dword;
  +	    792: tlpDataBramWrAddrReg <= truncate(dword);
  +	    793: tlpTraceLimitReg <= truncate(dword);
   
               //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
               // MSIx table entries
  
positive.code:    interface ReadOnly#(Bit#(32)) interruptData;
  
     interface Reg#(Bool)     tlpTracing;
     interface Reg#(Bit#(32)) tlpTraceLimit;
     interface Reg#(Bool) use4dw;
     interface Reg#(Bit#(32)) tlpDataBramWrAddr;
     interface Reg#(Bit#(32)) tlpOutCount;
     interface BRAMServer#(Bit#(11), TimestampedTlpData) tlpDataBram;
  endinterface: ControlAndStatusRegs
  
  // This module encapsulates all of the logic for instantiating and
  
negative.code: import XbsvXilinx7Pcie      :: *;
  //import XbsvXilinx7DDR3      :: *;
  import Portal               :: *;
  import Bscan                :: *;
  
  typedef 11 TlpTraceAddrSize;
  
  typedef struct {
      Bit#(32) timestamp;
  