anchor.diff:     function Put#(ObjectData#(dataWidth)) getMemPortalWriteData(MemSlave#(aw,dataWidth) x) = x.write_server.writeData;
      
      FIFO#(MemRequest#(aw)) req_ars <- mkSizedFIFO(1);
  -   FIFO#(void) req_ar_fifo <- mkSizedFIFO(1);
  -   FIFO#(Bit#(TLog#(numInputs))) rs <- mkFIFO();
  +   FIFO#(Bit#(TLog#(numInputs))) rs <- mkFIFO1();
      Vector#(numInputs, PipeOut#(ObjectData#(dataWidth))) readDataPipes <- mapM(mkPipeOut, map(getMemPortalReadData,portalIfcs));
      FunnelPipe#(1, numInputs, ObjectData#(dataWidth), bpc) read_data_funnel <- mkFunnelPipesPipelined(readDataPipes);
         
  -   FIFO#(MemRequest#(aw)) req_aws <- mkSizedFIFO(1);
  -   FIFO#(void) req_aw_fifo <- mkSizedFIFO(1);
  -   FIFO#(Bit#(TLog#(numInputs))) ws <- mkFIFO();
  +   FIFO#(MemRequest#(aw)) req_aws <- mkFIFO1();
  +   FIFO#(Bit#(TLog#(numInputs))) ws <- mkFIFO1();
      FIFOF#(Tuple2#(Bit#(TLog#(numInputs)), ObjectData#(dataWidth))) write_data <- mkFIFOF;
      UnFunnelPipe#(1, numInputs, ObjectData#(dataWidth), bpc) write_data_unfunnel <- mkUnFunnelPipesPipelined(cons(toPipeOut(write_data),nil));
      Vector#(numInputs, PipeIn#(ObjectData#(dataWidth))) writeDataPipes <- mapM(mkPipeIn, map(getMemPortalWriteData,portalIfcs));
  
positive.code: 	 method Action put(MemRequest#(addrWidth) req);
  	    req_aws.enq(MemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag});
  	    if (req.burstLen > 1) $display("**** \n\n mkSlaveMux.writeReq len=%d \n\n ****", req.burstLen);
  	    req_aw_fifo.enq(?);
  	    ws.enq(truncate(psel(req.addr)));
  	    //$display("mkSlaveMux.writeReq addr=%h aw=%d psel=%h", req.addr, valueOf(aw), psel(req.addr));
  	 endmethod
  
negative.code:       return a[(port_sel_low-1):0];
     endfunction
  
     FIFO#(MemRequest#(aw))   req_ars <- mkFIFO1();
     FIFO#(Bit#(TLog#(numSlaves))) rs <- mkFIFO1();
  
     FIFO#(MemRequest#(aw))   req_aws <- mkFIFO1();
     FIFO#(Bit#(TLog#(numSlaves))) ws <- mkFIFO1();
  
     rule req_aw;
        let req <- toGet(req_aws).get;
  