anchor.diff:  	    780: tlpDataScratchpad[4] <= dword;
   	    781: tlpDataScratchpad[5] <= dword;
   
  -	    792: tlpDataBramWrAddrReg <= dword;
  -	    793: tlpTraceLimitReg <= dword;
  +	    792: tlpDataBramWrAddrReg <= truncate(dword);
  +	    793: tlpTraceLimitReg <= truncate(dword);
   
               //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
               // MSIx table entries
  
positive.code:    endfunction: do_read
  
     rule bramResponse;
         let v <- tlpDataBram1Port.portA.response.get();
         tlpDataBramResponse <= v;
     endrule
  
  
negative.code:    interface Reg use4dw = use4dwReg;
     interface Reg tlpDataBramWrAddr = tlpDataBramWrAddrReg;
     interface Reg tlpOutCount = tlpOutCountReg;
     interface BRAMServer tlpDataBram = bscanBram.server;
  endmodule: mkControlAndStatusRegs
  
  // The PCIe-to-AXI bridge puts all of the elements together
  