anchor.diff:  	 let first    = firstReg;
   	 let last     = lastReg;
   	 if (first) begin
  -	    burstLen = req.burstLen >> beat_shift;
  +	    burstLen = req_burstLen >> beat_shift;
   	    last     = dreqFifo.first.last;
  -	    respFifos.portA.request.put(BRAMRequest{write:True,responseOnWrite:False, address:truncate(rename_tag), datain:RResp{orig_tag:req.tag, client:client}});
  +	    respFifos.portA.request.put(BRAMRequest{write:True,responseOnWrite:False, address:truncate(rename_tag), datain:RResp{orig_tag:req_tag, client:client}});
   	 end
   	 burstReg <= burstLen-1;
   	 firstReg <= (burstLen-1 == 0);
  
positive.code: 	    let rename_tag = reqFifo.first.rename_tag;
  	    if (False && physAddr[31:24] != 0)
  	       $display("req_ar: funny physAddr req.sglId=%d req.offset=%h physAddr=%h", req.sglId, req.offset, physAddr);
  	    dreqBram.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:truncate(rename_tag), datain:DRec{req:req, client:client, rename_tag:rename_tag, last:(req.burstLen == fromInteger(valueOf(dataWidthBytes)))}});
  	    //$display("readReq: client=%d, rename_tag=%d, physAddr=%h req.burstLen=%d beat_shift=%d last=%d", client,rename_tag,physAddr, req.burstLen, beat_shift, req.burstLen == beat_shift);
  	    if (debug) $display("read_client.readReq %d", cycle_cnt-last_readReq);
  	    last_readReq <= cycle_cnt;
  
negative.code:       let response <- toGet(readDataPipelineFifo).get();
        Bit#(MemTagSize) response_tag = response.tag;
        let drq <- dreqBram.portA.response.get;
        let otag = drq.req_tag;
        let burstLen = burstReg;
        let first =    firstReg;
        let last  =    lastReg;
        if (first) begin
  	 burstLen = drq.req_burstLen >> beat_shift;
  	 last = drq.last;
  	 dynamicAssert(last == (burstLen==1), "Last incorrect");
  	 //$display("burstLen=%d dreqFifo.first.last=%d last=%d\n", burstLen, dreqFifo.first.last, last);
  