anchor.diff:     rule handshake2;
           axiWires.awready(awready);
      endrule
  -   rule handshake3;
  -        axiWires.rid(rid);
  -        axiWires.rresp(rresp);
  -        axiWires.rdata(rdata);
  -        axiWires.rlast(rlast);
  -        axiWires.rvalid(rvalid);
  -   endrule
      rule handshake4;
           axiWires.wready(wready);
      endrule
  -   rule handshake5;
  -        axiWires.bvalid(bvalid);
  -        axiWires.bid(bid);
  -        axiWires.bresp(bresp);
  -   endrule
  +
  +   // rule handshake 3 & 5 done in toPutM modules
  +   Put#(Axi3ReadResponse#(dataWidth, tagWidth)) resp_read_put <- toPutM(axiWires);
  +   Put#(Axi3WriteResponse#(tagWidth)) resp_b_put <- toPutM(axiWires);
   
      interface Axi3Master client;
           interface Get req_ar;
  
positive.code:                 return v;
              endmethod
          endinterface
          interface Put resp_b;
              method Action put(Axi3WriteResponse#(tagWidth) v) if (axiWires.bready() != 0);
                  bvalid <= 1;
                  bid    <= v.id;
                  bresp  <= v.resp;
              endmethod
          endinterface
      endinterface
      method aresetn = axiWires.aresetn;
  endmodule
  
negative.code:                 return v;
             endmethod
          endinterface
          interface Put resp_read = resp_read_put;
          interface Get resp_write;
              method ActionValue#(Axi3WriteData#(dataWidth,tagWidth)) get() if (axiWires.wvalid() != 0);
                  Axi3WriteData#(dataWidth,tagWidth) v;
  