anchor.diff:     let axiReset <- mkSyncReset(10, reset, axiClock);
      let axiCtlReset <- mkSyncReset(10, reset, axiCtlClock);
   
  -   let axiRootPort <- mkAPRP(pcie_clk_100mhs_buf, reset, axiClock, axiReset, axiCtlClock, axiCtlReset);
  +   let axiRootPort <- mkAPRP(pcie_clk_100mhz_buf, reset, axiClock, axiReset, axiCtlClock, axiCtlReset);
      let axiClockC2B <- mkC2B(axiRootPort.axi.aclk_out);
      let axiCtlClockC2B <- mkC2B(axiRootPort.axi.ctl_aclk_out);
      rule rl_connect_clocks;
  
positive.code:       endmethod
  
        method Action read(Bit#(32) addr);
  	 araddrFifo.enq(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });
        endmethod
        method Action write(Bit#(32) addr, Bit#(64) value);
  	 awaddrFifo.enq(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });
  	 wdataFifo.enq(MemData {data: value, tag: 0, last: True});
        endmethod
  
        method Action readCtl(Bit#(32) addr);
  	 araddrFifoCtl.enq(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });
        endmethod
        method Action writeCtl(Bit#(32) addr, Bit#(64) value);
  	 araddrFifoCtl.enq(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });
  	 wdataFifoCtl.enq(MemData {data: truncate(value), tag: 0, last: True});
        endmethod
     endinterface
  
negative.code:    let reset <- exposeCurrentReset;
     let refclk_p <- mkB2C1();
     let refclk_n <- mkB2C1();
     let pcie_clk_100mhz_buf <- mkClockIBUFDS_GTE2(
  `ifdef ClockDefaultParam
         defaultValue,
  `endif
  