anchor.diff:     interface Reg#(Bool) axiEnabled;
      interface Reg#(Bool) pipeliningEnabled;
      interface Reg#(Bool) byteSwap;
  +   interface Reg#(Bool) use4dw;
      interface Reg#(Bit#(4)) numPortals;
      interface Reg#(Bit#(32)) axiTestEnabled;
      interface Reg#(Bit#(32)) addrLowerWord;
  
positive.code: 	 794: return byteSwapReg ? 1 : 0;
  	 795: return axiSlaveEngine.tlpOutFifoNotEmpty ? 1 : 0;
  	 796: return extend(numPortalsReg);
  
           // 4-entry MSIx table
           4096: return msix_entry[0].addr_lo;            // entry 0 lower address
  
negative.code:     interface Get#(TLPData#(16))   tlp_out;
      interface Axi3Slave#(40,64,8,12)  slave;
      method Bool tlpOutFifoNotEmpty();
      interface Reg#(Bool) use4dw;
  endinterface: AxiSlaveEngine
  
  module mkAxiSlaveEngine#(PciId my_id)(AxiSlaveEngine);
      FIFOF#(TLPData#(16)) tlpOutFifo <- mkFIFOF;
  
      Reg#(Bit#(7)) hitReg <- mkReg(0);
      Reg#(Bool) use4dwReg <- mkReg(True);
  
      MIMOConfiguration mimoCfg = defaultValue;
      MIMO#(4,2,8,Bit#(32)) completionMimo <- mkMIMO(mimoCfg);
      MIMO#(4,2,8,TLPTag) completionTagMimo <- mkMIMO(mimoCfg);
      Reg#(TLPTag) lastTag <- mkReg(0);
      function LUInt#(4) tlpWordCount(TLPData#(16) tlp);
         if (tlp.be == 16'h0000)
  	  return 0;
         else if (tlp.be == 16'h000f || tlp.be == 16'hf000)
  	  return 1;
         else if (tlp.be == 16'h00ff || tlp.be == 16'hff00)
  	  return 2;
         else if (tlp.be == 16'h0fff || tlp.be == 16'hfff0)
  	  return 3;
         else if (tlp.be == 16'hffff)
  	  return 4;
         else
  	  return 0;
      endfunction
      interface Put tlp_in;
          method Action put(TLPData#(16) tlp);
  	   $display("AxiSlaveEngine.put tlp=%h", tlp);
  	   TLPMemoryIO3DWHeader h = unpack(tlp.data);
  	   hitReg <= tlp.hit;
  	   TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);
  	   Vector#(4, Bit#(32)) vec = unpack(0);
  	   if (!tlp.sof) begin
  	      for (Integer i = 0; i < 4; i = i+1) begin
  		 if (tlp.be[(i+1)*4-1:i*4] == 4'hf) begin
  		    vec[i] = tlp.data[(i+1)*32-1:i*32];
  		 end
  	      end
  	      let count = tlpWordCount(tlp);
  	      completionMimo.enq(count, vec);
  	      completionTagMimo.enq(count, replicate(lastTag));
  	   end
  	   else if (hdr_3dw.format == MEM_WRITE_3DW_DATA && hdr_3dw.pkttype == COMPLETION) begin
  	      vec[0] = hdr_3dw.data;
  	      completionMimo.enq(1, vec);
  	      lastTag <= hdr_3dw.tag;
  	      completionTagMimo.enq(1, replicate(hdr_3dw.tag));
  	    end
  	endmethod
      endinterface: tlp_in
      interface Get tlp_out = toGet(tlpOutFifo);
  