anchor.diff:     let wdataCnx  <- mkConnection(toGet(wdataFifo), axiRootPortMemSlave.write_server.writeData);
      let doneCnx   <- mkConnection(axiRootPortMemSlave.write_server.writeDone, toPut(doneFifo));
   
  -   rule rl_rdata;
  +   rule rl_rdata if (!inSetup);
         let rdata <- toGet(rdataFifo).get();
         if (rdata.tag == 0)
   	 driverInd.readDone(truncate(rdata.data));
      endrule
   
  -   rule rl_writeDone;
  +   rule rl_writeDone if (!inSetup);
         let tag <- toGet(doneFifo).get();
         if (tag == 0)
   	 driverInd.writeDone();
  
positive.code:    let wdataCtlCnx  <- mkConnection(toGet(wdataFifoCtl), axiRootPortMemSlaveCtl.write_server.writeData);
     let doneCtlCnx   <- mkConnection(axiRootPortMemSlaveCtl.write_server.writeDone, toPut(doneFifoCtl));
  
     Reg#(Bool) inSetup <- mkReg(False);
  
     rule rl_rdata_ctl if (!inSetup);
        let rdata <- toGet(rdataFifoCtl).get();
        driverInd.readDone(extend(rdata.data));
  
negative.code:       method Action trace(Bool enabled);
  	 traceEnabled <= enabled;
        endmethod
        method Action read32(Bit#(32) addr) if (!inSetup);
  	 araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });
        endmethod
        method Action write32(Bit#(32) addr, Bit#(32) value) if (!inSetup);
  	 awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });
  	 wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});
        endmethod
        method Action read(Bit#(32) addr) if (!inSetup);
  	 araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });
        endmethod
        method Action write(Bit#(32) addr, Bit#(DataBusWidth) value) if (!inSetup);
  	 awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });
  	 wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});
        endmethod
  