anchor.diff:  import FIFOF::*;
   import SpecialFIFOs::*;
   import BRAM::*;
  +import Connectable::*;
   import AvalonCommon::*;
   
  -//export Cache(..) mkCache;
  +export Cache(..);
  +export mkCache;
   
   interface Cache#(numeric type address_width, numeric type inst_width, numeric type data_width);
       method Action clear();
  
positive.code:     endinterface
  endmodule
  
  /*
  module mkCache(Cache#(address_width,inst_width,data_width));
      SingleCache#(address_width,inst_width) instSCache <- mkSingleCache;
      SingleCache#(address_width,data_width) dataSCache <- mkSingleCache;
  
      method Action clear();
          instSCache.clear;
  
negative.code:     endmethod
  
      interface Client busClient;
          interface Get request = toGet(outReq);
          interface Put response;
              method Action put(Bit#(32) data);
                  case (pendingReq.first) matches
                      Instruction: instSCache.busClient.response.put(data);
                      Data:        dataSCache.busClient.response.put(data);
                      InstructionPrefetch:
                        action
                          let cacheLine = CacheLine{addr: pendingPrefetch.first,
                                                    data: tagged Valid data};
                          instSCache.prefetch.put(cacheLine);
                          pendingPrefetch.deq;
                        endaction
                  endcase
                  pendingReq.deq;
              endmethod
          endinterface
      endinterface
  
      interface Server instCache = instSCache.thisCache;
      interface Server dataCache = dataSCache.thisCache;
  endmodule
  
  