anchor.diff:  (* synthesize *)
   module mkProc(Proc#(DataSz));
       // Address map (some portions hard-coded in memory system
  -    // 0x0000_0000 - 0x4000_0000 : tightly coupled memory (not all used)
  +    // 0x0000_0000 - 0x2000_0000 : tightly coupled memory (not all used)
  +    // 0x2000_0000 - 0x3FFF_FFFF : rtc
       // 0x4000_0000 - 0xFFFF_FFFF : mmio
   
   `ifdef CONFIG_RV32
  
positive.code: 
  import Abstraction::*;
  import BasicMemorySystemBlocks::*;
  import BRAMTightlyCoupledMemory::*;
  import Core::*;
  import MemoryMappedCSRs::*;
  import RTC::*;
  
negative.code: 
      Wire#(Bool) extInterruptWire <- mkDWire(False);
  
      // Shared I/D Memory
      // the type of the imem port is Server#(Bit#(XLEN), Bit#(32))
      // the type of the dmem port is Server#(UncachedMemReq, UncachedMemResp)
      let sram <- mkBramIDMem;
  
      // This is the new way:
      FIFO#(UncachedMemReq) uncachedReqFIFO <- mkFIFO;
      FIFO#(UncachedMemResp) uncachedRespFIFO <- mkFIFO;
      let mmio_server = toGPServer(uncachedReqFIFO, uncachedRespFIFO);
      let mmio_client = toGPClient(uncachedReqFIFO, uncachedRespFIFO);
  
      // address decoding the dmem port of the sram for the RTC and MMIO
      function Bit#(2) whichServer(UncachedMemReq r);
          if (r.addr >= 'h4000_0000) return 2;
          else if (r.addr >= 'h2000_0000) return 1;
          else return 0;
      endfunction
      function Bool getsResponse(UncachedMemReq r);
          // currently all UncachedMemReq's get a response
          return True;
      endfunction
      MemoryBus#(UncachedMemReq, UncachedMemResp) memoryBus <- mkMemoryBus(whichServer, getsResponse, vec(sram.dmem, rtc.memifc, mmio_server));
  
      // mkUncachedConverter converts UncachedMemServer to Server#(RVDMemReq, RVDMemResp)
      let proc_dmem_ifc <- mkUncachedConverter(memoryBus.procIfc);
  
      Core core <- mkThreeStageCore(
                      transformReq(truncate, sram.imem), // truncate requests because they leave the processor as Bit#(64)
                      proc_dmem_ifc,
                      False, // inter-process interrupt
                      timer_interrupt, // timer interrupt
                      timer_value, // timer value
  