anchor.diff:  `endif
      endinterface
   
  -   interface Vector dmaReadClient = map(uncurry(traceReadClient(tracePipe,traceDataPipe)),
  -					zip(vec(DMA_TX, DMA_SG),
  -					    map(toMemReadClient(objId), vec(m_axi_mm2s, m_axi_sg))));
  -   interface Vector dmaWriteClient = map(uncurry(traceWriteClient(tracePipe,traceDataPipe)),
  -					 zip(vec(DMA_RX, DMA_SG),
  -					    map(toMemWriteClient(objId), vec(m_axi_s2mm, m_axi_sg))));
  +   interface Vector dmaReadClient = traceReadClients;
  +   interface Vector dmaWriteClient = traceWriteClients;
   endmodule
  
positive.code: import Probe::*;
  
  import ConnectalXilinxCells::*;
  import ConnectalConfig::*;
  import CtrlMux::*;
  import HostInterface::*;
  
negative.code:    PhysMemSlave#(20,32) bootRomMemSlave      <- mkPhysMemToBram(bootRom);
     PhysMemSlave#(21,32) memSlaveMux          <- mkPhysMemSlaveMux(vec(bootRomMemSlave, deviceSlaveMux));
  
     let memReadClients  <- mapM(mkMemReadClient(objId), vec(m_axi_mm2s, m_axi_sg));
     let memWriteClients <- mapM(mkMemWriteClient(objId), vec(m_axi_s2mm, m_axi_sg));
  
  `ifdef IncludeFlash
     PhysMemSlave#(26,16) bpiFlashSlave <- mkPhysMemToBram(bpiFlash.server);
  `endif
     FIFOF#(Bit#(32)) dfifo <- mkFIFOF();
     FIFOF#(Bit#(32)) flashdfifo <- mkFIFOF();
  
  