anchor.diff:  	 itersToFinish <= ic;
   	 itersToStart <= ic;
   	 mismatchCounts <= 0;
  -	 wordsRead <= 0;
  +	 bytesRead <= 0;
         endmethod
      endinterface
   endmodule
  
positive.code:    Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);
     Reg#(Bit#(32))  itersToFinish <- mkReg(0);
     Reg#(Bit#(32))   itersToStart <- mkReg(0);
     Reg#(Bit#(32))        wordsRead <- mkReg(0);
     Reg#(Bit#(32)) mismatchCounts <- mkReg(0);
     MemreadEngine#(DataBusWidth,1,1)        re <- mkMemreadEngine;
     FIFO#(Bit#(32)) checkDoneFifo <- mkFIFO();
  
negative.code:       // first pipeline stage
        if (re.dataPipes[0].notEmpty()) begin
  	 let v <- toGet(re.dataPipes[0]).get;
  	 let rval = bytesRead/4;
  	 let expectedV = {rval+1,rval};
  	 vReg <= v;
  	 vExpectedReg <= expectedV;
  	 validReg <= True;
  	 let next_bytesRead = bytesRead + fromInteger(valueOf(DataBusWidth))/8;
  	 let next_bytesToRead = bytesToRead - fromInteger(valueOf(DataBusWidth))/8;
  	 let last = (bytesToRead <= fromInteger(valueOf(DataBusWidth))/8);
  	 //$display("check next_bytesRead=%d next_bytesToRead=%d last=%d", next_bytesRead, next_bytesToRead, last);
  	 if (last) begin
  	    next_bytesRead = 0;
  	    next_bytesToRead = numBytes;
  	 end
  	 lastReg <= last;
  	 bytesRead <= next_bytesRead;
  	 bytesToRead <= next_bytesToRead;
        end
        else begin
  