anchor.diff:  	 784: return zeroExtend(pack(max_payload_bytes));
   	 785: return 0;
   	 786: return 0;
  -	 787: return pipeliningEnabledReg ? 1 : 0;
  +	 787: return 0;
   	 788: return axiEnabledReg ? 1 : 0;
   	 789: return tlpDataBramRdAddrReg;
   	 790: return msix_enabled ? 1 : 0;
  
positive.code: 	    780: tlpDataScratchpad[4] <= dword;
  	    781: tlpDataScratchpad[5] <= dword;
  
  	    787: pipeliningEnabledReg <= (dword != 0) ? True : False;
  	    788: axiEnabledReg <= (dword != 0) ? True : False;
  	    789: tlpDataBramRdAddrReg <= dword;
  	    792: tlpDataBramWrAddrReg <= dword;
  
negative.code: 
     interface Reg#(Bool) tlpTracing;
     interface Reg#(Bool) axiEnabled;
     interface Reg#(Bool) byteSwap;
     interface Reg#(Bool) use4dw;
     interface Reg#(Bit#(4)) numPortals;
  