anchor.diff:     Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);
      Reg#(Bit#(32))  itersToFinish <- mkReg(0);
      Reg#(Bit#(32))   itersToStart <- mkReg(0);
  -   Reg#(Bit#(32))        wordsRead <- mkReg(0);
  +   Reg#(Bit#(32))        bytesRead <- mkReg(0);
      Reg#(Bit#(32)) mismatchCounts <- mkReg(0);
      MemreadEngine#(DataBusWidth,1,1)        re <- mkMemreadEngine;
      FIFO#(Bit#(32)) checkDoneFifo <- mkFIFO();
  
positive.code: 	 itersToFinish <= ic;
  	 itersToStart <= ic;
  	 mismatchCounts <= 0;
  	 wordsRead <= 0;
        endmethod
     endinterface
  endmodule
  
negative.code: 	 let expectedV = vExpectedReg;
  	 let misMatch = v != expectedV;
  	 mismatchCounts <= mismatchCounts + (misMatch ? 1 : 0);
  	 //$display("Test: check new=%x numBytes=%x bytesRead=%x misMatch=%x read=%x expect=%x", new_bytesRead, numBytes, bytesRead, misMatch, v, expectedV);
  	 if (lastReg) begin
  	    checkDoneFifo.enq(mismatchCounts);
  	 end
  