anchor.diff:          delaye2.idatain(v);
       endmethod
       method Bit#(1)                align_busy();
  -        return this_align_busy_wire;
  +        return pack(qstate != QIdle);
       endmethod
       method Bit#(1)                aligned();
  -        return this_aligned_reg;
  +        return unaligned_reg;
       endmethod
       method Bit#(3)                samplein();
           return ctrl_sample;
  -    endmethod
  -    method Action                 delay_wren(Bit#(1) v);
  -        bvi_delay_wren_wire <= v;
       endmethod
       method Action                 fifo_wren(Bit#(1) v);
           fifo_wren_sync.send(v);
  
positive.code:     SyncBitIfc#(Bit#(1)) fifo_reset_sync <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) reset_hack <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
      SyncBitIfc#(Bit#(1)) samplein_reset_null <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  
      SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBit(serdes_clock, serdes_reset, serdes_clock);
      SyncBitIfc#(Bit#(10)) iserdes_data <-  mkSyncBits(0, serdes_clock, serdes_reset, defaultClock, defaultReset);
  
negative.code:     endrule
  
      rule sendup_imageon_clock;
         Bit#(1) unalignedw = 1;
         Bit#(1) alignbusyw = 0;
         Bit#(1) emptyw = 0;
         Bit#(3) samplein = 0;
         Bit#(50) rawdataw = 0;
         for (Bit#(8) i = 0; i < 5; i = i+1) begin
  	  unalignedw = unalignedw | serdes_v[i].aligned();
  	  alignbusyw = alignbusyw | serdes_v[i].align_busy();
  	  emptyw = emptyw | serdes_v[i].empty();
            samplein = samplein | serdes_v[i].samplein();
  	  rawdataw[(i+1)*10-1: i*10] = serdes_v[i].dataout();
         end
         serdes_align_busy_temp <= alignbusyw;
         serdes_aligned_temp <= unalignedw;
         //bittest_wire <= pack(samplein == 3'b110);
         empty_wire <= emptyw;
         raw_data_wire <= rawdataw;
      endrule
  