anchor.diff:  		      endseq;
      FSM trafficFSM <- mkFSM(trafficStmt);
         
  +   FIFO#(DmaError) dmaErrorFifo <- mkFIFO();
  +   rule dmaError;
  +      let error <- toGet(dmaErrorFifo).get();
  +      dmaIndication.dmaError(extend(pack(error.errorType)), error.pref, 0, 0);
  +   endrule
  +
      interface DmaConfig request;
         method Action getStateDbg(ChannelType rc);
   	 if (rc == Read)
  
positive.code:       endmethod
        method Action sglist(Bit#(32) pref, Bit#(64) addr, Bit#(32) len);
  	 if (bad_pointer(pref))
  	    dmaIndication.dmaError(extend(pack(DmaErrorBadPointer3)), pref, 0, 0);
  `ifdef BSIM
  `ifndef PCIE
  	 let va <- pareff(pref, len);
  
negative.code: 		      endseq;
     FSM trafficFSM <- mkFSM(trafficStmt);
  
     FIFO#(DmaError) dmaErrorFifo <- mkFIFO();
     rule dmaError;
        let error <- toGet(dmaErrorFifo).get();
        dmaIndication.dmaError(extend(pack(error.errorType)), error.pref, 0, 0);
     endrule
  
     interface DmaConfig request;
        method Action getStateDbg(ChannelType rc);
  	 if (rc == Write)
  