anchor.diff:      endinterface: out
   
       method Bit#(1)get_framesync();
  -        return framestart_wire;
  +        return framestart_reg;
       endmethod
   endmodule
   
  
positive.code: 
      rule update_debug;
          let dval = diff;
          dval = {diff[29:0], framestart_wire, fs2};
          if (diff[17] == 1)
              begin
              debugind_value <= diff;
  
negative.code: 
      Reg#(State)    hstate <- mkReg(Idle);
      Reg#(State)    vstate <- mkReg(Idle);
      Reg#(Bit#(1))  active_video_reg <- mkReg(0);
      Reg#(Bit#(16)) vsync_count <- mkReg(0);
      Reg#(Bit#(16)) hsync_count <- mkReg(0);
      Reg#(Bit#(10)) videodata <- mkReg(0);
      Reg#(Bit#(1))  framestart_delay_reg <- mkReg(0, clocked_by imageon_clock, reset_by imageon_reset);
      Reg#(Bit#(1))  framestart_new <- mkReg(0);
      
      rule start_fsm if (framestart_new == 1);
          vsync_count <= 0;
  