anchor.diff:     } DmaError deriving (Bits);
   
   // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  -module mkMMU#(Integer iid, Bool bsimMMap, MMUIndication mmuIndication)(MMU#(addrWidth))
  +module mkMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
      provisos(Log#(MaxNumSGLists, listIdxSize),
   	    Add#(listIdxSize,8, entryIdxSize),
   	    Add#(a__,addrWidth,MemOffsetSize));
  
positive.code:    Bit#(MemOffsetSize) off;
  } ReqTup deriving (Eq,Bits,FShow);
  
  `ifdef BSIM
  `ifndef PCIE
  import "BDPI" function ActionValue#(Bit#(32)) pareff_init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);
  import "BDPI" function ActionValue#(Bit#(32)) pareff_initfd(Bit#(32) id, Bit#(32) fd);
  `endif
  `endif
  
  interface MMU#(numeric type addrWidth);
     interface MMURequest request;
  
negative.code: 	    $display("mkMMU::sglist ERROR");
  	    $finish();
  	 end
  	 if(hostMapped)
  	    let va <- pareff.init({0,pointer[31:16]}, {0,pointer[15:0]}, len);
           Bit#(IndexWidth) ind = truncate(pointerIndex);
  	 portsel(pages, 0).request.put(BRAMRequest{write:True, responseOnWrite:False,
               address:{truncate(pointer),ind}, datain:truncate(addr)});
  