anchor.diff:  import AxiBits::*;
   
   
  -// The name of this interface is a prefix "Par_" plus the common prefix of the signals "txo"
  +// The name of this interface is a prefix "Par_" plus the common 
  +// prefix of the signals "tx"
   // Hopefully this is what importbvi.py would do
   (* always_ready, always_enabled *)
  -interface Par_txo;
  +interface Par_tx;
      method Action data_p(Bit#(8) v);
      method Action data_n(Bit#(8) v);
      method Action frame_p(Bit#(1) v);
      method Action frame_n(Bit#(1) v);
      method Action lclk_p(Bit#(1) v);
      method Action lclk_n(Bit#(1) v);
  -endinterface
  -
  -(* always_ready, always_enabled *)
  -interface Par_txi; 
      method Bit#(1) wr_wait_p();
      method Bit#(1) wr_wait_n();
      method Bit#(1) rd_wait_p();
  
positive.code:       method rxi_frame_n frame_n();
        method rxi_lclk_p lclk_p();
        method rxi_lclk_n lclk_n();
        method cclk_p(rxi_cclk_p) enable((*inhigh*) EN_rxi_cclk_p);
        method cclk_n(rxi_cclk_n) enable((*inhigh*) EN_rxi_cclk_n);
     endinterface
   
     interface Par_rxo rxo;
  
negative.code:       method reset_chip reset_chip();
        method reset_fpga reset_fpga();
        method csysreq(csysreq) enable((*inhigh*) EN_csysreq);
        method cclk_p(rxi_cclk_p) enable((*inhigh*) EN_rxi_cclk_p);
        method cclk_n(rxi_cclk_n) enable((*inhigh*) EN_rxi_cclk_n);
     endinterface
     
     interface Par_txo txo;
  