anchor.diff:  
   import Abstraction::*;
   import BasicMemorySystemBlocks::*;
  -import BRAMTightlyCoupledMemory::*;
  +import BramIDMem::*;
   import Core::*;
   import MemoryMappedCSRs::*;
   import RTC::*;
  
positive.code: (* synthesize *)
  module mkProc(Proc#(DataSz));
      // Address map (some portions hard-coded in memory system
      // 0x0000_0000 - 0x4000_0000 : tightly coupled memory (not all used)
      // 0x4000_0000 - 0xFFFF_FFFF : mmio
  
  `ifdef CONFIG_RV32
  
negative.code:         endinterface
      endinterface
  
      interface UncachedMemClient mmio = mmio_client;
  
      interface GenericMemServer extmem;
          interface Put request;
              method Action put(GenericMemReq#(XLEN) x);
                  if (x.byteen != '1) begin
                      $fdisplay(stderr, "[ERROR] mkProc.extmem : expecting byteen to be all 1's, but byteen = ", fshow(x.byteen));
                  end
                  memoryBus.extIfc.request.put(UncachedMemReq {
                          write:  x.write,
                          size:   (valueOf(XLEN) == 64 ? D : W),
                          addr:   x.addr,
                          data:   x.data
                      } );
              endmethod
          endinterface
          interface Get response;
              method ActionValue#(GenericMemResp#(XLEN)) get();
                  let x <- memoryBus.extIfc.response.get;
                  return GenericMemResp {
                          write: x.write,
                          data:  x.data
                      };
              endmethod
          endinterface
      endinterface
  
      // Interrupts
      method Action triggerExternalInterrupt;
          extInterruptWire <= True;
      endmethod
  endmodule
  