anchor.diff:     pcieportals[0] = simpleIndicationProxy.portalIfc;
      pcieportals[1] = simpleRequestWrapper.portalIfc;
      PhysMemSlave#(32,32) pcie_ctrl_mux <- mkSlaveMux(pcieportals, clocked_by host.portalClock, reset_by host.portalReset);
  +   // manually connect the PCIe host PhysMemMaster to the pcie_ctrl_mux PhysMemSlave
      mkConnection(host.tpciehost.master, pcie_ctrl_mux, clocked_by host.portalClock, reset_by host.portalReset);
   
  -   Reg#(Bit#(1)) resetSeenReg <- mkReg(0);
  +   // Construct the ZynqPcie interface
      ZynqPcie zpcie = (interface ZynqPcie;
   		     method Action pcie_sys_clk(Bit#(1) p, Bit#(1) n);
  +
  +		        // This is a bit of sleight of hand. We depend
  +		        // on the way the bluespec compiler generates
  +		        // verilog for the following method invocation
  +		        // to connect the input clock signals via the
  +		        // B2C to the 100Mhz pcie system clock input
  +		        // of the PcieHost.
   			b2c_pcie_sys_clk_p.inputclock(p);
   			b2c_pcie_sys_clk_n.inputclock(n);
   		     endmethod
   		     method Action sys_clk(Bit#(1) p, Bit#(1) n);
  +			// same for the 200MHz system clock
   			b2c_sys_clk_p.inputclock(p);
   			b2c_sys_clk_n.inputclock(n);
   		     endmethod
  
positive.code:    interface Clock deleteme_unused_clock100mhz;
  endinterface
  
  (* synthesize *)
  module mkPcieHostTopSynth#(Clock pcie_sys_clk_p, Clock pcie_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pcie_sys_reset_n)(PcieHostTop);
     (*hide*) let host <- mkPcieHostTop(pcie_sys_clk_p, pcie_sys_clk_n, sys_clk_p, sys_clk_n, pcie_sys_reset_n);
     return host;
  endmodule
  
  module mkConnectalTop(ConnectalTop#(PhysAddrWidth,64,ZynqPcie,0));
  
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  
     B2C1 b2c_pcie_sys_clk_p <- mkB2C1();
     B2C1 b2c_pcie_sys_clk_n <- mkB2C1();
     B2C b2c_pcie_sys_reset_n <- mkB2C();
     B2C1 b2c_sys_clk_p <- mkB2C1();
     B2C1 b2c_sys_clk_n <- mkB2C1();
  
     PcieHostTop host <- mkPcieHostTopSynth(b2c_pcie_sys_clk_p.c, b2c_pcie_sys_clk_n.c, b2c_sys_clk_p.c, b2c_sys_clk_n.c, b2c_pcie_sys_reset_n.r);
  
     // instantiate user portals
     SyncBitIfc#(Bit#(1)) resetBit <- mkSyncBit(b2c_pcie_sys_reset_n.c, b2c_pcie_sys_reset_n.r, defaultClock);
     SyncBitIfc#(Bit#(1)) resetSeenBit <- mkSyncBit(b2c_pcie_sys_reset_n.c, b2c_pcie_sys_reset_n.r, defaultClock);
     SyncBitIfc#(Bit#(1)) linkUpBit <- mkSyncBit(host.portalClock, host.portalReset, defaultClock);
     ZynqPcieTestIndicationProxy zynqPcieTestIndicationProxy <- mkZynqPcieTestIndicationProxy(ZynqPcieTestIndication);
     ZynqPcieTest zynqPcieTest <- mkZynqPcieTest(linkUpBit, resetBit, resetSeenBit, zynqPcieTestIndicationProxy.ifc);
     ZynqPcieTestRequestWrapper zynqPcieTestRequestWrapper <- mkZynqPcieTestRequestWrapper(ZynqPcieTestRequest,zynqPcieTest.request);
  
     mkConnectionWithClocks(zynqPcieTest.traceBramClient, host.tpciehost.traceBramServer, defaultClock, defaultReset, host.portalClock, host.portalReset);
  
     Vector#(2,StdPortal) portals;
     portals[0] = zynqPcieTestIndicationProxy.portalIfc;
     portals[1] = zynqPcieTestRequestWrapper.portalIfc;
     let ctrl_mux <- mkSlaveMux(portals);
     
     Reg#(Bit#(8)) ledsValue <- mkReg(5);
     Reg#(Bit#(32)) remainingDuration <- mkReg(100000000);
  
     rule updateLeds;
  
negative.code:       remainingDuration <= duration;
     endrule
  
     //
     // Instantiate Simple portals as the test case connected to the x86 host via PCIe
     //
     SimpleProxy simpleIndicationProxy <- mkSimpleProxy(SimpleIndication, clocked_by host.portalClock, reset_by host.portalReset);
     Simple simpleRequest <- mkSimple(simpleIndicationProxy.ifc, clocked_by host.portalClock, reset_by host.portalReset);
     SimpleWrapper simpleRequestWrapper <- mkSimpleWrapper(SimpleRequest,simpleRequest, clocked_by host.portalClock, reset_by host.portalReset);
  