anchor.diff:  
   typedef enum { DIdle, DValid, DLow} DState deriving (Bits,Eq);
   typedef enum { HIdle, HHigh, HLow} HState deriving (Bits,Eq);
  -
  +typedef enum { QIdle, QTrain, QOn, QOff} QState deriving (Bits,Eq);
   module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
       Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden, TrainRotate trainrot)(IserdesDatadeser);
   
  
positive.code:         serbvi.train8(trainrot[8]);
          serbvi.train9(trainrot[9]);
      endrule
  
      rule reset_clock_rule;
          bvi_resets_reg.send(bvi_reset_reg);
  
negative.code:             fwsync = bvi_fifo_wren_wire;
          fifo_wren_sync.send(fwsync);
          iodelay_reset_inc_ce <= sync_reset_inc_ce;
      endrule
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
  