anchor.diff:           tlp = mvec[i].tlp;
         end
         mkConnection((interface Server;
  -                       interface response = dispatcher[tlpCompleterRequest].out[i];
  -                       interface request = arbiter[tlpCompleterRequest].in[i];
  +                       interface response = dispatcher.out[i];
  +                       interface request = arbiter.in[i];
                       endinterface), tlp);
      end
   
  -   Vector#(NumberOfTlpIntfs, PcieTracer) traceif <- replicateM(mkPcieTracer());
  -   mkConnection(traceif[tlpCompleterRequest].bus, (interface Client;
  -                                    interface request = arbiter[tlpCompleterRequest].outToBus;
  -                                    interface response = dispatcher[tlpCompleterRequest].inFromBus;
  -                                 endinterface));
  -   mkConnection(traceif[tlpRequesterRequest].bus, (interface Client;
  -                                    interface request = arbiter[tlpRequesterRequest].outToBus;
  -                                    interface response = dispatcher[tlpRequesterRequest].inFromBus;
  -                                 endinterface));
  +   PcieTracer traceif <- mkPcieTracer();
  +   let splitter = (interface Client;
  +                      interface request = arbiter.outToBus;
  +                      interface response = dispatcher.inFromBus;
  +                  endinterface);
  +`ifdef TRACE_PORTAL
  +   mkConnection(traceif[tlpCompleterRequest].bus, splitter);
  +`else
  +   mkConnection(traceif.bus, sEngine.tlp);
  +`endif
   
      PcieControlAndStatusRegs csr <- mkPcieControlAndStatusRegs();
      mkConnection(mvec[portConfig].master, csr.memSlave);
   
  +   mkConnection(csr.traceClient, traceif.traceServer);
      interface msixEntry = csr.msixEntry;
      interface master = mvec[portPortal].master;
  -   interface slave = slavearr;
  +   interface slave = vec(sEngine.slave);
      interface interruptRequest = intr.interruptRequest;
  -   interface pcic = traceif[tlpCompleterRequest].pci;
  -   interface pcir = traceif[tlpRequesterRequest].pci;
  +`ifdef TRACE_PORTAL
  +   interface pcic = traceif.pci;
  +   interface pcir = sEngine.tlp;
  +`else
  +   interface pcic = splitter;
  +   interface pcir = traceif.pci;
  +`endif
   endmodule: mkPcieHost
   `else //NOT PCIE3
   // ======================================================
  
positive.code: `ifdef PCIE3
  Integer tlpCompleterRequest = 0;
  Integer tlpRequesterRequest = 1;
  typedef 2   NumberOfTlpIntfs;
  
  (* synthesize *)
  module mkPcieHost#(PciId my_pciId)(PcieHost#(DataBusWidth, NumberOfMasters));
     Vector#(NumberOfTlpIntfs, TLPDispatcher) dispatcher <- replicateM(mkTLPDispatcher);
     Vector#(NumberOfTlpIntfs, TLPArbiter) arbiter <- replicateM(mkTLPArbiter);
     Vector#(NumberOfMasters, MemToPcie#(DataBusWidth)) sEngine <- replicateM(mkMemToPcieSynth(my_pciId));
     Vector#(NumberOfMasters,PhysMemSlave#(PciePhysAddrWidth,DataBusWidth)) slavearr;
     MemInterrupt intr <- mkMemInterrupt(my_pciId);
     Vector#(PortMax, PcieToMem) mvec;
     for (Integer i=0; i < valueOf(NumberOfMasters); i=i+1) begin
        let tlp;
        tlp = sEngine[i].tlp;
        slavearr[i]  = sEngine[i].slave;
        mkConnection((interface Server;
                         interface response = dispatcher[tlpRequesterRequest].out[i];
                         interface request = arbiter[tlpRequesterRequest].in[i];
                      endinterface), tlp);
     end
     for (Integer i=0; i < valueOf(PortMax) - 1; i=i+1) begin
        let tlp;
        if (i == portInterrupt)
  
negative.code: // SOFTWARE.
  
  import Vector            :: *;
  import BuildVector       :: *;
  import Clocks            :: *;
  import GetPut            :: *;
  import FIFO              :: *;
  