anchor.diff:        AvalonStRx#(16) beat;
         beat.sop = pcie_ep.rx_st.sop;
         beat.eop = pcie_ep.rx_st.eop;
  -      beat.be  = pcie_ep.rx_specific.be;
  +      beat.be  = pcie_ep.rx_st.be;
         // bar[7] is reserved for endpoints.
  -      beat.hit = pcie_ep.rx_specific.bar[6:0];
  +      beat.hit = pcie_ep.rx_st.bar[6:0];
   
         // 128-bit interface
         // when rx_st_empty==1, rx_st_data[63:0] are valid
         if (pcie_ep.rx_st.empty[0] == 1 && pcie_ep.rx_st.eop == 1) begin
  -         if (pcie_ep.rx_specific.be == 16'h000f) begin
  +         if (pcie_ep.rx_st.be == 16'h000f) begin
               beat.data = {96'h0, pcie_ep.rx_st.data[31:0]};
            end
  -         else if (pcie_ep.rx_specific.be == 16'h00ff) begin
  +         else if (pcie_ep.rx_st.be == 16'h00ff) begin
               beat.data = {64'h0, pcie_ep.rx_st.data[63:0]};
            end
            else begin
  
positive.code:    method PciId device = deviceReg;
  
     interface PciewrapUser user;
        method Reset reset_out;
           return hip_rs.app_rstn;
        endmethod
        method Clock clk_out();
           return core_clk;
        endmethod
        method Bit#(1) lnk_up();
           return pcie_ep.hip_rst.serdes_pll_locked;
        endmethod
        method Bit#(1) app_rdy();
           return pcie_ep.hip_rst.pld_clk_inuse;
        endmethod
     endinterface
  
  
negative.code:    Bit#(TMul#(bytes, 8)) data;
  } AvalonStTx#(type bytes) deriving (Bits, Eq);
  
  typedef 8 PcieLanes;
  typedef 4 NumLeds;
  
  //(* synthesize *)
  module mkPcieEndpointS5#(Clock clk_100MHz, Clock clk_50MHz, Reset perst_n)(PcieEndpointS5#(PcieLanes));
  