anchor.diff:  
   module mkAxi3SlaveGather#(AxiSlaveBits#(addrWidth, dataWidth, tagWidth,
       extraType) axiWires)(AxiSlaveCommon#(addrWidth, dataWidth,tagWidth,extraType));
  -    AxiSlaveWires#(addrWidth,dataWidth,tagWidth) vtopsw <- mkAxiSlaveWires;
  +    Wire#(Bit#(addrWidth)) araddr <- mkDWire(0);
  +    Wire#(Bit#(2)) arburst <- mkDWire(0);
  +    Wire#(Bit#(4)) arcache <- mkDWire(0);
  +    Wire#(Bit#(tagWidth)) arid <- mkDWire(0);
  +    Wire#(Bit#(4)) arlen <- mkDWire(0);
  +    Wire#(Bit#(2)) arlock <- mkDWire(0);
  +    Wire#(Bit#(3)) arprot <- mkDWire(0);
  +    Wire#(Bit#(4)) arqos <- mkDWire(0);
  +    Wire#(Bit#(2)) arsize <- mkDWire(0);
  +    Wire#(Bit#(1)) arvalid <- mkDWire(0);
  +
  +    Wire#(Bit#(addrWidth)) awaddr <- mkDWire(0);
  +    Wire#(Bit#(2)) awburst <- mkDWire(0);
  +    Wire#(Bit#(4)) awcache <- mkDWire(0);
  +    Wire#(Bit#(tagWidth)) awid <- mkDWire(0);
  +    Wire#(Bit#(4)) awlen <- mkDWire(0);
  +    Wire#(Bit#(2)) awlock <- mkDWire(0);
  +    Wire#(Bit#(3)) awprot <- mkDWire(0);
  +    Wire#(Bit#(4)) awqos <- mkDWire(0);
  +    Wire#(Bit#(2)) awsize <- mkDWire(0);
  +    Wire#(Bit#(1)) awvalid <- mkDWire(0);
  +
  +    Wire#(Bit#(1)) rready <- mkDWire(0);
  +    Wire#(Bit#(tagWidth)) wid <- mkDWire(0);
  +    Wire#(Bit#(TDiv#(dataWidth,8))) wstrb <- mkDWire(0);
  +    Wire#(Bit#(dataWidth)) wdata <- mkDWire(0);
  +    Wire#(Bit#(1)) wlast <- mkDWire(0);
  +    Wire#(Bit#(1)) wvalid <- mkDWire(0);
  +    Wire#(Bit#(1)) bready <- mkDWire(0);
  +
       rule handshake1;
  -          axiWires.araddr(vtopsw.araddr);
  -          axiWires.arburst(vtopsw.arburst);
  -          axiWires.arcache(vtopsw.arcache);
  -          axiWires.arid(vtopsw.arid);
  -          axiWires.arlen(vtopsw.arlen);
  -          axiWires.arlock(vtopsw.arlock);
  -          axiWires.arprot(vtopsw.arprot);
  -          axiWires.arqos(vtopsw.arqos);
  -          axiWires.arsize(vtopsw.arsize);
  -          axiWires.arvalid(vtopsw.arvalid);
  +          axiWires.araddr(araddr);
  +          axiWires.arburst(arburst);
  +          axiWires.arcache(arcache);
  +          axiWires.arid(arid);
  +          axiWires.arlen(arlen);
  +          axiWires.arlock(arlock);
  +          axiWires.arprot(arprot);
  +          axiWires.arqos(arqos);
  +          axiWires.arsize(arsize);
  +          axiWires.arvalid(arvalid);
       endrule
       rule handshake2;
  -          axiWires.awaddr(vtopsw.awaddr);
  -          axiWires.awburst(vtopsw.awburst);
  -          axiWires.awcache(vtopsw.awcache);
  -          axiWires.awid(vtopsw.awid);
  -          axiWires.awlen(vtopsw.awlen);
  -          axiWires.awlock(vtopsw.awlock);
  -          axiWires.awprot(vtopsw.awprot);
  -          axiWires.awqos(vtopsw.awqos);
  -          axiWires.awsize(vtopsw.awsize);
  -          axiWires.awvalid(vtopsw.awvalid);
  +          axiWires.awaddr(awaddr);
  +          axiWires.awburst(awburst);
  +          axiWires.awcache(awcache);
  +          axiWires.awid(awid);
  +          axiWires.awlen(awlen);
  +          axiWires.awlock(awlock);
  +          axiWires.awprot(awprot);
  +          axiWires.awqos(awqos);
  +          axiWires.awsize(awsize);
  +          axiWires.awvalid(awvalid);
       endrule
       rule handshake3;
  -         axiWires.rready(vtopsw.rready);
  +         axiWires.rready(rready);
       endrule
       rule handshake4;
  -          axiWires.wid(vtopsw.wid);
  -          axiWires.wstrb(vtopsw.wstrb);
  -          axiWires.wdata(vtopsw.wdata);
  -          axiWires.wlast(vtopsw.wlast);
  -          axiWires.wvalid(vtopsw.wvalid);
  +          axiWires.wid(wid);
  +          axiWires.wstrb(wstrb);
  +          axiWires.wdata(wdata);
  +          axiWires.wlast(wlast);
  +          axiWires.wvalid(wvalid);
       endrule
       rule handshake5;
  -         axiWires.bready(vtopsw.bready);
  +         axiWires.bready(bready);
       endrule
       interface Axi3Slave server;
       interface Put req_ar;
           method Action put(Axi3ReadRequest#(addrWidth,tagWidth) v) if (axiWires.arready() != 0);
  -           vtopsw.araddr <= v.address;
  -           vtopsw.arburst <= v.burst;
  -           vtopsw.arcache <= v.cache;
  -           vtopsw.arid <= v.id;
  -           vtopsw.arlen <= v.len;
  -           vtopsw.arlock <= v.lock;
  -           vtopsw.arprot <= v.prot;
  -           vtopsw.arqos <= v.qos;
  -           vtopsw.arsize <= v.size[1:0];
  -
  -           vtopsw.arvalid <= 1;
  +           araddr <= v.address;
  +           arburst <= v.burst;
  +           arcache <= v.cache;
  +           arid <= v.id;
  +           arlen <= v.len;
  +           arlock <= v.lock;
  +           arprot <= v.prot;
  +           arqos <= v.qos;
  +           arsize <= v.size[1:0];
  +
  +           arvalid <= 1;
           endmethod
       endinterface
       interface Put req_aw;
           method Action put(Axi3WriteRequest#(addrWidth,tagWidth) v) if (axiWires.awready() != 0);
  -           vtopsw.awaddr <= v.address;
  -           vtopsw.awburst <= v.burst;
  -           vtopsw.awcache <= v.cache;
  -           vtopsw.awid <= v.id;
  -           vtopsw.awlen <= v.len;
  -           vtopsw.awlock <= v.lock;
  -           vtopsw.awprot <= v.prot;
  -           vtopsw.awqos <= v.qos;
  -           vtopsw.awsize <= v.size[1:0];
  -
  -           vtopsw.awvalid <= 1;
  +           awaddr <= v.address;
  +           awburst <= v.burst;
  +           awcache <= v.cache;
  +           awid <= v.id;
  +           awlen <= v.len;
  +           awlock <= v.lock;
  +           awprot <= v.prot;
  +           awqos <= v.qos;
  +           awsize <= v.size[1:0];
  +
  +           awvalid <= 1;
           endmethod
       endinterface
       interface Put resp_write;
           method Action put(Axi3WriteData#(dataWidth,tagWidth) v) if (axiWires.wready() != 0);
  -           vtopsw.wid <= v.id;
  -           vtopsw.wstrb <= v.byteEnable;
  -           vtopsw.wdata <= v.data;
  -           vtopsw.wlast <= v.last;
  -
  -           vtopsw.wvalid <= 1;
  +           wid <= v.id;
  +           wstrb <= v.byteEnable;
  +           wdata <= v.data;
  +           wlast <= v.last;
  +
  +           wvalid <= 1;
           endmethod
       endinterface
       interface Get resp_read;
  
positive.code:                 v.qos = axiWires.awqos();
                  v.size = {0, axiWires.awsize()};
  
                  vtopmw.awready <= 1;
                  return v;
             endmethod
          endinterface
          interface Put resp_read;
              method Action put(Axi3ReadResponse#(dataWidth, tagWidth) v) if (axiWires.rready() != 0);
                  vtopmw.rid <= v.id;
                  vtopmw.rresp <= v.resp;
                  vtopmw.rdata <= v.data;
                  vtopmw.rlast <= v.last;
                  vtopmw.rvalid <= 1;
              endmethod
          endinterface
          interface Get resp_write;
  
negative.code:             v.id = axiWires.bid();
              v.resp = axiWires.bresp();
  
              bready <= 1;
              return v;
          endmethod
       endinterface
  