anchor.diff:  	 burstLen = drq.req_burstLen >> beat_shift;
   	 last = drq.last;
   	 dynamicAssert(last == (burstLen==1), "Last incorrect");
  -	 //$display("mkMemReadInternal::burstLen=%d dreqFifo.first.last=%d last=%d\n", burstLen, dreqFifo.first.last, last);
         end
         Bit#(TLog#(numTags)) tt = truncate(response_tag);
  -      readBufferBram.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last}, address:{tt,truncate(burstLen)}});
  +      clientData.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last}, address:{tt,truncate(burstLen)}});
         if (last) begin
   	 tag_gen.returnTag(truncate(response_tag));
         end
         last_readData <= cycle_cnt;
  -      if (debug) $display("mkMemReadInternal::read_data cyclediff %d", cycle_cnt-last_readData);
  +      if (verbose) $display("mkMemReadInternal::read_data cyclediff %d", cycle_cnt-last_readData);
         burstReg <= burstLen-1;
         firstReg <= burstLen-1 == 0;
         lastReg  <= burstLen-1 == 1;
  
positive.code: 
     rule complete_burst0;
        let tag <- tag_gen.complete;
        dreqBram.portB.request.put(BRAMRequest{write:False, address:tag, datain: ?, responseOnWrite: ?});
        compFifo1.enq(tag);
        if(debug) $display("mkMemReadInternal::complete_burst0 %h", tag);
     endrule
     
     rule complete_burst1a if (compCountReg==0);
        let drq <- dreqBram.portB.response.get;
        let req_burstLen = drq.req_burstLen;
        let client = drq.client;
        let cnt = req_burstLen >> beat_shift;
        let tag <- toGet(compFifo1).get;
        if(killv[drq.req_tag[5:4]] == False) begin
  	 compFifo0.enq(extend(client));
  	 readBufferBram.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        end
        compCountReg <= cnt-1;
        compTagReg <= tag;
        compClientReg <= client;
        compTileReg <= drq.req_tag[5:4];
        if(debug) $display("mkMemReadInternal::complete_burst1a %h", client);
     endrule
  
     rule complete_burst1b if (compCountReg > 0);
        let cnt = compCountReg;
        let tag = compTagReg;
        let cli = compClientReg;
        if(killv[compTileReg] == False) begin
  	 compFifo0.enq(extend(cli));
  	 readBufferBram.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        end
        compCountReg <= cnt-1;
        if(debug) $display("mkMemReadInternal::complete_burst1b count %h", compCountReg);
     endrule
           
     rule checkMmuResp;
        let req = lreqFifo.first.req;
        let client = lreqFifo.first.client;
        let physAddr <- mmus[req.sglId[31:16]].response.get;
        let rename_tag <- tag_gen.getTag;
        lreqFifo.deq();
        reqFifo.enq(RRec{req:req, pa:physAddr, client:client, rename_tag:extend(rename_tag)});
        if (debug) $display("mkMemReadInternal::checkMmuResp: client=%d, rename_tag=%d", client,rename_tag);
        if (debug) $display("mkMemReadInternal::mmuResp %d %d", client, cycle_cnt-last_mmuResp);
        last_mmuResp <= cycle_cnt;
     endrule
     
     rule read_data;
        let response <- toGet(readDataPipelineFifo).get();
        Bit#(MemTagSize) response_tag = response.tag;
        let drq <- dreqBram.portA.response.get;
        let otag = drq.req_tag;
        let burstLen = burstReg;
        let first =    firstReg;
  
negative.code:    interface PhysMemWriteClient client;
        interface Get writeReq;
  	 method ActionValue#(PhysMemRequest#(addrWidth)) get();
  	    let req = serverRequest.first.req;
  	    let physAddr = serverRequest.first.pa;
  	    let client = serverRequest.first.client;
  	    let rename_tag = serverRequest.first.rename_tag;
  	    serverRequest.deq;
  	    serverProcessing.enq(DRec{req_tag:req.tag, req_burstLen: req.burstLen, client:client, rename_tag:rename_tag, last: (req.burstLen == fromInteger(valueOf(dataWidthBytes))) });
  	    //$display("mkMemWriteInternal::writeReq: client=%d, rename_tag=%d", client,rename_tag);
  	    return PhysMemRequest{addr:physAddr, burstLen:req.burstLen, tag:extend(rename_tag)};
  	 endmethod
  