anchor.diff:     Reset derivedReset <- mkAsyncReset(4, pcieReset250, derivedClock);
      Reset user_reset <- mkAsyncReset(2, pcie_ep.user_reset, pcie_ep.user_clk);
   
  +   // FIFOS
      FIFOF#(AxiStCq) fAxiCq <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);
      FIFOF#(AxiStRc) fAxiRc <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);
   
  
positive.code:    Reg#(Bool)    rq_even    <- mkRegU(clocked_by pcie_ep.user_clk, reset_by user_reset_n);
     Reg#(DWCount) rq_dwcount <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);
     Reg#(AxiStRq) rq_rq <- mkRegU(clocked_by pcie_ep.user_clk, reset_by user_reset_n);
     rule get_rq_tlps;
        let tlp <- toGet(frq).get;
        frq_tlps.enq(tlp);
     endrule
  
negative.code: import Real              ::*;
  import XilinxVirtex7PCIE ::*;
  import BUtils            ::*;
  import Probe             ::*;
  
  import ConnectalClocks   ::*;
  import ConnectalXilinxCells   ::*;
  