anchor.diff:         endmethod
      endinterface
      interface pins = top.pins;
  -   interface unused_clock = mainclock.c;
  -   interface unused_reset = mainclock.r;
  +   interface unused_clock = mainclock;
  +   interface unused_reset = mainreset;
   endmodule
   
   module mkZynqTop(ZynqTop#(Empty));
  
positive.code: typedef (function Module#(PortalTop#(32, 64, ipins)) mkpt()) MkPortalTop#(type ipins);
  
  module [Module] mkZynqTopFromPortal#(MkPortalTop#(ipins) constructor)(ZynqTop#(ipins));
     B2C mainclock <- mkB2C();
     PS7 ps7 <- mkPS7(mainclock.c, mainclock.r, clocked_by mainclock.c, reset_by mainclock.r);
     let top <- constructor(clocked_by mainclock.c, reset_by mainclock.r);
     Reg#(Bit#(8)) addrReg <- mkReg(9, clocked_by mainclock.c, reset_by mainclock.r);
     BscanBram#(Bit#(8), Bit#(64)) bscanBram <- mkBscanBram(1, addrReg, clocked_by mainclock.c, reset_by mainclock.r);
     BRAM_Configure bramCfg = defaultValue;
     bramCfg.memorySize = 256;
     bramCfg.latency = 1;
     BRAM2Port#(Bit#(8), Bit#(64)) traceBram <- mkSyncBRAM2Server(bramCfg, mainclock.c, mainclock.r,
  								bscanBram.jtagClock, bscanBram.jtagReset);
     mkConnection(bscanBram.bramClient, traceBram.portB);
  
     ReadOnly#(Bit#(4)) debugReg <- mkNullCrossingWire(mainclock.c, bscanBram.debug());
     
     let interrupt_bit = top.interrupt ? 1'b1 : 1'b0;
     
  
negative.code:        ps7.interrupt(interrupt_bit);
     endrule
  
     interface zynq = ps7.pins;
     interface leds = top.leds;
     interface XADC xadc;
  