anchor.diff:      SyncBitIfc#(Bit#(1)) fifo_reset_sync <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
       Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  -    Reg#(Bit#(1)) reset_hack <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
  -    SyncBitIfc#(Bit#(1)) samplein_reset_null <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
   
       SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBit(serdes_clock, serdes_reset, serdes_clock);
       SyncBitIfc#(Bit#(10)) iserdes_data <-  mkSyncBits(0, serdes_clock, serdes_reset, defaultClock, defaultReset);
  
positive.code:         srval_q1: 0, srval_q2: 0, srval_q3: 0, srval_q4: 0,
          serdes_mode: "SLAVE", iobdelay: "NONE"},
          serdest, serdest_inverted.slowClock, clocked_by serdes_clock);
      Wire#(Bit#(1)) bvi_delay_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      SyncBitIfc#(Bit#(1)) bvi_resets_reg <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);
      Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  
negative.code:         delaye2.idatain(v);
      endmethod
      method Bit#(1)                align_busy();
          return pack(qstate != QIdle);
      endmethod
      method Bit#(1)                aligned();
          return unaligned_reg;
      endmethod
      method Bit#(3)                samplein();
          return ctrl_sample;
      endmethod
      method Action                 fifo_wren(Bit#(1) v);
          fifo_wren_sync.send(v);
  