anchor.diff:        Reg#(Bit#(32)) reqHeadReg <- mkReg(0);
         Reg#(Bit#(32)) reqTailReg <- mkReg(0);
         Reg#(Bit#(16)) wordCountReg <- mkReg(0);
  -      Reg#(Bit#(16)) demuxCountReg <- mkReg(0);
         Reg#(Bit#(16)) messageWordsReg <- mkReg(0);
         Reg#(Bit#(16)) methodIdReg <- mkReg(0);
         Reg#(SharedMemoryPortalState) reqState <- mkReg(Idle);
   
         rule updateReqHeadTail if (reqState == Idle && readyReg);
  -	 //$display("updateReqHeadTail");
  +	 $display("updateReqHeadTail");
   	 readEngine.readServers[0].request.put(MemengineCmd { sglId: sglIdReg,
   							     base: 0,
   							     burstLen: 16,
  
positive.code:       endrule
        rule waiting if (reqState == Waiting);
  	 let done <- writeEngine.writeServers[0].response.get();
  	 //$display("done waiting for write");
  	 reqState <= Idle;
        endrule
  
  
negative.code: 	    else
  	       reqState <= Idle;
  	 end
  	 if (head != tail || verbose || True)
  	    $display("receiveReqHeadTail state=%d w0=%x w1=%x head=%d tail=%d limit=%d", reqState, w0, w1, head, tail, reqLimitReg);
        endrule
  
        rule requestMessage if (reqState == RequestMessage);
  