anchor.diff:      method Action           manual_tap(Bit#(10) v);
       method Action           reset(Bit#(1) v);
       method Action           dataout(Bit#(10) v);
  +    method Action           edgeint(Bit#(10) v);
  +    method Action           edgeintor(Bit#(1) v);
       method Bit#(1)          ctrl_bitslip();
       method Bit#(1)          ctrl_fifo_reset();
       method Bit#(3)          ctrl_reset_inc_ce();
  
positive.code:     method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
      method                  reset(RESET) enable((*inhigh*) en17) clocked_by (clkdiv) reset_by(clkdiv_reset);
      method                  dataout(CTRL_DATA) enable((*inhigh*) en18) clocked_by(clock);
      method CTRL_BITSLIP     ctrl_bitslip() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method CTRL_FIFO_RESET   ctrl_fifo_reset() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method CTRL_RESET_INC_CE ctrl_reset_inc_ce() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method                  endhandshake(end_handshake) enable((*inhigh*) en20) clocked_by(clock);
      method start_handshake_o starthandshake();
      schedule (endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap)
           CF (endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  
negative.code:     Reg#(Bit#(10)) ctrl_data <- mkReg(0);
      Reg#(HState)  hstate <- mkReg(HIdle);
      Reg#(Bit#(6)) hcounter <- mkReg(0);
      Reg#(Bit#(1)) edge_intor_reg <- mkReg(0);
      SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  
      rule reset_clock_rule;
  