anchor.diff:  
      // CSRs
      Reg#(Bit #(64))   csr_cycle   <- mkConfigReg(0);
  -   Reg#(Bit #(64))   csr_time    <- mkConfigReg(0);
      Reg#(Bit #(64))   csr_instret <- mkConfigReg(0);
   
      // ----------------
      // These CSRs are technically not present in the user-mode ISA.
  -   // We have them here so that we can at least record the cause, so that the
  -   // environment (Supervisor, Hypervisor, Machine, or magic) can deal with it.
  -   // They will actually be used when we extend the spec to include machine-mode.
   
      Reg#(Word)  csr_mepc       <- mkRegU;
      Reg#(Word)  csr_mcause     <- mkRegU;
  
positive.code:                           fa_finish_with_Rd(decoded.rd, value);
                         end
                 f3_LW:  begin
                            Int#(32)  s32   = unpack(truncate (u));
                            Word_S    s     = signExtend(s32);
                            Word      value = pack(s);
                            fa_finish_with_Rd(decoded.rd, value);
  
negative.code:          tagged DMem_Resp_Ok .u: begin
              case (decoded.funct3)
                 f3_LB:  begin
                            Int#(8)   s8    = unpack(truncate(u));
                            Word_S    s     = signExtend(s8);
                            Word      value = pack(s);
                            fa_finish_with_Rd(decoded.rd, value);
                         end
  