anchor.diff:      interface Clock rxuserclk2;
       interface Clock userclk;
       interface Clock userclk2;
  +    interface Reset pma_reset_out;
   endinterface
   import "BVI" axi_ethernet_0 =
   module mkAxiEthBvi#(Clock ref_clk, Clock s_axi_clk, Reset s_axi_reset, Clock axis_clk,
  
positive.code:     interface AxiethbviMac     mac;
      interface AxiethbviMgt     mgt;
      interface AxiethbviMmcm     mmcm;
      interface AxiethbviPma     pma;
      interface AxiethbviS_axi     s_axi;
      interface AxiStreamSlave#(32)     s_axis_txc;
      interface AxiStreamSlave#(32)     s_axis_txd;
  
negative.code: (* always_ready, always_enabled *)
  interface AxiethbviMmcm;
      method Bit#(1)     locked_out();
  endinterface
  (* always_ready, always_enabled *)
  interface AxiethbviS_axi;
  