anchor.diff:  
      interface Ddr3TestRequest request;
         method Action startWriteDram(Bit#(32) sglId);
  +	 sglWriteProbe <= sglId;
   	 writeReqFifo.enq(sglId);
         endmethod
         method Action startReadDram(Bit#(32) sglId);
  +	 sglReadProbe <= sglId;
   	 readReqFifo.enq(sglId);
         endmethod
      endinterface
  
positive.code:    endrule
     rule rl_wdata;
        let mds <- toGet(dramWriteGearbox).get();
        ddr3Controller.slave.resp_write.put(Axi4WriteData {
  	 data: pack(mds),
  	 byteEnable: maxBound,
  
negative.code: 
     Gearbox#(BusRatio,1,Bit#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);
     SyncFIFOIfc#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkSyncFIFO(8, clock, reset, ddr3Controller.uiClock);
     //mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);
     rule rl_arfifo;
        let req <- toGet(arfifo).get();
        arAddrProbe <= req.address;
        arLenProbe <= req.len;
        arSizeProbe <= req.size;
        ddr3Controller.slave.req_ar.put(req);
     endrule
  
     Reg#(Bit#(Ddr3AddrWidth)) dramReadOffset <- mkReg(0);
     Reg#(Bit#(Ddr3AddrWidth)) dramReadLimit <- mkReg(0);
     rule rl_req_ar if (dramReadOffset < dramReadLimit);
        Axi4ReadRequest#(Ddr3AddrWidth,6) req = Axi4ReadRequest {
  	 address: truncate(dramReadOffset),
  	 len: 0, // indicates one beat of data
  	 size: axiBusSize(valueOf(Ddr3DataWidth)),
  