anchor.diff:             ,Mul#(dataWidthBytes, 8, busDataWidth)
              ,Div#(busDataWidth, 8, dataWidthBytes)
              );
  +   let verbose = False;
   
      FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();
      FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();
  
positive.code:                , req.firstbe, req.lastbe
  `endif
                 );
  	    readAddrGenerator.request.put(req);
              readByteEnableFifo.enq(reqLastByteEnable(req));
  	 endmethod
        endinterface
  
negative.code: 
     AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
  
     FIFO#(PhysMemRequest#(busAddrWidth, busDataWidth)) req_ars <- mkFIFO1;
     FIFO#(Bit#(bramAddrWidth)) req_addr <- mkFIFO1;
     FIFO#(BRAMRequestBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), dataWidthBytes)) req_aws <- mkFIFO1;
  
     Reg#(Bit#(32)) cycles      <- mkReg(0);
     rule count if (verbose);
        cycles <= cycles + 1;
     endrule
  
     rule req_ar;
       let req <- toGet(req_ars).get;
       readAddrGenerator.request.put(req);
     endrule
  
     rule read_req;
        let addrBeat <- readAddrGenerator.addrBeat.get();
  