anchor.diff:     MIMO#(2,1,2,Bit#(32)) readMimo <- mkMIMO(mimoConfig);
      Vector#(pipeCount, FIFOF#(Bit#(32))) dataFifo <- replicateM(mkFIFOF);
   
  -   let verbose = True;
  +   let verbose = False;
   
      rule updateReqRdWrPtr if (state == Idle && readyReg);
         if (verbose) $display("updateReqRdWrPtr");
  
positive.code:    rule send64bits;
        let v = gb.first;
        gb.deq();
        writeEngine[0].data.enq(pack(v));
     endrule
  
     rule sendHeader if (state == SendHeader && interruptStatus);
        Bit#(32) hdr <- toGet(pipes[readyChannel]).get();
        Bit#(16) numWords = hdr[15:0];
        let totalWords = numWords;
        if (numWords[0] == 1)
           totalWords = numWords + 1;
        paddingReg <= numWords[0] == 1;
        $display("sendHeader hdr=%h numWords=%d totalWords=%d paddingReg=%d wrPtrReg=%h", hdr, numWords, totalWords, paddingReg, wrPtrReg);
        wrPtrReg <= wrPtrReg + totalWords;
        messageWordsReg <= numWords;
        methodIdReg <= readyChannel;
        gb.enq(vec(hdr));
        writeEngine[0].request.put( MemengineCmd
            {sglId: sglIdReg, base: extend(wrPtrReg) << 2, burstLen: 8, len: extend(totalWords) << 2, tag: 0});
        state <= SendMessage;
     endrule
  
  
negative.code:    endrule
  
     rule updateWrPtr if (state == UpdateWrPtr);
        $display("updateWrPtr limit=%d wrPtr=%d", limitReg, wrPtrReg);
        Bit#(64) metadata = extend(limitReg);
        gb.enq(vec(extend(limitReg)));
        writeEngine[0].request.put(
               MemengineCmd {sglId: sglIdReg, base: 0 << 2, burstLen: 8, len: 2 << 2, tag: 0});
  