anchor.diff:        if (addr == 'h004)
   	 interruptEnableReg <= v[0] == 1'd1;
         if (b.last)
  -	 ctrlWriteDoneFifo.enq(b.tag);
  +	 fifoWriteDoneFifo.enq(b.tag);
      endrule
   
      interface PhysMemSlave memSlave;
         interface PhysMemReadServer read_server;
  -	 interface Put readReq = ctrlReadAddrGenerator.request;
  +	 interface Put readReq = fifoReadAddrGenerator.request;
   	 interface Get readData;
   	    method ActionValue#(MemData#(dataWidth)) get();
  -	       let b <- ctrlReadAddrGenerator.addrBeat.get();
  +	       let b <- fifoReadAddrGenerator.addrBeat.get();
   	       let addr = b.addr;
   	       let v = 'h05a05a0;
   	       if (addr == 'h000)
  
positive.code: module mkPortalCtrlMemSlave#(Bit#(dataWidth) ifcId, PortalInterrupt#(dataWidth) intr)
     (PortalCtrlMemSlave#(addrWidth, dataWidth))
     provisos(Add#(d__, dataWidth, TMul#(dataWidth, 2)));
     
     AddressGenerator#(addrWidth,dataWidth) ctrlReadAddrGenerator  <- mkAddressGenerator();
     AddressGenerator#(addrWidth,dataWidth) ctrlWriteAddrGenerator <- mkAddressGenerator();
     FIFO#(MemData#(dataWidth))        ctrlWriteDataFifo <- mkFIFO();
     FIFO#(Bit#(MemTagSize))        ctrlWriteDoneFifo <- mkFIFO();
     Reg#(Bit#(dataWidth)) num_portals_reg <- mkReg(0);
  
     Reg#(Bool) interruptEnableReg <- mkReg(False);
     Reg#(Bit#(TMul#(dataWidth,2))) cycle_count <- mkReg(0);
     Reg#(Bit#(dataWidth))    snapshot <- mkReg(0);
  
negative.code:     Bit#(6) tag;
  } ReadReqInfo deriving (Bits);
  
  module mkPipeInMemSlave#(PipeIn#(Bit#(dataWidth)) methodPipe)(PhysMemSlave#(addrWidth, dataWidth))
     provisos (Add#(1,a__,dataWidth));
     AddressGenerator#(addrWidth,dataWidth) fifoReadAddrGenerator  <- mkAddressGenerator();
     AddressGenerator#(addrWidth,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();
     FIFO#(Bit#(MemTagSize))                fifoWriteDoneFifo <- mkFIFO();
  
     interface PhysMemReadServer read_server;
        interface Put readReq = fifoReadAddrGenerator.request;
        interface Get readData;
  	 method ActionValue#(MemData#(dataWidth)) get();
  	    let b <- fifoReadAddrGenerator.addrBeat.get();
  	    let v = 0;
  	    if (b.addr == 4)
  	       v = extend(pack(methodPipe.notFull()));
  	    return MemData { data: v, tag: b.tag, last: b.last };
  	 endmethod
        endinterface
     endinterface
     interface PhysMemWriteServer write_server; 
        interface Put writeReq = fifoWriteAddrGenerator.request;
        interface Put writeData;
  	 method Action put((MemData#(dataWidth)) d);
  	    let b <- fifoWriteAddrGenerator.addrBeat.get();
  	    //$display("mkPipeInMemSlave.writeData.put addr=%h data=%h", b.addr, d.data);
  	    if (b.last)
  	       fifoWriteDoneFifo.enq(b.tag);
  	    methodPipe.enq(d.data);
  	    // this used to be where we triggered putFailed
  	 endmethod
        endinterface
        interface Get writeDone = toGet(fifoWriteDoneFifo);
     endinterface
  endmodule
  
  module mkPipeOutMemSlave#(PipeOut#(Bit#(dataWidth)) methodPipe)(PhysMemSlave#(addrWidth, dataWidth))
     provisos (Add#(1,a__,dataWidth));
     AddressGenerator#(addrWidth,dataWidth) fifoReadAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(addrWidth,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();
     FIFO#(Bit#(MemTagSize))                fifoWriteDoneFifo <- mkFIFO();
     FIFO#(MemData#(dataWidth))             fifoReadDataFifo <- mkFIFO();
  
     rule readDataRule;
        let b <- fifoReadAddrGenerator.addrBeat.get();
        let v = 0;
        if (b.addr == 0)
  	 v <- toGet(methodPipe).get();
        else if (b.addr == 4)
  	 v = extend(pack(methodPipe.notEmpty()));
        //$display("mkPipeOutMemSlave.readData.get addr=%h data=%h", b.addr, data);
        fifoReadDataFifo.enq(MemData { data: v, tag: b.tag, last: b.last });
     endrule
  
     interface PhysMemReadServer read_server;
        interface Put readReq = fifoReadAddrGenerator.request;
        interface Get readData;
  	 method ActionValue#(MemData#(dataWidth)) get();
  	    let d <- toGet(fifoReadDataFifo).get();
  	    return d;
  	 endmethod
        endinterface
     endinterface
     interface PhysMemWriteServer write_server; 
        interface Put writeReq = fifoWriteAddrGenerator.request;
        interface Put writeData;
  	 method Action put((MemData#(dataWidth)) d);
  	    let b <- fifoWriteAddrGenerator.addrBeat.get();
  	    //$display("mkPipeOutMemSlave.writeData.put addr=%h data=%h", b.addr, d.data);
  	    if (b.last)
  	       fifoWriteDoneFifo.enq(b.tag);
  	 endmethod
        endinterface
        interface Get writeDone = toGet(fifoWriteDoneFifo);
     endinterface
  endmodule
  
  interface PortalCtrlMemSlave#(numeric type addrWidth, numeric type dataWidth);
     interface PhysMemSlave#(addrWidth, dataWidth) memSlave;
     interface ReadOnly#(Bool) interrupt;
  