anchor.diff:  import Vector::*;
   import Clocks :: *;
   import FIFO::*;
  +import SyncBits::*;
   import XilinxCells::*;
   import XbsvXilinxCells::*;
   
  
positive.code:            master_data.q7(), master_data.q6(), master_data.q5(),
             master_data.q4(), master_data.q3(), master_data.q2(), master_data.q1()};
          ctrl_data_temp <= dout;
          for (Integer i = 0; i < 10; i = i + 1)
              iserdes_data[i].send(dout[i]);
      endrule
  
      rule datain_rule;
          Bit#(10) dout = 0;
          for (Integer i = 0; i < 10; i = i + 1)
              dout[i] = iserdes_data[i].read();
          if (fifo_wren_sync.read() == 1)
              begin
              dfifo.di({6'b0,dout});
  
negative.code: 
      rule qfsmall;
          let abusy = pack(qstate != QIdle);
          fifo_reset_sync.send(abusy);
          this_align_busy_wire <= abusy;
          samplein_reset_null.send(ctrl_sample[2]);
      endrule
  