anchor.diff:  	       tlp.data = pack(hdr_3dw);
   	    end
   	    tlpWriteHeaderFifo.enq(TlpWriteHeaderInfo {tlp: tlp, dwCount: tlplen, is3dw: writeIs3dw, isHeaderOnly: (writeIs3dw && tlplen == 1) });
  -	    writeBurstCountFifo.enq(extend(burstLen));
  +	    writeBurstCountFifo.enq(burstLen);
   	    writeTag.enq(extend(awid));
            endmethod
   	endinterface
         interface Put writeData;
            method Action put(MemData#(buswidth) wdata)
  -	      provisos (Bits#(Vector#(busWidthWords, Bit#(32)), busWidth)) if (writeDataMimo.enqReadyN(fromInteger(valueOf(busWidthWords))));
  +	    provisos (Bits#(Vector#(busWidthWords, Bit#(32)), busWidth)) if (writeDataMimoHasRoom); //.enqReadyN(fromInteger(valueOf(busWidthWords))));
   
   	    let burstLen = writeBurstCount;
   	    if (burstLen == 0) begin
  
positive.code:    `define AVALON
  `endif
  
  typedef 32 WriteDataMimoSize;
  module mkMemSlaveEngine#(PciId my_id)(MemSlaveEngine#(buswidth))
     provisos (Div#(buswidth, 8, busWidthBytes),
  	     Div#(buswidth, 32, busWidthWords),
  
negative.code:    mimoCfg.unguarded = True;
      MIMO#(busWidthWords,4,WriteDataMimoSize,Bit#(32)) writeDataMimo <- mkMIMO(mimoCfg);
      ConfigCounter#(8) writeDataCnt <- mkConfigCounter(0);
      Reg#(Bit#(WriteDataBurstLenSize)) writeBurstCount <- mkReg(0);
      FIFO#(Bit#(WriteDataBurstLenSize)) writeBurstCountFifo <- mkFIFO();
      Reg#(TLPLength)  writeDwCount <- mkReg(0); // how many 4 byte (double) words to send
      Reg#(LUInt#(4))    tlpDwCount <- mkReg(0); // how many to send in the next tlp (at most 4)
      Reg#(Bool)            lastTlp <- mkReg(False); // if the next tlp sent is the last one
  