anchor.diff:     BRAM_Configure bramConfig = defaultValue;
      //bramConfig.memorySize = 1024;
      bramConfig.latency = 2;
  -   BRAM2Port#(Bit#(PktAddrWidth), ByteStream#(n)) memBuffer <- mkBRAM2Server(bramConfig);
  +   BRAM2Port#(Bit#(depth), ByteStream#(n)) memBuffer <- mkBRAM2Server(bramConfig);
   
      FIFOF#(ByteStream#(n)) fifoWriteData <- mkFIFOF;
      FIFOF#(Bit#(EtherLen)) fifoEop <- mkFIFOF;
  -   FIFO#(ReqT#(n)) incomingReqs     <- mkFIFO;
  +   FIFO#(ReqT#(n, depth)) incomingReqs     <- mkFIFO;
   
      // Client
  -   Reg#(Bit#(PktAddrWidth))     rdCurrPtr   <- mkReg(0);
  +   Reg#(Bit#(depth))     rdCurrPtr   <- mkReg(0);
      Reg#(Bool)                   outPacket   <- mkReg(False);
   
      FIFOF#(Bit#(EtherLen))    fifoLen     <- mkSizedFIFOF(16);
  
positive.code: `include "SynthBuilder.defines"
  
  typedef struct {
     Bit#(PktAddrWidth) addr;
     ByteStream#(n)     data;
  } ReqT#(numeric type n) deriving (Eq, Bits);
  instance FShow#(ReqT#(n));
     function Fmt fshow (ReqT#(n) req);
        return ($format(" addr=0x%x ", req.addr)
                + $format(" data=0x%x ", req.data.data)
                + $format(" user=0x%x ", req.data.user)
  
negative.code:    endrule
  
     rule enqueue_first_beat(!fifoEop.notEmpty && !inPacket);
        ReqT#(n, depth) req <- toGet(incomingReqs).get;
        dbprint(3, $format("%s enqueue_first_beat ", msg, fshow(req)));
        memBuffer.portA.request.put(BRAMRequest{write:True, responseOnWrite:False,
           address:req.addr, datain:req.data});
  