anchor.diff:     let bramQueryResponse <- mkProbe();
      let requestCompleted <- mkProbe();
   
  -   let fsm <- mkAutoFSM(seq
  +   let requestFsm <- mkAutoFSM(seq
         while (True) seq
   	 action
   	    let req <- toGet(ioCommandFifo).get();
  
positive.code:    MemServerPortal          bramMemServerPortal <- mkPhysMemSlavePortal(bramMemB,bramIndication);
  
     let portB1 = arbiter.users[1];
     Reg#(Bit#(16)) requestId <- mkReg(0);
     Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);
     Reg#(Bool) requestInProgress <- mkReg(True);
     Reg#(Vector#(16,Bit#(32))) ioCommand <- mkReg(unpack(0));
     Reg#(Bit#(32)) requestStartTimestamp <- mkReg(0);
  
negative.code: 	    command[13] = req.dsm;
  	    requestId <= req.requestId;
  	    ioCommand <= command;
  
  	    requestSlotAvailable <= False;
  	 endaction
  
  	 while (!requestSlotAvailable) seq // wait for open request slot
  	    portB1.request.put(BRAMRequest {address: (extend(requestId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),
  					    write: False, responseOnWrite: False, datain: 0});
  	    action
  	       let response <- portB1.response.get();
  	       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == ~phase) begin
  		  requestSlotAvailable <= True;
  	       end
  	    endaction
  	 endseq // wait for open request slot
  
  	 // write a IO read request to BRAM
           for (i <= 0; i < fromInteger(requestSize/bytesPerEntry); i <= i + 1) seq
  	    portB1.request.put(BRAMRequest {address: 'h1000/fromInteger(bytesPerEntry) + (extend(requestId[2:0]) * fromInteger(requestSize/bytesPerEntry)) + i,
  