anchor.diff:     let wdataCtlCnx  <- mkConnection(toGet(wdataFifoCtl), axiRootPortMemSlaveCtl.write_server.writeData);
      let doneCtlCnx   <- mkConnection(axiRootPortMemSlaveCtl.write_server.writeDone, toPut(doneFifoCtl));
   
  -   Reg#(Bool) inSetup <- mkReg(False);
  -
      rule rl_rdata_ctl if (!inSetup);
         let rdata <- toGet(rdataFifoCtl).get();
         driverInd.readDone(extend(rdata.data));
  
positive.code:       method Action trace(Bool enabled);
  	 traceEnabled <= enabled;
        endmethod
        method Action read32(Bit#(32) addr);
  	 araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });
        endmethod
        method Action write32(Bit#(32) addr, Bit#(32) value);
  	 awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });
  	 wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});
        endmethod
        method Action read(Bit#(32) addr);
  	 araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });
        endmethod
        method Action write(Bit#(32) addr, Bit#(DataBusWidth) value);
  	 awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });
  	 wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});
        endmethod
  
negative.code:    MemServerGearbox#(PcieDataBusWidth,DataBusWidth) axiGearbox <- mk1toNMemServerGearbox();
     let gearboxCnx <- mkConnection(splitter.busClient, axiGearbox.server);
  
     Reg#(Bit#(16)) requestId <- mkReg(0);
     Reg#(Bit#(16)) responseId <- mkReg(0);
     Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);
  