anchor.diff:         let tlp <- arbiter.tlp_out_to_bus.get();
          tlpToBusFifo.enq(tlp);
          if (csr.tlpTracing) begin
  -	   TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 7'h08, tlp: tlp };
  -	   csr.toPcieTraceBramPort.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(csr.toPcieTraceBramWrAddr), datain: ttd });
  -	   csr.toPcieTraceBramWrAddr <= csr.toPcieTraceBramWrAddr + 1;
  +	  toPcie.send();
  +	  toPcieTlp <= tlp;
          end
      endrule: traceTlpToBus
  +
  +   rule doTracing if (fromPcie || toPcie);
  +      TLPData#(16) fromtlp = (fromPcie) ? fromPcieTlp : unpack(0);
  +      TLPData#(16)   totlp =   (toPcie) ?   toPcieTlp : unpack(0);
  +      TimestampedTlpData fromttd = TimestampedTlpData { timestamp: timestamp, source: 7'h04, tlp: fromtlp };
  +      csr.fromPcieTraceBramPort.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(csr.fromPcieTraceBramWrAddr), datain: fromttd });
  +      csr.fromPcieTraceBramWrAddr <= csr.fromPcieTraceBramWrAddr + 1;
  +
  +      TimestampedTlpData   tottd = TimestampedTlpData { timestamp: timestamp, source: 7'h08, tlp: totlp };
  +      csr.toPcieTraceBramPort.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(csr.toPcieTraceBramWrAddr), datain: tottd });
  +      csr.toPcieTraceBramWrAddr <= csr.toPcieTraceBramWrAddr + 1;
  +   endrule
   
      // route the interfaces to the sub-components
   
  
positive.code: 
     FIFO#(TLPData#(16)) tlpFromBusFifo <- mkFIFO();
     Reg#(Bool) skippingIncomingTlps <- mkReg(False);
     rule traceTlpFromBus;
         let tlp = tlpFromBusFifo.first;
         tlpFromBusFifo.deq();
  
negative.code: 	      // do nothing
  	   end
  	   else begin
  	      fromPcie.send();
  	      fromPcieTlp <= tlp;
  	       skippingIncomingTlps <= False;
  	   end
         end
  