anchor.diff:  import Leds              :: *;
   import Top               :: *;
   import AxiMasterSlave    :: *;
  +import Dma               :: *;
   import AxiDma            :: *;
   
   // implemented in BsimCtrl.cxx
  
positive.code:    endrule
  
     interface axi_servers = servers;
     interface Axi3Master axi_client;
        interface Get req_ar;
  	 method ActionValue#(Axi3ReadRequest#(clientAddrWidth,clientIdWidth)) get() if (crw.readReq);
  	    //$write("req_ar: ");
  	    let ra <- crw.readAddr;
  	    //$display("ra=%h", ra);
  	    return Axi3ReadRequest { address: ra, len: 0, size: axiBusSize(32), id: 0, prot: 0, burst: 1, cache: 'b11, qos: 0, lock: 0 };
  	 endmethod
        endinterface
        interface Put resp_read;
  	 method Action put(Axi3ReadResponse#(clientBusWidth,clientIdWidth) rd);
  	    //$display("resp_read: rd=%h", rd);
  	    crw.readData(rd.data);
  	 endmethod
        endinterface
        interface Get req_aw;
  	 method ActionValue#(Axi3WriteRequest#(clientAddrWidth,clientIdWidth)) get() if (crw.writeReq());
  	    //$write("req_aw: ");
  	    let wa <- crw.writeAddr;
  	    let wd <- crw.writeData;
  	    //$display("wa=%h, wd=%h", wa,wd);
  	    wf.enq(wd);
  	    return Axi3WriteRequest { address: wa, len: 0, size: axiBusSize(32), id: 0, prot: 0, burst: 1, cache: 'b11, qos: 0, lock: 0 };
  	 endmethod
        endinterface
        interface Get resp_write;
  	 method ActionValue#(Axi3WriteData#(clientBusWidth,clientIdWidth)) get;
  	    wf.deq;
  	    //$display("resp_write %h", wf.first);
  	    return Axi3WriteData { data: wf.first, id: 0, last: 1 };
  	 endmethod
        endinterface
        interface Put resp_b;
  	 method Action put(Axi3WriteResponse#(clientIdWidth) resp);
  	    noAction;
  	 endmethod
        endinterface
     endinterface
  endmodule
     
  typedef (function Module#(PortalTop#(40, dsz, ipins, nMasters)) mkPortalTop()) MkPortalTop#(numeric type dsz, type ipins, numeric type nMasters);
  
  module [Module] mkBsimTopFromPortal#(MkPortalTop#(dsz,Empty,nMasters) mkPortalTop)(Empty)
  
negative.code:    BsimHost#(32,32,12,40,dsz,6,nMasters) host <- mkBsimHost;
     PortalTop#(40,dsz,Empty,nMasters) top <- mkPortalTop;
     Vector#(nMasters,Axi3Master#(40,dsz,6)) m_axis <- mapM(mkAxiDmaMaster,top.masters);
     mkConnection(host.mem_client, top.slave);
     mapM(uncurry(mkConnection),zip(m_axis, host.axi_servers));
  
     // mkConnection(m_axis[0].req_ar, host.axi_servers[0].req_ar);
  