anchor.diff:     interface Reg axiEnabled = axiEnabledReg;
      interface Reg pipeliningEnabled = pipeliningEnabledReg;
      interface Reg byteSwap = byteSwapReg;
  +   interface Reg use4dw = use4dwReg;
      interface Reg axiTestEnabled = axiTestEnabledReg;
      interface Reg numPortals = numPortalsReg;
      interface Reg addrLowerWord = addrLowerWordReg;
  
positive.code:    interface Reg#(Bool) axiEnabled;
     interface Reg#(Bool) pipeliningEnabled;
     interface Reg#(Bool) byteSwap;
     interface Reg#(Bit#(4)) numPortals;
     interface Reg#(Bit#(32)) axiTestEnabled;
     interface Reg#(Bit#(32)) addrLowerWord;
  
negative.code: 	    792: tlpDataBramWrAddrReg <= dword;
  	    794: byteSwapReg <= (dword != 0) ? True : False;
  	    796: numPortalsReg <= truncate(dword);
  	    797: use4dwReg <= unpack(truncate(dword));
  
              // MSIx table entries
              4096: msix_entry[0].addr_lo  <= update_dword(msix_entry[0].addr_lo, be, (dword & 32'hfffffffc));
  