anchor.diff:  
      method Bit#(32) readStatus(Bit#(12) addr);
   
  -   interface AxiMasterRead#(busWidth) axi;
  +   interface Axi3ReadClient#(busWidth,idWidth) axi;
   
      method Action deq();
      method Bit#(busWidth) first();
      method ActionValue#(Bit#(32)) getResponse();
   endinterface
   
  -module mkFifoToAxi(FifoToAxi#(busWidth,busWidthBytes)) provisos(Div#(busWidth,8,busWidthBytes),Add#(1,z,busWidth));
  +module mkFifoToAxi(FifoToAxi#(busWidth,busWidthBytes,idWidth)) provisos(Div#(busWidth,8,busWidthBytes),Add#(1,z,busWidth));
      Reg#(Bool) enabledReg <- mkReg(False);
      Reg#(Bool) oneBeatAddressReg <- mkReg(True);
      Reg#(Bool) thirtyTwoBitTransferReg <- mkReg(False);
  
positive.code: 
             let d = dfifo.first;
             dfifo.deq;
             return d;
         endmethod
         method Bit#(busWidthBytes) writeDataByteEnable();
             return maxBound;
         endmethod
         method Bit#(1) writeLastDataBeat(); // last data beat
             if (burstCountReg == 8'd1)
                 return 1'b1;
             else
                 return 1'b0;
         endmethod
  
         method Action writeResponse(Bit#(2) responseCode, Bit#(1) id) if (axiBrespFifo.notFull);
             if (responseCode != 2'b00)
                 axiBrespFifo.enq(responseCode);
         endmethod
     endinterface
  
  
negative.code: 
     method Bit#(32) readStatus(Bit#(12) addr);
  
     interface Axi3WriteClient#(busWidth,busWidthBytes,idWidth) axi;
     method Action enq(Bit#(busWidth) value);
     method ActionValue#(Bit#(32)) getResponse();
  endinterface
  
  interface FifoFromAxi#(type busWidth, type idWidth);
     interface Reg#(Bit#(32)) base;
     interface Reg#(Bit#(32)) bounds;
     interface Reg#(Bit#(32)) threshold;
  