anchor.diff:  
   
   (* synthesize *)
  -module mkSynthesizeablePortalTop#(Clock clock200, Clock io_vita_clk)(PortalTop#(40, 64, ImageonVita));
  +module mkSynthesizeablePortalTop#(Clock clock200, Clock io_vita_clk)(PortalTop#(40, 64, ImageCapturePins));
      let top <- mkPortalTop(clock200, io_vita_clk);
  -   interface ctrl = top.ctrl;
  -   interface read_client = top.read_client;
  -   interface write_clinet = top.write_client;
  +   interface master = top.master;
  +   interface slave = top.slave;
      interface interrupt = top.interrupt;
      interface leds = top.leds;
      interface pins = top.pins;
  
positive.code:    X7PcieSplitter#(PcieLanes) x7pcie <- mkX7PcieSplitter(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n,
  							 contentId );
     
     Reg#(Bool) interruptRequested <- mkReg(False, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // instantiate user portals
     Clock io_vita_clk <- XilinxCells::mkClockIBUFDS(io_vita_clk_out_p, io_vita_clk_out_n);
     let portalTop <- mkPortalTop(x7pcie.clock200, io_vita_clk, clocked_by x7pcie.clock125, reset_by x7pcie.portalReset);
  
negative.code: // SOFTWARE.
  
  import Vector            :: *;
  import GetPut            :: *;
  import Connectable       :: *;
  import Xilinx            :: *;
  import XilinxCells       :: *;
  