anchor.diff:  //  word7  TAG[31:0]
   
   module mkCopyEngine#(DMAReadServer#(64) copy_read_chan, DMAWriteServer#(64) copy_write_chan) ( ServerF#(Bit#(64), Bit#(64)));
  -   FIFO#(Bit#(64)) f_in  <- mkSizedFIFO(16);    // to buffer incoming requests
  -   FIFO#(Bit#(64)) f_out <- mkSizedFIFO(16);    // to buffer outgoing responses
  +   FIFOF#(Bit#(64)) f_in  <- mkSizedFIFOF(16);    // to buffer incoming requests
  +   FIFOF#(Bit#(64)) f_out <- mkSizedFIFOF(16);    // to buffer outgoing responses
      Reg#(Bit#(16)) copyReadCount <- mkReg(0);
      Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
      Reg#(Bit#(DmaAddrSize)) copyReadAddr <- mkReg(0);
  
positive.code: 	       copyWriteCount <= f_in.first()[15:0];
  	       f_in.deq();  // word 3
  	    endaction
  	    for (ii <= 4; ii < 8; ii <= ii+1)
  	       f_in.deq;  // discard words 4-7
  	    copyBusy <= True;
  	 endseq
  
negative.code: 		  let v <- copy_write_chan.writeDone.get;
  		  copyWriteCount <= copyWriteCount - 8;	 
  	       endaction
  	    f_out.enq(0);
  	    f_out.enq(0);
  	    f_out.enq(0);
  	    f_out.enq(0);
  	    f_out.enq(0);
  	    f_out.enq(0);
  	    f_out.enq(0);
  	    f_out.enq(extend(copyTag));
  	    copyBusy <= False;
  	 endseq
  