anchor.diff:         addrReg <= addr;
      endrule
   
  -   method Bit#(4) debug;
  -       return {bscan.sel(), bscan.capture(), bscan.shift(), bscan.update()};
  -   endmethod
      interface BRAMClient bramClient;
         interface Get request;
   	 method ActionValue#(BRAMRequest#(atype,dtype)) get() if (requestWire matches tagged Valid .req);
  
positive.code:    Reg#(Bit#(asz)) addrReg <- mkReg(0, clocked_by tck, reset_by rst);
     Reg#(Bool) capture_delay <- mkReg(False, clocked_by tck, reset_by rst);
     Reg#(Bool) selected_delay <- mkReg(False, clocked_by tck, reset_by rst);
     Wire#(Bit#(1)) tdow <- mkDWire(0, clocked_by tck, reset_by rst);
     rule tdo;
        bscan.tdo(tdow);
     endrule
  
     rule selected_rule;
  
negative.code:        capture_delay <= bscan.sel() == 1 && bscan.capture() == 1;
     endrule
  
     //rule addr_clock_crossing;
         //addr_jtag.send(pack(addr));
     //endrule
  
     rule captureRule if (bscan.sel() == 1 && bscan.capture() == 1);
         requestWire <= tagged Valid BRAMRequest {write:False, responseOnWrite:False, address:unpack(addrReg), datain:?};
  