anchor.diff:              `SLLW:  tagged Valid (tagged Alu AluInst{op: Sll,   w: True});
               `SRLW:  tagged Valid (tagged Alu AluInst{op: Srl,   w: True});
               `SRAW:  tagged Valid (tagged Alu AluInst{op: Sra,   w: True});
  -
               // LOAD
  -            `LB:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: B, isUnsigned: False});
  -            `LH:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: H, isUnsigned: False});
  -            `LW:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: W, isUnsigned: False});
  -            `LBU:   tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: B, isUnsigned: True});
  -            `LHU:   tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: H, isUnsigned: True});
  -            // 64-bit Only
               `LD:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: D, isUnsigned: False});
               `LWU:   tagged Valid (tagged Mem RVMemInst{op: tagged Mem Ld, size: W, isUnsigned: True});
               // STORE
  -            `SB:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem St, size: B, isUnsigned: False});
  -            `SH:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem St, size: H, isUnsigned: False});
  -            `SW:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem St, size: W, isUnsigned: False});
  -            // 64-bit Only
               `SD:    tagged Valid (tagged Mem RVMemInst{op: tagged Mem St, size: D, isUnsigned: False});
  -
               // MISC-MEM
               `FENCE:     tagged Valid (tagged Fence (tagged InterCore unpack(truncate(inst[27:20]))));
               `FENCE_I:   tagged Valid (tagged Fence (tagged IntraCore FenceI));
  
positive.code:             `FSQRT_S:   tagged Valid (tagged Fpu FpuInst{func: FSqrt,    precision: Single});
  `endif
  
              `FADD_D:    tagged Valid (tagged Fpu FpuInst{func: FAdd,     precision: Double});
              `FSUB_D:    tagged Valid (tagged Fpu FpuInst{func: FSub,     precision: Double});
              `FMUL_D:    tagged Valid (tagged Fpu FpuInst{func: FMul,     precision: Double});
  
negative.code:         endcase);
  endfunction
  
  function Maybe#(ExecFunc) toExecFuncPriv(Instruction inst);
      InstructionFields instFields = unpack(inst);
      return (case (inst) matches
              `ECALL:     tagged Valid (tagged System ECall);
  