anchor.diff:          fifo_reset <= dfifo_reset_r;
           sric[0] = 0;
           sric[1] = 0;
  -        //iodelay_reset_inc_ce <= sync_reset_inc_ce;
  -        //iserdes_bitslip <= sync_bitslip;
  -        iodelay_reset_inc_ce <= serbvi.iodelay_reset_inc_ce();
  -        iserdes_bitslip <= serbvi.bitslip();
  +        iserdes_bitslip <= sync_bitslip;
           if (dstate == DIdle && dreqpipe1 == 1)
               begin
               sric = serbvi.ctrl_reset_inc_ce();
  
positive.code:     method Bit#(1)          align_busy();
      method Bit#(1)          aligned();
      method Bit#(3)          samplein();
      method Bit#(3)          iodelay_reset_inc_ce();
      method Bit#(1)          bitslip();
      method Action           autoalign(Bit#(1) v);
      method Action           training(Bit#(10) v);
      method Action           manual_tap(Bit#(10) v);
      method Action           delay_wren(Bit#(1) v);
      method Action           fifo_wren(Bit#(1) v);
      method Action           reset(Bit#(1) v);
      method Bit#(1)          fifo_wren_sync();
      method Action           dataout(Bit#(10) v);
      method Bit#(1)          itemreq();
      method Bit#(1)          ctrl_bitslip();
  
negative.code:     method CTRL_FIFO_RESET_o   ctrl_fifo_reset() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method CTRL_RESET_INC_CE_o ctrl_reset_inc_ce() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method                  dackint(DACKINT) enable((*inhigh*) en19) clocked_by(clkdiv) reset_by(clkdiv_reset);
      schedule (dackint, ctrl_reset_inc_ce, itemreq, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap)
           CF (dackint, ctrl_reset_inc_ce, itemreq, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  