anchor.diff:      endrule
       rule aw_to_slave;
          let req <- toGet(awFifo).get();
  -       slave.read_server.readReq.put(req);
  +       slave.write_server.writeReq.put(req);
       endrule
   
       rule r_rule if (rreadyWire == 1 && rdataFifo.notEmpty());
          rdataFifo.deq();
  +    endrule
  +    rule rdata_rule;
  +       rdataWire <= rdataFifo.first.data;
       endrule
       rule rdata_from_slave;
          let mdata <- slave.read_server.readData.get();
  
positive.code:        return pack(brespFifo.notEmpty());
      endmethod
      method Bit#(dataWidth)     rdata();
         return rdataFifo.first.data;
      endmethod
      method Action      rready(Bit#(1) v);
         rreadyWire <= v;
  
negative.code:    method Action pwr_state(Bit#(2) pwr_state);
  endinterface
  
  (* always_ready, always_enabled *)
  interface AwsF1Top;
     interface PinType pins;
     interface AwsF1ShCl sh_cl;
  