anchor.diff:      method Bit#(1) DDR_VRN();
       method Bit#(1) DDR_VRP();
       method Bit#(1) DDR_WEB();
  +endinterface
  +interface Dma;
       method Action DMA0_ACLK(Bit#(1) v);
       method Action DMA0_DAREADY(Bit#(1) v);
       method Bit#(2) DMA0_DATYPE();
  
positive.code:     method Action DMA0_DRTYPE(Bit#(2) v);
      method Action DMA0_DRVALID(Bit#(1) v);
      method Bit#(1) DMA0_RSTN();
      method Action DMA1_ACLK(Bit#(1) v);
      method Action DMA1_DAREADY(Bit#(1) v);
      method Bit#(2) DMA1_DATYPE();
      method Bit#(1) DMA1_DAVALID();
      method Action DMA1_DRLAST(Bit#(1) v);
      method Bit#(1) DMA1_DRREADY();
      method Action DMA1_DRTYPE(Bit#(2) v);
      method Action DMA1_DRVALID(Bit#(1) v);
      method Bit#(1) DMA1_RSTN();
      method Action DMA2_ACLK(Bit#(1) v);
      method Action DMA2_DAREADY(Bit#(1) v);
      method Bit#(2) DMA2_DATYPE();
      method Bit#(1) DMA2_DAVALID();
      method Action DMA2_DRLAST(Bit#(1) v);
      method Bit#(1) DMA2_DRREADY();
      method Action DMA2_DRTYPE(Bit#(2) v);
      method Action DMA2_DRVALID(Bit#(1) v);
      method Bit#(1) DMA2_RSTN();
      method Action DMA3_ACLK(Bit#(1) v);
      method Action DMA3_DAREADY(Bit#(1) v);
      method Bit#(2) DMA3_DATYPE();
      method Bit#(1) DMA3_DAVALID();
      method Action DMA3_DRLAST(Bit#(1) v);
      method Bit#(1) DMA3_DRREADY();
      method Action DMA3_DRTYPE(Bit#(2) v);
      method Action DMA3_DRVALID(Bit#(1) v);
      method Bit#(1) DMA3_RSTN();
      method Action ENET0_EXT_INTIN(Bit#(1) v);
      method Action ENET0_GMII_COL(Bit#(1) v);
      method Action ENET0_GMII_CRS(Bit#(1) v);
  
negative.code:     method Bit#(8) WCOUNT();
      method Action WRISSUECAP1_EN(Bit#(1) v);
  endinterface
  interface Ddr;
      method Bit#(15) DDR_Addr();
      method Bit#(3) DDR_BankAddr();
      method Bit#(1) DDR_CAS_n();
  