anchor.diff:  	  match { .addr, .data } = intr;
   	  Bool mswIsZero = (addr[63:32] == 0);
   	  Bool lswIsZero = (addr[31:0] == 0);
  -          interruptRequestFifo.enq(tuple4(addr, data, lswIsZero, mswIsZero));
  +          interruptRequestFifo.enq(InterruptRequest { addr: addr, data: data, mswIsZero: mswIsZero, lswIsZero: lswIsZero });
          endmethod
       endinterface
   endmodule: mkMemInterrupt
  
positive.code:     interface Put#(Tuple2#(Bit#(64),Bit#(32))) interruptRequest;
  endinterface
  
  //(* synthesize *)
  module mkMemInterrupt#(PciId my_id)(MemInterrupt);
      FIFOF#(Tuple4#(Bit#(64),Bit#(32),Bool,Bool)) interruptRequestFifo <- mkFIFOF();
      Reg#(Maybe#(Bit#(32))) interruptSecondHalf <- mkReg(tagged Invalid);
      Reg#(TLPTag) tlpTag <- mkReg(0);
      FIFOF#(TLPData#(16)) tlpOutFifo <- mkSizedFIFOF(8);
  
negative.code:        let interruptRequested = True;
         let sendInterrupt = False;
  
         let interruptRequest = interruptRequestFifo.first;
         let interruptAddr = interruptRequest.addr;
         let interruptData = interruptRequest.data;
         let mswIsZero = interruptRequest.mswIsZero;
         let lswIsZero = interruptRequest.lswIsZero;
  
         if (mswIsZero && lswIsZero) begin
  	  // do not write to 0 -- it wedges the host
  	  interruptRequested = False;
  