anchor.diff:  	    requestStartTimestamp <= cycles;
   	    trace.traceData(unpack(0), False, truncate(requestId), cycles);
   	 endaction
  +      endseq // while True
  +      endseq);
  +
  +   let responseFsm <- mkAutoFSM(seq
   	 // wait for response queue to be updated
  +      while (True) seq
  +	 requestInProgress <= True;
   	 while (requestInProgress) seq
  -	    portB1.request.put(BRAMRequest {address: (extend(requestId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),
  +	    portB2.request.put(BRAMRequest {address: (extend(responseId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),
   					    write: False, responseOnWrite: False, datain: 0});
  -	    bramQueryAddress <= (requestId * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry);
  +	    bramQueryAddress <= (responseId * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry);
   	    action
  -	       let response <- portB1.response.get();
  +	       let response <- portB2.response.get();
   	       bramQueryResponse <= response;
   	       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == phase) begin
   		  requestCompleted <= response;
   		  // if status field written by NVME
  -		  ind.transferCompleted(requestId, truncate(response), cycles - requestStartTimestamp);
  +		  ind.transferCompleted(responseId, truncate(response), cycles - requestStartTimestamp);
   		  requestInProgress <= False;
   	       end
   	    endaction
  
positive.code:    BRAM2Port#(Bit#(32),Bit#(PcieDataBusWidth)) bram <- mkBRAM2Server(bramConfig);
  
     let arbIfc <- mkFixedPriority();
     Arbiter#(2, BRAMRequest#(Bit#(32),Bit#(PcieDataBusWidth)),Bit#(PcieDataBusWidth)) arbiter <- mkArbiter(arbIfc,2);
     let arbCnx <- mkConnection(arbiter.master, bram.portB);
  
     MemServer#(PcieDataBusWidth)            bramMemA <- mkMemServerFromBram(bram.portA);
  
negative.code:    MemServerPortal          bramMemServerPortal <- mkPhysMemSlavePortal(bramMemB,bramIndication);
  
     let portB1 = arbiter.users[1];
     let portB2 = arbiter.users[2];
     Reg#(Bit#(16)) requestId <- mkReg(0);
     Reg#(Bit#(16)) responseId <- mkReg(0);
     Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);
     Reg#(Bool) requestSlotAvailable <- mkReg(True);
     Reg#(Bool) requestInProgress <- mkReg(True);
     Reg#(Vector#(16,Bit#(32))) ioCommand <- mkReg(unpack(0));
     Reg#(Bit#(32)) requestStartTimestamp <- mkReg(0);
  