anchor.diff:  				     regionall.reg8.barrier, regionall.reg4.barrier, regionall.reg0.barrier,
   				     off8, off4, off0);
   	       
  -	       conds[i].enq(tuple4(cond12,cond8,cond4,cond0));
  -	       idxOffsets0[i].enq(tuple4(regionall.reg12.idxOffset,regionall.reg8.idxOffset,regionall.reg4.idxOffset, regionall.reg0.idxOffset));
  -	       reqs1[i].enq(req);
  +	       stage3Params[i].enq(Stage3Params {cond12: cond12, cond8: cond8, cond4: cond4, cond0: cond0,
  +						 idxOffset12: regionall.reg12.idxOffset,idxOffset8: regionall.reg8.idxOffset,
  +						 idxOffset4: regionall.reg4.idxOffset, idxOffset0: regionall.reg0.idxOffset,
  +						 req: req });
   	    end
   	    tagged Invalid:
   	       dmaErrorFifo.enq(DmaError { errorType: DmaErrorSGLIdInvalid, pref: extend(req.id), off:req.off });
   	 endcase
         endrule
         rule stage3; // Based on results of comparision, select a region, putting it into 'o.pageSize'.  idxOffset holds offset in sglist table of relevant entry
  -	 ReqTup req <- toGet(reqs1[i]).get;
  +	 let params <- toGet(stage3Params[i]).get();
  +	 ReqTup req = params.req;
   	 Offset o = Offset{pageSize: 0, value: truncate(req.off)};
   	 Bit#(IndexWidth) pbase = 0;
   	 Bit#(IndexWidth) idxOffset = 0;
   
  -	 match{.cond12,.cond8,.cond4,.cond0} <- toGet(conds[i]).get;
  -	 match{.idxOffset12,.idxOffset8,.idxOffset4,.idxOffset0} <- toGet(idxOffsets0[i]).get;
  -
  -	 if (cond12) begin
  +	 if (params.cond12) begin
   	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
   	    o.pageSize = 4;
   	    pbase = truncate(req.off>>page_shift12);
  -	    idxOffset = idxOffset12;
  -	 end
  -	 else if (cond8) begin
  +	    idxOffset = params.idxOffset12;
  +	 end
  +	 else if (params.cond8) begin
   	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
   	    o.pageSize = 3;
   	    pbase = truncate(req.off>>page_shift8);
  -	    idxOffset = idxOffset8;
  -	 end
  -	 else if (cond4) begin
  +	    idxOffset = params.idxOffset8;
  +	 end
  +	 else if (params.cond4) begin
   	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
   	    o.pageSize = 2;
   	    pbase = truncate(req.off>>page_shift4);
  -	    idxOffset = idxOffset4;
  -	 end
  -	 else if (cond0) begin
  +	    idxOffset = params.idxOffset4;
  +	 end
  +	 else if (params.cond0) begin
   	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
   	    o.pageSize = 1;
   	    pbase = truncate(req.off>>page_shift0);
  -	    idxOffset = idxOffset0;
  +	    idxOffset = params.idxOffset0;
   	 end
   	 offs0[i].enq(o);
   	 pbases[i].enq(pbase);
  
positive.code: 		Bit#(MemOffsetSize) off;
     } DmaError deriving (Bits);
  
  // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  module mkMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
     provisos(Log#(MaxNumSGLists, listIdxSize),
  
negative.code:    Vector#(2,FIFOF#(ReqTup))          reqs0 <- replicateM(mkSizedFIFOF(3));
     
     // stage 2 (latency == 1)
     Vector#(2, FIFOF#(Stage3Params)) stage3Params <- replicateM(mkFIFOF);
  
     // stage 3 (latency == 1)
     Vector#(2,FIFOF#(Offset))           offs0 <- replicateM(mkFIFOF);
  