anchor.diff:      interface Get#(TLPData#(16))   tlp_out;
       interface Axi3Master#(32,32,4,12) portal;
       interface Reg#(Bool)           pipeliningEnabled;
  +    interface Reg#(Bool)           byteSwap;
   endinterface
   
   (* synthesize *)
   module mkPortalEngine#(PciId my_id)(PortalEngine);
       Reg#(Bool) pipeliningEnabledReg <- mkReg(False);
  +    Reg#(Bool) byteSwapReg <- mkReg(True);
       Reg#(Bool) busyReg <- mkReg(False);
       Reg#(Bit#(7)) hitReg <- mkReg(0);
       Reg#(Bit#(4)) timerReg <- mkReg(0);
  
positive.code: 	    method ActionValue#(Bit#(32)) writeData();
  	        busyReg <= False;
  	        writeDataFifo.deq;
  		return byteSwap(writeDataFifo.first.data);
  	    endmethod
  	    method Bit#(12) writeWid();
  		return extend(writeDataFifo.first.tag);
  
negative.code: 	    788: axiEnabledReg <= (dword != 0) ? True : False;
  	    789: tlpDataBramRdAddrReg <= dword;
  	    792: tlpDataBramWrAddrReg <= dword;
  	    794: byteSwapReg <= (dword != 0) ? True : False;
  
              // MSIx table entries
              4096: msix_entry[0].addr_lo  <= update_dword(msix_entry[0].addr_lo, be, (dword & 32'hfffffffc));
  