anchor.diff:        Integer intr_num = i+1;
         MSIX_Entry msixEntry = csr.msixEntry[intr_num];
         rule interruptRequest;
  -	 if (portalTop.interrupt[i] && !interruptRequested[i])
  +	 if (ptinterrupt[i] && !interruptRequested[i])
   	    portalEngine.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));
  -	 interruptRequested[i] <= portalTop.interrupt[i];
  +	 interruptRequested[i] <= ptinterrupt[i];
         endrule
      end
  -   interface pins = portalTop.pins;
  +   interface msixEntry = csr.msixEntry;
  +   interface master = portalEngine.master;
  +   interface slave = dmaEngine.slave;
  +   interface interruptRequest = portalEngine.interruptRequest;
   endmodule: mkPcieHost
   
   (* no_default_clock, no_default_reset *)
  
positive.code:    interface ipins       pins;
  endinterface
  
  interface PcieHost#(type ipins);
     interface ipins       pins;
  endinterface
  
  module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId, MkPortalTop#(dsz, ipins) mkPortalTop,
  Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(ipins))
  provisos(
     Mul#(TDiv#(dsz, 8), 8, dsz),
      Add#(a__, TDiv#(dsz, 32), 8),
  
negative.code:    Clock epClock125 = clkgen.clkout0; /* half speed user_clk */
     Reset epReset125 <- mkAsyncReset(4, user_reset_n, epClock125);
  
     MakeResetIfc portalResetIfc <- mkReset(10, False, epClock125, clocked_by epClock125, reset_by epReset125);
     let portalTop <- mkPortalTop(clocked_by epClock125, reset_by portalResetIfc.new_rst);
     PcieHost#(dsz) pciehost <- mkPcieHost(epClock250, epReset250,
           PciId{ bus:  _ep.cfg.bus_number(), dev: _ep.cfg.device_number(), func: _ep.cfg.function_number()},
           //portalTop.slave,
           portalTop.masters,
           portalTop.interrupt,
           portalResetIfc,
           _ep.tlp, clocked_by epClock125, reset_by epReset125);
  
     mkConnection(pciehost.master, portalTop.slave, clocked_by epClock125, reset_by epReset125);
     // going from level to edge-triggered interrupt
     Vector#(15, Reg#(Bool)) interruptRequested <- replicateM(mkReg(False, clocked_by epClock125, reset_by epReset125));
     for (Integer i = 0; i < 15; i = i + 1) begin
        // intr_num 0 for the directory
        Integer intr_num = i+1;
        MSIX_Entry msixEntry = pciehost.msixEntry[intr_num];
  /*
        rule interruptRequest;
  	 if (portalTop.interrupt[i] && !interruptRequested[i])
  	    pciehost.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));
  	 interruptRequested[i] <= portalTop.interrupt[i];
        endrule
  */
     end
  
     interface pcie = _ep.pcie;
     method Bit#(NumLeds) leds();
        return extend({_ep.user.lnk_up(),3'd2});
     endmethod
     interface pins = portalTop.pins;
  endmodule: mkPcieTopFromPortal
  
  (* synthesize *)
  