anchor.diff:     method Action rd_wait_n(Bit#(1) v);
   endinterface
   
  +(* always_ready, always_enabled *)
   interface Par_misc;
  +   method Bit#(1) csysack();
      method Bit#(1) cactive();
  -   method Bit#(1) csysack();
  +   method Action csysreq();
      method Action reset_chip();
      method Action reset_fpga();
   endinterface
   
  +(* always_ready, always_enabled *)
   interface PParallellaLib;
      interface Par_txo txo;
      interface Par_txi txi;
      interface Par_rxo rxo;
      interface Par_rxi rxi;
  -   interface AxiSlaveBits#(32,32,12) maxi;   // this will connect to a master
  -   interface AxiMasterBits#(32,64,6) saxi;  // this will connect to a slave
  +   interface Pps7Saxihp maxi;   // this will connect to a master
  +   interface Pps7Maxigp saxi;  // this will connect to a slave
      interface Par_misc misc;
   endinterface
   
  -import "BVI" PParallella =
  +import "BVI" PParallellaZZZ =
   module mkPParallellaLIB#(Clock maxiclk, Clock saxiclk, 
      Reset maxiclk_reset, Reset saxiclk_reset,
      Reset maxireset, Reset saxireset,
  
positive.code:       method data_n(txo_data_n) enable((*inhigh*) EN_txo_data_n);
        method frame_p(txo_frame_p) enable((*inhigh*) EN_txo_frame_p);
        method frame_n(txo_frame_n) enable((*inhigh*) EN_txo_frame_n);
     endinterface
  
     interface Par_txi txi;
  
negative.code:    method Bit#(1) rd_wait_n();
  endinterface
  
  (* always_ready, always_enabled *)
  interface Par_rxi;
     method Bit#(8) data_p();
     method Bit#(8) data_n();
  