anchor.diff:          Bit#(internalAddrSize) addr = tpl_2(reqTuple);
           Bit#(32) retVal = 0;
           case (truncate(addr))
  -          txDataAddr: retVal = txDataReg;
  -          rxDataAddr: retVal = rxDataReg;
  +          txDataAddr: begin
  +                        retVal = 0
  +                        if (txDataReg matches tagged Valid .x) begin
  +                          retVal = {1'b1, '0, x};
  +                        end
  +                      end
  +          rxDataAddr: begin
  +                        retVal = 0;
  +                        if (rxDataReg matches tagged Valid .x) begin
  +                          retVal = {1'b1, '0, x};
  +                          rxDataReg <= tagged Invalid;
  +                          end
  +                      end
             txCtrlAddr: retVal = txCtrlReg;
             rxCtrlAddr: retVal = rxCtrlReg;
             divAddr:    retVal = divReg;
  
positive.code:     endinterface
    endinterface
  
    method Action put(Bit#(8) data);
      if (txDataReg[31] && txCtrlReg[0]) begin
        txDataReg <= {1, '0, data};
      end
    endmethod
  
    method ActionValue#(Maybe#(Bit#(8))) get;
      Bit#(8) retVal = tagged Invalid;
      if (rxDataReg[31]) begin
        retVal = tagged Valid(rxDataReg[7:0]);
        if (rxCtrlReg[0]) begin
          rxDataReg <= 0;
        end
      end
      return retVal;
    endmethod
  
    method Action rx (Bit#(1) x) = uart.sin;
    method Bit#(1) tx = uart.sout;
    method Bit#(16) divisor = divReg;
    method Vector#(1, Bool) receiveInterrupt = vec(receiveInterrupt);
  
  
negative.code:       method Action put(UncachedMemReq req) if (!isValid(pendingReq[1]));
          if (req.write) begin
            case (truncate(req.addr))
              txDataAddr: begin
                            txDataReg <= tagged Valid(truncate(req.data));
                          end
              rxDataAddr: noAction;
              txCtrlAddr: txCtrlReg  <= req.data;
              rxCtrlAddr: rxCtrlReg  <= req.data;
              divAddr:    divReg     <= req.data;
              default: noAction;
            endcase
            pendingReq[1] <= tagged Valid tuple2(True, truncate(req.addr));
  