anchor.diff:        let tag = compReg1;
         let cli = compReg2;
         compFifo0.enq(cli);
  -      read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}});
  +      read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
         compReg0 <= cnt-1;
      endrule
      
  
positive.code:       interface Put readData;
  	 method Action put(MemData#(dataWidth) response);
  	    readDataPipelineFifo.enq(response);
  	    dreqFifos.portA.request.put(BRAMRequest{write:False, address:truncate(response.tag)});
  	    beatCount <= beatCount+1;
  	 endmethod
        endinterface
  
negative.code:       let cli = drq.client;
        let tag <- toGet(compFifo1).get;
        compFifo0.enq(cli);
        read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        compReg0 <= cnt-1;
        compReg1 <= tag;
        compReg2 <= cli;
  