anchor.diff:  	       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == phase) begin
   		  requestCompleted <= response;
   		  // if status field written by NVME
  +		  let source <- toGet(ioResponseSourceFifo).get();
   `ifdef NVME_ACCELERATOR_INTERFACE
  -		  ioResponseFifo.enq(NvmeIoResponse {});
  +		  if (source == 1)
  +		     ioResponseFifoAccel.enq(NvmeIoResponse {requestId: responseId, statusCode: 'h5a5a, statusCodeType: 'h5a5a });
  +		  else
   `else
  -		  nvmeInd.transferCompleted(responseId, truncate(response), cycles - requestStartTimestamp);
  +		     nvmeInd.transferCompleted(responseId, truncate(response), cycles - requestStartTimestamp);
   `endif
   		  requestInProgress <= False;
   	       end
  
positive.code: 	       let command = v.ctxt;
  	       if (v.last) begin
  		  command.numBlocks = command.numBlocks - v.value; //fixme
  	       end
  	       else begin
  		  command.numBlocks = `BlocksPerRequest;
  	       end
  	       command.startBlock = command.startBlock + extend(v.value);
  	       ioSegmentFifo.enq(command);
  
  	       segmentStartProbe <= truncate(command.startBlock) + v.value;
  	       segmentNumBlocksProbe <= command.numBlocks;
  
negative.code:       while (True) seq
  	 action
  	    let req <- toGet(ioSegmentFifo).get();
  	    let source <- toGet(ioSegmentSourceFifo).get();
  	    Vector#(16,Bit#(32)) command = unpack(0);
  	    command[0] = { requestId, req.flags, req.opcode };
  	    command[1] = 1; // nsid
  