anchor.diff:     rule senddown_oddr;
         let d = gb.first;
         gb.deq();
  -      dac_ddr.d1(d[0]);
  -      dac_ddr.d2(d[1]);
  +      dac_ddr.d1(d[0].data_i[15:2]);
  +      dac_ddr.d2(d[0].data_q[15:2]);
      endrule
   
   
  -   function Bit#(1) foo_p(DiffPair v);
  +   function Bit#(1) foo_p(DiffOut v);
         return (v.read_p());
      endfunction
   
  -   function Bit#(1) foo_n(DiffPair v);
  +   function Bit#(1) foo_n(DiffOut v);
         return (v.read_n());
      endfunction
   
  -   function Bit#(14) get_p(Vector#(14, DiffPair) v);
  +   function Bit#(14) get_p(Vector#(14, DiffOut) v);
         return(pack(map(foo_p, v)));
      endfunction
      
  -   function Bit#(14) get_n(Vector#(14, DiffPair) v);
  +   function Bit#(14) get_n(Vector#(14, DiffOut) v);
         return(pack(map(foo_n, v)));
      endfunction
      
  
positive.code:  * At this point, the data is a 14 bit in-phase data signal, 
   * plus a 14 bit quadrature signal, interleaved
   * 
   * The SDR data is a 32-bit IQ datatype
   * 
   * The 32-bit data is converted from 64-bits by a Gearbox
   * 
  
negative.code: typedef struct {
     Bit#(16) data_i;
     Bit#(16) data_q;
     } OIQ deriving (Bits);
  
  interface FMComms1DAC;
     interface FMComms1DACPins pins;
     interface PipeIn#(Vector#(2, OIQ)) dac;
  endinterface
  
  /* This module drives an Analog Devices FMComms1
  