anchor.diff:      method Action           train9(Bit#(10) v);
       method Action           edgeintor(Bit#(1) v);
       method Bit#(1)          ctrl_bitslip();
  -    method Bit#(1)          ctrl_fifo_reset();
       method Bit#(3)          ctrl_reset_inc_ce();
       method Action           endhandshake(Bit#(1) v);
       method Bit#(1)          starthandshake();
  
positive.code: typedef enum { HIdle, HHigh, HLow} HState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden)(IserdesDatadeser);
  
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
  
negative.code: import Clocks :: *;
  import XilinxCells::*;
  import XbsvXilinxCells::*;
  
  typedef Vector#(10, Reg#(Bit#(10))) TrainRotate;
  
  interface Iserdesbvi;
      method Action           align_start(Bit#(1) v);
  