anchor.diff:          dcounter <= dcounter - 1;
           if (dcounter[2] == 1)
               begin
  -            dackint.send(1);
  +            dackint.enq(1);
               dstate <= DLow;
               end
           sync_reset_inc_ce <= {sync_reset_inc_ce[2], 2'b0};
           sync_bitslip <= 0;
       endrule
       rule clkdivlow_rule if (bvi_reset_reg != 0 && dstate == DLow);
  -        dackint.send(0);
           dstate <= DIdle;
           sync_reset_inc_ce <= {sync_reset_inc_ce[2], 2'b0};
           sync_bitslip <= 0;
  
positive.code:         iserdes_bitslip <= 0;
          iodelay_reset_inc_ce <= 0;
          dstate <= DIdle;
          dackint.send(0);
      endrule
      rule wrensync_rule if (bvi_reset_reg != 0);
          let fwsync = 0;
  
negative.code: 
      SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);
      Vector#(10, SyncBitIfc#(Bit#(1))) iserdes_data <-  replicateM(mkSyncBit(serdes_clock, serdes_reset, defaultClock));
      SyncFIFOIfc#(Bit#(1)) dackint <- mkSyncFIFO(2, serdes_clock, serdes_reset, defaultClock);
  
      Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) ctrl_data <- mkReg(0);
      Reg#(Bit#(10)) ctrl_data_temp <- mkReg(0);
      Reg#(Bit#(10)) data_init <- mkReg(0);
      Reg#(Bit#(10)) edge_init <- mkReg(0);
      Reg#(Bit#(10)) edge_int <- mkReg(0);
      Reg#(HState)  hstate <- mkReg(HIdle);
      Reg#(Bit#(1)) edge_intor_reg <- mkReg(0);
      SyncFIFOIfc#(Bit#(1)) item_req_wire <- mkSyncFIFO(2, defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
  