anchor.diff:  //////
      Clock clock200_buf <- mkClockBUFG(clocked_by clock200);
      IDELAYCTRL idel <- mkIDELAYCTRL(2, clocked_by clock200_buf);
  -
  +/*
      ClockGenerator7AdvParams clockParams = defaultValue;
      clockParams.bandwidth          = "OPTIMIZED";
      clockParams.compensation       = "ZHOLD";
  
positive.code:    ClockGenerator7 clockGen <- mkClockGenerator7Adv(clockParams, clocked_by fmc_imageon_clk1);
     Clock hdmi_clock = clockGen.clkout0;    // 148.5   MHz
     Clock imageon_clock = clockGen.clkout1; //  37.125 MHz
  
      Reset fmc_imageon_reset <- mkAsyncReset(2, defaultReset, fmc_imageon_clk1);
      Reset hdmi_reset <- mkAsyncReset(2, defaultReset, hdmi_clock);
  
negative.code:    //interface ImageonTopPins toppins;
     interface ImageonSerdesPins serpins;
     interface HDMI hdmi;
     //method Bit#(1) i2c_mux_reset_n();
  endinterface
  
  module mkPortalTop#(Clock clock200, Clock fmc_imageon_clk1)(PortalTop#(addrWidth,64,ImageCapturePins));
  