anchor.diff:  
      Gearbox#(BusRatio,1,Bit#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);
      SyncFIFOIfc#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkSyncFIFO(8, clock, reset, ddr3Controller.uiClock);
  -   mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);
  +   //mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);
  +   rule rl_arfifo;
  +      let req <- toGet(arfifo).get();
  +      arAddrProbe <= req.address;
  +      arLenProbe <= req.len;
  +      arSizeProbe <= req.size;
  +      ddr3Controller.slave.req_ar.put(req);
  +   endrule
   
      Reg#(Bit#(Ddr3AddrWidth)) dramReadOffset <- mkReg(0);
      Reg#(Bit#(Ddr3AddrWidth)) dramReadLimit <- mkReg(0);
      rule rl_req_ar if (dramReadOffset < dramReadLimit);
  -      arfifo.enq(Axi4ReadRequest {
  +      Axi4ReadRequest#(Ddr3AddrWidth,6) req = Axi4ReadRequest {
   	 address: truncate(dramReadOffset),
   	 len: 0, // indicates one beat of data
   	 size: axiBusSize(valueOf(Ddr3DataWidth)),
  
positive.code: import AxiDma::*;
  import ConnectalConfig::*;
  import HostInterface::*;
  
  interface Ddr3TestRequest;
     method Action startWriteDram(Bit#(32) sglId);
  
negative.code: 	 cache: 4'b0011, //ignored
  	 lock: 2'b00,    //ignored
  	 qos: 4'b0000    //ignored
  	 };
        awfifo.enq(req);
        aw_req_probe <= req.address;
        dramWriteOffset <= dramWriteOffset + 1;
     endrule
  
  