anchor.diff:        let rsp = DM_CPU_Rsp {ok: True, data: data};
         f_csr_rsps.enq (rsp);
         if (cur_verbosity > 1)
  -	 $display ("%0d: CPU.rl_debug_read_csr: csr %0d => 0x%0h",
  +	 $display ("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h",
   		   mcycle, csr_addr, data);
      endrule
   
  
positive.code:       // Simulation heuristic: finish if trap back to this instr
  `ifndef INCLUDE_GDB_CONTROL
        if (epc == next_pc) begin
  	 $display ("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", mcycle,
  		   next_pc, instr);
  	 fa_report_CPI;
  	 $finish (0);
  
negative.code:    rule rl_stage1_stop (   (rg_state== CPU_RUNNING)
  			&& stage1_stop
  			&& (stageF.out.ostatus != OSTATUS_BUSY));
        if (cur_verbosity > 1) $display ("%0d: %m.rl_stage1_stop", mcycle);
  
        let pc    = stage1.out.data_to_stage2.pc;    // We'll retry this instruction on 'continue'
        let instr = stage1.out.data_to_stage2.instr;
  
        // Report CPI only stop-req, but not on step-req (where it's not very useful)
        if (rg_stop_req) begin
  	 $display ("%0d: %m.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h",
  		   mcycle, minstret, rg_cur_priv, pc, instr);
  	 fa_report_CPI;
        end
        else
  	 $display ("%0d: %m.rl_stage1_stop: Stop after single-step. PC = 0x%08h", mcycle, pc);
  
        DCSR_Cause cause= (rg_stop_req ? DCSR_CAUSE_HALTREQ : DCSR_CAUSE_STEP);
        csr_regfile.write_dcsr_cause_priv (cause, rg_cur_priv);
  