anchor.diff:        method emaxi_wvalid wvalid() clocked_by (maxiclk) reset_by(maxireset);
      endinterface   
      
  -   
  -   
  -   
  -   interface Par_saxi saxi;
  +   interface Pps7Maxigp saxi;
         method araddr(esaxi_araddr) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_araddr);
         method arburst(esaxi_arburst) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_arburst);
         method arcache(esaxi_arcache) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_arcache);
  
positive.code:    input_clock saxiclk(esaxi_aclk) = saxiclk;  // assigns the verilog esaxi_aclk
     input_reset maxiclk_reset() = maxiclk_reset; /* from clock*/
     input_reset saxiclk_reset() = saxiclk_reset; /* from clock*/
     
     interface Par_misc misc;
        method cactive(cactive);
        method csysack(csysack);
        method reset_chip(reset_chip) enable((*inhigh*) EN_reset_chip);
        method reset_fpga(reset_fpga) enable((*inhigh*) EN_reset_fpga);
     endinterface
  
negative.code:    method Action lclk_n(Bit#(1) v);
  endinterface
  
  (* always_ready, always_enabled *)
  interface Par_txi; 
     method Bit#(1) wr_wait_p();
     method Bit#(1) wr_wait_n();
  