anchor.diff:      method Action setNumberOfPixels(Bit#(12) pixels);
           numberOfPixels <= pixels;
       endmethod
  -
  -    interface HDMI hdmi;
  -        method Bit#(1) hdmi_vsync;
  -            return yuv422StageReg.vsync;
  -        endmethod
  -        method Bit#(1) hdmi_hsync;
  -            return yuv422StageReg.hsync;
  -        endmethod
  -        method Bit#(1) hdmi_de;
  -            return yuv422StageReg.de ? 1 : 0;
  -        endmethod
  -        method Bit#(16) hdmi_data;
  -            return yuv422StageReg.data;
  -        endmethod
  -        interface hdmi_clock_if = defaultClock;
  -        interface hdmi_reset_if = defaultReset;
  -    endinterface
  -
   endmodule
  + 
   module mkHdmiOut(HdmiOut);
  -
       Clock defaultClock <- exposeCurrentClock();
       Reset defaultReset <- exposeCurrentReset();
  -    Wire#(Rgb888Stage) rgb888StageWire <- mkDWire(unpack(0));
  -    Reg#(Yuv444IntermediatesStage) yuv444IntermediatesStageReg <- mkReg(Yuv444IntermediatesStage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
  -    Reg#(Yuv444Stage) yuv444StageReg <- mkReg(Yuv444Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
  -    Reg#(Yuv422Stage) yuv422StageReg <- mkReg(Yuv422Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
  +    Reg#(Rgb888Stage) rgb888StageReg <- mkReg(unpack(0));
  +    Reg#(Yuv444IntermediatesStage) yuv444IntermediatesStageReg <- mkReg(
  +        Yuv444IntermediatesStage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
  +    Reg#(Yuv444Stage) yuv444StageReg <- mkReg(
  +        Yuv444Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
  +    Reg#(Yuv422Stage) yuv422StageReg <- mkReg(
  +        Yuv422Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
       Reg#(Bool) evenOddPixelReg <- mkReg(False);
   
       rule yuv444IntermediatesStage;
  -        let previous = rgb888StageWire;
  +        let previous = rgb888StageReg;
           let pixel = previous.pixel;
           yuv444IntermediatesStageReg <= Yuv444IntermediatesStage {
               vsync: previous.vsync,
  
positive.code:         else if (dataEnable)
              dataCount <= dataCount + 1;
  
          bramOutStageFifo.enq(Rgb888Stage { vsync: vsync, hsync: hsync, de: dataEnable, dataCount: dataCount });
          lineBuffer.readAddr(dataCount);
  
      endrule
  
      rule bramOutStage;
          let d <- lineBuffer.readData;
  
negative.code: 
  import YUV::*;
  import NrccSyncBRAM::*;
  
  interface HDMI;
      method Bit#(1) hdmi_vsync;
  