anchor.diff:      interface Clock rxuserclk2;
       interface Clock userclk;
       interface Clock userclk2;
  +    interface Reset pma_reset_out;
   endinterface
   import "BVI" axi_ethernet_0 =
   module mkAxiEthBvi#(Clock ref_clk, Clock s_axi_clk, Reset s_axi_reset, Clock axis_clk,
  
positive.code:    output_clock rxuserclk2(rxuserclk2_out);
     output_clock userclk(userclk_out);
     output_clock userclk2(userclk2_out);
      interface AxiethbviGt     gt0;
          method gt0_qplloutclk_out qplloutclk_out();
          method gt0_qplloutrefclk_out qplloutrefclk_out();
  
negative.code: (* always_ready, always_enabled *)
  interface AxiethbviMmcm;
      method Bit#(1)     locked_out();
  endinterface
  (* always_ready, always_enabled *)
  interface AxiethbviS_axi;
  