anchor.diff:                                                  tag: truncate(tag)
                                                   });
            endmethod
  +         method Action objTransferFromFpga(Bit#(8) id, Bit#(32) objId);
  +            if (id < 4) writeObjs[channel][id] <= objId;
  +         endmethod
            endinterface);
      endfunction
      function PipeIn#(Bit#(dsz)) writeServerData(MemWriteEngineServer#(dsz) s); return s.data; endfunction
  
positive.code:    Vector#(numChannels, FIFO#(Bit#(EtherLen))) ringToDmaLen <- replicateM(mkFIFO(clocked_by txClock, reset_by txReset));
     Vector#(numChannels, FIFO#(EtherReq)) ringToDmaReq <- replicateM(mkFIFO(clocked_by txClock, reset_by txReset));
     Vector#(numChannels, SyncFIFOIfc#(Bit#(32)))   writeLens <- replicateM(mkSyncFIFO(valueOf(NumOutstandingRequests), txClock, txReset, defaultClock));
  
     Reg#(Bit#(BurstLenSize)) writeRequestSizeReg <- mkReg(64);
     Reg#(Bit#(BurstLenSize)) readRequestSizeReg <- mkReg(256);
  
negative.code:          toPut(we.writeServers[channel].data).put(v.data);
           if (v.sop) begin     // parallalize dma
              let pktLen = findNearestMultiple(writeLens[channel].first, 16);
              let vec = writeObjs[channel];
              let idx = writeObjsCurIdx[channel];
              writeCmds[channel].enq(MemengineCmd {sglId:truncate(vec[idx]),   // TODO
              //writeCmds[channel].enq(MemengineCmd {sglId:0,   // TODO
                          base:0, 
                          burstLen: extend(writeRequestSizeReg),
                          len: pktLen,
                          tag:0
                          });
              writeLens[channel].deq;
              writeObjsCurIdx[channel] <= (writeObjsCurIdx[channel] + 1) & 'h3;
           end
        endrule
        rule transferFromFpgaReqRule (!writeProcessing);
  