anchor.diff:        dataFifo.enq(md);
      endrule
   
  +   rule rl_wr_done;
  +      let tag <- toGet(doneFifo).get();
  +      if (traceDonePipe.notFull())
  +	 traceDonePipe.enq(tuple2(chan, cycles));
  +      m.writeDone.put(tag);
  +   endrule
  +
      interface Get writeReq = toGet(reqFifo);
      interface Get writeData = toGet(dataFifo);
  -   interface Put writeDone = m.writeDone;
  +   interface Put writeDone = toPut(doneFifo);
   endmodule
  
positive.code: 
  module mkTraceWriteClient#(PipeIn#(Tuple4#(dmaChanId,Bool,MemRequest,Bit#(timeStampWidth))) tracePipe,
  			   PipeIn#(Tuple4#(dmaChanId,Bool,MemData#(dataWidth),Bit#(timeStampWidth))) traceDataPipe,
  			   dmaChanId chan, MemWriteClient#(dataWidth) m)
     (MemWriteClient#(dataWidth));
  
  
negative.code: 
     let reqFifo <- mkFIFOF();
     let dataFifo <- mkFIFOF();
     let doneFifo <- mkFIFOF();
  
     rule rl_wr_req;
        let mr <- m.writeReq.get();
  