anchor.diff:  import BRAMCore::*;
   import SMul::*;
   import ARAM::*;
  -
  +import Utils::*;
  +
  +// Internal ROM Table
   Integer g_t32[32][16] =
   {
       { 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64 },
  
positive.code:       colCnt <= colCnt + 1;
     endrule
  
     rule do_2D;
        let x = fifo_col.first;
  
        if (False) begin
  
negative.code:    Wire#(Bit#(1)) w_syncCol <- mkDWire(0);
     Reg#(Bit#(2)) syncCol <- mkReg(0);
     FIFOF#(Vector#(32, Bit#(17))) fifo_col <- mkPipelineFIFOF;        // [E[0..15] O[0..15]]
     RWire#(Tuple3#(Bit#(2), Bit#(9), Vector#(32, Bit#(16)))) wr_1D <- mkRWire;
  
  
     rule write_bram_1D(wr_1D.wget matches tagged Valid .x);
        let sz  = tpl_1(x);
        let idx = tpl_2(x);
        let dat = tpl_3(x);
  
        case(sz)
           0: begin
             mem[{idx[0], 3'd0}].write(0, {dat[ 5], dat[ 4], dat[ 1], dat[ 0]});
             mem[{idx[0], 3'd1}].write(0, {dat[ 7], dat[ 6], dat[ 3], dat[ 2]});
             mem[{idx[0], 3'd2}].write(0, {dat[13], dat[12], dat[ 9], dat[ 8]});
             mem[{idx[0], 3'd3}].write(0, {dat[15], dat[14], dat[10], dat[11]});
             mem[{idx[0], 3'd4}].write(0, {dat[21], dat[20], dat[17], dat[16]});
             mem[{idx[0], 3'd5}].write(0, {dat[23], dat[22], dat[19], dat[18]});
             mem[{idx[0], 3'd6}].write(0, {dat[29], dat[28], dat[25], dat[24]});
             mem[{idx[0], 3'd7}].write(0, {dat[31], dat[30], dat[27], dat[26]});
           end
  
           1: begin
             mem[{idx[1:0], 2'd0}].write(0, {dat[ 3], dat[ 2], dat[ 1], dat[ 0]});
             mem[{idx[1:0], 2'd1}].write(0, {dat[ 7], dat[ 6], dat[ 5], dat[ 4]});
             mem[{idx[1:0], 2'd2}].write(0, {dat[11], dat[10], dat[ 9], dat[ 8]});
             mem[{idx[1:0], 2'd3}].write(0, {dat[15], dat[14], dat[13], dat[12]});
           end
  
           2: begin
             mem[{idx[2:0], 1'd0}].write({2'd0, idx[5:3]}, {dat[ 3], dat[ 2], dat[ 1], dat[ 0]});
             mem[{idx[2:0], 1'd1}].write({2'd0, idx[5:3]}, {dat[ 7], dat[ 6], dat[ 5], dat[ 4]});
           end
  
           default: begin
              mem[idx[7:4]].write({idx[8],idx[3:0]}, pack(take(dat)));
              $display("[%6d] (%2d,%2d) %04X, %04X, %04X, %04X", cycles, idx[7:4], idx[3:0], dat[0], dat[1], dat[2], dat[3]);
           end
        endcase
     endrule
  
  
     rule do_dct_1D(fifo_in.notEmpty);
        let x = fifo_in.first;
  
        /*
  