anchor.diff:              fwsync = dfifo_wren_r;
           else
               fwsync = bvi_fifo_wren_wire;
  -        fifo_wren_sync <= fwsync;
  +        fifo_wren_sync.send(fwsync);
           iodelay_reset_inc_ce <= sync_reset_inc_ce;
       endrule
       rule wren_dfifo_rule;
  -        dfifo.wren(fifo_wren_sync);
  +        dfifo.wren(fifo_wren_sync.read());
       endrule
   
       rule clkdiv_rule if (bvi_reset_reg != 0);
  
positive.code:     endrule
  
      rule serdesdata_rule;
          let dout = 10'b0;
          master_data.d(0);
          master_data.bitslip(iserdes_bitslip);
          master_data.ce1(1);
  
negative.code:         sync_reset_inc_ce <= sric;
          sync_bitslip <= sbs;
      endrule
      rule state1_rule if (bvi_reset_reg != 0 && dstate == DValid && dcounter[2] == 1);
          dackint.send(1);
      endrule
      rule state2_rule if (bvi_reset_reg != 0 && dstate == DLow && dreqpipe1 == 0);
          dackint.send(0);
      endrule
  
      rule setrule;
  