anchor.diff:     (* descending_urgency = "rl_probe_and_immed_rsp, rl_writeback_updated_PTE" *)
   `endif
   
  -   rule rl_probe_and_immed_rsp (rg_state == MODULE_RUNNING);
  +   rule rl_probe_and_immed_rsp ((rg_state == MODULE_RUNNING) && (! load_stall));
  +
         // Print some initial information for debugging
         if (cfg_verbosity > 1) begin
   	 $display ("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", cur_cycle, d_or_i, rg_addr);
  
positive.code:    endrule
  
     // ----------------------------------------------------------------
     // This rule probes the MMU and provides an immediate response for
     // memory (non-IO) requests, if possible, i.e., if
     //     VM off, LD or AMO_LR, cache hit
  
negative.code:    // Memory-mapped I/O read requests (LD and AMO_LR)
     // LRs are treated just like LDs, but we do not place any reservation on the address
     // (so a subsequent SC is guaranteed to fail).
     // TODO: Move this into rl_probe_and_immed_rsp, post MMU translation?
     // No caching, send request directly to fabric
  
     rule rl_io_read_req (   (rg_state == IO_REQ)
  			&& ((rg_op == CACHE_LD) || is_AMO_LR)
  			&& (ctr_wr_rsps_pending.value == 0));
  
        if (cfg_verbosity > 1)
  	 $display ("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
  