anchor.diff:        interface Put readData = toPut(rfifo);
      endmodule
   
  -   module mkMemWriteClient#(GetObjId objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));
  +   module mkMemWriteClient#(GetObjId#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));
   
         Wire#(Bit#(1)) awready <- mkDWire(0);
         Wire#(Bit#(1)) wready <- mkDWire(0);
  
positive.code:       rule rl_awaddr if (m.awvalid() == 1);
  	 let addr = m.awaddr();
  	 let burstLenBytes = (extend(m.awlen())+1)*fromInteger(valueOf(TDiv#(dataWidth,8)));
  	 awfifo.enq(MemRequest { sglId: objId.objId(addr), offset: extend(addr), burstLen: burstLenBytes, tag: extend(m.awid()) });
        endrule
        rule handshake_awaddr;
  	 m.awready(pack(awfifo.notFull()));
  
negative.code:    endmodule
  endinstance
  
  interface GetObjId#(numeric type addrWidth);
     method SGLId objId(Bit#(addrWidth) axiAddr);
     method Bit#(MemOffsetSize) addr(Bit#(addrWidth) axiAddr);
  endinterface
  instance AxiToMemReadClient#(GetObjId#(32),32,dataWidth);
     module mkMemReadClient#(GetObjId#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemReadClient#(dataWidth));
  
        Wire#(Bit#(1)) arready <- mkDWire(0);
        Wire#(Bit#(1)) rvalid <- mkDWire(0);
  