anchor.diff:        readTagFifo.enq(tag);
         readLastFifo.enq(addrBeat.last);
         Bit#(bramAddrWidth) regFileAddr = truncate(addr << fromInteger(valueOf(TLog#(dataWidthBytes))));
  -      br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:regFileAddr, datain:?});
  +      req_addr.enq(regFileAddr);
         if (verbose) $display("%d read_server.readData (a) %h %d last=%d", cycles, addr, burstCount, addrBeat.last);
  +   endrule
  +
  +   rule read_bram_req;
  +      let addr <- toGet(req_addr).get;
  +      br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:addr, datain:?});
  +   endrule
  +
  +   rule req_aw;
  +      let req <- toGet(req_aws).get;
  +      br.request.put(req);
      endrule
   
      interface PhysMemReadServer read_server;
  
positive.code:            ,Mul#(dataWidthBytes, 8, busDataWidth)
             ,Div#(busDataWidth, 8, dataWidthBytes)
             );
  
     FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();
     FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();
  
negative.code: 
     AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
  
     FIFO#(PhysMemRequest#(busAddrWidth, busDataWidth)) req_ars <- mkFIFO1;
     FIFO#(Bit#(bramAddrWidth)) req_addr <- mkFIFO1;
     FIFO#(BRAMRequestBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), dataWidthBytes)) req_aws <- mkFIFO1;
  
     Reg#(Bit#(32)) cycles      <- mkReg(0);
     rule count if (verbose);
        cycles <= cycles + 1;
     endrule
  
     rule req_ar;
       let req <- toGet(req_ars).get;
       readAddrGenerator.request.put(req);
     endrule
  
     rule read_req;
        let addrBeat <- readAddrGenerator.addrBeat.get();
  