anchor.diff:  
       rule qfsmall;
           let abusy = pack(qstate != QIdle);
  -        dfifo_reset_r.send(abusy);
  +        fifo_reset_sync.send(abusy);
           this_align_busy_wire <= abusy;
           samplein_reset_null.send(ctrl_sample[2]);
       endrule
  
positive.code: import Vector::*;
  import Clocks :: *;
  import FIFO::*;
  import XilinxCells::*;
  import XbsvXilinxCells::*;
  
  
negative.code:     //*************************** serdes setting FSM *****************
      rule serdes_idle_rule if (bvi_reset_reg != 0 && serdes_running == 0);
          serdes_setting.deq();
          //Bit#(3) sric = 0;
          //for (Integer i = 0; i < 3; i = i + 1)
              //sric[i] = serdes_reset_inc_ce[i].read();
          sync_reset_inc_ce <= serdes_reset_inc_ce.read();
          sync_bitslip <= serdes_bitslip.read();
          serdes_running <= 1;
          dcounter <= 3;
  