anchor.diff:         pclk_sel <= ps;
      endrule
   
  +   FIFOF#(RegChange) changeFifo <- mkFIFOF(); //mkSizedBRAMFIFOF(128, clocked_by user_clk, reset_by user_reset_n);
  +
      let txready = (pcie_ep.s_axis_tx.tready != 0 && fAxiTx.notEmpty);
   
      //(* fire_when_enabled, no_implicit_conditions *)
  
positive.code: import PCIEWRAPPER       ::*;
  import Bufgctrl           ::*;
  import PcieGearbox       :: *;
  
  `include "ConnectalProjectConfig.bsv"
  
  
negative.code:    interface PciewrapUser#(lanes)      user;
     interface PciewrapCfg#(lanes)       cfg;
     interface Server#(TLPData#(16), TLPData#(16)) tlp;
     interface PipeOut#(Bit#(64)) regChanges;
     interface Clock epPcieClock;
     interface Reset epPcieReset;
     interface Clock epPortalClock;
  