anchor.diff:              begin
               gencounter <= 8;
               as = AAlign;
  -            serdes_bitslip.send(1);
               serdes_start.enq(0);
               end
           astate <= as;
  
positive.code:             else
                  begin
                  gencounter <= gencounter - 1;
                  serdes_bitslip.send(1);
                  serdes_start.enq(0);
                  end
              end
          astate <= as;
      endrule
      rule afsmdone_rule if (bvi_resets_reg.read() != 0 && astate == ADone);
          serdes_bitslip.send(0);
          astate <= AIdle;
      endrule
  
  
negative.code:     Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      SyncBitIfc#(Bit#(1)) fifo_reset_sync <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      SyncBitIfc#(Bit#(1)) astate_idle <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      SyncBitIfc#(Bit#(1)) astate_bitslip <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(2)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
  