anchor.diff:  import AxiCsr            :: *;
   
   import BRAM         :: *;
  -//import BRAMFIFO     :: *;
   
   typedef (function Module#(PortalTop#(40, dsz, ipins,nMasters)) mkPortalTop()) MkPortalTop#(numeric type dsz, type ipins, numeric type nMasters);
   
  
positive.code:    method Bit#(NumLeds) leds();
     interface ipins       pins;
  endinterface
  
  (* no_default_clock, no_default_reset *)
  module [Module] mkPcieTopFromPortal #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
  
negative.code:    Clock epClock125 = clkgen.clkout0; /* half speed user_clk */
     Reset epReset125 <- mkAsyncReset(4, user_reset_n, epClock125);
  
     PcieHost#(ipins) pciehost <- mkPcieHost(epClock250, epReset250,
           PciId{ bus:  _ep.cfg.bus_number(), dev: _ep.cfg.device_number(), func: _ep.cfg.function_number()},
           mkPortalTop, _ep.tlp, clocked_by epClock125, reset_by epReset125);
  
     interface pcie = _ep.pcie;
     method Bit#(NumLeds) leds();
        return extend({_ep.user.lnk_up(),3'd2});
     endmethod
     interface pins = pciehost.pins;
  
  endmodule: mkPcieTopFromPortal
  
  