anchor.diff:     endfunction
   endinstance
   
  -instance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(16,32), AprpS_axi_ctl);
  -   function Axi4SlaveLiteBits#(16,32) toAxi4SlaveBits(AprpS_axi_ctl s);
  -      return (interface Axi4SlaveLiteBits#(16,32);
  +instance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(32,32), AprpS_axi_ctl);
  +   function Axi4SlaveLiteBits#(32,32) toAxi4SlaveBits(AprpS_axi_ctl s);
  +      return (interface Axi4SlaveLiteBits#(32,32);
   	 method araddr = compose(s.araddr, extend);
   	 method arready = s.arready;
   	 method arvalid = s.arvalid;
  
positive.code: 
  
     FIFOF#(Bit#(32)) dfifoCtl <- mkFIFOF();
     Axi4SlaveBits#(16,64,4,Empty) axiRootPortSlave    = toAxi4SlaveBits(axiRootPort.s_axi);
     Axi4SlaveLiteBits#(16,32)     axiRootPortSlaveCtl = toAxi4SlaveBits(axiRootPort.s_axi_ctl);
     PhysMemSlave#(16,64)          axiRootPortMemSlave    <- mkPhysMemSlave(axiRootPortSlave, clocked_by axiClock, reset_by axiReset);
     PhysMemSlave#(16,32)          axiRootPortMemSlaveCtl <- mkPhysMemSlave(axiRootPortSlaveCtl, clocked_by axiCtlClock, reset_by axiCtlReset);
  
     FIFOF#(PhysMemRequest#(16,64)) araddrFifo <- mkDualClockBramFIFOF(clock, reset, axiClock, axiReset);
     FIFOF#(PhysMemRequest#(16,64)) awaddrFifo <- mkDualClockBramFIFOF(clock, reset, axiClock, axiReset);
     FIFOF#(MemData#(64))           rdataFifo <- mkDualClockBramFIFOF(axiClock, axiReset, clock, reset);
     FIFOF#(MemData#(64))           wdataFifo <- mkDualClockBramFIFOF(clock, reset, axiClock, axiReset);
     FIFOF#(Bit#(6))                doneFifo <- mkDualClockBramFIFOF(axiClock, axiReset, clock, reset);
  
negative.code:    let axiReset <- mkSyncReset(10, reset, axiClock);
     let axiCtlReset <- mkSyncReset(10, reset, axiCtlClock);
  
     let axiRootPort <- mkAPRP(pcie_clk_100mhz_buf, reset, axiClock, axiReset, axiCtlClock, axiCtlReset);
     let axiClockC2B <- mkC2B(axiRootPort.axi.aclk_out);
     let axiCtlClockC2B <- mkC2B(axiRootPort.axi.ctl_aclk_out);
     rule rl_connect_clocks;
  