anchor.diff:        wAxiTxData  <= info.data;
         wAxiTxKeep  <= info.keep;
      endrule
  -   
  +
      (* fire_when_enabled, no_implicit_conditions *)
      rule drive_axi_rx_ready;
         pcie_ep.m_axis_rx.tready(pack(fAxiRx.notFull));
      endrule
  -   
  +
      (* fire_when_enabled *)
      rule sink_axi_rx if (pcie_ep.m_axis_rx.tvalid != 0);
         let info = AxiRx {
  
positive.code:    clockParams.clkin_buffer = False;
     clockParams.clkout0_buffer = True;
     clockParams.clkout2_buffer = True;
     XClockGenerator7 clockGen <- mkClockGenerator7Adv(clockParams, clocked_by b2c.c); //mmcm_i ( .RST(1'b0)
     C2B c2b_fb <- mkC2B(clockGen.clkfbout, clocked_by clockGen.clkfbout);
     rule txoutrule5;
        clockGen.clkfbin(c2b_fb.o());
     endrule
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
     Reset rst0 <- mkAsyncReset(2, defaultReset, clockGen.clkout0);
     Reset rst1 <- mkAsyncReset(2, defaultReset, clockGen.clkout1);
     Bufgctrl bbufc <- mkBufgctrl(clockGen.clkout0, defaultReset, clockGen.clkout1, defaultReset);
     Reset rsto <- mkAsyncReset(2, defaultReset, bbufc.o);
  
     Reg#(Bit#(1)) pclk_sel <- mkReg(0, clocked_by bbufc.o, reset_by rsto);
     Reg#(Bit#(lanes)) pclk_sel_reg1 <- mkReg(0, clocked_by bbufc.o, reset_by rsto);
     Reg#(Bit#(lanes)) pclk_sel_reg2 <- mkReg(0, clocked_by bbufc.o, reset_by rsto);
     rule bufcruleinit;
        bbufc.ce0(1);
        bbufc.ce1(1);
  
negative.code:    rule others;
        pcie_ep.fc.sel(0 /*RECEIVE_BUFFER_AVAILABLE_SPACE*/);
     endrule
  
     (* fire_when_enabled, no_implicit_conditions *)
     rule drive_axi_tx;
        pcie_ep.s_axis_tx.tuser({ wDiscontinue, wCutThrough, wErrFwd, wEcrcGen });
  