anchor.diff:     interface Clock tsys_clk_200mhz_buf = sys_clk_200mhz_buf;
      interface Clock tpci_clk_100mhz_buf = pci_clk_100mhz_buf;
      interface PcieEndpointX7 tep7 = ep7;
  -`endif
      interface Clock tepClock125 = epClock125;
      interface Reset tepReset125 = epReset125;
      interface PcieHost tpciehost = pciehost;
  
positive.code: `endif
  endmodule
  		 
  		 
negative.code: `endif
  endinterface
  
  
  `ifdef BSIM
  module mkPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pci_sys_reset_n)(PcieHostTop);
     let dc <- exposeCurrentClock;
     let dr <- exposeCurrentReset;
     Clock epClock125 = dc;
  