anchor.diff:     end
   
      rule idle if (state == Idle);
  -      state <= MessageHeader;
  -      stateProbe <= MessageHeader;
  -   endrule
  -
  -   rule sendHeader if (state == MessageHeader && interruptStatus);
  -      Bit#(32) hdr <- toGet(inputFifos[readyChannel]).get();
  +      readyChannelReg <= readyChannel;
  +      interruptStatusReg <= interruptStatus;
  +      SerialPortalState nextState = Idle;
  +      if (interruptStatus)
  +	 nextState = MessageHeader;
  +
  +      state <= nextState;
  +      stateProbe <= nextState;
  +   endrule
  +
  +   rule sendHeader if (state == MessageHeader && interruptStatusReg);
  +      Bit#(32) hdr <- toGet(inputFifos[readyChannelReg]).get();
         Bit#(16) totalWords = hdr[15:0];
         let messageWords = totalWords-1;
         messageWordsProbe <= messageWords;
   
         messageWordsReg <= messageWords;
  -      methodIdReg <= readyChannel;
         outputFifo.enq(hdr);
         state <= MessageBody;
         stateProbe <= MessageBody;
  
positive.code: 
     rule sendMessage if (state == MessageBody);
        messageWordsReg <= messageWordsReg - 1;
        let v <- toGet(inputFifos[methodIdReg]).get();
        outputFifo.enq(v);
        $display("sendMessage v=%h messageWords=%d paddingReg=%d", v, messageWordsReg, paddingReg);
        if (messageWordsReg == 1) begin
           state <= MessageHeader;
  	 stateProbe <= MessageHeader;
        end
        messageDataProbe <= v;
     endrule
  
negative.code:    let clock <- exposeCurrentClock;
     let reset <- exposeCurrentReset;
     Reg#(Bit#(16)) messageWordsReg <- mkReg(0);
     Reg#(Bit#(16)) readyChannelReg <- mkReg(0);
     Reg#(Bool)     interruptStatusReg <- mkReg(False);
     Reg#(Bool) paddingReg <- mkReg(False);
     Reg#(SerialPortalState) state <- mkReg(Idle);
     Reg#(Bit#(32)) sglIdReg <- mkReg(0);
  