anchor.diff:  
   //(* synthesize *)
   module mkMemInterrupt#(PciId my_id)(MemInterrupt);
  -    FIFOF#(Tuple2#(Bit#(64),Bit#(32))) interruptRequestFifo <- mkSizedFIFOF(16);
  +    FIFOF#(Tuple4#(Bit#(64),Bit#(32),Bool,Bool)) interruptRequestFifo <- mkFIFOF();
       Reg#(Maybe#(Bit#(32))) interruptSecondHalf <- mkReg(tagged Invalid);
       Reg#(TLPTag) tlpTag <- mkReg(0);
       FIFOF#(TLPData#(16)) tlpOutFifo <- mkSizedFIFOF(8);
  
positive.code:     endinterface: tlp
      interface Put interruptRequest;
         method Action put(Tuple2#(Bit#(64),Bit#(32)) intr);
            interruptRequestFifo.enq(intr);
         endmethod
      endinterface
  endmodule: mkMemInterrupt
  
negative.code:        let interruptRequested = True;
         let sendInterrupt = False;
  
         match { .interruptAddr, .interruptData, .mswIsZero, .lswIsZero } = interruptRequestFifo.first;
         if (mswIsZero && lswIsZero) begin
  	  // do not write to 0 -- it wedges the host
  	  interruptRequested = False;
         end
         else if (mswIsZero) begin
            TLPMemoryIO3DWHeader hdr_3dw = defaultValue();
            hdr_3dw.format = MEM_WRITE_3DW_DATA;
  	  //hdr_3dw.pkttype = MEM_READ_WRITE;
  