anchor.diff:     endrule
   endmodule
   
  +`ifdef SUPPORT_PCIE
   (* no_default_clock, no_default_reset *)
   module mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
                             Clock sys_clk_p,     Clock sys_clk_n,
  
positive.code: import Leds::*;
  
  // for PCIE
  import Xilinx            :: *;
  import XilinxPCIE        :: *;
  import Xilinx7PcieBridge :: *;
  import PcieToAxiBridge   :: *;
  
  
  // generated by tool
  
negative.code: 			     });
  
  endmodule: mkPcieTop
  `endif
  