anchor.diff:     `define AVALON
   `endif
   
  -typedef 32 WriteDataMimoSize;
  +typedef 64 WriteDataMimoSize;
  +typedef TAdd#(1,TLog#(WriteDataMimoSize)) WriteDataBurstLenSize;
   module mkMemSlaveEngine#(PciId my_id)(MemSlaveEngine#(buswidth))
      provisos (Div#(buswidth, 8, busWidthBytes),
   	     Div#(buswidth, 32, busWidthWords),
  
positive.code:    interface PhysMemWriteServer write_server; 
        interface Put writeReq;
           method Action put(PhysMemRequest#(40) req); // if (writeBurstCount == 0);
  	    let burstLen = req.burstLen >> beat_shift;
  	    let addr = req.addr;
  	    let awid = req.tag;
  	    let writeIs3dw = False;
  
negative.code:    endrule
  
     Reg#(Bool) writeDataCntAboveThreshold <- mkReg(False);
     Reg#(Bool) writeDataMimoHasRoom <- mkReg(False);
     rule updateWriteDataMimoHasRoom;
        writeDataMimoHasRoom <= (writeDataCnt.read <= fromInteger(valueOf(WriteDataMimoSize) - valueOf(busWidthWords)));
     endrule
     rule noheader if (!tlpWriteHeaderFifo.notEmpty());
        writeDataCntAboveThreshold <= False;
     endrule
  