anchor.diff:         let resp <- m.resp_write.get();
          s.resp_write.put(resp);
          bscan_fifos[3].enq(
  -           {3'h4, interrupt_bit, 6'h0, resp.id[5:0], 
  -`ifdef AXI_WRITE_TIMING
  -	    seqCounter,
  -`else
  -	    resp.last, resp.byteEnable[3:0], 11'b0, 
  +           {3'h4, interrupt_bit, 6'h0, resp.id[5:0],
  +`ifdef AXI_WRITE_TIMING
  +	    seqCounter,
  +`else
  +	    resp.last, resp.byteEnable[3:0], 11'b0,
   `endif
   	    resp.data[31:0]});
      endrule
  
positive.code:        let req <- m.req_aw.get();
         s.req_aw.put(req);
         bscan_fifos[2].enq(
             {3'h3, interrupt_bit, 6'h0, req.id[5:0], 
  `ifdef AXI_WRITE_TIMING
  	    seqCounter,
  `else	    
  	    req.len, req.cache, req.prot, req.size,
  	    pack(req.burst == 2'b01), pack(req.lock == 0 && req.qos == 0), 
  `endif
  	    req.address});
     endrule
  
negative.code: `ifndef TRACE_AXI
     mkConnection(m, s);
  `else
  
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
     Reg#(Bit#(`TRACE_ADDR_WIDTH)) addrReg <- mkReg(9);
  