anchor.diff:     Reg#(Bool) traceTransfers <- mkReg(False);
      rule notransfer if (referenceReg matches tagged Invalid);
         vsyncFifo.deq();
  +   endrule
  +   rule resetfiforule if (vsyncPulse.pulse());
  +      fifo_reset.assertReset();
      endrule
      rule startTransfer if (vsyncPulse.pulse() &&& referenceReg matches tagged Valid .reference);
         memreadEngine.readServers[0].request.put(MemengineCmd{pointer:reference, base:0, len:pack(extend(byteCountReg)), burstLen:64});
  
positive.code: 
      HdmiGenerator#(Rgb888) hdmiGen <- mkHdmiGenerator(defaultClock, defaultReset,
  							vsyncPulse, hdmiInternalIndication, clocked_by hdmi_clock, reset_by hdmi_reset);
  `ifndef ZC706
     Rgb888ToYyuv converter <- mkRgb888ToYyuv(clocked_by hdmi_clock, reset_by hdmi_reset);
     mkConnection(hdmiGen.rgb888, converter.rgb888);
     HDMI#(Bit#(HdmiBits)) hdmisignals <- mkHDMI(converter.yyuv, clocked_by hdmi_clock, reset_by hdmi_reset);
  `else
  
negative.code:    endrule
  `endif
  
     SyncFIFOIfc#(Bit#(64)) synchronizer <- mkSyncBRAMFIFO(1024, defaultClock, fifo_reset.new_rst, hdmi_clock, fifo_reset_hdmi);
     rule fromMemread;
        let v <- toGet(memreadEngine.dataPipes[0]).get;
        synchronizer.enq(v);
  