anchor.diff:     Reg#(Bool)     readyReg   <- mkReg(False);
      MIMOConfiguration mimoConfig = defaultValue;
      MIMO#(2,1,2,Bit#(32)) readMimo <- mkMIMO(mimoConfig);
  -   FIFOF#(Bit#(32)) dataFifo <- mkSizedFIFOF(32);
  +   Vector#(pipeCount, FIFOF#(Bit#(32))) dataFifo <- replicateM(mkFIFOF);
   
      let verbose = True;
   
  -   rule updateReqHeadTail if (state == Idle && readyReg);
  -      if (verbose) $display("updateReqHeadTail");
  +   rule updateReqWrPtrRdPtr if (state == Idle && readyReg);
  +      if (verbose) $display("updateReqWrPtrRdPtr");
         readEngine[0].request.put(
             MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});
  -      state <= HeadRequested;
  -   endrule
  -
  -   rule receiveReqHeadTail if (state == HeadRequested || state == TailRequested);
  +      state <= WrPtrRequested;
  +   endrule
  +
  +   rule receiveReqWrPtrRdPtr if (state == WrPtrRequested || state == RdPtrRequested);
         let v <- toGet(readEngine[0].data).get();
         let w0 = v.data[31:0];
         let w1 = v.data[63:32];
  -      let head = headReg;
  -      let tail = tailReg;
  +      let wrPtr = wrPtrReg;
  +      let rdPtr = rdPtrReg;
         let limit = limitReg;
  -      if (state == HeadRequested) begin
  +      if (state == WrPtrRequested) begin
   	 limit = w0;
            limitReg <= w0;
  -         headReg <= w1;
  -         head = w1;
  -         state <= TailRequested;
  +         wrPtrReg <= w1;
  +         wrPtr = w1;
  +         state <= RdPtrRequested;
         end
         else begin
  -         if (tailReg == 0) begin
  -            tail = w0;
  -            tailReg <= tail;
  +         if (rdPtrReg == 0) begin
  +            rdPtr = w0;
  +            rdPtrReg <= rdPtr;
            end
  -         if (tail != headReg)
  +         if (rdPtr != wrPtrReg)
               state <= RequestMessage;
            else
               state <= Idle;
         end
         if (verbose)
  -         $display("receiveReqHeadTail state=%d w0=%x w1=%x head=%d tail=%d limit=%d", state, w0, w1, head, tail, limit);
  +         $display("receiveReqWrPtrRdPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limit);
      endrule
   
      rule requestMessage if (state == RequestMessage);
  -      Bit#(32) wordCount = headReg - tailReg;
  -      if ((tailReg & 1) == 1) begin
  -         $display("WARNING requestMessage: reqTail=%d is odd.", tailReg);
  -      end
  -      let tail = tailReg + wordCount;
  -      if (headReg < tailReg) begin
  -         $display("requestMessage wrapped: head=%d tail=%d", headReg, tailReg);
  -         wordCount = limitReg - tailReg;
  -         tail = 4;
  -      end
  -      if (verbose) $display("requestMessage id=%d tail=%h head=%h wordCount=%d", sglIdReg, tailReg, headReg, wordCount);
  -      tailReg <= tail;
  +      Bit#(32) wordCount = wrPtrReg - rdPtrReg;
  +      if ((rdPtrReg & 1) == 1) begin
  +         $display("WARNING requestMessage: reqRdPtr=%d is odd.", rdPtrReg);
  +      end
  +      let rdPtr = rdPtrReg + wordCount;
  +      if (wrPtrReg < rdPtrReg) begin
  +         $display("requestMessage wrapped: wrPtr=%d rdPtr=%d", wrPtrReg, rdPtrReg);
  +         wordCount = limitReg - rdPtrReg;
  +         rdPtr = 4;
  +      end
  +      if (verbose) $display("requestMessage id=%d rdPtr=%h wrPtr=%h wordCount=%d", sglIdReg, rdPtrReg, wrPtrReg, wordCount);
  +      rdPtrReg <= rdPtr;
         countReg <= truncate(wordCount);
         readEngine[1].request.put( MemengineCmd
  -          {sglId: sglIdReg, base: extend(tailReg << 2), burstLen: 16, len: wordCount << 2, tag: 0});
  +          {sglId: sglIdReg, base: extend(rdPtrReg << 2), burstLen: 16, len: wordCount << 2, tag: 0});
         state <= MessageHeaderRequested;
      endrule
   
  
positive.code: 
  typedef enum {
     Idle,
     HeadRequested, // 1
     TailRequested, // 2
     RequestMessage, // 3
     MessageHeaderRequested, // 4
     MessageRequested, // 5
     Drain,
     UpdateTail,
     UpdateHead,
     UpdateHead2,
     Waiting,
     SendHeader,
     SendMessage,
  
negative.code:       end
     end
  
     rule updateIndWrPtrRdPtr if (state == Idle && readyReg);
        readEngine[0].request.put(
            MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});
        state <= WrPtrRequested;
     endrule
  
     rule receiveIndWrPtrRdPtr if (state == WrPtrRequested || state == RdPtrRequested);
        let md <- toGet(readEngine[0].data).get();
        let data = md.data;
        let w0 = data[31:0];
        let w1 = data[63:32];
        let wrPtr = wrPtrReg;
        let rdPtr = rdPtrReg;
        if (state == WrPtrRequested) begin
           limitReg <= truncate(w0);
           wrPtrReg <= truncate(w1);
           wrPtr = truncate(w1);
           state <= RdPtrRequested;
        end
        else begin
           if (rdPtrReg == 0) begin
              rdPtr = truncate(w0);
              rdPtrReg <= rdPtr;
           end
           //if (rdPtr != wrPtrReg)
              state <= SendHeader;
           //else
              //state <= Idle;
        end
        if (verbose)
           $display("receiveIndWrPtrRdPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limitReg);
     endrule
  
     rule send64bits;
  