anchor.diff:  `include "ConnectalProjectConfig.bsv"
   
   // starting word of MSIX config registers
  -`define msix_base 4096
  +`define msix_base 1024
   
   // An MSIX table entry, as defined in the PCIe spec
   interface MSIX_Entry;
  
positive.code:       let addr = beat.addr >> 2; // word address
        Bit#(32) data = 32'hbad0add0;
        let modaddr = (addr % 8192);
        let msix_base = (`msix_base >> 2);
        let msixaddr = modaddr - msix_base;
        let oneHotDecode000 <- toGet(csrOneHotFifo000).get();
        let oneHotDecode774 <- toGet(csrOneHotFifo774).get();
  
negative.code:       let addr = beat.addr >> 2; // word address
        Bit#(32) data = 0;
        let modaddr = (addr % 8192);
        let msixaddr = modaddr - `msix_base;
  
        csrRagBeatFifo.enq(beat);
        csrIsMsixAddrFifo.enq(msixaddr >= 0 && msixaddr <= 63);
  