anchor.diff:     endrule
   `endif
   
  -`ifdef DEBUG_SETRAM
  -   rule readSetram;
  -      let v <- toGet(setRam.getRead).get;
  -      indication.read_setram_result(zeroExtend(v));
  -   endrule
  -`endif
  -
      //mkConnection(parser.phvOut, ingress_port_mapping.phvIn);
   
   `ifdef MTABLE
  
positive.code: endinterface
  
  //module mkP4Top#(Clock derivedClock, Reset derivedReset, P4TopIndication indication)(P4Top);
  module mkP4Top#(P4TopIndication indication)(P4Top);
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  
  `ifndef BSIM
  `ifndef SIMULATION
     B2C iclock_50 <- mkB2C();
     B2C1 iclock_644 <- mkB2C1();
  
negative.code: 
  `ifdef DEBUG_BCAM
  import Bcam::*;
  import BcamTypes::*;
  import AsymmetricBRAM::*;
  `endif
  
  import PriorityEncoder1::*;
  
  typedef TDiv#(`DataBusWidth, 32) WordsPerBeat;
  
  