anchor.diff:  	    writeDwCountFifo.enq(tlplen);
   	    writeIs3dwFifo.enq(writeIs3dw);
   	    writeIsHeaderOnlyFifo.enq(writeIs3dw && tlplen == 1);
  -	    writeBurstCount <= burstLen;
  +	    writeBurstCount <= extend(burstLen);
   	    writeTag.enq(extend(awid));
            endmethod
   	endinterface
  
positive.code:          method Action put(MemData#(buswidth) wdata)
  	      provisos (Bits#(Vector#(busWidthWords, Bit#(32)), busWidth)) if (writeBurstCount > 0 && writeDataMimo.enqReadyN(fromInteger(valueOf(busWidthWords))));
  
  	      writeBurstCount <= writeBurstCount - 1;
  	      Vector#(busWidthWords, Bit#(32)) v = unpack(wdata.data);
  	      writeDataMimo.enq(fromInteger(valueOf(busWidthWords)), v);
             endmethod
         endinterface
        interface Get writeDone;
  
negative.code:       tlp.sof = True;
        tlp.eof = True;
        tlp.hit = 7'h00;
        TLPLength tlplen = fromInteger(valueOf(busWidthWords))*extend(burstLen);
        if (addr[39:32] != 0) begin
  	 TLPMemory4DWHeader hdr_4dw = defaultValue;
  	 hdr_4dw.format = MEM_READ_4DW_NO_DATA;
  