anchor.diff:        alu_outputs = fv_LOAD (inputs);
   
      else if (inputs.decoded_instr.opcode == op_STORE)
  -      alu_outputs = fv_ST (inputs);
  +      alu_outputs = fv_STORE (inputs);
   
      else if (inputs.decoded_instr.opcode == op_MISC_MEM)
         alu_outputs = fv_MISC_MEM (inputs);
  
positive.code:       alu_outputs = fv_LOAD (inputs);
  
     else if (   (inputs.decoded_instr.opcode == op_STORE_FP))
        alu_outputs = fv_ST (inputs);
  
     else if (   (inputs.decoded_instr.opcode == op_FP)
              || (inputs.decoded_instr.opcode == op_FMADD)
  
negative.code:    alu_outputs.rd        = inputs.decoded_instr.rd;
     alu_outputs.addr      = eaddr;
  `ifdef ISA_F
     // For LOAD_FP, destination register is in FP regs
     alu_outputs.rd_in_fpr = (opcode == op_LOAD_FP);
  `endif
  
  