anchor.diff:  import AxiMasterSlave    :: *;
   import AxiDma            :: *;
   
  +`ifdef USES_FCLK1
  +`define CLOCK_ARG  ps7.fclkclk[1],
  +`else
  +`define CLOCK_ARG
  +`endif
  +
  +`ifndef NumberOfMasters
  +`define NumberOfMasters 1
  +`endif
  +`ifndef PinType
  +`define PinType Empty
  +`endif
  +
  +typedef `PinType PinType;
  +typedef `NumberOfMasters NumberOfMasters;
  +
   interface I2C_Pins;
      interface Inout#(Bit#(1)) scl;
      interface Inout#(Bit#(1)) sda;
  
positive.code:    interface deleteme_unused_clock = unused_clock;
     interface deleteme_unused_reset = unused_reset;
  endmodule
  
  `ifndef PinType
  `define PinType Empty
  `endif
  module mkZynqTop(ZynqTop#(`PinType));
     let top <- mkZynqTopFromPortal(mkPortalTop);
     return top;
  endmodule
  
negative.code:    interface Vector#(4, Reset) deleteme_unused_reset;
  endinterface
  
  module mkZynqTop(ZynqTop#(PinType));
  
     PS7 ps7 <- mkPS7();
     Clock mainclock = ps7.fclkclk[0];
  