anchor.diff:          end
           // move deqP: find the first non-commit port
           function Bool notCommit(SupWaySel i) = !commitEn[i];
  +        indexT nextDeqP;
           if(find(notCommit, supIdxVec) matches tagged Valid .idx) begin
  -            deqP <= commitIndex[idx];
  +            nextDeqP = commitIndex[idx];
               // sanity check: commit is done consecutively
               for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
                   doAssert((fromInteger(i) < idx) == commitEn[i], "commit must be consecutive");
               end
           end
           else begin
  -            deqP <= incrIndex(deqP, valueof(SupSize));
  -        end
  +            nextDeqP = incrIndex(deqP, fromInteger(valueof(SupSize)));
  +        end
  +        deqP <= nextDeqP;
   
           // do wrongSpec OR claim free phy reg
           if(wrongSpecEn.wget matches tagged Valid .x) begin
  
positive.code: 
              method Action claimRename(ArchRegs r, SpecBits sb) if(guard);
                  // record the claim
                  claimEn[i][0] <= Valid (RenameClaim {
                      arch: r.dst,
                      phy: claim_phy_reg,
                      specBits: sb
  
negative.code: // old name is taken from the FreeList and moved back to the RenamingTable.
  
  import Vector::*;
  import GetPut::*;
  import List::*;
  import RevertingVirtualReg::*;
  import Types::*;
  