anchor.diff:  	    779: tlpDataScratchpad[3] <= dword;
   	    780: tlpDataScratchpad[4] <= dword;
   	    781: tlpDataScratchpad[5] <= dword;
  -	    782: axiTestEnabledReg <= dword;
  -	    783: addrLowerWordReg <= dword;
  -	    784: addrUpperWordReg <= dword;
  -	    785: testResultReg <= dword;
  -	    786: testStateReg <= dword;
   
   	    787: pipeliningEnabledReg <= (dword != 0) ? True : False;
   	    788: axiEnabledReg <= (dword != 0) ? True : False;
  
positive.code:    interface Reg pipeliningEnabled = pipeliningEnabledReg;
     interface Reg byteSwap = byteSwapReg;
     interface Reg use4dw = use4dwReg;
     interface Reg axiTestEnabled = axiTestEnabledReg;
     interface Reg numPortals = numPortalsReg;
     interface Reg addrLowerWord = addrLowerWordReg;
     interface Reg addrUpperWord = addrUpperWordReg;
     interface Reg testResult = testResultReg;
     interface Reg testState = testStateReg;
     interface Reg tlpDataBramWrAddr = tlpDataBramWrAddrReg;
     interface Reg tlpSeqno = tlpSeqnoReg;
     interface Reg tlpOutCount = tlpOutCountReg;
  
negative.code:    interface Reg use4dw = use4dwReg;
  endmodule: mkAxiSlaveEngine
  
  // The control and status registers which are accessible from the PCIe
  // bus.
  interface ControlAndStatusRegs;
  