anchor.diff:              //state <= Idle;
         end
         if (verbose)
  -         $display("receiveIndWrPtrRdPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limitReg);
  +         $display("receiveIndRdWrPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limitReg);
      endrule
   
      rule send64bits;
  
positive.code: 
     let verbose = True;
  
     rule updateReqWrPtrRdPtr if (state == Idle && readyReg);
        if (verbose) $display("updateReqWrPtrRdPtr");
        readEngine[0].request.put(
            MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});
        state <= WrPtrRequested;
     endrule
  
     rule receiveReqWrPtrRdPtr if (state == WrPtrRequested || state == RdPtrRequested);
        let v <- toGet(readEngine[0].data).get();
        let w0 = v.data[31:0];
        let w1 = v.data[63:32];
  
negative.code:    endrule
  
     rule sendHeader if (state == SendHeader && interruptStatus);
        Bit#(32) hdr <- toGet(pipes[readyChannel]).get();
        Bit#(16) numWords = hdr[15:0];
        let totalWords = numWords;
  