anchor.diff:  import DefaultValue::*;
   import HostInterface::*;
   import MemTypes::*;
  +import PhysMemToBram::*;
   import Pipe::*;
   import TraceMemClient::*;
   import XilinxCells::*;
  
positive.code: // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  // SOFTWARE.
  
  import BuildVector::*;
  import Clocks::*;
  import Connectable::*;
  
negative.code:    let memReadClients  <- mapM(mkMemReadClient(getObjId), vec(m_axi_mm));
     let memWriteClients <- mapM(mkMemWriteClient(getObjId), vec(m_axi_mm));
  
     FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo <- mkSizedBRAMFIFOF(128);
     PipeIn#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) tracePipe = toPipeIn(traceFifo);
     FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo <- mkSizedBRAMFIFOF(512);
     PipeIn#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataPipe = toPipeIn(traceDataFifo);
     rule rl_trace1;
        match { .chan, .write, .req, .timestamp } <- toGet(traceFifo).get();
        trace.traceDmaRequest(chan, write, truncate(req.sglId), extend(req.offset), extend(req.burstLen), extend(req.tag), timestamp);
     endrule
     rule rl_trace_data;
        match { .chan, .write, .md, .timestamp } <- toGet(traceDataFifo).get();
        trace.traceDmaData(chan, write, md.data, md.last, extend(md.tag), timestamp);
     endrule
  
  