anchor.diff:     interface ipins       pins;
   endinterface
   
  -interface PcieHost#(type ipins);
  -   interface ipins       pins;
  +interface PcieHost#(numeric type dsz);
  +   interface Vector#(16,MSIX_Entry) msixEntry;
  +   interface MemMaster#(32,32) master;
  +   interface Axi3Slave#(40,dsz,6)  slave;
  +   interface Put#(Tuple2#(Bit#(64),Bit#(32))) interruptRequest;
   endinterface
   
  -module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId, MkPortalTop#(dsz, ipins) mkPortalTop,
  -Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(ipins))
  +module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId,
  +   //MemSlave#(32,32) ptslave,
  +   Vector#(`NumberOfMasters,MemMaster#(40, dsz)) masters,
  +   Vector#(16,ReadOnly#(Bool)) ptinterrupt,
  +   MakeResetIfc portalResetIfc,
  +Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(dsz))
   provisos(
      Mul#(TDiv#(dsz, 8), 8, dsz),
       Add#(a__, TDiv#(dsz, 32), 8),
  
positive.code:       Integer intr_num = i+1;
        MSIX_Entry msixEntry = csr.msixEntry[intr_num];
        rule interruptRequest;
  	 if (portalTop.interrupt[i] && !interruptRequested[i])
  	    portalEngine.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));
  	 interruptRequested[i] <= portalTop.interrupt[i];
        endrule
     end
     interface pins = portalTop.pins;
  endmodule: mkPcieHost
  
  (* no_default_clock, no_default_reset *)
  
negative.code:     Mul#(TDiv#(dsz, 32), 32, dsz));
     Clock epClock125 <- exposeCurrentClock();
     Reset epReset125 <- exposeCurrentReset();
  
     PcieSplitter    splitter    <- mkPcieSplitter();
  
  