anchor.diff:  			   resetSeenReg <= 1;
   			resetSeenBit.send(resetSeenReg);
   			resetBit.send(n);
  +			// same for the reset
   			b2c_pcie_sys_reset_n.inputreset(n);
   		     endmethod
   		     interface pcie = host.tep7.pcie;
  +		     // The Bluespec compiler requires that the clocks
  +		     // used by exported methods/pins also be
  +		     // exposed. Because of the b2c, some of the clock
  +		     // pins were not visible to the compiler, so we
  +		     // export them here.
  +		     //
  +		     // We do not have FPGA pins to which we want to
  +		     // connect them, so we rename them
  +		     // "deleteme_unused_clock..." so that the
  +		     // synthesis script will disconnect them from the
  +		     // ports of the toplevel netlist.
   		     interface Clock deleteme_unused_clockFoo = b2c_pcie_sys_reset_n.c;
   		     interface Clock deleteme_unused_clockPortal = host.portalClock;
   		     interface Clock deleteme_unused_clock100mhz = host.tpci_clk_100mhz_buf;
   		     endinterface);
   
  +   // connect the standard LEDS interface
      LEDS ledsIF = (interface LEDS; method Bit#(LedsWidth) leds(); return truncate(ledsValue); endmethod endinterface);
   
  -   interface interrupt = getInterruptVector(portals);
  +   // export the interfaces from the Zynq portals
  +   interface interrupt = getInterruptVector(zynqPortals);
      interface slave = ctrl_mux;
      interface masters = nil;
      interface leds = ledsIF;
  +
  +   // expose the pcie interface as pins
      interface pins = zpcie;
   
   endmodule : mkConnectalTop
  
positive.code:       remainingDuration <= duration;
     endrule
  
     rule updateLinkBit;
        linkUpBit.send(host.tep7.user.lnk_up());
     endrule
     SimpleProxy simpleIndicationProxy <- mkSimpleProxy(SimpleIndication, clocked_by host.portalClock, reset_by host.portalReset);
     Simple simpleRequest <- mkSimple(simpleIndicationProxy.ifc, clocked_by host.portalClock, reset_by host.portalReset);
     SimpleWrapper simpleRequestWrapper <- mkSimpleWrapper(SimpleRequest,simpleRequest, clocked_by host.portalClock, reset_by host.portalReset);
  
negative.code:    pcieportals[0] = simpleIndicationProxy.portalIfc;
     pcieportals[1] = simpleRequestWrapper.portalIfc;
     PhysMemSlave#(32,32) pcie_ctrl_mux <- mkSlaveMux(pcieportals, clocked_by host.portalClock, reset_by host.portalReset);
     // manually connect the PCIe host PhysMemMaster to the pcie_ctrl_mux PhysMemSlave
     mkConnection(host.tpciehost.master, pcie_ctrl_mux, clocked_by host.portalClock, reset_by host.portalReset);
  
     // Construct the ZynqPcie interface
     ZynqPcie zpcie = (interface ZynqPcie;
  		     method Action pcie_sys_clk(Bit#(1) p, Bit#(1) n);
  
  		        // This is a bit of sleight of hand. We depend
  		        // on the way the bluespec compiler generates
  		        // verilog for the following method invocation
  		        // to connect the input clock signals via the
  		        // B2C to the 100Mhz pcie system clock input
  		        // of the PcieHost.
  			b2c_pcie_sys_clk_p.inputclock(p);
  			b2c_pcie_sys_clk_n.inputclock(n);
  		     endmethod
  		     method Action sys_clk(Bit#(1) p, Bit#(1) n);
  			// same for the 200MHz system clock
  			b2c_sys_clk_p.inputclock(p);
  			b2c_sys_clk_n.inputclock(n);
  		     endmethod
  