anchor.diff:          sync_reset_inc_ce <= sric;
           sync_bitslip <= sbs;
       endrule
  -    rule state1_rule (dstate == DValid && dcounter[2] == 1);
  -        dackint <= 1;
  -    endrule
  -    rule state2_rule if (dstate == DLow && dreqpipe1 == 0);
  -        dackint <= 0;
  +    rule state1_rule if (bvi_reset_reg != 0 && dstate == DValid && dcounter[2] == 1);
  +        dackint.send(1);
  +    endrule
  +    rule state2_rule if (bvi_reset_reg != 0 && dstate == DLow && dreqpipe1 == 0);
  +        dackint.send(0);
       endrule
   
       rule setrule;
  
positive.code:     Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(1)) bvi_fifo_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) iserdes_data <-  mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe0 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe1 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_reset_r <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_wren_sync <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dackint <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      ReadOnly#(Bit#(3)) samplein_null <- mkNullCrossingWire(serdes_clock, serbvi.samplein());
  
      Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule wrensyncr_rule if (bvi_reset_reg == 0);
          dfifo_wren_r <= 0;
          fifo_wren_sync <= 0;
          iserdes_bitslip <= 0;
          iodelay_reset_inc_ce <= 0;
          dstate <= DIdle;
          dackint <= 0;
      endrule
      rule wrensync_rule if (bvi_reset_reg != 0);
          let fwsync = 0;
  
negative.code:             fwsync = dfifo_wren_r;
          else
              fwsync = bvi_fifo_wren_wire;
          fifo_wren_sync.send(fwsync);
          iodelay_reset_inc_ce <= sync_reset_inc_ce;
      endrule
      rule wren_dfifo_rule;
          dfifo.wren(fifo_wren_sync.read());
      endrule
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
  