anchor.diff:  `ifndef BSIM
      interface StdAxi3Master m_axi = axi_master;
   `endif
  -endmodule : mkAxiTop
  +endmodule : mkPortalDmaTop
   
  -module mkZynqTop(AxiTop);
  -   let axiTop <- mkAxiTop();
  -   return axiTop;
  +module mkZynqTop(PortalDmaTop);
  +   let portalTop <- mkPortalDmaTop();
  +   return portalTop;
   endmodule : mkZynqTop
   
   import "BDPI" function Action      initPortal(Bit#(32) d);
  
positive.code: // defined by user
  import Memread::*;
  
  interface AxiTop;
     interface StdAxi3Slave     ctrl;
     interface StdAxi3Master    m_axi;
     interface ReadOnly#(Bool)  interrupt;
     interface LEDS             leds;
  endinterface
  
  module mkAxiTop(AxiTop);
  
     DMAIndicationProxy dmaIndicationProxy <- mkDMAIndicationProxy(9);
  
  
negative.code: 
  
  module mkBsimTop();
     PortalDmaTop top <- mkPortalDmaTop;
     let wf <- mkPipelineFIFO;
     let init_seq = (action 
  		      initPortal(0);
  