anchor.diff:                       "addr BE should be naturally aligned");
               doAssert(st_specBits_deqSt[deqP] == 0,
                        "must have zero spec bits");
  +            doAssert((st_memFunc[deqP] == Fence) == !st_computed_deqSt[deqP],
  +                     "only fence is not computed");
           end
   
           // remove entry
  
positive.code:                                               genWith(fromInteger));
          Maybe#(StQTag) matchStTag = findYoungestSt(checkSts);
  
          // select the younger one from LQ and SQ search results
          LdQTag ldTag = validValue(matchLdTag);
          Maybe#(StQVirTag) ldTagOlderSt = olderStVirTags[ldTag];
          StQTag stTag = validValue(matchStTag);
          StQVirTag stVTag = stVirTags[stTag];
          if(isValid(matchLdTag) && (!isValid(matchStTag) ||
                                     (isValid(ldTagOlderSt) && 
                                      validValue(ldTagOlderSt) >= stVTag))) begin
              // stalled by Ld, Lr or acquire in LQ
              issRes = Stall (LdQ);
              if(ld_acq[ldTag]) begin
  
negative.code:              st_computed_verify[verP], noAction);
  
  `else
          // WEAK: just check computed XXX don't verify fence for now
          when(st_computed_verify[verP], noAction);
  `endif
  
          // mark as verified and move verify ptr
  