anchor.diff:        rdataProbe <= data;
         dramReadGearbox.enq(data);
      endrule
  -   FIFOF#(Bit#(DataBusWidth)) slackFifo <- mkFIFOF();
      rule rl_rdata_gb;
         Bit#(DataBusWidth) rdata <- toGet(dramReadGearbox).get();
  -      slackFifo.enq(rdata);
  +      dramReadFifo.enq(rdata);
      endrule
      rule rl_rdata_slack;
  -      let rdata <- toGet(slackFifo).get();
  +      let rdata <- toGet(dramReadFifo).get();
         //fixme last field
         we.writeServers[0].data.enq(rdata);
      endrule
  
positive.code:    let sglWriteProbe <- mkProbe();
     let sglReadProbe <- mkProbe();
  
     Gearbox#(1,BusRatio,Bit#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
     SyncFIFOIfc#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkSyncFIFO(8, clock, reset, ddr3Controller.uiClock);
     SyncFIFOIfc#(Axi4WriteResponse#(6)) bfifo <- mkSyncFIFO(8, ddr3Controller.uiClock, ddr3Controller.uiReset, clock);
     //mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);
     //mkConnection(ddr3Controller.slave.resp_b, toPut(bfifo));
     rule rl_awfifo;
  
negative.code: 						  });
     endrule
  
     Gearbox#(BusRatio,1,Bit#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, ddr3Controller.uiClock, ddr3Controller.uiReset);
     FIFOF#(Bit#(DataBusWidth)) dramReadFifo <- mkDualClockBramFIFOF(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);
     FIFOF#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
     //mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);
     rule rl_arfifo;
        let req <- toGet(arfifo).get();
  