anchor.diff:          Bit#(internalAddrSize) addr = tpl_2(reqTuple);
           Bit#(32) retVal = 0;
           case (truncate(addr))
  -          txDataAddr: retVal = txDataReg;
  -          rxDataAddr: retVal = rxDataReg;
  +          txDataAddr: begin
  +                        retVal = 0
  +                        if (txDataReg matches tagged Valid .x) begin
  +                          retVal = {1'b1, '0, x};
  +                        end
  +                      end
  +          rxDataAddr: begin
  +                        retVal = 0;
  +                        if (rxDataReg matches tagged Valid .x) begin
  +                          retVal = {1'b1, '0, x};
  +                          rxDataReg <= tagged Invalid;
  +                          end
  +                      end
             txCtrlAddr: retVal = txCtrlReg;
             rxCtrlAddr: retVal = rxCtrlReg;
             divAddr:    retVal = divReg;
  
positive.code:   //   interface Put#(Bit#(8))  rx;
    //     method Action put(x)
    // Get and Put have FiFos attached to the ends of them
    UART#(16) uart <- mkUART(8, EVEN, STOP_1_5, divReg);
    // Data registers
    Reg#(Bit#(32)) txDataReg <- mkReg(0);
    Reg#(Bit#(32)) rxDataReg <- mkReg(0);
    Reg#(Bit#(32)) txCtrlReg <- mkReg(0);
    Reg#(Bit#(32)) rxCtrlReg <- mkReg(0);
    Reg#(Bit#(16)) divReg <- mkReg(divsor);
  
    Ehr#(2, Bool) interruptReg <- mkEhr(0);
  
    rule doTxData (txDataReg[31] && txCtrlReg[0]);
      // There is an implicit guard on the Fifo for uart.put
      uart.put(txDataReg[7:0]);
      txDataReg[31] <= 0;
    endrule
  
    rule doRxData (!rxDataReg[0] && rxCtrlReg[0]);
      rxDataReg <= uart.get;
      interruptReg[0] <= True;
    endrule
  
negative.code:     endinterface
    endinterface
  
    interface RS232 uart_pins = uart.rs232;
    method Bit#(16) divisor = divReg;
    method Vector#(1, Bool) receiveInterrupt = vec(receiveInterrupt);
  
  