anchor.diff:  module mkPortalCtrlMemSlave#(Vector#(numIndications, PipeOut#(Bit#(dataWidth))) indicationPipes)(PortalCtrlMemSlave#(addrWidth, dataWidth));
      AddressGenerator#(addrWidth,dataWidth) ctrlReadAddrGenerator  <- mkAddressGenerator();
      AddressGenerator#(addrWidth,dataWidth) ctrlWriteAddrGenerator <- mkAddressGenerator();
  +   FIFO#(MemData#(dataWidth))        ctrlWriteDataFifo <- mkFIFO();
      FIFO#(Bit#(ObjectTagSize))        ctrlWriteDoneFifo <- mkFIFO();
   
       // indication-specific state
  
positive.code:            readyChannel = fromInteger(i);
          end
      end
  
     interface MemSlave memSlave;
        interface MemReadServer read_server;
  
negative.code: 	 interface Put writeReq = ctrlWriteAddrGenerator.request;
  	 interface Put writeData;
  	    method Action put(MemData#(dataWidth) d);
  	       ctrlWriteDataFifo.enq(d);
  	    endmethod
  	 endinterface
  	 interface Get writeDone;
  