anchor.diff:  	 tlpOutFifo.enq(tlp);
         end
      endrule
  -   rule txnTimer if (timerReg > 0);
  -      timerReg <= timerReg - 1;
  -   endrule
   
       interface Client        tlp;
       interface Put response;
  
positive.code: (* synthesize *)
  module mkMemMasterEngine#(PciId my_id)(MemMasterEngine);
      Reg#(Bit#(7)) hitReg <- mkReg(0);
      Reg#(Bit#(4)) timerReg <- mkReg(0);
      FIFOF#(TLPMemoryIO3DWHeader) readHeaderFifo <- mkSizedFIFOF(8);
      FIFOF#(TLPMemoryIO3DWHeader) readDataFifo <- mkSizedFIFOF(8);
      FIFOF#(TLPMemoryIO3DWHeader) writeHeaderFifo <- mkSizedFIFOF(8);
  
negative.code: 	       if (writeHeaderFifo.notFull())
  		  writeHeaderFifo.enq(hdr_3dw);
  	    end
  	endmethod
      endinterface
      interface Get request = toGet(tlpOutFifo);
  