anchor.diff:  
      method Action setupA(Bit#(32) strPointer, Bit#(32) strLen);
         aLenReg <= strLen;
  -      n2a.start(strPointer, 0, pack(truncate(strLen+1)), 0);
  +      n2a.start(strPointer, 0, pack(truncate(strLen)), 0);
      endmethod
   
      method Action setupB(Bit#(32) strPointer, Bit#(32) strLen);
         bLenReg <= strLen;
  -      n2b.start(strPointer, 0, pack(truncate(strLen+1)), 0);
  +      n2b.start(strPointer, 0, pack(truncate(strLen)), 0);
      endmethod
      
      method Action fetch(Bit#(32) strPointer, Bit#(32) strLen);
         rLenReg <= strLen;
  -      l2n.start(strPointer, 0, pack(trunate(strLen+1)), 0);
  +      l2n.start(strPointer, 0, pack(trunate(strLen)), 0);
      endmethod
   
      method Action start();
  
positive.code:    method Action fetchComplete(); 
  endinterface
  
  
  typedef 128 MaxStringLen;
  typedef Bit#(TLog#(MaxStringLen)) StringIdx;
  typedef Bit#TLog#(MaxStringLen*MaxStringLen)) LIdx;
  
  module mkMaxcommonsubseqRequest#(MaxcommonsubseqIndication indication,
  			DmaReadServer#(busWidth)   setupA_read_server,
  
negative.code: 	    Add#(1, b__, nc),
  	    Add#(c__, 32, busWidth),
  	    Add#(1, d__, TDiv#(busWidth, 32)),
  	    Mul#(TDiv#(busWidth, 32), 32, busWidth));
     
    Reg#(Bit#(32)) aLenReg <- mkReg(0);
    Reg#(Bit#(32)) bLenReg <- mkReg(0);
    Reg#(Bit#(32)) rLenReg <- mkReg(0);
    
     BRAM2Port#(StringIdx, Char) strA  <- mkBRAM2Server(defaultValue);
     BRAM2Port#(StringIdx, Char) strB <- mkBRAM2Server(defaultValue);
  
     BRAM2Port#(LIdx, Bit#(16)) matL <- mkBRAM2Server(defaultValue);
  
     BRAMReadClient#(StringIdx,busWidth) n2a <- mkBRAMReadClient(strA.portB);
     mkConnection(n2a.dmaClient, setupA_read_server);
     BRAMReadClient#(StringIdx,busWidth) n2b <- mkBRAMReadClient(strB.portB);
     mkConnection(n2b.dmaClient, setupB_read_server);
     BRAMWriteClient#(LIdx, 16) l2n <- mkBRAMWriteClient(matL.portB);
  
     // create BRAM Write client for matL
  
  