anchor.diff:        let cli = compReg2;
         if(killv[compReg3] == False) begin
   	 compFifo0.enq(extend(cli));
  -	 read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
  +	 readBufferBram.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
         end
         compReg0 <= cnt-1;
         if(debug) $display("mkMemReadInternal::complete_burst1b %h", compReg0);
  
positive.code: 		  interface Get readData;
  		     method ActionValue#(MemData#(dataWidth)) get if (compFifo0.first == fromInteger(i));
  			compFifo0.deq;
  			let data <- read_buffer.portB.response.get;
  			if (debug) $display("mkMemReadInternal::comp %d  %x %d", i, data.data, cycle_cnt-last_comp);
  			last_comp <= cycle_cnt;
  			return data;
  
negative.code:       interface Put readData;
  	 method Action put(MemData#(dataWidth) response);
  	    readDataPipelineFifo.enq(response);
  	    dreqBram.portA.request.put(BRAMRequest{write:False, address:truncate(response.tag), datain: ?, responseOnWrite: ?});
  	    beatCount <= beatCount+1;
  	 endmethod
        endinterface
  