anchor.diff:        endinterface
         interface Get writeDone;
   	 method ActionValue#(Bit#(6)) get();
  -	    let rv <- ifcs[ws.first].write_server.writeDone.get();
  +	    let rv <- portalIfcs[ws.first].write_server.writeDone.get();
   	    req_aw_fifo.deq;
   	    ws.deq();
   	    return rv;
  
positive.code: 	    Add#(a__, TLog#(numSlaves), selWidth)
        );
  
     Vector#(numSlaves, MemSlave#(aw,dataWidth)) ifcs = take(slaves);
     let port_sel_low = valueOf(aw);
     let port_sel_high = valueOf(TSub#(addrWidth,1));
     function Bit#(selWidth) psel(Bit#(addrWidth) a);
  
negative.code: 
     rule req_aw;
        let req <- toGet(req_aws).get;
        portalIfcs[ws.first].write_server.writeReq.put(req);
     endrule
  
     rule req_ar;
        let req <- toGet(req_ars).get;
        portalIfcs[rs.first].read_server.readReq.put(req);
     endrule
  
     interface MemWriteServer write_server;
  