anchor.diff:      endrule
   
       rule wrensyncr_rule if (bvi_reset_reg == 0);
  -        dfifo_wren_r <= 0;
  -        fifo_wren_sync.send(0);
           sync_bitslip <= 0;
           sync_reset_inc_ce <= 0;
  -        dstate <= DIdle;
  +        serdes_running <= 0;
       endrule
       rule wrensync_rule if (bvi_reset_reg != 0);
  -        fifo_wren_sync.send(bvi_fifo_wren_wire);
           fifo_reset <= dfifo_reset_r.read();
       endrule
   
  
positive.code: 
      rule datain_rule;
          Bit#(10) dout = 0;
          Bit#(10) edgeo = 0;
          for (Integer i = 0; i < 10; i = i + 1)
              dout[i] = iserdes_data[i].read();
          for (Integer i = 0; i < 9; i = i + 1)
              edgeo[i] = dout[i] ^ dout[i+1];
          edgeo[9] = dout[0] ^ dout[9];
          edge_int <= edgeo;
          edge_intor_reg <= pack(edgeo != 0);
          if (fifo_wren_sync.read() == 1)
              begin
              dfifo.di({6'b0,dout});
  
negative.code:     Wire#(Bit#(1)) bvi_delay_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      SyncBitIfc#(Bit#(1)) bvi_resets_reg <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);
      Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) serdes_running <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      SyncBitIfc#(Bit#(1)) dfifo_reset_r <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
  