anchor.diff:  
      Vector#(PortMax, MemMasterEngine) mvec;
      for (Integer i = 0; i < valueOf(PortMax); i=i+1) begin
  -       let serv = (interface Server;
  -                     interface response = dispatcher.out[i];
  -                     interface request = arbiter.in[i];
  -                  endinterface);
  -       if (i == portAxi)
  -           mkConnection(serv, sEngine.tlp);
  -       else begin
  +       let tlp = sEngine.tlp;
  +       if (i != portAxi) begin
              mvec[i] <- mkMemMasterEngine(my_pciId);
  -           mkConnection(serv, mvec[i].tlp);
  +           tlp = mvec[i].tlp;
          end
  +       mkConnection((interface Server;
  +                        interface response = dispatcher.out[i];
  +                        interface request = arbiter.in[i];
  +                     endinterface), tlp);
      end
   
  -   // The PCIE endpoint is processing TLPData#(8)s at 250MHz.  The
  -   // AXI bridge is accepting TLPData#(16)s at 125 MHz. The
  -   // connection between the endpoint and the AXI contains GearBox
  -   // instances for the TLPData#(8)@250 <--> TLPData#(16)@125
  -   // conversion.
  -   PcieGearbox gb <- mkPcieGearbox(epClock250, epReset250, epClock125, epReset125);
  -   mkConnection(ep_tlp, gb.tlp, clocked_by epClock250, reset_by epReset250);
  -
      PcieTracer  traceif <- mkPcieTracer();
  -   mkConnection(gb.pci, traceif.pci);
  +   //mkConnection(gb.pci, traceif.pci);
      mkConnection(traceif.bus, (interface Client;
                                    interface request = arbiter.outToBus;
                                    interface response = dispatcher.inFromBus;
  
positive.code:    Reset epReset125 <- mkAsyncReset(4, user_reset_n, epClock125);
  
     let portalTop <- mkSynthesizeablePortalTop(clocked_by epClock125, reset_by epReset125);
     PcieHost#(DataBusWidth) pciehost <- mkPcieHost(epClock250, epReset250,
           PciId{ bus:  _ep.cfg.bus_number(), dev: _ep.cfg.device_number(), func: _ep.cfg.function_number()},
           _ep.tlp, clocked_by epClock125, reset_by epReset125);
  
     mkConnection(pciehost.master, portalTop.slave, clocked_by epClock125, reset_by epReset125);
     if (valueOf(NumberOfMasters) > 0) begin
  
negative.code:    interface master = mvec[portPortal].master;
     interface slave = sEngine.slave;
     interface interruptRequest = mvec[portPortal].interruptRequest;
     interface pci = traceif.pci;
  endmodule: mkPcieHost
  
  
  