anchor.diff:        // Await mem system FENCE.I completion
         let dummy <- near_mem.server_fence_i.response.get;
   
  +      // MSTATUS.MXR for initiating FETCH
  +      Bit #(1) mstatus_MXR = mstatus [19];
  +      Bit #(1) sstatus_SUM = 0;
  +
  +      // SSTATUS.SUM for initiating FETCH
  +`ifdef ISA_PRIV_S
  +      sstatus_SUM = (csr_regfile.read_sstatus) [18];
  +`else
  +      sstatus_SUM = 0;
  +`endif
  +
         // Resume pipe
         rg_state <= CPU_RUNNING;
         let new_epoch <- fav_update_epoch;
         let m_old_pc   = tagged Invalid;
  -      fa_start_ifetch (new_epoch, m_old_pc, rg_next_pc, rg_cur_priv);
  +      fa_start_ifetch (
  +           new_epoch
  +         , m_old_pc
  +         , rg_next_pc
  +         , rg_cur_priv
  +         , mstatus_MXR
  +         , sstatus_SUM);
  +
         stageF.set_full (True);
  -
         stageD.set_full (False);
         stage1.set_full (False);
   
  
positive.code:    Reg #(Priv_Mode)  rg_cur_priv <- mkReg (m_Priv_Mode);
     Reg #(Epoch)      rg_epoch    <- mkRegU;
  
     // Save next_pc across split-phase FENCE.I and other split-phase ops
     Reg #(WordXL) rg_next_pc <- mkRegU;
  
     // ----------------
     // Pipeline stages
  
negative.code: `endif
  	      CPU_RUNNING,          // Normal operation
  	      CPU_TRAP,
  	      CPU_SPLIT_FETCH,      // To initiate IFetch after traps/interrupts/RET
  	      CPU_CSRRX_RESTART,    // Restart pipe after a CSRRX instruction
  	      CPU_FENCE_I,          // While waiting for FENCE.I to complete in Near_Mem
  	      CPU_FENCE,            // While waiting for FENCE to complete in Near_Mem
  