anchor.diff:        Bool log_rcvd_next    = False;
         if (dtpEventInFifo.notEmpty) begin
            let v <- toGet(dtpEventInFifo).get;
  -         if (v.e == init_type) begin
  +         if ((v.e == init_type) && initTimestampFifo.notFull) begin
               initTimestampFifo.enq(v.t);
               let parity = ^(v.t);
               initParityFifo.enq(parity);
  
positive.code: 
  module mkDtpTx#(Integer id, Integer c_local_init)(DtpTx);
  
     let verbose = True;
     Wire#(Bool) tx_ready_wire <- mkDWire(False);
     Wire#(Bool) rx_ready_wire <- mkDWire(False);
     Wire#(Bool) switch_mode_wire <- mkDWire(False);
  
negative.code:    Reg#(Bit#(32))  timeout_count_init <- mkReg(0);
     Reg#(Bit#(32))  timeout_count_sync <- mkReg(0);
     Reg#(Bit#(64))  jumpCount <- mkReg(0);
     Reg#(Bit#(32))  interval_reg <- mkReg(10);
  
     Wire#(Bool) init_rcvd    <- mkDWire(False);
     Wire#(Bool) ack_rcvd     <- mkDWire(False);
  