anchor.diff:  
      FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo <- mkSizedBRAMFIFOF(128);
      PipeIn#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) tracePipe = toPipeIn(traceFifo);
  -   FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo <- mkSizedBRAMFIFOF(512);
  +   FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo <- mkSizedBRAMFIFOF(1024);
      PipeIn#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataPipe = toPipeIn(traceDataFifo);
      rule rl_trace1;
         match { .chan, .write, .req, .timestamp } <- toGet(traceFifo).get();
  
positive.code:    let writeDoneFifo <- mkFIFOF();
  
     let busReadReqFifo   <- mkFIFOF();
     let busReadDataFifo  <- mkFIFOF();
     let busWriteReqFifo  <- mkFIFOF();
     let busWriteDataFifo <- mkFIFOF();
     let busWriteDoneFifo <- mkFIFOF();
  
     let bramReadReqFifo   <- mkFIFOF();
     let bramReadDataFifo  <- mkFIFOF();
     let bramWriteReqFifo  <- mkFIFOF();
     let bramWriteDataFifo <- mkFIFOF();
     let bramWriteDoneFifo <- mkFIFOF();
  
     let doneFifo <- mkFIFOF();
  
     let dataFifo <- mkSizedBRAMFIFOF(128);
  
     AddressGenerator#(24,DataBusWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(24,DataBusWidth) writeAddrGenerator <- mkAddressGenerator();
  
     rule rl_rd_req;
        MemRequest req <- toGet(readReqFifo).get();
  
negative.code:       else
  	 busReadReqFifo.enq(req);
        readAddrGenerator.request.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen, tag: extend(dest) });
  
        readReqObj <= req.sglId;
        readReqDest <= dest;
        readReqOffset <= req.offset[31:0];
     endrule
  
     rule rl_rd_data;
        let addrBeat <- readAddrGenerator.addrBeat.get();
        let dest = addrBeat.tag[1:0];
  