anchor.diff:     Clock sys_clk_p,     Clock sys_clk_n,
      Clock io_vita_clk_out_p, Clock io_vita_clk_out_n,
      Reset pci_sys_reset_n)
  -   (PcieTop#(ImageonVita));
  +   (PcieTop#(ImageCapturePins));
   
      let top <- mkPcieTopFromPortal(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n,
   				  io_vita_clk_out_p, io_vita_clk_out_n,
  
positive.code: // SOFTWARE.
  
  import Vector            :: *;
  import Connectable       :: *;
  import Xilinx            :: *;
  import XilinxCells       :: *;
  
negative.code:    mkConnection(tpl_1(x7pcie.slave), tpl_2(axiSlaveEngine.tlps), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(tpl_1(axiSlaveEngine.tlps), tpl_2(x7pcie.slave), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     Axi3Master#(40,dsz,6) m_axi <- mkAxiDmaMaster(portalTop.master,clocked_by x7pcie.clock125, reset_by x7pcie.portalReset);
     mkConnection(m_axi, axiSlaveEngine.slave, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     mkConnection(tpl_1(x7pcie.master), axiMasterEngine.tlp_in);
     mkConnection(axiMasterEngine.tlp_out, tpl_2(x7pcie.master));
  
     Axi3Slave#(32,32,12) ctrl <- mkAxiDmaSlave(portalTop.slave, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(axiMasterEngine.master, ctrl, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // going from level to edge-triggered interrupt
     Vector#(15, Reg#(Bool)) interruptRequested <- replicateM(mkReg(False, clocked_by x7pcie.clock125, reset_by x7pcie.reset125));
     for (Integer i = 0; i < 15; i = i + 1) begin
        // intr_num 0 for the directory
        Integer intr_num = i+1;
        MSIX_Entry msixEntry = x7pcie.msixEntry[intr_num];
        rule interruptRequest;
  	 if (portalTop.interrupt[i] && !interruptRequested[i])
  	    axiMasterEngine.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));
  	 interruptRequested[i] <= portalTop.interrupt[i];
        endrule
     end
  
     interface pcie = x7pcie.pcie;
     //interface ddr3 = x7pcie.ddr3;
  