anchor.diff:                 Word_S offset  = extend(unpack(decoded.imm13_SB));
                  Word   next_pc = pack(unpack(pc) + offset);
   
  -               if      (decoded.funct3 == f3_BEQ)  fa_finish_cond_branch(v1  == v2,    next_pc);
  -               else if (decoded.funct3 == f3_BNE)  fa_finish_cond_branch(v1  != v2,    next_pc);
  -               else if (decoded.funct3 == f3_BLT)  fa_finish_cond_branch(s_v1 <  s_v2, next_pc);
  -               else if (decoded.funct3 == f3_BGE)  fa_finish_cond_branch(s_v1 >= s_v2, next_pc);
  -               else if (decoded.funct3 == f3_BLTU) fa_finish_cond_branch(v1  <  v2,    next_pc);
  -               else if (decoded.funct3 == f3_BGEU) fa_finish_cond_branch(v1  >= v2,    next_pc);
  -               else fa_finish_with_exception(pc, exc_code_ILLEGAL_INSTRUCTION, ?);
  +               case(decoded.instr)
  +                  OP_BEQ   :  fa_finish_cond_branch(v1  == v2,    next_pc);
  +                  OP_BNE   :  fa_finish_cond_branch(v1  != v2,    next_pc);
  +                  OP_BLT   :  fa_finish_cond_branch(s_v1 <  s_v2, next_pc);
  +                  OP_BGE   :  fa_finish_cond_branch(s_v1 >= s_v2, next_pc);
  +                  OP_BLTU  :  fa_finish_cond_branch(v1  <  v2,    next_pc);
  +                  /* OP_BGEU */
  +                  default  :  fa_finish_cond_branch(v1  >= v2,    next_pc);
  +               endcase
   
                  if (cfg_verbose > 2) begin
                     $display("[%7d] Decoded: PC = %h, %s %s, %s, 0x%h", csr_cycle, decoded.pc,
  -                              case(decoded.funct3)
  -                                 f3_BEQ  : "beq";
  -                                 f3_BNE  : "bne";
  -                                 f3_BLT  : "blt";
  -                                 f3_BGE  : "bge";
  -                                 f3_BLTU : "bltu";
  -                                 f3_BGEU : "bgeu";
  +                              case(decoded.instr)
  +                                 OP_BEQ  : "beq";
  +                                 OP_BNE  : "bne";
  +                                 OP_BLT  : "blt";
  +                                 OP_BGE  : "bge";
  +                                 OP_BLTU : "bltu";
  +                                 OP_BGEU : "bgeu";
                                 endcase,
                                 regNameABI[decoded.rs1],
                                 regNameABI[decoded.rs2],
  
positive.code: 
                 rg_mem_addr <= mem_addr;
  
                 if      (decoded.funct3 == f3_LB)      fa_LD_Req(BITS8);
                 else if (decoded.funct3 == f3_LBU)     fa_LD_Req(BITS8);
                 else if (decoded.funct3 == f3_LH)      fa_LD_Req(BITS16);
                 else if (decoded.funct3 == f3_LHU)     fa_LD_Req(BITS16);
                 else if (decoded.funct3 == f3_LW)      fa_LD_Req(BITS32);
                 else fa_finish_with_exception(pc, exc_code_ILLEGAL_INSTRUCTION, ?);
  
                 if (cfg_verbose > 2) begin
                    $display("[%7d] Decoded: PC = %h, %s %s, %s, %1d", csr_cycle, decoded.pc,
                                case(decoded.funct3)
                                   f3_LB  : "lb";
                                   f3_LBU : "lbu";
                                   f3_LH  : "lh";
                                   f3_LHU : "lhu";
                                   f3_LW  : "lw";
                                endcase,
                                regNameABI[decoded.rd],
                                regNameABI[decoded.rs1],
  
negative.code:             action
                 Bit#(TLog#(XLEN)) shamt = truncate(v2);    // NOTE: upper bits are unspecified in spec
  
                 case(decoded.instr)
                    OP_ADD   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 + s_v2));
                    OP_SUB   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 - s_v2));
                    OP_SLL   :  fa_finish_with_Rd(decoded.rd, (v1 << shamt));
                    OP_SLT   :  fa_finish_with_Rd(decoded.rd, ((s_v1 < s_v2) ? 1 : 0));
                    OP_SLTU  :  fa_finish_with_Rd(decoded.rd, ((v1  < v2)  ? 1 : 0));
                    OP_XOR   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 ^ s_v2));
                    OP_SRL   :  fa_finish_with_Rd(decoded.rd, (v1 >> shamt));
                    OP_SRA   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 >> shamt));
                    OP_OR    :  fa_finish_with_Rd(decoded.rd, pack(s_v1 | s_v2));
                    /*OP_AND*/
                    default  :  fa_finish_with_Rd(decoded.rd, pack(s_v1 & s_v2));
                 endcase
  
                 if (cfg_verbose > 2) begin
                    $display("[%7d] Decoded: PC = %h, %s %s, %s, %s", csr_cycle, decoded.pc,
                          case(decoded.instr)
                             OP_ADD  : "add";
                             OP_SUB  : "sub";
                             OP_SLL  : "sll";
                             OP_SLT  : "slt";
                             OP_SLTU : "sltu";
                             OP_XOR  : "xor";
                             OP_SRL  : "srl";
                             OP_SRA  : "sra";
                             OP_OR   : "or";
                             OP_AND  : "and";
                          endcase,
                          regNameABI[decoded.rd],
                          regNameABI[decoded.rs1],
  