anchor.diff:  	  hdr_3dw.data = byteSwap(interruptDataReg);
   	  tlp.data = pack(hdr_3dw);
   	  tlp.eof = True;
  -	  interruptRequestedReg <= False;
  +	  sendInterrupt = True;
  +	  interruptRequested = False;
          end
          else begin
   	  TLPMemory4DWHeader hdr_4dw = defaultValue;
  
positive.code: 		     hitReg <= tlp.hit;
  		     TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);
  		     Vector#(4, Bit#(32)) vec = unpack(0);
  		     if (!tlp.sof) begin
  			for (Integer i = 0; i < 4; i = i+1) begin
  			   if (tlp.be[(i+1)*4-1:i*4] == 4'hf) begin
  			      vec[i] = tlp.data[(i+1)*32-1:i*32];
  			   end
  			end
  			let count = tlpWordCount(tlp);
  			completionMimo.enq(count, vec);
  			completionTagMimo.enq(count, replicate(lastTag));
  		     end
  
negative.code:         timerReg <= timerReg - 1;
      endrule
  
      rule interruptTlpOut if (interruptRequestedReg && !interruptSecondHalf);
         TLPData#(16) tlp = defaultValue;
         tlp.sof = True;
         tlp.eof = False;
         tlp.hit = 7'h00;
         tlp.be = 16'hffff;
  
         let sendInterrupt = False;
         let interruptRequested = interruptRequestedReg;
  
         if (interruptAddrReg == '0) begin
  	  // do not write to 0 -- it wedges the host
  	  interruptRequested = False;
         end
         else if (interruptAddrReg[63:32] == '0) begin
            TLPMemoryIO3DWHeader hdr_3dw = defaultValue();
            hdr_3dw.format = MEM_WRITE_3DW_DATA;
  	  //hdr_3dw.pkttype = MEM_READ_WRITE;
  