anchor.diff:        else
   	 doneTag <- toGet(busWriteDoneFifo).get();
         writeDoneFifo.enq(doneTag);
  -
  -      writeDoneTag <= doneTag;
  -      writeDoneDest <= dest;
      endrule
   
      interface MemServer server;
  
positive.code: 	 bramReadReqFifo.enq(req);
        else
  	 busReadReqFifo.enq(req);
        readAddrGenerator.request.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen, tag: extend(dest) });
  
        readReqObj <= req.sglId;
        readReqDest <= dest;
        readReqOffset <= req.offset[31:0];
     endrule
  
     rule rl_rd_data;
        let addrBeat <- readAddrGenerator.addrBeat.get();
        let dest = addrBeat.tag[1:0];
        MemData#(dataBusWidth) md;
        if (dest == 2)
  	 md <- toGet(bramReadDataFifo).get();
        else
  	 md <- toGet(busReadDataFifo).get();
        readDataFifo.enq(md);
  
        readDataDest <= dest;
        readDataData <= md.data;
        readDataLast <= md.last;
        readBeatAddr <= addrBeat.addr[15:0];
        readBeatByteCount <= addrBeat.bc;
        readBeatLast <= addrBeat.last;
     endrule
  
     rule rl_wr_req;
  
negative.code: 	 // no need to send the request
        end else
  	 busWriteReqFifo.enq(req);
        writeDestFifo.enq(dest);
     endrule
     
     rule rl_wr_data;
        let dest = writeDestFifo.first();
        MemData#(dataBusWidth) md <- toGet(writeDataFifo).get();
        if (dest == 2)
  	 bramWriteDataFifo.enq(md);
  