anchor.diff:        method                  delay_wren(DELAY_WREN) enable((*inhigh*) en11) clocked_by (clkdiv);
         method                  reset(RESET) enable((*inhigh*) en17) clocked_by (clkdiv);
         method                  dataout(ISERDES_DATA) enable((*inhigh*) en18) clocked_by(clkdiv);
  -   schedule (fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
  -         CF (fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  +   schedule (fifo_reset, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
  +         CF (fifo_reset, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
   endmodule: mkIserdesbvi
   
   interface IserdesDatadeser;
  
positive.code: 
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
      ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
      Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
      FIFO18 dfifo <- mkFIFO18(serdes_clock);
      IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
          cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
  
negative.code:         slave_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
          serbvi.dataout(dout);
          dfifo.di({6'b0,dout});
      endrule
  
      rule wren_dfifo_rule;
  