anchor.diff:      Reg#(Bit#(1)) fifo_wren_c_reg <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
   
       ClockGenIfc serdest_clk <- mkBUFIO(ibufds_clk);
  -    Vector#(5, ReadOnly#(Bit#(1))) ibufds_v;
  -    for (Integer i = 0; i < 5; i = i + 1)
  -        ibufds_v[i] <- mkIBUFDS(vita_data_p[i], vita_data_n[i]);
       Reg#(Bit#(1)) serdes_align_busy_temp <- mkReg(0);
       Reg#(Bit#(1)) serdes_align_busy_reg <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);
       Reg#(Bit#(1)) serdes_aligned_temp <- mkReg(0);
  
positive.code:     SyncFIFOIfc#(Bit#(1)) item_req_wire <- mkSyncFIFO(2, defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
      Wire#(Bit#(1)) this_align_busy_wire <- mkDWire(0);
      FIFO#(Bit#(1)) this_start_align_reg <- mkFIFO();
      Reg#(Bit#(16)) serdes_counter <- mkReg(0);
      Reg#(QState)  qstate <- mkReg(QIdle);
      Reg#(AState)  astate <- mkReg(AIdle);
  
negative.code:     method Bit#(1)                aligned();
          return this_aligned_reg;
      endmethod
      method Bit#(3)                samplein();
          return ctrl_sample;
      endmethod
      method Action                 delay_wren(Bit#(1) v);
          bvi_delay_wren_wire <= v;
  