anchor.diff:                                                   , max_payload_bytes
                                                    );
   
  -   rule endTrace if (csr.tlpTracing && csr.tlpDataBramWrAddr > 1023);
  +   rule endTrace if (csr.tlpTracing && csr.tlpDataBramWrAddr > 2047);
          csr.tlpTracing <= False;
      endrule
      rule connectEnables;
  
positive.code:     interface Reg interruptData      = interruptDataReg;
  endmodule: mkPortalEngine
  
  interface AxiSlaveEngine#(type buswidth, type buswidthbytes);
      interface GetPut#(TLPData#(16))   tlps;
      interface Axi3Slave#(40,buswidth,buswidthbytes,12)  slave;
      method Bool tlpOutFifoNotEmpty();
      interface Reg#(Bool) use4dw;
  endinterface: AxiSlaveEngine
  
  module mkAxiSlaveEngine#(PciId my_id)(AxiSlaveEngine#(buswidth, buswidthbytes))
     provisos (Div#(buswidth, 8, buswidthbytes),
  	     Div#(buswidth, 32, buswidthwords),
  	     Add#(aaa, 32, buswidth),
  	     Add#(bbb, TMul#(8, buswidthwords), 64),
  	     Add#(ccc, TMul#(32, buswidthwords), 256),
  	     Add#(ddd, buswidthwords, 8));
  
      FIFOF#(TLPData#(16)) tlpOutFifo <- mkFIFOF;
  
  
negative.code:     interface Axi3Slave slave;
  	interface Axi3SlaveWrite write;
  	   method Action writeAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
  				   Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) awid) if (writeBurstCount == 0);
  	      TLPLength tlplen = 2*(extend(burstLen) + 1);
  	      TLPMemory4DWHeader hdr_4dw = defaultValue;
  	      hdr_4dw.format = MEM_WRITE_4DW_DATA;
  	      hdr_4dw.tag = truncate(awid);
  	      hdr_4dw.reqid = my_id;
  	      hdr_4dw.nosnoop = SNOOPING_REQD;
  	      hdr_4dw.addr = addr[40-1:2];
  	      hdr_4dw.length = tlplen;
  	      hdr_4dw.firstbe = 4'hf;
  	      hdr_4dw.lastbe = 4'hf;
  	      TLPData#(16) tlp = defaultValue;
  	      tlp.sof = True;
  	      tlp.eof = False;
  	      tlp.hit = 7'h00;
  	      tlp.data = pack(hdr_4dw);
  	      tlp.be = 16'hffff;
  	      tlpOutFifo.enq(tlp);
  	      writeBurstCount <= zeroExtend(burstLen)+1;
  	      writeDwCount <= zeroExtend(burstLen)*fromInteger(valueOf(busWidthWords)) + fromInteger(valueOf(busWidthWords));
  	      writeTag <= truncate(awid);
             endmethod: writeAddr
  	   method Action writeData(Bit#(busWidth) data, Bit#(busWidthBytes) byteEnable, Bit#(1) last)
  	      provisos (Bits#(Vector#(busWidthWords, Bit#(32)), busWidth)) if (writeBurstCount > 0);
  	      writeBurstCount <= writeBurstCount - 1;
  	      Vector#(busWidthWords, Bit#(32)) v = unpack(data);
  	      writeDataMimo.enq(fromInteger(valueOf(busWidthWords)), v);
             endmethod: writeData
  	   method ActionValue#(Bit#(2)) writeResponse();
  	       return 0;
  