anchor.diff:      method Bit#(32)     statistics_vector();
   endinterface
   (* always_ready, always_enabled *)
  -interface TrimodemacbviTx_axis_mac;
  +interface TrimodemacTx_axis_mac;
       method Action      tdata(Bit#(8) v);
       method Action      tlast(Bit#(1) v);
       method Bit#(1)     tready();
  
positive.code: import XilinxCells::*;
  import GetPut::*;
  import AxiBits::*;
  
  (* always_ready, always_enabled *)
  (* always_ready, always_enabled *)
  interface TrimodemacbviGmii;
      method Action      rx_dv(Bit#(1) v);
      method Action      rx_er(Bit#(1) v);
      method Action      rxd(Bit#(8) v);
  
negative.code:     endinterface
      method speedis100 speedis100();
      method speedis10100 speedis10100();
      interface TrimodemacTx     tx;
          output_clock mac_aclk(tx_mac_aclk);
          output_reset reset(tx_reset) clocked_by (tx_mac_aclk);
          method ifg_delay(tx_ifg_delay) enable((*inhigh*) EN_tx_ifg_delay) clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method tx_statistics_valid statistics_valid() clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method tx_statistics_vector statistics_vector() clocked_by (tx_mac_aclk) reset_by (tx_reset);
      endinterface
      interface TrimodemacTx_axis_mac     tx_axis_mac;
          method tdata(tx_axis_mac_tdata) enable((*inhigh*) EN_tx_axis_mac_tdata) clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method tlast(tx_axis_mac_tlast) enable((*inhigh*) EN_tx_axis_mac_tlast) clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method tx_axis_mac_tready tready() clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method tuser(tx_axis_mac_tuser) enable((*inhigh*) EN_tx_axis_mac_tuser) clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method tvalid(tx_axis_mac_tvalid) enable((*inhigh*) EN_tx_axis_mac_tvalid) clocked_by (tx_mac_aclk) reset_by (tx_reset);
      endinterface
      interface TrimodemacPause     pause;
          method req(pause_req) enable((*inhigh*) EN_pause_req) clocked_by (tx_mac_aclk) reset_by (tx_reset);
          method val(pause_val) enable((*inhigh*) EN_pause_val) clocked_by (tx_mac_aclk) reset_by (tx_reset);
      endinterface
      schedule (gmii.rx_dv, gmii.rx_er, gmii.rxd, gmii.tx_en, gmii.tx_er, gmii.txd, mac.irq, mdc, mdio.i, mdio.o, mdio.t, pause.req, pause.val, rx.axis_filter_tuser, rx.statistics_valid, rx.statistics_vector, rx_axis_mac.tdata, rx_axis_mac.tlast, rx_axis_mac.tuser, rx_axis_mac.tvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wvalid, speedis100, speedis10100, tx.ifg_delay, tx.statistics_valid, tx.statistics_vector, tx_axis_mac.tdata, tx_axis_mac.tlast, tx_axis_mac.tready, tx_axis_mac.tuser, tx_axis_mac.tvalid) CF (gmii.rx_dv, gmii.rx_er, gmii.rxd, gmii.tx_en, gmii.tx_er, gmii.txd, mac.irq, mdc, mdio.i, mdio.o, mdio.t, pause.req, pause.val, rx.axis_filter_tuser, rx.statistics_valid, rx.statistics_vector, rx_axis_mac.tdata, rx_axis_mac.tlast, rx_axis_mac.tuser, rx_axis_mac.tvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wvalid, speedis100, speedis10100, tx.ifg_delay, tx.statistics_valid, tx.statistics_vector, tx_axis_mac.tdata, tx_axis_mac.tlast, tx_axis_mac.tready, tx_axis_mac.tuser, tx_axis_mac.tvalid);
  endmodule
  
  `ifdef FLUTE
  import TLM3         :: *;
  import Axi4         :: *;
  import AxiDefines   ::*;
  
  instance ToAxi4LRdWrSlave#(TrimodemacS_axi);
     function Axi4LRdWrSlave#(`SoC_PRM) toAxi4LRdWrSlave(TrimodemacS_axi s);
        return (interface Axi4LRdWrSlave#(`SoC_PRM);
           interface Axi4LRdSlave read;
  	    method Action arADDR(AxiAddr#(`SoC_PRM) addr); s.araddr(truncate(addr)); endmethod
  