anchor.diff:  } Axi4WriteData#(type busWidth, type busWidthBytes, type idWidth) deriving (Bits);
   
   typedef struct {
  -    Bit#(2) code;
  +    Bit#(2) resp;
       Bit#(idWidth) id;
   } Axi4WriteResponse#(type idWidth) deriving (Bits);
   
  
positive.code:     Bit#(8) len;
      Bit#(3) size; // assume matches bus width of Axi4Client
      Bit#(2) burst;  // drive with 2'b01
      Bit#(2) prot; // drive with 3'b000
      Bit#(3) cache; // drive with 4'b0011
      Bit#(idWidth) id;
  } Axi4ReadRequest#(type addrWidth, type idWidth) deriving (Bits);
  
  typedef struct {
      Bit#(busWidth) data;
      Bit#(2) code;
      Bit#(1) last;
      Bit#(idWidth) id;
  } Axi4ReadResponse#(type busWidth, type idWidth) deriving (Bits);
  
negative.code: } Axi3WriteData#(type busWidth, type busWidthBytes, type idWidth) deriving (Bits);
  
  typedef struct {
      Bit#(2) resp;
      Bit#(idWidth) id;
  } Axi3WriteResponse#(type idWidth) deriving (Bits);
  
  