anchor.diff:  
      module mkMemWriteClient#(Bit#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));
   
  -      Wire#(Bit#(1)) awready <- mkDWire(0);
  -      Wire#(Bit#(1)) wready <- mkDWire(0);
  -      Wire#(Bit#(1)) bvalid <- mkDWire(0);
  -      Wire#(Bit#(MemTagSize)) bid <- mkDWire(0);
  -      Wire#(Bit#(2)) bresp <- mkDWire(0);
  -
  -      FIFOF#(MemRequest)       awfifo   <- mkCFFIFOF();
  -      FIFOF#(MemData#(dataWidth)) wfifo <- mkCFFIFOF();
  -      FIFOF#(Bit#(MemTagSize))    bfifo <- mkCFFIFOF();
  +      let clock <- exposeCurrentClock();
  +      let mClock = clockOf(m);
  +      let reset <- exposeCurrentReset();
  +      let mReset = resetOf(m);
  +
  +      Wire#(Bit#(1)) awready <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(1)) wready <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(1)) bvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(MemTagSize)) bid <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(2)) bresp <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +
  +      FIFOF#(MemRequest)       awfifo;
  +      FIFOF#(MemData#(dataWidth)) wfifo;
  +      FIFOF#(Bit#(MemTagSize))    bfifo;
  +      if ( isAncestor(clock, mClock)) begin
  +	 awfifo   <- mkCFFIFOF();
  +	 wfifo <- mkCFFIFOF();
  +	 bfifo <- mkCFFIFOF();
  +      end
  +      else begin
  +	 awfifo   <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);
  +	 wfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);
  +	 bfifo <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);
  +      end
   
         rule rl_awaddr if (m.awvalid() == 1);
   	 let addr = m.awaddr();
  
positive.code: 	 let wdata = md.data;
  	 axiSlave.wdata(wdata);
  	 axiSlave.wlast(pack(wfifo.first.last));
  	 axiSlave.wstrb('hf);
  	 if (wfifo.first.last)
  	    wstrbfifo.deq();
        endrule
  
negative.code:       endrule   
        rule rl_done if (axiSlave.bvalid() == 1);
  	 let tag <- toGet(wtagfifo).get();
  	 bfifo.enq(extend(axiSlave.bid()));
        endrule
  
        interface PhysMemReadServer read_server;
  