anchor.diff:      endrule
   
       rule clkdiv_rule if (bvi_reset_reg != 0);
  -        let ds = dstate;
  -        let dc = dcounter;
  +        fifo_reset <= dfifo_reset_r.read();
  +    endrule
  +
  +    rule clkdividle_rule if (bvi_reset_reg != 0 && dstate == DIdle);
  +        item_req_wire.deq();
  +        Bit#(3) sric = 0;
  +        for (Integer i = 0; i < 3; i = i + 1)
  +            sric[i] = ctrl_reset_inc_ce_serdes[i].read();
  +        sync_reset_inc_ce <= sric;
  +        sync_bitslip <= ctrl_bitslip_serdes.read();
  +        dstate <= DValid;
  +        dcounter <= 3;
  +        iserdes_bitslip <= sync_bitslip;
  +    endrule
  +    rule state1_rule if (bvi_reset_reg != 0 && dstate == DValid);
  +        dcounter <= dcounter - 1;
  +        if (dcounter[2] == 1)
  +            begin
  +            dackint.send(1);
  +            dstate <= DLow;
  +            end
           Bit#(3) sric = sync_reset_inc_ce;
  -        let sbs = 0;
  -  
  -        dc = dc - 1;
  -        dreqpipe0 <= item_req_wire.read();
  -        dreqpipe1 <= dreqpipe0;
  -        fifo_reset <= dfifo_reset_r.read();
           sric[0] = 0;
           sric[1] = 0;
  +        sync_reset_inc_ce <= sric;
  +        sync_bitslip <= 0;
           iserdes_bitslip <= sync_bitslip;
  -        if (dstate == DIdle && dreqpipe1 == 1)
  -            begin
  -            for (Integer i = 0; i < 3; i = i + 1)
  -                sric[i] = ctrl_reset_inc_ce_serdes[i].read();
  -            sbs = ctrl_bitslip_serdes.read();
  -            dc = 3;
  -            ds = DValid;
  -            end
  -        if (dstate == DValid && dcounter[2] == 1)
  -            begin
  -            ds = DLow;
  -            end
  -        if (dstate == DLow && dreqpipe1 == 0)
  -            begin
  -            ds = DIdle;
  -            end
  -        dstate <= ds;
  -        dcounter <= dc;
  +    endrule
  +    rule state2_rule if (bvi_reset_reg != 0 && dstate == DLow);
  +        dackint.send(0);
  +        dstate <= DIdle;
  +        Bit#(3) sric = sync_reset_inc_ce;
  +        sric[0] = 0;
  +        sric[1] = 0;
           sync_reset_inc_ce <= sric;
  -        sync_bitslip <= sbs;
  -    endrule
  -    rule state1_rule if (bvi_reset_reg != 0 && dstate == DValid && dcounter[2] == 1);
  -        dackint.send(1);
  -    endrule
  -    rule state2_rule if (bvi_reset_reg != 0 && dstate == DLow && dreqpipe1 == 0);
  -        dackint.send(0);
  +        sync_bitslip <= 0;
  +        iserdes_bitslip <= sync_bitslip;
       endrule
   
       rule setrule;
  
positive.code:         qstate <= QOn;
      endrule
      rule qfsmqon_rule if (bvi_resets_reg.read() != 0 && qstate == QOn);
  // && busy_align_i == 1);
          qstate <= QOff;
      endrule
      rule qfsmqoff1_rule if (bvi_resets_reg.read() != 0 && qstate == QOff && serdes_counter <= 'h7fff);
  //&& busy_align_i == 0 
          ctrl_sample <= ctrl_samplein_i;
          this_aligned_reg <= 1;
          qstate <= QIdle;
      endrule
      rule qfsmqoff2_rule if (bvi_resets_reg.read() != 0 && qstate == QOff && serdes_counter > 'h7fff);
  //&& busy_align_i == 0 
          serdes_counter <= serdes_counter + 1;
          qstate <= QTrain;
      endrule
  
negative.code:     rule handinit_rule if (bvi_resets_reg.read() == 0);
          hstate <= HIdle;
          hcounter <= 0;
          end_handshake.clear();
      endrule
  
  