anchor.diff: +import GetPut::*;
  +import FIFO::*;
  +import FIFOF::*;
   import Clocks::*;
   
   interface Dsp48E1;
      method Bool     notEmpty();
      method Bit#(48) p();
  +   method Action deq();
   // Control: 4-bit (each) input: Control Inputs/Status Bits
      method Action alumode(Bit#(4) v);		// 4-bit input: ALU control input
      method Action carryinsel(Bit#(3) v);		// 3-bit input: Carry select input
  
positive.code:    method Bit#(48) p() if (last5Reg == 1);
        return dsp.p();
     endmethod
     method Action last(Bit#(1) v);
        lastWire <= v;
     endmethod
  endmodule
  
negative.code:    method Action last(Bit#(1) v);
  endinterface
  
  `ifndef BSIM
  (* always_ready, always_enabled *)
  interface PRIM_DSP48E1;
     method Bit#(48) p();
  