anchor.diff:                  CSRmcycle:              mcycle_csr;
                   CSRmtime:               mtime_csr;
                   CSRminstret:            minstret_csr;
  +                CSRmcycleh:             mcycleh_csr;
  +                CSRmtimeh:              mtimeh_csr;
  +                CSRminstreth:           minstreth_csr;
                   CSRmucounteren:         mucounteren_csr;
                   CSRmscounteren:         mscounteren_csr;
                   CSRmucycle_delta:       mucycle_delta_csr;
  
positive.code: endinterface
  
  module mkRVCsrFile#(
              Data hartid,                // Compile-time constant
              Bit#(64) mtime, Bool mtip,  // From RTC
              Bool msip,                  // From IPI
              Bool meip                   // From interrupt controller
          )(RVCsrFile);
  
      let verbose = False;
      File fout = stdout;
  
      RiscVISASubset isa = defaultValue;
      Data mvendorid     = 0; // non-commercial
      Data marchid       = 0; // not implemented
      Data mimpid        = 0; // not implemented
  
negative.code:                 CSRscycle:              (s_cy_field == 1);
                  CSRstime:               (s_tm_field == 1);
                  CSRsinstret:            (s_ir_field == 1);
                  CSRscycleh:             ((s_cy_field == 1) && is32bit);
                  CSRstimeh:              ((s_tm_field == 1) && is32bit);
                  CSRsinstreth:           ((s_ir_field == 1) && is32bit);
                  CSRmisa:                True;
                  CSRmvendorid:           True;
                  CSRmarchid:             True;
  