anchor.diff:     Bit#(8) idxOffset;
      } Region deriving (Eq,Bits,FShow);
   
  +typedef struct {DmaErrorType errorType;
  +		Bit#(32) pref; } DmaError deriving (Bits);
  +
   // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
   module mkSGListMMU#(DmaIndication dmaIndication)(SGListMMU#(addrWidth))
      provisos(Log#(MaxNumSGLists, listIdxSize),
  
positive.code:    // stage 4 (latnecy == 1)
     Vector#(2,FIFOF#(Bit#(addrWidth))) pageResponseFifos <- replicateM(mkFIFOF);
        
     let page_shift0 = fromInteger(valueOf(SGListPageShift0));
     let page_shift4 = fromInteger(valueOf(SGListPageShift4));
     let page_shift8 = fromInteger(valueOf(SGListPageShift8));
  
negative.code: 	 if (off.pageSize == 0) begin
  	    //FIXME offset
  	    //$display("mkSGListMMU.addr[%d].request.put: ERROR   ptr=%h off=%h\n", i, ptr, off);
  	    dmaErrorFifo.enq(DmaError { errorType: DmaErrorBadAddrTrans, pref: extend(ptr) });
  	 end
  	 //$display("p ages[%d].read %h", i, rp[i].first());
  	 portsel(pages, i).request.put(BRAMRequest{write:False, responseOnWrite:False,
  