anchor.diff:  
      rule addr_clock_crossing;
          addr_jtag.send(pack(addr));
  -   endrule
  -
  -   rule reset_addr if (bscan.sel() == 1 && !selected_delay);
  -       addrReg <= addr_jtag.read();  // first time USER1 selected, reset address
      endrule
   
      rule captureRule if (bscan.sel() == 1 && bscan.capture() == 1);
  
positive.code: 	  let d = fromMaybe(unpack(0), m);
  	  shift = pack(d);
         end
         bscan.tdo(shift[0]);
         let v = (shift >> 1);
         v[dsz-1] = bscan.tdi();
         shiftReg <= v;
  
negative.code:    Reg#(Bit#(asz)) addrReg <- mkReg(0, clocked_by tck, reset_by rst);
     Reg#(Bool) capture_delay <- mkReg(False, clocked_by tck, reset_by rst);
     Reg#(Bool) selected_delay <- mkReg(False, clocked_by tck, reset_by rst);
     Wire#(Bit#(1)) tdow <- mkDWire(0, clocked_by tck, reset_by rst);
     rule tdo;
        bscan.tdo(tdow);
     endrule
  
     rule selected_rule;
         selected_delay <= bscan.sel() == 1;
  