anchor.diff:  	     Add#(j__, TLog#(i__), 6),
   	     Mul#(k__, nMasters, TMax#(nMasters, TMax#(nMasters, numReadClientsActual))),
   	     Add#(l__, TLog#(h__), 6),
  -	     Mul#(m__, nMasters, TMax#(nMasters, nMasters))
  +	     Mul#(m__, nMasters, TMax#(nMasters, nMasters)),
  +             Add#(n__, addrWidth, 64),
  +             Add#(o__, 12, addrWidth)
         );
   
      Vector#(numReadClientsNull, MemReadClient#(dataWidth)) nullReadClients = replicate(null_mem_read_client());
      Vector#(numWriteClientsNull, MemWriteClient#(dataWidth)) nullWriteClients = replicate(null_mem_write_client());
   
  -   MemServer#(PhysAddrWidth,dataWidth,nMasters) reader <- mkMemServerR(indication, append(readClients,nullReadClients), mmus);
  -   MemServer#(PhysAddrWidth,dataWidth,nMasters) writer <- mkMemServerW(indication, append(writeClients,nullWriteClients), mmus);
  -   
  -   function PhysMemMaster#(PhysAddrWidth,dataWidth) mkm(Integer i) = (interface PhysMemMaster#(PhysAddrWidth,dataWidth);
  +   MemServer#(addrWidth,dataWidth,nMasters) reader <- mkMemServerR(indication, append(readClients,nullReadClients), mmus);
  +   MemServer#(addrWidth,dataWidth,nMasters) writer <- mkMemServerW(indication, append(writeClients,nullWriteClients), mmus);
  +   
  +   function PhysMemMaster#(addrWidth,dataWidth) mkm(Integer i) = (interface PhysMemMaster#(addrWidth,dataWidth);
   								 interface PhysMemReadClient read_client = reader.masters[i].read_client;
   								 interface PhysMemWriteClient write_client = writer.masters[i].write_client;
   							      endinterface);
  
positive.code: 	     Mul#(nrc, nMasters, numReadClients),
  	     Add#(b__, TLog#(nrc), 6),
  	     Add#(c__, TLog#(nwc), 6),
  	     Add#(TLog#(TDiv#(dataWidth, 8)), d__, BurstLenSize)
  	     );
  
     MemServer#(PhysAddrWidth,dataWidth,nMasters) reader <- mkMemServerR(indication,  readClients, mmus);
     MemServer#(PhysAddrWidth,dataWidth,nMasters) writer <- mkMemServerW(indication, writeClients, mmus);
     
     function PhysMemMaster#(PhysAddrWidth,dataWidth) mkm(Integer i) = (interface PhysMemMaster#(PhysAddrWidth,dataWidth);
  								 interface PhysMemReadClient read_client = reader.masters[i].read_client;
  								 interface PhysMemWriteClient write_client = writer.masters[i].write_client;
  							      endinterface);
  
negative.code: 
  module mkMemServer#(Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
  		    Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  		    Vector#(numMMUs,MMU#(addrWidth)) mmus,
  		    MemServerIndication indication)
     (MemServer#(addrWidth, dataWidth, nMasters))
     
     provisos (Max#(nMasters,numReadClients,numReadClientsActual),
  	     Add#(numReadClients,numReadClientsNull,numReadClientsActual),
  