anchor.diff:      Mul#(TDiv#(dsz, 32), 32, dsz));
      Clock epClock125 <- exposeCurrentClock();
      Reset epReset125 <- exposeCurrentReset();
  -   MakeResetIfc portalResetIfc <- mkReset(10, False, epClock125);
  -   let portalTop <- mkPortalTop(reset_by portalResetIfc.new_rst);
   
      PcieSplitter    splitter    <- mkPcieSplitter();
   
  
positive.code: 
     MemMasterEngine portalEngine <- mkMemMasterEngine(my_pciId);
     mkConnection(splitter.servers[portPortal], portalEngine.tlp);
     mkConnection(portalEngine.master, portalTop.slave);
  
     if (`NumberOfMasters > 0) begin
        AxiSlaveEngine#(dsz) dmaEngine <- mkAxiSlaveEngine(my_pciId);
        Vector#(`NumberOfMasters,Axi3Master#(40,dsz,6)) m_axis;   
        m_axis[0] <- mkAxiDmaMaster(portalTop.masters[0], reset_by portalResetIfc.new_rst);
        mkConnection(splitter.servers[portAxi], dmaEngine.tlp);
        mkConnection(m_axis[0], dmaEngine.slave);
     end
  
  
negative.code:       Integer intr_num = i+1;
        MSIX_Entry msixEntry = csr.msixEntry[intr_num];
        rule interruptRequest;
  	 if (ptinterrupt[i] && !interruptRequested[i])
  	    portalEngine.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));
  	 interruptRequested[i] <= ptinterrupt[i];
        endrule
     end
     interface msixEntry = csr.msixEntry;
     interface master = portalEngine.master;
     interface slave = dmaEngine.slave;
     interface interruptRequest = portalEngine.interruptRequest;
  endmodule: mkPcieHost
  
  (* no_default_clock, no_default_reset *)
  