anchor.diff:     ReqTup req;
      } Stage3Params deriving (Bits);
   
  +typedef struct {
  +   Offset off;
  +   Bit#(IndexWidth) pbase;
  +   Bit#(IndexWidth) idxOffset;
  +   SGListId ptr;
  +   } Stage4Params deriving (Bits);
  +
   // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
   module mkMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
      provisos(Log#(MaxNumSGLists, listIdxSize),
  
positive.code: 	    pbase = truncate(req.off>>page_shift0);
  	    idxOffset = params.idxOffset0;
  	 end
  	 offs0[i].enq(o);
  	 pbases[i].enq(pbase);
  	 idxOffsets1[i].enq(idxOffset);
  	 ptrs1[i].enq(req.id);
        endrule
        (* descending_urgency = "stage2, stage4" *)
        rule stage4; // Read relevant sglist entry
  	 let off <- toGet(offs0[i]).get();
  	 let pbase <- toGet(pbases[i]).get();
  	 let idxOffset <- toGet(idxOffsets1[i]).get();
  	 let ptr <- toGet(ptrs1[i]).get();
  	 Bit#(IndexWidth) p = pbase + idxOffset;
  	 if (off.pageSize == 0) begin
  	    if (verbose) $display("mkMMU::addr[%d].request.put: ERROR   ptr=%h off=%h\n", i, ptr, off);
  
negative.code:    Vector#(2, FIFOF#(Stage3Params)) stage3Params <- replicateM(mkFIFOF);
  
     // stage 3 (latency == 1)
     Vector#(2, FIFOF#(Stage4Params)) stage4Params <- replicateM(mkFIFOF);
  
     // stage 4 (latency == 2)
     BRAM2Port#(Bit#(entryIdxSize),Page0) pages <- mkBRAM2Server(bramConfig);
  