anchor.diff:     method Action                 fifo_wren(Bit#(1) v);
      method Action                 reset(Bit#(1) v);
      method Bit#(1)                fifo_wren_sync();
  -   method Reset                  fifo_reset();
  +   method Bit#(1)                fifo_reset();
      method Bit#(10)               dataout();
   endinterface: Iserdesbvi
   
  
positive.code:     Reset defaultReset <- exposeCurrentReset();
      ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
      Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
      FIFO18 dfifo <- mkFIFO18(serdes_clock, reset_by serbvi.fifo_reset);
      MakeResetIfc iodelay_reset <- mkReset(2, True, serdes_clock, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule resetrule if (serbvi.iodelay_reset_inc_ce()[2] == 1);
          iodelay_reset.assertReset();
      endrule
  
negative.code:       method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
        method                  fifo_wren(FIFO_WREN) enable((*inhigh*) en10) clocked_by (clkdiv);
        method FIFO_WREN_SYNC   fifo_wren_sync() clocked_by (clock);
        method FIFO_RESET       fifo_reset() clocked_by(clkdiv);
        method                  delay_wren(DELAY_WREN) enable((*inhigh*) en11) clocked_by (clkdiv);
        method                  reset(RESET) enable((*inhigh*) en16) clocked_by (clkdiv);
        method FIFO_DATAOUT  dataout() clocked_by(clkdiv);
     schedule (fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
           CF (fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  