anchor.diff:  	    else
   	       reqState <= Idle;
   	 end
  -	 if (head != tail)
  -	    $display("receiveReqHeadTail state=%d w0=%x w1=%x", reqState, w0, w1);
  +	 if (head != tail || verbose || True)
  +	    $display("receiveReqHeadTail state=%d w0=%x w1=%x head=%d tail=%d limit=%d", reqState, w0, w1, head, tail, reqLimitReg);
         endrule
   
         rule requestMessage if (reqState == RequestMessage);
  
positive.code: import ClientServer::*;
  import CtrlMux::*;
  
  import Pipe::*;
  import Portal::*;
  import MemTypes::*;
  
negative.code:       Reg#(Bit#(32)) reqHeadReg <- mkReg(0);
        Reg#(Bit#(32)) reqTailReg <- mkReg(0);
        Reg#(Bit#(16)) wordCountReg <- mkReg(0);
        Reg#(Bit#(16)) messageWordsReg <- mkReg(0);
        Reg#(Bit#(16)) methodIdReg <- mkReg(0);
        Reg#(SharedMemoryPortalState) reqState <- mkReg(Idle);
  
        rule updateReqHeadTail if (reqState == Idle && readyReg);
  	 $display("updateReqHeadTail");
  	 readEngine.readServers[0].request.put(MemengineCmd { sglId: sglIdReg,
  							     base: 0,
  							     burstLen: 16,
  