anchor.diff:     // Memory-mapped I/O read requests (LD and AMO_LR)
      // LRs are treated just like LDs, but we do not place any reservation on the address
      // (so a subsequent SC is guaranteed to fail).
  -   // TODO: Move this into rl_probe_and_immed_rsp, post MMU translation
  +   // TODO: Move this into rl_probe_and_immed_rsp, post MMU translation?
      // No caching, send request directly to fabric
   
      rule rl_io_read_req (   (rg_state == IO_REQ)
  -			&& ((rg_op == CACHE_LD) || is_AMO_LR));
  +			&& ((rg_op == CACHE_LD) || is_AMO_LR)
  +			&& (ctr_wr_rsps_pending.value == 0));
   
         if (cfg_verbosity > 1)
   	 $display ("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
  
positive.code:    endrule
  
     // ----------------------------------------------------------------
     // This rule probes the MMU and provides an immediate response for
     // memory (non-IO) requests, if possible, i.e., if
     //     VM off, LD or AMO_LR, cache hit
  
negative.code: 		     // Update cache line in cache
  		     let new_word64_set = fn_update_word64_set (word64_set, way_hit, vm_xlate_result.pa, rg_f3, rg_st_amo_val);
  		     ram_word64_set.a.put (bram_cmd_write, word64_set_in_cache, new_word64_set);
  		     fa_arm_the_load_stall (rg_f3);
  
  		     if (cfg_verbosity > 1) begin
  			$display ("        Write-Cache-Hit: pa 0x%0h word64 0x%0h", vm_xlate_result.pa, rg_st_amo_val);
  