anchor.diff:        pcie.pld.clk(c2b.o());
      endrule
   
  -//`ifdef PCIES5_SIM
      (* no_implicit_conditions *)
      rule pcie_rx;
         pcie.rx.in0(rx_in_wires[0]);
  
positive.code: module mkPcieS5Wrap#(Clock clk_100Mhz, Clock clk_50Mhz, Reset npor, Reset pin_perst)(PcieS5Wrap#(12, 32, 128));
  
     Vector#(8, Wire#(Bit#(1))) rx_in_wires <- replicateM(mkDWire(0));
  
  //`ifdef PCIES5_SIM
     Vector#(8, Wire#(Bit#(8))) rxdata_wires <- replicateM(mkDWire(0));
     Vector#(8, Wire#(Bit#(1))) rxdatak_wires <- replicateM(mkDWire(0));
     Vector#(8, Wire#(Bit#(1))) rxelecidle_wires <- replicateM(mkDWire(0));
     Vector#(8, Wire#(Bit#(3))) rxstatus_wires  <- replicateM(mkDWire(0));
     Vector#(8, Wire#(Bit#(1))) rxvalid_wires   <- replicateM(mkDWire(0));
     Vector#(8, Wire#(Bit#(1))) phystatus_wires <- replicateM(mkDWire(0));
  //`endif
  
     Clock default_clock <- exposeCurrentClock;
     Reset default_reset <- exposeCurrentReset;
  
negative.code:       pcie.phy.status6(phystatus_wires[6]);
        pcie.phy.status7(phystatus_wires[7]);
     endrule
  
     method Clock coreclkout_hip;
        return pcie.coreclkout.hip;
  