anchor.diff:     endinterface
   
      interface Parallel parallel;
  -      method Vector#(np, Bit#(40)) rx_parallel_data;
  -         Vector#(np, Bit#(40)) ret_val;
  -         for(Integer i=0; i < valueOf(np); i = i+1) begin
  +      method Vector#(PortNum, Bit#(40)) rx_parallel_data;
  +         Vector#(PortNum, Bit#(40)) ret_val;
  +         for(Integer i=0; i < valueOf(PortNum); i = i+1) begin
               ret_val[i] = unpack(xcvr.rx.pma_parallel_data)[39 + 80 * i : 80 * i];
            end
            return ret_val;
  
positive.code:    interface rx_clkout = out_rx_clk;
  
     interface Status status;
        method Vector#(np, Bit#(1)) rx_ready();
           Vector#(np, Bit#(1)) ret_val = map(getBit(rst.rx.ready), genVector);
           return ret_val;
        endmethod
  
        method Vector#(np, Bit#(1)) tx_ready();
           Vector#(np, Bit#(1)) ret_val = map(getBit(rst.tx.ready), genVector);
           return ret_val;
        endmethod
  
        method Vector#(np, Bit#(1)) pll_locked();
           Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.pll.locked), genVector);
           return ret_val;
        endmethod
  
        method Vector#(np, Bit#(1)) rx_is_lockedtodata();
           Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtodata), genVector);
           return ret_val;
        endmethod
  
        method Vector#(np, Bit#(1)) rx_is_lockedtoref();
           Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtoref), genVector);
           return ret_val;
        endmethod
     endinterface
  
negative.code:    interface Parallel#(np)      parallel;
  endinterface
  
  (* synthesize *)
  module mkEthPma#(Clock phy_mgmt_clk, Clock pll_ref_clk, Reset phy_mgmt_reset, Reset pll_ref_reset)(EthPmaIfc#(PortNum));
  
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  