anchor.diff:  	 // no need to send the request
         end else
   	 busWriteReqFifo.enq(req);
  -      writeAddrGenerator.request.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen, tag: extend(dest) });
  -
  -      writeReqObj <= req.sglId;
  -      writeReqDest <= dest;
  -      writeReqOffset <= req.offset[31:0];
  +      writeDestFifo.enq(dest);
      endrule
      
      rule rl_wr_data;
  -      let addrBeat <- writeAddrGenerator.addrBeat.get();
  -      let dest = addrBeat.tag[1:0];
  +      let dest = writeDestFifo.first();
         MemData#(dataBusWidth) md <- toGet(writeDataFifo).get();
         if (dest == 2)
   	 bramWriteDataFifo.enq(md);
  
positive.code: 	 dataFifo.enq(md);
        else
  	 busWriteDataFifo.enq(md);
        if (addrBeat.last)
  	 doneFifo.enq(tuple2(dest, md.tag));
        else if (md.last)
  	 doneFifo.enq(tuple2(dest, maxBound));
  
        writeDataDest <= dest;
        writeDataData <= md.data;
        writeDataLast <= md.last;
        writeBeatAddr <= addrBeat.addr[15:0];
        writeBeatByteCount <= addrBeat.bc;
        writeBeatLast <= addrBeat.last;
  
     endrule
  
     rule rl_wr_done;
  
negative.code: 	 bramReadReqFifo.enq(req);
        else
  	 busReadReqFifo.enq(req);
        readDestFifo.enq(dest);
     endrule
  
     rule rl_rd_data;
        let dest = readDestFifo.first();
        MemData#(dataBusWidth) md;
        if (dest == 2)
  	 md <- toGet(bramReadDataFifo).get();
        else
  	 md <- toGet(busReadDataFifo).get();
        if (md.last)
  	 readDestFifo.deq();
        readDataFifo.enq(md);
     endrule
  
     rule rl_wr_req;
  