anchor.diff:     // ---------------- LD-responses from DMem
   
      rule rl_exec_LD_response(cpu_state == STATE_EXEC_LD_RESPONSE);
  -      if (cfg_verbose > 1) $display("[%6d] RISCV(rl_exec_LD_response): STATE_EXEC_LD_RESPONSE", csr_cycle);
  +      if (cfg_verbose > 1) $display("[%7d] rl_exec_LD_response: ", csr_cycle);
   
         Decoded_Instr decoded = fv_decode(rg_instr);
   
  
positive.code:    // ---------------- ST-responses from DMem
  
     rule rl_exec_ST_response(cpu_state == STATE_EXEC_ST_RESPONSE);
        if (cfg_verbose > 1) $display("[%6d] RISCV_Spec.rl_exec_ST_response: STATE_EXEC_ST_RESPONSE", csr_cycle);
  
        DMem_Resp resp <- memory.dmem_resp;
  
  
negative.code:          // Main body of fa_exec(), dispatching to the sub functions
           // based on major OPCODE
  
           if (cfg_verbose != 0) $display("[%7d] fa_exec: instr 0x%08h", csr_cycle, instr);
  
           if      (decoded.opcode == op_LUI)      fa_exec_LUI();
           else if (decoded.opcode == op_AUIPC)    fa_exec_AUIPC();
  