anchor.diff:  
       Reg#(Data) sptbr_csr    = concatReg2(asid_field, sptbr_ppn_field);
   
  -    // TODO: Support 32-bit ISA
  -    Reg#(Data) scycle_csr   = readOnlyReg(mcycle_csr + mscycle_delta_csr);
  -    Reg#(Data) stime_csr    = readOnlyReg(mtime_csr + mstime_delta_csr);
  -    Reg#(Data) sinstret_csr = readOnlyReg(minstret_csr + msinstret_delta_csr);
  +    Bit#(64) scycle_counter   = cycle_counter + mscycle_delta_field;
  +    Bit#(64) stime_counter    = time_counter + mstime_delta_field;
  +    Bit#(64) sinstret_counter = instret_counter + msinstret_delta_field;
  +
  +    Reg#(Data) scycle_csr   = readOnlyReg(truncate(scycle_counter));
  +    Reg#(Data) stime_csr    = readOnlyReg(truncate(stime_counter));
  +    Reg#(Data) sinstret_csr = readOnlyReg(truncate(sinstret_counter));
  +
  +    // Upper 32-bits of CSRs for RV32: (these will just be unused copies of
  +    // the other cycle/time/instret registers for RV64)
  +    Reg#(Data) scycleh_csr   = readOnlyReg(truncateLSB(scycle_counter));
  +    Reg#(Data) stimeh_csr    = readOnlyReg(truncateLSB(stime_counter));
  +    Reg#(Data) sinstreth_csr = readOnlyReg(truncateLSB(sinstret_counter));
   
       // Machine Information Registers
       Reg#(Data) misa_csr      = readOnlyReg(getMISA(isa));
  
positive.code:     Reg#(Data) fcsr_csr   = addWriteSideEffect(zeroExtendReg(concatReg2(frm_field, fflags_field)), fs_field._write(2'b11));
  
      // User Timers and Counters
      // TODO: support 32-bit ISA
      Reg#(Data) cycle_csr   = readOnlyReg(mcycle_csr + mucycle_delta_csr);
      Reg#(Data) time_csr    = readOnlyReg(mtime_csr + mutime_delta_csr);
      Reg#(Data) instret_csr = readOnlyReg(minstret_csr + muinstret_delta_csr);
  
      // Supervisor
      Reg#(Data) sstatus_csr =  concatReg20(
  
negative.code: endinterface
  
  module mkRVCsrFile#(
              Data hartid,                      // Compile-time constant
              Bit#(64) time_counter, Bool mtip, // From RTC
              Bool msip,                        // From IPI
              Bool meip                         // From interrupt controller
          )(RVCsrFile);
  
      let verbose = False;
      File fout = stdout;
  
      RiscVISASubset isa = defaultValue;
      Bool is32bit       = valueOf(XLEN) == 32;
      Data mvendorid     = 0; // non-commercial
      Data marchid       = 0; // not implemented
      Data mimpid        = 0; // not implemented
  