anchor.diff:  
   
   
  -
  -
  -
  -
  -
  -
  -   interface NocNode tap;
  -   
  -      interface NocNodeIn in;
  -   
  -	 method Action frame(bit i );
  -	    frameinbit <= i ;
  -	 endmethod
  -   
  -	 method Action data( bit i );
  -	    datainbit <= i;
  -	 endmethod
  -
  -      endinterface
  -   
  -      interface NocNodeOut out;
  -      
  -	 method bit frame();
  -	    return frameinbit;
  -	 endmethod
  -      
  -	 method bit data();
  -	    return dataoutwire;
  -	 endmethod
  -   
  -      endinterface
  -   
  -   endinterface
  -
  -   interface Reg r;
  -
  -      method Action _write(a v);
  -	 data <= pack(v);
  -      endmethod
  -   
  -      method a _read();
  -	 return(unpack(data));
  -      endmethod
  -
  -   endinterface
  -
   endmodule
   
  
positive.code: 
  typedef struct {
  	Bit#(4) lsn;
  	Bit#(12) busy;
  	} FlowMessage deriving(Bits);
  
  
  
  interface NocNode;
     interface NocNodeIn in;
     interface NocNodeOut inrev;
     interface NocNodeOut out;
     interface NocNodeIn outrev;
  endinterface
  
  interface SpiReg#(type a);
     interface NocNode tap;
     interface FIFO#(a) send;
     interface FIFO#(a) recv;
  endinterface
  
  
  
  instance Connectable#(NocNodeOut, NocNodeIn);
     module mkConnection#(NocNodeOut out, NocNodeIn in)(Empty);
        rule move_data;
  	 in.frame(out.frame());
  	 in.data(out.data());
  	 endrule
     endmodule
  endinstance
  
  module mkNocNode#(Bit#(4) id)(NocNode#(a))
     provisos(Bits#(a,asize)),
              Log#(asize, k);
  
  
  
  
  
     NocLink east <- mkNocLink();
     NocLink west <- mkNocLink();
     NocHost host <- mkNocHost();
  
  
  
  endmodule
  /* numlinks controls how many fifos to other links there are */
  
  module mkLinkIn(
  
  module mkLinkIn(LinkIn#(a))
         provisos(Bits#(a,asize)),
  	        Log#(asize, k);
  
     // registers for receiving data messages
     Reg#(bit) framebit <- mkReg(0);
     Reg#(bit) databit <- mkReg(0);
     Reg#(Bit#(6)) incount <= mkReg(0);
     Reg#(a) shifter <- mkReg(0);
     Reg#(a) data <- mkReg(0);
  
  
     rule handleDataFrame;
        if (datainframebit == 0)
  	 begin
              dataincount <= 0;
  	 end
        else
  	 dataincount <= dataincount + 1;
     endrule
     
     rule handleDataInShift (datainframebit == 1);
        Bit#(SizeOf(DataMessage)) tmp = datainshifter;
        tmp = tmp >> 1;
        tmp[SizeOf(DataMessage)-1] = datainbit;
        datainshifter <= tmp;
        if (dataincount == (SizeOf(DataMessage) - 1))
           begin
  	 let msg
  	 end;
     endrule
     
     interface LinkIn;
     
     		method Action frame(bit i );
  	    frameinbit <= i ;
  	 endmethod
     
  	 method Action data( bit i );
  	    datainbit <= i;
  	 endmethod
  
  	       endinterface
  
  
  
  
  
     // registers for sending flow control messages
     Wire#(bit) fcoutwire <- mkDWire(0);
  
     // registers for sending data messages
     Wire#(bit) dataoutwire <- mkDWire(0);
  
     // registers for receiving flow control messages
     Reg#(bit) fcinbit <- mkReg(0);
     Reg#(bit) fcinframeinbit <- mkReg(0);
     Reg#(Bit#(6)) fcincount <= mkReg(0);
     Reg#(FlowMessage) fcinshifter <- mkReg(0);
     Reg#(FlowMessage) fcindata <- mkReg(0);
  
     // buffers for incoming messages
  
     FIFOF#(DataMessage) bufinhost <- mkSizedFIFOF(4);
     Vector#(numlinks, FIFOF#(DataMessage)) bufinlink = newVector; 
  
     for (Integer i = 0; i < numlinks; i = i + 1) 
     begin
       bufinlink[i] = mkSizedFIFOF#(4);
     end
     // XXX how to decode address?  Source routing? Node id?
  
  
  
  
negative.code:  * The data register is assumed to always be available, so an arriving
   * message must be removed ASAP or be overwritten 
   */
  
  typedef struct {
  	Bit#(4) address;
  