anchor.diff:     
      rule tag_rule if (inited && counter.positive);
         //tags.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, address:head_ptr, datain:True});
  -      //tags.upd(head_ptr, True);
  -      tags[head_ptr] <= True;
  +      //tags[head_ptr] <= True;
  +      begin
  +	 let t = tags.r2;
  +	 t[head_ptr] = 1;
  +	 tags.r2 <= t;
  +      end
         head_ptr <= head_ptr+1;
         tagFifo.enq(head_ptr);
         counter.decrement(1);
  
positive.code:    method ActionValue#(Bit#(TLog#(numTags))) complete;
  endinterface
  
  module mkTagGen(TagGen#(numTags))
     provisos(Log#(numTags,tsz));
     
     BRAM_Configure cfg = defaultValue;
     cfg.outFIFODepth = 1;
     //BRAM2Port#(Bit#(tsz),Bool) tags <- mkBRAM2Server(cfg);
     Vector#(numTags, Reg#(Bool)) tags <- replicateM(mkReg(False));
     //RegFile#(Bit#(tsz),Bool)     tags <- mkRegFile(0, fromInteger(valueOf(numTags)-1));
     Reg#(Bit#(tsz))        head_ptr <- mkReg(0);
     Reg#(Bit#(tsz))        tail_ptr <- mkReg(0);
     Reg#(Bool)               inited <- mkReg(False);
  
negative.code:    rule ret_rule;
        let tag <- toGet(retFifo).get;
        //tags.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:tag, datain:False});
        //tags[tag] <= False;
        begin
  	 let t = tags.r1;
  	 t[tag] = 0;
  	 tags.r1 <= t;
        end
        comp_state <= 1 | (comp_state << 1);
     endrule
  
     rule init_rule(!inited);
        //tags.portA.request.put(BRAMRequest{write:True,address:head_ptr,responseOnWrite:False,datain:False});
        //Not needed: tags[head_ptr] <= False;
        head_ptr <= head_ptr+1;
        inited <= head_ptr+1==0;
  