anchor.diff:  	    Bit#(bramAddrWidth) regFileAddr = truncate(addr << fromInteger(valueOf(TLog#(TDiv#(busDataWidth,8)))));
               let writeBE = writeByteEnableFifo.first;
               Bit#(dataWidthBytes) byteEnable = addrBeat.last ? writeBE : maxBound;
  -            br.request.put(BRAMRequestBE{writeen:byteEnable, responseOnWrite:False, address:regFileAddr, datain:resp.data});
  +            req_aws.enq(BRAMRequestBE{writeen:byteEnable, responseOnWrite:False, address:regFileAddr, datain:resp.data});
               if (verbose) $display("%d write_server.writeData %h %h %d", cycles, addr, resp.data, addrBeat.bc);
               if (addrBeat.last)
                  writeByteEnableFifo.deq;
  
positive.code:       readTagFifo.enq(tag);
        readLastFifo.enq(addrBeat.last);
        Bit#(bramAddrWidth) regFileAddr = truncate(addr << fromInteger(valueOf(TLog#(dataWidthBytes))));
        br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:regFileAddr, datain:?});
        if (verbose) $display("%d read_server.readData (a) %h %d last=%d", cycles, addr, burstCount, addrBeat.last);
     endrule
  
     interface PhysMemReadServer read_server;
  
negative.code: 
     AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
  
     FIFO#(PhysMemRequest#(busAddrWidth, busDataWidth)) req_ars <- mkFIFO1;
     FIFO#(Bit#(bramAddrWidth)) req_addr <- mkFIFO1;
     FIFO#(BRAMRequestBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), dataWidthBytes)) req_aws <- mkFIFO1;
  
     Reg#(Bit#(32)) cycles      <- mkReg(0);
     rule count if (verbose);
        cycles <= cycles + 1;
     endrule
  
     rule req_ar;
       let req <- toGet(req_ars).get;
       readAddrGenerator.request.put(req);
     endrule
  
     rule read_req;
        let addrBeat <- readAddrGenerator.addrBeat.get();
  