anchor.diff:     Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) copyReadAddr <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) copyWriteAddr <- mkReg(0);
  -   Reg#(DmaPointer) copyReadHandle <- mkReg(0);
  -   Reg#(DmaPointer) copyWriteHandle <- mkReg(0);
  +   Reg#(DmaPointer) copyReadPointer <- mkReg(0);
  +   Reg#(DmaPointer) copyWritePointer <- mkReg(0);
      Reg#(Bit#(32)) copyTag <- mkReg(0);
      Reg#(Bool) copyBusy <- mkReg(False);
      Reg#(Bit#(4)) cmdCtr <- mkReg(0);
  
positive.code:       
      rule copyReadRule (copyBusy && (copyReadCount != 0));
         //$display("copyRead %h, count %h", copyReadAddr, copyReadCount);
         copy_read_chan.readReq.put(DmaRequest{handle: copyReadHandle, address: copyReadAddr, burstLen: 1, tag: copyReadAddr[8:3]});
         copyReadAddr <= copyReadAddr + 8;
         copyReadCount <= copyReadCount - 8;
      endrule
  
negative.code:     rule copyReadWriteRule (copyBusy);
         let data <- copy_read_chan.readData.get;
         //$display("copyReadWrite addr %h", copyWriteAddr);
         copy_write_chan.writeReq.put(DmaRequest{pointer: copyWritePointer, address: copyWriteAddr, burstLen: 1, tag: copyWriteAddr[8:3]});
         copy_write_chan.writeData.put(DmaData{data: data.data, tag: copyWriteAddr[8:3]});
         copyWriteAddr <= copyWriteAddr + 8;
      endrule
  