anchor.diff:     interface slave = slavearr;
      interface interruptRequest = intr.interruptRequest;
      interface pci = traceif.pci;
  -   interface BscanTop bscanif = bscan;
  +   interface BscanTop bscanif = lbscan.loc[0];
   endmodule: mkPcieHost
   
   (* synthesize *)
   module mkSynthesizeablePortalTop(PortalTop#(40, DataBusWidth, PinType, NumberOfMasters));
      Clock defaultClock <- exposeCurrentClock();
  -   BscanTop local_bscan <- mkBscanTop(3); // Use USER3  (JTAG IDCODE address 0x22)
  +   //BscanTop local_bscan <- mkBscanTop(3); // Use USER3  (JTAG IDCODE address 0x22)
      let top <- mkPortalTop(`CLOCK_ARG `BSCAN_ARG);
      interface masters = top.masters;
      interface slave = top.slave;
  
positive.code:                               endinterface));
  `ifndef BSIM
     Reg#(Bit#(TAdd#(TlpTraceAddrSize,1))) bscanPcieTraceBramWrAddrReg <- mkReg(0);
     BscanBram#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) pcieBscanBram <- mkBscanBram(127, bscanPcieTraceBramWrAddrReg, bscan);
     mkConnection(pcieBscanBram.bramClient, traceif.tlpdata.bscanBramServer);
     rule tdorule;
        bscan.tdo(pcieBscanBram.data_out());
     endrule
  `endif
  
  
negative.code:    Vector#(NumberOfMasters,MemSlave#(40,DataBusWidth)) slavearr;
     MemInterrupt intr <- mkMemInterrupt(my_pciId);
     BscanTop bscan <- mkBscanTop(3); // Use USER3  (JTAG IDCODE address 0x22)
     BscanLocal lbscan <- mkBscanLocal(bscan, clocked_by bscan.tck, reset_by bscan.rst);
  
     Vector#(PortMax, MemMasterEngine) mvec;
     for (Integer i = 0; i < valueOf(PortMax) - 1 + valueOf(NumberOfMasters); i=i+1) begin
  