anchor.diff:        readResponseFifo.enq(MemData { data: data, tag: beat.tag, last: beat.last });
      endrule
   
  +   FIFOF#(BRAMRequest#(Bit#(TAdd#(TlpTraceAddrSize,1)),TimestampedTlpData)) bramRequestFifo <- mkFIFOF();
  +   mkConnection(toGet(bramRequestFifo), tlpdata.bramServer.request);
  +
      rule writeDataRule;
         let beat <- csrWag.addrBeat.get();
         let addr = beat.addr;
  
positive.code: 	    775: tlpdata.tlpTracing <= (dword != 0) ? True : False;
  
  	    768: begin
  		    tlpdata.bramServer.request.put(BRAMRequest{ write: False, responseOnWrite: False, address: bramMuxRdAddrReg, datain: unpack(0)});
  		    bramMuxRdAddrReg <= bramMuxRdAddrReg + 1;
  		 end
  	    792: tlpdata.pcieTraceBramWrAddr <= truncate(dword);
  
negative.code: import BRAM           :: *;
  import FIFOF          :: *;
  import GetPut         :: *;
  import Connectable    :: *;
  import PCIE           :: *;
  import Clocks         :: *;
  import PcieTracer     :: *;
  