anchor.diff:  import Instructions::*;
   import Trace::*;
   import RFile::*;
  +import Divider::*;
   
   typedef union tagged {
       struct { Ridx     r;    Bit#(32) data;               } WbREG;
  
positive.code:             tagged SLTI  .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(signedLT(rf.rd1(s.rs),signExtend(s.im))))});
              tagged SLTIU .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(         rf.rd1(s.rs)<signExtend(s.im)) )});
              tagged SLTU  .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(         rf.rd1(s.rs)<rf.rd2(s.rt)))     });
              /*tagged DIV   .s: 
                  action
                      Int#(32) r1 = unpack(rf.rd1(s.rs));
                      Int#(32) r2 = unpack(rf.rd2(s.rt));
                      r2 = r2 == 0 ? 1 : r2;  // make the simulator happy
                      lo <= pack(r1 / r2);
                      hi <= pack(r1 % r2);
                  endaction
              tagged DIVU  .s:
                  action
                      UInt#(32) r1 = unpack(rf.rd1(s.rs));
                      UInt#(32) r2 = unpack(rf.rd2(s.rt));
                      r2 = r2 == 0 ? 1 : r2;  // make the simulator happy
                      lo <= pack(r1 / r2);
                      hi <= pack(r1 % r2);
                  endaction*/
              tagged MULT  .s:
                  action
                      Int#(64) r1 = unpack(signExtend(rf.rd1(s.rs)));
  
negative.code:         jumpTo.deq;
      endrule
  
      rule exec(!pendingLoad.notEmpty && !dividerPending && !clearCache);
          Instr inst = unpack(instFIFO.first);
          let pc  = execPC.first;
          let pc1 = pc+1;
  