anchor.diff:     let derivedReset <- mkAsyncReset(2, defaultReset, derivedClock);
      let optionalReset = derivedReset; // noReset
      let syncIn <- mkSyncFIFO(16, defaultClock, defaultReset, derivedClock);
  -   SyncFIFOIfc#(Int#(48)) syncOut <- mkSyncFIFO(16, derivedClock, derivedReset, defaultClock);
  -   FIFOF#(Int#(48)) bramFifo <- mkSizedBRAMFIFOF(512, clocked_by derivedClock, reset_by derivedReset);
  +   FIFOF#(Int#(48)) bramFifo <- mkDualClockBramFIFOF(derivedClock, derivedReset, defaultClock, defaultReset);
   
      Reg#(Bit#(32)) cycles <- mkReg(0, clocked_by derivedClock, reset_by derivedReset);
      rule cyclesRule;
  
positive.code:       tile.request.put(req);
     endrule
     mkConnection(tile.response, toPut(bramFifo), clocked_by derivedClock, reset_by derivedReset);
     mkConnection(toGet(bramFifo), toPut(syncOut), clocked_by derivedClock, reset_by derivedReset);
     rule indRule;
        let r <- toGet(syncOut).get();
        $display("%d: indRule v=%x %d", cycles, r, r);
        ind.innerProd(pack(r));
     endrule
  
negative.code: 	 match { .a, .b, .first, .last, .alumode, .inmode, .opmode } = req;
  	 dsp.a(extend(pack(a)));
  	 dsp.b(extend(pack(b)));
  	 dsp.c('h22);
  	 dsp.d(0);
  	 //let opmode = 7'h45; // p = M + P
  	 //if (first)
  