anchor.diff:  endinterface
   
   interface PS7#(numeric type data_width, numeric type id_width, numeric type gpio_width, numeric type mio_width);
  -    interface Vector#(2, Can) can;
  -    interface Vector#(2, Core)core;
  +    //interface Vector#(2, Can) can;
  +    //interface Vector#(2, Core)core;
       interface Ddr#(10,1,1)    ddr;
  -    interface Vector#(4, Dma) dma;
  -    interface Vector#(2, Enet)enet;
  +    //interface Vector#(4, Dma) dma;
  +    //interface Vector#(2, Enet)enet;
       method Action             event_eventi(Bit#(1) v);
       method Bit#(1)            event_evento();
       method Bit#(2)            event_standbywfe();
  
positive.code:     method Bit#(1)            irq_p2f_usb0();
      method Bit#(1)            irq_p2f_usb1();
      method Bit#(mio_width)mio();
      interface AxiSlaveCommon#(data_width, id_width)    s_axi_acp;
      method Action             s_axi_acp_aruser(Bit#(5) v);
      method Action             s_axi_acp_awuser(Bit#(5) v);
      interface AxiSlaveCommon#(data_width, id_width)    s_axi_gp0;
      interface AxiSlaveCommon#(data_width, id_width)    s_axi_gp1;
      interface AxiSlaveHighSpeed#(data_width, id_width) s_axi_hp0;
      interface AxiSlaveHighSpeed#(data_width, id_width) s_axi_hp1;
      interface AxiSlaveHighSpeed#(data_width, id_width) s_axi_hp2;
      interface AxiSlaveHighSpeed#(data_width, id_width) s_axi_hp3;
      interface AxiMasterCommon#(data_width, id_width)   m_axi_gp0;
      interface AxiMasterCommon#(data_width, id_width)   m_axi_gp1;
      method Action             pjtag_tck(Bit#(1) v);
      interface Bidir#(1)       pjtag_td;
      method Action             pjtag_tms(Bit#(1) v);
      method Action             ps_clk(Bit#(1) v);
      method Action             ps_porb(Bit#(1) v);
      method Action             ps_srstb(Bit#(1) v);
      interface Vector#(2, Sdio)sdio;
      interface Vector#(2, Spi) spi;
      method Action             sram_intin(Bit#(1) v);
      method Action             trace_clk(Bit#(1) v);
      method Bit#(1)            trace_ctl();
      method Bit#(32)           trace_data();
      interface Vector#(2, Ttc) ttc;
      interface Vector#(2, Uart)uart;
      interface Vector#(2, Usb) usb;
      method Action             wdt_clk_in(Bit#(1) v);
      method Bit#(1)            wdt_rst_out();
      //schedule (datain, idatain, inc, ce) CF (datain, idatain, inc, ce);
  endinterface
  
  module mkPS7#(int data_width, int id_width, int gpio_width, int mio_width)(PS7#(data_width, id_width, gpio_width, mio_width));
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
  endmodule
  
negative.code: import DefaultValue::*;
  import XilinxCells::*;
  import Vector::*;
  import GetPut::*;
  
  typedef struct {
      Bit#(32)                  addr;
  