anchor.diff:     
      let verbose = False;
      
  -   RegFile#(Bit#(5),Bit#(BurstLenSize)) clientBurstLen <- mkRegFileFull();
  +   RegFile#(Bit#(TLog#(numTags)),Bit#(BurstLenSize)) clientBurstLen <- mkRegFileFull();
      Reg#(Bit#(BurstLenSize)) burstReg <- mkReg(0);
      Reg#(Bool)               firstReg <- mkReg(True);
      Reg#(Bool)                lastReg <- mkReg(False);
  
positive.code: 	 last = drq.last;
  	 dynamicAssert(last == (burstLen==1), "Last incorrect");
        end
        Bit#(TLog#(numTags)) tt = truncate(response_tag);
        clientData.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last},
  					       address:{tt,truncate(burstLen)}});
        if (last) begin
  	 tag_gen.returnTag(truncate(response_tag));
        end
        last_readData <= cycle_cnt;
        if (verbose) $display("mkMemReadInternal::read_data cyclediff %d", cycle_cnt-last_readData);
  
negative.code:       let request <- toGet(clientRequest).get();
        let physAddr <- mmus[request.req.sglId[31:16]].response.get;
        let rename_tag <- tag_gen.getTag;
        let burstLenBeats = request.req.burstLen >> beat_shift;
        clientBurstLen.upd(truncate(rename_tag), burstLenBeats);
        
        serverRequest.enq(RRec{req:request.req, pa:physAddr, client:request.client, rename_tag:extend(rename_tag)});
        if (verbose) $display("mkMemReadInternal::checkMmuResp: client=%d, tag=%d rename_tag=%d burstLen=%d", request.client, request.req.tag, rename_tag, burstLenBeats);
        if (verbose) $display("mkMemReadInternal::mmuResp %d %d", request.client, cycle_cnt-last_mmuResp);
        last_mmuResp <= cycle_cnt;
     endrule
     
     rule read_data;
        let response <- toGet(serverData).get();
        let drq <- serverProcessing.portA.response.get;
        let tag = drq.req_tag;
        let burstLen = clientBurstLen.sub(truncate(response.tag));
        let first   = firstReg;
        let last    = response.last;
  