anchor.diff:     // When imem32.instr [31:15] has lower half of 32b instr, cache it and fetch next 32 bits
   
      (* no_implicit_conditions, fire_when_enabled *)
  -   rule rl_fetch_next_32b (imem32.valid && cond_i32_odd_fetch_next);
  +   rule rl_fetch_next_32b (cond_i32_odd_fetch_next);
         Addr next_b32_addr = imem32.pc + 4;
         imem32.req (rg_f3, next_b32_addr, rg_priv, rg_sstatus_SUM, rg_mstatus_MXR, rg_satp);
         rg_cache_addr <= imem32.pc;
  
positive.code: 
     Integer verbosity = 0;
  
     // This register holds the actual PC value (which can be +/-2 from
     // the address given to the ICache.
     Reg #(WordXL)  rg_pc  <- mkRegU;
  
     // These registers caches the last output of imem32 (imem32.pc, and imem32.instr [31:16])
     Reg #(WordXL)    rg_cache_addr <- mkReg ('1);
     Reg #(Bit #(16)) rg_cache_b16  <- mkRegU;
  
     // The following hold args of the 'req' method.
     Reg #(Bit #(3))  rg_f3          <- mkRegU;
     Reg #(Priv_Mode) rg_priv        <- mkRegU;
     Reg #(Bit #(1))  rg_sstatus_SUM <- mkRegU;
     Reg #(Bit #(1))  rg_mstatus_MXR <- mkRegU;
  
negative.code:       // (the 16b we've already got is saved in r16_cache_b16).
        // Note: since we know it's a 32b instr, this next fetch is not speculative, so ok if it page faults.
        if (   is_addr_odd16 (addr)
  	  && (imem32.valid && (! imem32.exc))
  	  && (addr_of_b32 == imem32.pc)
  	  && is_32b_instr (imem32.instr [31:16]))
  	 begin
  