anchor.diff:  import StmtFSM::*;
   import FIFO::*;
   
  +// for PCIE
  +import Connectable       :: *;
  +import Xilinx            :: *;
  +import XilinxPCIE        :: *;
  +import Xilinx7PcieBridge :: *;
  +import PcieToAxiBridge   :: *;
   
   // portz libraries
   import AxiMasterSlave::*;
  
positive.code: `ifndef BSIM
     interface StdAxi3Master m_axi = axi_master;
  `endif
  endmodule
  
  import "BDPI" function Action      initPortal(Bit#(32) d);
  
negative.code: // defined by user
  import Memcpy::*;
  
  interface AxiTop;
     interface StdAxi3Slave     ctrl;
     interface StdAxi3Master    m_axi;
     interface ReadOnly#(Bool)  interrupt;
     interface LEDS             leds;
  endinterface
  
  module mkAxiTop(Top);
  
     DMAIndicationProxy dmaIndicationProxy <- mkDMAIndicationProxy(9);
     // dma read channel 0 is reserved for memcpy read path
  