anchor.diff:          dfifo.wren(fifo_wren_sync.read());
       endrule
   
  +    rule handinit_rule if (bvi_resets_reg.read() == 0);
  +        hstate <= HIdle;
  +        hcounter <= 0;
  +        item_req_wire.send(0);
  +        serbvi.endhandshake(0);
  +    endrule
  +
  +    rule hand_rule if (bvi_resets_reg.read() != 0);
  +        let hs = hstate;
  +        let hend = 0;
  +        let hc = hcounter;
  +        hc = hc + 1;
  +        if (hstate == HIdle && serbvi.starthandshake() == 1)
  +            begin
  +            hc = 0;
  +            hs = HHigh;
  +            end
  +        if (hstate == HHigh && dackint.read() == 1)
  +            begin
  +            hc = 0;
  +            hs = HLow;
  +            end
  +        if (hstate == HHigh && hcounter >= 'h20)
  +            begin
  +            hend = 1;
  +            hs = HIdle;
  +            end
  +        if (hstate == HLow && (dackint.read() == 0 || hcounter >= 'h20))
  +            begin
  +            hend = 1;
  +            hs = HIdle;
  +            end
  +        serbvi.endhandshake(hend);
  +        hstate <= hs;
  +        hcounter <= hc;
  +    endrule
  +    rule hstate1_rule if (bvi_resets_reg.read() != 0 && hstate == HIdle && serbvi.starthandshake() == 1);
  +        item_req_wire.send(1);
  +    endrule
  +    rule hstate2_rule if (bvi_resets_reg.read() != 0 && hstate == HHigh && dackint.read() == 1);
  +        item_req_wire.send(0);
  +    endrule
  +
       rule serdesrule;
           serbvi.align_start(align_start);
           serbvi.autoalign(autoalign);
  
positive.code:     method CTRL_FIFO_RESET_o   ctrl_fifo_reset() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method CTRL_RESET_INC_CE_o ctrl_reset_inc_ce() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method                  dackint(DACKINT) enable((*inhigh*) en19) clocked_by(clock);
      schedule (dackint, ctrl_reset_inc_ce, itemreq, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap)
           CF (dackint, ctrl_reset_inc_ce, itemreq, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  
negative.code:     Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) ctrl_data <- mkReg(0);
      Reg#(HState)  hstate <- mkReg(HIdle);
      Reg#(Bit#(6)) hcounter <- mkReg(0);
      SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  
      rule reset_clock_rule;
          bvi_resets_reg.send(bvi_reset_reg);
      endrule
  
      rule wrensyncr_rule if (bvi_reset_reg == 0);
          dfifo_wren_r <= 0;
  