anchor.diff:      Vector#(LdQSize, Reg#(Bool))                ld_acq             <- replicateM(mkRegU);
       Vector#(LdQSize, Reg#(Bool))                ld_rel             <- replicateM(mkRegU);
       Vector#(LdQSize, Reg#(Maybe#(PhyDst)))      ld_dst             <- replicateM(mkRegU);
  -    Vector#(LdQSize, Ehr#(3, Addr))             ld_paddr           <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))             ld_isMMIO          <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, ByteEn))           ld_shiftedBE       <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))             ld_computed        <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Addr))             ld_paddr           <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Bool))             ld_isMMIO          <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, ByteEn))           ld_shiftedBE       <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Bool))             ld_computed        <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, Bool))             ld_inIssueQ        <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))             ld_executing       <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))             ld_done            <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Bool))             ld_executing       <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Bool))             ld_done            <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, Bool))             ld_killed          <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Maybe#(StQTag)))   ld_olderSt         <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))             ld_olderStVerified <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Maybe#(StQTag)))   ld_olderSt         <- replicateM(mkEhr(?));
  +    Vector#(LdQSize, Ehr#(2, Bool))             ld_olderStVerified <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, Maybe#(StQTag)))   ld_readFrom        <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, Maybe#(LdStQTag))) ld_depLdQDeq       <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Maybe#(LdStQTag))) ld_depLdEx         <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, Maybe#(SBIndex)))  ld_depStQDeq       <- replicateM(mkEhr(?));
   `ifndef TSO_MM
  +    Vector#(LdQSize, Ehr#(3, Maybe#(LdStQTag))) ld_depLdEx         <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, Maybe#(SBIndex)))  ld_depSBDeq        <- replicateM(mkEhr(?));
   `endif
       Vector#(LdQSize, Ehr#(3, Maybe#(SpecTag)))  ld_specTag         <- replicateM(mkEhr(?));
       Vector#(LdQSize, Ehr#(3, SpecBits))         ld_specBits        <- replicateM(mkEhr(?));
       // wrong-path load filter (must init to all False)
  -    Vector#(LdStQSize, Reg#(Bool))              ld_waitWPResp      <- replicateM(mkReg(False));
  +    Vector#(LdQSize, Ehr#(1, Bool))             ld_waitWPResp      <- replicateM(mkEhr(False));
       // enq/deq ptr
       Reg#(LdQTag)    ld_enqP <- mkReg(0);
       Ehr#(2, LdQTag) ld_deqP <- mkEhr(0);
   
  -    // Ports of each EHR used in each method or rule
  +    // Ports of each EHR used in each method or rule ("write" means the write
  +    // port is used, "assert" means the port is only used for assert in
  +    // simulation)
       let ld_valid_getKill   = getVEhrPort(ld_valid, 0);
       let ld_valid_findIss   = getVEhrPort(ld_valid, 0);
  -    let ld_valid_wrongSpec = getVEhrPort(ld_valid, 0);
  -    let ld_valid_deq       = getVEhrPort(ld_valid, 0); // write
  +    let ld_valid_wrongSpec = getVEhrPort(ld_valid, 0); // write
  +    let ld_valid_deqLd     = getVEhrPort(ld_valid, 0); // write
       let ld_valid_evict     = getVEhrPort(ld_valid, 1);
       let ld_valid_updAddr   = getVEhrPort(ld_valid, 1);
       let ld_valid_issue     = getVEhrPort(ld_valid, 1);
       let ld_valid_enqIss    = getVEhrPort(ld_valid, 1); // assert
  -    let ld_valid_respLd    = getVEhrPort(ld_valid, 1); // assert
  +    let ld_valid_resp      = getVEhrPort(ld_valid, 1); // assert
       let ld_valid_enq       = getVEhrPort(ld_valid, 1); // write
  +
  +    let ld_paddr_deqLd   = getVEhrPort(ld_paddr, 0);
  +    let ld_paddr_evict   = getVEhrPort(ld_paddr, 0);
  +    let ld_paddr_updAddr = getVEhrPort(ld_paddr, 0); // write
  +    let ld_paddr_issue   = getVEhrPort(ld_paddr, 1);
  +    let ld_paddr_enqIss  = getVEhrPort(ld_paddr, 1); // assert
  +    let ld_paddr_resp    = getVEhrPort(ld_paddr, 1);
  +
  +    let ld_isMMIO_findIss = getVEhrPort(ld_isMMIO, 0);
  +    let ld_isMMIO_evict   = getVEhrPort(ld_isMMIO, 0); // assert
  +    let ld_isMMIO_deqLd   = getVEhrPort(ld_isMMIO, 0);
  +    let ld_isMMIO_updAddr = getVEhrPort(ld_isMMIO, 0); // write
  +    let ld_isMMIO_issue   = getVEhrPort(ld_isMMIO, 1); // assert
  +    let ld_isMMIO_enqIss  = getVEhrPort(ld_isMMIO, 1); // assert
  +
  +    let ld_shiftedBE_deqLd   = getVEhrPort(ld_shiftedBE, 0);
  +    let ld_shiftedBE_updAddr = getVEhrPort(ld_shiftedBE, 0); // write
  +    let ld_shiftedBE_issue   = getVEhrPort(ld_shiftedBE, 1);
  +    let ld_shiftedBE_enqIss  = getVEhrPort(ld_shiftedBE, 1); // assert
  +
  +    let ld_computed_findIss = getVEhrPort(ld_computed, 0);
  +    let ld_computed_deqLd   = getVEhrPort(ld_computed, 0);
  +    let ld_computed_evict   = getVEhrPort(ld_computed, 0); // assert
  +    let ld_computed_updAddr = getVEhrPort(ld_computed, 0); // write
  +    let ld_computed_issue   = getVEhrPort(ld_computed, 1);
  +    let ld_computed_enqIss  = getVEhrPort(ld_computed, 1); // assert
  +    let ld_computed_resp    = getVEhrPort(ld_computed, 1); // assert
  +    let ld_computed_enq     = getVEhrPort(ld_computed, 1); // write
  +
  +    let ld_inIssueQ_findIss = getVEhrPort(ld_inIssueQ, 0);
  +    let ld_inIssueQ_updAddr = getVEhrPort(ld_inIssueQ, 0); // assert
  +    let ld_inIssueQ_issue   = getVEhrPort(ld_inIssueQ, 0); // write
  +    let ld_inIssueQ_enqIss  = getVEhrPort(ld_inIssueQ, 1); // write
  +    let ld_inIssueQ_enq     = getVEhrPort(ld_inIssueQ, 2); // write
  +
  +    let ld_executing_findIss = getVEhrPort(ld_executing, 0);
  +    let ld_executing_getKill = getVEhrPort(ld_executing, 0); // assert
  +    let ld_executing_evict   = getVEhrPort(ld_executing, 0);
  +    let ld_executing_updAddr = getVEhrPort(ld_executing, 0);
  +    let ld_executing_issue   = getVEhrPort(ld_executing, 0); // write
  +    let ld_executing_enqIss  = getVEhrPort(ld_executing, 1); // assert
  +    let ld_executing_resp    = getVEhrPort(ld_executing, 1); // assert
  +    let ld_executing_enq     = getVEhrPort(ld_executing, 1); // write
  +
  +    let ld_done_deqLd  = getVEhrPort(ld_done, 0);
  +    let ld_done_issue  = getVEhrPort(ld_done, 0); // assert
  +    let ld_done_enqIss = getVEhrPort(ld_done, 0); //assert
  +    let ld_done_resp   = getVEhrPort(ld_done, 0); // write
  +    let ld_done_enq    = getVEhrPort(ld_done, 1); // write
  +
  +    let ld_killed_getKill = getVEhrPort(ld_killed, 0); // assert
  +    let ld_killed_deqLd   = getVEhrPort(ld_killed, 0);
  +    let ld_killed_evict   = getVEhrPort(ld_killed, 0); // write
  +    let ld_killed_updAddr = getVEhrPort(ld_killed, 1); // write
  +    let ld_killed_enqIss  = getVEhrPort(ld_killed, 2); // assert
  +    let ld_killed_enq     = getVEhrPort(ld_killed, 2); // write
  +
  +    let ld_olderSt_deqLd  = getVEhrPort(ld_olderSt, 0);
  +    let ld_olderSt_verify = getVEhrPort(ld_olderSt, 0);
  +    let ld_olderSt_deqSt  = getVEhrPort(ld_olderSt, 0); // write
  +    let ld_olderSt_enq    = getVEhrPort(ld_olderSt, 1); // write
  +
  +    let ld_olderStVerified_deqLd = getVEhrPort(ld_olderStVerified, 0);
  +    let ld_olderStVerified_verify = getVEhrPort(ld_olderStVerified, 0); // write
  +    let ld_olderStVerified_enq = getVEhrPort(ld_olderStVerified, 1); // write
  +
  +    let ld_readFrom_evict = getVEhrPort(ld_readFrom, 0);
  +    let ld_readFrom_issue = getVEhrPort(ld_readFrom, 0); // write
  +    let ld_readFrom_deqSt = getVEhrPort(ld_readFrom, 1); // write
  +    let ld_readFrom_enq   = getVEhrPort(ld_readFrom, 2); // write
  +
  +    let ld_depLdQDeq_findIss = getVEhrPort(ld_depLdQDeq, 0);
  +    let ld_depLdQDeq_deqLd   = getVEhrPort(ld_depLdQDeq, 0); // write
  +    let ld_depLdQDeq_issue   = getVEhrPort(ld_depLdQDeq, 1); // write
  +    let ld_depLdQDeq_enqIss  = getVEhrPort(ld_depLdQDeq, 2); // assert
  +    let ld_depLdQDeq_enq     = getVEhrPort(ld_depLdQDeq, 2); // write
  +
  +    let ld_depStQDeq_findIss = getVEhrPort(ld_depStQDeq, 0);
  +    let ld_depStQDeq_issue   = getVEhrPort(ld_depStQDeq, 0); // write
  +    let ld_depStQDeq_enqIss  = getVEhrPort(ld_depStQDeq, 1); // assert
  +    let ld_depStQDeq_deqSt   = getVEhrPort(ld_depStQDeq, 1); // write
  +    let ld_depStQDeq_enq     = getVEhrPort(ld_depStQDeq, 2); // write
  +
  +`ifndef TSO_MM
  +    let ld_depLdEx_findIss = getVEhrPort(ld_depLdEx, 0);
  +    let ld_depLdEx_issue   = getVEhrPort(ld_depLdEx, 0); // write
  +    let ld_depLdEx_enqIss  = getVEhrPort(ld_depLdEx, 1); // assert
  +    let ld_depLdEx_enq     = getVEhrPort(ld_depLdEx, 1); // write
  +
  +    let ld_depSBDeq_findIss = getVEhrPort(ld_depSBDeq, 0);
  +    let ld_depSBDeq_issue   = getVEhrPort(ld_depSBDeq, 0); // write
  +    let ld_depSBDeq_enqIss  = getVEhrPort(ld_depSBDeq, 1); // assert
  +    let ld_depSBDeq_wakeSB  = getVEhrPort(ld_depSBDeq, 1); // write
  +    let ld_depSBDeq_enq     = getVEhrPort(ld_depSBDeq, 2); // write
  +`endif
  +
  +    let ld_specTag_getKill = getVEhrPort(ld_specTag, 0);
  +    let ld_specTag_deqLd   = getVEhrPort(ld_specTag, 0);
  +    let ld_specTag_updAddr = getVEhrPort(ld_specTag, 0); // write
  +    let ld_specTag_enq     = getVEhrPort(ld_specTag, 1); // write
  +
  +    let ld_specBits_wrongSpec   = getVEhrPort(ld_specBits, 0); // write
  +    let ld_specBits_deqLd       = getVEhrPort(ld_specBits, 0); // C with wrongSpec
  +    let ld_specBits_updAddr     = getVEhrPort(ld_specBits, 0); // C with wrongSpec
  +    let ld_specBits_enqIss      = getVEhrPort(ld_specBits, 0); // C with wrongSpec
  +    let ld_specBits_enq         = getVEhrPort(ld_specBits, 0); // write, C with wrongSpec
  +    let ld_specBits_correctSpec = getVEhrPort(ld_specBits, 1); // write
  +
  +    let ld_waitWPResp_hit       = getVEhrPort(ld_waitWPResp, 0);
  +    let ld_waitWPResp_deqLd     = getVEhrPort(ld_waitWPResp, 0);
  +    let ld_waitWPResp_updAddr   = getVEhrPort(ld_waitWPResp, 0);
  +    let ld_waitWPResp_issue     = getVEhrPort(ld_waitWPResp, 0); // assert
  +    let ld_waitWPResp_resp      = getVEhrPort(ld_waitWPResp, 0); // write
  +    let ld_waitWPResp_wrongSpec = getVEhrPort(ld_waitWPResp, 0); // write
  +
  +    Reg#(LdQTag) ld_deqP_deqLd  = ld_deqP[0]; // write
  +    Reg#(LdQTag) ld_deqP_verify = ld_deqP[0]; // in TSO, C with deqLd
  +    Reg#(LdQTag) ld_deqP_deqSt  = ld_deqP[1];
   
       // SQ
       // entry valid bits
  -    Vector#(LdQSize, Ehr#(3, Bool))            st_valid     <- replicateM(mkEhr(False));
  +    Vector#(StQSize, Ehr#(2, Bool))            st_valid     <- replicateM(mkEhr(False));
       // entry contents
  -    Vector#(LdQSize, Reg#(InstTag))            st_instTag   <- replicateM(mkRegU);
  -    Vector#(LdQSize, Reg#(StQMemFunc))         st_memFunc   <- replicateM(mkRegU);
  -    Vector#(LdQSize, Reg#(ByteEn))             st_byteEn    <- replicateM(mkRegU);
  -    Vector#(LdQSize, Reg#(Bool))               st_acq       <- replicateM(mkRegU);
  -    Vector#(LdQSize, Reg#(Bool))               st_rel       <- replicateM(mkRegU);
  -    Vector#(LdQSize, Reg#(Maybe#(PhyDst)))     st_dst       <- replicateM(mkRegU);
  -    Vector#(LdQSize, Ehr#(3, Addr))            st_paddr     <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))            st_isMMIO    <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, ByteEn))          st_shiftedBE <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Data))            st_stData    <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))            st_computed  <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Bool))            st_verified  <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, Maybe#(SpecTag))) st_specTag   <- replicateM(mkEhr(?));
  -    Vector#(LdQSize, Ehr#(3, SpecBits))        st_specBits  <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Reg#(InstTag))            st_instTag   <- replicateM(mkRegU);
  +    Vector#(StQSize, Reg#(StQMemFunc))         st_memFunc   <- replicateM(mkRegU);
  +    Vector#(StQSize, Reg#(ByteEn))             st_byteEn    <- replicateM(mkRegU);
  +    Vector#(StQSize, Reg#(Bool))               st_acq       <- replicateM(mkRegU);
  +    Vector#(StQSize, Reg#(Bool))               st_rel       <- replicateM(mkRegU);
  +    Vector#(StQSize, Reg#(Maybe#(PhyDst)))     st_dst       <- replicateM(mkRegU);
  +    Vector#(StQSize, Ehr#(2, Addr))            st_paddr     <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(2, Bool))            st_isMMIO    <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(3, ByteEn))          st_shiftedBE <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(1, Data))            st_stData    <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(2, Bool))            st_computed  <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(2, Bool))            st_verified  <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(3, Maybe#(SpecTag))) st_specTag   <- replicateM(mkEhr(?));
  +    Vector#(StQSize, Ehr#(3, SpecBits))        st_specBits  <- replicateM(mkEhr(?));
       // enq/deq ptr
       Reg#(StQTag)    st_enqP <- mkReg(0);
       Ehr#(2, StQTag) st_deqP <- mkEhr(0);
       Ehr#(2, StQTag) st_verifyP <- mkEhr(0);
  +
  +    let st_valid_wrongSpec = getVEhrPort(st_valid, 0); // write
  +    let st_valid_verify    = getVEhrPort(st_valid, 0);
  +    let st_valid_updAddr   = getVEhrPort(st_valid, 0); // assert
  +    let st_valid_issue     = getVEhrPort(st_valid, 0);
  +    let st_valid_deqSt     = getVEhrPort(st_valid, 0); // write
  +    let st_valid_enq       = getVEhrPort(st_valid, 1); // write
  +
  +    let st_paddr_updAddr = getVEhrPort(st_paddr, 0); // write
  +    let st_paddr_issue   = getVEhrPort(st_paddr, 1);
  +    let st_paddr_deqSt   = getVEhrPort(st_paddr, 1);
  +
  +    let st_isMMIO_verify  = getVEhrPort(st_isMMIO, 0);
  +    let st_isMMIO_updAddr = getVEhrPort(st_isMMIO, 0); // write
  +    let st_isMMIO_deqSt   = getVEhrPort(st_isMMIO, 1);
  +
  +    let st_shiftedBE_updAddr = getVEhrPort(st_shiftedBE, 0); // write
  +    let st_shiftedBE_issue   = getVEhrPort(st_shiftedBE, 1);
  +    let st_shiftedBE_deqSt   = getVEhrPort(st_shiftedBE, 1);
  +    
  +    let st_stData_issue   = getVEhrPort(st_stData, 0);
  +    let st_stData_deqSt   = getVEhrPort(st_stData, 0);
  +    let st_stData_updData = getVEhrPort(st_stData, 0); // write
  +
  +    let st_computed_verify  = getVEhrPort(st_computed, 0);
  +    let st_computed_updAddr = getVEhrPort(st_computed, 0); // write
  +    let st_computed_issue   = getVEhrPort(st_computed, 1);
  +    let st_computed_deqSt   = getVEhrPort(st_computed, 1);
  +    let st_computed_enq     = getVEhrPort(st_computed, 1); // write
  +
  +    let st_verified_wrongSpec = getVEhrPort(st_verified, 0);
  +    let st_verified_verify    = getVEhrPort(st_verified, 0); // write
  +    let st_verified_enq       = getVEhrPort(st_verified, 1); // write
  +
  +    let st_specTag_updAddr = getVEhrPort(st_specTag, 0); // write
  +    let st_specTag_deqSt   = getVEhrPort(st_specTag, 1);
  +    let st_specTag_enq     = getVEhrPort(st_specTag, 1); // write
  +
  +    let st_specBits_wrongSpec   = getVEhrPort(st_specBits, 0); // write
  +    let st_specBits_updAddr     = getVEhrPort(st_specBits, 0); // C with wrongSpec
  +    let st_specBits_deqSt       = getVEhrPort(st_specBits, 0); // C with wrongSpec
  +    let st_specBits_enq         = getVEhrPort(st_specBits, 0); // write, C with wrongSpec
  +    let st_specBits_correctSpec = getVEhrPort(st_specBits, 1); // write
   
       // FIFO of LSQ tags that try to issue, there should be no replication in it
       LSQIssueLdQ issueLdQ <- mkLSQIssueLdQ;
  
positive.code:     // updated LQ entry into issueQ; this can create problem because the new
      // updated load may be immediately issued to execution in the same cycle
      // later.
      // - Only one of deqLd and verifySt can fire at one cycle, because of
      // sequential verification requirement.
  
      // W.r.t wrongSpec:
      // getKillLd < wrongSpec (they fire in same rule)
  
negative.code:         doAssert(!ld_isMMIO_enqIss[info.tag],
                   "enq issueQ entry cannot be MMIO");
          doAssert(!isValid(ld_depLdQDeq_enqIss[info.tag]) &&
  `ifndef TSO_MM
                   !isValid(ld_depLdEx_enqIss[info.tag]) &&
                   !isValid(ld_depSBDeq_enqIss[info.tag]) &&
  `endif
                   !isValid(ld_depStQDeq_enqIss[info.tag]),
  