anchor.diff:     Vector #(tn_num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_wr_sjs <- replicateM (mkSizedFIFOF (8));
   
      // On an mi->sj write-transaction, this fifo records mi for slave sj
  -   Vector #(tn_num_slaves,  FIFOF #(Bit #(log_nm))) v_f_wr_mis  <- replicateM (mkSizedFIFOF (8));
  +   Vector #(tn_num_slaves,  FIFOF #(Bit #(log_nm_plus_1))) v_f_wr_mis  <- replicateM (mkSizedFIFOF (8));
   
      // On an mi->sj write-transaction, this fifo records a task (sj, awlen) for W channel
      Vector #(tn_num_masters,
  
positive.code:        xactors_to_slaves <- replicateM (mkAXI4_Master_Xactor);
  
     // ----------------------------------------------------------------
     // Book-keeping to keep track of which master originated a transaction, in
     // order to route corresponding responses back to that master, etc.
     // Legal slaves  are 0..(num_slaves-1)
     // The "illegal" value of 'num_slaves' is used for decode errors (no such slave)
     // Size of SizedFIFOs is estimated: should cover round-trip latency to slave and back.
  
     // ----------------
  
negative.code: 	 // If sj is a legal slave, send it the data beat, else drop it.
  	 if (sj < fromInteger (num_slaves))
  	    xactors_to_slaves [sj].i_wr_data.enq (d);
  
  	 if (cfg_verbosity > 0) begin
  	    $display ("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
  		      cur_cycle, mi, sj, v_rg_wd_beat_count [mi], awlen);
  	    $display ("    ", fshow (d));
  	 end
  
  	 if (v_rg_wd_beat_count [mi] == awlen) begin
  	    // End of burst
  