anchor.diff:  	    method ActionValue#(Bit#(32)) writeData();
   	        busyReg <= False;
   	        writeDataFifo.deq;
  -		return byteSwap(writeDataFifo.first.data);
  +		if (byteSwapReg)
  +		    return byteSwap(writeDataFifo.first.data);
  +		else
  +		    return writeDataFifo.first.data;
   	    endmethod
   	    method Bit#(12) writeWid();
   		return extend(writeDataFifo.first.tag);
  
positive.code:    interface Reg tlpTracing = tlpTracingReg;
     interface Reg axiEnabled = axiEnabledReg;
     interface Reg pipeliningEnabled = pipeliningEnabledReg;
     interface Reg axiTestEnabled = axiTestEnabledReg;
     interface Reg addrLowerWord = addrLowerWordReg;
     interface Reg addrUpperWord = addrUpperWordReg;
  
negative.code:    interface Reg#(Bool) tlpTracing;
     interface Reg#(Bool) axiEnabled;
     interface Reg#(Bool) pipeliningEnabled;
     interface Reg#(Bool) byteSwap;
     interface Reg#(Bool) axiTestEnabled;
     interface Reg#(Bit#(32)) addrLowerWord;
     interface Reg#(Bit#(32)) addrUpperWord;
  