anchor.diff:     FIFOF#(Bit#(32))   writeReqFifo <- mkFIFOF();
      FIFOF#(Bit#(32))   readReqFifo <- mkFIFOF();
   
  +   Probe#(Bit#(Ddr3AddrWidth)) aw_req_probe <- mkProbe();
  +   Reg#(Bit#(Ddr3AddrWidth)) dramWriteLimitProbe <- mkReg(0);
  +   Reg#(Bit#(Ddr3AddrWidth)) dramReadLimitProbe <- mkReg(0);
  +
  +   Probe#(Bit#(Ddr3AddrWidth)) awAddrProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Bit#(8)) awLenProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Bit#(3)) awSizeProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Vector#(BusRatio,Bit#(DataBusWidth))) wdataProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Axi4WriteResponse#(6)) bProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Bit#(Ddr3AddrWidth)) arAddrProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Bit#(8)) arLenProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Bit#(3)) arSizeProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   Probe#(Vector#(BusRatio,Bit#(DataBusWidth))) rdataProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);
  +   let sglWriteProbe <- mkProbe();
  +   let sglReadProbe <- mkProbe();
  +
      Gearbox#(1,BusRatio,Bit#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
      SyncFIFOIfc#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkSyncFIFO(8, clock, reset, ddr3Controller.uiClock);
      SyncFIFOIfc#(Axi4WriteResponse#(6)) bfifo <- mkSyncFIFO(8, ddr3Controller.uiClock, ddr3Controller.uiReset, clock);
  -   mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);
  -   mkConnection(ddr3Controller.slave.resp_b, toPut(bfifo));
  +   //mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);
  +   //mkConnection(ddr3Controller.slave.resp_b, toPut(bfifo));
  +   rule rl_awfifo;
  +      let req <- toGet(awfifo).get();
  +      awAddrProbe <= req.address;
  +      awLenProbe <= req.len;
  +      awSizeProbe <= req.size;
  +      ddr3Controller.slave.req_aw.put(req);
  +   endrule
  +   rule rl_bfifo;
  +      let b <- ddr3Controller.slave.resp_b.get();
  +      bProbe <= b;
  +      bfifo.enq(b);
  +   endrule
   
      Reg#(Bit#(Ddr3AddrWidth)) dramWriteOffset <- mkReg(0);
      Reg#(Bit#(Ddr3AddrWidth)) dramWriteLimit <- mkReg(0);
      rule rl_req_aw if (dramWriteOffset < dramWriteLimit);
  -      awfifo.enq(Axi4WriteRequest {
  +      Axi4WriteRequest#(Ddr3AddrWidth,6) req = Axi4WriteRequest {
   	 address: truncate(dramWriteOffset),
  -	 len: 1,
  +	 len: 0, // indicates 1 beat of data
   	 size: axiBusSize(valueOf(Ddr3DataWidth)),
   	 id: 0,
   	 burst: 2'b01,
  
positive.code:    endrule
     rule rl_wdata;
        let mds <- toGet(dramWriteGearbox).get();
        ddr3Controller.slave.resp_write.put(Axi4WriteData {
  	 data: pack(mds),
  	 byteEnable: maxBound,
  
negative.code: 
     interface Ddr3TestRequest request;
        method Action startWriteDram(Bit#(32) sglId);
  	 sglWriteProbe <= sglId;
  	 writeReqFifo.enq(sglId);
        endmethod
        method Action startReadDram(Bit#(32) sglId);
  	 sglReadProbe <= sglId;
  	 readReqFifo.enq(sglId);
        endmethod
     endinterface
  