anchor.diff:  	    command[13] = req.dsm;
   	    requestId <= req.requestId;
   	    ioCommand <= command;
  +
  +	    requestSlotAvailable <= False;
   	 endaction
  +
  +	 while (!requestSlotAvailable) seq // wait for open request slot
  +	    portB1.request.put(BRAMRequest {address: (extend(requestId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),
  +					    write: False, responseOnWrite: False, datain: 0});
  +	    action
  +	       let response <- portB1.response.get();
  +	       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == ~phase) begin
  +		  requestSlotAvailable <= True;
  +	       end
  +	    endaction
  +	 endseq // wait for open request slot
  +
   	 // write a IO read request to BRAM
            for (i <= 0; i < fromInteger(requestSize/bytesPerEntry); i <= i + 1) seq
   	    portB1.request.put(BRAMRequest {address: 'h1000/fromInteger(bytesPerEntry) + (extend(requestId[2:0]) * fromInteger(requestSize/bytesPerEntry)) + i,
  
positive.code: 
  	 // tell the NVME the new response queue head pointer
  	 action
  	    let nextRequestId = (requestId + 1);
  	    if (nextRequestId[2:0] == 0) begin
  	       phase <= ~phase;
  	    end
  	    requestId <= nextRequestId;
  	    awaddrFifo.enq(PhysMemRequest { addr: 'h1000 + (2*2+1)*(4<<0), burstLen: 4, tag: 1 });
  	    wdataFifo.enq(MemData{data: zeroExtend((nextRequestId)[2:0]), tag: 1, last: True});
  	 endaction
  
negative.code: 	    requestStartTimestamp <= cycles;
  	    trace.traceData(unpack(0), False, truncate(requestId), cycles);
  	 endaction
        endseq // while True
        endseq);
  
     let responseFsm <- mkAutoFSM(seq
  	 // wait for response queue to be updated
        while (True) seq
  	 requestInProgress <= True;
  	 while (requestInProgress) seq
  	    portB2.request.put(BRAMRequest {address: (extend(responseId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),
  					    write: False, responseOnWrite: False, datain: 0});
  	    bramQueryAddress <= (responseId * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry);
  	    action
  	       let response <- portB2.response.get();
  	       bramQueryResponse <= response;
  	       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == phase) begin
  		  requestCompleted <= response;
  		  // if status field written by NVME
  		  ind.transferCompleted(responseId, truncate(response), cycles - requestStartTimestamp);
  		  requestInProgress <= False;
  	       end
  	    endaction
  