anchor.diff:  	 axiSlave.awsize(axireq.size);
   	 axiSlave.awlen(axireq.len);
   	 axiSlave.awburst(2'b01);     // burst: INCR
  -	 axiSlave.awcache(4'b0011);   //FIXME
  +	 axiSlave.awcache(4'b0011);   // FIXME: 0011? 1111?
   	 axiSlave.awlock(2'b0);       // normal access 
   	 axiSlave.awprot(3'b0);       // unprevileged, protedted, data access
   	 axiSlave.awqos(4'b0);        // unused - default 0
   	 axiSlave.extra.awuser(1'b0); // unused
  -	 wtagfifo.enq(req.tag);
  +	 awInFlight.enq(True);
         endrule
         rule rl_wvalid;
   	 axiSlave.wvalid(pack(wfifo.notEmpty));
  
positive.code:    endfunction
  endinstance
  
  //FIXME extra aruser awuser
  instance MkPhysMemSlave#(Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra),addrWidth,DataBusWidth)
        provisos (Add#(addrWidth,a__,49));
     module mkPhysMemSlave#(Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra) axiSlave)(PhysMemSlave#(addrWidth,DataBusWidth));
  
negative.code: 	 axiSlave.wdata(extend(wdata));
  	 axiSlave.wlast(pack(last));
  	 axiSlave.wstrb(16'hFFFF); // using full 128-bit
  	 // wid deprecated; the master must issue the data in the same order in which it issued the write address (aw_req)
        endrule
        rule rl_bready;
  	 axiSlave.bready(pack(awInFlight.notEmpty && bfifo.notFull));
        endrule
        rule rl_done if (axiSlave.bvalid() == 1);
  	 let tag <- toGet(awInFlight).get();
  	 bfifo.enq(axiSlave.bid());
        endrule
  
        interface PhysMemReadServer read_server;
  