anchor.diff:        debugReg <= False;
      endrule
   
  -   rule loadChannel if (valueOf(numReadClients) > 0);
  +   rule loadChannel if (valueOf(numReadClients) > 0 && !isConfiguring);
         DMAAddressRequest req = unpack(0);
         if (valueOf(numReadClients) > 0)
   	 req <- readClients[selectReg].readReq.get();
  -      $display("dmaread.loadClient activeChan=%d handle=%h addr=%h burst=%h", selectReg, req.handle, req.address, req.burstLen);
  -
  -      reqFifo.enq(req);
  +      $display("dmaread.loadChannel activeChan=%d handle=%h addr=%h burst=%h", selectReg, req.handle, req.address, req.burstLen);
  +
  +      lreqFifo.enq(req);
         chanFifo.enq(selectReg);
         sgl.addrReq(truncate(req.handle),req.address);
      endrule
      
  -   rule checkSglResp;
  +   rule checkSglResp if (!debugReg);
         let physAddr <- sgl.addrResp();
  +      let req = lreqFifo.first();
  +      lreqFifo.deq();
         if (physAddr == 0) begin
   	 // squash request
  -	 reqFifo.deq();
  -	 dmaIndication.badAddr(reqFifo.first.handle, reqFifo.first.address);
  +	 dmaIndication.badAddr(req.handle, req.address);
         end
         else begin
  +	 reqFifo.enq(req);
   	 paFifo.enq(physAddr);
         end
      endrule
   
  -   method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr);
  -      sgl.page(truncate(tabsel), off, addr);
  -   endmethod
  -   
  -   method Action readSglist(Bit#(32) pref, Bit#(40) addr) if (!debugReg);
  -      debugReg <= True;
  -      sgl.addrReq(truncate(pref), addr);
  -   endmethod
  +   interface ConfigureSglist configure;
  +       method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr) if (isConfiguring);
  +	  sgl.page(truncate(tabsel), off, addr);
  +       endmethod
  +
  +       method Action readSglist(Bit#(32) pref, Bit#(40) addr) if (!debugReg);
  +	  debugReg <= True;
  +	  sgl.addrReq(truncate(pref), addr);
  +       endmethod
  +      method Action configuring(Bool c);
  +	 isConfiguring <= c;
  +      endmethod
  +   endinterface
   
      interface DMARead read;
         method ActionValue#(DmaDbgRec) dbg();
  
positive.code: 	 lenReg  <= (len >> page_shift) + idx;
  	 addrReg <= addr >> page_shift;
  	 idxReg <= idx;
  	 if (addr == 0 && len == 0) // sw marks end-of-list with zeros
  	    dmaIndication.sglistResp(pref, idx);
        endmethod
        method Action readSglist(ChannelType rc, Bit#(32) handle, Bit#(64) addr);
  	 if (rc == Read)
  	    reader.readSglist(handle, truncate(addr));
  	 else
  	    writer.readSglist(handle, truncate(addr));
        endmethod
     endinterface
     interface Axi3Client m_axi;
  
negative.code:    interface Axi3Client#(40,dsz,dbytes,12) m_axi;
  endinterface
  
  interface ConfigureSglist;
     method Action configuring(Bool c);
     method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr);
     method Action readSglist(Bit#(32) pref, Bit#(40) addr);
  endinterface
  
  interface AxiDMAWriteInternal#(numeric type dsz, numeric type dbytes);
     interface DMAWrite write;
     interface Axi3WriteClient#(40,dsz,dbytes,12) m_axi_write;
     interface ConfigureSglist configure;
  endinterface
  
  interface AxiDMAReadInternal#(numeric type dsz, numeric type dbytes);
     interface DMARead read;
     interface Axi3ReadClient#(40,dsz,12) m_axi_read;
     interface ConfigureSglist configure;
  endinterface
  
  typedef enum {Idle, Translate, Address, Data, Done} InternalState deriving(Eq,Bits);
  