anchor.diff:      // Priv 1.9 CSRs
   
       // Machine Timers and Counters
  -    Reg#(Data) mcycle_csr   = readOnlyReg(cycle_counter);
  -    Reg#(Data) mtime_csr    = readOnlyReg(mtime);
  -    Reg#(Data) minstret_csr = readOnlyReg(instret_counter);
  +    // TODO: support 32-bit ISA
  +    Reg#(Data) mcycle_csr   = readOnlyReg(truncate(cycle_counter));
  +    Reg#(Data) mtime_csr    = readOnlyReg(truncate(mtime));
  +    Reg#(Data) minstret_csr = readOnlyReg(truncate(instret_counter));
   
       // Machine Counter-Delta Registers
  +    // TODO: support 32-bit ISA
       Reg#(Data) mucycle_delta_csr   <- mkReg(0);
       Reg#(Data) mutime_delta_csr    <- mkReg(0);
       Reg#(Data) muinstret_delta_csr <- mkReg(0);
  
positive.code: 
      Reg#(Data) sptbr_csr    = concatReg2(asid_field, sptbr_ppn_field);
  
      Reg#(Data) scycle_csr   = readOnlyReg(mcycle_csr + mscycle_delta_csr);
      Reg#(Data) stime_csr    = readOnlyReg(mtime_csr + mstime_delta_csr);
      Reg#(Data) sinstret_csr = readOnlyReg(minstret_csr + msinstret_delta_csr);
  
negative.code:     Reg#(Data) fcsr_csr   = addWriteSideEffect(zeroExtendReg(concatReg2(frm_field, fflags_field)), fs_field._write(2'b11));
  
      // User Timers and Counters
      // TODO: support 32-bit ISA
      Reg#(Data) cycle_csr   = readOnlyReg(mcycle_csr + mucycle_delta_csr);
      Reg#(Data) time_csr    = readOnlyReg(mtime_csr + mutime_delta_csr);
      Reg#(Data) instret_csr = readOnlyReg(minstret_csr + muinstret_delta_csr);
  