anchor.diff:        alu_outputs = fv_LOAD (inputs);
   
      else if (   (inputs.decoded_instr.opcode == op_STORE_FP))
  -      alu_outputs = fv_ST (inputs);
  +      alu_outputs = fv_STORE (inputs);
   
      else if (   (inputs.decoded_instr.opcode == op_FP)
               || (inputs.decoded_instr.opcode == op_FMADD)
  
positive.code:    alu_outputs.rd        = inputs.decoded_instr.rd;
     alu_outputs.addr      = eaddr;
  `ifdef ISA_F
     // note that the destination register for this load is in the FPR
     alu_outputs.rd_in_fpr = (opcode == op_LOAD_FP);
  `endif
  
  
negative.code: // ----------------------------------------------------------------
  // STORE
  
  function ALU_Outputs fv_STORE (ALU_Inputs inputs);
     // Signed version of rs1_val
     IntXL  s_rs1_val = unpack (inputs.rs1_val);
     IntXL  imm_s     = extend (unpack (inputs.decoded_instr.imm12_S));
  