anchor.diff:  
      Reg#(Bool) tlpTracingReg <- mkReg(False);
      Reg#(Bool) axiEnabledReg <- mkReg(False);
  -   Reg#(Bool) pipeliningEnabledReg <- mkReg(False);
      Reg#(Bool) byteSwapReg <- mkReg(False);
      Reg#(Bool) use4dwReg <- mkReg(True);
      Reg#(Bit#(4)) numPortalsReg <- mkReg(1);
  
positive.code: 
     interface Reg#(Bool) tlpTracing;
     interface Reg#(Bool) axiEnabled;
     interface Reg#(Bool) pipeliningEnabled;
     interface Reg#(Bool) byteSwap;
     interface Reg#(Bool) use4dw;
     interface Reg#(Bit#(4)) numPortals;
  
negative.code:    endrule
     rule connectEnables;
        dispatcher.axiEnabled <= csr.axiEnabled;
        portalEngine.byteSwap <= csr.byteSwap;
     endrule
  
  