anchor.diff:     endinterface
   endmodule
   
  -module mkNullAxi3Master(Axi3Master#(busWidth,busWidthBytes)) provisos(Div#(busWidth,8,busWidthBytes),Add#(1,a,busWidth));
  +module mkNullAxi3Master(Axi3Master#(busWidth,busWidthBytes,idWidth)) provisos(Div#(busWidth,8,busWidthBytes),Add#(1,a,busWidth));
      interface Axi3MasterWrite write;
          method ActionValue#(Bit#(32)) writeAddr() if (False);
              return 0;
  
positive.code: import FIFOF::*;
  import FIFOLevel::*;
  import SpecialFIFOs::*;
  
  interface AxiMasterRead#(type busWidth);
     method ActionValue#(Bit#(32)) readAddr();
  
negative.code:        method Bit#(3) writeBurstCache(); // drive with 4'b0011
             return 3'b011;
         endmethod
         method Bit#(idWidth) writeId();
             return 0;
         endmethod
  
  