anchor.diff:     
      let beat_shift = fromInteger(valueOf(beatShift));
   
  -   rule read_rule if (readDelayFifo.notEmpty() && (cycles-tpl_1(readDelayFifo.first) > readLatency));
  +   rule read_rule if (readDelayFifo.notEmpty() && (cycles-tpl_1(readDelayFifo.first) >= readLatency));
   	 match { .reqTime, .req } = readDelayFifo.first;
   	 Bit#(BurstLenSize) readLen = readLenReg;
   	 Bit#(32) readOffset = readOffsetReg;
  
positive.code: 	 endmethod
        endinterface
        interface Get writeDone;
  	 method ActionValue#(Bit#(MemTagSize)) get() if ((cycles-tpl_1(bFifo.first)) > writeLatency);
  	 bFifo.deq();
  	 return tpl_2(bFifo.first());
  	 endmethod
  
negative.code: 	 endmethod
        endinterface
        interface Put writeData;
  	 method Action put(MemData#(serverBusWidth) resp) if (writeDelayFifo.notEmpty && (cycles-tpl_1(writeDelayFifo.first)) >= writeLatency);
  	    match { .reqTime, .req } = writeDelayFifo.first;
  	    Bit#(BurstLenSize) writeLen = writeLenReg;
  	    Bit#(32) writeOffset = writeOffsetReg;
  