anchor.diff:         Bit#(3) samplein = 0;
          Bit#(50) rawdataw = 0;
          for (Bit#(8) i = 0; i < 5; i = i+1) begin
  -	  unalignedw = unalignedw | serdes_v[i].aligned();
  -	  alignbusyw = alignbusyw | serdes_v[i].align_busy();
  -	  emptyw = emptyw | serdes_v[i].empty();
  -          samplein = samplein | serdes_v[i].samplein();
  -	  rawdataw[(i+1)*10-1: i*10] = serdes_v[i].dataout();
  +	  unalignedw = unalignedw | pin_v[i].aligned();
  +	  alignbusyw = alignbusyw | pin_v[i].align_busy();
  +	  emptyw = emptyw | pin_v[i].empty();
  +          samplein = samplein | pin_v[i].samplein();
  +	  rawdataw[(i+1)*10-1: i*10] = pin_v[i].dataout();
          end
          serdes_align_busy_temp <= alignbusyw;
          serdes_aligned_temp <= unalignedw;
  
positive.code:     Reg#(Bit#(1)) serdes_aligned_reg <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);
      Wire#(Bit#(1)) new_raw_empty_wire <- mkDWire(0);
      TrainRotate trainrot <- replicateM(mkReg(0));
      Vector#(5, IserdesDatadeser) serdes_v <- replicateM(mkIserdesDatadeser(serdes_clock, serdes_reset, serdest_clk.gen_clk,
  	  serdes_align_start_reg, serdes_auto_align_reg, serdes_training_reg,
  	  serdes_manual_tap_reg, trainrot));
  
  
negative.code:     Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
  
      SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBit(serdes_clock, serdes_reset, serdes_clock);
  
      Reg#(Bit#(10)) ctrl_data <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      Reg#(Bit#(10)) ctrl_data_temp <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  