anchor.diff:                  });
               end
           end
  -    endrule
  -
  -    rule doTrainBP;
  -        let x <- toGet(trainBPQ).get;
  -        inIfc.fetch_train_predictors(
  -            x.pc, x.nextPc, x.iType, x.taken, x.dpTrain, x.mispred
  -        );
       endrule
   
       interface recvBypass = map(getRecvBypassIfc, bypassWire);
  
positive.code:     // index to send bypass, ordering doesn't matter
      Integer exeSendBypassPort = 0;
      Integer finishSendBypassPort = 1;
  
      // train BP in a new cycle
      FIFO#(AluExeTrainBP) trainBPQ <- mkFIFO;
  
  `ifdef PERF_COUNT
      // performance counters
  
negative.code:             inIfc.redirect(x.controlFlow.nextPc, validValue(x.spec_tag), x.tag);
              // must be a branch, train branch predictor
              doAssert(x.iType == Jr || x.iType == Br, "only jr and br can mispredict");
              inIfc.fetch_train_predictors(FetchTrainBP {
                  pc: x.controlFlow.pc,
                  nextPc: x.controlFlow.nextPc,
                  iType: x.iType,
  