anchor.diff:  
   module mkAxi3MasterGather#(Pps7Maxigp axiWires)(AxiMasterCommon);
      AxiMasterWires vtopmw <- mkAxiMasterWires;
  -   rule axi_gp_handshake1;
  +   rule handshake1;
           axiWires.arready(vtopmw.arready);
      endrule
  -   rule axi_gp_handshake2;
  +   rule handshake2;
           axiWires.awready(vtopmw.awready);
      endrule
  -   rule axi_gp_handshake3;
  +   rule handshake3;
           axiWires.rid(vtopmw.rid);
           axiWires.rresp(vtopmw.rresp);
           axiWires.rdata(vtopmw.rdata);
           axiWires.rlast(vtopmw.rlast);
           axiWires.rvalid(vtopmw.rvalid);
      endrule
  -   rule axi_gp_handshake4;
  +   rule handshake4;
           axiWires.wready(vtopmw.wready);
      endrule
  -   rule axi_gp_handshake5;
  +   rule handshake5;
           axiWires.bvalid(vtopmw.bvalid);
           axiWires.bid(vtopmw.bid);
           axiWires.bresp(vtopmw.bresp);
  
positive.code: 
  module mkAxi3SlaveGather#(Pps7Saxigp axiWires)(AxiSlaveCommon#(32,6));
      AxiSlaveWires#(32,6) vtopsw <- mkAxiSlaveWires;
      rule axi_gp_handshake11;
            axiWires.araddr(vtopsw.araddr);
            axiWires.arburst(vtopsw.arburst);
            axiWires.arcache(vtopsw.arcache);
  
negative.code:           axiWires.awsize(vtopsw.awsize);
            axiWires.awvalid(vtopsw.awvalid);
      endrule
      rule handshake3;
         axiWires.rready(vtopsw.rready);
      endrule
      rule handshake4;
            axiWires.wid(vtopsw.wid);
            axiWires.wstrb(vtopsw.wstrb);
            axiWires.wdata(vtopsw.wdata);
            axiWires.wlast(vtopsw.wlast);
            axiWires.wvalid(vtopsw.wvalid);
      endrule
      rule handshake5;
           axiWires.bready(vtopsw.bready);
      endrule
      rule issuecap;
  