anchor.diff:      for (Integer i = 0; i < 2; i = i + 1)
           vtops_axi_gp[i] = interface AxiSlaveCommon#(32, id_width);
               interface Put req_ar;
  -                method Action put(AxiREQ#(id_width) v) if (vs_axi_gp[i].arready() != 0);
  -                    vs_axi_gp[i].araddr(v.addr);
  +                method Action put(Axi3ReadRequest#(32,id_width) v) if (vs_axi_gp[i].arready() != 0);
  +                    vs_axi_gp[i].araddr(v.address);
                       vs_axi_gp[i].arburst(v.burst);
                       vs_axi_gp[i].arcache(v.cache);
                       vs_axi_gp[i].arid(v.id);
  
positive.code:                 endmethod
              endinterface
              interface Put req_aw;
                  method Action put(AxiREQ#(id_width) v) if (vs_axi_gp[i].awready() != 0);
                      vs_axi_gp[i].awaddr(v.addr);
                      vs_axi_gp[i].awburst(v.burst);
                      vs_axi_gp[i].awcache(v.cache);
                      vs_axi_gp[i].awid(v.id);
  
negative.code:     endrule
  
      rule s_areqw_rule;
          let address <- m_axi.write.writeAddr();
          hp.axi.req_aw.put(StdAxiREQW{ address: address[31:0],
              len: m_axi.write.writeBurstLen(),
              size: m_axi.write.writeBurstWidth(),
              burst: m_axi.write.writeBurstType(),
  