anchor.diff:  
   //FIXME burst transfers
   instance MkPhysMemSlave#(Axi4SlaveBits#(axiAddrWidth,dataWidth,tagWidth,Empty),addrWidth,dataWidth)
  -      provisos (Add#(axiAddrWidth,a__,addrWidth));
  +      provisos (Add#(axiAddrWidth,a__,addrWidth),
  +		Add#(b__, tagWidth, 6));
      module mkPhysMemSlave#(Axi4SlaveBits#(axiAddrWidth,dataWidth,tagWidth,Empty) axiSlave)(PhysMemSlave#(addrWidth,dataWidth));
         FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) arfifo <- mkAxiFifoF();
         FIFOF#(MemData#(dataWidth)) rfifo <- mkAxiFifoF();
  
positive.code: 
        rule rl_awvalid_awaddr;
  	 axiSlave.awvalid(pack(awfifo.notEmpty && wtagfifo.notFull));
  	 let addr = 0;
  	 if (awfifo.notEmpty)
  	    addr = truncate(awfifo.first.addr);
  	 axiSlave.awaddr(addr);
        endrule   
        rule rl_awfifo if (axiSlave.awready() == 1);
  	 let req <- toGet(awfifo).get();
  
negative.code: import GetPut::*;
  import MemTypes::*;
  import EHRM::*;
  import Axi4MasterSlave::*;
  
  interface AxiMasterBits#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);
      method Bit#(addrWidth)     araddr();
  