anchor.diff:        cycle <= cycle + 1;
      endrule
   
  -   FIFOF#(Tuple2#(Bit#(camSz), Bit#(9))) writeReqFifo <- mkBypassFIFOF;
  -   FIFOF#(Bool) wEnb_setram_fifo <- mkBypassFIFOF;
  -   FIFOF#(Bit#(9)) oldPatt_fifo <- mkBypassFIFOF();
  -   FIFOF#(Bool) oldPattV_fifo<- mkBypassFIFOF();
  -   FIFOF#(Bool) oldPattMultiOcc_fifo <- mkBypassFIFOF();
  -   FIFOF#(Bool) newPattMultiOcc_fifo <- mkBypassFIFOF();
  -   FIFOF#(Bit#(5)) newPattOccFLoc_fifo <- mkBypassFIFOF();
  -   FIFOF#(Bit#(32)) oldPattIndc_fifo <- mkBypassFIFOF();
  -   FIFOF#(Bit#(32)) newPattIndc_fifo <- mkBypassFIFOF();
  -   FIFOF#(Vector#(8, RPatt)) rpatt_fifo <- mkBypassFIFOF();
  +   FIFOF#(Tuple2#(Bit#(camSz), Bit#(9))) writeReqFifo0 <- mkFIFOF;
  +   FIFOF#(Tuple2#(Bit#(camSz), Bit#(9))) writeReqFifo1<- mkFIFOF;
  +   FIFOF#(Tuple2#(Bit#(camSz), Bit#(9))) writeReqFifo2<- mkFIFOF;
  +   FIFOF#(Tuple2#(Bit#(camSz), Bit#(9))) writeReqFifo3<- mkFIFOF;
  +   FIFOF#(Tuple2#(Bit#(camSz), Bit#(9))) writeReqFifo4<- mkFIFOF;
  +
  +   FIFOF#(Bool) wEnb_setram_fifo <- mkFIFOF;
  +   FIFOF#(Bit#(9)) oldPatt_fifo <- mkFIFOF();
  +   FIFOF#(Bit#(9)) oldPatt_fifo2 <- mkFIFOF();
  +   FIFOF#(Bool) oldPattV_fifo<- mkFIFOF();
  +   FIFOF#(Bool) oldPattMultiOcc_fifo <- mkFIFOF();
  +   FIFOF#(Bool) newPattMultiOcc_fifo <- mkFIFOF();
  +   FIFOF#(Bit#(5)) newPattOccFLoc_fifo <- mkFIFOF();
  +   FIFOF#(Bit#(32)) oldPattIndc_fifo <- mkFIFOF();
  +   FIFOF#(Bit#(32)) newPattIndc_fifo <- mkFIFOF();
  +
  +   Vector#(8, FIFOF#(RPatt)) rpatt_fifo0 <- replicateM(mkFIFOF);
  +   Vector#(8, FIFOF#(RPatt)) rpatt_fifo1 <- replicateM(mkFIFOF);
   
   `define SETRAM AsymmetricBRAM#(Bit#(readDepthSz), Bit#(readSz), Bit#(writeDepthSz), Bit#(writeSz))
   
      Vector#(8, `SETRAM) setRam <- replicateM(mkAsymmetricBRAM(True, False, "Setram"));
   
  -   Vector#(3, PipeOut#(Tuple2#(Bit#(camSz), Bit#(9)))) writeRequestPipes <- mkForkVector(toPipeOut(writeReqFifo));
  -
      PEnc32 pe_multiOcc <- mkPriorityEncoder32();
   
  +   rule setram_read_request;
  +      let v <- toGet(writeReqFifo0).get;
  +      let wAddr = tpl_1(v);
  +      Vector#(wAddrHWidth, Bit#(1)) wAddrH = takeAt(5, unpack(wAddr));
  +      if (verbose) $display("setram %d: setram read Addr=%x", cycle, pack(wAddrH));
  +      for (Integer i=0; i<8; i=i+1) begin
  +         setRam[i].readServer.request.put(pack(wAddrH));
  +      end
  +      writeReqFifo1.enq(v);
  +      writeReqFifo3.enq(v);
  +      writeReqFifo4.enq(v);
  +   endrule
  +
  +   rule setram_read_response;
  +      let v <- toGet(writeReqFifo1).get;
  +      let wAddr = tpl_1(v);
  +      let wPatt = tpl_2(v);
  +      Vector#(5, Bit#(1)) wAddrL = take(unpack(wAddr));
  +      OInt#(32) wAddrLOH = toOInt(pack(wAddrL));
  +      Vector#(8, RPatt) data = newVector;
  +      for (Integer i=0; i<8; i=i+1) begin
  +         let setram_data <- setRam[i].readServer.response.get;
  +         Vector#(4, Maybe#(Bit#(9))) m = unpack(setram_data);
  +         data[i] = unpack(setram_data);
  +      end
  +      Bit#(3) wAddrL_ram = pack(wAddrL)[4:2];
  +      Bit#(2) wAddrL_word = pack(wAddrL)[1:0];
  +      Bool oldPattV = isValid(data[wAddrL_ram].rpatt[wAddrL_word]);
  +      Bit#(9) oldPatt = fromMaybe(?, data[wAddrL_ram].rpatt[wAddrL_word]);
  +      oldPatt_fifo.enq(oldPatt);
  +      oldPatt_fifo2.enq(oldPatt);
  +      oldPattV_fifo.enq(oldPattV);
  +      writeReqFifo2.enq(v);
  +      for (Integer i=0; i<8; i=i+1) begin
  +         rpatt_fifo0[i].enq(data[i]);
  +         rpatt_fifo1[i].enq(data[i]);
  +      end
  +      if(verbose) $display("setram %d: lastWritten oldPatt=%x oldPattV=%d", cycle, oldPatt, oldPattV);
  +   endrule
  +
      rule setram_input;
  -      let v <- toGet(writeRequestPipes[0]).get;
  +      let v <- toGet(writeReqFifo2).get;
         let wEnb <- toGet(wEnb_setram_fifo).get;
         let wAddr = tpl_1(v);
         let wPatt = tpl_2(v);
  
positive.code:       end
     endrule
  
     rule setram_read_request;
        let v <- toGet(writeRequestPipes[1]).get;
        let wAddr = tpl_1(v);
        Vector#(wAddrHWidth, Bit#(1)) wAddrH = takeAt(5, unpack(wAddr));
        if (verbose) $display("setram %d: setram read Addr=%x", cycle, pack(wAddrH));
        for (Integer i=0; i<8; i=i+1) begin
           setRam[i].readServer.request.put(pack(wAddrH));
        end
     endrule
  
     rule setram_read_response;
        let v <- toGet(writeRequestPipes[2]).get;
        let wAddr = tpl_1(v);
        let wPatt = tpl_2(v);
        Vector#(5, Bit#(1)) wAddrL = take(unpack(wAddr));
        OInt#(32) wAddrLOH = toOInt(pack(wAddrL));
        Vector#(8, RPatt) data = newVector;
        for (Integer i=0; i<8; i=i+1) begin
           let setram_data <- setRam[i].readServer.response.get;
           Vector#(4, Maybe#(Bit#(9))) m = unpack(setram_data);
           data[i] = unpack(setram_data);
        end
        Bit#(3) wAddrL_ram = pack(wAddrL)[4:2];
        Bit#(2) wAddrL_word = pack(wAddrL)[1:0];
        Bool oldPattV = isValid(data[wAddrL_ram].rpatt[wAddrL_word]);
        Bit#(9) oldPatt = fromMaybe(?, data[wAddrL_ram].rpatt[wAddrL_word]);
        if(verbose) $display("setram %d: lastWritten oldPatt=%x oldPattV=%d", cycle, oldPatt, oldPattV);
  
        Vector#(32, Bool) oldPattIndc;
        for (Integer i=0; i<8; i=i+1) begin
           for (Integer j=0; j<4; j=j+1) begin
              Bit#(9) rPatt = fromMaybe(?, data[i].rpatt[j]);
              Bool rPattV = isValid(data[i].rpatt[j]);
              Bit#(32) indx = pack(wAddrLOH);
              oldPattIndc[i*4+j] = (rPatt == oldPatt) && !unpack(indx[i*4+j]) && rPattV;
              //$display("%d: rPatt=%x, wAddrLOH=%x, rPattV=%d oldPattIndc=%d", cycle, rPatt, wAddrLOH, rPattV, oldPattIndc[i*4+j]);
           end
        end
        oldPattIndc_fifo.enq(pack(oldPattIndc));
        if (verbose) $display("setram %d: oldPattIndc=%x", cycle, pack(oldPattIndc));
  
        Vector#(32, Bool) newPattIndc_prv;
        for (Integer i=0; i<8; i=i+1) begin
           for (Integer j=0; j<4; j=j+1) begin
              Bit#(9) rPatt = fromMaybe(?, data[i].rpatt[j]);
              Bool rPattV = isValid(data[i].rpatt[j]);
              newPattIndc_prv[i*4+j] = (rPatt == wPatt) && rPattV;
              //$display("%d: rPatt=%x, rPattV=%d newPattIndc_prv=%d", cycle, fromMaybe(?, data[i].rpatt[j]), isValid(data[i].rpatt[j]), newPattIndc_prv[i*4+j]);
           end
        end
  
        pe_multiOcc.oht.put(pack(newPattIndc_prv));
  
        Bit#(32) newPattIndc = pack(newPattIndc_prv) | pack(wAddrLOH);
        newPattIndc_fifo.enq(newPattIndc);
        if (verbose) $display("setram %d: newPattIndc=%x", cycle, newPattIndc);
  
        // detect if old pattern has multi-occurence in segment
        Bool oldPattMultiOcc = (pack(oldPattIndc) != 0);
        oldPattMultiOcc_fifo.enq(oldPattMultiOcc);
        if (verbose) $display("setram %d: oldPattMultiOcc=%x", cycle, oldPattMultiOcc);
  
        oldPatt_fifo.enq(oldPatt);
        oldPattV_fifo.enq(oldPattV);
     endrule
  
     rule setram_encoder;
  
negative.code:       if (verbose) $display("setram %d: newPattMultiOcc=%x, newPattOccFLoc=%x", cycle, vld, bin);
     endrule
  
     interface Put writeServer = toPut(writeReqFifo0);
     interface PipeIn wEnb_setram = toPipeIn(wEnb_setram_fifo);
     interface PipeOut oldPatt = toPipeOut(oldPatt_fifo);
     interface PipeOut oldPattV = toPipeOut(oldPattV_fifo);
  