anchor.diff:     Reg#(Bit#(32)) wordsDeqCount <- mkReg(0);
      Reg#(Bit#(32)) lastDataBeatCount <- mkReg(0);
      FIFOF#(Bit#(busWidth)) rfifo <- mkSizedBRAMFIFOF(32);
  -   Reg#(Bit#(8)) burstCountReg <- mkReg(0);
  +   Reg#(Bit#(4)) burstCountReg <- mkReg(0);
      Reg#(Bool) operationInProgress <- mkReg(False);
      Reg#(Bool) addressPresented <- mkReg(False);
      FIFOF#(Bit#(2)) axiRrespFifo <- mkSizedBRAMFIFOF(32);
   
      rule updateBurstCount if (!rfifo.notEmpty && !operationInProgress && enabledReg && ptrReg < boundsReg);
  -       burstCountReg <= 8'd8;
  +       burstCountReg <= 4'd8;
          operationInProgress <= True;
          addressPresented <= False;
      endrule
  
positive.code: 
             let d = dfifo.first;
             dfifo.deq;
             return d;
         endmethod
         method Bit#(busWidthBytes) writeDataByteEnable();
             return maxBound;
         endmethod
         method Bit#(1) writeLastDataBeat(); // last data beat
             if (burstCountReg == 8'd1)
                 return 1'b1;
             else
                 return 1'b0;
         endmethod
  
         method Action writeResponse(Bit#(2) responseCode, Bit#(1) id) if (axiBrespFifo.notFull);
             if (responseCode != 2'b00)
                 axiBrespFifo.enq(responseCode);
         endmethod
     endinterface
  
  
negative.code: import RegFile::*;
  import BRAMFIFO::*;
  import FIFOF::*;
  import AxiClientServer::*;
  
  interface FifoToAxi#(type busWidth, type busWidthBytes, type idWidth);
     interface Reg#(Bit#(32)) base;
     interface Reg#(Bit#(32)) bounds;
     interface Reg#(Bit#(32)) threshold;
  