anchor.diff:     mapM_(mkXsimSink, append(top.requests, append(vec(lMMURequestInputNoc), vec(lMemServerRequestInputNoc))));
      mapM_(mkXsimSource, append(top.indications, append(vec(lMMUIndicationOutputNoc), vec(lMemServerIndicationOutputNoc))));
      mapM_(mkXsimMemoryConnection, lMemServer.masters);
  +
  +`ifdef PIN_TYPE
  +   interface pins = top.pins;
  +`endif
   endmodule
  
positive.code: import BuildVector::*;
  
  `include "ConnectalProjectConfig.bsv"
  
  interface XsimSource;
      method Action beat(Bit#(32) v);
  
negative.code:    mkConnection(master, slave);
  endmodule
  
  module mkXsimTop#(Clock derivedClock, Reset derivedReset)(XsimTop);
  
     Reg#(Bool) dumpstarted <- mkReg(False);
     rule startdump if (!dumpstarted);
  