anchor.diff:  	      // do nothing
   	   end
   	   else begin
  -	       TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 7'h04, tlp: tlp };
  -	       csr.fromPcieTraceBramPort.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(csr.fromPcieTraceBramWrAddr), datain: ttd });
  -	       csr.fromPcieTraceBramWrAddr <= csr.fromPcieTraceBramWrAddr + 1;
  +	      fromPcie.send();
  +	      fromPcieTlp <= tlp;
   	       skippingIncomingTlps <= False;
   	   end
          end
  
positive.code:        let tlp <- arbiter.tlp_out_to_bus.get();
         tlpToBusFifo.enq(tlp);
         if (csr.tlpTracing) begin
  	   TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 7'h08, tlp: tlp };
  	   csr.toPcieTraceBramPort.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(csr.toPcieTraceBramWrAddr), datain: ttd });
  	   csr.toPcieTraceBramWrAddr <= csr.toPcieTraceBramWrAddr + 1;
         end
     endrule: traceTlpToBus
  
     // route the interfaces to the sub-components
  
  
negative.code: 
     FIFO#(TLPData#(16)) tlpFromBusFifo <- mkFIFO();
     Reg#(Bool) skippingIncomingTlps <- mkReg(False);
     PulseWire fromPcie <- mkPulseWire;
     PulseWire   toPcie <- mkPulseWire;
     Wire#(TLPData#(16)) fromPcieTlp <- mkDWire(unpack(0));
     Wire#(TLPData#(16))   toPcieTlp <- mkDWire(unpack(0));
     rule traceTlpFromBus;
         let tlp = tlpFromBusFifo.first;
         tlpFromBusFifo.deq();
  