anchor.diff:        interface Put writeData;
   	 method Action put(MemData#(dataWidth) wdata);
   	    //$display("mkMemMethodMux.writeData aw=%d ws=%d data=%h", valueOf(aw), ws.first, wdata.data);
  +	    let b <- fifoWriteAddrGenerator.addrBeat.get();
               if (wsCtrl.first)
   	       ctrl.write_server.writeData.put(wdata);
               else begin
  -	       let b <- fifoWriteAddrGenerator.addrBeat.get();
   	       //$display("mkPipeOutMemSlave.writeData.put addr=%h data=%h", b.addr, d.data);
   	       if (b.last)
   	          fifoWriteDoneFifo.enq(b.tag);
  
positive.code:    rule readDataRule;
        let b <- fifoReadAddrGenerator.addrBeat.get();
        let v = 0;
        if (b.addr == 0)
  	 v <- toGet(indications[rs.first]).get();
        else if (b.addr == 4)
  	 v = extend(pack(indications[rs.first].notEmpty()));
        //$display("mkPipeOutMemSlave.readData.get addr=%h data=%h", b.addr, data);
        fifoReadDataFifo.enq(MemData { data: v, tag: b.tag, last: b.last });
     endrule
  
     rule write_done;
  
negative.code: 
     rule req_aw;
        let req <- toGet(req_aws).get;
        fifoWriteAddrGenerator.request.put(req);
        if (wsCtrl.first)
           ctrl.write_server.writeReq.put(req);
     endrule
  
     rule req_ar;
        let req <- toGet(req_ars).get;
        fifoReadAddrGenerator.request.put(req);
        if (rsCtrl.first)
           ctrl.read_server.readReq.put(req);
     endrule
  
     FIFO#(MemData#(dataWidth)) rvFifo <- mkFIFO;
     rule rvrule;
        let rv;
        let b <- fifoReadAddrGenerator.addrBeat.get();
        if (rsCtrl.first)
  	 rv <- ctrl.read_server.readData.get();
        else begin
  	 let v = 0;
  	 if (b.addr == 4)
  	    v = extend(pack(requests[rs.first].notFull()));
  