anchor.diff:        traceBram.portA.request.put(BRAMRequest {write:True, responseOnWrite:False, address:addrReg, datain:data});
         addrReg <= addrReg + 1;
      endrule
  -   Reg#(Bit#(16)) seqCounter <- mkReg(0, clocked_by mainclock.c, reset_by mainclock.r);
  +   Reg#(Bit#(16)) seqCounter <- mkReg(0, clocked_by mainclock, reset_by mainreset);
      rule seqinc;
          seqCounter <= seqCounter + 1;
      endrule
  
positive.code:        endmethod
     endinterface
     interface pins = top.pins;
     interface unused_clock = mainclock.c;
     interface unused_reset = mainclock.r;
  endmodule
  
  module mkZynqTop(ZynqTop#(Empty));
  
negative.code:        ps7.interrupt(interrupt_bit);
     endrule
  
     interface zynq = ps7.pins;
     interface leds = top.leds;
     interface XADC xadc;
  