anchor.diff:        AvalonStRx#(16) beat;
         beat.sop = pcie_ep.rx_st.sop;
         beat.eop = pcie_ep.rx_st.eop;
  -      beat.be  = pcie_ep.rx_specific.be;
  +      beat.be  = pcie_ep.rx_st.be;
         // bar[7] is reserved for endpoints.
  -      beat.hit = pcie_ep.rx_specific.bar[6:0];
  +      beat.hit = pcie_ep.rx_st.bar[6:0];
   
         // 128-bit interface
         // when rx_st_empty==1, rx_st_data[63:0] are valid
         if (pcie_ep.rx_st.empty[0] == 1 && pcie_ep.rx_st.eop == 1) begin
  -         if (pcie_ep.rx_specific.be == 16'h000f) begin
  +         if (pcie_ep.rx_st.be == 16'h000f) begin
               beat.data = {96'h0, pcie_ep.rx_st.data[31:0]};
            end
  -         else if (pcie_ep.rx_specific.be == 16'h00ff) begin
  +         else if (pcie_ep.rx_st.be == 16'h00ff) begin
               beat.data = {64'h0, pcie_ep.rx_st.data[63:0]};
            end
            else begin
  
positive.code: import Real              ::*;
  
  import PCIE              ::*;
  import PS5LIB            ::*;
  import PcieEndpointS5Test ::*;
  
  (* always_ready, always_enabled *)
  interface PciewrapPci_exp#(numeric type lanes);
  
negative.code: 
     rule pertick1;
        pcie_ep.rx_st.ready(pack(fAvalonStRx.notFull));
        //pcie_ep.hip_rst.core_ready(pcie_ep.hip_rst.serdes_pll_locked);
     endrule
  
     rule capture_deviceid(pcie_ep.tl_cfg.add == 4'hF);
        deviceReg <= PciId {bus: pcie_ep.tl_cfg.ctl[12:5],
                            dev: pcie_ep.tl_cfg.ctl[4:0],
                            func: 0};
     endrule
  
     // The PCIE endpoint is processing TLPData#(16)s at 125MHz.  The
  