anchor.diff:        rg_sstatus_SUM <= 0;
   `endif
   
  -      rg_state <= CPU_SPLIT_FETCH;
  +      rg_state <= CPU_START_TRAP_HANDLER;
         
         stageD.set_full (False);
         stage1.set_full (False);    fa_step_check;
  
positive.code:       if (cur_verbosity != 0)
  	 $display ("    mcause:0x%0h  epc 0x%0h  tval:0x%0h  new pc 0x%0h, new mstatus 0x%0h",
  		   mcause, epc, tval, next_pc, new_mstatus);
     endrule : rl_stage2_nonpipe
  
     // ================================================================
     // Stage1: nonpipe special: CSRRW and CSRRWI
  
negative.code:       Bool permitted = csr_regfile.access_permitted_2 (rg_cur_priv, csr_addr, read_not_write);
  
        if (! permitted) begin
  	 rg_state <= CPU_CSRRx_TRAP;
  
  	 // Debug
  	 fa_emit_instr_trace (minstret, stage1.out.data_to_stage2.pc, instr, rg_cur_priv);
  