anchor.diff:  	    );
      
      FIFOF#(Int#(32)) locf <- mkFIFOF;
  -   FIFO#(Bool) conff <- mkSizedFIFO(1);
      
      let verbose = True;
  -   let debug = False;
  +   let debug = True;
   
      Clock clk <- exposeCurrentClock;
      Reset rst <- exposeCurrentReset;
      BRAM2Port#(NeedleIdx, Char) needleBram  <- mkBRAM2Server(defaultValue);
      BRAM2Port#(NeedleIdx, Bit#(32)) mpNextBram <- mkBRAM2Server(defaultValue);
  -   FIFOF#(MemData#(haystackBusWidth)) haystackFifo <- mkFIFOF();
  +   FIFOF#(MemDataF#(haystackBusWidth)) haystackFifo <- mkFIFOF();
      Gearbox#(haystackBusBytes,1,Char) haystackGb <- mkNto1Gearbox(clk,rst,clk,rst);
   
      Reg#(Bit#(32)) cycleCnt <- mkReg(0);
      Reg#(Bit#(32)) lastHD <- mkReg(0);
      
  -   Reg#(Stage)    stage <- mkReg(Config_needle);
  +   Reg#(Stage)    stage <- mkReg(Initialized);
      Reg#(Bit#(32)) needleLenReg <- mkReg(0);
  -   Reg#(Bit#(32)) haystackLenReg <- mkReg(0);
  -   Reg#(Bit#(32)) haystackBase <- mkReg(0);
  -   Reg#(Bit#(32)) jReg <- mkReg(0); // offset in haystack
  -   Reg#(Bit#(32)) iReg <- mkReg(0); // offset in needle
  -   Reg#(Bit#(2))  epochReg <- mkReg(0);
  +   Reg#(Bit#(32)) jReg <- mkReg(1); // offset in haystack
  +   Reg#(Bit#(32)) iReg <- mkReg(1); // offset in needle
   
      BRAMPipeIn#(NeedleIdxWidth,configBusWidth) n2b <- mkBRAMPipeIn(0, needleBram.portB);
      BRAMPipeIn#(NeedleIdxWidth,configBusWidth) mp2b <- mkBRAMPipeIn(1, mpNextBram.portB);
  
positive.code: endinterface
  
  interface MPStreamEngine#(numeric type haystackBusWidth, numeric type configBusWidth);
     interface PipeIn#(MemData#(configBusWidth)) needle;
     interface PipeIn#(MemData#(configBusWidth)) mpNext;
     interface PipeIn#(MemData#(haystackBusWidth)) haystack;
     interface PipeOut#(Int#(32)) locdone;
  endinterface
  
  typedef Bit#(8) Char;
  
negative.code: import Gearbox::*;
  import Connectable::*;
  import ConfigReg::*;
  import StmtFSM::*;
  
  import MemUtils::*;
  import MemTypes::*;
  