anchor.diff:      rule clkdiv_rule if (bvi_reset_reg != 0);
           let ds = dstate;
           let dc = dcounter;
  -        let sric = sync_reset_inc_ce;
  +        Bit#(3) sric = sync_reset_inc_ce;
           let sbs = 0;
     
           dc = dc - 1;
  
positive.code: typedef enum { DIdle, DValid, DLow} DState deriving (Bits,Eq);
  typedef enum { HIdle, HHigh, HLow} HState deriving (Bits,Eq);
  typedef enum { QIdle, QTrain, QOn, QOff} QState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden, TrainRotate trainrot)(IserdesDatadeser);
  
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
      Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdes_reset);
      FIFO18 dfifo <- mkFIFO18(serdes_clock);
      IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
          cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
  
negative.code: 
  import Vector::*;
  import Clocks :: *;
  import FIFO::*;
  import XilinxCells::*;
  import XbsvXilinxCells::*;
  
  typedef Vector#(10, Reg#(Bit#(10))) TrainRotate;
  
  interface IserdesDatadeser;
      method Action           ibufdso(Bit#(1) v);
  