anchor.diff:  	 let first    = firstReg;
   	 let last     = lastReg;
   	 if (first) begin
  -	    burstLen = req.burstLen >> beat_shift;
  +	    burstLen = req_burstLen >> beat_shift;
   	    last     = dreqFifo.first.last;
  -	    respFifos.portA.request.put(BRAMRequest{write:True,responseOnWrite:False, address:truncate(rename_tag), datain:RResp{orig_tag:req.tag, client:client}});
  +	    respFifos.portA.request.put(BRAMRequest{write:True,responseOnWrite:False, address:truncate(rename_tag), datain:RResp{orig_tag:req_tag, client:client}});
   	 end
   	 burstReg <= burstLen-1;
   	 firstReg <= (burstLen-1 == 0);
  
positive.code:       let response <- toGet(readDataPipelineFifo).get();
        Bit#(MemTagSize) response_tag = response.tag;
        let drq <- dreqBram.portA.response.get;
        let otag = drq.req.tag;
        let burstLen = burstReg;
        let first =    firstReg;
        let last  =    lastReg;
        if (first) begin
  	 burstLen = drq.req.burstLen >> beat_shift;
  	 last = drq.last;
  	 dynamicAssert(last == (burstLen==1), "Last incorrect");
  	 //$display("burstLen=%d dreqFifo.first.last=%d last=%d\n", burstLen, dreqFifo.first.last, last);
  
negative.code:    
     if(valueOf(numServers) > 0)
        rule memdata;
  	 let drq = dreqFifo.first;
  	 let req_tag = drq.req_tag;
  	 let req_burstLen = drq.req_burstLen;
  	 let rename_tag = drq.rename_tag;
  	 let client = drq.client;
  	 MemData#(dataWidth) tagdata = unpack(0);
  	 if (killv[req_tag[5:4]] == False) begin
  	    tagdata = clientWriteData[client].first;
  	    clientWriteData[client].deq;
  	 end
  