anchor.diff:     endrule
   
      rule driveInputs;
  -      opmodeReg <= opmodeWire;
  +      opmode1Reg <= opmodeWire;
  +      opmode2Reg <= opmode1Reg;
  +      opmode3Reg <= opmode2Reg;
  +      opmode4Reg <= opmode3Reg;
  +
         alumodeReg <= alumodeWire;
   
         c1Reg <= cWire;
         c2Reg <= c1Reg;
         c3Reg <= c2Reg;
   
  +      //if (lastWire == 1 || last1Reg == 1 || last2Reg == 1 || last3Reg == 1 || last4Reg == 1 || last5Reg == 1)
  +	 $display("%d: a=%h b=%h c=%h p=%h", cycles, aWire, bWire, c3Reg, dsp.p());
  +
         dsp.alumode(alumodeReg);
         dsp.carryinsel(carryinselWire);
         dsp.inmode(inmodeWire);
  -      dsp.opmode(opmodeReg);
  -      //dsp.a(aWire);
  -      //dsp.b(bWire);
  -      dsp.c(c3Reg);
  +      dsp.opmode(opmode1Reg);
  +      dsp.a(aWire);
  +      dsp.b(bWire);
  +      dsp.c(c1Reg);
         //dsp.d(dWire);
   
         dsp.acin(0);
  
positive.code:    method Action d(Bit#(25) v);
        dsp.d(v);
     endmethod
     method Bit#(48) p() if (last6Reg == 1);
        return dsp.p();
     endmethod
     method Action last(Bit#(1) v);
        last1Wire <= v;
     endmethod
  endmodule
  
negative.code:    Reg#(Bit#(4)) alumodeReg <- mkReg(0);
     Wire#(Bit#(3)) carryinselWire <- mkDWire(0);
     Wire#(Bit#(5)) inmodeWire <- mkDWire(0);
     Wire#(Bit#(7)) opmodeWire <- mkDWire(7'h20);
     Reg#(Bit#(7)) opmode1Reg <- mkReg(0);
     Reg#(Bit#(7)) opmode2Reg <- mkReg(0);
     Reg#(Bit#(7)) opmode3Reg <- mkReg(0);
     Reg#(Bit#(7)) opmode4Reg <- mkReg(0);
  
     Wire#(Bit#(30)) aWire <- mkDWire(0);
     Wire#(Bit#(18)) bWire <- mkDWire(0);
  