anchor.diff:          fifo_reset <= fifo_reset_sync.read();
       endrule
   
  +    rule clear_fifo if (sync_reset_inc_ce[2] == 1);
  +        dfifo.clear();
  +    endrule
       rule setrule;
  -        dfifo.reset(sync_reset_inc_ce[2]);
           delaye2.reset(sync_reset_inc_ce[2]);
           delaye2.cinvctrl(0);
           delaye2.cntvaluein(0);
  
positive.code:            master_data.q7(), master_data.q6(), master_data.q5(),
             master_data.q4(), master_data.q3(), master_data.q2(), master_data.q1()};
          ctrl_data_temp <= dout;
          iserdes_data.send(dout);
      endrule
  
      rule datain_rule;
          Bit#(10) dout = 0;
          dout = iserdes_data.read();
          if (fifo_wren_sync.read() == 1)
              begin
              dfifo.di({6'b0,dout});
              dfifo.wren(1);
              end
          else
              begin
              dfifo.di(16'b0);
              dfifo.wren(0);
              end
      endrule
  
      rule serdesrule;
          dfifo.rden(rden);
      endrule
  
      method Action ibufdso(Bit#(1) v);
  
negative.code:     //*************************** serdes setting FSM *****************
      rule serdes_idle_rule if (bvi_reset_reg != 0 && serdes_running == 0);
          serdes_setting.deq();
          sync_reset_inc_ce <= serdes_reset_inc_ce.read();
          sync_bitslip <= serdes_bitslip.read();
          serdes_running <= 1;
  