anchor.diff:        shiftReg <= v;
      endrule
   
  -   rule updateRule2 if (bscan.update() == 1 && bscan.sel() == 1 && doincrement);
  +   rule updateRule if (bscan.update() == 1 && bscan.sel() == 1);
         bram.portB.request.put(BRAMRequest {write:True, responseOnWrite:False, address:addrReg, datain:shiftReg});
         addrReg <= addrReg + 1;
  -      doincrement <= False;
      endrule
   
      interface server = bram.portA;
  
positive.code:    Reg#(Bit#(dsz)) shiftReg <- mkReg(0, clocked_by tck, reset_by rst);
     Reg#(Bit#(asz)) addrReg <- mkReg(0, clocked_by tck, reset_by rst);
     Reg#(Bool) captured <- mkReg(False, clocked_by tck, reset_by rst);
  
     rule reset_signal;
         resetAddr.send(bscan2.capture() == 1 && bscan2.sel() == 1);
     endrule
     rule reset_addr if (resetAddr.read());
         addrReg <= 0;  // if we read USER2, reset address
     endrule
  
     rule captureRule if (bscan.capture() == 1 && bscan.sel() == 1);
         bram.portB.request.put(BRAMRequest {write:False, responseOnWrite:False, address:addrReg, datain:?});
         captured <= True;
         doincrement <= True;
     endrule
  
     Wire#(Maybe#(Bit#(dsz))) dataWire <- mkDWire(tagged Invalid, clocked_by tck, reset_by rst);
     rule captureResultRule if (captured);
        let shift <- bram.portB.response.get();
        dataWire <= tagged Valid shift;
        captured <= False;
     endrule
  
     rule shift2 if (bscan.shift() == 1 && bscan.sel() == 1);
        Bit#(dsz) shift;
        if (dataWire matches tagged Valid .data)
  	 shift = data;
        else
  	 shift = shiftReg;
        bscan.tdo(shift[0]);
  
negative.code:    Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  
     BscanE2 bscan <- mkBscanE2(bus);
     Clock tck <- mkClockBUFG(clocked_by bscan.tck);
     Reset rst <- mkAsyncReset(2, defaultReset, tck);
  
     BRAM_Configure bramCfg = defaultValue;
     bramCfg.memorySize = memorySize;
  