anchor.diff:      Clock defaultClock <- exposeCurrentClock();
       Reset defaultReset <- exposeCurrentReset();
       ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
  -    Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock,
  -        defaultClock);
  +    Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
       FIFO18 dfifo <- mkFIFO18(serdes_clock);
  -
  -    rule setrule;
  -        serbvi.serreset(serbvi.iodelay_reset_inc_ce()[2]);
  -    endrule
  -    rule setrule9;
  -        dfifo.reset(serbvi.iodelay_reset_inc_ce()[2]);
  -    endrule
       IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
           cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
           high_performance_mode: "TRUE",
           idelay_type: "VARIABLE", idelay_value: 0,
           pipe_sel: "FALSE", refclk_frequency: 200, signal_pattern: "DATA"},
  -        defaultClock,
  -        clocked_by serdes_clock);
  -
  -    rule delaye2_rule;
  -        delaye2.cinvctrl(0);
  -        delaye2.cntvaluein(0);
  -        delaye2.ld(0);
  -        delaye2.ldpipeen(0);
  -        delaye2.datain(0);
  -        delaye2.inc(serbvi.iodelay_reset_inc_ce()[1] == 1);
  -        delaye2.ce(serbvi.iodelay_reset_inc_ce()[0]);
  -    endrule
  -
  +        defaultClock, clocked_by serdes_clock);
       IserdesE2 master_data <- mkISERDESE2( ISERDESE2_Config{
           data_rate: "DDR", data_width: 10,
           dyn_clk_inv_en: "FALSE", dyn_clkdiv_inv_en: "FALSE",
  
positive.code:         master_data.oclk(0);
          master_data.oclkb(0);
          master_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
          dout[0] = master_data.q1();
          dout[1] = master_data.q2();
          dout[2] = master_data.q3();
          dout[3] = master_data.q4();
          dout[4] = master_data.q5();
          dout[5] = master_data.q6();
          dout[6] = master_data.q7();
          dout[7] = master_data.q8();
          slave_data.d(0);
          slave_data.bitslip(serbvi.bitslip());
          slave_data.ce1(1);
  
negative.code:         slave_data.dynclksel(0);
          slave_data.shiftin1(master_data.shiftout1());
          slave_data.shiftin2(master_data.shiftout2());
          dout = {slave_data.q4(), slave_data.q3(), master_data.q8(),
             master_data.q7(), master_data.q6(), master_data.q5(),
             master_data.q4(), master_data.q3(), master_data.q2(), master_data.q1()};
          slave_data.oclk(0);
          slave_data.oclkb(0);
          slave_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
          serbvi.dataout(dout);
          dfifo.di({6'b0,dout});
          serbvi.idelay_out(delaye2.dataout());
      endrule
  
  