anchor.diff:     // Condition: 32b instr from { ...next imem [15:0], imem [31:16] }
      Bool cond_i32_odd_fetch_next = (   is_addr_odd16 (rg_pc)
   				   && imem32.valid
  +				   && (! imem32.exc)
   				   && eq_b32_addr (rg_pc, imem32.pc)
   				   && is_32b_instr (imem32.instr [31:16]));
   
  
positive.code: // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
  
  package CPU_Fetch_C;
  
  
negative.code: 
     // Holds a faulting address
     Reg #(WordXL)    rg_tval        <- mkRegU;
  
     // These registers caches the last output of imem32 (imem32.pc, and imem32.instr [31:16])
     Reg #(WordXL)    rg_cache_addr <- mkReg ('1);
     Reg #(Bit #(16)) rg_cache_b16  <- mkRegU;
  
     // ----------------------------------------------------------------
     // Conditions for selecting 16b and 32b instruction
  