anchor.diff:        deparser_start_time <= clk_cnt;
       end
     endrule
  -  rule clear if (!start_fsm && curr_state == StateDeparseIdle);
  +  rule stop if (!start_fsm && curr_state == StateDeparseIdle);
       if (started) begin
  -      deparse_ethernet.clear;
  -      deparse_ipv4.clear;
  +      deparse_ethernet.stop;
  +      deparse_ipv4.stop;
         started <= False;
         deparser_end_time <= clk_cnt;
       end
  
positive.code:   method Action stop;
  endinterface
  module mkStateParseEthernet#(Reg#(ParserState) state, FIFOF#(EtherData) datain)(ParseEthernet);
    let verbose = True;
    FIFOF#(Bit#(16)) unparsed_parse_ipv4_fifo <- mkSizedFIFOF(1);
  
    FIFOF#(Bit#(16)) parsed_etherType_fifo <- mkFIFOF;
  
    Wire#(Bit#(128)) packet_in_wire <- mkDWire(0);
    Vector#(4, Wire#(Maybe#(ParserState))) next_state_wire <- replicateM(mkDWire(tagged Invalid));
    PulseWire start_wire <- mkPulseWire();
    PulseWire clear_wire <- mkPulseWire();
    (* fire_when_enabled *)
    rule arbitrate_outgoing_state if (state == StateParseEthernet);
      Vector#(4, Bool) next_state_valid = replicate(False);
  
negative.code:     packet_in_wire <= data_current.data;
    endrule
  
    Stmt parse_ethernet =
    seq
    action
      let data_this_cycle = packet_in_wire;
      Vector#(128, Bit#(1)) dataVec = unpack(data_this_cycle);
      Vector#(16, Bit#(1)) unparsed = takeAt(112, dataVec);
      let ethernet_t = extract_ethernet_t(pack(takeAt(0, dataVec)));
      let nextState = compute_next_state(ethernet_t.etherType);
      if (verbose) $display("Goto state ", nextState);
      if (nextState == StateParseIpv4) begin
        unparsed_parse_ipv4_fifo.enq(pack(unparsed));
  