anchor.diff:     Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);
      Reg#(Bit#(32))              srcGens <- mkReg(0);
   
  +   ConfigCounter#(16) counter          <- mkConfigCounter(0);
      FIFO#(MemRequest) readReqFifo <- mkFIFO();
      FIFO#(MemRequest) writeReqFifo <- mkFIFO();
      FIFO#(MemData#(DataBusWidth))   dataFifo <- mkSizedBRAMFIFO(1024);
  
positive.code: 
     let verboseProgress = False;
  
     rule startReqRule if (numReqs != 0);
        readReqFifo.enq(MemRequest { sglId: readPointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag) });
        writeReqFifo.enq(MemRequest { sglId: writePointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag) });
  
        numReqs <= numReqs - 1;
        reqOffset <= reqOffset + extend(burstLenBytes);
        tag <= tag + 1;
        //$display("start numReqs", numReqs);
     endrule
  
     rule finish;
        let donetag <- toGet(doneFifo).get();
        //$display("finished num todo=%d", numDone);
        if (numDone == 1) begin
           indication.copyDone(0);
        end
  
negative.code: 
  interface Memcopy;
     interface MemcopyRequest request;
     interface Vector#(1, MemReadClient#(DataBusWidth)) readClients;
     interface Vector#(1, MemWriteClient#(DataBusWidth)) writeClients;
  endinterface
  
  module  mkMemcopy#(MemcopyIndication indication) (Memcopy);
  