anchor.diff:        if(debug) $display("mkMemReadInternal::complete_burst0 %h", tag);
      endrule
      
  -   rule complete_burst1a if (compReg0==0);
  +   rule complete_burst1a if (compCountReg==0);
         let drq <- dreqBram.portB.response.get;
         let cnt = drq.req.burstLen >> beat_shift;
         let cli = drq.client;
  
positive.code: 	 compFifo0.enq(extend(cli));
  	 readBufferBram.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        end
        compReg0 <= cnt-1;
        compReg1 <= tag;
        compReg2 <= cli;
        compReg3 <= drq.req.tag[5:4];
        if(debug) $display("mkMemReadInternal::complete_burst1a %h", cli);
     endrule
  
     rule complete_burst1b if (compReg0 > 0);
        let cnt = compReg0;
        let tag = compReg1;
        let cli = compReg2;
        if(killv[compReg3] == False) begin
  	 compFifo0.enq(extend(cli));
  	 readBufferBram.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        end
        compReg0 <= cnt-1;
        if(debug) $display("mkMemReadInternal::complete_burst1b %h", compReg0);
     endrule
           
     rule checkMmuResp;
  
negative.code:    let beat_shift = fromInteger(valueOf(beatShift));
     TagGen#(numTags) tag_gen <- mkTagGen;
  
     Reg#(Bit#(BurstLenSize))      compCountReg <- mkReg(0);
     Reg#(Bit#(TLog#(numTags)))    compTagReg <- mkReg(0);
     Reg#(Bit#(TLog#(TMax#(1,numServers)))) compClientReg <- mkReg(0);
     Reg#(Bit#(2))                 compTileReg <- mkReg(0);
     FIFO#(Bit#(TAdd#(1,TLog#(TMax#(1,numServers))))) compFifo0 <- mkFIFO;
     FIFO#(Bit#(TLog#(numTags)))   compFifo1 <- mkFIFO;
     
  