anchor.diff:  	  interruptSecondHalf <= True;
          end
   
  -       tlpTag <= tlpTag + 1;
  +       //tlpTag <= tlpTag + 1;
   
          tlpOutFifo.enq(tlp);
       endrule
  
positive.code: 	interface Axi3SlaveRead read;
  	   method Action readAddr(Bit#(40) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
  				  Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) arid);
                 TLPMemory4DWHeader hdr_4dw = defaultValue;
  	       hdr_4dw.format = MEM_READ_4DW_NO_DATA;
  	       hdr_4dw.tag = truncate(arid);
  	       hdr_4dw.reqid = my_id;
  	       hdr_4dw.nosnoop = SNOOPING_REQD;
  	       hdr_4dw.addr = addr[40-1:2];
  	       hdr_4dw.length = 1;
  	       hdr_4dw.firstbe = 4'hf;
  	       hdr_4dw.lastbe = 0;
  	       TLPData#(16) tlp = defaultValue;
  	       tlp.data = pack(hdr_4dw);
  	       tlp.sof = True;
  	       tlp.eof = True;
  	       tlp.hit = 7'h00;
  	       tlp.be = 16'hffff;
  	       tlpOutFifo.enq(tlp);
             endmethod: readAddr
  	   method ActionValue#(Bit#(64)) readData();
  	       let hdr = completionFifo.first;
  	       completionFifo.deq;
  	       return extend(hdr.data);
             endmethod: readData
  	   method Bit#(1) last();
  	       return 1;
             endmethod: last
  	   method Bit#(12) rid();
  	       return zeroExtend(completionFifo.first.tag);
             endmethod: rid
  	   // method Action readResponse(Bit#(2) responseCode);
  	endinterface: read
      endinterface: slave
     method Bool tlpOutFifoNotEmpty() = tlpOutFifo.notEmpty;
  endmodule: mkAxiSlaveEngine
  
  typedef enum {
  
negative.code:        csr.tlpTracing <= False;
     endrule
     rule connectEnables;
        dispatcher.axiEnabled <= csr.axiEnabled;
        portalEngine.pipeliningEnabled <= csr.pipeliningEnabled;
        portalEngine.byteSwap <= csr.byteSwap;
        axiSlaveEngine.use4dw <= csr.use4dw;
     endrule
  
     // connect the sub-components to each other
  