anchor.diff:  module mkMemServerFromBram#(BRAMServer#(Bit#(bramAddrWidth), Bit#(busDataWidth)) br) (MemServer#(busDataWidth))
      provisos(Add#(a__, bramAddrWidth, MemOffsetSize));
   
  -   FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();
  +   FIFOF#(Tuple2#(Bit#(6),Bool))  readTagFifo <- mkFIFOF();
      FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();
  -   FIFO#(Bool)     readLastFifo <- mkFIFO();
      AddressGenerator#(bramAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
      AddressGenerator#(bramAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
      let verbose = False;
  
positive.code:       endinterface
        interface Get readData;
  	 method ActionValue#(MemData#(busDataWidth)) get();
  	    let tag = readTagFifo.first;
  	    readTagFifo.deq;
  	    readLastFifo.deq;
              let data <- br.response.get;
              if (verbose) $display("%d read_server.readData (b) %h", cycles, data);
              return MemData { data: data, tag: tag, last: readLastFifo.first };
  	 endmethod
        endinterface
     endinterface
  
negative.code:       let addr = addrBeat.addr;
        let tag = addrBeat.tag;
        let burstCount = addrBeat.bc;
        readTagFifo.enq(tuple2(tag, addrBeat.last));
        Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));
        br.request.put(BRAMRequest{write:False, responseOnWrite:False, address:regFileAddr, datain:?});
        if (verbose) $display("%d read_server.readData (a) %h %d last=%d", cycles, addr, burstCount, addrBeat.last);
  