anchor.diff:     Reg#(DmaPointer) ptr <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) woff <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) wbase <- mkReg(0);
  -   
  -   let writeFifo <- mkFIFOF;
  +   Gearbox#(1,nd,Bit#(dsz)) gb <- mk1toNGearbox(clk,rst,clk,rst);
  +   
  +   FIFOF#(Bit#(busWidth)) writeFifo = (interface FIFOF;
  +				       method Bit#(busWidth) first(); return pack(gb.first); endmethod
  +				       method Bool notEmpty(); return gb.notEmpty(); endmethod
  +				       endinterface);
      MemwriteEngine#(busWidth) we <- mkMemwriteEngine(writeFifo);
      let bus_width_in_bytes = fromInteger(valueOf(busWidth)/8);
      
  
positive.code: 
  endmodule
  
  module mkBRAMWriteClient#(BRAMServer#(bramIdx,Bit#(busWidth)) br)(BRAMWriteClient#(bramIdx,busWidth))
     
     provisos(Eq#(bramIdx),
  	    Bits#(bramIdx, a__),
  	    Ord#(bramIdx),
  	    Arith#(bramIdx));
  
     FIFO#(void) f <- mkSizedFIFO(1);
     Reg#(bramIdx) n <- mkReg(0);
  
negative.code:    endrule
  
     rule bramResp;
        d rv <- br.response.get;
        gb.enq(cons(pack(rv), nil));
     endrule
     
     rule loadReq(i < n);
  