anchor.diff:          serdes_end.deq();
           maxcount <= 31;
           gencounter <= 15;
  -        astate <= AWDelay;
  -    endrule
  -    rule afsmwdelay_rule if (bvi_resets_reg.read() != 0 && astate == AWDelay);
           astate <= AEdge;
           serdes_start.enq(0);
       endrule
  
positive.code:                 else if (gencounter == 8)
                      csamplein = 3'b100;
                  ctrl_sample <= csamplein;
                  as = AValid;
                  end
              gc = gc - 1;
              end
          astate <= as;
          gencounter <= gc;
      endrule
      rule afsmvalid_rule if (bvi_resets_reg.read() != 0 && astate == AValid);
          maxcount <= maxcount - 1;
          astate <= A1Changed;
          serdes_start.enq(2'b11);
      endrule
      rule afsm1changed_rule if (bvi_resets_reg.read() != 0 && astate == A1Changed);
          serdes_end.deq();
  
negative.code: endinterface: IserdesDatadeser
  
  typedef enum { QIdle, QTrain, QOff} QState deriving (Bits,Eq);
  typedef enum { AIdle, ADelay, AEdge, ACEdge, AWait, ACompare,
       A1Changed, A1Stable, ASecond, AFound, AManual, AStart, AAlign, ADone } AState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
  