anchor.diff:     Reg#(Bit#(1)) selreg <- mkReg(1);
      Reg#(Bit#(TAdd#(logawidth,1))) countreg <- mkReg(0);
      FIFOF#(a) resultFifo <- mkFIFOF;
  +
  +   Clock outputClock = invert_clk ? clockInverter.slowClock : defaultClock;
  +   Reset outputReset = defaultReset;
  +   ReadOnly#(Bit#(awidth)) sync_shiftreg <- mkNullCrossingWire(outputClock, shiftreg);
   
      Wire#(Bit#(1)) misoWire <- mkDWire(0);
      let verbose = False;
  
positive.code:    endrule
  
     rule miso if (spi.pins.sel_n == 0);
        spi.pins.miso(slaveValue[19]);
     endrule
  
     rule spipins if (spi.pins.sel_n == 0);
        if(verbose) $display("miso=%d mosi=%d sel=%d", slaveValue[19], spi.pins.mosi, spi.pins.sel_n);
        responseValue <= { responseValue[18:0], spi.pins.mosi };
     endrule
  
  
negative.code:       method Action miso(Bit#(1) v);
           misoWire <= v;
        endmethod
        interface Clock clock = outputClock;
        interface Clock deleteme_unused_clock = invert_clk ? defaultClock : clockInverter.slowClock;
        interface Reset deleteme_unused_reset = defaultReset;
     endinterface: pins
  