anchor.diff:  	 axiSlave.rready(pack(rfifo.notFull && arInFlight.notEmpty));
         endrule
         rule rl_rdata if (axiSlave.rvalid() == 1);
  -	 let ar = arInFlight.first; // implicit guard (arInFlight should not be empty to fire this rule)
  +	 let dummy = arInFlight.first; // implicit guard (arInFlight should not be empty to fire this rule)
   	 let last = axiSlave.rlast == 1;
   	 if (last) arInFlight.deq;
   
  -	 rfifo.enq(MemData { data: truncate(axiSlave.rdata()), tag: ar?axiSlave.rid():0, last: last } );
  +	 rfifo.enq(MemData { data: truncate(axiSlave.rdata()), tag: axiSlave.rid(), last: last } );
         endrule
   
         rule rl_awvalid_awaddr;
  -	 axiSlave.awvalid(pack(awfifo.notEmpty && wtagfifo.notFull));
  +	 axiSlave.awvalid(pack(awfifo.notEmpty && awInFlight.notFull));
         endrule
         rule rl_awfifo if (axiSlave.awready() == 1);
   	 let req <- toGet(awfifo).get();
  
positive.code: 	 axiSlave.awsize(axireq.size);
  	 axiSlave.awlen(axireq.len);
  	 axiSlave.awburst(2'b01);     // burst: INCR
  	 axiSlave.awcache(4'b0011);   //FIXME
  	 axiSlave.awlock(2'b0);       // normal access 
  	 axiSlave.awprot(3'b0);       // unprevileged, protedted, data access
  	 axiSlave.awqos(4'b0);        // unused - default 0
  	 axiSlave.extra.awuser(1'b0); // unused
  	 wtagfifo.enq(req.tag);
        endrule
        rule rl_wvalid;
  	 axiSlave.wvalid(pack(wfifo.notEmpty));
  
negative.code:       FIFOF#(MemData#(DataBusWidth)) wfifo <- mkAxiFifoF();
        FIFOF#(Bit#(MemTagSize)) bfifo <- mkAxiFifoF();
  
        FIFOF#(Bool) arInFlight <- mkSizedFIFOF(valueOf(TExp#(MemTagSize)));
        FIFOF#(Bool) awInFlight <- mkSizedFIFOF(valueOf(TExp#(MemTagSize)));
  
  	Probe#(Bit#(1)) arNF <- mkProbe();
  	Probe#(Bit#(1)) arNE <- mkProbe();
  