anchor.diff:     
      rule complete_burst0;
         let tag <- tag_gen.complete;
  -      dreqFifos.portB.request.put(BRAMRequest{write:False, address:tag});      
  +      dreqFifos.portB.request.put(BRAMRequest{write:False, address:tag, responseOnWrite: ?, datain: ?});      
         compFifo1.enq(tag);
      endrule
      
  
positive.code:       let cli = drq.client;
        let tag <- toGet(compFifo1).get;
        compFifo0.enq(cli);
        read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}});
        compReg0 <= cnt-1;
        compReg1 <= tag;
        compReg2 <= cli;
  
negative.code:    // consider access to portA and portB to be conflict free **sigh** 
     rule ret;
        let tag <- toGet(retFifo).get;
        tags.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:tag, datain:False});
        comp_state <= 1 | (comp_state << 1);
     endrule
  
     rule init(!inited);
        tags.portA.request.put(BRAMRequest{write:True,address:head_ptr,responseOnWrite:False,datain:False});
        head_ptr <= head_ptr+1;
        inited <= head_ptr+1==0;
     endrule
     
     method ActionValue#(Bit#(tsz)) getTag() if (inited && (head_ptr+1 != tail_ptr));
        tags.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, address:head_ptr, datain:True});
        head_ptr <= head_ptr+1;
        return head_ptr;
     endmethod
  