anchor.diff:  		  interface Get readData;
   		     method ActionValue#(MemData#(dataWidth)) get if (compFifo0.first == fromInteger(i));
   			compFifo0.deq;
  -			let data <- read_buffer.portB.response.get;
  +			let data <- readBufferBram.portB.response.get;
   			if (debug) $display("mkMemReadInternal::comp %d  %x %d", i, data.data, cycle_cnt-last_comp);
   			last_comp <= cycle_cnt;
   			return data;
  
positive.code:    // stage 1: address validation (latency = 1)
     FIFO#(RRec#(numServers,addrWidth))  reqFifo <- mkFIFO;
     // stage 2: read commands
     BRAM2Port#(Bit#(TLog#(numTags)), DRec#(numServers,addrWidth)) dreqFifos <- mkBRAM2Server(defaultValue);
     BRAM2Port#(Bit#(TAdd#(TLog#(numTags),TSub#(BurstLenSize,beatShift))), MemData#(dataWidth)) read_buffer <- mkBRAM2Server(defaultValue);
     // stage 3: read data 
     FIFO#(MemData#(dataWidth)) readDataPipelineFifo <- mkFIFO;
     
  
negative.code:    rule read_data;
        let response <- toGet(readDataPipelineFifo).get();
        Bit#(MemTagSize) response_tag = response.tag;
        let drq <- dreqBram.portA.response.get;
        let otag = drq.req.tag;
        let burstLen = burstReg;
        let first =    firstReg;
  