anchor.diff:      return ret_ifc;
   endmodule
   
  +`ifndef SIMULATION
   module mkAsymmetricBRAMVerilog#(Bool hasOutputRegister, Bool hasForwarding)
                                  (AsymmetricBRAM#(raddr_t, rdata_t, waddr_t, wdata_t))
       provisos(
  
positive.code: 
  // Assume narrower write port
  // Wrapper for the verilog
  `ifdef ALTERA
  import "BVI" AsymmetricBRAM_Altera =
  `else
  import "BVI" AsymmetricBRAM_Xilinx =
  module vAsymBRAM#(Bool hasOutputRegister)
                   (VAsymBRAMIfc#(raddr_t, rdata_t, waddr_t, wdata_t))
      provisos(
  
negative.code:    endinterface);
  
  endmodule
  `endif
  
  import "BDPI" mem_create    = function ActionValue#(Bit#(64)) mem_create(msize_t size, rsize_t rsize, wsize_t wsize)
                                provisos (Bits#(msize_t, msize_sz),
  