anchor.diff:      Reg#(Bit#(12)) medeleg_field <- mkReg(0);
       Reg#(Bit#(12)) mideleg_field <- mkReg(0);
   
  -    // trap vector fields (same as CSR without bottom 2 bits
  -    Reg#(Bit#(62)) mtvec_field <- mkReg(default_mtvec[63:2]);
  -    Reg#(Bit#(62)) stvec_field <- mkReg(default_stvec[63:2]);
  +    // trap vector fields (same as CSR without bottom 2 bits)
  +    Reg#(Bit#(TSub#(XLEN,2))) mtvec_field <- mkReg(truncateLSB(default_mtvec));
  +    Reg#(Bit#(TSub#(XLEN,2))) stvec_field <- mkReg(truncateLSB(default_stvec));
   
       // mstatus fields
       Reg#(Bit#(5)) vm_field   <- mkReg(0); // WARL
  
positive.code:     // Supervisor
      Reg#(Data) sstatus_csr =  concatReg20(
              sd_field,
              readOnlyReg(0),
              vm_field,
              readOnlyReg(4'b0),
              readOnlyReg(1'b0), pum_field, readOnlyReg(1'b0), // memory privilege
  
negative.code:     // Priv 1.9 CSRs
  
      // Machine Timers and Counters
      // TODO: support 32-bit ISA
      Reg#(Data) mcycle_csr   = readOnlyReg(truncate(cycle_counter));
      Reg#(Data) mtime_csr    = readOnlyReg(truncate(mtime));
      Reg#(Data) minstret_csr = readOnlyReg(truncate(instret_counter));
  
      // Machine Counter-Delta Registers
      // TODO: support 32-bit ISA
      Reg#(Data) mucycle_delta_csr   <- mkReg(0);
      Reg#(Data) mutime_delta_csr    <- mkReg(0);
      Reg#(Data) muinstret_delta_csr <- mkReg(0);
  