anchor.diff:     let portalTop <- mkPortalTop(clocked_by epClock125, reset_by epReset125);
      PcieHost#(dsz) pciehost <- mkPcieHost(epClock250, epReset250,
            PciId{ bus:  _ep.cfg.bus_number(), dev: _ep.cfg.device_number(), func: _ep.cfg.function_number()},
  -         //portalTop.slave,
            portalTop.masters,
  -         portalTop.interrupt,
            _ep.tlp, clocked_by epClock125, reset_by epReset125);
   
      mkConnection(pciehost.master, portalTop.slave, clocked_by epClock125, reset_by epReset125);
  +
  +   // going from level to edge-triggered interrupt
  +   Vector#(15, Reg#(Bool)) interruptRequested <- replicateM(mkReg(False, clocked_by epClock125, reset_by epReset125));
  +   rule interrupt_rule;
  +     Integer intr_num = 0;
  +     for (Integer i = 0; i < 15; i = i + 1) begin
  +	 if (intr_num == 0 && portalTop.interrupt[i] && !interruptRequested[i])
  +             intr_num = i+1;
  +	 interruptRequested[i] <= portalTop.interrupt[i];
  +     end
  +     if (intr_num != 0) begin // i= 0 for the directory
  +        MSIX_Entry msixEntry = pciehost.msixEntry[intr_num];
  +        pciehost.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));
  +     end
  +   endrule
   
      interface pcie = _ep.pcie;
      method Bit#(NumLeds) leds();
  
positive.code: endinterface
  
  module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId,
     //MemSlave#(32,32) ptslave,
     Vector#(`NumberOfMasters,MemMaster#(40, dsz)) masters,
     Vector#(16,ReadOnly#(Bool)) ptinterrupt,
  Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(dsz))
  provisos(
     Mul#(TDiv#(dsz, 8), 8, dsz),
  
negative.code:       m_axis[0] <- mkAxiDmaMaster(masters[0]);
        mkConnection(m_axis[0], dmaEngine.slave);
     end
     interface msixEntry = csr.msixEntry;
     interface master = portalEngine.master;
     interface slave = dmaEngine.slave;
  