anchor.diff:  
   interface AxiEthTestRequest;
      method Action reset();
  +   method Action setupDma(Bit#(32) memref);
      method Action read(Bit#(32) addr);
      method Action write(Bit#(32) addr, Bit#(32) value);
   endinterface
  
positive.code:    interface AxiEthTestRequest request;
        method Action reset();
        endmethod
        method Action read(Bit#(32) addr);
  	 memSlaveMux.read_server.readReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });
        endmethod
  
negative.code:    let axiEthBvi <- mkAxiEthBvi(host.tsys_clk_200mhz_buf,
  				clock, reset, clock,
  				reset, reset, reset, reset);
  
     Reg#(Bit#(32)) objId <- mkReg(0);
  
     let irqLevel <- mkReg(0);
     let intrLevel <- mkReg(0);
  