anchor.diff:  	 axiSlave.awid(axireq.id);
   	 axiSlave.awsize(axireq.size);
   	 axiSlave.awlen(axireq.len);
  -	 axiSlave.awburst(2'b01);   //FIXME
  -	 axiSlave.awcache(4'b0011); //FIXME
  -	 //FIXME axiSlave.extra.awuser();
  +	 axiSlave.awburst(2'b01);     // burst: INCR
  +	 axiSlave.awcache(4'b0011);   //FIXME
  +	 axiSlave.awlock(2'b0);       // normal access 
  +	 axiSlave.awprot(3'b0);       // unprevileged, protedted, data access
  +	 axiSlave.awqos(4'b0);        // unused - default 0
  +	 axiSlave.extra.awuser(1'b0); // unused
   	 wtagfifo.enq(req.tag);
         endrule
         rule rl_wvalid;
  
positive.code: 	 axiSlave.arid(axireq.id);
  	 axiSlave.arsize(axireq.size);
  	 axiSlave.arlen(axireq.len);
  	 axiSlave.arburst(2'b01);   //FIXME
  	 axiSlave.arcache(4'b0011); //FIXME
  	 //FIXME axiSlave.extra.aruser();
  	 rtagfifo.enq(req.tag);
        endrule
        rule rl_rready;
  	 axiSlave.rready(pack(rfifo.notFull && rtagfifo.notEmpty));
        endrule
        rule rl_rdata if (axiSlave.rvalid() == 1);
  	 let rtag <- toGet(rtagfifo).get();
  	 rfifo.enq(MemData { data: truncate(axiSlave.rdata()), tag: rtag } );
        endrule
  
        rule rl_awvalid_awaddr;
  
negative.code: 
  instance ConnectableWithTrace#(PS8LIB, Platform, traceType);
     module mkConnectionWithTrace#(PS8LIB psu, Platform top, traceType readout)(Empty);
        Axi4MasterBits#(40,128,16,Ps8MaxigpExtra) master = toAxi4MasterBits(psu.m_axi_gp[0]);
        PhysMemMaster#(32,32) physMemMaster <- mkPhysMemMaster(master);
        mkConnection(physMemMaster, top.slave);
  
        Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra) slave = toAxi4SlaveBits(psu.s_axi_gp[0]);
        PhysMemSlave#(40,DataBusWidth) physMemSlave <- mkPhysMemSlave(slave);
        mkConnection(top.masters[0], physMemSlave);
     endmodule
  endinstance
  