anchor.diff:     Bool break_into_Debug_Mode = False;
   `endif
   
  -   rule rl_stage1_trap (   (   (rg_state == CPU_TRAP)
  +   rule rl_stage1_trap (   (   (rg_state == CPU_CSRRx_TRAP)
   			    || (   (rg_state == CPU_RUNNING)
   				&& (! halting)
   				&& (stage3.out.ostatus == OSTATUS_EMPTY)
  
positive.code: 	      CPU_DEBUG_MODE,       // Stopped (normally for debugger)
  	      CPU_RUNNING,          // Normal operation
  	      CPU_TRAP,
  	      CPU_SPLIT_FETCH,      // To initiate IFetch after traps/interrupts/RET
  	      CPU_CSRRX_RESTART,    // Restart pipe after a CSRRX instruction
  	      CPU_FENCE_I,          // While waiting for FENCE.I to complete in Near_Mem
  	      CPU_FENCE,            // While waiting for FENCE to complete in Near_Mem
  
negative.code:       rg_sstatus_SUM <= 0;
  `endif
  
        rg_state <= CPU_START_TRAP_HANDLER;
        
        stageD.set_full (False);
        stage1.set_full (False);    fa_step_check;
  