anchor.diff:  import AxiMasterSlave::*;
   import Axi4MasterSlave::*;
   import AxiBits::*;
  +import GetPutM::*;
  +import FIFOF::*;
  +
  +instance ToPutM#(AxiMasterBits#(addrWidth,dataWidth,tagWidth,Empty), Axi3ReadResponse#(dataWidth, tagWidth));
  +   module toPutM#(AxiMasterBits#(addrWidth, dataWidth, tagWidth, Empty) m)(Put#(Axi3ReadResponse#(dataWidth, tagWidth)));
  +      FIFOF#(Axi3ReadResponse#(dataWidth, tagWidth)) dfifo <- mkFIFOF();
  +
  +      rule handshake;
  +          m.rvalid(pack(dfifo.notEmpty()));
  +      endrule
  +
  +      rule deq if (unpack(m.rready()));
  +          let d = dfifo.first;
  +          m.rid(d.id);
  +          m.rresp(d.resp);
  +          m.rdata(d.data);
  +          m.rlast(d.last);
  +          dfifo.deq;
  +      endrule
  +
  +      return toPut(dfifo);
  +   endmodule
  +endinstance
  +
  +instance ToPutM#(AxiMasterBits#(addrWidth,dataWidth,tagWidth,Empty), Axi3WriteResponse#(tagWidth));
  +   module toPutM#(AxiMasterBits#(addrWidth, dataWidth, tagWidth, Empty) m)(Put#(Axi3WriteResponse#(tagWidth)));
  +      FIFOF#(Axi3WriteResponse#(tagWidth)) dfifo <- mkFIFOF();
  +
  +      rule handshake;
  +          m.bvalid(pack(dfifo.notEmpty()));
  +      endrule
  +
  +      rule deq if (unpack(m.rready()));
  +          let d = dfifo.first;
  +          m.bid(d.id);
  +          m.bresp(d.resp);
  +          dfifo.deq;
  +      endrule
  +
  +      return toPut(dfifo);
  +   endmodule
  +endinstance
   
   interface AxiMasterCommon#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth);
       method Bit#(1)            aresetn();
  
positive.code:                 return v;
              endmethod
          endinterface
          interface Put resp_b;
              method Action put(Axi3WriteResponse#(tagWidth) v) if (axiWires.bready() != 0);
                  bvalid <= 1;
                  bid    <= v.id;
                  bresp  <= v.resp;
              endmethod
          endinterface
      endinterface
      method aresetn = axiWires.aresetn;
  endmodule
  
negative.code:    rule handshake2;
          axiWires.awready(awready);
     endrule
     rule handshake4;
          axiWires.wready(wready);
     endrule
  
     // rule handshake 3 & 5 done in toPutM modules
     Put#(Axi3ReadResponse#(dataWidth, tagWidth)) resp_read_put <- toPutM(axiWires);
     Put#(Axi3WriteResponse#(tagWidth)) resp_b_put <- toPutM(axiWires);
  
     interface Axi3Master client;
          interface Get req_ar;
  