anchor.diff:  
       Clock defaultClock <- exposeCurrentClock();
       Reset defaultReset <- exposeCurrentReset();
  -    ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
  -    Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
  +    Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock);
       FIFO18 dfifo <- mkFIFO18(serdes_clock);
       IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
           cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
  
positive.code:         idelay_type: "VARIABLE", idelay_value: 0,
          pipe_sel: "FALSE", refclk_frequency: 200, signal_pattern: "DATA"},
          defaultClock, clocked_by serdes_clock);
      IserdesE2 master_data <- mkISERDESE2( ISERDESE2_Config{
          data_rate: "DDR", data_width: 10,
          dyn_clk_inv_en: "FALSE", dyn_clkdiv_inv_en: "FALSE",
  
negative.code:       method                  delay_wren(DELAY_WREN) enable((*inhigh*) en11) clocked_by (clkdiv);
        method                  reset(RESET) enable((*inhigh*) en17) clocked_by (clkdiv);
        method                  dataout(ISERDES_DATA) enable((*inhigh*) en18) clocked_by(clkdiv);
     schedule (fifo_reset, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
           CF (fifo_reset, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  