anchor.diff:     Reset portalReset_ = epPcieReset;
   
      PcieHost#(DataBusWidth, NumberOfMasters) pciehost <- mkPcieHost(ep7.device, clocked_by portalClock_, reset_by portalReset_);
  -   mkConnection(ep7.tlp, pciehost.pci, clocked_by portalClock_, reset_by portalReset_);
  +   mkConnection(ep7.tlp, pciehost.pcic, clocked_by portalClock_, reset_by portalReset_);
   
      interface PcieEndpointS5 tep7 = ep7;
      interface PcieHost tpciehost = pciehost;
  
positive.code: `endif
  `endif
  endmodule: mkPcieHost
  
  interface PcieTop#(type ipins);
  `ifndef BSIM
  
negative.code:    return memSlaveEngine;
  endmodule
  
  // ==================================================
  // PCIE Gen3  PcieHost
  //
  `ifdef PCIE3
  Integer tlpCompleterRequest = 0;
  Integer tlpRequesterRequest = 1;
  typedef 2   NumberOfTlpIntfs;
  
  module mkPcieHost(PcieHost#(DataBusWidth, NumberOfMasters));
     Vector#(NumberOfTlpIntfs, TLPDispatcher) dispatcher <- replicateM(mkTLPDispatcher);
     Vector#(NumberOfTlpIntfs, TLPArbiter) arbiter <- replicateM(mkTLPArbiter);
     Vector#(NumberOfMasters, MemSlaveEngine#(DataBusWidth)) sEngine <- replicateM(mkMemSlaveEngineSynth(my_pciId));
     Vector#(NumberOfMasters,PhysMemSlave#(PciePhysAddrWidth,DataBusWidth)) slavearr;
     MemInterrupt intr <- mkMemInterrupt(my_pciId);
     Vector#(PortMax, MemMasterEngine) mvec;
     for (Integer i=0; i < valueOf(NumberOfMasters); i=i+1) begin
        let tlp;
        tlp = sEngine[i].tlp;
        slavearr[i]  = sEngine[i].slave;
        mkConnection((interface Server;
                         interface response = dispatcher[tlpRequesterRequest].out[i];
                         interface request = arbiter[tlpRequesterRequest].in[i];
                      endinterface), tlp);
     end
     for (Integer i=0; i < valueOf(PortMax) - 1; i=i+1) begin
        let tlp;
        if (i == portInterrupt)
           tlp = intr.tlp;
        else begin
           mvec[i] <- mkMemMasterEngine(my_pciId);
           tlp = mvec[i].tlp;
        end
        mkConnection((interface Server;
                         interface response = dispatcher[tlpCompleterRequest].out[i];
                         interface request = arbiter[tlpCompleterRequest].in[i];
                      endinterface), tlp);
     end
  
     Vector#(NumberOfTlpIntfs, PcieTracer) traceif <- replicateM(mkPcieTracer());
     mkConnection(traceif[tlpCompleterRequest].bus, (interface Client;
                                      interface request = arbiter[tlpCompleterRequest].outToBus;
                                      interface response = dispatcher[tlpCompleterRequest].inFromBus;
                                   endinterface));
     mkConnection(traceif[tlpRequesterRequest].bus, (interface Client;
                                      interface request = arbiter[tlpRequesterRequest].outToBus;
                                      interface response = dispatcher[tlpRequesterRequest].inFromBus;
                                   endinterface));
  
     PcieControlAndStatusRegs csr <- mkPcieControlAndStatusRegs(traceif[tlpCompleterRequest].tlpdata);
     mkConnection(mvec[portConfig].master, csr.memSlave);
  
     interface msixEntry = csr.msixEntry;
     interface master = mvec[portPortal].master;
     interface slave = slavearr;
     interface interruptRequest = intr.interruptRequest;
     interface pcic = traceif[tlpCompleterRequest].pci;
     interface pcir = traceif[tlpRequesterRequest].pci;
  endmodule: mkPcieHost
  `else //NOT PCIE3
  // ======================================================
  // PCIE GEN1 and GEN2 PcieHost
  //(* synthesize *) commented out so that the guards in MemServer aren't destroyed (mdk)
  module  mkPcieHost#(PciId my_pciId)(PcieHost#(DataBusWidth, NumberOfMasters));
     let dispatcher <- mkTLPDispatcher;
  