anchor.diff:  endmodule
   
   
  -module mkBramReaderPipe#(BRAMServer#(Bit#(addrsz), Bit#(dsz)) bramServer,
  +module mkBramReaderPipe#(BRAMServer#(Bit#(addrsz), dataType) bramServer,
   			 IteratorIfc#(Bit#(addrsz)) addrIterator)(PipeOut#(MemData#(dsz)))
  -   provisos (Add#(a__, addrsz, MemOffsetSize));
  +   provisos (Add#(a__, addrsz, MemOffsetSize),
  +	     Bits#(dataType,dsz));
   
      FIFOF#(Bool) lastFifo <- mkFIFOF();
      FIFOF#(MemData#(dsz)) readDataFifo <- mkFIFOF();
  
positive.code: 
     rule issueBramReadRequest;
        let addr <- toGet(addrIterator.pipe).get();
        bramServer.request.put(BRAMRequest{write: False, responseOnWrite: False, address: addr, datain: 0});
        lastFifo.enq(addrIterator.isLast());
        if (verbose) $display("issueBramReadRequest addr=%h first=%d last=%d", addr, addrIterator.isFirst(), addrIterator.isLast());
     endrule
  
negative.code:    rule readData;
        let v <- bramServer.response.get();
        let last <- toGet(lastFifo).get();
        readDataFifo.enq(MemData { data: pack(v), last: last, tag: 0 });
     endrule
     return toPipeOut(readDataFifo);
  endmodule
  