anchor.diff:     Reg#(Bit#(asz)) addrReg <- mkReg(0, clocked_by tck, reset_by rst);
      Reg#(Bool) capture_delay <- mkReg(False, clocked_by tck, reset_by rst);
      Reg#(Bool) selected_delay <- mkReg(False, clocked_by tck, reset_by rst);
  +   Wire#(Bit#(1)) tdow <- mkDWire(0, clocked_by tck, reset_by rst);
  +   rule tdo;
  +      bscan.tdo(tdow);
  +   endrule
   
      rule selected_rule;
          selected_delay <= bscan.sel() == 1;
  
positive.code: 	  let d = fromMaybe(unpack(0), m);
  	  shift = pack(d);
         end
         bscan.tdo(shift[0]);
         let v = (shift >> 1);
         v[dsz-1] = bscan.tdi();
         shiftReg <= v;
  
negative.code:    Reg#(Bit#(width)) shiftReg <- mkReg(0, clocked_by tck, reset_by rst);
     SyncFIFOIfc#(Bit#(width)) infifo <- mkSyncFIFO(2, defaultClock, defaultReset, tck);
     SyncFIFOIfc#(Bit#(width)) outfifo <- mkSyncFIFO(2, tck, rst, defaultClock);
     Wire#(Bit#(1)) tdow <- mkDWire(0, clocked_by tck, reset_by rst);
     rule tdo;
        bscan.tdo(tdow);
     endrule
  
     rule captureRule if (bscan.capture() == 1 && bscan.sel() == 1);
        if (infifo.notEmpty()) begin
  	 infifo.deq();
        end
        //else
        //shiftReg <= 0;
     endrule
     rule shift if (bscan.shift() == 1 && bscan.sel() == 1);
        tdow <= shiftReg[0];
        let v = (shiftReg >> 1);
        v[width-1] = bscan.tdi();
        shiftReg <= v;
  