anchor.diff:  endfunction
   endinstance
   
  -instance ToAxi4MasterBits#(Axi4MasterBits#(32,32,tagWidth,Empty), AxidmabviM_axi_sg);
  -function Axi4MasterBits#(32,32,tagWidth,Empty) toAxi4MasterBits(AxidmabviM_axi_sg m);
  -   return (interface Axi4MasterBits#(32,32,tagWidth,Empty);
  +instance ToAxi4MasterBits#(Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty), AxidmabviM_axi_sg);
  +function Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty) toAxi4MasterBits(AxidmabviM_axi_sg m);
  +   return (interface Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty);
       method araddr = m.araddr;
         method arburst = m.arburst;
         method arcache = m.arcache;
  
positive.code:     method Bit#(1)     bready();
      method Action      bresp(Bit#(2) v);
      method Action      bvalid(Bit#(1) v);
      method Bit#(32)     wdata();
      method Bit#(1)     wlast();
      method Action      wready(Bit#(1) v);
      method Bit#(4)     wstrb();
      method Bit#(1)     wvalid();
  endinterface
  (* always_ready, always_enabled *)
  
negative.code: import DefaultValue::*;
  import XilinxCells::*;
  import GetPut::*;
  import ConnectalConfig::*;
  import AxiBits::*;
  import AxiStream::*;
  
  