anchor.diff:     endrule
      
      rule muloutaccumin0;
  -      let m <- mul[0].y.get();
  -      if (m.filterPhase)
  +      let m = mul[0].y.first();
  +      mul[0].y.deq();
  +      if (m.filterPhase == 1)
   	 begin
   	    accum[0] <= m.y;
   	    accumout[0].enq(accum[0]);
  
positive.code:    endrule
  
     rule muloutaccumin1;
        let m <- mul[1].y.get();
        if (m.filterPhase)
  	 begin
  	    accum[1] <= m.y;
  	    accumout[1].enq(accum[1]);
  
negative.code: interface ChannelSelect;
     interface PipeIn#(Vector#(2, Complex#(Signal))) rfreq;
     interface PipeOut#(Complex#(Signal)) ifreq;
     method Action setCoeff(Bit#(11) addr, Bit#(32) valre, Bit#(32) valim);
  endinterface
  
  
  module mkChannelSelect#(Bit#(10) decimation, DDS dds)(ChannelSelect)
     provisos(Bits#(CoeffData, a__),
  	    Bits#(ProductData, b__),
  	    Bits#(MulData, c__));
     BRAM_Configure cfg = defaultValue;
     cfg.memorySize = 1024;
     BRAM2Port#(Bit#(10), Complex#(FixedPoint#(2,23))) coeffRam0 <- 
         mkBRAM2Server(cfg);
     BRAM2Port#(Bit#(10), Complex#(FixedPoint#(2,23))) coeffRam1 <- 
         mkBRAM2Server(cfg);
     Reg#(Bit#(10)) filterPhase <- mkReg(?);
     FIFO#(Bit#(1)) delayFilterPhase <- mkSizedFIFO(3);  // length > bram read latency
     FIFOF#(Vector#(2, Complex#(Signal))) infifo <- mkFIFOF();
     FIFOF#(Complex#(Signal)) outfifo <- mkFIFOF();
     Vector#(2, FPCMult) mul <- replicateM(mkFPCMult());
  
     Vector#(2, Reg#(Complex#(Product))) accum <- replicateM(mkReg(?));
  