anchor.diff:  	    let v = 0;
   	    v[8] = 1;
   	    v[9] = serdes_align_busy_reg;
  -	    v[10] = serdes_aligned_reg;
  +	    v[10] = ~serdes_aligned_reg;
   	    return v;
   	endmethod
   	method Action set_decoder_control(Bit#(32) v);
  
positive.code:     Reg#(Bit#(10)) edge_init <- mkReg(0);
      Reg#(Bit#(10)) edge_int <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      SyncFIFOIfc#(Bit#(1)) serdes_setting <- mkSyncFIFO(2, defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
      Wire#(Bit#(1)) this_align_busy_wire <- mkDWire(0);
      Reg#(Bit#(16)) top_align_counter <- mkReg(0);
      Reg#(QState)  qstate <- mkReg(QIdle);
      Reg#(AState)  astate <- mkReg(AIdle);
  
negative.code:         bvi_resets_reg.send(bvi_reset_reg);
      endrule
  
      rule serdesreset_rule if (bvi_reset_reg == 0);
          sync_bitslip <= 0;
          sync_reset_inc_ce <= 0;
          serdes_running <= 0;
          dfifo.clear();
      endrule
      rule wrensync_rule if (bvi_reset_reg != 0);
          fifo_reset <= fifo_reset_sync.read();
  