anchor.diff:     interface Reg#(Bool) byteSwap;
      interface Reg#(Bool) use4dw;
      interface Reg#(Bit#(4)) numPortals;
  -   interface Reg#(Bit#(32)) axiTestEnabled;
  -   interface Reg#(Bit#(32)) addrLowerWord;
  -   interface Reg#(Bit#(32)) addrUpperWord;
  -   interface Reg#(Bit#(32)) testResult;
  -   interface Reg#(Bit#(32)) testState;
      interface Reg#(Bit#(32)) tlpDataBramWrAddr;
      interface Reg#(Bit#(32)) tlpSeqno;
      interface Reg#(Bit#(32)) tlpOutCount;
  
positive.code: 	 779: return tlpDataBramResponseSlice(3);
  	 780: return tlpDataBramResponseSlice(4);
  	 781: return tlpDataBramResponseSlice(5);
  	 782: return axiTestEnabledReg;
  	 783: return addrLowerWordReg;
  	 784: return addrUpperWordReg;
  	 785: return testResultReg;
  	 786: return testStateReg;
  	 787: return pipeliningEnabledReg ? 1 : 0;
  	 788: return axiEnabledReg ? 1 : 0;
  	 789: return tlpDataBramRdAddrReg;
  
negative.code:    Reg#(Bool) byteSwapReg <- mkReg(False);
     Reg#(Bool) use4dwReg <- mkReg(True);
     Reg#(Bit#(4)) numPortalsReg <- mkReg(1);
     Reg#(Bit#(32)) tlpSeqnoReg <- mkReg(0);
     Reg#(Bit#(32)) tlpDataBramRdAddrReg <- mkReg(0);
     Reg#(Bit#(32)) tlpDataBramWrAddrReg <- mkReg(0);
  