anchor.diff:          return dfifo.dataout()[9:0];
       endmethod
   endmodule: mkIserdesDatadeser
  + 
   (* always_enabled *)
   interface ImageonSerdesPins;
  
positive.code:         return serbvi.samplein()[0];
      endmethod
      method Action                 delay_wren(Bit#(1) v);
          serbvi.delay_wren(v);
      endmethod
      method Action                 fifo_wren(Bit#(1) v);
          serbvi.fifo_wren(v);
      endmethod
      method Action                 reset(Bit#(1) v);
          serbvi.reset(v);
      endmethod
      method Bit#(1)                empty();
  
negative.code:         srval_q1: 0, srval_q2: 0, srval_q3: 0, srval_q4: 0,
          serdes_mode: "SLAVE", iobdelay: "NONE"},
          serdest, serdest_inverted.slowClock, clocked_by serdes_clock);
      Reg#(Bit#(1)) bvi_delay_wren_wire <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) bvi_reset_reg <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
  //
      Reg#(Bit#(3)) ctrl_ric <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) ctrl_fifo_reset <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ctrl_SAMPLEIN <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) tempfifo_wren <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) iserdes_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) ctrl_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  //
      Reg#(Bit#(1)) itemreq <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe0 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe1 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_ric <- mkReg(3'b100, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_wren_sync <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_reset_r <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dackint <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ireset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) sync_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
          let ds = dstate;
          let dc = dcounter;
          let da = dackint;
          let fwsync = 0;
    
          dc = dc - 1;
          dreqpipe0 <= itemreq;
          dreqpipe1 <= dreqpipe0;
          dfifo_reset_r <= ctrl_fifo_reset;
          fifo_reset <= dfifo_reset_r;
          dfifo_wren_r <= tempfifo_wren;
          if (bvi_delay_wren_wire == 1 && ctrl_SAMPLEIN[2] == 1)
              fwsync = dfifo_wren_r;
          else
              fwsync = tempfifo_wren;
          ireset_inc_ce <= sync_ric;
          iserdes_bitslip <= sync_bitslip;
          sync_data <= iserdes_data;
          if (dstate == DIdle && dreqpipe1 == 1)
              begin
              sync_ric <= ctrl_ric;
              sync_bitslip <= ctrl_bitslip;
              dc = 3'b011;
              ds = DLow;
              end
          if (dstate == DValid && dcounter >= 3'b100)
              begin
              da = 1;
              ds = DLow;
              end
          if (dstate == DLow && dreqpipe1 == 0)
              begin
              da = 0;
              ds = DIdle;
              end
          dstate <= ds;
          dcounter <= dc;
          dackint <= da;
          fifo_wren_sync <= fwsync;
      endrule
  
      rule setrule;
          dfifo.reset(serbvi.iodelay_reset_inc_ce()[2]);
  