anchor.diff:  		      endinterface);
   
      let splitter <- mkSplitMemServer();
  +   BRAM_Configure bramConfig = defaultValue;
  +   bramConfig.latency = 2;
  +   bramConfig.memorySize = 1024;
  +   BRAM1Port#(Bit#(32),Bit#(DataBusWidth)) bram        <- mkBRAM1Server(bramConfig);
  +   MemServer#(DataBusWidth) bramMem     <- mkMemToBram(bram.portA);
      let traceMemCnx <- mkConnection(traceClient, splitter.server);
  +   let bramMemCnx  <- mkConnection(splitter.bramClient, bramMem);
      rule rl_data;
         let md <- toGet(splitter.data).get();
         trace.traceData(md.data, md.last, extend(md.tag));
  
positive.code: 
     FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo <- mkSizedBRAMFIFOF(128);
     PipeIn#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) tracePipe = toPipeIn(traceFifo);
     FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo <- mkSizedBRAMFIFOF(512);
     PipeIn#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataPipe = toPipeIn(traceDataFifo);
     rule rl_trace1;
        match { .chan, .write, .req, .timestamp } <- toGet(traceFifo).get();
  
negative.code: import Connectable::*;
  import FIFOF::*;
  import GetPut::*;
  import Probe::*;
  import Vector::*;
  
  import AddressGenerator::*;
  