anchor.diff:  		      endseq;
      FSM trafficFSM <- mkFSM(trafficStmt);
         
  -   FIFO#(DmaError) dmaErrorFifo <- mkFIFO();
  -   rule dmaError;
  -      let error <- toGet(dmaErrorFifo).get();
  -      dmaIndication.error(extend(pack(error.errorType)), error.pref, 0, 0);
  -   endrule
  -
      interface DmaDebugRequest request;
         method Action getStateDbg(ChannelType rc);
   	 if (rc == Read)
  
positive.code: 		      endseq;
     FSM trafficFSM <- mkFSM(trafficStmt);
  
     FIFO#(DmaError) dmaErrorFifo <- mkFIFO();
     rule dmaError;
        let error <- toGet(dmaErrorFifo).get();
        dmaIndication.error(extend(pack(error.errorType)), error.pref, 0, 0);
     endrule
  
     interface DmaDebugRequest request;
        method Action getStateDbg(ChannelType rc);
  	 if (rc == Write)
  
negative.code:    MemServer#(PhysAddrWidth,dataWidth,nMasters) reader <- mkMemServerR(dmaIndication,  readClients, mmus);
     MemServer#(PhysAddrWidth,dataWidth,nMasters) writer <- mkMemServerW(dmaIndication, writeClients, mmus);
     
     function PhysMemMaster#(PhysAddrWidth,dataWidth) mkm(Integer i) = (interface PhysMemMaster#(PhysAddrWidth,dataWidth);
  								 interface PhysMemReadClient read_client = reader.masters[i].read_client;
  								 interface PhysMemWriteClient write_client = writer.masters[i].write_client;
  