anchor.diff:  	    788: axiEnabledReg <= (dword != 0) ? True : False;
   	    789: tlpDataBramRdAddrReg <= dword;
   	    792: tlpDataBramWrAddrReg <= dword;
  +	    794: byteSwapReg <= (dword != 0) ? True : False;
   
               // MSIx table entries
               4096: msix_entry[0].addr_lo  <= update_dword(msix_entry[0].addr_lo, be, (dword & 32'hfffffffc));
  
positive.code: 	endinterface: read
      endinterface: portal
      interface Reg pipeliningEnabled = pipeliningEnabledReg;
  endmodule: mkPortalEngine
  
  interface AxiSlaveEngine;
  
negative.code: 		completion.bytecount = 4;
  		completion.reqid = hdr.reqid;
  		completion.loweraddr = getLowerAddr(hdr.addr, hdr.firstbe);
  		if (byteSwapReg)
  		    completion.data = byteSwap(data);
  		else
  		    completion.data = data;
  	        TLPData#(16) tlp = defaultValue;
  		tlp.data = pack(completion);
  		tlp.sof = True;
  