anchor.diff:        method Bit#(1) last();
   	 return inputs[rs].read.last;
         endmethod
  -      method Bit#(12) rid();
  +      method Bit#(idWidth) rid();
            return inputs[rs].read.rid;
         endmethod
         method ActionValue#(Bit#(busWidth)) readData();
  
positive.code: 
  module mkClientSlaveConnection#(Axi3WriteClient#(addrWidth, busWidth, busWidthBytes,idWidth) axicw,
                                  Axi3ReadClient#(addrWidth, busWidth,idWidth) axicr,
                                  Axi3Slave#(addrWidth, busWidth, busWidthBytes) axiSlave)
                                  () provisos (Div#(busWidth, 8, busWidthBytes),
  				             Add#(1, a__, busWidth),
  					     Add#(busWidth, b__, 65),
  
negative.code: endmodule
  
  module mkAxi3SlaveFromRegFile#(RegFile#(Bit#(regFileBusWidth), Bit#(busWidth)) rf)
                                (Axi3Slave#(addrWidth, busWidth, busWidthBytes, idWidth))
                                provisos(Div#(busWidth,8,busWidthBytes),
                                         Add#(nz, regFileBusWidth, addrWidth));
      Reg#(Bit#(regFileBusWidth)) readAddrReg <- mkReg(0);
      Reg#(Bit#(regFileBusWidth)) writeAddrReg <- mkReg(0);
      Reg#(Bit#(idWidth)) readIdReg <- mkReg(0);
      Reg#(Bit#(idWidth)) writeIdReg <- mkReg(0);
      Reg#(Bit#(4)) readBurstCountReg <- mkReg(0);
      Reg#(Bit#(4)) writeBurstCountReg <- mkReg(0);
      FIFO#(Bit#(2)) writeRespFifo <- mkFIFO();
      FIFO#(Bit#(idWidth)) writeIdFifo <- mkFIFO();
  
      Bool verbose = False;
      interface Axi3SlaveRead read;
          method Action readAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
                                 Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(idWidth) id) if (readBurstCountReg == 0);
              if (verbose) $display("axiSlave.read.readAddr %h bc %d", addr, burstLen+1);
              readAddrReg <= truncate(addr/fromInteger(valueOf(busWidthBytes)));
  	    readIdReg <= id;
  