anchor.diff:     
      (* fire_when_enabled, no_implicit_conditions *)
      rule drive_axi_rx_ready;
  -      pcie_ep.axi_rx.rready(fAxiRx.notFull);
  +      pcie_ep.m_axis_rx.tready(pack(fAxiRx.notFull));
      endrule
      
      (* fire_when_enabled *)
  -   rule sink_axi_rx if (pcie_ep.axi_rx.rvalid);
  +   rule sink_axi_rx if (pcie_ep.m_axis_rx.tvalid != 0);
         let info = AxiRx {
  -	 user:    pcie_ep.axi_rx.ruser,
  -	 last:    pcie_ep.axi_rx.rlast,
  -	 keep:    pcie_ep.axi_rx.rkeep,
  -	 data:    pcie_ep.axi_rx.rdata
  +	 user:    pcie_ep.m_axis_rx.tuser,
  +	 last:    pcie_ep.m_axis_rx.tlast != 0,
  +	 keep:    pcie_ep.m_axis_rx.tkeep,
  +	 data:    pcie_ep.m_axis_rx.tdata
   	 };
         fAxiRx.enq(info);
      endrule
  
positive.code:       
     schedule (user_lnk_up, user_app_rdy, fc_ph, fc_pd, fc_nph, fc_npd, fc_cplh, fc_cpld, fc_sel, s_axis_tx_tlast,
  	     s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tvalid, s_axis_tx_tready, s_axis_tx_tuser, axi_tx_tbuf_av, axi_tx_terr_drop,
  	     axi_tx_tcfg_req, axi_tx_tcfg_gnt, axi_rx_rlast, axi_rx_rdata, axi_rx_rkeep, axi_rx_ruser, axi_rx_rvalid,
  	     axi_rx_rready, rx_np_ok, rx_np_req, pl_initial_link_width, pl_phy_link_up, pl_lane_reversal_mode,
  	     pl_link_gen2_capable, pl_link_partner_gen2_supported, pl_link_upcfg_capable, pl_sel_link_rate, pl_sel_link_width,
  	     pl_ltssm_state, pl_rx_pm_state, pl_tx_pm_state, pl_directed_link_auton, pl_directed_link_change, 
  	     pl_directed_link_speed, pl_directed_link_width, pl_directed_change_done, pl_upstream_prefer_deemph, 
  
negative.code: 	     ) CF 
              (user_lnk_up, user_app_rdy, fc_ph, fc_pd, fc_nph, fc_npd, fc_cplh, fc_cpld, fc_sel, s_axis_tx_tlast,
  	     s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tvalid, s_axis_tx_tready, s_axis_tx_tuser, axi_tx_tbuf_av, axi_tx_terr_drop,
  	     axi_tx_tcfg_req, axi_tx_tcfg_gnt, m_axis_rx_tlast, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tuser, m_axis_rx_tvalid,
  	     m_axis_rx_tready, rx_np_ok, rx_np_req, pl_initial_link_width, pl_phy_link_up, pl_lane_reversal_mode,
  	     pl_link_gen2_capable, pl_link_partner_gen2_supported, pl_link_upcfg_capable, pl_sel_link_rate, pl_sel_link_width,
  	     pl_ltssm_state, pl_rx_pm_state, pl_tx_pm_state, pl_directed_link_auton, pl_directed_link_change, 
  	     pl_directed_link_speed, pl_directed_link_width, pl_directed_change_done, pl_upstream_prefer_deemph, 
  