anchor.diff:  import MemTypes::*;
   import Platform::*;
   import ZYNQ_ULTRA::*;
  +import Probe::*;
   
   (* always_ready, always_enabled *)
   interface Bidir#(numeric type data_width);
  
positive.code: 	 method rresp = s.rresp;
  	 method rvalid = s.rvalid;
  	 method wdata = s.wdata;
  	 method wlast = s.wlast;
  	 method wready = s.wready;
  	 method wvalid = s.wvalid;
  	 method wstrb = s.wstrb;
  	 endinterface);
     endfunction
  endinstance
  
  //FIXME extra aruser awuser
  instance MkPhysMemSlave#(Axi4SlaveBits#(49,128,6,Empty),addrWidth,DataBusWidth)
        provisos (Add#(addrWidth,a__,49));
     module mkPhysMemSlave#(Axi4SlaveBits#(49,128,6,Empty) axiSlave)(PhysMemSlave#(addrWidth,DataBusWidth));
        FIFOF#(PhysMemRequest#(addrWidth,DataBusWidth)) arfifo <- mkAxiFifoF();
        FIFOF#(MemData#(DataBusWidth)) rfifo <- mkAxiFifoF();
        FIFOF#(PhysMemRequest#(addrWidth,DataBusWidth)) awfifo <- mkAxiFifoF();
        FIFOF#(MemData#(DataBusWidth)) wfifo <- mkAxiFifoF();
        FIFOF#(Bit#(MemTagSize)) bfifo <- mkAxiFifoF();
        FIFOF#(Bit#(MemTagSize)) rtagfifo <- mkAxiFifoF();
        FIFOF#(Bit#(MemTagSize)) wtagfifo <- mkAxiFifoF();
  
        rule rl_arvalid_araddr;
  	 axiSlave.arvalid(pack(arfifo.notEmpty && rtagfifo.notFull));
        endrule
        rule rl_arfifo if (axiSlave.arready() == 1);
  	 let req <- toGet(arfifo).get();
  
negative.code:    endfunction: toAxi4MasterBits
  endinstance
  
  instance ToAxi4SlaveBits#(Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra), Ps8Saxigp);
     function Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra) toAxi4SlaveBits(Ps8Saxigp s);
        return (interface Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra);
  	 method araddr = s.araddr;
  	 method arburst = s.arburst;
  	 method arcache = s.arcache;
  	 //method aresetn = 1; //no aresetn port in zcu
  	 method arid = s.arid;
  	 method arlen = s.arlen;
  	 method arlock = compose(s.arlock, truncate);
  