anchor.diff:     let verbose = True;
   
         rule updateReqHeadTail if (reqState == Idle && readyReg);
  -	 readEngine.readServers[0].request.put(MemengineCmd { sglId: sglIdReg,
  -							     base: 0,
  -							     burstLen: 16,
  -							     len: 16
  -							     });
  +	 readEngine.cmdServer.request.put(MemengineCmd { sglId: sglIdReg,
  +							base: 0,
  +							burstLen: 16,
  +							len: 16
  +							});
   	 reqState <= HeadRequested;
         endrule
   
         rule receiveReqHeadTail if (reqState == HeadRequested || reqState == TailRequested);
  -	 let data <- toGet(readEngine.dataPipes[0]).get();
  +	 let data <- toGet(readEngine.dataPipe).get();
   	 let w0 = data[31:0];
   	 let w1 = data[63:32];
   	 let head = reqHeadReg;
  
positive.code: 
  	 reqTailReg <= tail;
  	 wordCountReg <= truncate(wordCount);
  	 readEngine.readServers[0].request.put(MemengineCmd {sglId: sglIdReg,
  							     base: extend(reqTailReg << 2),
  							     burstLen: 16,
  							     len: wordCount << 2
  							     });
  	 reqState <= MessageHeaderRequested;
        endrule
  
        MIFO#(4,1,4,Bit#(32)) readMifo <- mkMIFO();
        rule demuxwords if (readMifo.enqReady());
  	 let data <- toGet(readEngine.dataPipes[0]).get();
  	 Vector#(2,Bit#(32)) dvec = unpack(data);
  	 let enqCount = 2;
  	 Vector#(4,Bit#(32)) dvec4;
  
negative.code:    } SharedMemoryPortalState deriving (Bits,Eq);
  
  module mkSharedMemoryRequestPortal#(PipePortal#(numRequests, numIndications, 32) portal,
  				    MemreadServer#(64) readEngine,
  				    MemwriteServer#(64) writeEngine,
  				    Reg#(Bit#(32)) sglIdReg,
  				    Reg#(Bool)     readyReg)(SharedMemoryPortal#(64));
        // read the head and tail pointers, if they are different, then read a request
  