anchor.diff:  	       if (writeHeaderFifo.notFull())
   		  writeHeaderFifo.enq(hdr_3dw);
   	    end
  -            timerReg <= truncate(32'hFFFFFFFF);
   	endmethod
       endinterface
       interface Get request = toGet(tlpOutFifo);
  
positive.code: 	 tlpOutFifo.enq(tlp);
        end
     endrule
     rule txnTimer if (timerReg > 0);
        timerReg <= timerReg - 1;
     endrule
  
      interface Client        tlp;
      interface Put response;
  
negative.code: (* synthesize *)
  module mkMemMasterEngine#(PciId my_id)(MemMasterEngine);
      Reg#(Bit#(7)) hitReg <- mkReg(0);
      FIFOF#(TLPMemoryIO3DWHeader) readHeaderFifo <- mkSizedFIFOF(8);
      FIFOF#(TLPMemoryIO3DWHeader) readDataFifo <- mkSizedFIFOF(8);
      FIFOF#(TLPMemoryIO3DWHeader) writeHeaderFifo <- mkSizedFIFOF(8);
  