anchor.diff:      Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       Wire#(Bit#(1)) bvi_fifo_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  +    Reg#(Bit#(10)) iserdes_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) dreqpipe0 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) dreqpipe1 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) dfifo_reset_r <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  -    Reg#(Bit#(1)) fifo_wren_sync <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  +    Reg#(Bit#(1)) fifo_wren_sync <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
       Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  +    Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       //outputs
       Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) dackint <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  -    //Reg#(Bit#(3)) ireset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  +    Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       ReadOnly#(Bit#(3)) samplein_null <- mkNullCrossingWire(serdes_clock, serbvi.samplein());
   
       rule clkdiv_rule if (bvi_reset_reg != 0);
           let ds = dstate;
           let dc = dcounter;
           let da = dackint;
  +        let sric = sync_reset_inc_ce;
  +        let sbs = 0;
           let fwsync = 0;
     
           dc = dc - 1;
  
positive.code:     method CTRL_BITSLIP_o   ctrl_bitslip() clocked_by(clkdiv);
      method CTRL_FIFO_RESET_o   ctrl_fifo_reset() clocked_by(clkdiv);
      method CTRL_RESET_INC_CE_o ctrl_reset_inc_ce() clocked_by(clkdiv);
      method                  sync_reset_inc_ce(SYNC_RESET_INC_CE_i) enable((*inhigh*) en33) clocked_by(clkdiv);
      schedule (sync_reset_inc_ce, ctrl_reset_inc_ce, itemreq, ctrl_bitslip, ctrl_fifo_reset, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
           CF (sync_reset_inc_ce, ctrl_reset_inc_ce, itemreq, ctrl_bitslip, ctrl_fifo_reset, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  
negative.code:         slave_data.oclk(0);
          slave_data.oclkb(0);
          slave_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
          //slave_data.reset(iodelay_reset_inc_ce[2]);
          iserdes_data <= dout;
          serbvi.dataout(dout);
          dfifo.di({6'b0,dout});
      endrule
      //rule bozodata_rule;
          //serbvi.dataout(iserdes_data);
      //endrule
  
      rule wren_dfifo_rule;
          dfifo.wren(serbvi.fifo_wren_sync());
          //dfifo.wren(fifo_wren_sync);
      endrule
  
      rule serdesrule;
  