anchor.diff:        Bool stageF_full = (stageF.out.ostatus != OSTATUS_EMPTY);
   
         // ----------------
  +      // Signal from Stage1 back to StageF. Valid (e, pc1, pc2) says:
  +      //  - pc1 was followed by pc2, and was mis-predicted to something other than pc2.
  +      //        (so StageF must be fetching from the wrong pc)
  +      //  - re-start fetching from pc2, with new epoch e.
  +
  +      Maybe #(Tuple3 #(Epoch, WordXL, WordXL)) redirect = Invalid;
  +
  +      // ----------------
         // Stage3 sink (does regfile writebacks)
   
         if (stage3.out.ostatus == OSTATUS_PIPE) begin
  
positive.code:    CPU_StageD_IFC  stageD <- mkCPU_StageD (cur_verbosity, misa);
  
     CPU_StageF_IFC  stageF <- mkCPU_StageF (cur_verbosity, imem);
  
     // ----------------
     // FIFO from Stage1 back to StageF.  Each (e, pc1, pc2) says:
     //  - pc1 was followed by pc2, and was mis-predicted to something other than pc2.
     //        (so StageF must be fetching from the wrong pc)
     //  - re-start fetching from pc2, with new epoch e.
  
     FIFOF #(Tuple3 #(Epoch, WordXL, WordXL)) f_redirects <- mkFIFOF;
  
     // ----------------
     // Interrupt pending based on current priv, mstatus.ie, mie and mip registers
  
negative.code: 	    Maybe #(WordXL)  m_old_pc = tagged Invalid;
  
  	    // Override, if stage1 is redirecting
  	    if (redirect matches tagged Valid { .e, .pc1, .pc2 }) begin
  	       epoch   = e;
  	       next_pc = pc2;
  	       m_old_pc = tagged Valid pc1;
  