anchor.diff:  instance AxiToMemReadClient#(Bit#(32),32,dataWidth);
      module mkMemReadClient#(Bit#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemReadClient#(dataWidth));
   
  -      Wire#(Bit#(1)) arready <- mkDWire(0);
  -      Wire#(Bit#(1)) rvalid <- mkDWire(0);
  -      Wire#(Bit#(MemTagSize)) rid <- mkDWire(0);
  -      Wire#(Bit#(2)) rresp <- mkDWire(0);
  -      Wire#(Bit#(dataWidth)) rdata <- mkDWire(0);
  -      Wire#(Bit#(1)) rlast <- mkDWire(0);
  -
  -      FIFOF#(MemRequest)          arfifo <- mkCFFIFOF();
  -      FIFOF#(MemData#(dataWidth))  rfifo <- mkCFFIFOF();
  +      let clock <- exposeCurrentClock();
  +      let mClock = clockOf(m);
  +      let reset <- exposeCurrentReset();
  +      let mReset = resetOf(m);
  +
  +      Wire#(Bit#(1)) arready <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(1)) rvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(MemTagSize)) rid <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(2)) rresp <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(dataWidth)) rdata <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +      Wire#(Bit#(1)) rlast <- mkDWire(0, clocked_by mClock, reset_by mReset);
  +
  +      FIFOF#(MemRequest)          arfifo;
  +      FIFOF#(MemData#(dataWidth))  rfifo;
  +      if ( isAncestor(clock, mClock)) begin
  +	 arfifo <- mkCFFIFOF();
  +	 rfifo  <- mkCFFIFOF();
  +      end
  +      else begin
  +	 arfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);
  +	 rfifo  <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);
  +      end
   
         rule rl_araddr if (m.arvalid() == 1);
   	 let addr = m.araddr();   
  
positive.code:       endrule
        rule rl_arfifo if (axiSlave.arready() == 1);
  	 let req <- toGet(arfifo).get();
  	 rtagfifo.enq(req.tag);
        endrule
        rule rl_rready;
  
negative.code: 
     module mkMemWriteClient#(Bit#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));
  
        let clock <- exposeCurrentClock();
        let mClock = clockOf(m);
        let reset <- exposeCurrentReset();
        let mReset = resetOf(m);
  
        Wire#(Bit#(1)) awready <- mkDWire(0, clocked_by mClock, reset_by mReset);
        Wire#(Bit#(1)) wready <- mkDWire(0, clocked_by mClock, reset_by mReset);
        Wire#(Bit#(1)) bvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);
        Wire#(Bit#(MemTagSize)) bid <- mkDWire(0, clocked_by mClock, reset_by mReset);
        Wire#(Bit#(2)) bresp <- mkDWire(0, clocked_by mClock, reset_by mReset);
  
        FIFOF#(MemRequest)       awfifo;
        FIFOF#(MemData#(dataWidth)) wfifo;
        FIFOF#(Bit#(MemTagSize))    bfifo;
        if ( isAncestor(clock, mClock)) begin
  	 awfifo   <- mkCFFIFOF();
  	 wfifo <- mkCFFIFOF();
  	 bfifo <- mkCFFIFOF();
        end
        else begin
  	 awfifo   <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);
  	 wfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);
  	 bfifo <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);
        end
  
        rule rl_awaddr if (m.awvalid() == 1);
  	 let addr = m.awaddr();
  