anchor.diff:     let ip <- mkInnerProdSynth(derivedClock);
      rule indRule;
         match { .t, .v } <- ip.response.get();
  -      $display("indRule v=%x %h", t, v);
  +      $display("indRule tile=%d v=%h", t, v);
         ind.innerProd(pack(t), pack(v));
      endrule
   
  
positive.code:    Reg#(Bool)        validReg       <- mkReg(False, reset_by ipReset);
  
     rule request_rule;
        let req <- toGet(reqFifo).get();
  
        let addr = addrReg + 1;
        if (req.update && req.tile == tile) begin
  	 $display("tile %d: writing kernel addr=%d value=%d", tile, addrReg, req.v);
  	 kernelBram.portA.request.put(BRAMRequest {write:True, responseOnWrite:False, address: addrReg, datain: req.v});
        end
        else if (req.tile == tile || req.tile == fromInteger(valueOf(NumTiles))) begin
  	 kernelBram.portA.request.put(BRAMRequest {write:False, responseOnWrite:False, address: addrReg, datain: 0});
  	 req1Fifo.enq(req);
        end
        if (req.last)
  	 addr = 0;
        addrReg <= addr;
     endrule
  
     rule process_rule;
        let req <- toGet(req1Fifo).get();
        let b <- kernelBram.portA.response.get();
        $display("tile %d: inner prod a=%h b=%h", tile, req.v, b);
  
        dsp.a(extend(pack(req.v)));
        dsp.b(extend(pack(b)));
  
negative.code:    endrule
  
     rule responseRule;
        InnerProdResponse v = unpack(0);
        let valid = False;
        if (dsp.notEmpty()) begin
  	 $display("InnerProdTile tile=%d dsp.p %h", tile, dsp.p());
  	 Int#(16) uintTile = extend(unpack(tile));
  	 v = tuple2(uintTile, unpack(dsp.p()[23:8]));
  	 valid = True;
        end
        else if (nextRespFifo.notEmpty()) begin
  	 v <- toGet(nextRespFifo).get();
  	 $display("tile %d: nextResp tile=%d", tile, tpl_1(v));
  	 valid = True;
        end
        if (valid)
  