anchor.diff:  import AxiMasterSlave    :: *;
   import AxiDma            :: *;
   
  +`ifdef USES_FCLK1
  +`define CLOCK_DECL Clock clk1
  +`define CLOCK_ARG  ps7.fclkclk[1],
  +`else
  +`define CLOCK_DECL
  +`define CLOCK_ARG
  +`endif
  +
  +`ifndef NumberOfMasters
  +`define NumberOfMasters 1
  +`endif
  +`ifndef PinType
  +`define PinType Empty
  +`endif
  +
  +typedef `PinType PinType;
  +typedef `NumberOfMasters NumberOfMasters;
   
   interface I2C_Pins;
      interface Inout#(Bit#(1)) scl;
  
positive.code: endinterface
  
  (* always_ready, always_enabled *)
  interface ZynqTop#(type pins);
     (* prefix="" *)
     interface ZynqPins zynq;
     (* prefix="GPIO" *)
  
negative.code:    interface I2C_Pins         i2c1;
  `endif
     (* prefix="" *)
     interface PinType          pins;
     interface Vector#(4, Clock) deleteme_unused_clock;
     interface Vector#(4, Reset) deleteme_unused_reset;
  endinterface
  
  typedef (function Module#(PortalTop#(32, 64, PinType, NumberOfMasters)) mkpt(`CLOCK_DECL)) MkPortalTop;
  
  module [Module] mkZynqTopFromPortal#(MkPortalTop constructor)(ZynqTop);
     PS7 ps7 <- mkPS7();
     Clock mainclock = ps7.fclkclk[0];
     Reset mainreset = ps7.fclkreset[0];
  