anchor.diff:  	    let addr = req.addr;
   	    let awid = req.tag;
   	    let writeIs3dw = False;
  -
  +	    let use3dw = True;
  +`ifdef PCIE3
  +	    use3dw = False;
  +`endif
   	    TLPLength tlplen = fromInteger(valueOf(busWidthWords))*extend(burstLen);
   	    TLPData#(16) tlp = defaultValue;
   	    tlp.sof = True;
  
positive.code:       let dataInSecondTlp = quadWordAligned;
  `endif
        if (!tlp.sof) begin
  	 vec = reverse(tlpvec);
  	 // The MIMO implicit guard only checks for space to enqueue 1 element
  	 // so we explicitly check for the number of elements required
  	 // otherwise elements in the queue will be overwritten.
  
negative.code:               Bit#(buswidth) v = 0;
                for (Integer i = 0; i < valueOf(busWidthWords); i = i+1) begin
  `ifdef AXI
  `ifdef PCIE3
  		 v[(i+1)*32-1:i*32] = data_v[i];
  `else
  		 v[(i+1)*32-1:i*32] = byteSwap(data_v[i]);
  `endif
  `elsif AVALON
  		 v[(i+1)*32-1:i*32] = data_v[i];
  `endif
  