anchor.diff:     rule ret_rule;
         let tag <- toGet(retFifo).get;
         //tags.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:tag, datain:False});
  -      //tags.upd(tag, False);
  -      tags[tag] <= False;
  +      //tags[tag] <= False;
  +      begin
  +	 let t = tags.r1;
  +	 t[tag] = 0;
  +	 tags.r1 <= t;
  +      end
         comp_state <= 1 | (comp_state << 1);
      endrule
   
      rule init_rule(!inited);
         //tags.portA.request.put(BRAMRequest{write:True,address:head_ptr,responseOnWrite:False,datain:False});
  -      //tags.upd(head_ptr, False);
         //Not needed: tags[head_ptr] <= False;
         head_ptr <= head_ptr+1;
         inited <= head_ptr+1==0;
  
positive.code: import Assert::*;
  import BRAM::*;
  import RegFile::*;
  
  // CONNECTAL Libraries
  import MemTypes::*;
  
negative.code:    method ActionValue#(Bit#(TLog#(numTags))) complete;
  endinterface
  
  //(* synthesize *)
  module mkTagEHR (EHR2BSV#(Bit#(numTags)));
     EHR#(2,Bit#(numTags)) ehr <- mkEHR(0);
     interface r1 = ehr[0];
     interface r2 = ehr[1];
  endmodule
  
  module mkTagGen(TagGen#(numTags))
     provisos(Log#(numTags,tsz));
     
     BRAM_Configure cfg = defaultValue;
     cfg.outFIFODepth = 1;
     //BRAM2Port#(Bit#(tsz),Bool) tags <- mkBRAM2Server(cfg);
     //Vector#(numTags, Reg#(Bool)) tags <- replicateM(mkReg(False));
     EHR2BSV#(Bit#(numTags)) tags <- mkTagEHR();
     Reg#(Bit#(tsz))        head_ptr <- mkReg(0);
     Reg#(Bit#(tsz))        tail_ptr <- mkReg(0);
     Reg#(Bool)               inited <- mkReg(False);
  