anchor.diff:  // defined by user
   import Memread::*;
   
  -interface AxiTop;
  -   interface StdAxi3Slave     ctrl;
  -   interface StdAxi3Master    m_axi;
  -   interface ReadOnly#(Bool)  interrupt;
  -   interface LEDS             leds;
  -endinterface
  -
  -module mkAxiTop(AxiTop);
  +module mkPortalDmaTop(PortalDmaTop);
   
      DMAIndicationProxy dmaIndicationProxy <- mkDMAIndicationProxy(9);
   
  
positive.code:    Reg#(Bool) interruptRequested <- mkReg(False, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // instantiate user portals
     let axiTop <- mkAxiTop(clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // connect them to PCIE
     mkConnection(x7pcie.portal0, axiTop.ctrl, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     AxiSlaveEngine#(64,8) axiSlaveEngine <- mkAxiSlaveEngine(x7pcie.pciId(), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(tpl_1(x7pcie.slave), tpl_2(axiSlaveEngine.tlps), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(tpl_1(axiSlaveEngine.tlps), tpl_2(x7pcie.slave), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(axiTop.m_axi, axiSlaveEngine.slave3, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     rule requestInterrupt;
        if (axiTop.interrupt && !interruptRequested)
  	 x7pcie.interrupt();
        interruptRequested <= axiTop.interrupt;
     endrule
  
     interface pcie = x7pcie.pcie;
  
negative.code: 
  
  module mkBsimTop();
     PortalDmaTop top <- mkPortalDmaTop;
     let wf <- mkPipelineFIFO;
     let init_seq = (action 
  		      initPortal(0);
  