anchor.diff:     interface Vector#(2,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) addr;
   endinterface
   
  -module mkSimpleMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
  +module mkSimpleMMU#(Bit#(4) mmuid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
      provisos (Add#(b__,8,addrWidth)
   	     ,Add#(c__,24,addrWidth)
   	     ,Bits#(AddrTransResponse#(addrWidth),d__)
  
positive.code:       mkConnection(toGet(dmaErrorFifos[i]), toPut(dmaErrorFifo));
     rule dmaError;
        let error <- toGet(dmaErrorFifo).get();
        mmuIndication.error(extend(pack(error.errorType)), error.pref, extend(error.off), fromInteger(iid));
     endrule
  
     let page_shift0 = fromInteger(valueOf(SGListPageShift0));
  
negative.code:    } Stage4Params deriving (Bits);
  
  // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  module mkMMU#(Bit#(4) mmuid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
     provisos(Log#(MaxNumSGLists, listIdxSize),
  	    Add#(listIdxSize,8, entryIdxSize),
  	    Add#(a__,addrWidth,MemOffsetSize));
  