anchor.diff:     interface unused_reset3 = fclk[3].r;
   endmodule
   
  -module mkImageonZynqTop(ZynqTop#(ImageonVita));
  -   let top <- mkZynqTopFromPortal(mkPortalTop);
  +module mkImageonZynqTop#(Clock io_vita_clk_out_p, Clock io_vita_clk_out_n)(ZynqTop#(ImageonVita));
  +   let top <- mkZynqTopFromPortal(io_vita_clk_out_p, io_vita_clk_out_n, mkPortalTop);
      return top;
   endmodule
  
positive.code: 
     FromPS7 fromPS7 = (interface FromPS7;
  			 interface Clock processing_system7_1_fclk_clk3 = fclk[3].c;
  			 interface Clock fmc_imageon_video_clk1 = fclk[2].c; // FIXME
  		      endinterface);
     let top <- constructor(fromPS7, clocked_by mainclock.c, reset_by mainclock.r);
     Reg#(Bit#(8)) addrReg <- mkReg(9, clocked_by mainclock.c, reset_by mainclock.r);
  
negative.code: 
  typedef (function Module#(PortalTop#(32, 64, ipins)) mkpt(FromPS7 fromPS7)) MkPortalTop#(type ipins);
  
  module [Module] mkZynqTopFromPortal#(Clock io_vita_clk_out_p, Clock io_vita_clk_out_n, MkPortalTop#(ipins) constructor)(ZynqTop#(ipins));
     Clock io_vita_clk <- XilinxCells::mkClockIBUFDS(io_vita_clk_out_p, io_vita_clk_out_n);
     // B2C converts a bit to a clock, enabling us to break the apparent cycle
     Vector#(4, B2C) fclk <- replicateM(mkB2C());
     B2C mainclock = fclk[0];
  