anchor.diff:  
      let verbose = True;
   
  -   rule updateReqWrPtrRdPtr if (state == Idle && readyReg);
  -      if (verbose) $display("updateReqWrPtrRdPtr");
  +   rule updateReqRdWrPtr if (state == Idle && readyReg);
  +      if (verbose) $display("updateReqRdWrPtr");
         readEngine[0].request.put(
             MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});
         state <= WrPtrRequested;
      endrule
   
  -   rule receiveReqWrPtrRdPtr if (state == WrPtrRequested || state == RdPtrRequested);
  +   rule receiveReqRdWrPtr if (state == WrPtrRequested || state == RdPtrRequested);
         let v <- toGet(readEngine[0].data).get();
         let w0 = v.data[31:0];
         let w1 = v.data[63:32];
  
positive.code:       end
     end
  
     rule updateIndWrPtrRdPtr if (state == Idle && readyReg);
        readEngine[0].request.put(
            MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});
        state <= WrPtrRequested;
     endrule
  
     rule receiveIndWrPtrRdPtr if (state == WrPtrRequested || state == RdPtrRequested);
        let md <- toGet(readEngine[0].data).get();
        let data = md.data;
        let w0 = data[31:0];
  
negative.code:             //state <= Idle;
        end
        if (verbose)
           $display("receiveIndRdWrPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limitReg);
     endrule
  
     rule send64bits;
  