anchor.diff:        let v <- toGet(data_in_fifo).get;
         if (v.eop) begin
            curr_state <= S0;
  -         parse_ethernet.clear;
  -         parse_ipv4.clear;
  -         parse_vlan.clear;
            if (verbose) $display(fshow(cycle) + fshow("Done with") + fshow(curr_state));
         end
      endrule
  
positive.code:                             $format(" ipv4.dstAddr=%x", ipv4.dstAddr));
        nextStateArbiter.in[2].enq(S4);
     endaction
     endseq
     endpar;
  
     FSM fsm_parse_ipv4 <- mkFSMWithPred(parse_ipv4, True);
     Once once_parse_ipv4 <- mkOnce(fsm_parse_ipv4.start);
  
     method Action init = once_parse_ipv4.start;
     method Action clear = once_parse_ipv4.clear;
     interface packetIn = toPipeIn(packet_in_fifo);
     interface unparsedIn = toPipeIn(unparsed_in_fifo);
     interface unparsedInVlan0 = toPipeIn(unparsed_in_vlan0_fifo);
  
negative.code:    FIFOF#(Bit#(16))  unparsed_out_parse_ipv4_fifo <- mkSizedFIFOF(1);
     FIFOF#(Bit#(16))  unparsed_out_parse_vlan_fifo <- mkSizedFIFOF(1);
     FIFOF#(ParserState) next_state_fifo <- mkBypassFIFOF;
     Wire#(Bit#(128)) packet_in_wire <- mkDWire(0);
  
     let verbose = True;
     Reg#(Cycle_t) cycle <- mkReg(defaultValue);
  