anchor.diff:     rule incTimestamp;
          timestamp <= timestamp + 1;
      endrule
  -//   rule endTrace if (csr.tlpTracing && csr.tlpTraceLimit != 0 && csr.tlpDataBramWrAddr > truncate(csr.tlpTraceLimit));
  +//   rule endTrace if (csr.tlpTracing && csr.tlpTraceLimit != 0 && csr.tlpTraceBramWrAddr > truncate(csr.tlpTraceLimit));
   //       csr.tlpTracing <= False;
   //   endrule
   
  
positive.code:        tlpToBusFifo.enq(tlp);
         if (csr.tlpTracing) begin
  	   TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 7'h08, tlp: tlp };
  	   csr.tlpDataBram.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(csr.tlpDataBramWrAddr), datain: ttd });
  	   csr.tlpDataBramWrAddr <= csr.tlpDataBramWrAddr + 1;
         end
     endrule: traceTlpToBus
  
  
negative.code:    interface Reg tlpTracing    = tlpTracingReg;
     interface Reg tlpTraceLimit = tlpTraceLimitReg;
     interface Reg use4dw = use4dwReg;
     interface Reg fromPcieTraceBramWrAddr = fromPcieTraceBramWrAddrReg;
     interface Reg   toPcieTraceBramWrAddr =   toPcieTraceBramWrAddrReg;
     interface Reg tlpOutCount = tlpOutCountReg;
     interface BRAMServer fromPcieTraceBramPort = fromPcieTraceBram.portA;
     interface BRAMServer   toPcieTraceBramPort =   toPcieTraceBram.portA;
  endmodule: mkControlAndStatusRegs
  
  // The PCIe-to-AXI bridge puts all of the elements together
  