anchor.diff:     
      BRAM_Configure cfg = defaultValue;
      cfg.outFIFODepth = 1;
  -   BRAM2Port#(Bit#(tsz),Bool) tags <- mkBRAM2Server(cfg);
  +   //BRAM2Port#(Bit#(tsz),Bool) tags <- mkBRAM2Server(cfg);
  +   Vector#(numTags, Reg#(Bool)) tags <- replicateM(mkReg(False));
  +   //RegFile#(Bit#(tsz),Bool)     tags <- mkRegFile(0, fromInteger(valueOf(numTags)-1));
      Reg#(Bool)              notFull <- mkReg(False);
      Reg#(Bit#(tsz))        head_ptr <- mkReg(0);
      Reg#(Bit#(tsz))        tail_ptr <- mkReg(0);
  
positive.code:    let retFifo <- mkFIFO;
     let tagFifo <- mkFIFO;
  
     rule complete_rule0 (comp_state[0] != 0);
        tags.portB.request.put(BRAMRequest{write:False, address:tail_ptr, datain: ?, responseOnWrite: ?});
     endrule
  
     rule complete_rule1 (comp_state[0] != 0);
        let rv <- tags.portB.response.get;
        if (!rv) begin
  	 tail_ptr <= tail_ptr+1;
  	 comp_state <= comp_state >> 1;
  
negative.code: import ClientServer::*;
  import Assert::*;
  import BRAM::*;
  import RegFile::*;
  
  // CONNECTAL Libraries
  import MemTypes::*;
  