anchor.diff:                  CSRmscycle_delta:       mscycle_delta_csr;
                   CSRmstime_delta:        mstime_delta_csr;
                   CSRmsinstret_delta:     msinstret_delta_csr;
  +                CSRmucycleh_delta:      mucycleh_delta_csr;
  +                CSRmutimeh_delta:       mutimeh_delta_csr;
  +                CSRmuinstreth_delta:    muinstreth_delta_csr;
  +                CSRmscycleh_delta:      mscycleh_delta_csr;
  +                CSRmstimeh_delta:       mstimeh_delta_csr;
  +                CSRmsinstreth_delta:    msinstreth_delta_csr;
                   default:                (readOnlyReg(64'h0));
               endcase);
       endfunction
  
positive.code: endinterface
  
  module mkRVCsrFile#(
              Data hartid,                // Compile-time constant
              Bit#(64) mtime, Bool mtip,  // From RTC
              Bool msip,                  // From IPI
              Bool meip                   // From interrupt controller
          )(RVCsrFile);
  
      let verbose = False;
      File fout = stdout;
  
      RiscVISASubset isa = defaultValue;
      Data mvendorid     = 0; // non-commercial
      Data marchid       = 0; // not implemented
      Data mimpid        = 0; // not implemented
  
negative.code:     Reg#(Data) fcsr_csr   = addWriteSideEffect(zeroExtendReg(concatReg2(frm_field, fflags_field)), fs_field._write(2'b11));
  
      // User Timers and Counters
      Bit#(64) ucycle_counter   = cycle_counter + mucycle_delta_field;
      Bit#(64) utime_counter    = time_counter + mutime_delta_field;
      Bit#(64) uinstret_counter = instret_counter + muinstret_delta_field;
  
      Reg#(Data) cycle_csr   = readOnlyReg(truncate(ucycle_counter));
      Reg#(Data) time_csr    = readOnlyReg(truncate(utime_counter));
      Reg#(Data) instret_csr = readOnlyReg(truncate(uinstret_counter));
  
      // Upper 32-bits of CSRs for RV32: (these will just be unused copies of
      // the other cycle/time/instret registers for RV64)
      Reg#(Data) cycleh_csr   = readOnlyReg(truncateLSB(ucycle_counter));
      Reg#(Data) timeh_csr    = readOnlyReg(truncateLSB(utime_counter));
      Reg#(Data) instreth_csr = readOnlyReg(truncateLSB(uinstret_counter));
  
      // Supervisor
      Reg#(Data) sstatus_csr =  concatReg20(
  