anchor.diff:  	  let d = fromMaybe(unpack(0), m);
   	  shift = pack(d);
          end
  -       tdow <= shift[0];
  -       let v = (shift >> 1);
  -       v[dsz-1] = bscan.tdi();
  -       shiftReg <= v;
  +       shiftReg <= {bscan.tdi(), shift[dsz-1:1]};
      endrule
   
      rule updateRule if (bscan.sel() == 1 && bscan.update() == 1 && bscan.capture() == 0);
  
positive.code:        addrReg <= addr;
     endrule
  
     method Bit#(4) debug;
         return {bscan.sel(), bscan.capture(), bscan.shift(), bscan.update()};
     endmethod
     interface BRAMClient bramClient;
        interface Get request;
  	 method ActionValue#(BRAMRequest#(atype,dtype)) get() if (requestWire matches tagged Valid .req);
  
negative.code: import XilinxCells::*;
  import SyncBits::*;
  
  // From: http://siliconexposed.blogspot.com/2013/10/soc-framework-part-5.html
  // Example usage: http://www.pld.ttu.ee/~vadim/tty/IAY0570/video_pipeline/psram_app/program_rom.v
  // Example usage: http://ohm.bu.edu/~dean/G-2TrackerWORKING/uart_test.vhd
  
  interface BscanBram#(type atype, type dtype);
     interface Clock jtagClock;
     interface Reset jtagReset;
     interface BRAMClient#(atype, dtype) bramClient;
  endinterface
  
  module mkBscanBram#(Integer bus, atype addr)(BscanBram#(atype, dtype))
     provisos (Bits#(atype, asz), Bits#(dtype,dsz), Add#(1, a__, dsz));
     let asz = valueOf(asz);
     let dsz = valueOf(dsz);
  
     //Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  
     BscanE2 bscan <- mkBscanE2(bus);
     Clock tck <- mkClockBUFG(clocked_by bscan.tck);
     Reset rst <- mkAsyncReset(2, defaultReset, tck);
     //SyncBitIfc#(Bit#(asz)) addr_jtag <- mkSyncBits(0, defaultClock, defaultReset, tck, rst);
     Wire#(Maybe#(BRAMRequest#(atype, dtype))) requestWire <- mkDWire(tagged Invalid, clocked_by tck, reset_by rst);
     Wire#(Maybe#(dtype)) responseWire <- mkDWire(tagged Invalid, clocked_by tck, reset_by rst);
  
  