anchor.diff:     Bit#(32) pref;
      } DmaError deriving (Bits);
   
  -module mkMemServerRW#(MemServerIndication indication,
  -		      Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
  -		      Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  -		      Vector#(numMMUs,MMU#(PhysAddrWidth)) mmus)
  +module mkMemServer#(Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
  +		    Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  +		    Vector#(numMMUs,MMU#(PhysAddrWidth)) mmus,
  +		    MemServerIndication indication)
      (MemServer#(PhysAddrWidth, dataWidth, nMasters))
      
      provisos (Max#(nMasters,numReadClients,numReadClientsActual),
  
positive.code: 	     Mul#(h__, nMasters, TMax#(nMasters, numReadClientsActual)),
  	     Mul#(i__, nMasters, TMax#(nMasters, numWriteClientsActual)),
  	     Add#(e__, TLog#(b__), 6),
  	     Add#(f__, TLog#(a__), 6)
        );
  
     Vector#(numReadClientsNull, MemReadClient#(dataWidth)) nullReadClients = replicate(null_mem_read_client());
  
negative.code: 			  Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  			  MemServerIndication indication,
  			  MMUIndication mmuIndication)(SimpleMemServer#(PhysAddrWidth, dataWidth,nMasters))
     provisos (Max#(nMasters,numReadClients,numReadClientsActual),
  	     Add#(numReadClients,numReadClientsNull,numReadClientsActual),
  	     Mul#(a__, nMasters, numReadClientsActual),
  	     Max#(nMasters,numWriteClients,numWriteClientsActual),
  	     Add#(numWriteClients,numWriteClientsNull,numWriteClientsActual),
  	     Mul#(b__, nMasters, numWriteClientsActual),
  	     Add#(1,c__,dataWidth),
  	     Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
  	     Add#(TLog#(TDiv#(dataWidth, 8)), d__, BurstLenSize),
  	     Mul#(h__, nMasters, TMax#(nMasters, numReadClientsActual)),
  	     Mul#(i__, nMasters, TMax#(nMasters, numWriteClientsActual)),
  
  	     Add#(e__, TLog#(a__), 6),
  	     Add#(f__, TLog#(b__), 6)
  
  	     );
  
     MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, mmuIndication);
  
     Vector#(numReadClientsNull, MemReadClient#(dataWidth)) nullReadClients = replicate(null_mem_read_client());
     Vector#(numWriteClientsNull, MemWriteClient#(dataWidth)) nullWriteClients = replicate(null_mem_write_client());
  
     // if this is implemented in terms of mkMemServer, then we go into loop where the compiler keeps asking for more provisos...
     MemServer#(PhysAddrWidth,dataWidth,nMasters) dma <- mkMemServerRW(indication, append(readClients,nullReadClients), append(writeClients,nullWriteClients), cons(hostMMU,nil));
  
     interface MemServerRequest memServerRequest = dma.request;
     interface MMURequest mmuRequest = hostMMU.request;
  