anchor.diff:  endinterface
   
   module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId,
  -   //MemSlave#(32,32) ptslave,
      Vector#(`NumberOfMasters,MemMaster#(40, dsz)) masters,
  -   Vector#(16,ReadOnly#(Bool)) ptinterrupt,
   Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(dsz))
   provisos(
      Mul#(TDiv#(dsz, 8), 8, dsz),
  
positive.code:    let portalTop <- mkPortalTop(clocked_by epClock125, reset_by epReset125);
     PcieHost#(dsz) pciehost <- mkPcieHost(epClock250, epReset250,
           PciId{ bus:  _ep.cfg.bus_number(), dev: _ep.cfg.device_number(), func: _ep.cfg.function_number()},
           //portalTop.slave,
           portalTop.masters,
           portalTop.interrupt,
           _ep.tlp, clocked_by epClock125, reset_by epReset125);
  
     mkConnection(pciehost.master, portalTop.slave, clocked_by epClock125, reset_by epReset125);
  
     interface pcie = _ep.pcie;
     method Bit#(NumLeds) leds();
  
negative.code:       m_axis[0] <- mkAxiDmaMaster(masters[0]);
        mkConnection(m_axis[0], dmaEngine.slave);
     end
     interface msixEntry = csr.msixEntry;
     interface master = portalEngine.master;
     interface slave = dmaEngine.slave;
  