anchor.diff:  
      
      interface MemlatencyRequest request;
  -   method Action start(Bit#(32) wp, Bit#(32) rp, Bit#(32) bl);
  +   method Action start(Bit#(32) wp, Bit#(32) rp, Bit#(32) bl) if (rdIterCnt == 0 && wrIterCnt == 0);
         $display("start wrPointer=%d rdPointer=%d burstLen=%d", wp, rp, bl);
         indication.started;
         // initialized
  
positive.code:    rule startWrite(wrIterCnt > 0);
        we.writeServers[0].request.put(MemengineCmd{pointer:wrPointer, base:0, len:burstLen*4, burstLen:truncate(burstLen*4)});
        wrIterCnt <= wrIterCnt-1;
        wrStart <= cycles;
     endrule
  
     rule finishWrite;
        let rv0 <- we.writeServers[0].response.get;
        wrLatFifo.enq(cycles-wrStart);
     endrule
     
  
negative.code:    Reg#(Bit#(32))         burstLen <- mkReg(0);
     
     Reg#(Bit#(32))           cycles <- mkReg(0);
     FIFO#(Bit#(32))     rdStartFifo <- mkSizedBRAMFIFO(16);
     FIFO#(Bit#(32))     wrStartFifo <- mkSizedBRAMFIFO(16);
     FIFO#(Bit#(32))       rdLatFifo <- mkSizedBRAMFIFO(16);
     FIFO#(Bit#(32))       wrLatFifo <- mkSizedBRAMFIFO(16);
     
  