anchor.diff:     Reg#(DmaPointer) ptr <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) woff <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) wbase <- mkReg(0);
  -   
  -   let writeFifo <- mkFIFOF;
  +   Gearbox#(1,nd,Bit#(dsz)) gb <- mk1toNGearbox(clk,rst,clk,rst);
  +   
  +   FIFOF#(Bit#(busWidth)) writeFifo = (interface FIFOF;
  +				       method Bit#(busWidth) first(); return pack(gb.first); endmethod
  +				       method Bool notEmpty(); return gb.notEmpty(); endmethod
  +				       endinterface);
      MemwriteEngine#(busWidth) we <- mkMemwriteEngine(writeFifo);
      let bus_width_in_bytes = fromInteger(valueOf(busWidth)/8);
      
  
positive.code:    endrule
  
     rule bramResp;
        let rv <- br.response.get;
        writeFifo.enq(rv);
     endrule
     
     rule loadReq(i < n);
  
negative.code: 
  endmodule
  
  module mkBRAMWriteClient#(BRAMServer#(bramIdx,d) br)(BRAMWriteClient#(bramIdx,busWidth))
     
     provisos(Bits#(d,dsz),
  	    Div#(busWidth,dsz,nd),
  	    Mul#(nd,dsz,busWidth),
  	    Add#(1,a__,nd),
  	    Add#(1, b__, TMul#(2, nd)),
  	    Add#(nd, c__, TMul#(2, nd)),
  	    Eq#(bramIdx),
  	    Bits#(bramIdx, d__),
  	    Ord#(bramIdx),
  	    Arith#(bramIdx));
  
     Clock clk <- exposeCurrentClock;
     Reset rst <- exposeCurrentReset;
  
     FIFO#(void) f <- mkSizedFIFO(1);
     Reg#(bramIdx) n <- mkReg(0);
  