anchor.diff:      Reg#(Bit#(32)) lo <- mkReg(0);
       Reg#(Bit#(32)) hi <- mkReg(0);
   
  +    Divider divider <- mkDivider;
  +    Reg#(Bool) dividerPending <- mkReg(False);
  +
       Reg#(Bool) clearCache <- mkReg(False);
   
       mkConnection(cache.busClient.request, masterAdapter.busServer.request);
  
positive.code:         jumpTo.deq;
      endrule
  
      rule exec(!pendingLoad.notEmpty && !clearCache);
          Instr inst = unpack(instFIFO.first);
          let pc  = execPC.first;
          let pc1 = pc+1;
  
negative.code:             tagged SLTI  .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(signedLT(rf.rd1(s.rs),signExtend(s.im))))});
              tagged SLTIU .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(         rf.rd1(s.rs)<signExtend(s.im)) )});
              tagged SLTU  .s: execToWB.enq(WbREG{r:s.rt, data:zeroExtend(pack(         rf.rd1(s.rs)<rf.rd2(s.rt)))     });
              tagged DIV   .s:
                  action
                      dividerPending <= True;
                      divider.request.put(tuple3(rf.rd1(s.rs),rf.rd2(s.rt),True));
                  endaction
              tagged DIVU  .s:
                  action
                      dividerPending <= True;
                      divider.request.put(tuple3(rf.rd1(s.rs),rf.rd2(s.rt),False));
                  endaction
              tagged MULT  .s:
                  action
                      Int#(64) r1 = unpack(signExtend(rf.rd1(s.rs)));
  