anchor.diff:  import Instructions::*;
   import Trace::*;
   import RFile::*;
  +import Divider::*;
   
   typedef union tagged {
       struct { Ridx     r;    Bit#(32) data;               } WbREG;
  
positive.code:     rule clearTheCaches(clearCache);
          clearCache <= False;
          cache.clear;
      endrule
  
      rule fetchAhead(!jumpTo.notEmpty && !clearCache);
  
negative.code:     Reg#(Bit#(32)) lo <- mkReg(0);
      Reg#(Bit#(32)) hi <- mkReg(0);
  
      Divider divider <- mkDivider;
      Reg#(Bool) dividerPending <- mkReg(False);
  
      Reg#(Bool) clearCache <- mkReg(False);
  
      mkConnection(cache.busClient.request, masterAdapter.busServer.request);
  