anchor.diff:     
      interface interrupt = getInterruptVector(portals);
      interface slave = ctrl_mux;
  -   interface master = dma.master;
  +   interface masters = dma.masters;
   
   endmodule : mkPortalTop
  
positive.code:       writeClients = rbm.writeClients;
     end
  
     MemServer#(addrWidth, TMul#(32,N)) dma <- mkMemServer(dmaIndicationProxy.ifc, readClients, writeClients);
  
     DmaConfigWrapper dmaConfigWrapper <- mkDmaConfigWrapper(DmaConfig,dma.request);
  
  
negative.code: 
  typedef enum {RbmIndication, RbmRequest, DmaIndication, DmaConfig} IfcNames deriving (Eq,Bits);
  
  module [Module] mkPortalTop(PortalTop#(addrWidth,TMul#(32,N),Empty,1))
     provisos (Add#(a__, addrWidth, 40),
  	     Add#(a__, b__, 40),
  	     Add#(addrWidth, c__, 52),
  