anchor.diff:      Reg#(Bit#(1)) serdes_running <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
       SyncBitIfc#(Bit#(1)) fifo_reset_sync <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  +    SyncBitIfc#(Bit#(1)) astate_idle <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
       Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
  
positive.code: 
  typedef enum { QIdle, QTrain, QOff} QState deriving (Bits,Eq);
  typedef enum { AIdle, ADelay, AWDelay, AEdge, ACEdge, AWait, ACompare, AValid,
       A1Changed, A1Stable, ASecond, AFound, AResetman, AStart, AAlign, ADone } AState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, TrainRotate trainrot)(IserdesDatadeser);
  
negative.code:         fifo_reset <= fifo_reset_sync.read();
      endrule
  
      rule clear_fifo if (astate_idle.read() == 1);
          dfifo.clear();
      endrule
      rule setrule;
          delaye2.reset(astate_idle.read());
          delaye2.cinvctrl(0);
          delaye2.cntvaluein(0);
          delaye2.ld(0);
  