anchor.diff:     MemServerGearbox#(PcieDataBusWidth,DataBusWidth) axiGearbox <- mk1toNMemServerGearbox();
      let gearboxCnx <- mkConnection(splitter.busClient, axiGearbox.server);
   
  -   let requestSize = 64;
  -   let responseSize = 16;
  -   let bytesPerEntry = valueOf(TDiv#(PcieDataBusWidth,8));
  -   let wordsPerEntry = valueOf(TDiv#(PcieDataBusWidth,32));
  -
  -   BRAM_Configure bramConfig = defaultValue;
  -   bramConfig.latency = 2;
  -   bramConfig.memorySize = 4096*4/bytesPerEntry; // 4 pages
  -   BRAM2Port#(Bit#(32),Bit#(PcieDataBusWidth)) bram <- mkBRAM2Server(bramConfig);
  -
  -   let arbIfc <- mkFixedPriority();
  -   Arbiter#(3, BRAMRequest#(Bit#(32),Bit#(PcieDataBusWidth)),Bit#(PcieDataBusWidth)) arbiter <- mkArbiter(arbIfc,2);
  -   let arbCnx <- mkConnection(arbiter.master, bram.portB);
  -
  -   MemServer#(PcieDataBusWidth)            bramMemA <- mkMemServerFromBram(bram.portA);
  -   PhysMemSlave#(32,PcieDataBusWidth)      bramMemB <- mkPhysMemSlaveFromBram(arbiter.users[0]);
  -   MemServerPortal          bramMemServerPortal <- mkPhysMemSlavePortal(bramMemB,bramIndication);
  -
  -   let portB1 = arbiter.users[1];
  -   let portB2 = arbiter.users[2];
      Reg#(Bit#(16)) requestId <- mkReg(0);
      Reg#(Bit#(16)) responseId <- mkReg(0);
      Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);
  
positive.code:       method Action trace(Bool enabled);
  	 traceEnabled <= enabled;
        endmethod
        method Action read32(Bit#(32) addr);
  	 araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });
        endmethod
        method Action write32(Bit#(32) addr, Bit#(32) value);
  	 awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });
  	 wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});
        endmethod
        method Action read(Bit#(32) addr);
  	 araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });
        endmethod
        method Action write(Bit#(32) addr, Bit#(DataBusWidth) value);
  	 awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });
  	 wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});
        endmethod
  
negative.code:    let wdataCnx  <- mkConnection(toGet(wdataFifo), axiRootPortMemSlave.write_server.writeData);
     let doneCnx   <- mkConnection(axiRootPortMemSlave.write_server.writeDone, toPut(doneFifo));
  
     rule rl_rdata if (!inSetup);
        let rdata <- toGet(rdataFifo).get();
        if (rdata.tag == 0)
  	 driverInd.readDone(truncate(rdata.data));
     endrule
  
     rule rl_writeDone if (!inSetup);
        let tag <- toGet(doneFifo).get();
        if (tag == 0)
  	 driverInd.writeDone();
  