anchor.diff:      rule copyReadWriteRule (copyBusy);
          let data <- copy_read_chan.readData.get;
          $display("copyReadWrite addr %h", copyWriteAddr);
  -       copy_write_chan.writeReq.put(DMAAddressRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: extend(1), tag: truncate(copyWriteAddr >> 3)});
  -       copy_write_chan.writeData.put(DMAData{data: data.data, tag: copyWriteAddr >> 3});
  +       copy_write_chan.writeReq.put(DMAAddressRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: 1, tag: copyWriteAddr[8:3]});
  +       copy_write_chan.writeData.put(DMAData{data: data.data, tag: copyWriteAddr[8:3]});
          copyWriteAddr <= copyWriteAddr + 8;
       endrule
       
  
positive.code: 	       copyWriteCount <= f_in.first()[15:0];
  	       f_in.deq();  // word 3
  	    endaction
  	    for (ii <= 4; ii < 8; ii <= ii+1)
  	       f_in.deq;  // discard words 4-7
  	    copyBusy <= True;
  	 endseq
  
negative.code:    Reg#(DmaMemHandle) copyWriteHandle <- mkReg(0);
     Reg#(Bit#(32)) copyTag <- mkReg(0);
     Reg#(Bool) copyBusy <- mkReg(False);
     Stmt copyStart = 
     seq
        while(True)
  