anchor.diff:        Bool permitted = csr_regfile.access_permitted_2 (rg_cur_priv, csr_addr, read_not_write);
   
         if (! permitted) begin
  -	 rg_state <= CPU_TRAP;
  +	 rg_state <= CPU_CSRRx_TRAP;
   
   	 // Debug
   	 fa_emit_instr_trace (minstret, stage1.out.data_to_stage2.pc, instr, rg_cur_priv);
  
positive.code:    // external interrupt and RET rules. Separated to break long timing
     // paths from stage2 and stage3 status to IFetch
  
     rule rl_trap_fetch (rg_state == CPU_SPLIT_FETCH);
        let new_epoch <- fav_update_epoch;
        let m_old_pc   = tagged Invalid;
        fa_start_ifetch (new_epoch,
  
negative.code:       rg_sstatus_SUM <= 0;
  `endif
  
        rg_state <= CPU_START_TRAP_HANDLER;
  
        stage1.set_full (False);
        stage2.set_full (False);
  