anchor.diff:     Reg#(Bit#(logawidth)) countreg <- mkReg(0);
      FIFOF#(a) resultFifo <- mkFIFOF;
   
  -   Probe#(Bit#(awidth)) shiftprobe <- mkProbe();
  -   Probe#(Bit#(1)) selprobe <- mkProbe();
  -
      Wire#(Bit#(1)) misoWire <- mkDWire(0);
  -
  -   rule selproberule;
  -       selprobe <= selreg;
  -   endrule
   
      rule running if (countreg > 0);
         countreg <= countreg - 1;
         Bit#(awidth) newshiftreg = { shiftreg[valueOf(awidth)-2:0], misoWire };
         $display("newshiftreg = %08h", newshiftreg);
         shiftreg <= newshiftreg;
  -      shiftprobe <= newshiftreg;
         if (countreg == 1 && resultFifo.notFull) begin
   	 resultFifo.enq(unpack(newshiftreg));
   	 selreg <= 1;
  
positive.code:    rule finished;
        let result <- spi.response.get();
        $display("master received %h", result);
        responseProbe <= result;
        if (result == slaveV)
  	 $finish(0);
        else
  
negative.code: import Connectable :: *;
  import StmtFSM     :: *;
  import SpecialFIFOs:: *;
  
  (* always_enabled *)
  interface SpiPins;
  