anchor.diff:  import ALTERA_ETH_PMA_RECONFIG_WRAPPER      ::*;
   import ALTERA_ETH_PMA_RESET_CONTROL_WRAPPER ::*;
   
  +`ifdef USE_4_PORTS
  +typedef 4 PortNum;
  +`elsif USE_2_PORTS
  +typedef 2 PortNum;
  +`endif
  +
   interface PhyMgmtIfc;
      method Action      phy_mgmt_address(Bit#(7) v);
      method Action      phy_mgmt_read(Bit#(1) v);
  
positive.code:    endrule
  
     /* connect all three components */
     Vector#(np, B2C1) tx_clk;
     Vector#(np, B2C1) rx_clk;
     for (Integer i=0; i < valueOf(np); i=i+1) begin
        tx_clk[i] <- mkB2C1();
        rx_clk[i] <- mkB2C1();
     end
  
     rule out_pma_clk;
        for (Integer i=0; i < valueOf(np); i=i+1) begin
           tx_clk[i].inputclock(xcvr.tx.pma_clkout[i]);
           rx_clk[i].inputclock(xcvr.rx.pma_clkout[i]);
        end
     endrule
  
     Vector#(np, Clock) out_tx_clk;
     Vector#(np, Clock) out_rx_clk;
     for (Integer i=0; i< valueOf(np); i=i+1) begin
        out_tx_clk[i] = tx_clk[i].c;
        out_rx_clk[i] = rx_clk[i].c;
     end
  
     Vector#(np, Wire#(Bit#(1))) rx_serial_wires <- replicateM(mkDWire(0));
  
     function Bit#(1) getBit(Bit#(n) data, Integer i);
        return data[i];
  
negative.code:    endinterface
  
     interface Parallel parallel;
        method Vector#(PortNum, Bit#(40)) rx_parallel_data;
           Vector#(PortNum, Bit#(40)) ret_val;
           for(Integer i=0; i < valueOf(PortNum); i = i+1) begin
              ret_val[i] = unpack(xcvr.rx.pma_parallel_data)[39 + 80 * i : 80 * i];
           end
           return ret_val;
  