anchor.diff:      method Action setDeLineCountMinMax(Bit#(11) min, Bit#(11) max);
       method Action setNumberOfLines(Bit#(11) lines);
       method Action setNumberOfPixels(Bit#(12) pixels);
  -//
  -    //method Bool vsync();
  -    //method Bool hsync();
       interface HDMI hdmi;
   endinterface
   
  
positive.code:             index[1] = 1;
          Bit#(32) data = patternRegs[index];
  
          bramOutStageFifo.enq(Rgb888Stage { vsync: vsync, hsync: hsync, de: dataEnable, pixel: unpack(truncate(data)) });
          lineBuffer.readAddr(0);
  
          if (dataEnable)
  
negative.code:         else if (dataEnable)
              dataCount <= dataCount + 1;
  
          bramOutStageFifo.enq(Rgb888Stage { vsync: vsync, hsync: hsync, de: dataEnable, pixel: Rgb888{r:0,g:0,b:0}, dataCount: dataCount });
          lineBuffer.readAddr(dataCount);
  
      endrule
  
      Reg#(Rgb888Stage) rgb888StageReg <- mkReg(unpack(0));
      Reg#(Yuv444IntermediatesStage) yuv444IntermediatesStageReg <- mkReg(
          Yuv444IntermediatesStage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
      Reg#(Yuv444Stage) yuv444StageReg <- mkReg(
          Yuv444Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
      Reg#(Yuv422Stage) yuv422StageReg <- mkReg(
          Yuv422Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
      Reg#(Bool) evenOddPixelReg <- mkReg(False);
  
      rule bramOutStage;
          let d <- lineBuffer.readData;
  