anchor.diff:    Reg#(Bit#(7)) jj <- mkReg(0);
      Reg#(Char) aData <- mkReg(0);
      Reg#(Char) bData <- mkReg(0);
  -   Reg#(Bit#(16)) lim1jm1 <- mkReg(0);
  -   Reg#(Bit#(16)) lim1j <- mkReg(0);
  -   Reg#(Bit#(16)) lijm1 <- mkReg(0);
  +   Reg#(Bit#(16)) k0j <- mkReg(0);
  +   Reg#(Bit#(16)) k1jm1 <- mkReg(0);
  +
  +
      BRAM2Port#(StringIdx, Char) strA  <- mkBRAM2Server(defaultValue);
      BRAM2Port#(StringIdx, Char) strB <- mkBRAM2Server(defaultValue);
      BRAM2Port#(LIdx, Bit#(16)) matL <- mkBRAM2Server(defaultValue);
  
positive.code:    FIFOF#(void) bReady <- mkFIFOF;
     FIFOF#(void) mReady <- mkFIFOF;
  
     Stmt maxQuadratic =
     seq while(True)
     seq
        action
  	 let ra <- aReady.deq();
  	 $display("Splice A Ready");
        endaction
        action
  	 let rb <- bReady.deq();
  	 $display("Splice B Ready");
        endaction
        for (ii<= 0; ii < aLenReg; ii <= ii + 1)
  	 seq
  	    matL.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {ii,0}, datain: 0});
  	    endseq
        for (ii<= 0; ii < aLenReg; ii <= ii + 1)
  	 seq
  	    matL.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {0,ii}, datain: 0});
  	 endseq
        for (ii<= 1; ii <= aLenReg; ii <= ii + 1)
  	 for (jj<= 1; jj <= bLenReg; jj <= jj + 1)
  	    seq
  	       strA.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: ii-1, datain: 0});
  	       strB.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: jj-1, datain: 0});
  	       action
  		  let ta <- strA.portA.response.get();
  		  let tb <- strB.portA.response.get();
  		  aData <= ta;
  		  bData <= tb;
  	       endaction
  	       if (aData == bData)
  		  seq
  		     matL.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {ii-1,jj-1}, datain: 0});
  		     action
  			let temp <- matL.portA.response.get();
  			lim1jm1 <= temp;
  		     endaction
  		     matL.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {ii,jj}, datain: lim1jm1+1});
  		     
  		  endseq
  	       else
  		  seq
  		     matL.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {ii,jj-1}, datain: 0});
  		     action
  			let tlijm1 <- matL.portA.response.get();
  			lijm1 <= tlijm1;
  		     endaction
  		     matL.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {ii-1,jj}, datain: 0});
  		     action
  			let tlim1j <- matL.portA.response.get();
  			lim1j <= tlim1j;
  		     endaction
  			matL.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {ii,jj}, datain: max(lijm1,lim1j)});
  		  endseq
  	    endseq
        matL.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {aLenReg, bLenReg}, datain: 0});
        action
  	 let result <- matL.portA.response.get();
  	 indication.searchResult(zeroExtend(unpack(result)));
        endaction
     endseq
     endseq;
     
     
     
     // create BRAM Write client for matL
  
negative.code:       l2n.start(strPointer, zeroExtend(dest), bram_start_idx, bram_finish_idx);
     endmethod
  
     method Action start(int alg);
        case (alg) 
  	 0: hirschA.start();
  	 1: hirschB.start();
  	 2: hirschC.start();
  	 default:
        endcase
     endmethod
  
  endmodule
  