anchor.diff:     Reg#(Bit#(1)) selreg <- mkReg(1);
      Reg#(Bit#(TAdd#(logawidth,1))) countreg <- mkReg(0);
      FIFOF#(a) resultFifo <- mkFIFOF;
  +
  +   Clock outputClock = invert_clk ? clockInverter.slowClock : defaultClock;
  +   Reset outputReset = defaultReset;
  +   ReadOnly#(Bit#(awidth)) sync_shiftreg <- mkNullCrossingWire(outputClock, shiftreg);
   
      Wire#(Bit#(1)) misoWire <- mkDWire(0);
      let verbose = False;
  
positive.code: endmodule
  
  module mkSpiTestBench(Empty);
     Bit#(20) slaveV = 20'h96ed5;
     Bit#(20) masterV = 20'h8baeb;
     let verbose = False;
  
     SPI#(Bit#(20)) spi <- mkSPI(4, True);
     Reg#(Bit#(20)) slaveCount <- mkReg(20, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
     Reg#(Bit#(20)) slaveValue <- mkReg(slaveV, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
     Reg#(Bit#(20)) responseValue <- mkReg(0, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
  
     rule slaveIn if (spi.pins.sel_n == 0);
        slaveCount <= slaveCount - 1;
  
negative.code:       method Action miso(Bit#(1) v);
           misoWire <= v;
        endmethod
        interface Clock clock = outputClock;
        interface Clock deleteme_unused_clock = invert_clk ? defaultClock : clockInverter.slowClock;
        interface Reset deleteme_unused_reset = defaultReset;
     endinterface: pins
  