anchor.diff:        rg_mstatus_MXR <= mstatus_MXR;
         rg_satp        <= satp;
         rg_tval        <= addr;
  -      WordXL even_addr = { addr [xlen-1:2], 2'b_00 };
  -      imem32.req (f3, even_addr, priv, sstatus_SUM, mstatus_MXR, satp);
  +
  +      // Cache the previous output, if valid
  +      if (imem32.valid) begin
  +	 rg_cache_addr     <= imem32.pc;
  +	 rg_cache_b16 <= imem32.instr [31:16];
  +      end
  +
  +      WordXL addr_of_b32 = fn_to_b32_addr (addr);
  +
  +      // Fetch next 32b word if request is odd-16b aligned, we've already got those 16b, and it's a 32b instr
  +      // (the 16b we've already got is saved in r16_cache_b16).
  +      // Note: since we know it's a 32b instr, this next fetch is not speculative, so ok if it page faults.
  +      if (   is_addr_odd16 (addr)
  +	  && imem32.valid
  +	  && (addr_of_b32 == imem32.pc)
  +	  && is_32b_instr (imem32.instr [31:16]))
  +	 begin
  +	    addr_of_b32 = addr_of_b32 + 4;
  +	 end
  +
  +      imem32.req (f3, addr_of_b32, priv, sstatus_SUM, mstatus_MXR, satp);
         if (verbosity > 0) begin
  -	 $display ("CPU_Fetch_C.req: addr 0x%0h, even_addr 0x%0h", addr, even_addr);
  +	 $display ("CPU_Fetch_C.req: addr 0x%0h, addr_of_b32 0x%0h", addr, addr_of_b32);
         end
      endmethod
   
  
positive.code:    method Bool     is_i32_not_i16 = (cond_i32_odd || cond_i32_even);
  
     method WordXL   pc       = rg_pc;
     method Instr    instr    = instr_out;
     method Bool     exc      = imem32.exc;
     method Exc_Code exc_code = imem32.exc_code;
     method WordXL   tval     = rg_tval;        // Can be different from rg_pc
  
negative.code: 
  // This module completely encapsulates the logic needed to extend it to
  // 16-bit "compressed" instructions ('C' extension)
  // which then also includes 32-bit instructions which may be only 16-bit-aligned,
  // since 32b and 16b instructions can be freely mixed.
  
  // ================================================================
  // Exports
  