anchor.diff:        endmethod
         method Action sglist(Bit#(32) pref, Bit#(64) addr, Bit#(32) len);
   	 if (bad_pointer(pref))
  -	    dmaIndication.dmaError(extend(pack(DmaErrorBadPointer2)), pref, 0, 0);
  +	    dmaErrorFifo.enq(DmaError { errorType: DmaErrorBadPointer2, pref: pref });
   `ifdef BSIM
   `ifndef PCIE
   	 let va <- pareff(pref, len);
  
positive.code: endmodule
  
     
  module mkConfigMemServerRW#(DmaIndication dmaIndication,
  			    Vector#(nMasters,TagGen#(nrc, numReadTags)) readTagGens,
  			    Vector#(nMasters,TagGen#(nwc, numWriteTags)) writeTagGens,
  
negative.code: 		      endseq;
     FSM trafficFSM <- mkFSM(trafficStmt);
  
     FIFO#(DmaError) dmaErrorFifo <- mkFIFO();
     rule dmaError;
        let error <- toGet(dmaErrorFifo).get();
        dmaIndication.dmaError(extend(pack(error.errorType)), error.pref, 0, 0);
     endrule
  
     interface DmaConfig request;
        method Action getStateDbg(ChannelType rc);
  	 if (rc == Write)
  