anchor.diff:     interface Wire#(Bit#(1)) rvalid;
      interface Wire#(Bit#(1)) wready;
      interface Wire#(Bit#(1)) bvalid;
  -endinterface
  -
  -interface AxiSlaveWires;
  +
  +   interface Wire#(Bit#(12)) rid;
  +   interface Wire#(Bit#(2))  rresp;
  +   interface Wire#(Bit#(32)) rdata;
  +   interface Wire#(Bit#(1))  rlast;
  +   interface Wire#(Bit#(12)) bid;
  +   interface Wire#(Bit#(2)) bresp;
  +endinterface
  +
  +interface AxiSlaveWires#(numeric type data_width);
  +   interface Wire#(Bit#(32)) araddr;
  +   interface Wire#(Bit#(2)) arburst;
  +   interface Wire#(Bit#(4)) arcache;
  +   interface Wire#(Bit#(6)) arid;
  +   interface Wire#(Bit#(4)) arlen;
  +   interface Wire#(Bit#(2)) arlock;
  +   interface Wire#(Bit#(3)) arprot;
  +   interface Wire#(Bit#(4)) arqos;
  +   interface Wire#(Bit#(2)) arsize;
      interface Wire#(Bit#(1)) arvalid;
  +   interface Wire#(Bit#(32)) awaddr;
  +   interface Wire#(Bit#(2)) awburst;
  +   interface Wire#(Bit#(4)) awcache;
  +   interface Wire#(Bit#(6)) awid;
  +   interface Wire#(Bit#(4)) awlen;
  +   interface Wire#(Bit#(2)) awlock;
  +   interface Wire#(Bit#(3)) awprot;
  +   interface Wire#(Bit#(4)) awqos;
  +   interface Wire#(Bit#(2)) awsize;
      interface Wire#(Bit#(1)) awvalid;
      interface Wire#(Bit#(1)) rready;
  +   interface Wire#(Bit#(6)) wid;
  +   interface Wire#(Bit#(TDiv#(data_width,8))) wstrb;
  +   interface Wire#(Bit#(data_width)) wdata;
  +   interface Wire#(Bit#(1)) wlast;
      interface Wire#(Bit#(1)) wvalid;
      interface Wire#(Bit#(1)) bready;
   endinterface
   
   module mkAxiMasterWires(AxiMasterWires);
  -   Vector#(5, Wire#(Bit#(1))) wires <- replicateM(mkDWire(0));
  +   Vector#(6, Wire#(Bit#(1))) wires <- replicateM(mkDWire(0));
  +   Vector#(1, Wire#(Bit#(32))) datawires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(12))) idwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(2))) respwires <- replicateM(mkDWire(0));
      interface Wire arready = wires[0];
      interface Wire awready = wires[1];
      interface Wire rvalid = wires[2];
      interface Wire wready = wires[3];
  -   interface Wire bvalid = wires[4];
  +   interface Wire rid  = idwires[0];
  +   interface Wire rresp  = respwires[0];
  +   interface Wire rdata  = datawires[0];
  +   interface Wire rlast  = wires[4];
  +   interface Wire bvalid = wires[5];
  +   interface Wire bid    = idwires[1];
  +   interface Wire bresp  = respwires[1];
   endmodule
   
  -module mkAxiSlaveWires(AxiSlaveWires);
  +module mkAxiSlaveWires(AxiSlaveWires#(data_width));
      Vector#(5, Wire#(Bit#(1))) wires <- replicateM(mkDWire(0));
  -   interface Wire arvalid = wires[0];
  -   interface Wire awvalid = wires[1];
  -   interface Wire rready = wires[2];
  -   interface Wire wvalid = wires[3];
  -   interface Wire bready = wires[4];
  +   Vector#(2, Wire#(Bit#(32))) addrwires <- replicateM(mkDWire(0));
  +   Vector#(1, Wire#(Bit#(data_width))) datawires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(2))) burstwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(4))) cachewires <- replicateM(mkDWire(0));
  +   Vector#(3, Wire#(Bit#(6))) idwires <- replicateM(mkDWire(0));
  +   Vector#(1, Wire#(Bit#(TDiv#(data_width,8)))) strbwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(4))) lenwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(2))) lockwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(3))) protwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(4))) qoswires <- replicateM(mkDWire(0));
  +   Vector#(3, Wire#(Bit#(1))) validwires <- replicateM(mkDWire(0));
  +   Vector#(2, Wire#(Bit#(2))) sizewires <- replicateM(mkDWire(0));
  +   Vector#(3, Wire#(Bit#(1))) readywires <- replicateM(mkDWire(0));
  +   Vector#(1, Wire#(Bit#(1))) lastwires <- replicateM(mkDWire(0));
  +   interface Wire araddr = addrwires[0];
  +   interface Wire arburst = burstwires[0];
  +   interface Wire arcache = cachewires[0];
  +   interface Wire arid = idwires[0];
  +   interface Wire arlen = lenwires[0];
  +   interface Wire arlock = lockwires[0];
  +   interface Wire arprot = protwires[0];
  +   interface Wire arqos = qoswires[0];
  +   interface Wire arsize = sizewires[0];
  +   interface Wire arvalid = validwires[0];
  +   interface Wire awaddr = addrwires[1];
  +   interface Wire awburst = burstwires[1];
  +   interface Wire awcache = cachewires[1];
  +   interface Wire awid = idwires[1];
  +   interface Wire awlen = lenwires[1];
  +   interface Wire awlock = lockwires[1];
  +   interface Wire awprot = protwires[1];
  +   interface Wire awqos = qoswires[1];
  +   interface Wire awsize = sizewires[1];
  +   interface Wire awvalid = validwires[1];
  +   interface Wire rready = readywires[0];
  +   interface Wire wid = idwires[2];
  +   interface Wire wstrb = strbwires[0];
  +   interface Wire wdata = datawires[0];
  +   interface Wire wlast = lastwires[0];
  +   interface Wire wvalid = validwires[2];
  +   interface Wire bready = readywires[1];
   endmodule
   
   (* always_ready, always_enabled *)
  
positive.code:        endrule
         rule axi_master_handshake5;
              vm_axi_gp[i].bvalid(vtopmw_axi_gp[i].bvalid);
         endrule
         end
      for (Integer i = 0; i < 2; i = i + 1)
  
negative.code:             endinterface
              interface Put resp_b;
                  method Action put(Axi3WriteResponse#(12) v) if (vm_axi_gp[i].bready() != 0);
                      vtopmw_axi_gp[i].bvalid <= 1;
                      vtopmw_axi_gp[i].bid    <= v.id;
                      vtopmw_axi_gp[i].bresp  <= v.resp;
                  endmethod
              endinterface
              endinterface
  