anchor.diff:  
       default_clock clock(RDCLK);
       input_clock clkdiv (WRCLK) = clkdiv;
  -    // reset RST;
  +    no_reset;
       port DIP = 0;
   
  -    method          di(DI) enable((*inhigh*) en0) clocked_by (clock);
  +    method          reset(RST) enable((*inhigh*) en9) clocked_by (clkdiv);
  +    method          di(DI) enable((*inhigh*) en0) clocked_by (clkdiv);
       method          rden(RDEN) enable((*inhigh*) en2) clocked_by (clock);
       method          wren(WREN) enable((*inhigh*) en3) clocked_by (clock);
       method DO       dataout() clocked_by(clock);
       method EMPTY    empty() clocked_by(clock);
  -   schedule (di, rden, wren, dataout, empty) CF (di, rden, wren, dataout, empty);
  +   schedule (reset, di, rden, wren, dataout, empty) CF (reset, di, rden, wren, dataout, empty);
   endmodule: mkFIFO18
   
   module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
  
positive.code:       method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
        method                  fifo_wren(FIFO_WREN) enable((*inhigh*) en10) clocked_by (clkdiv);
        method FIFO_WREN_SYNC   fifo_wren_sync() clocked_by (clock);
     output_reset fifo_reset(FIFO_RESET);
        method                  delay_wren(DELAY_WREN) enable((*inhigh*) en11) clocked_by (clkdiv);
        method                  reset(RESET) enable((*inhigh*) en16) clocked_by (clkdiv);
        method FIFO_DATAOUT  dataout() clocked_by(clock);
     schedule (idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
           CF (idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  
negative.code:    method Action   di(Bit#(16) v);
     method Action   rden(Bit#(1) v);
     method Action   wren(Bit#(1) v);
     method Action   reset(Bit#(1) v);
     method Bit#(16) dataout();
     method Bit#(1)  empty();
  endinterface: FIFO18
  