anchor.diff:      rule clkdiv_rule if (bvi_reset_reg != 0);
           let ds = dstate;
           let dc = dcounter;
  -        let sric = sync_reset_inc_ce;
  +        Bit#(3) sric = sync_reset_inc_ce;
           let sbs = 0;
     
           dc = dc - 1;
  
positive.code:     Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) ctrl_data <- mkReg(0);
      Reg#(HState)  hstate <- mkReg(HIdle);
      Reg#(Bit#(6)) hcounter <- mkReg(0);
      Reg#(Bit#(1)) edge_intor_reg <- mkReg(0);
      SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
      Wire#(Bit#(1)) this_align_busy_wire <- mkDWire(0);
      Reg#(Bit#(1)) this_start_align_reg <- mkReg(0);
      Reg#(Bit#(16)) serdes_counter <- mkReg(0);
      Reg#(QState)  qstate <- mkReg(QIdle);
  
      rule trainrot_rule;
          serbvi.train0(trainrot[0]);
          serbvi.train1(trainrot[1]);
          serbvi.train2(trainrot[2]);
          serbvi.train3(trainrot[3]);
          serbvi.train4(trainrot[4]);
          serbvi.train5(trainrot[5]);
          serbvi.train6(trainrot[6]);
          serbvi.train7(trainrot[7]);
          serbvi.train8(trainrot[8]);
          serbvi.train9(trainrot[9]);
      endrule
      //rule clkdivreset_rule if (bvi_resets_reg.read() != 0);
          //dfifo_reset_r.send(this_align_busy_wire);
      //endrule
      rule qfsmreset_rule if (bvi_resets_reg.read() == 0);
          this_aligned_reg <= 0;
          qstate <= QIdle;
          serdes_counter <= 0;
          ctrl_sample <= 0;
          this_start_align_reg <= 0;
      endrule
      rule qfsmall;
          serbvi.start_align_i(this_start_align_reg);
          let abusy = pack(qstate != QIdle);
          dfifo_reset_r.send(abusy);
          this_align_busy_wire <= abusy;
          samplein_reset_null.send(ctrl_sample[2]);
      endrule
      rule qfsm_rule if (bvi_resets_reg.read() != 0);
          let qs = qstate;
          let scount = serdes_counter;
          let sa = 0;
          if (qstate == QIdle && align_start == 1)
              begin
              scount = 0;
              sa = 1;
              qs = QTrain;
              end
          if (qstate == QTrain)
              qs = QOn;
          if (qstate == QOn && serbvi.busy_align_i() == 1)
              qs = QOff;
          if (qstate == QOff && serbvi.busy_align_i() == 0)
              begin
              ctrl_sample <= serbvi.samplein();
              if (serdes_counter <= 'h7fff)
                  begin
                  this_aligned_reg <= 1;
                  qs = QIdle;
                  end
              else
                  begin
                  scount = scount + 1;
                  sa = 1;
                  qs = QTrain;
                  end
              end
          qstate <= qs;
          serdes_counter <= scount;
          this_start_align_reg <= sa;
      endrule
  
      rule reset_clock_rule;
  
negative.code:     endmethod
      method Action                 reset(Bit#(1) v);
          bvi_reset_reg <= v;
      endmethod
      method Bit#(1)                empty();
          return dfifo.empty();
  