anchor.diff:             ,Mul#(dataWidthBytes, 8, busDataWidth)
              ,Div#(busDataWidth, 8, dataWidthBytes)
              );
  +   let verbose = False;
   
      FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();
      FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();
  
positive.code: 
     AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
     let verbose = False;
  
      Reg#(Bit#(32)) cycles      <- mkReg(0);
      rule count;
         cycles <= cycles + 1;
      endrule
  
     rule read_req;
        let addrBeat <- readAddrGenerator.addrBeat.get();
  
negative.code:       readTagFifo.enq(tag);
        readLastFifo.enq(addrBeat.last);
        Bit#(bramAddrWidth) regFileAddr = truncate(addr << fromInteger(valueOf(TLog#(dataWidthBytes))));
        req_addr.enq(regFileAddr);
        if (verbose) $display("%d read_server.readData (a) %h %d last=%d", cycles, addr, burstCount, addrBeat.last);
     endrule
  
     rule read_bram_req;
        let addr <- toGet(req_addr).get;
        br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:addr, datain:?});
     endrule
  
     rule req_aw;
        let req <- toGet(req_aws).get;
        br.request.put(req);
     endrule
  
     interface PhysMemReadServer read_server;
  