anchor.diff:     method Action data_n(Bit#(8) v);
      method Action frame_p(Bit#(1) v);
      method Action frame_n(Bit#(1) v);
  +   method Action lclk_p(Bit#(1) v);
  +   method Action lclk_n(Bit#(1) v);
  +endinterface
  +
  +interface Par_txi;
      method Bit#(1) wr_wait_p();
      method Bit#(1) wr_wait_n();
      method Bit#(1) rd_wait_p();
  
positive.code:    
     
     interface Par_saxi;
        method araddr(saxi_araddr) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_araddr);
        method arburst(saxi_arburst) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arburst);
        method arcache(saxi_arcache) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arcache);
        method saxi_aresetn aresetn() clocked_by(saxiclk) reset_by(saxireset);
        method arid(saxi_arid) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arid);
        method arlen(saxi_arlen) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arlen);
        method arlock(saxi_arlock) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arlock);
        method arprot(saxi_arprot) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arprot);
        method arqos(saxi_arqos) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arqos);
        method saxi_arready arready() clocked_by(saxiclk) reset_by(saxireset);
        method arsize(saxi_arsize) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arsize);
        method arvalid(saxi_arvalid) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_arvalid);
        method awaddr(saxi_awaddr) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awaddr);
        method awburst(saxi_awburst) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awburst);
        method awcache(saxi_awcache) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awcache);
        method awid(saxi_awid) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awid);
        method awlen(saxi_awlen) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awlen);
        method awlock(saxi_awlock) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awlock);
        method awprot(saxi_awprot) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awprot);
        method awqos(saxi_awqos) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awqos);
        method saxi_awready awready() clocked_by(saxiclk) reset_by(saxireset);
        method awsize(saxi_awsize) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awsize);
        method awvalid(saxi_awvalid) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_awvalid);
        method saxi_bid bid() clocked_by(saxiclk) reset_by(saxireset);
        method bready(saxi_bready) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_bready);
        method saxi_bresp bresp() clocked_by(saxiclk) reset_by(saxireset);
        method saxi_bvalid bvalid() clocked_by(saxiclk) reset_by(saxireset);
        method saxi_rdata rdata() clocked_by(saxiclk) reset_by(saxireset);
        method saxi_rlast rlast() clocked_by(saxiclk) reset_by(saxireset);
        method rready(saxi_rready) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_rready);
        method saxi_rresp rresp() clocked_by(saxiclk) reset_by(saxireset);
        method saxi_rvalid rvalid() clocked_by(saxiclk) reset_by(saxireset);
        method wdata(saxi_wdata) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_wdata);
        method wid(saxi_wid) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_wid);
        method wlast(saxi_wlast) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_wlast);
        method saxi_wready wready() clocked_by(saxiclk) reset_by(saxireset);
        method wstrb(saxi_wstrb) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_wstrb);
        method wvalid(saxi_wvalid) clocked_by(saxiclk) reset_by(saxireset) enable((*inhigh*) EN_saxi_wvalid);
        method saxi_rid rid() clocked_by(saxiclk) reset_by(saxireset);
        interface extraType   extra;
     endinterface
     
     
  schedule (
     csysack, cactive, reset_chip, reset_fpga, txo_data_p, txo_data_n,
     txo_frame_p, txo_frame_n, txo_lclk_p, txo_lclk_n, rxo_wr_wait_p,
     rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, rxi_cclk_p,
     rxi_cclk_n, emaxi_awid, emaxi_awaddr, emaxi_awlen, emaxi_awsize,
     emaxi_awburst, emaxi_awlock, emaxi_awcache, emaxi_awprot,
     emaxi_awvalid, esaxi_awready, emaxi_wid, emaxi_wdata, emaxi_wstrb,
     emaxi_wlast, emaxi_wvalid, esaxi_wready, emaxi_bready, esaxi_bid,
     esaxi_bresp, esaxi_bvalid, emaxi_arid, emaxi_araddr, emaxi_arlen,
     emaxi_arsize, emaxi_arburst, emaxi_arlock, emaxi_arcache,
     emaxi_arprot, emaxi_arvalid, esaxi_arready, emaxi_rready,
     esaxi_rid, esaxi_rdata, esaxi_rresp, esaxi_rlast, esaxi_rvalid,
     emaxi_awqos, emaxi_arqos,
     // Inputs
     clkin_100, esaxi_aclk, emaxi_aclk, reset, esaxi_aresetn,
     emaxi_aresetn, csysreq, rxi_data_p, rxi_data_n, rxi_frame_p,
     rxi_frame_n, rxi_lclk_p, rxi_lclk_n, txi_wr_wait_p, txi_wr_wait_n,
     txi_rd_wait_p, txi_rd_wait_n, emaxi_awready, esaxi_awid,
     esaxi_awaddr, esaxi_awlen, esaxi_awsize, esaxi_awburst,
     esaxi_awlock, esaxi_awcache, esaxi_awprot, esaxi_awvalid,
     emaxi_wready, esaxi_wid, esaxi_wdata, esaxi_wstrb, esaxi_wlast,
     esaxi_wvalid, emaxi_bid, emaxi_bresp, emaxi_bvalid, esaxi_bready,
     emaxi_arready, esaxi_arid, esaxi_araddr, esaxi_arlen, esaxi_arsize,
     esaxi_arburst, esaxi_arlock, esaxi_arcache, esaxi_arprot,
     esaxi_arvalid, emaxi_rid, emaxi_rdata, emaxi_rresp, emaxi_rlast,
     emaxi_rvalid, esaxi_rready, esaxi_awqos, esaxi_arqos
  );
  
  endmodule
negative.code:    Reset reset_chip, Reset reset_fpga)(PParallellaLib);
     default_clock clk();
     default_reset rst();
     input_clock maxiclk(emaxi_aclk) = maxiclk;  // assigns the verilog emaxi_aclk
     input_clock saxiclk(esaxi_aclk) = saxiclk;  // assigns the verilog esaxi_aclk
     input_reset maxiclk_reset() = maxiclk_reset; /* from clock*/
     input_reset saxiclk_reset() = saxiclk_reset; /* from clock*/
     
     interface Par_misc;
     method cactive(cactive);
     method csysack(csysack);
     method reset_chip(reset_chip) enable((*inhigh*) EN_reset_chip);
     method reset_fpga(reset_fpga) enable((*inhigh*) EN_reset_fpga);
     endinterface
     
     interface Par_txo;
        method data_p(txo_data_p) enable((*inhigh*) EN_txo_data_p);
        method data_n(txo_data_n) enable((*inhigh*) EN_txo_data_n);
        method frame_p(txo_frame_p) enable((*inhigh*) EN_txo_frame_p);
        method frame_n(txo_frame_n) enable((*inhigh*) EN_txo_frame_n);
     endinterface
  
     interface Par_txi;
        method txo_wr_wait_p wr_wait_p();
        method txo_wr_wait_n wr_wait_n();
        method txo_rd_wait_p rd_wait_p();
  