anchor.diff:  import MemSlave          :: *;
   import Dma               :: *;
   
  -import BRAM         :: *;
  -
  -typedef (function Module#(PortalTop#(40, dsz, ipins,nMasters)) mkPortalTop()) MkPortalTop#(numeric type dsz, type ipins, numeric type nMasters);
  -
   `ifdef Artix7
   typedef 4 PcieLanes;
   typedef 4 NumLeds;
  
positive.code:    interface pins = pciehost.pins;
  endmodule: mkPcieTopFromPortal
  
  `ifndef DataBusWidth
  `define DataBusWidth 64
  `endif
  `ifndef NumberOfMasters
  `define NumberOfMasters 1
  `endif
  (* synthesize *)
  module mkSynthesizeablePortalTop(PortalTop#(40, `DataBusWidth, Empty, `NumberOfMasters));
     let top <- mkPortalTop();
  
negative.code: 	     Add#(d__, TMul#(8, TDiv#(dsz, 32)), 64),
  	     Add#(e__, TMul#(32, TDiv#(dsz, 32)), 256),
  	     Add#(f__, TDiv#(dsz, 32), 8),
  	     Mul#(TDiv#(dsz, 8), 8, dsz)
        );
  
     Clock sys_clk_200mhz <- mkClockIBUFDS(sys_clk_p, sys_clk_n);
  