anchor.diff:        last2Reg <= last1Wire;
         last3Reg <= last2Reg;
         last4Reg <= last3Reg;
  +      last5Reg <= last4Reg;
  +      last6Reg <= last5Reg;
   
         dsp.cea1(1); // (ce1Wire);
         dsp.cea2(1); // (ce2Reg);
  
positive.code:    method Action d(Bit#(25) v);
        dsp.d(v);
     endmethod
     method Bit#(48) p() if (last2Reg == 1 || last3Reg == 1 || last4Reg == 1);
        return dsp.p();
     endmethod
     method Action last(Bit#(1) v);
  
negative.code:    Reg#(Bit#(1))  last2Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last3Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last4Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last5Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last6Reg  <- mkReg(0, reset_by optionalReset);
  
     rule clock_enable_and_reset;
        ce2Reg <= ce1Wire;
  