anchor.diff:  endmodule
   
   module mkAdapterTb(Empty);
  -   ToBit32#(Bit#(72)) adapter72 <- mkToBit32();
  -   ToBit32#(Bit#(17)) adapter17 <- mkToBit32();
  +   ToBit32#(Bit#(72)) tb32_72 <- mkToBit32();
  +   ToBit32#(Bit#(17)) tb32_17 <- mkToBit32();
   
      FromBit32#(Bit#(72)) fb32_72 <- mkFromBit32();
      FromBit32#(Bit#(17)) fb32_17 <- mkFromBit32();
  
positive.code:    FIFOF#(Bit#(asz32)) fifo <- mkFIFOF1();
     Reg#(Bit#(32))   count <- mkReg(0);
  
  
     method Action enq(a val);
         fifo.enq({pack(val),padding});
     endmethod
  
     method Bit#(32) first() if (fifo.notEmpty);
  
negative.code:        dynamicAssert(!fb32_17.notEmpty, "Adapter empty");
         dynamicAssert(fb32_17.notFull, "Adapter not full");
  
  
         // they should be duals
         tb32_72.enq(72'h090807060504030201);
         fb32_72.enq(tb32_72.first);
         tb32_72.deq;
         fb32_72.enq(tb32_72.first);
         tb32_72.deq;
         fb32_72.enq(tb32_72.first);
         tb32_72.deq;
         dynamicAssert(fb32_72.first == 72'h090807060504030201, "Expected 090807060504030201");
         fb32_72.deq;
               
         tb32_17.enq(17'h10203);
         fb32_17.enq(tb32_17.first);
         tb32_17.deq;
         dynamicAssert(fb32_17.first == 17'h10203, "Expected 10203");
         fb32_17.deq;
         	     
         $finish(0);
     endseq
     );
  