anchor.diff:  				     vsync: vsync, hsync: hsync, pixel: pixel };
       endrule
   
  -   rule testpattern_setup;
  -      patternIndex <= {pack(lineCount >= lineMidpoint), pack(pixelCount >= pixelMidpoint)};
  -   endrule
  -
  -   rule testpattern_rule if (testPatternEnabled != 0);
  -      pixelData <= patternRegs[patternIndex];
  -   endrule
  +    rule testpattern_rule if (testPatternEnabled != 0);
  +       pixelData <= patternRegs[{patternIndex1, patternIndex0}];
  +    endrule
   
       interface Put request;
  -        method Action put(Bit#(32) v) if (testPatternEnabled == 0);
  +        method Action put(Bit#(32) v) if (testPatternEnabled == 0 && dataEnable);
   	   pixelData <= v[23:0];
           endmethod
       endinterface: request
  
positive.code: 	    end
              testPatternEnabled <= shadowTestPatternEnabled;
          end
          if (pixelCount == numberOfPixels-1)
             begin
             pixelCount <= 0; 
             if (lineCount == numberOfLines-1)
                 lineCount <= 0;
             else
                 lineCount <= lineCount+1;
             end
          else
              pixelCount <= pixelCount + 1;
      endrule
  
      rule output_data_rule;
          let hsync = (pixelCount < hsyncWidth) ? 1 : 0;
          let vsync = (lineCount < vsyncWidth) ? 1 : 0;
          let isActiveLine = (lineCount >= deLineCountMinimum && lineCount < deLineCountMaximum);
          let dataEnable = (pixelCount >= dePixelCountMinimum && pixelCount < dePixelCountMaximum && isActiveLine);
         Rgb888 pixel = unpack(0);
         if (dataEnable) begin
  	   pixel = unpack(pixelData);
  
negative.code:     Reg#(Bit#(11)) lineCount <- mkReg(0);
      Reg#(Bit#(12)) pixelCount <- mkReg(0);
      Vector#(4, Reg#(Bit#(24))) patternRegs <- replicateM(mkSyncReg(24'h00FFFFFF, axi_clock, axi_reset, defaultClock));
      Reg#(Bit#(1)) patternIndex0 <- mkReg(0);
      Reg#(Bit#(1)) patternIndex1 <- mkReg(0);
      Reg#(Bit#(1)) shadowTestPatternEnabled <- mkSyncReg(1, axi_clock, axi_reset, defaultClock);
      Reg#(Bit#(1)) testPatternEnabled <- mkReg(1);
      Reg#(Bool) waitingForVsync <- mkSyncReg(False, axi_clock, axi_reset, defaultClock);
  