anchor.diff:  			     });
   
   endmodule: mkPcieTop
  +`endif
  
positive.code:    endrule
  endmodule
  
  (* no_default_clock, no_default_reset *)
  module mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
                            Clock sys_clk_p,     Clock sys_clk_n,
  
negative.code: import Leds::*;
  
  // for PCIE
  `ifdef SUPPORT_PCIE
  import Xilinx            :: *;
  import XilinxPCIE        :: *;
  import Xilinx7PcieBridge :: *;
  import PcieToAxiBridge   :: *;
  `endif
  
  
  // generated by tool
  