anchor.diff:  typedef 8 PcieLanes;
   typedef 8 NumLeds;
   `endif
  +`ifndef DataBusWidth
  +`define DataBusWidth 64
  +`endif
  +`ifndef NumberOfMasters
  +`define NumberOfMasters 1
  +`endif
  +`ifndef PinType
  +`define PinType Empty
  +`endif
  +
  +typedef (function Module#(PortalTop#(40, dsz, ipins, `NumberOfMasters)) mkPortalTop()) MkPortalTop#(numeric type dsz, type ipins);
   
   interface PcieTop#(type ipins);
      (* prefix="PCIE" *)
  
positive.code:    interface pins = top.pins;
  endmodule
  
  `ifndef PinType
  `define PinType Empty
  `endif
  module mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
     Clock sys_clk_p,     Clock sys_clk_n,
     Reset pci_sys_reset_n)
     (PcieTop#(`PinType));
     let top <- mkPcieTopFromPortal(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n,mkSynthesizeablePortalTop);
     return top;
  
negative.code: import MemSlave          :: *;
  import Dma               :: *;
  
  `ifdef Artix7
  typedef 4 PcieLanes;
  typedef 4 NumLeds;
  