anchor.diff:  		Bit#(MemOffsetSize) off;
      } DmaError deriving (Bits);
   
  +typedef struct {
  +   Bool cond12;
  +   Bool cond8;
  +   Bool cond4;
  +   Bool cond0;
  +   Bit#(IndexWidth) idxOffset12;
  +   Bit#(IndexWidth) idxOffset8;
  +   Bit#(IndexWidth) idxOffset4;
  +   Bit#(IndexWidth) idxOffset0;
  +   ReqTup req;
  +   } Stage3Params deriving (Bits);
  +
   // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
   module mkMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
      provisos(Log#(MaxNumSGLists, listIdxSize),
  
positive.code:    Vector#(2,FIFOF#(ReqTup))          reqs0 <- replicateM(mkSizedFIFOF(3));
     
     // stage 2 (latency == 1)
     Vector#(2,FIFOF#(Tuple4#(Bool,Bool,Bool,Bool))) conds <- replicateM(mkFIFOF);
     Vector#(2,FIFOF#(Tuple4#(Bit#(IndexWidth),Bit#(IndexWidth),Bit#(IndexWidth),Bit#(IndexWidth)))) idxOffsets0 <- replicateM(mkFIFOF);
     Vector#(2,FIFOF#(ReqTup))           reqs1 <- replicateM(mkSizedFIFOF(3));
  
     // stage 3 (latency == 1)
     Vector#(2,FIFOF#(Offset))           offs0 <- replicateM(mkFIFOF);
  
negative.code: 				     regionall.reg8.barrier, regionall.reg4.barrier, regionall.reg0.barrier,
  				     off8, off4, off0);
  	       
  	       stage3Params[i].enq(Stage3Params {cond12: cond12, cond8: cond8, cond4: cond4, cond0: cond0,
  						 idxOffset12: regionall.reg12.idxOffset,idxOffset8: regionall.reg8.idxOffset,
  						 idxOffset4: regionall.reg4.idxOffset, idxOffset0: regionall.reg0.idxOffset,
  						 req: req });
  	    end
  	    tagged Invalid:
  	       dmaErrorFifo.enq(DmaError { errorType: DmaErrorSGLIdInvalid, pref: extend(req.id), off:req.off });
  	 endcase
        endrule
        rule stage3; // Based on results of comparision, select a region, putting it into 'o.pageSize'.  idxOffset holds offset in sglist table of relevant entry
  	 let params <- toGet(stage3Params[i]).get();
  	 ReqTup req = params.req;
  	 Offset o = Offset{pageSize: 0, value: truncate(req.off)};
  	 Bit#(IndexWidth) pbase = 0;
  	 Bit#(IndexWidth) idxOffset = 0;
  
  	 if (params.cond12) begin
  	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
  	    o.pageSize = 4;
  	    pbase = truncate(req.off>>page_shift12);
  	    idxOffset = params.idxOffset12;
  	 end
  	 else if (params.cond8) begin
  	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
  	    o.pageSize = 3;
  	    pbase = truncate(req.off>>page_shift8);
  	    idxOffset = params.idxOffset8;
  	 end
  	 else if (params.cond4) begin
  	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
  	    o.pageSize = 2;
  	    pbase = truncate(req.off>>page_shift4);
  	    idxOffset = params.idxOffset4;
  	 end
  	 else if (params.cond0) begin
  	    if (verbose) $display("mkMMU::request: req.id=%h req.off=%h", req.id, req.off);
  	    o.pageSize = 1;
  	    pbase = truncate(req.off>>page_shift0);
  	    idxOffset = params.idxOffset0;
  	 end
  	 offs0[i].enq(o);
  	 pbases[i].enq(pbase);
  