anchor.diff:     Reset reset_high <- invertCurrentReset;
      Reset npor = perst_n; //No soft reset signal from Application
   
  -   PcieS5Wrap#(12, 32, 128) pcie_ep <- mkPcieS5Wrap(clk_100MHz, clk_50MHz, npor, perst_n);
  +`ifdef BOARD_de5
  +   PcieWrap#(12, 32, 128) pcie_ep <- mkPcieS5Wrap(clk_100MHz, clk_50MHz, npor, perst_n);
  +`elsif BOARD_htg4
  +   PcieWrap#(12, 32, 128) pcie_ep <- mkPcieS4Wrap(clk_100MHz, clk_50MHz, clk_100MHz, npor, perst_n);
  +`endif
   
      Clock core_clk = pcie_ep.coreclkout_hip;
      Reset core_reset = pcie_ep.core_reset;
  
positive.code:       pcie_ep.tx_st.sop(info.sop);
        pcie_ep.tx_st.eop(info.eop);
        let txStEmpty = getTxStEmpty(info.be);
        pcie_ep.tx_st.empty(txStEmpty);
        pcie_ep.tx_st.err(0);
        pcie_ep.tx_st.data(info.data);
     endrule
  
negative.code: import Real              ::*;
  
  import PCIE              ::*;
  
  `ifdef BOARD_de5
  import PS5LIB            ::*;
  //import PcieEndpointS5Test ::*;
  `elsif BOARD_htg4
  import PS4LIB            ::*;
  `endif
  
  (* always_ready, always_enabled *)
  interface PciewrapPci_exp#(numeric type lanes);
  