anchor.diff:          serbvi.train8(trainrot[8]);
           serbvi.train9(trainrot[9]);
       endrule
  +    rule clkdivreset_rule if (bvi_resets_reg.read() != 0);
  +        dfifo_reset_r.send(serbvi.align_busy());
  +    endrule
  +    rule qfsmreset_rule if (bvi_resets_reg.read() == 0);
  +        this_aligned_reg <= 0;
  +        qstate <= QIdle;
  +        serdes_counter <= 0;
  +        //ctrl_sample <= 0;
  +        this_start_align_reg <= 0;
  +    endrule
  +    rule qfsmall;
  +        //serbvi.start_align_i(this_start_align_reg);
  +        //dfifo_reset_r.send(this_start_align_reg);
  +        //samplein_reset_null.send(ctrl_sample[2]);
  +        ctrl_sample <= serbvi.samplein();
  +    endrule
  +    rule qfsm_rule if (bvi_resets_reg.read() != 0);
  +        let qs = qstate;
  +        let scount = serdes_counter;
  +        let sa = 0;
  +        if (qstate == QIdle && align_start == 1)
  +            begin
  +            scount = 0;
  +            sa = 1;
  +            qs = QTrain;
  +            end
  +        if (qstate == QTrain)
  +            qs = QOn;
  +        if (qstate == QOn && serbvi.busy_align_i() == 1)
  +            qs = QOff;
  +        if (qstate == QOff && serbvi.busy_align_i() == 0)
  +            begin
  +            //ctrl_sample <= serbvi.samplein();
  +            if (serdes_counter >= 'h8000)
  +                begin
  +                this_aligned_reg <= 1;
  +                qs = QIdle;
  +                end
  +            else
  +                begin
  +                scount = scount + 1;
  +                sa = 1;
  +                qs = QTrain;
  +                end
  +            end
  +        qstate <= qs;
  +        serdes_counter <= scount;
  +        this_start_align_reg <= sa;
  +    endrule
   
       rule reset_clock_rule;
           bvi_resets_reg.send(bvi_reset_reg);
  
positive.code:     Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      ReadOnly#(Bit#(3)) samplein_null <- mkNullCrossingWire(serdes_clock, serbvi.samplein());
  
      SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);
  
negative.code:     method CTRL_RESET_INC_CE ctrl_reset_inc_ce() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method                  endhandshake(end_handshake) enable((*inhigh*) en20) clocked_by(clock);
      method start_handshake starthandshake();
      method busy_align_o busy_align_i();
      method                  start_align_i(start_align_o) enable((*inhigh*) en22) clocked_by(clock);
      schedule (busy_align_i, start_align_i, train0, train1, train2, train3, train4, train5, train6, train7, train8, train9,
                edgeintor, edgeint, endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap)
           CF (busy_align_i, start_align_i, train0, train1, train2, train3, train4, train5, train6, train7, train8, train9,
                edgeintor, edgeint, endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap);
  endmodule: mkIserdesbvi
  
  