anchor.diff:  
       FIFOF#(TLPData#(16)) tlpOutFifo <- mkFIFOF;
       FIFOF#(TLPData#(16)) tlpInFifo <- mkFIFOF;
  -    FIFOF#(TLPData#(16)) tlpWriteHeaderFifo <- mkFIFOF;
  +    FIFO#(TLPData#(16)) tlpWriteHeaderFifo <- mkFIFO;
  +    FIFO#(TLPLength)      writeDwCountFifo <- mkFIFO;
  +    FIFO#(Bool)             writeIs3dwFifo <- mkFIFO;
   
       Reg#(Bit#(7)) hitReg <- mkReg(0);
       Reg#(Bool) use4dwReg <- mkReg(True);
  
positive.code: 	      let burstLen = req.burstLen >> beat_shift;
  	      let addr = req.addr;
  	      let awid = req.tag;
  
  	      TLPLength tlplen = fromInteger(valueOf(busWidthWords))*(extend(burstLen));
  	      TLPData#(16) tlp = defaultValue;
  
negative.code:     endfunction
  
     rule writeHeaderTlp if (!writeInProgress && writeDataMimo.deqReadyN(1));
        let tlp <- toGet(tlpWriteHeaderFifo).get();
        let dwCount <- toGet(writeDwCountFifo).get();
        let is3dw <- toGet(writeIs3dwFifo).get();
  
        TLPMemory4DWHeader hdr_4dw = unpack(tlp.data);
  
        TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);
        if (is3dw) begin
  	 if (hdr_3dw.format != MEM_WRITE_3DW_DATA)
  	    $display("MemSlaveEngine: expecting MEM_WRITE_3DW_DATA, got %d", hdr_3dw.format);
  	 Vector#(4, Bit#(32)) v = writeDataMimo.first();
  	 writeDataMimo.deq(1);
  	 hdr_3dw.data = byteSwap(v[0]);
  