anchor.diff:     endinterface
      interface MemReadServer read_server;
         interface Put readReq;
  -         method Action put(MemRequest#(40) req) if (!writeInProgress && !writeDataMimo.deqReady());
  +         method Action put(MemRequest#(40) req);
   	    readReqFifo.enq(req);
            endmethod
          endinterface
  
positive.code:     interface MemSlave slave;
     interface MemWriteServer write_server; 
        interface Put writeReq;
           method Action put(MemRequest#(40) req);
  	    writeReqFifo.enq(req);
           endmethod
  	endinterface
        interface Put writeData;
  
negative.code:       end
     endrule
  
     FIFO#(MemRequest#(40)) readReqFifo <- mkFIFO();
     rule readReqRule if (!writeInProgress && !writeDataMimo.deqReady());
        let req <- toGet(readReqFifo).get();
        let burstLen = req.burstLen >> beat_shift;
        let addr = req.addr;
  