anchor.diff:  	    serdes_training_reg <= v;
   	endmethod
   	method Action set_iserdes_control(Bit#(32) v);
  -	    serdes_reset_reg <= v[0];
  +	    serdes_reset_reg <= ~v[0];
   	    serdes_auto_align_reg <= v[1];
   	    serdes_align_start_reg <= v[2];
   	    serdes_fifo_enable_reg <= v[3];
  
positive.code:         ibufds_v[i] <- mkIBUFDS(vita_data_p[i], vita_data_n[i]);
      Vector#(5, IserdesDatadeser) serdes_v <- replicateM(mkIserdesDatadeser(serdes_clock, serdest_clk.gen_clk));
  
      Reg#(Bit#(1)) vita_reset_n_o <- mkReg(0);
      Wire#(Bit#(1)) zero_wire <- mkDWire(0);
      Wire#(Bit#(1)) one_wire <- mkDWire(1);
      Wire#(Bit#(1)) trigger_wire <- mkDWire(0);
      Vector#(3, ReadOnly#(Bit#(1))) vita_trigger_wire;
      vita_trigger_wire[2] <- mkOBUFT(zero_wire, imageon_oe);
      vita_trigger_wire[1] <- mkOBUFT(one_wire, imageon_oe);
      vita_trigger_wire[0] <- mkOBUFT(trigger_wire, imageon_oe);
      ReadOnly#(Bit#(1)) vita_reset_n_wire <- mkOBUFT(vita_reset_n_o, imageon_oe);
  
      Reg#(Bit#(1)) serdes_align_busy_temp <- mkReg(0);
      Reg#(Bit#(1)) serdes_align_busy_reg <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);
  
negative.code: 
      rule sendup_sdes_clock;
      for (Bit#(8) i = 0; i < 5; i = i+1) begin
         serdes_v[i].wren.reset(~serdes_reset_null);
         serdes_v[i].wren.delay_wren(delay_wren_c_reg);
         serdes_v[i].wren.fifo_wren(serdes_fifo_enable_null);
      end
      endrule
      
      rule serdes_reset_rule if (serdes_reset_reg == 0);
          new_raw_empty_wire <= 0;
          delay_wren_r_reg <= 0;
          delay_wren_r2_reg <= 0;
      endrule
  
      rule serdes_resetc_rule if (serdes_reset_null == 0);
          delay_wren_c_reg <= 0;
          fifo_wren_r2_reg <= 0;
          fifo_wren_c_reg <= 0;
      endrule
  
      rule serdes_calc2 if (serdes_reset_reg == 1);
          new_raw_empty_wire <= empty_wire;
          delay_wren_r_reg <= bittest_wire;
          delay_wren_r2_reg <= delay_wren_r_reg;
      endrule
  
      rule serdes_calc2c if (serdes_reset_null == 1);
          delay_wren_c_reg <= delay_wren_r2_reg;
          fifo_wren_r2_reg <= serdes_fifo_enable_null;
          fifo_wren_c_reg <= fifo_wren_r2_reg;
  