anchor.diff:  typedef enum { HIdle, HHigh, HLow} HState deriving (Bits,Eq);
   
   module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
  -    Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden)(IserdesDatadeser);
  +    Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden, TrainRotate trainrot)(IserdesDatadeser);
   
       Clock defaultClock <- exposeCurrentClock();
       Reset defaultReset <- exposeCurrentReset();
  
positive.code:         iodelay_reset_inc_ce <= sync_reset_inc_ce;
      endrule
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
          let ds = dstate;
          let dc = dcounter;
  
negative.code:     Reg#(Bit#(6)) hcounter <- mkReg(0);
      Reg#(Bit#(1)) edge_intor_reg <- mkReg(0);
      SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  
      rule trainrot_rule;
          serbvi.train0(trainrot[0]);
          serbvi.train1(trainrot[1]);
          serbvi.train2(trainrot[2]);
  