anchor.diff:  	     Add#(c__, dsz, 256),
   	     Add#(d__, TMul#(8, TDiv#(dsz, 32)), 64),
   	     Add#(e__, TMul#(32, TDiv#(dsz, 32)), 256),
  -	     Add#(f__, TDiv#(dsz, 32), 8)
  +	     Add#(f__, TDiv#(dsz, 32), 8),
  +	     Mul#(TDiv#(dsz, 8), 8, dsz)
         );
   
      let contentId = 0;
  
positive.code: 
  
  (* synthesize *)
  module mkSynthesizeablePortalTop#(Clock clock200, Clock io_vita_clk)(PortalTop#(40, 64, ImageonVita));
     let top <- mkPortalTop(clock200, io_vita_clk);
     interface ctrl = top.ctrl;
     interface read_client = top.read_client;
     interface write_clinet = top.write_client;
     interface interrupt = top.interrupt;
     interface leds = top.leds;
     interface pins = top.pins;
  
negative.code:    X7PcieSplitter#(PcieLanes) x7pcie <- mkX7PcieSplitter(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n,
  							 contentId );
     
     // instantiate user portals
     Clock io_vita_clk <- XilinxCells::mkClockIBUFDS(io_vita_clk_out_p, io_vita_clk_out_n);
     let portalTop <- mkPortalTop(x7pcie.clock200, io_vita_clk, clocked_by x7pcie.clock125, reset_by x7pcie.portalReset);
  