anchor.diff:  
      function Action fa_finish_cond_branch(Bool condition_taken, Addr next_pc);
         action
  -         pc[1]    <= (condition_taken ? next_pc : fv_fall_through_pc(pcEpoch));
  +         if (condition_taken) begin
  +            pc[1] <= next_pc;
  +         end
            pcEpoch  <= (condition_taken ? next_pc : fv_fall_through_pc(pcEpoch));
         endaction
      endfunction
  
positive.code:          end
        endcase
  
        if (cfg_verbose > 1) $display("[%7d] rl_write : %s = %h, clear scoreGPRs[%1d] (= %1d)", csr_cycle, regNameABI[rd], rd_value, rd, rg_scoreGPRs[rd][0] ? 1 : 0);
  
        // NOTE: DOES NOT check register x0 because set value to Zero when read
        rf_GPRs.upd(rd, rd_value);
        rg_scoreGPRs[rd][0] <= False;
     endrule
  
  
  
negative.code:    // ================================================================
     // The CPU's top-level logic
  
     (* fire_when_enabled, no_implicit_conditions *)
     rule update_score;
        let x = fromMaybe(0, rw_scoreGPRsSet.wget);
        let y = fromMaybe(0, rw_scoreGPRsReset.wget);
  
        rg_scoreGPRs[x] <= True;
        if (x != y) begin
           rg_scoreGPRs[y] <= False;
        end
     endrule
  
     // ---------------- FETCH
     // Issue instruction request and decode
  
     // ----------------------------------------------------------------
     // Instruction fetch
     (* fire_when_enabled *)
     rule rl_fetch(cpu_enabled);
        if (cfg_verbose > 1) $display("[%7d] rl_fetch : Read instruction pc = 0x%08h", csr_cycle, pc[2]);
        memory.imem_req(pc[2]);
  