anchor.diff:        let request <- toGet(clientRequest).get();
         let physAddr <- mmus[request.req.sglId[31:16]].response.get;
         let rename_tag <- tag_gen.getTag;
  +      
         serverRequest.enq(RRec{req:request.req, pa:physAddr, client:request.client, rename_tag:extend(rename_tag)});
         if (verbose) $display("mkMemReadInternal::checkMmuResp: client=%d, rename_tag=%d", request.client,rename_tag);
         if (verbose) $display("mkMemReadInternal::mmuResp %d %d", request.client, cycle_cnt-last_mmuResp);
  
positive.code:       Bit#(MemTagSize) response_tag = response.tag;
        let drq <- serverProcessing.portA.response.get;
        let otag = drq.req_tag;
        let burstLen = burstReg;
        let first =    firstReg;
        let last  =    lastReg;
        if (first) begin
  	 burstLen = drq.req_burstLen >> beat_shift;
  	 last = drq.last;
  	 dynamicAssert(last == (burstLen==1), "Last incorrect");
        end
        Bit#(TLog#(numTags)) tt = truncate(response_tag);
        clientData.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last}, address:{tt,truncate(burstLen)}});
        if (last) begin
  	 tag_gen.returnTag(truncate(response_tag));
        end
        last_readData <= cycle_cnt;
        if (verbose) $display("mkMemReadInternal::read_data cyclediff %d", cycle_cnt-last_readData);
        burstReg <= burstLen-1;
        firstReg <= burstLen-1 == 0;
        lastReg  <= burstLen-1 == 1;
     endrule
  
  
negative.code:    
     let verbose = False;
     
     RegFile#(Bit#(5),Bit#(BurstLenSize)) clientBurstLen <- mkRegFileFull();
     Reg#(Bit#(BurstLenSize)) burstReg <- mkReg(0);
     Reg#(Bool)               firstReg <- mkReg(True);
     Reg#(Bool)                lastReg <- mkReg(False);
  