anchor.diff:                Bit#(buswidth) v = 0;
                 for (Integer i = 0; i < valueOf(busWidthWords); i = i+1) begin
   `ifdef AXI
  +`ifdef PCIE3
  +		 v[(i+1)*32-1:i*32] = data_v[i];
  +`else
   		 v[(i+1)*32-1:i*32] = byteSwap(data_v[i]);
  +`endif
   `elsif AVALON
   		 v[(i+1)*32-1:i*32] = data_v[i];
   `endif
  
positive.code: 	    tlp.be = 16'hffff;
  
  	    $display("slave.writeAddr tlplen=%d burstLen=%d", tlplen, burstLen);
  	    if ((addr >> 32) != 0) begin
  	       TLPMemory4DWHeader hdr_4dw = defaultValue;
  	       hdr_4dw.format = MEM_WRITE_4DW_DATA;
  	       hdr_4dw.tag = extend(awid);
  
negative.code: 
        for (Integer i = 0; i < currDwCount; i = i + 1) begin
  `ifdef AXI
  `ifdef PCIE3
  	 tlp.data[(i+1)*32-1:i*32] = v[i];
  `else
  	 tlp.data[(i+1)*32-1:i*32] = byteSwap(v[(currDwCount-1)-i]);
  `endif
  `elsif AVALON
  	 tlp.data[(i+1)*32-1:i*32] = v[(currDwCount-1)-i];
  `endif
        end
  
        tlpOutFifo.enq(tlp);
     endrule: writeTlps
  
     Reg#(TLPTag) lastTag <- mkReg(0);
     FIFOF#(TLPData#(16)) tlpDecodeFifo <- mkFIFOF();
  