anchor.diff:          slave_data.oclkb(0);
           slave_data.reset(iodelay_reset_inc_ce[2]);
       endrule
  +
       rule serdesda2_rule;
           let dout = {slave_data.q4(), slave_data.q3(), master_data.q8(),
              master_data.q7(), master_data.q6(), master_data.q5(),
  
positive.code:             astate <= AStart;
          else
              begin
              start_handshake.enq(1);
              ctrl_reset_inc_ce <= 3'b011;
              gencounter <= gencounter - 1;
              end
  
negative.code:     schedule (reset, di, rden, wren, dataout, empty) CF (reset, di, rden, wren, dataout, empty);
  endmodule: mkFIFO18
  
  typedef enum { DIdle, DValid} DState deriving (Bits,Eq);
  typedef enum { QIdle, QTrain, QOn, QOff} QState deriving (Bits,Eq);
  typedef enum { AIdle, ADelay, AWDelay, AEdge, ACEdge, AWait, ACompare, AValid,
       A1Changed, A1Stable, ASecond, AFound, AResetman, AStart, AAlign, ADone } AState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden, TrainRotate trainrot)(IserdesDatadeser);
  