anchor.diff:  //(* synthesize *)
   module mkMemInterrupt#(PciId my_id)(MemInterrupt);
       FIFOF#(InterruptRequest) interruptRequestFifo <- mkFIFOF();
  +    FIFOF#(InterruptRequest) interruptTraceFifo <- mkSizedFIFOF(4);
       Reg#(Maybe#(Bit#(32))) interruptSecondHalf <- mkReg(tagged Invalid);
       Reg#(TLPTag) tlpTag <- mkReg(0);
       FIFOF#(TLPData#(16)) tlpOutFifo <- mkSizedFIFOF(8);
  
positive.code: 	  interruptSecondHalf <= tagged Valid interruptData;
         end
  
         if (!interruptRequested)
  	  interruptRequestFifo.deq();
         if (sendInterrupt)
  	  tlpOutFifo.enq(tlp);
      endrule
  
negative.code: 	  match { .addr, .data } = intr;
  	  Bool mswIsZero = (addr[63:32] == 0);
  	  Bool lswIsZero = (addr[31:0] == 0);
  	  let interruptRequest = InterruptRequest { addr: addr, data: data, mswIsZero: mswIsZero, lswIsZero: lswIsZero };
            interruptRequestFifo.enq(interruptRequest);
  	  if (interruptTraceFifo.notFull())
  	      interruptTraceFifo.enq(interruptRequest);
         endmethod
      endinterface
      interface Get interruptTrace;
         method ActionValue#(Tuple2#(Bit#(64),Bit#(32))) get();
             let req = interruptTraceFifo.first();
             interruptTraceFifo.deq();
  	   return tuple2(req.addr, req.data);
         endmethod
      endinterface
  endmodule: mkMemInterrupt
  