anchor.diff:     Reg#(Bool)     readyReg   <- mkReg(False);
   
      if (valueOf(numRequests) > 0) begin
  -      let readPortal <- mkSharedMemoryRequestPortal(portal, readEngine, writeEngine, sglIdReg, readyReg);
  +      let readPortal <- mkSharedMemoryRequestPortal(portal, readEngine.read_servers[0], writeEngine.write_servers[0], sglIdReg, readyReg);
      end
      if (valueOf(numIndications) > 0) begin
      end
  
positive.code:    } SharedMemoryPortalState deriving (Bits,Eq);
  
  module mkSharedMemoryRequestPortal#(PipePortal#(numRequests, numIndications, 32) portal,
  				    MemreadEngineV#(64,n,m) readEngine,
  				    MemwriteEngineV#(64,2,2) writeEngine,
  				    Reg#(Bit#(32)) sglIdReg,
  				    Reg#(Bool)     readyReg)(SharedMemoryPortal#(64));
        // read the head and tail pointers, if they are different, then read a request
  
negative.code: 
  	 reqTailReg <= tail;
  	 wordCountReg <= truncate(wordCount);
  	 readEngine.cmdServer.request.put(MemengineCmd {sglId: sglIdReg,
  							base: extend(reqTailReg << 2),
  							burstLen: 16,
  							len: wordCount << 2
  							});
  	 reqState <= MessageHeaderRequested;
        endrule
  
        MIFO#(4,1,4,Bit#(32)) readMifo <- mkMIFO();
        rule demuxwords if (readMifo.enqReady());
  	 let data <- toGet(readEngine.dataPipe).get();
  	 Vector#(2,Bit#(32)) dvec = unpack(data);
  	 let enqCount = 2;
  	 Vector#(4,Bit#(32)) dvec4;
  