anchor.diff:  
      Vector#(np, Wire#(Bit#(1))) rx_serial_wires <- replicateM(mkDWire(0));
   
  +   function Bit#(1) getBit(Bit#(n) data, Integer i);
  +      return data[i];
  +   endfunction
  +
      interface tx_clkout = out_tx_clk;
      interface rx_clkout = out_rx_clk;
   
      interface Status status;
         method Vector#(np, Bit#(1)) rx_ready();
  -         Vector#(np, Bit#(1)) ret_val;
  -         for(Integer i=0; i< valueOf(np); i=i+1) begin
  -            ret_val[i] = rst.rx.ready[i];
  -         end
  +         Vector#(np, Bit#(1)) ret_val = map(getBit(rst.rx.ready), genVector);
            return ret_val;
         endmethod
   
         method Vector#(np, Bit#(1)) tx_ready();
  -         Vector#(np, Bit#(1)) ret_val;
  -         for(Integer i=0; i< valueOf(np); i=i+1) begin
  -            ret_val[i] = rst.tx.ready[i];
  -         end
  +         Vector#(np, Bit#(1)) ret_val = map(getBit(rst.tx.ready), genVector);
            return ret_val;
         endmethod
   
         method Vector#(np, Bit#(1)) pll_locked();
  -         Vector#(np, Bit#(1)) ret_val;
  -         for(Integer i=0; i< valueOf(np); i=i+1) begin
  -            ret_val[i] = xcvr.pll.locked[i];
  -         end
  +         Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.pll.locked), genVector);
            return ret_val;
         endmethod
   
         method Vector#(np, Bit#(1)) rx_is_lockedtodata();
  -         Vector#(np, Bit#(1)) ret_val;
  -         for(Integer i=0; i< valueOf(np); i=i+1) begin
  -            ret_val[i] = xcvr.rx.is_lockedtodata[i];
  -         end
  +         Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtodata), genVector);
            return ret_val;
         endmethod
   
         method Vector#(np, Bit#(1)) rx_is_lockedtoref();
  -         Vector#(np, Bit#(1)) ret_val;
  -         for(Integer i=0; i< valueOf(np); i=i+1) begin
  -            ret_val[i] = xcvr.rx.is_lockedtoref[i];
  -         end
  +         Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtoref), genVector);
            return ret_val;
         endmethod
      endinterface
  
positive.code: 
  interface Serial#(numeric type np);
     method Bit#(np)    tx_serial_data;
  `ifdef USE_4_PORTS
     method Action      rx_serial_data(Bit#(4) v);
  `elsif USE_2_PORTS
     method Action      rx_serial_data(Bit#(2) v);
  `endif
  endinterface
  
  interface Parallel#(numeric type np);
     method Vector#(np, Bit#(40)) rx_parallel_data;
  `ifdef USE_4_PORTS
     method Action                tx_parallel_data(Vector#(np, Bit#(40)) v);
  `elsif USE_2_PORTS
     method Action                tx_parallel_data(Vector#(np, Bit#(40)) v);
  `endif
  endinterface
  
  (* always_ready, always_enabled *)
  
negative.code:    interface Parallel#(np)      parallel;
  endinterface
  
  module mkEthPma#(Clock phy_mgmt_clk, Clock pll_ref_clk, Reset phy_mgmt_reset, Reset pll_ref_reset)(EthPmaIfc#(np)) provisos (Add#(np, unused, 4));
  
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  