anchor.diff:  	     ttd[31+(3*32):0+(3*32)] = tlpDataScratchpad[3];
   	     ttd[31+(4*32):0+(4*32)] = tlpDataScratchpad[4];
   	     ttd[24+(5*32):0+(5*32)] = tlpDataScratchpad[5][24:0];
  -	     tlpDataBram1Port.portA.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(tpl_2(value[0])),
  +	     bscanBram.server.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(tpl_2(value[0])),
   	                                                     datain: unpack(ttd)});
            end else if ((addr % 8192) == 795) begin
   					       portalResetIfc.assertReset();
  
positive.code:    interface ReadOnly#(Bit#(32)) interruptData;
  
     interface Reg#(Bool)     tlpTracing;
     interface Reg#(Bit#(32)) tlpTraceLimit;
     interface Reg#(Bool) use4dw;
     interface Reg#(Bit#(32)) tlpDataBramWrAddr;
     interface Reg#(Bit#(32)) tlpOutCount;
     interface BRAMServer#(Bit#(11), TimestampedTlpData) tlpDataBram;
  endinterface: ControlAndStatusRegs
  
  // This module encapsulates all of the logic for instantiating and
  
negative.code: import XbsvXilinx7Pcie      :: *;
  //import XbsvXilinx7DDR3      :: *;
  import Portal               :: *;
  import Bscan                :: *;
  
  typedef 11 TlpTraceAddrSize;
  
  typedef struct {
      Bit#(32) timestamp;
  