anchor.diff:  	    return d.data;
   	endmethod
   	method Bit#(busWidthBytes) writeDataByteEnable();
  -	    return maxBound;
  +	    return wWriteData.byteEnable;
   	endmethod
   	method Bit#(1) writeLastDataBeat(); // last data beat
   	    return wWriteData.last;
   	endmethod
   
   	method Action writeResponse(Bit#(2) responseCode, Bit#(idWidth) id);
  -	    client.write.response(Axi3WriteResponse { response: responseCode, id: id});
  +	    client.write.response(Axi3WriteResponse { code: responseCode, id: id});
   	endmethod
       endinterface
   
  
positive.code: 	method Bit#(idWidth) readId();
  	    return wReadRequest.id;
  	endmethod
  	method Action readData(Bit#(busWidth) data, Bit#(2) resp, Bit#(1) last, Bit#(idWidth) id);
  	    client.read.data(Axi3ReadResponse { data: data, resp: resp, last: last, id: id});
  	endmethod
     endinterface
  endmodule
  
negative.code:     endrule
  endmodule
  
  module mkClientSlaveConnection#(Axi3WriteClient#(busWidth, busWidthBytes,idWidth) axicw,
                                  Axi3ReadClient#(busWidth,idWidth) axicr,
                                  Axi3Slave#(busWidth, busWidthBytes) axiSlave)
                                  () provisos (Div#(busWidth, 8, busWidthBytes),
  				             Add#(1, a__, busWidth),
  					     Add#(busWidth, b__, 65),
  					     Add#(idWidth, 1, 13));
         
      Reg#(Bit#(8)) writeBurstCountReg <- mkReg(0);
      Bool verbose = False;
  
      Axi3Client#(busWidth,busWidthBytes,idWidth) axic <- mkAxi3Client(axicw, axicr);
      Axi3Master#(busWidth,busWidthBytes,idWidth) m_axiMaster <- mkAxi3Master(axic);
      let axir = m_axiMaster.read;
      let axiw = m_axiMaster.write;
  
      rule readAddr;
          Bit#(32) addr <-axir.readAddr;
          let burstLen = axir.readBurstLen;
          let burstWidth = axir.readBurstWidth;
          let burstType = axir.readBurstType;
          let burstProt = axir.readBurstProt;
          let burstCache = axir.readBurstCache;
  	let id = axir.readId;
          axiSlave.read.readAddr(addr, burstLen, burstWidth, burstType, burstProt, burstCache, id);
  	if (verbose) $display("        MasterSlaveConnection.readAddr %h %d", addr, burstLen+1);
      endrule
      rule readData;
          let data <- axiSlave.read.readData();
  	let id = axiSlave.read.rid();
          axir.readData(data, 2'b00, 0, id);
          if (verbose) $display("        MasterSlaveConnection.readData %h", data);
      endrule
      rule writeAddr;
          Bit#(32) addr <- axiw.writeAddr;
          let burstLen = axiw.writeBurstLen;
          let burstWidth = axiw.writeBurstWidth;
          let burstType = axiw.writeBurstType;
          let burstProt = axiw.writeBurstProt;
          let burstCache = axiw.writeBurstCache;
  	let id = axiw.writeId;
          axiSlave.write.writeAddr(addr, burstLen, burstWidth, burstType, burstProt, burstCache, id);
          if (verbose) $display("        MasterSlaveConnection.writeAddr %h %d", addr, burstLen+1);
      endrule
      rule writeData;
          let data <- axiw.writeData;
          let byteEnable = axiw.writeDataByteEnable;
          let last = axiw.writeLastDataBeat;
          axiSlave.write.writeData(data, byteEnable, last);
          if (verbose) $display("        MasterSlaveConnection.writeData %h", data);
      endrule
      rule writeResponse;
          let response <- axiSlave.write.writeResponse();
          let id <- axiSlave.write.bid();
          axiw.writeResponse(response, id);
      endrule
  endmodule
  
  module mkAxi3MasterWires#(Axi3Client#(busWidth,busWidthBytes,idWidth) client)(Axi3Master#(busWidth,busWidthBytes,idWidth))
  	 provisos(Div#(busWidth,8,busWidthBytes),Add#(1,a,busWidth));
  
      Wire#(Axi3ReadRequest#(idWidth))                      wReadRequest <- mkDWire(unpack(0));
  