anchor.diff:     endinterface
   endmodule
   
  -module mkPhysMemToBramBE#(BRAMServerBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), n) br) (PhysMemSlave#(busAddrWidth, busDataWidth))
  +module mkPhysMemToBramBE#(BRAMServerBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), dataWidthBytes) br) (PhysMemSlave#(busAddrWidth, busDataWidth))
      provisos(Add#(a__, bramAddrWidth, busAddrWidth)
  -           ,Mul#(n, 8, busDataWidth)
  -           ,Div#(busDataWidth, 8, n)
  +           ,Mul#(dataWidthBytes, 8, busDataWidth)
  +           ,Div#(busDataWidth, 8, dataWidthBytes)
              );
   
      FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();
  
positive.code: 	    readTagFifo.deq;
  	    readLastFifo.deq;
              let data <- br.response.get;
              let byteEnable <- toGet(readByteEnableFifo).get();
              let newdata = updateDataWithMask(0, data, byteEnable);
              if (verbose) $display("%d read_server.readData (b) %h, %h", cycles, data, newdata);
              return MemData { data: newdata, tag: tag, last: readLastFifo.first };
  	 endmethod
        endinterface
  
negative.code:       let burstCount = addrBeat.bc;
        readTagFifo.enq(tag);
        readLastFifo.enq(addrBeat.last);
        Bit#(bramAddrWidth) regFileAddr = truncate(addr << fromInteger(valueOf(TLog#(dataWidthBytes))));
        br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:regFileAddr, datain:?});
        if (verbose) $display("%d read_server.readData (a) %h %d last=%d", cycles, addr, burstCount, addrBeat.last);
     endrule
  