anchor.diff:  	 interface Put readData;
   	    method Action put(MemData#(dataBusWidth) md);
   	       busReadDataFifo.enq(md);
  -	       busReadDataData <= md.data;
  -	       busReadDataLast <= md.last;
   	    endmethod
   	 endinterface
         endinterface
  
positive.code: 	 bramReadReqFifo.enq(req);
        else
  	 busReadReqFifo.enq(req);
        readAddrGenerator.request.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen, tag: extend(dest) });
  
        readReqObj <= req.sglId;
        readReqDest <= dest;
        readReqOffset <= req.offset[31:0];
     endrule
  
     rule rl_rd_data;
        let addrBeat <- readAddrGenerator.addrBeat.get();
        let dest = addrBeat.tag[1:0];
        MemData#(dataBusWidth) md;
        if (dest == 2)
  	 md <- toGet(bramReadDataFifo).get();
        else
  	 md <- toGet(busReadDataFifo).get();
        readDataFifo.enq(md);
  
        readDataDest <= dest;
        readDataData <= md.data;
        readDataLast <= md.last;
        readBeatAddr <= addrBeat.addr[15:0];
        readBeatByteCount <= addrBeat.bc;
        readBeatLast <= addrBeat.last;
     endrule
  
     rule rl_wr_req;
  
negative.code:    let doneFifo <- mkFIFOF();
  
     let dataFifo <- mkSizedBRAMFIFOF(4096);
     let readDestFifo <- mkFIFOF();
     let writeDestFifo <- mkFIFOF();
  
     rule rl_rd_req;
        MemRequest req <- toGet(readReqFifo).get();
  