anchor.diff:  import DefaultValue::*;
   import XilinxCells::*;
   import GetPut::*;
  +import ConnectalConfig::*;
   import AxiBits::*;
   import AxiStream::*;
   
  
positive.code: endfunction
  endinstance
  
  instance ToAxi4MasterBits#(Axi4MasterBits#(32,32,tagWidth,Empty), AxidmabviM_axi_sg);
  function Axi4MasterBits#(32,32,tagWidth,Empty) toAxi4MasterBits(AxidmabviM_axi_sg m);
     return (interface Axi4MasterBits#(32,32,tagWidth,Empty);
      method araddr = m.araddr;
        method arburst = m.arburst;
        method arcache = m.arcache;
  
negative.code: 	   method rready = m.rready;
  	   method rresp = m.rresp;
  	   method rvalid = m.rvalid;
  	   method Bit#(DataBusWidth)     wdata(); return 0; endmethod
  	   method Bit#(tagWidth)     wid(); return 0; endmethod
  	   method Bit#(1)     wlast(); return 0; endmethod
  	   method Action      wready(Bit#(1) v); endmethod
  	   method Bit#(TDiv#(DataBusWidth,8))     wstrb(); return 0; endmethod
  	   method Bit#(1)     wvalid(); return 0; endmethod
  	 interface extra = ?;   
  	 endinterface);
     endfunction
  endinstance
  
  instance ToAxi4MasterBits#(Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty), AxidmabviM_axi_s2mm);
  function Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty) toAxi4MasterBits(AxidmabviM_axi_s2mm m);
     return (interface Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty);
      method Bit#(32)     araddr(); return 0; endmethod
      method Bit#(2)     arburst(); return 0; endmethod
      method Bit#(4)     arcache(); return 0; endmethod
  