anchor.diff:  
   interface ProcVerilator;
       // Processor Control
  -    method Action start(Bit#(64) startPc);
  +    method Action start();
       method Action stop();
       method Action stallPipeline(Bool stall);
   
  
positive.code:     // connect the processor to the simRam
      mkConnection(proc.ram, simRam);
  
      rule tieOff;
          proc.pins.spi.miso(0);
      endrule
  
      Reg#(Bit#(16)) uartDivisor <- mkReg(17);
      UART#(16) simUart <- mkUART(8, NONE, STOP_1, uartDivisor);
      let uartSimToFPGABridge <- mkConnection(toPut(proc.pins.uart.sin), toGet(simUart.rs232.sout));
  
negative.code:         let x <- simUart.tx.get();
          $write("%c", x);
      endrule
  `endif
  
      // Processor Control
      method Action start;
          proc.start;
      endmethod
      method Action stop();
          proc.stop;
  