anchor.diff:  // defined by user
   import Memread::*;
   
  -interface Top;
  +interface AxiTop;
      interface StdAxi3Slave     ctrl;
      interface StdAxi3Master    m_axi;
      interface ReadOnly#(Bool)  interrupt;
      interface LEDS             leds;
   endinterface
   
  -module mkZynqTop(Top);
  +module mkAxiTop(AxiTop);
   
      DMAIndicationProxy dmaIndicationProxy <- mkDMAIndicationProxy(9);
   
  
positive.code: `ifndef BSIM
     interface StdAxi3Master m_axi = axi_master;
  `endif
  endmodule
  
  import "BDPI" function Action      initPortal(Bit#(32) d);
  import "BDPI" function Bool                    writeReq();
  
negative.code:    Reg#(Bool) interruptRequested <- mkReg(False, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // instantiate user portals
     let axiTop <- mkAxiTop(clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // connect them to PCIE
     mkConnection(x7pcie.portal0, axiTop.ctrl, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     AxiSlaveEngine#(64,8) axiSlaveEngine <- mkAxiSlaveEngine(x7pcie.pciId(), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(tpl_1(x7pcie.slave), tpl_2(axiSlaveEngine.tlps), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(tpl_1(axiSlaveEngine.tlps), tpl_2(x7pcie.slave), clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     mkConnection(axiTop.m_axi, axiSlaveEngine.slave3, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     rule requestInterrupt;
        if (axiTop.interrupt && !interruptRequested)
  	 x7pcie.interrupt();
        interruptRequested <= axiTop.interrupt;
     endrule
  
     interface pcie = x7pcie.pcie;
  