anchor.diff:     rule incTimestamp;
          timestamp <= timestamp + 1;
      endrule
  -   rule endTrace if (csr.tlpTracing && csr.tlpDataBramWrAddr > 2047);
  -       csr.tlpTracing <= False;
  -   endrule
  +//   rule endTrace if (csr.tlpTracing && csr.tlpTraceLimit != 0 && csr.tlpDataBramWrAddr > truncate(csr.tlpTraceLimit));
  +//       csr.tlpTracing <= False;
  +//   endrule
   
      // connect the sub-components to each other
   
  
positive.code:    // Registers and their default values
     Vector#(4,MSIX_Entry) msix_entry               <- replicateM(mkMSIXEntry);
  
     Reg#(Bool) tlpTracingReg <- mkReg(False);
     Reg#(Bool) use4dwReg <- mkReg(True);
     Reg#(Bit#(32)) tlpDataBramRdAddrReg <- mkReg(0);
     Reg#(Bit#(32)) tlpDataBramWrAddrReg <- mkReg(0);
  
negative.code: 	    781: tlpDataScratchpad[5] <= dword;
  
  	    792: tlpDataBramWrAddrReg <= dword;
  	    793: tlpTraceLimitReg <= dword;
  
              //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
              // MSIx table entries
  