anchor.diff:      method                  train9(TRAIN9) enable((*inhigh*) en39) clocked_by(clock);
       method                  edgeintor(EDGE_INT_OR) enable((*inhigh*) en21) clocked_by(clock);
       method CTRL_BITSLIP     ctrl_bitslip() clocked_by(clkdiv) reset_by(clkdiv_reset);
  -    method CTRL_FIFO_RESET   ctrl_fifo_reset() clocked_by(clkdiv) reset_by(clkdiv_reset);
       method CTRL_RESET_INC_CE ctrl_reset_inc_ce() clocked_by(clkdiv) reset_by(clkdiv_reset);
       method                  endhandshake(end_handshake) enable((*inhigh*) en20) clocked_by(clock);
       method start_handshake starthandshake();
       schedule (train0, train1, train2, train3, train4, train5, train6, train7, train8, train9,
  -              edgeintor, edgeint, endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap)
  +              edgeintor, edgeint, endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap)
            CF (train0, train1, train2, train3, train4, train5, train6, train7, train8, train9,
  -              edgeintor, edgeint, endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, ctrl_fifo_reset, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap);
  +              edgeintor, edgeint, endhandshake, starthandshake, ctrl_reset_inc_ce, ctrl_bitslip, reset, dataout, align_busy, aligned, samplein, align_start, autoalign, training, manual_tap);
   endmodule: mkIserdesbvi
   
   interface IserdesDatadeser;
  
positive.code:     Reg#(Bit#(1)) serdes_aligned_temp <- mkReg(0);
      Reg#(Bit#(1)) serdes_aligned_reg <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);
      Wire#(Bit#(1)) new_raw_empty_wire <- mkDWire(0);
      Vector#(5, IserdesDatadeser) serdes_v <- replicateM(mkIserdesDatadeser(serdes_clock, serdes_reset, serdest_clk.gen_clk,
  	  serdes_align_start_reg, serdes_auto_align_reg, serdes_training_reg,
  	  serdes_manual_tap_reg, decoder_enable_reg));
  
      rule serdes_copybits;
          serdes_aligned_reg <= serdes_aligned_temp;
  
negative.code:         iodelay_reset_inc_ce <= sync_reset_inc_ce;
      endrule
  
      rule clkdivreset_rule if (bvi_resets_reg.read() != 0);
          dfifo_reset_r.send(serbvi.align_busy());
      endrule
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
          let ds = dstate;
          let dc = dcounter;
  