anchor.diff:     return truncate (addr >> bits_per_byte_in_data);
   endfunction
   
  -function Bit #(64) fn_addr_to_data_addr (Bit #(64) addr);
  +function Bit #(64) fn_addr_to_line_addr (Bit #(64) addr);
      return ((addr >> bits_per_byte_in_data) << bits_per_byte_in_data);
   endfunction
   
  
positive.code: 
  	 // Update cache tag to state requested by L2
  	 let new_tag = DMA_Cache_Tag {tag_state: l2_to_l1_req.to_state,
  				      tag_addr:  addr };
  	 tag_set [0] = new_tag;        // Direct mapped only, for now
  	 rf_tag_sets.upd(index, tag_set);
        end
     endrule
  
     // ================================================================
     // Evictions on conflict-miss
     // (Cache frame for AXI4 request's address is currently occupied by
     //  data with a different address; needs to be handed back to L2).
  
     rule rl_evict ((rg_state == STATE_IDLE)
  		  && (! f_L2_to_L1_Reqs.notEmpty)        // L2-to-L1 requests have priority
  		  && soc_map.m_is_mem_addr (addr)        // cacheable addrs only
  		  && (tag.tag_state != META_INVALID)
  		  && (tag.tag_addr  != fn_addr_to_data_addr (addr)));
        let index   = fn_addr_to_index (addr);
        let tag_set = rf_tag_sets.sub (index);
        let tag     = tag_set [0];    // Direct mapped only, for now
  
        // Evict current occupant (=> INVALID), and evict data if modified
        let m_data = ((tag.tag_state != META_MODIFIED)
  		    ? tagged Invalid
  		    : tagged Valid rf_data_sets.sub (index) [0]);
        let l1_to_l2_rsp = L1_to_L2_Rsp {addr:     tag.tag_addr,
  				       to_state: META_INVALID,
  				       m_cline:  m_data };
        f_L1_to_L2_Rsps.enq (l1_to_l2_rsp);
  
        // Set cache frame tag to INVALID
        let new_tag = DMA_Cache_Tag {tag_state: META_INVALID, tag_addr:  ? };
        let new_tag_set = fn_mk_Tag_Set (new_tag);
        rf_tag_sets.upd (index, new_tag_set);
  
  
negative.code:       let rsp <- pop (f_L2_to_L1_Rsps);
  
        // Assert response is for addr requested
        if (rsp.addr != line_addr) begin
  	 $display ("%0d: DMA_Cache.rl_upgrade_rsp: ERROR: rsp is not for addr %0h",
  		   cur_cycle, line_addr);
  	 $display ("    ", fshow (rsp));
  	 $finish (1);
        end
  
        // Old data can be from L2 or from this cache
        Data old_data = ?;
        if (rsp.m_cline matches tagged Valid .x) begin
  	 if (tag.tag_state != META_INVALID) begin
  