anchor.diff:        for (ii<= 1; ii <= aLenReg; ii <= ii + 1)
   	 for (jj<= 1; jj <= bLenReg; jj <= jj + 1)
   	    seq
  -	       strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: ii-1, datain: 0});
  -	       strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: jj-1, datain: 0});
  +	       strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: aStartReg + ii-1, datain: 0});
  +	       strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: bStartReg + jj-1, datain: 0});
   	       action
   		  let ta <- strA.response.get();
   		  let tb <- strB.response.get();
  
positive.code:    
     FSM hA <- mkFSM(hirschA);
    
     method Action setupA(Bit#(7) strLen);
        aLenReg <= strLen;
     endmethod
     
     method Action setupB(Bit#(7) strLen);
        bLenReg <= strLen;
     endmethod
    
     interface FSM fsm = hA;
  
negative.code:       provisos(Add#(0, 7, strIndexWidth),
  	       Add#(0, 14, lIndexWidth));
  
     Reg#(Bit#(7)) aStartReg <- mkReg(0);
     Reg#(Bit#(7)) bStartReg <- mkReg(0);
     Reg#(Bit#(7)) aLenReg <- mkReg(0);
     Reg#(Bit#(7)) bLenReg <- mkReg(0);
     Reg#(Bit#(14)) rLenReg <- mkReg(0);
  