anchor.diff:        Bit#(1)  parity = ^v[65:13];
         Bit#(53) c_remote = v[65:13];
         Bit#(66) vo = v;
  -      Bool init_rcvd_next   = False;
  -      Bool ack_rcvd_next    = False;
  -      Bool beacon_rcvd_next = False;
  -      Bool log_rcvd_next    = False;
   
         let c_remote_compensated = c_remote + rxtx_delay;
   
  -      if ((v[9:2] == 8'h1e) && (v[12:10] != 0) && bsync_lock_wire) begin
  +      if ((v[9:2] == 8'h1e)) begin
            vo[65:10] = 56'h0;
            if (v[11:10] == init_type) begin
               if (parity == v[12]) begin
  -               init_rcvd_next = True;
  -               if(dtpEventOutFifo.notFull) begin
  +               if(dtpEventOutFifo.notFull && bsync_lock_wire) begin
                     dtpEventOutFifo.enq(DtpEvent{e:zeroExtend(v[11:10]), t:c_remote});
                  end
                  if(verbose) $display("%d: %d init_rcvd %d, forward to tx %d", cycle, id, c_remote, c_remote_compensated);
  
positive.code:    let verbose = True;
  
     Reg#(Bit#(32))  cycle   <- mkReg(0);
     Wire#(Bool) init_rcvd   <- mkDWire(False);
     Wire#(Bool) ack_rcvd    <- mkDWire(False);
     Wire#(Bool) beacon_rcvd <- mkDWire(False);
     Wire#(Bool) log_rcvd    <- mkDWire(False);
     Wire#(Bool) rx_ready_wire <- mkDWire(False);
     Wire#(Bool) bsync_lock_wire <- mkDWire(False);
  
  
negative.code:          end
           else if (v[11:10] == ack_type) begin
              if (parity == v[12]) begin
                 if(dtpEventOutFifo.notFull && bsync_lock_wire) begin
                    dtpEventOutFifo.enq(DtpEvent{e:zeroExtend(v[11:10]), t:c_remote});
                 end
                 if(verbose) $display("%d: %d ack_rcvd %d, forward to tx %d", cycle, id, c_remote, c_remote_compensated);
  