anchor.diff:      endrule
   
       rule controlserdes_rule;
  -        //for (Integer i = 0; i < 3; i = i + 1)
  -            //serdes_reset_inc_ce[i].send(ctrl_reset_inc_ce[i]);
           serdes_reset_inc_ce.send(ctrl_reset_inc_ce);
       endrule
   
  
positive.code:     method Bit#(10)         dataout();
  endinterface: IserdesDatadeser
  
  interface FIFO18;
     method Action            di(Bit#(16) v);
     method Action            rden(Bit#(1) v);
     method Action            wren(Bit#(1) v);
     method Action            reset(Bit#(1) v);
     method Bit#(16)          dataout();
     method Bit#(1)           empty();
  endinterface: FIFO18
  
  import "BVI" FIFO18 = 
  module mkFIFO18#(Clock clkdiv)(FIFO18);
      parameter ALMOST_FULL_OFFSET = 'h80;
      parameter ALMOST_EMPTY_OFFSET = 'h80;
      parameter DATA_WIDTH = 18;
      parameter DO_REG = 1;
      parameter EN_SYN = 0;
      parameter FIRST_WORD_FALL_THROUGH = 0;
      parameter SIM_MODE = "SAFE";
  
      default_clock clock(RDCLK);
      input_clock clkdiv (WRCLK) = clkdiv;
      no_reset;
      port DIP = 0;
  
      method          reset(RST) enable((*inhigh*) en9) clocked_by (clkdiv);
      method          di(DI) enable((*inhigh*) en0) clocked_by (clock); //clkdiv);
      method          rden(RDEN) enable((*inhigh*) en2) clocked_by (clock);
      method          wren(WREN) enable((*inhigh*) en3) clocked_by (clock);
      method DO       dataout() clocked_by(clock);
      method EMPTY    empty() clocked_by(clock);
      schedule (reset, di, rden, wren, dataout, empty) CF (reset, di, rden, wren, dataout, empty);
  endmodule: mkFIFO18
  
  typedef enum { QIdle, QTrain, QOff} QState deriving (Bits,Eq);
  typedef enum { AIdle, ADelay, AWDelay, AEdge, ACEdge, AWait, ACompare, AValid,
       A1Changed, A1Stable, ASecond, AFound, AResetman, AStart, AAlign, ADone } AState deriving (Bits,Eq);
  
negative.code:         fifo_reset <= fifo_reset_sync.read();
      endrule
  
      rule clear_fifo if (sync_reset_inc_ce[2] == 1);
          dfifo.clear();
      endrule
      rule setrule;
          delaye2.reset(sync_reset_inc_ce[2]);
          delaye2.cinvctrl(0);
          delaye2.cntvaluein(0);
  