anchor.diff:      no_reset;
       port DIP = 0;
   
  -    method          reset(RST) enable((*inhigh*) en9) clocked_by (clkdiv);
  +    method          reset(RST) enable((*inhigh*) en9) clocked_by (clock);
       method          di(DI) enable((*inhigh*) en0) clocked_by (clkdiv);
       method          rden(RDEN) enable((*inhigh*) en2) clocked_by (clock);
       method          wren(WREN) enable((*inhigh*) en3) clocked_by (clock);
  
positive.code:     Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
      ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
      Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
      //MakeResetIfc fifo_reset <- mkReset(2, True, serdes_clock);
      FIFO18 dfifo <- mkFIFO18(serdes_clock);
      MakeResetIfc iodelay_reset <- mkReset(2, True, serdes_clock, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule dfifo_reset_rule;
          dfifo.reset(serbvi.fifo_reset);
      endrule
      //rule fresetrule if (serbvi.fifo_reset == 1);
          //fifo_reset.assertReset();
      //endrule
      rule resetrule if (serbvi.iodelay_reset_inc_ce()[2] == 1);
          iodelay_reset.assertReset();
      endrule
  
negative.code:    method Action                 delay_wren(Bit#(1) v);
     method Action                 fifo_wren(Bit#(1) v);
     method Action                 reset(Bit#(1) v);
     method Action                 serreset(Bit#(1) v);
     method Bit#(1)                fifo_wren_sync();
     method Bit#(1)                fifo_reset();
     method Bit#(10)               dataout();
  