anchor.diff:  // SOFTWARE.
   
   import Vector            :: *;
  +import BuildVector       :: *;
   import Clocks            :: *;
   import GetPut            :: *;
   import FIFO              :: *;
  
positive.code:          tlp = mvec[i].tlp;
        end
        mkConnection((interface Server;
                         interface response = dispatcher[tlpCompleterRequest].out[i];
                         interface request = arbiter[tlpCompleterRequest].in[i];
                      endinterface), tlp);
     end
  
     Vector#(NumberOfTlpIntfs, PcieTracer) traceif <- replicateM(mkPcieTracer());
     mkConnection(traceif[tlpCompleterRequest].bus, (interface Client;
                                      interface request = arbiter[tlpCompleterRequest].outToBus;
                                      interface response = dispatcher[tlpCompleterRequest].inFromBus;
                                   endinterface));
     mkConnection(traceif[tlpRequesterRequest].bus, (interface Client;
                                      interface request = arbiter[tlpRequesterRequest].outToBus;
                                      interface response = dispatcher[tlpRequesterRequest].inFromBus;
                                   endinterface));
  
     PcieControlAndStatusRegs csr <- mkPcieControlAndStatusRegs();
     mkConnection(mvec[portConfig].master, csr.memSlave);
  
     interface msixEntry = csr.msixEntry;
     interface master = mvec[portPortal].master;
     interface slave = slavearr;
     interface interruptRequest = intr.interruptRequest;
     interface pcic = traceif[tlpCompleterRequest].pci;
     interface pcir = traceif[tlpRequesterRequest].pci;
  endmodule: mkPcieHost
  `else //NOT PCIE3
  // ======================================================
  
negative.code: `ifdef PCIE3
  Integer tlpCompleterRequest = 0;
  Integer tlpRequesterRequest = 1;
  
  (* synthesize *)
  module mkPcieHost#(PciId my_pciId)(PcieHost#(DataBusWidth, NumberOfMasters));
     TLPDispatcher dispatcher <- mkTLPDispatcher;
     TLPArbiter arbiter <- mkTLPArbiter;
     MemToPcie#(DataBusWidth) sEngine <- mkMemToPcieSynth(my_pciId);
     MemInterrupt intr <- mkMemInterrupt(my_pciId);
     Vector#(PortMax, PcieToMem) mvec;
     for (Integer i=0; i < valueOf(PortMax) - 1; i=i+1) begin
        let tlp;
        if (i == portInterrupt)
  