anchor.diff:  import Clocks                               ::*;
   import Vector                               ::*;
   import Connectable                          ::*;
  +import FIFOF ::*;
  +import SpecialFIFOs ::*;
  +import Pipe ::*;
  +import GetPut ::*;
   
   import ConnectalClocks                      ::*;
   import Ethernet                             ::*;
  -
   import ALTERA_ETH_PMA_WRAPPER               ::*;
   import ALTERA_ETH_PMA_RECONFIG_WRAPPER      ::*;
   import ALTERA_ETH_PMA_RESET_CONTROL_WRAPPER ::*;
  
positive.code: endinterface
  
  (* always_ready, always_enabled *)
  interface EthPmaIfc#(numeric type np);
     interface PhyMgmtIfc             phy_mgmt;
     interface Vector#(np, Status)    status;
     interface Vector#(np, SerialIfc) fiber;
     interface Vector#(np, XCVR_PMA)  fpga;
  endinterface
  
  (* synthesize *)
  module mkEthPma#(Clock phy_mgmt_clk, Clock pll_ref_clk, Reset phy_mgmt_reset)(EthPmaIfc#(NumPorts));
  
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  
negative.code:    endrule
  
     interface status = status_ifcs;
     interface pmd    = serial_ifcs;
     interface fpga   = xcvr_ifcs;
  
     interface PhyMgmtIfc phy_mgmt;
  