anchor.diff:     endrule
   
      // Internal
  -   Vector#(16, FIFOF#(Bit#(64)))  mem;
  -   for(Integer i = 0; i < 15; i = i + 1)
  -      mem[i] <- mkUGSizedFIFOF(16);
  -   mem[15] <- mkSizedFIFOF(16);
  -
  -   Reg#(Bit#(8)) rowIdx <- mkConfigReg(0);
  -   Reg#(Bit#(4)) colCnt <- mkConfigReg(0);
  +   Vector#(16, BRAM_SDP_PORT#(5,64,6,32))  mem <- replicateM(mkRAM_Nx1);
  +
  +   Reg#(Bit#(9)) rowIdx <- mkConfigReg(0);
  +   Reg#(Bit#(6)) colCnt <- mkConfigReg(0);
      Reg#(Bit#(3)) colIdx <- mkConfigReg(0);
   
      Vector#(4, IDct32Core#(10)) dct_1D <- replicateM(mkDct32Core);
      Vector#(4, IDct32Core#(17)) dct_2D <- replicateM(mkDct32Core);
  +   Wire#(Bit#(1)) w_syncCol <- mkDWire(0);
  +   Reg#(Bit#(2)) syncCol <- mkReg(0);
      FIFOF#(Vector#(32, Bit#(17))) fifo_col <- mkPipelineFIFOF;        // [E[0..15] O[0..15]]
   
      rule do_1D(fifo_in.notEmpty);
  
positive.code: import BUtils::*;
  import BRAMCore::*;
  import SMul::*;
  
  Integer g_t32[32][16] =
  {
  
negative.code: 
        fifo_col.enq(y);
        colCnt <= colCnt + 1;
     endrule
  
     rule do_2D;
        let x = fifo_col.first;
  
        if (False) begin
           $write("[%6d] EO-2D: ", cycles);
           for(Integer i = 0; i < 32; i = i + 1) begin
              Bit#(16) t = truncate(x[i]);
  