anchor.diff:                             xT[ 7], xT[ 6], xT[ 5], xT[ 4], xT[ 3], xT[ 2], xT[ 1], xT[ 0]
                           });
            end
  +         33: begin
  +            Bit#(8) dc = truncate(dcVal >> 6);
  +            y = unpack({?,
  +                           dc, dc, dc, dc, dc, dc, dc, dc,
  +                           dc, dc, dc, dc, dc, dc, dc, dc,
  +                           dc, dc, dc, dc, dc, dc, dc, dc,
  +                           dc, dc, dc, dc, dc, dc, dc, dc
  +                        });
  +         end
         endcase
   
         // swap Top and Left on Horizon/Vertical mode edge
  
positive.code:          tmpLeft = takeAt(1, x.top);
           tmpTop  = cons(x.top[0], x.left);
        end
        reg_i  <= (mode == 32) ? (tagged Invalid) : (tagged Valid IntraRef_t {left:tmpLeft, top:tmpTop});
  
        moded1 <= mode;
        mode   <= mode + 1;
        stage0 <= tagged Valid y;
        cnt1   <= (mode < 16) ? ~0 : 0;
  
negative.code:    FIFOF#(Vector#(2, (Vector#(32, Bit#(13)))))  stage2   <- mkPipelineFIFOF;
     Reg#(Vector#(32, Bit#(8)))                   pixd1    <- mkRegU;
     Reg#(Bit#(6))                                cnt1     <- mkReg(0);
     Reg#(Bit#(8))                                dcVal    <- mkRegU;
  
     Integer chen_debug = 0;
  
  
     rule do_stage0(!isValid(stage0) &&& reg_i matches tagged Valid .x);
        let xL = cons(?, x.left);
  