anchor.diff:           readyReg <= True;
         endmethod
      endinterface
  -   interface data = toPipeOut(dataFifo);
  +   interface data = map(toPipeOut, dataFifo);
   endmodule
   
   module mkSharedMemoryIndicationPortal#(PipePortal#(numRequests, numIndications, 32) portal,
       Vector#(2,MemReadServer#(64)) readEngine, Vector#(2, MemWriteServer#(64)) writeEngine)(SharedMemoryPortal#(64));
      let defaultClock <- exposeCurrentClock;
      let defaultReset <- exposeCurrentReset;
  -   // read the head and tail pointers, if they are different, then read a request
  +   // read the wrPtr and rdPtr pointers, if they are different, then read a request
      Reg#(Bit#(16)) limitReg <- mkReg(0);
  -   Reg#(Bit#(16)) headReg <- mkReg(0);
  -   Reg#(Bit#(16)) tailReg <- mkReg(0);
  +   Reg#(Bit#(16)) wrPtrReg <- mkReg(0);
  +   Reg#(Bit#(16)) rdPtrReg <- mkReg(0);
      Reg#(Bit#(16)) messageWordsReg <- mkReg(0);
      Reg#(Bit#(16)) methodIdReg <- mkReg(0);
      Reg#(Bool) paddingReg <- mkReg(False);
  
positive.code:       if (verbose)
           $display("receiveMessage data=%x messageWords=%d wordCount=%d", data, messageWordsReg, countReg);
        if (methodIdReg != 16'hFFFF)
           dataFifo.enq(data);
        messageWordsReg <= messageWordsReg - 1;
        countReg <= countReg - 1;
        if (countReg <= 1)
           state <= UpdateTail;
        else if (messageWordsReg == 1)
           state <= MessageHeaderRequested;
     endrule
  
     rule updateTail if (state == UpdateTail);
        if (verbose)
           $display("updateTail: tail=%d", tailReg);
        // update the tail pointer
        writeEngine[0].request.put(
            MemengineCmd {sglId: sglIdReg, base: 8, len: 8, burstLen: 8, tag: 0});
        writeEngine[0].data.enq(extend(tailReg));
        state <= Waiting;
     endrule
  
  
negative.code: import MemTypes::*;
  import ConnectalMemory::*;
  
  interface SharedMemoryPipeOut#(numeric type dataBusWidth, numeric type pipeCount);
     interface SharedMemoryPortalConfig cfg;
     interface Vector#(pipeCount, PipeOut#(Bit#(32))) data;
  endinterface
  interface SharedMemoryPipeIn#(numeric type dataBusWidth);
     interface SharedMemoryPortalConfig cfg;
  