anchor.diff:     FIFOF#(Bit#(32))   writeReqFifo <- mkFIFOF();
      FIFOF#(Bit#(32))   readReqFifo <- mkFIFOF();
   
  -   Gearbox#(1,4,MemData#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
  +   Gearbox#(1,BusRatio,MemData#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
      SyncFIFOIfc#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkSyncFIFO(4, clock, reset, ddr3Controller.uiClock);
      SyncFIFOIfc#(Axi4WriteResponse#(6)) bfifo <- mkSyncFIFO(4, ddr3Controller.uiClock, ddr3Controller.uiReset, clock);
      mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);
  
positive.code:    interface Ddr3Pins ddr3;
  endinterface
  
  module mkDdr3Test#(HostInterface host, Ddr3TestIndication indication)(Ddr3Test);
  
     let clock <- exposeCurrentClock();
  
negative.code:       let sglId <- toGet(readReqFifo).get();
        we.writeServers[0].request.put(MemengineCmd { sglId: sglId,
  						   base: 0,
  						   burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),
  						   len: 1024,
  						   tag: 0
  						   });
        ddr3re.readServers[0].request.put(MemengineCmd { sglId: 0,
  						      base: 0,
  						      burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),
  						      len: 1024,
  						      tag: 0
  						      });
     endrule
  