anchor.diff:     MemServerPortal          bramMemServerPortal <- mkPhysMemSlavePortal(bramMemB,bramIndication);
   
      let portB1 = arbiter.users[1];
  +   let portB2 = arbiter.users[2];
      Reg#(Bit#(16)) requestId <- mkReg(0);
  +   Reg#(Bit#(16)) responseId <- mkReg(0);
      Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);
  +   Reg#(Bool) requestSlotAvailable <- mkReg(True);
      Reg#(Bool) requestInProgress <- mkReg(True);
      Reg#(Vector#(16,Bit#(32))) ioCommand <- mkReg(unpack(0));
      Reg#(Bit#(32)) requestStartTimestamp <- mkReg(0);
  
positive.code: 	    command[13] = req.dsm;
  	    requestId <= req.requestId;
  	    ioCommand <= command;
  	 endaction
  	 // write a IO read request to BRAM
           for (i <= 0; i < fromInteger(requestSize/bytesPerEntry); i <= i + 1) seq
  	    portB1.request.put(BRAMRequest {address: 'h1000/fromInteger(bytesPerEntry) + (extend(requestId[2:0]) * fromInteger(requestSize/bytesPerEntry)) + i,
  
negative.code:    BRAM2Port#(Bit#(32),Bit#(PcieDataBusWidth)) bram <- mkBRAM2Server(bramConfig);
  
     let arbIfc <- mkFixedPriority();
     Arbiter#(3, BRAMRequest#(Bit#(32),Bit#(PcieDataBusWidth)),Bit#(PcieDataBusWidth)) arbiter <- mkArbiter(arbIfc,2);
     let arbCnx <- mkConnection(arbiter.master, bram.portB);
  
     MemServer#(PcieDataBusWidth)            bramMemA <- mkMemServerFromBram(bram.portA);
  