anchor.diff:     for(Integer i = 0; i < valueOf(numServers); i=i+1)
         rs[i] = (interface Server#(MemengineCmd,Bool);
   		  interface Put request;
  -		     method Action put(MemengineCmd cmd) if (outs0[i] < cmd_q_depth);
  +		     method Action put(MemengineCmd cmd);
   			Bit#(32) bsb = fromInteger(bufferSizeBytes);
   `ifdef BSIM	 
   			Bit#(32) dw = fromInteger(valueOf(dataWidthBytes));
  
positive.code: 		  interface Get response;
  		     method ActionValue#(Bool) get;
  			outfs[i].deq;
  	 		outs0[i] <= outs0[i]-1;
  			return True;
  		     endmethod
  		  endinterface
  
negative.code: 
     Integer bufferSizeBeats = bufferSizeBytes/valueOf(dataWidthBytes);
     Vector#(numServers, Reg#(Bool))               outs1 <- replicateM(mkReg(False));
     Vector#(numServers, ConfigCounter#(16))     buffCap <- replicateM(mkConfigCounter(fromInteger(bufferSizeBeats)));
     Vector#(numServers, Reg#(MemengineCmd))     cmdRegs <- replicateM(mkReg(unpack(0)));
     
     Reg#(Bool) load_in_progress <- mkReg(False);
     FIFO#(Tuple3#(MemengineCmd,Bool,Bool))         loadf_b <- mkSizedFIFO(1);
     FIFO#(Tuple2#(Bit#(serverIdxSz),MemengineCmd)) loadf_c <- mkSizedFIFO(valueOf(cmdQDepth));
     FIFO#(Tuple3#(Bit#(8),Bit#(serverIdxSz),Bool))   workf <- mkSizedBRAMFIFO(valueOf(cmdQDepth));
     
  
     Vector#(numServers, FIFO#(void))              outfs <- replicateM(mkSizedFIFO(1));
     Vector#(numServers, FIFO#(MemengineCmd))    cmds_in <- replicateM(mkFIFO());
  
     FIFOF#(MemData#(dataWidth))                             read_data <- mkFIFOF;
     Vector#(numServers, FIFOF#(MemData#(dataWidth)))  read_data_buffs <- replicateM(mkSizedBRAMFIFOF(bufferSizeBeats));
  