anchor.diff:        let rsp = DM_CPU_Rsp {ok: False, data: ?};
         f_gpr_rsps.enq (rsp);
   
  -      if (cur_verbosity > 1) $display ("%0d: CPU.rl_debug_gpr_access_busy", mcycle);
  +      if (cur_verbosity > 1) $display ("%0d: %m.rl_debug_gpr_access_busy", mcycle);
      endrule
   
      // ----------------
  
positive.code:    // ----------------
     rule rl_reset_from_WFI (   (rg_state == CPU_WFI_PAUSED)
  			   && f_reset_reqs.notEmpty);
        if (cur_verbosity > 1) $display ("%0d: CPU.rl_reset_from_WFI", mcycle);
  
        rg_state <= CPU_RESET1;
     endrule: rl_reset_from_WFI
  
negative.code: 			     && (rg_state == CPU_RUNNING)
  			     && stage1_take_interrupt
  			     && (stageF.out.ostatus != OSTATUS_BUSY));
        if (cur_verbosity > 1) $display ("%0d: %m.rl_stage1_interrupt", mcycle);
  
        let instr = stage1.out.data_to_stage2.instr;
  
  