anchor.diff:      // reset RST;
       port DIP = 0;
   
  -    method          di(DI) enable((*inhigh*) en0); // clocked_by () reset_by ()
  -    method          rden(RDEN) enable((*inhigh*) en2); // clocked_by () reset_by ()
  -    method          wren(WREN) enable((*inhigh*) en3); // clocked_by () reset_by ()
  +    method          di(DI) enable((*inhigh*) en0) clocked_by (clock);
  +    method          rden(RDEN) enable((*inhigh*) en2) clocked_by (clock);
  +    method          wren(WREN) enable((*inhigh*) en3) clocked_by (clock);
       method DO       dataout() clocked_by(clock);
       method EMPTY    empty() clocked_by(clock);
      schedule (di, rden, wren, dataout, empty) CF (di, rden, wren, dataout, empty);
   endmodule: mkFIFO18
   
  -module mkIserdesDatadeser#(Clock clkdiv, Reset clkdiv_reset, Clock serdest, Bit#(1) align_start,
  +module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
       Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden)(IserdesDatadeser);
   
       Clock defaultClock <- exposeCurrentClock();
  -    Iserdesbvi serbvi <- mkIserdesbvi(clkdiv, serdest);
  -    FIFO18 dfifo <- mkFIFO18(clkdiv, reset_by serbvi.fifo_reset);
  -    MakeResetIfc iodelay_reset <- mkReset(2, True, clkdiv, clocked_by clkdiv, reset_by clkdiv_reset);
  +    Reset defaultReset <- exposeCurrentReset();
  +    ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
  +    Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
  +    FIFO18 dfifo <- mkFIFO18(serdes_clock, reset_by serbvi.fifo_reset);
  +    MakeResetIfc iodelay_reset <- mkReset(2, True, serdes_clock, clocked_by serdes_clock, reset_by serdes_reset);
   
       rule resetrule if (serbvi.iodelay_reset_inc_ce()[2] == 1);
           iodelay_reset.assertReset();
  
positive.code:         delaye2.ce(serbvi.iodelay_reset_inc_ce()[0]);
      endrule
  
      rule idelayout_rule;
          serbvi.idelay_out(delaye2.dataout());
      endrule
  
      rule ssrule;
          dfifo.di({6'b0,serbvi.dataout()});
          dfifo.wren(serbvi.fifo_wren_sync());
      endrule
  
negative.code:         idelay_type: "VARIABLE", idelay_value: 0,
          pipe_sel: "FALSE", refclk_frequency: 200, signal_pattern: "DATA"},
          defaultClock,
          clocked_by serdes_clock, reset_by iodelay_reset.new_rst);
  
      rule delaye2_rule;
          delaye2.cinvctrl(0);
  