anchor.diff:  	    /* Loop through string B */
   	    for (jj <= 1; jj <= bLenReg; jj <= jj + 1)
   	       seq
  +		  //$display("hirschB jj = %d", jj);
   		  action
   		     /* Read a[i] and b[j] */
   		     strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: ii-1, datain: 0});
  
positive.code:    endmethod
  
     method Action setupL(Bit#(14) start);
     endmethod
  
     
  
negative.code:    Reg#(Bit#(16)) k1jm1 <- mkReg(0);
     Reg#(Bit#(16)) k0j <- mkReg(0);
     Reg#(Bit#(16)) k0jm1 <- mkReg(0);
     BRAM1Port#(Bit#(lIndexWidth), Bit#(16)) k0  <- mkBRAM1Server(defaultValue);
  
  
    Stmt hirschB =
     seq
        $display("hirschB running ");
        /* initialize K1 (stored in lMat) of temporary storage */
        for (jj <= 0; jj <= bLenReg; jj <= jj + 1)
  	 seq
  	    matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: rStartReg + zeroExtend(jj), datain: 0});
  	 endseq
        /* Loop through string a */
        for (ii <= 1; ii <= aLenReg; ii <= ii + 1)
  	 seq
  	    //$display("hirschB ii = %d", ii);
  	    /* Copy L[1] to L[0].  could pingpong instead, or unroll loop */
  	    /* L[1] is stored in matL[0] and L[0] is stored in k0[1] so that the result is in the right place at the end */
  	    for (jj <= 0; jj <= bLenReg; jj <= jj + 1)
  	       seq
  		  matL.request.put(BRAMRequest{write: False, responseOnWrite: False, address: rStartReg + zeroExtend(jj), datain: 0});
  		  action
  		     let ta <- matL.response.get();
  		     k0.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: rStartReg + zeroExtend(jj), datain: ta});
  		  endaction
  	       endseq
  	    /* initialize pipelining */
  