anchor.diff: -// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
  +// Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved
   
   package Boot_ROM;
   
  
positive.code:    rule rl_process_rd_req (rg_module_ready);
        let rda <- pop_o (slave_xactor.o_rd_addr);
  
        let byte_addr = rda.araddr - rg_addr_base;
  
        AXI4_Resp  rresp  = axi4_resp_okay;
        Bit #(64)  data64 = 0;
        if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim, rda.arsize)) begin
  	 rresp = axi4_resp_slverr;
  	 $display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized or misaligned addr",
  		   cur_cycle);
  	 $display ("    ", fshow (rda));
        end
        else if (rda.araddr [2:0] == 3'b0) begin
  	 Bit #(32) d0 = fn_read_ROM_0 (byte_addr);
  	 Bit #(32) d1 = fn_read_ROM_4 (byte_addr + 4);
  	 data64 = { d1, d0 };
        end
        else begin    // ((valueOf (Wd_Data) == 32) && (rda.addr [1:0] == 2'b_00))
  	 Bit #(32) d1 = fn_read_ROM_4 (byte_addr);
  	 data64 = { 0, d1 };
  	 if (valueOf (Wd_Data) == 64)
  	    data64 = { d1, 0 };
        end
  
        Bit #(Wd_Data) rdata  = truncate (data64);
        let rdr = AXI4_Rd_Data {rid:   rda.arid,
  
negative.code:    // ----------------
  
     function Bool fn_addr_is_aligned (Fabric_Addr addr, AXI4_Size arsize);
        if      (arsize == axsize_1)  return True;
        else if (arsize == axsize_2)  return (addr [0] == 1'b_0);
        else if (arsize == axsize_4)  return (addr [1:0] == 2'b_00);
        else if (arsize == axsize_8)  return (addr [2:0] == 3'b_000);
        else return False;
     endfunction
  
     function Bool fn_addr_is_in_range (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
  