anchor.diff:  
         // Just save relevant info and handle in next clock
         rg_trap_info       <= stage2.out.trap_info;
  +      rg_trap_interrupt  <= False;
         rg_trap_instr      <= stage2.out.data_to_stage3.instr;
   `ifdef INCLUDE_TANDEM_VERIF
         rg_trap_trace_data <= stage2.out.trace_data;
  
positive.code: 
     // These regs save info on a trap in Stage1 or Stage2
     Reg #(Trap_Info)  rg_trap_info       <- mkRegU;
     Reg #(Instr)      rg_trap_instr      <- mkRegU;
  `ifdef INCLUDE_TANDEM_VERIF
     Reg #(Trace_Data) rg_trap_trace_data <- mkRegU;
  
negative.code: 			     && (stageF.out.ostatus != OSTATUS_BUSY));
        if (cur_verbosity > 1) $display ("%0d: %m.rl_stage1_interrupt", mcycle);
  
        // Just save relevant info and handle in next clock
        Exc_Code exc_code = 0;    // "Unknown cause" for NMI
        if (csr_regfile.interrupt_pending (rg_cur_priv) matches tagged Valid .ec
  	  &&& (! csr_regfile.nmi_pending))
  	 exc_code = ec;
  
        rg_trap_info       <= Trap_Info {epc:      stage1.out.data_to_stage2.pc,
  				       exc_code: exc_code,
  				       tval:     0};
        rg_trap_interrupt  <= True;
        rg_trap_instr      <= stage1.out.data_to_stage2.instr;
  
  `ifdef INCLUDE_TANDEM_VERIF
        // rg_trap_trace_data <= ?;    // Will be filled in in rl_trap
  `endif
  
        rg_state           <= CPU_TRAP;
     endrule: rl_stage1_interrupt
  
  
     // ================================================================
     // Stage1: Handle debugger stop-request and dcsr.step step-request while running
     // and no interrupt pending.  Stage1 has an architectural instruction,
     // and stage2 and stage3 are empty, and stageF is not BUSY.
  