anchor.diff:     FIFO#(Bit#(64)) f_out <- mkSizedFIFO(16);    // to buffer outgoing responses
      Reg#(Bit#(16)) copyReadCount <- mkReg(0);
      Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
  -   Reg#(Bit#(40)) copyReadAddr <- mkReg(0);
  -   Reg#(Bit#(40)) copyWriteAddr <- mkReg(0);
  +   Reg#(Bit#(DmaAddrSize)) copyReadAddr <- mkReg(0);
  +   Reg#(Bit#(DmaAddrSize)) copyWriteAddr <- mkReg(0);
  +   Reg#(DmaMemHandle) copyReadHandle <- mkReg(0);
  +   Reg#(DmaMemHandle) copyWriteHandle <- mkReg(0);
      Reg#(Bit#(32)) copyTag <- mkReg(0);
      Reg#(Bool) copyBusy <- mkReg(False);
       
  
positive.code:       while(True)
  	 seq
  	    while (copyBusy) noAction;
  	    copyTag <= f_in.first()[31:0];
  	    f_in.deq();
  	    copyReadAddr <= f_in.first()[39:0];
  	    f_in.deq();
  	    copyWriteAddr <= f_in.first()[39:0];
  	    f_in.deq();
  	    action
  	       copyReadCount <= f_in.first()[15:0];
  	       copyWriteCount <= f_in.first()[15:0];
  	       f_in.deq();
  	    endaction
  	    for (ii <= 0; ii < 4; ii <= ii+1)
  	       f_in.deq;
  	    copyBusy <= True;
  	 endseq
     endseq;
        
      rule copyReadRule (copyBusy && (copyReadCount != 0));
         $display("copyRead %h, count %h", copyReadAddr, copyReadCount);
         copy_read_chan.readReq.put(copyReadAddr);
         copyReadAddr <= copyReadAddr + 8;
         copyReadCount <= copyReadCount - 8;
      endrule
  
negative.code:     rule copyReadWriteRule (copyBusy);
         let data <- copy_read_chan.readData.get;
         $display("copyReadWrite addr %h", copyWriteAddr);
         copy_write_chan.writeReq.put(DMAAddressRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: extend(1), tag: truncate(copyWriteAddr >> 3)});
         copy_write_chan.writeData.put(DMAData{data: data.data, tag: copyWriteAddr >> 3});
         copyWriteAddr <= copyWriteAddr + 8;
      endrule
      
  