anchor.diff:      Reg#(Bool) init <- mkReg(False);
       Vector#(n, Reg#(Bit#(8))) schedWires <- replicateM(mkDWire(charToBits("_")));
       Reg#(Maybe#(Bit#(64))) pcWire <- mkDWire(tagged Invalid);
  +    Reg#(Maybe#(Bit#(32))) instWire <- mkDWire(tagged Invalid);
   
       rule printLegend(!init);
           for (Integer i = 0 ; i < valueOf(n) ; i = i+1) begin
  
positive.code: interface ScheduleMonitor;
      method Action record(String ruleName, Char char);
      method Action recordPC(Bit#(64) pc);
  endinterface
  
  module mkScheduleMonitor#(File file, Vector#(n, String) ruleNames)(ScheduleMonitor);
  
negative.code:     method Action recordPC(Bit#(64) pc);
          pcWire <= tagged Valid pc;
      endmethod
      method Action recordInst(Bit#(32) inst);
          instWire <= tagged Valid inst;
      endmethod
  endmodule
  
  endpackage
  