anchor.diff:        // (the 16b we've already got is saved in r16_cache_b16).
         // Note: since we know it's a 32b instr, this next fetch is not speculative, so ok if it page faults.
         if (   is_addr_odd16 (addr)
  -	  && imem32.valid
  +	  && (imem32.valid && (! imem32.exc))
   	  && (addr_of_b32 == imem32.pc)
   	  && is_32b_instr (imem32.instr [31:16]))
   	 begin
  
positive.code:    // Condition: 32b instr from { ...next imem [15:0], imem [31:16] }
     Bool cond_i32_odd_fetch_next = (   is_addr_odd16 (rg_pc)
  				   && imem32.valid
  				   && eq_b32_addr (rg_pc, imem32.pc)
  				   && is_32b_instr (imem32.instr [31:16]));
  
  
negative.code: 
     // Holds a faulting address
     Reg #(WordXL)    rg_tval        <- mkRegU;
  
     // These registers caches the last output of imem32 (imem32.pc, and imem32.instr [31:16])
     Reg #(WordXL)    rg_cache_addr <- mkReg ('1);
     Reg #(Bit #(16)) rg_cache_b16  <- mkRegU;
  
     // ----------------------------------------------------------------
     // Conditions for selecting 16b and 32b instruction
  