anchor.diff:  	 interface Put writeReq = ctrlWriteAddrGenerator.request;
   	 interface Put writeData;
   	    method Action put(MemData#(dataWidth) d);
  -	       let b <- ctrlWriteAddrGenerator.addrBeat.get();
  -	       //$display("mkCtrl.writeData addr=%h data=%h last=%d", b.addr, d.data, b.last);
  -	       let v = d.data;
  -	       let addr = b.addr;
  -	       if (addr == 'h000)
  -		  noAction;
  -	       if (addr == 'h004)
  -		  interruptEnableReg <= v[0] == 1'd1;
  -	       if (b.last)
  -		  ctrlWriteDoneFifo.enq(b.tag);
  +	       ctrlWriteDataFifo.enq(d);
   	    endmethod
   	 endinterface
   	 interface Get writeDone;
  
positive.code:            readyChannel = fromInteger(i);
          end
      end
  
     interface MemSlave memSlave;
        interface MemReadServer read_server;
  
negative.code:    AddressGenerator#(addrWidth,dataWidth) fifoReadAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(addrWidth,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();
     FIFO#(Bit#(ObjectTagSize))                  fifoWriteDoneFifo <- mkFIFO();
     FIFO#(MemData#(dataWidth))                   fifoReadDataFifo <- mkFIFO();
     rule readDataRule;
        let b <- fifoReadAddrGenerator.addrBeat.get();
        let v = 0;
        if (b.addr[7:0] == 0)
  	 v <- toGet(methodPipe).get();
        else if (b.addr[7:0] == 4)
  	 v = extend(pack(methodPipe.notEmpty()));
        //$display("mkPipeOutMemSlave.readData.get addr=%h data=%h", b.addr, data);
        fifoReadDataFifo.enq(MemData { data: v, tag: b.tag, last: b.last });
     endrule
  
     interface MemReadServer read_server;
        interface Put readReq;
  	 method Action put(MemRequest#(addrWidth) req);
  