anchor.diff:  
         let v = client.rd(unpack(addr >> 2));
         $display("MemSlave do_read addr=%h len=%d v=%h", addr, bc, v);
  -      resp_read_fifo.enq(MemData { data: v, tag: req.tag });
  +      slaveReadDataFifos.enq(MemData { data: v, tag: req.tag });
   
         addr = addr + 4;
         bc = bc - 1;
  
positive.code:       endinterface
        interface Get     readData;
           method ActionValue#(MemData#(32)) get();
              let resp = resp_read_fifo.first();
              resp_read_fifo.deq();
              return resp;
           endmethod
        endinterface
     endinterface
     interface MemWriteServer write_server; 
        interface Put writeReq;
           method Action put(MemRequest#(32) req);
              req_aw_fifo.enq(req);
           endmethod
        endinterface
        interface Put writeData;
           method Action put(MemData#(32) resp);
              resp_write_fifo.enq(resp);
           endmethod
        endinterface
        interface Get writeDone;
           method ActionValue#(Bit#(ObjectTagSize)) get();
              let b = resp_b_fifo.first();
              resp_b_fifo.deq();
              return b;
           endmethod
        endinterface
     endinterface
  
negative.code: 
  module mkMemSlave#(MemSlaveClient client)(MemSlave#(32,32));
     FIFOF#(MemRequest#(32)) req_ar_fifo <- mkFIFOF();
     FIFOF#(MemData#(32)) slaveReadDataFifos <- mkSizedFIFOF(8);
     FIFOF#(MemRequest#(32)) req_aw_fifo <- mkFIFOF();
     FIFOF#(MemData#(32)) slaveWriteDataFifos <- mkSizedFIFOF(8);
     FIFOF#(Bit#(ObjectTagSize)) slaveBrespFifo <- mkFIFOF();
  
     Reg#(Bit#(8)) readBurstCount <- mkReg(0);
     Reg#(Bit#(30)) readAddr <- mkReg(0);
  