anchor.diff:        end
         rvFifo.enq(rv);
         //$display("mkMemMethodMux.readData aw=%d rs=%d data=%h", valueOf(aw), rs.first, rv.data);
  -      rs.deq();
  -      rsCtrl.deq();
  +      if (b.last) begin
  +	 rs.deq();
  +	 rsCtrl.deq();
  +      end
      endrule
   
      interface PhysMemWriteServer write_server;
  
positive.code: 
     rule req_aw;
        let req <- toGet(req_aws).get;
        if (wsCtrl.first)
           ctrl.write_server.writeReq.put(req);
        else
           fifoWriteAddrGenerator.request.put(req);
     endrule
  
     rule req_ar;
        let req <- toGet(req_ars).get;
        if (rsCtrl.first)
           ctrl.read_server.readReq.put(req);
        else
           fifoReadAddrGenerator.request.put(req);
     endrule
  
     FIFO#(MemData#(dataWidth)) rvFifo <- mkFIFO;
  
negative.code:    rule readDataRule;
        let b <- fifoReadAddrGenerator.addrBeat.get();
        let v = 0;
        if (!rsCtrl.first) begin
  	  if (b.addr == 0)
  	     v <- toGet(indications[rs.first]).get();
  	  else if (b.addr == 4)
  	     v = extend(pack(indications[rs.first].notEmpty()));
  	  //$display("mkPipeOutMemSlave.readData.get addr=%h data=%h", b.addr, data);
  	  fifoReadDataFifo.enq(MemData { data: v, tag: b.tag, last: b.last });
        end
     endrule
  
     rule write_done;
  