anchor.diff:  	    781: tlpDataScratchpad[5] <= dword;
   
   	    792: tlpDataBramWrAddrReg <= dword;
  +	    793: tlpTraceLimitReg <= dword;
   
               //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
               // MSIx table entries
  
positive.code:    interface ReadOnly#(Bit#(64)) interruptAddr;
     interface ReadOnly#(Bit#(32)) interruptData;
  
     interface Reg#(Bool) tlpTracing;
     interface Reg#(Bool) use4dw;
     interface Reg#(Bit#(32)) tlpDataBramWrAddr;
     interface Reg#(Bit#(32)) tlpOutCount;
  
negative.code: 		       (X7PcieBridgeIfc#(lanes))
     provisos(Add#(1,_,lanes), XbsvXilinx7Pcie::SelectXilinx7PCIE#(lanes));
  
     Clock sys_clk_200mhz <- mkClockIBUFDS(sys_clk_p, sys_clk_n);
  
     ClockGenerator7Params clk_params = defaultValue();
  