anchor.diff:     Vector#(NumSGLists, Reg#(SGListIdx))      listEnds <- genWithM(bar);
      FIFOF#(SGListId)                          loadReqs <- mkFIFOF;
      Reg#(SGListIdx)                            initPtr <- mkReg(0);
  -   Reg#(Bool)                             initialized <- mkReg(False);
   
  -   mkAutoFSM(
  -      seq
  -   	 initialized <= True;
  -      endseq
  -      );
  -   
      method Action sglist(Bit#(32) pref, Bit#(40) addr, Bit#(32) len);
         let off = listEnds[pref-1];
         listEnds[pref-1] <= off+1;
  
positive.code: // if this structure becomes too expensive, we can switch to a multi-level structure
  module mkSGListMMU(SGListMMU);
  
     Vector#(NumSGLists, BRAM1Port#(PageIdx, Maybe#(Bit#(TSub#(40,SGListPageShift))))) pageTables <- replicateM(mkBRAM1Server(defaultValue));
     FIFOF#(Bit#(SGListPageShift)) offs <- mkFIFOF;
     FIFOF#(SGListId) ids  <- mkFIFOF;
     Reg#(Bool) initialized <- mkReg(False);
     
     let page_shift = fromInteger(valueOf(SGListPageShift));
     
     mkAutoFSM(
        seq
     	 initialized <= True;
        endseq
        );
     
     method Action page(SGListId id, Bit#(32) off, Bit#(40) addr);
        pageTables[id].portA.request.put(BRAMRequest{write:True, responseOnWrite:False, address:truncate(off), datain:tagged Valid truncate(addr)});
     endmethod
  
  
negative.code:    endmethod
     
     method ActionValue#(Bit#(40)) addrResp();
        respFifo.deq();
        return respFifo.first();
     endmethod
     
  endmodule
  