anchor.diff:                                                  memAccessAtCommit: False,
                                                   lsqAtCommitNotified: False,
                                                   nonMMIOStDone: False,
  -                                                epochIncremented: needReplay,
  +                                                epochIncremented: False,
                                                   spec_bits: spec_bits
                                                  };
                           rob.enqPort[i].enq(y);
  
positive.code: 
                          // display information
                          if (verbose) begin
                              $display("  [doRenaming - %d] regs_ready: cons ", i, fshow(regs_ready_cons), " ; aggr ", fshow(regs_ready_aggr));
                              if (arch_regs.src1 matches tagged Valid .valid_src) begin
                                  if (phy_regs.src1 matches tagged Valid .valid_src_renamed) begin
                                      $fdisplay(stdout, "    [SRC RENAMING] ", fshow(valid_src), " -> ", fshow(valid_src_renamed));
                                  end else begin
                                      $fdisplay(stdout, "    [SRC RENAMING] ERROR: ", fshow(valid_src), " -> INVALID");
                                  end
                              end
                              if (arch_regs.src2 matches tagged Valid .valid_src) begin
                                  if (phy_regs.src2 matches tagged Valid .valid_src_renamed) begin
                                      $fdisplay(stdout, "    [SRC RENAMING] ", fshow(valid_src), " -> ", fshow(valid_src_renamed));
                                  end else begin
                                      $fdisplay(stdout, "    [SRC RENAMING] ERROR: ", fshow(valid_src), " -> INVALID");
                                  end
                              end
                              if (arch_regs.src3 matches tagged Valid .valid_src) begin
                                  if (phy_regs.src3 matches tagged Valid .valid_src_renamed) begin
                                      $fdisplay(stdout, "    [SRC RENAMING] ", fshow(valid_src), " -> ", fshow(valid_src_renamed));
                                  end else begin
                                      $fdisplay(stdout, "    [SRC RENAMING] ERROR: ", fshow(valid_src), " -> INVALID");
                                  end
                              end
                              if (arch_regs.dst matches tagged Valid .valid_dst) begin
                                  if (phy_regs.dst matches tagged Valid .valid_dst_renamed) begin
                                      $fdisplay(stdout, "    [DST RENAMING] ", fshow(valid_dst), " => ", fshow(valid_dst_renamed));
                                  end else begin
                                      $fdisplay(stdout, "    [DST RENAMING] ERROR: ", fshow(valid_dst), " -> INVALID");
                                  end
                              end
                          end
  
                          // Enqueue into reorder buffer
  
negative.code:                 // Figure out if there is new speculation and if there is
                  // speculative renaming happening.
                  Bool new_speculation = False;
                  Bool speculative_renaming = False; // deprecated: this is originally for Ld/St checkpoint
                  if (dInst.execFunc matches tagged Br .br) begin
                      // This instruction can cause a redirection due to branch
                      // misprediction. Lets claim a checkpoint for this instruction.
                      // If this instruction is a JAL or JRAL instruction, then the
  