anchor.diff:  
       rule m_arespr_rule;
           let data <- ctrl.read.readData();
  -        AxiRead#(32/*data_width*/, 12/*id_width*/) m_arespr;
  -        m_arespr.rd.data = data;
  -        m_arespr.r.resp = 2'b0;
  -        m_arespr.rd.last = ctrl.read.last();
  -        m_arespr.r.id = ctrl.read.rid();
  +        Axi3ReadResponse#(32/*data_width*/, 12/*id_width*/) m_arespr;
  +        m_arespr.data = data;
  +        m_arespr.resp = 2'b0;
  +        m_arespr.last = ctrl.read.last();
  +        m_arespr.id = ctrl.read.rid();
           ps7.m_axi_gp[0].resp_read.put(m_arespr);
       endrule
   
       rule m_arespw_rule;
           let m_arespw <- ps7.m_axi_gp[0].resp_write.get();
  -        ctrl.write.writeData(m_arespw.wd.data, m_arespw.wstrb, m_arespw.wd.last, m_arespw.wid);
  +        ctrl.write.writeData(m_arespw.data, m_arespw.byteEnable, m_arespw.last, m_arespw.id);
       endrule
   
   if (nmasters > 0) begin
  
positive.code:     for (Integer i = 0; i < 2; i = i + 1)
          vtops_axi_gp[i] = interface AxiSlaveCommon#(32, id_width);
              interface Put req_ar;
                  method Action put(AxiREQ#(id_width) v) if (vs_axi_gp[i].arready() != 0);
                      vs_axi_gp[i].araddr(v.addr);
                      vs_axi_gp[i].arburst(v.burst);
                      vs_axi_gp[i].arcache(v.cache);
                      vs_axi_gp[i].arid(v.id);
  
negative.code:                 endmethod
              endinterface
              interface Put req_aw;
                  method Action put(Axi3WriteRequest#(32,id_width) v) if (vs_axi_gp[i].awready() != 0);
                      vs_axi_gp[i].awaddr(v.address);
                      vs_axi_gp[i].awburst(v.burst);
                      vs_axi_gp[i].awcache(v.cache);
                      vs_axi_gp[i].awid(v.id);
  