anchor.diff:      Reg#(Bit#(1)) fifo_wren_c_reg <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
   
       ClockGenIfc serdest_clk <- mkBUFIO(ibufds_clk);
  -    Vector#(5, ReadOnly#(Bit#(1))) ibufds_v;
  -    for (Integer i = 0; i < 5; i = i + 1)
  -        ibufds_v[i] <- mkIBUFDS(vita_data_p[i], vita_data_n[i]);
       Reg#(Bit#(1)) serdes_align_busy_temp <- mkReg(0);
       Reg#(Bit#(1)) serdes_align_busy_reg <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);
       Reg#(Bit#(1)) serdes_aligned_temp <- mkReg(0);
  
positive.code:         sync_bitslip <= ctrl_bitslip_serdes.read();
          dstate <= DValid;
          dcounter <= 3;
          iserdes_bitslip <= sync_bitslip;
      endrule
      rule state1_rule if (bvi_reset_reg != 0 && dstate == DValid);
          dcounter <= dcounter - 1;
          if (dcounter[2] == 1)
              begin
              dackint.send(1);
              dstate <= DLow;
              end
          Bit#(3) sric = sync_reset_inc_ce;
          sric[0] = 0;
          sric[1] = 0;
          sync_reset_inc_ce <= sric;
          sync_bitslip <= 0;
          iserdes_bitslip <= sync_bitslip;
      endrule
      rule state2_rule if (bvi_reset_reg != 0 && dstate == DLow);
          dackint.send(0);
          dstate <= DIdle;
          Bit#(3) sric = sync_reset_inc_ce;
          sric[0] = 0;
          sric[1] = 0;
          sync_reset_inc_ce <= sric;
          sync_bitslip <= 0;
          iserdes_bitslip <= sync_bitslip;
      endrule
  
      rule setrule;
  
negative.code:     Reg#(Bit#(3)) ctrl_samplein_i <- mkReg(0);
      Reg#(Bit#(16)) retrycounter <- mkReg(0);
      Reg#(Bit#(16)) gencounter <- mkReg(0);
      FIFO#(Bit#(1)) this_start_align_reg <- mkFIFO();
      FIFO#(Bit#(1)) start_handshake <- mkFIFO();
      FIFO#(Bit#(1)) end_handshake <- mkFIFO();
      Reg#(Bit#(1)) ctrl_bitslip <- mkReg(0);
  