anchor.diff:     interface PciewrapUser#(lanes)      user;
      interface PciewrapCfg#(lanes)       cfg;
      interface Server#(TLPData#(16), TLPData#(16)) tlp;
  +   interface PipeOut#(Bit#(64)) regChanges;
      interface Clock epPcieClock;
      interface Reset epPcieReset;
      interface Clock epPortalClock;
  
positive.code: import PCIEWRAPPER       ::*;
  import Bufgctrl           ::*;
  import PcieGearbox       :: *;
  
  `include "ConnectalProjectConfig.bsv"
  
  
negative.code:    interface pcie    = pcie_ep.pcie;
     interface PciewrapUser user = pcie_ep.user;
     interface PciewrapCfg cfg = pcie_ep.cfg;
     interface regChanges = mapPipe(pack, toPipeOut(changeFifo));
     interface Clock epPcieClock = clock125;
     interface Reset epPcieReset = reset125;
     interface Clock epPortalClock = portalClock;
  