anchor.diff:     endrule
   
      // ================================================================
  -   // MMIO (request addr is not cached mem)
  +   // MMIO (request addr is not in cached mem: pass thru to MMIO box)
   
      // These regs are used to slice 512-bit data into 64-bit slices, one per MMIO transaction
      Reg #(Bit #(Wd_Addr_Dma))                        rg_mmio_addr       <- mkRegU;
  
positive.code:    function Action fa_upd_cache_and_respond (Meta_State new_tag_state, Data rdata);
        action
  	 // Update cache tag
  	 let new_tag = DMA_Cache_Tag {tag_state: ((req_op == AXI4_OP_WR) ? META_MODIFIED : new_tag_state),
  				      tag_addr: addr};
  	 let new_tag_set = fn_mk_Tag_Set (new_tag);
  	 rf_tag_sets.upd (index, new_tag_set);
  	 if(verbosity >= 1)
  
negative.code:       end
     endrule
  
     // ================================================================
     // Handle downgrade-request from L2 (highest priority)
  
  