anchor.diff:        alu_outputs = fv_LOAD (inputs);
   
      else if (   (inputs.decoded_instr.opcode == op_STORE_FP))
  -      alu_outputs = fv_ST (inputs);
  +      alu_outputs = fv_STORE (inputs);
   
      else if (   (inputs.decoded_instr.opcode == op_FP)
               || (inputs.decoded_instr.opcode == op_FMADD)
  
positive.code: 
     let opcode = inputs.decoded_instr.opcode;
     let funct3 = inputs.decoded_instr.funct3;
     Bool legal_ST = (   (funct3 == f3_SB)
  		    || (funct3 == f3_SH)
  		    || (funct3 == f3_SW)
  `ifdef RV64
  		    || (funct3 == f3_SD)
  `endif
  `ifdef ISA_F
  		    || (funct3 == f3_FSW)
  `endif
  `ifdef ISA_D
  		    || (funct3 == f3_FSD)
  `endif
  		    );
  
     let alu_outputs = alu_outputs_base;
  
     // FP stores are not legal unless the MSTATUS.FS bit is set
     Bool legal_FP_ST = True;
  `ifdef ISA_F
     if (opcode == op_STORE_FP) begin
        legal_FP_ST = (fv_mstatus_fs (inputs.mstatus) != fs_xs_off);
  
        // note that the source data register for this store is in the FPR
        alu_outputs.rs_frm_fpr = True;
     end
  `endif
  
     alu_outputs.control   = ((legal_ST && legal_FP_ST) ? CONTROL_STRAIGHT
                                                        : CONTROL_TRAP);
     alu_outputs.op_stage2 = OP_Stage2_ST;
     alu_outputs.addr      = eaddr;
  
  
negative.code: 
  `ifdef ISA_F
     alu_outputs.fval2     = inputs.frs2_val;
     // For STORE_FP, source data register is in FP Regs
     alu_outputs.rs_frm_fpr = (opcode == op_STORE_FP);
  `endif
  
  `ifdef INCLUDE_TANDEM_VERIF
  