anchor.diff:              action
                  Bit#(TLog#(XLEN)) shamt = truncate(v2);    // NOTE: upper bits are unspecified in spec
   
  -               if      (decoded.funct10 == f10_ADD)  fa_finish_with_Rd(decoded.rd, pack(s_v1 + s_v2));
  -               else if (decoded.funct10 == f10_SUB)  fa_finish_with_Rd(decoded.rd, pack(s_v1 - s_v2));
  -               else if (decoded.funct10 == f10_SLL)  fa_finish_with_Rd(decoded.rd, (v1 << shamt));
  -               else if (decoded.funct10 == f10_SLT)  fa_finish_with_Rd(decoded.rd, ((s_v1 < s_v2) ? 1 : 0));
  -               else if (decoded.funct10 == f10_SLTU) fa_finish_with_Rd(decoded.rd, ((v1  < v2)  ? 1 : 0));
  -               else if (decoded.funct10 == f10_XOR)  fa_finish_with_Rd(decoded.rd, pack(s_v1 ^ s_v2));
  -               else if (decoded.funct10 == f10_SRL)  fa_finish_with_Rd(decoded.rd, (v1 >> shamt));
  -               else if (decoded.funct10 == f10_SRA)  fa_finish_with_Rd(decoded.rd, pack(s_v1 >> shamt));
  -               else if (decoded.funct10 == f10_OR)   fa_finish_with_Rd(decoded.rd, pack(s_v1 | s_v2));
  -               else if (decoded.funct10 == f10_AND)  fa_finish_with_Rd(decoded.rd, pack(s_v1 & s_v2));
  -
  -               else
  -                  fa_finish_with_exception(pc, exc_code_ILLEGAL_INSTRUCTION, ?);
  +               case(decoded.instr)
  +                  OP_ADD   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 + s_v2));
  +                  OP_SUB   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 - s_v2));
  +                  OP_SLL   :  fa_finish_with_Rd(decoded.rd, (v1 << shamt));
  +                  OP_SLT   :  fa_finish_with_Rd(decoded.rd, ((s_v1 < s_v2) ? 1 : 0));
  +                  OP_SLTU  :  fa_finish_with_Rd(decoded.rd, ((v1  < v2)  ? 1 : 0));
  +                  OP_XOR   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 ^ s_v2));
  +                  OP_SRL   :  fa_finish_with_Rd(decoded.rd, (v1 >> shamt));
  +                  OP_SRA   :  fa_finish_with_Rd(decoded.rd, pack(s_v1 >> shamt));
  +                  OP_OR    :  fa_finish_with_Rd(decoded.rd, pack(s_v1 | s_v2));
  +                  /*OP_AND*/
  +                  default  :  fa_finish_with_Rd(decoded.rd, pack(s_v1 & s_v2));
  +               endcase
   
                  if (cfg_verbose > 2) begin
                     $display("[%7d] Decoded: PC = %h, %s %s, %s, %s", csr_cycle, decoded.pc,
  -                        case(decoded.funct10)
  -                           f10_ADD  : "add";
  -                           f10_SUB  : "sub";
  -                           f10_SLL  : "sll";
  -                           f10_SLT  : "slt";
  -                           f10_SLTU : "sltu";
  -                           f10_XOR  : "xor";
  -                           f10_SRL  : "srl";
  -                           f10_SRA  : "sra";
  -                           f10_OR   : "or";
  -                           f10_AND  : "and";
  +                        case(decoded.instr)
  +                           OP_ADD  : "add";
  +                           OP_SUB  : "sub";
  +                           OP_SLL  : "sll";
  +                           OP_SLT  : "slt";
  +                           OP_SLTU : "sltu";
  +                           OP_XOR  : "xor";
  +                           OP_SRL  : "srl";
  +                           OP_SRA  : "sra";
  +                           OP_OR   : "or";
  +                           OP_AND  : "and";
                           endcase,
                           regNameABI[decoded.rd],
                           regNameABI[decoded.rs1],
  
positive.code: 
           function Action fa_exec_SYSTEM();
              action
                 // CSRRW
                 if (m_v_csr matches tagged Valid .csr_old_val &&& (decoded.funct3 == f3_CSRRW)) begin
                    fa_write_csr(decoded.csr, v1);
                    fa_finish_with_Rd(decoded.rd, csr_old_val);
                 end
  
                 // CSRRS
                 else if (m_v_csr matches tagged Valid .csr_old_val &&& (decoded.funct3 == f3_CSRRS)) begin
                    if (decoded.rs1 != 0) begin
                       Word csr_new_val = (csr_old_val | v1);
                       fa_write_csr(decoded.csr, csr_new_val);
                    end
                    fa_finish_with_Rd(decoded.rd, csr_old_val);
                 end
  
                 // CSRRC
                 else if (m_v_csr matches tagged Valid .csr_old_val &&& (decoded.funct3 == f3_CSRRC)) begin
                    if (decoded.rs1 != 0) begin
                       Word csr_new_val = (csr_old_val & (~ v1));
                       fa_write_csr(decoded.csr, csr_new_val);
                    end
                    fa_finish_with_Rd(decoded.rd, csr_old_val);
                 end
  
                 else begin
                    fa_finish_with_exception(pc, exc_code_ILLEGAL_INSTRUCTION, ?);
                 end
  
                 if (cfg_verbose > 2) begin
                    if ( (decoded.funct3 == f3_CSRRS) && (decoded.csr == csr_CYCLE) )
                       $display("[%7d] Decoded: PC = %h, rdcycle %s", csr_cycle, decoded.pc, regNameABI[decoded.rd]);
                    else if ( (decoded.funct3 == f3_CSRRS) && (decoded.csr == csr_INSTRET) )
                       $display("[%7d] Decoded: PC = %h, rdinstret %s", csr_cycle, decoded.pc, regNameABI[decoded.rd]);
                    else if ( (decoded.funct3 == f3_CSRRW) && (decoded.csr == csr_DCSR) )
                       $display("[%7d] Decoded: PC = %h, csrw dcsr, %s", csr_cycle, decoded.pc, regNameABI[decoded.rs1]);
                    else begin
                       $display("[%7d] Decoded: PC = %h, %s %s, 0x%h, %s", csr_cycle, decoded.pc,
                             case(decoded.funct3)
                                f3_CSRRW : "csrrw";
                                f3_CSRRS : "csrrs";
                                f3_CSRRC : "csrrc";
                                //f3_CSRRWI : "csrrwi";
                                //f3_CSRRSI : "csrrsi";
                                //f3_CSRRCI : "csrrci";
                                default  : "Unsupport";
                             endcase,
                             regNameABI[decoded.rd],
  
negative.code:                Word_S offset  = extend(unpack(decoded.imm13_SB));
                 Word   next_pc = pack(unpack(pc) + offset);
  
                 case(decoded.instr)
                    OP_BEQ   :  fa_finish_cond_branch(v1  == v2,    next_pc);
                    OP_BNE   :  fa_finish_cond_branch(v1  != v2,    next_pc);
                    OP_BLT   :  fa_finish_cond_branch(s_v1 <  s_v2, next_pc);
                    OP_BGE   :  fa_finish_cond_branch(s_v1 >= s_v2, next_pc);
                    OP_BLTU  :  fa_finish_cond_branch(v1  <  v2,    next_pc);
                    /* OP_BGEU */
                    default  :  fa_finish_cond_branch(v1  >= v2,    next_pc);
                 endcase
  
                 if (cfg_verbose > 2) begin
                    $display("[%7d] Decoded: PC = %h, %s %s, %s, 0x%h", csr_cycle, decoded.pc,
                                case(decoded.instr)
                                   OP_BEQ  : "beq";
                                   OP_BNE  : "bne";
                                   OP_BLT  : "blt";
                                   OP_BGE  : "bge";
                                   OP_BLTU : "bltu";
                                   OP_BGEU : "bgeu";
                                endcase,
                                regNameABI[decoded.rs1],
                                regNameABI[decoded.rs2],
  