anchor.diff:                                       || ((hdr_3dw.addr % 8192) == 1026)
                                        || ((hdr_3dw.addr % 8192) == 1027)
                                        ;
  -      Bool in_axi_addr_range         =  ((hdr_3dw.addr % 8192) == 1028)
  -                                     || ((hdr_3dw.addr % 8192) == 1029)
  -                                     || ((hdr_3dw.addr % 8192) == 1030)
  -                                     || ((hdr_3dw.addr % 8192) == 1031)
  -                                     || ((hdr_3dw.addr % 8192) == 1032)
  -                                     || ((hdr_3dw.addr % 8192) == 1039)
  -                                     || ((hdr_3dw.addr % 8192) == 1040)
  -                                     ;
         Bool is_config_read    =  tlp.sof
                                && (tlp.hit == 7'h01)
                                && (hdr_3dw.format == MEM_READ_3DW_NO_DATA)
  -                             && (!axiEnabledReg || !in_axi_addr_range)
                                ;
         Bool is_config_write   =  tlp.sof
                                && (tlp.hit == 7'h01)
                                && (hdr_3dw.format == MEM_WRITE_3DW_DATA)
                                && (hdr_3dw.pkttype != COMPLETION)
                                && !in_dma_command_addr_range
  -                             && (!axiEnabledReg || !in_axi_addr_range)
                                ;
         Bool is_axi_read       =  tlp.sof
  -                             && (tlp.hit == 7'h01)
  +                             && (tlp.hit != 7'h01)
                                && (hdr_3dw.format == MEM_READ_3DW_NO_DATA)
  -                             && in_axi_addr_range
  -			     && axiEnabledReg
                                ;
         Bool is_axi_write      =  tlp.sof
  -                             && (tlp.hit == 7'h01)
  +                             && (tlp.hit != 7'h01)
                                && (hdr_3dw.format == MEM_WRITE_3DW_DATA)
                                && (hdr_3dw.pkttype != COMPLETION)
  -                             && in_axi_addr_range
  -			     && axiEnabledReg
                                ;
         Bool is_dma_command    =  tlp.sof
                                && (tlp.hit == 7'h01)
  
positive.code:    Reg#(Bit#(32)) tlpOutCountReg <- mkReg(0);
  
     // Function to return a one-word slice of the tlpDataBramResponse
     function tlpDataBramResponseSlice(Bit#(3) i);
         begin
             Bit#(192) v = extend(pack(tlpDataBramResponse));
             return v[31 + (i*32) : 0 + (i*32)];
         end
     endfunction
  
  
negative.code: 	    method ActionValue#(Bit#(32)) writeData();
  	        busyReg <= False;
  	        writeDataFifo.deq;
  		return byteSwap(writeDataFifo.first.data);
  	    endmethod
  	    method Bit#(SizeOf#(TLPTag)) writeWid();
  		return extend(writeDataFifo.first.tag);
  