anchor.diff:  endmodule
   
   import "BVI" XsimSource =
  -module mkXsimSource#(Bit#(32) portal, Bool src_rdy, MsgBeat#(4) beat)(Empty);
  +module mkXsimSourceBVI#(Bit#(32) portal, Bool src_rdy, MsgBeat#(4) beat)(Empty);
       port portal = portal;
       port src_rdy = src_rdy;
       port beat = beat;
  +endmodule
  +module mkXsimSource#(MsgSource#(4) indication, Integer i)(Empty);
  +   mkXsimSourceBVI(fromInteger(i), indication.src_rdy, indication.beat());
  +   rule ind_dst_rdy;
  +      indication.dst_rdy(True);
  +   endrule
   endmodule
   
   interface MsgSinkR#(numeric type bytes_per_beat);
  
positive.code: endinterface
  
  import "BVI" XsimSink =
  module mkXsimSink#(Bit#(32) portal, Bool dst_rdy)(MsgSinkR#(4));
      port portal = portal;
      port dst_rdy = dst_rdy;
      method src_rdy src_rdy();
      method beat beat();
      schedule (src_rdy, beat) CF (src_rdy, beat);
  endmodule
  
  module mkXsimTop(Empty);
  
negative.code: `endif
         );
  
     mapM_(uncurry(mkXsimSource), zip(top.indications, genVector()));
     mapM_(uncurry(mkXsimSink), zip(top.requests, genVector()));
  endmodule
  