anchor.diff:  endfunction
   
   instance MkPhysMemSlave#(Axi4Slave#(axiAddrWidth,dataWidth,idWidth),addrWidth,dataWidth)
  -      provisos (Add#(axiAddrWidth,a__,addrWidth),Add#(b__, idWidth, 6));
  +      provisos (Add#(axiAddrWidth,a__,addrWidth),Add#(b__, idWidth, MemTagSize));
      module mkPhysMemSlave#(Axi4Slave#(axiAddrWidth,dataWidth,idWidth) axiSlave)(PhysMemSlave#(addrWidth,dataWidth));
         FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) arfifo <- mkFIFOF();
         FIFOF#(MemData#(dataWidth)) rfifo <- mkFIFOF();
  
positive.code: 
  function Axi4ReadRequest#(axiAddrWidth,idWidth) toAxi4ReadRequest(PhysMemRequest#(addrWidth,dataBusWidth) req)
     provisos (Add#(axiAddrWidth,a__,addrWidth)
  	     ,Add#(b__, idWidth, 6));
     Axi4ReadRequest#(axiAddrWidth,idWidth) axireq  = unpack(0);
     axireq.address = truncate(req.addr);
     axireq.id   = truncate(req.tag);
  
negative.code: endfunction
  function Axi4WriteRequest#(axiAddrWidth,idWidth) toAxi4WriteRequest(PhysMemRequest#(addrWidth,dataBusWidth) req)
     provisos (Add#(axiAddrWidth,a__,addrWidth)
  	     ,Add#(b__, idWidth, MemTagSize));
     Axi4WriteRequest#(axiAddrWidth,idWidth) axireq  = unpack(0);
     axireq.address = truncate(req.addr);
     axireq.id   = truncate(req.tag);
  