anchor.diff:  	 interface Put readData;
   	    method Action put(MemData#(dataBusWidth) md);
   	       busReadDataFifo.enq(md);
  -	       busReadDataData <= md.data;
  -	       busReadDataLast <= md.last;
   	    endmethod
   	 endinterface
         endinterface
  
positive.code:    let doneFifo <- mkFIFOF();
  
     let dataFifo <- mkSizedBRAMFIFOF(4096);
  
     AddressGenerator#(24,dataBusWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(24,dataBusWidth) writeAddrGenerator <- mkAddressGenerator();
  
     let readReqObj <- mkProbe();
     let readReqDest <- mkProbe();
     let readReqOffset <- mkProbe();
     let readDataDest <- mkProbe();
     let readDataData <- mkProbe();
     let readDataLast <- mkProbe();
     let readBeatAddr <- mkProbe();
     let readBeatByteCount <- mkProbe();
     let readBeatLast <- mkProbe();
     let busReadDataData <- mkProbe();
     let busReadDataLast <- mkProbe();
     let writeReqObj <- mkProbe();
     let writeReqDest <- mkProbe();
     let writeReqOffset <- mkProbe();
     let writeDataDest <- mkProbe();
     let writeDataData <- mkProbe();
     let writeDataLast <- mkProbe();
     let writeBeatAddr <- mkProbe();
     let writeBeatByteCount <- mkProbe();
     let writeBeatLast <- mkProbe();
     let writeDoneTag <- mkProbe();
     let writeDoneDest <- mkProbe();
  
     rule rl_rd_req;
        MemRequest req <- toGet(readReqFifo).get();
  
negative.code: 	 dataFifo.enq(md);
        else
  	 busWriteDataFifo.enq(md);
        if (md.last) begin
  	 writeDestFifo.deq();
  	 doneFifo.enq(tuple2(dest, md.tag));
        end
     endrule
  
     rule rl_wr_done;
  