anchor.diff:     endinterface
   
      interface Axi3ReadClient m_axi_read;
  -      method ActionValue#(Axi3ReadRequest#(40,12)) address() if (!debugReg);
  +      method ActionValue#(Axi3ReadRequest#(40,12)) address();
   	 let req = reqFifo.first();
   	 reqFifo.deq();
   	 let physAddr = paFifo.first();
  
positive.code: module mkAxiDMAWriteInternal#(Integer numRequests, Vector#(numWriteClients, DMAWriteClient#(dsz)) writeClients,
  			      DMAIndication dmaIndication)(AxiDMAWriteInternal#(dsz,dbytes))
     provisos(Add#(1,a__,dsz),
  	    Mul#(dbytes,8,dsz));
     SGListMMU sgl <- mkSGListMMU();
     
     FIFO#(DMAAddressRequest) reqFifo <- mkFIFO();
     FIFO#(DMAAddressRequest) dreqFifo <- mkSizedFIFO(numRequests);
     FIFO#(Bit#(40))        paFifo     <- mkFIFO();
  
negative.code:    interface Axi3Client#(40,dsz,dbytes,12) m_axi;
  endinterface
  
  interface ConfigureSglist;
     method Action configuring(Bool c);
     method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr);
     method Action readSglist(Bit#(32) pref, Bit#(40) addr);
  endinterface
  
  interface AxiDMAWriteInternal#(numeric type dsz, numeric type dbytes);
     interface DMAWrite write;
     interface Axi3WriteClient#(40,dsz,dbytes,12) m_axi_write;
     interface ConfigureSglist configure;
  endinterface
  
  interface AxiDMAReadInternal#(numeric type dsz, numeric type dbytes);
     interface DMARead read;
     interface Axi3ReadClient#(40,dsz,12) m_axi_read;
     interface ConfigureSglist configure;
  endinterface
  
  typedef enum {Idle, Translate, Address, Data, Done} InternalState deriving(Eq,Bits);
  