anchor.diff:        // Save new privilege and pc for ifetch
         rg_cur_priv <= new_priv;
         rg_next_pc  <= next_pc;
  -      rg_state    <= CPU_TRAP_FETCH;
  +
  +      // Note old MSTATUS.MXR for initiating FETCH in next phase
  +      rg_mstatus_MXR <= mstatus [19];
  +
  +      // Note SSTATUS.SUM for initiating FETCH in next phase
  +`ifdef ISA_PRIV_S
  +      rg_sstatus_SUM <= (csr_regfile.read_sstatus) [18];
  +`else
  +      rg_sstatus_SUM <= 0;
  +`endif
  +      rg_state    <= CPU_SPLIT_FETCH;
   
         stage1.set_full (False);
         stage2.set_full (False);
  
positive.code:       end
     endrule : rl_stage1_trap
  
     // Initiate the instruction fetch from the new_pc on a trap. These actions
     // were formerly part of the stage1 and stage2 trap rules. Separated to
     // break a long timing path
     rule rl_trap_fetch (rg_state == CPU_TRAP_FETCH);
        let new_epoch <- fav_update_epoch;
        let m_old_pc   = tagged Invalid;
        fa_start_ifetch (new_epoch, m_old_pc, rg_next_pc, rg_cur_priv);
        stageF.set_full (True);
        rg_state <= CPU_RUNNING;
  
        stageD.set_full (False);
     endrule : rl_trap_fetch
  
     // ================================================================
  
negative.code:    Reg #(Priv_Mode)  rg_cur_priv <- mkReg (m_Priv_Mode);
     Reg #(Epoch)      rg_epoch    <- mkRegU;
  
     // Save next_pc across split-phase FENCE.I and other split-phase ops. This
     // register is also used for initiating fetches on a trap or external
     // interrupt
     Reg #(WordXL) rg_next_pc <- mkRegU;
  
     // Save sstatus_SUM and mstatus_MXR to initiate fetches on an external
     // interrupt
     Reg #(Bit #(1)) rg_sstatus_SUM <- mkRegU;
     Reg #(Bit #(1)) rg_mstatus_MXR <- mkRegU;
  
     // ----------------
     // Pipeline stages
  