anchor.diff:     interface MemWriteEngineServer#(userWidth) writeServer;
   endinterface
   
  -module mkMemWriteChannel#(Integer bufferSizeBytes, Integer channelNumber)(MemWriteChannel#(busWidth, userWidth, cmdQDepth))
  +module mkMemWriteChannel#(Integer bufferSizeBytes, Integer channelNumber,
  +			  PipeOut#(Bit#(MemTagSize)) writeGntPipe, PipeOut#(Bit#(MemTagSize)) writeDonePipe)
  +   (MemWriteChannel#(busWidth, userWidth, cmdQDepth))
      provisos ( Div#(busWidth,8,busWidthBytes)
   	     ,Log#(busWidthBytes,beatShift)
   	     ,Add#(1, d__, userWidth)
  
positive.code:              ,FunnelPipesPipelined#(1, numServers, MemRequest, 2)
               ,FunnelPipesPipelined#(1, numServers, Bit#(MemTagSize), 2)
  	     );
     Vector#(numServers, MemWriteChannel#(busWidth,userWidth,cmdQDepth)) writeChannels <- genWithM(mkMemWriteChannel(bufferSizeBytes));
     function PipeOut#(MemRequest) writeChannelDmaWriteReq(Integer i);
        return writeChannels[i].writeReq;
     endfunction
  
negative.code:    Reg#(Bool)         reqInFlight <- mkReg(False);
     FIFOF#(MemRequest)          writeReqFifo <- mkFIFOF();
     FIFOF#(MemData#(userWidth)) writeDataFifo <- mkFIFOF();
     FunnelPipe#(1,numServers,MemRequest,2) reqFunnel <- mkFunnelPipesPipelined(genWith(writeChannelDmaWriteReq));
     FunnelPipe#(1,numServers,MemData#(userWidth),2) dataFunnel <- mkFunnelPipesPipelined(genWith(writeChannelDmaWriteData));
  
     rule rl_arbitration if (!reqInFlight);
        let req <- toGet(reqFunnel[0]).get();
  