anchor.diff:  // DM-to-CPU GPR tap (for writes to GPRs)
   
   interface DM_GPR_Tap_IFC;
  -   interface MemoryClient #(5, XLEN)  client;
  -   interface MemoryServer #(5, XLEN)  server;
  +   interface Client #(DM_CPU_Req #(5,  XLEN), DM_CPU_Rsp #(XLEN))  client;
  +   interface Server #(DM_CPU_Req #(5,  XLEN), DM_CPU_Rsp #(XLEN))  server;
      interface Get #(Trace_Data)        trace_data_out;
   endinterface
   
   (* synthesize *)
   module mkDM_GPR_Tap (DM_GPR_Tap_IFC);
      // req from DM
  -   FIFOF #(MemoryRequest #(5, XLEN)) f_req_in     <- mkFIFOF;
  +   FIFOF #(DM_CPU_Req #(5,  XLEN)) f_req_in     <- mkFIFOF;
      // req to CPU
  -   FIFOF #(MemoryRequest #(5, XLEN)) f_req_out    <- mkFIFOF;
  +   FIFOF #(DM_CPU_Req #(5,  XLEN)) f_req_out    <- mkFIFOF;
      // resp CPU->DM
  -   FIFOF #(MemoryResponse #(XLEN))   f_rsp        <- mkFIFOF;
  +   FIFOF #(DM_CPU_Rsp #(XLEN))     f_rsp        <- mkFIFOF;
      // Tap to TV
  -   FIFOF #(Trace_Data)               f_trace_data <- mkFIFOF;
  +   FIFOF #(Trace_Data)             f_trace_data <- mkFIFOF;
   
      rule request;
         let req <- pop (f_req_in);
  
positive.code: import GetPut        :: *;
  import ClientServer  :: *;
  import Connectable   :: *;
  import Memory        :: *;
  
  // ----------------
  // BSV additional libs
  
negative.code: // ================================================================
  // Project imports
  
  import ISA_Decls      :: *;
  import DM_CPU_Req_Rsp :: *;
  import TV_Info        :: *;
  
  import AXI4_Types   :: *;
  import Fabric_Defs  :: *;
  