anchor.diff:  
   typedef (function Module#(PortalTop#(32, 64, ipins)) mkpt(FromPS7 fromPS7)) MkPortalTop#(type ipins);
   
  -module [Module] mkZynqTopFromPortal#(MkPortalTop#(ipins) constructor)(ZynqTop#(ipins));
  +module [Module] mkZynqTopFromPortal#(Clock io_vita_clk_out_p, Clock io_vita_clk_out_n, MkPortalTop#(ipins) constructor)(ZynqTop#(ipins));
  +   Clock io_vita_clk <- XilinxCells::mkClockIBUFDS(io_vita_clk_out_p, io_vita_clk_out_n);
      // B2C converts a bit to a clock, enabling us to break the apparent cycle
      Vector#(4, B2C) fclk <- replicateM(mkB2C());
      B2C mainclock = fclk[0];
  
positive.code: import Leds              :: *;
  import Top               :: *;
  import AxiMasterSlave    :: *;
  import XbsvXilinxCells   :: *;
  import PS7LIB::*;
  import PPS7LIB::*;
  
negative.code:    interface unused_reset3 = fclk[3].r;
  endmodule
  
  module mkImageonZynqTop#(Clock io_vita_clk_out_p, Clock io_vita_clk_out_n)(ZynqTop#(ImageonVita));
     let top <- mkZynqTopFromPortal(io_vita_clk_out_p, io_vita_clk_out_n, mkPortalTop);
     return top;
  endmodule
  