anchor.diff:  (* always_ready, always_enabled *)
   interface AxiEthBvi;
       interface AxiethbviAxi     axi;
  -    interface AxiethbviAxis     axis;
       interface AxiethbviGt     gt0;
       interface AxiethbviGtref     gtref;
       method Bit#(1)     interrupt();
  
positive.code:     interface AxiethbviUserclk     userclk;
  endinterface
  import "BVI" axi_ethernet_0 =
  module mkAxiEthBvi#(Clock s_axi_clk, Reset s_axi_reset)(AxiEthBvi);
      default_clock clk();
      default_reset rst();
      input_clock (s_axi_lite_clk) = s_axi_clk;
      input_reset (s_axi_lite_resetn) = s_axi_reset;
      interface AxiethbviAxi     axi;
          method rxd_arstn(axi_rxd_arstn) enable((*inhigh*) EN_axi_rxd_arstn);
          method rxs_arstn(axi_rxs_arstn) enable((*inhigh*) EN_axi_rxs_arstn);
          method txc_arstn(axi_txc_arstn) enable((*inhigh*) EN_axi_txc_arstn);
          method txd_arstn(axi_txd_arstn) enable((*inhigh*) EN_axi_txd_arstn);
      endinterface
      interface AxiethbviAxis     axis;
          method clk(axis_clk) enable((*inhigh*) EN_axis_clk);
      endinterface
      interface AxiethbviGt     gt0;
          method gt0_qplloutclk_out qplloutclk_out();
  
negative.code:     method Action      txd_arstn(Bit#(1) v);
  endinterface
  (* always_ready, always_enabled *)
  interface AxiethbviGt;
      method Bit#(1)     qplloutclk_out();
      method Bit#(1)     qplloutrefclk_out();
  