anchor.diff:  typedef enum { DIdle, DValid, DLow} DState deriving (Bits,Eq);
   typedef enum { HIdle, HHigh, HLow} HState deriving (Bits,Eq);
   typedef enum { QIdle, QTrain, QOn, QOff} QState deriving (Bits,Eq);
  +typedef enum { AIdle, ADelay, AWDelay, AEdge, ACEdge, AWait, ACompare, AValid, A1Changed, A1Stable, ASecond, AFound, AResetman, AStart, AAlign, ADone } AState deriving (Bits,Eq);
   
   module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
       Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden, TrainRotate trainrot)(IserdesDatadeser);
   
       Clock defaultClock <- exposeCurrentClock();
       Reset defaultReset <- exposeCurrentReset();
  -    Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdes_reset);
       FIFO18 dfifo <- mkFIFO18(serdes_clock);
       IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
           cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
  
positive.code:         iserdes_bitslip <= sync_bitslip;
          if (dstate == DIdle && dreqpipe1 == 1)
              begin
              sric = serbvi.ctrl_reset_inc_ce();
              sbs = serbvi.ctrl_bitslip();
              dc = 3;
              ds = DValid;
              end
  
negative.code:         dackint_last <= dackint.read();
          if (dackint.read() == 1 && dackint_last == 0)
              ctrl_data <= dout;
          for (Integer i = 0; i < 9; i = i + 1)
              edgeo[i] = dout[i] ^ dout[i+1];
          edgeo[9] = dout[0] ^ dout[9];
          edge_int <= edgeo;
          edge_intor_reg <= pack(edgeo != 0);
          dfifo.di({6'b0,dout});
          dfifo.wren(fifo_wren_sync.read());
      endrule
  