anchor.diff:  (* synthesize *)
   module mkMatchTable_port_mapping(MatchTable_port_mapping);
   
  +   Reg#(Bit#(32)) cycle <- mkReg(0);
      FIFOF#(MatchInput_port_mapping) fifo_in_port_mapping <- mkSizedFIFOF(1);
      FIFOF#(ActionSpec_port_mapping) fifo_out_action_data <- mkSizedFIFOF(1);
   
  -   FIFOF#(Bit#(9)) match_cfFifo <- mkSizedFIFOF(1);
  +   CAM#(16, Bit#(9), Bit#(9)) cam <- mkCAM();
   
  -   CAM#(16, Bit#(9), Bit#(9)) cam <- mkCAM();
  -   Reg#(Bit#(32)) cycle <- mkReg(0);
  +   BRAM_Config cfg = defaultValue;
  +   cfg.latency = 1;
  +   BRAM2Port#(Bit#(9), Bit#(16)) actionRam <- mkBRAM2Server(cfg);
   
      rule every1;
         cycle <= cycle + 1;
      endrule
   
  -   rule get_phv;
  +   rule cam_lookup;
         let v <- toGet(fifo_in_port_mapping).get;
         $display("%x: match table get_phv %x", cycle, v);
  -      match_cfFifo.enq(1);
  +      cam.readPort.request.put(pack(v));
      endrule
   
  -   rule doMatch;
  -      let v <- toGet(match_cfFifo).get;
  +   rule action_param_lookup;
  +      let v <- cam.readPort.response.get;
  +
  +   rule action_param_output;
         $display("%x: match table domatch %x", cycle, v);
  -      cam.readPort.request.put(v);
  -   endrule
  -
  -   rule getMatchResult;
  -      let entry <- cam.readPort.response.get;
  -      $display("%x: match table domatch %x", cycle, entry);
  -      fifo_out_action_data.enq(ActionSpec_port_mapping{bd:0});
  +      // either match or not match
  +      if (isValid(v)) begin
  +         fifo_out_action_data.enq(ActionSpec_port_mapping{bd:0});
  +      end
  +      else begin
  +         $display("packet match missed");
  +      end
      endrule
   
      interface Put put_entry;
         method Action put(MatchSpec_port_mapping e);
  -         cam.writePort.put(tuple2(zeroExtend(pack(e)), pack(e)));
  +         cam.writePort.put(tuple2(pack(e), pack(e)));
         endmethod
      endinterface
   
  
positive.code:    FIFOF#(MatchInput_bd) fifo_in_bd <- mkSizedFIFOF(1);
     FIFOF#(ActionSpec_bd) fifo_out_action_data <- mkSizedFIFOF(1);
  
     FIFOF#(Bit#(16)) match_cfFifo <- mkSizedFIFOF(1);
  
     CAM#(16, Bit#(16), Bit#(16)) cam <- mkCAM();
  
     rule get_phv;
        let v <- toGet(fifo_in_bd).get;
        match_cfFifo.enq(1);
     endrule
  
     rule doMatch;
        let v <- toGet(match_cfFifo).get;
        cam.readPort.request.put(zeroExtend(v));
     endrule
  
     rule getMatchResult;
        let entry <- cam.readPort.response.get;
        fifo_out_action_data.enq(ActionSpec_bd{vrf:0});
     endrule
  
  
negative.code: import Types::*;
  import SimpleCAM::*;
  
  interface MatchTable_port_mapping;
     interface PipeIn#(MatchInput_port_mapping) phv_in;
     interface PipeOut#(ActionSpec_port_mapping) action_data;
  