anchor.diff:  
   `include "ProcConfig.bsv"
   import Vector::*;
  +import FIFO::*;
  +import GetPut::*;
   import BuildVector::*;
   import Cntrs::*;
   import Types::*;
  
positive.code:             // train branch predictor if needed 
              // since we can only do 1 training in a cycle, split the rule
              // XXX not training JAL, reduce chance of conflicts
              (* split *)
              if(x.iType == Jr || x.iType == Br) (* nosplit *) begin
                  inIfc.fetch_train_predictors(
                      x.controlFlow.pc, x.controlFlow.nextPc, x.iType,
                      x.controlFlow.taken, x.dpTrain, False
                  );
              end
          end
      endrule
  
      interface recvBypass = map(getRecvBypassIfc, bypassWire);
  
negative.code:     // speculation
      Maybe#(SpecTag) spec_tag;
  } AluExeToFinish deriving(Bits, Eq, FShow);
  
  typedef struct {
      Addr pc;
      Addr nextPc;
      IType iType;
      Bool taken;
      DirPredTrainInfo dpTrain;
      Bool mispred;
  } AluExeTrainBP deriving(Bits, Eq, FShow);
  
  // XXX currently ALU/Br should not have any exception, so we don't have cause feild above
  // TODO FIXME In future, if branch target is unaligned to 4 bytes, we may have exception
  