anchor.diff:     PhysMemSlave#(20,32) bootRomMemSlave      <- mkPhysMemToBram(bootRom);
      PhysMemSlave#(21,32) memSlaveMux          <- mkPhysMemSlaveMux(vec(bootRomMemSlave, deviceSlaveMux));
   
  +   let memReadClients  <- mapM(mkMemReadClient(objId), vec(m_axi_mm2s, m_axi_sg));
  +   let memWriteClients <- mapM(mkMemWriteClient(objId), vec(m_axi_s2mm, m_axi_sg));
  +
   `ifdef IncludeFlash
      PhysMemSlave#(26,16) bpiFlashSlave <- mkPhysMemToBram(bpiFlash.server);
   `endif
  -
      FIFOF#(Bit#(32)) dfifo <- mkFIFOF();
      FIFOF#(Bit#(32)) flashdfifo <- mkFIFOF();
   
  
positive.code: import Probe::*;
  
  import ConnectalXilinxCells::*;
  import ConnectalConfig::*;
  import CtrlMux::*;
  import HostInterface::*;
  
negative.code:       axiIicBvi.scl.i(sclIOBuf.o);
     endrule
  
     FIFOF#(Tuple3#(DmaChannel,Bool,MemRequest)) traceFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);
     FIFOF#(Tuple3#(DmaChannel,Bool,MemRequest)) traceFifo0 <- mkFIFOF();
     FIFOF#(Tuple3#(DmaChannel,Bool,MemRequest)) traceFifo1 <- mkFIFOF();
     PipeIn#(Tuple3#(DmaChannel,Bool,MemRequest)) tracePipe = toPipeIn(traceFifo0);
     FIFOF#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);
     FIFOF#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataFifo0 <- mkFIFOF();
     FIFOF#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataFifo1 <- mkFIFOF();
     PipeIn#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataPipe = toPipeIn(traceDataFifo0);
     let trace0Cnx <- mkConnection(toGet(traceFifo0), toPut(traceFifo));
     let trace1Cnx <- mkConnection(toGet(traceFifo), toPut(traceFifo1));
     rule rl_trace1;
        match { .chan, .write, .req } <- toGet(traceFifo1).get();
        ind.traceDmaRequest(chan, write, truncate(req.sglId), truncate(req.offset), extend(req.burstLen));
     endrule
     let traceData0Cnx <- mkConnection(toGet(traceDataFifo0), toPut(traceDataFifo));
     let traceData1Cnx <- mkConnection(toGet(traceDataFifo), toPut(traceDataFifo1));
     rule rl_trace_data;
        match { .chan, .write, .md } <- toGet(traceDataFifo1).get();
        ind.traceDmaData(chan, write, md.data, md.last);
     endrule
  
     let traceReadClients <- mapM(uncurry(mkTraceReadClient(tracePipe,traceDataPipe)),
  				zip(vec(DMA_TX, DMA_SG),
  				    memReadClients));
     let traceWriteClients <- mapM(uncurry(mkTraceWriteClient(tracePipe,traceDataPipe)),
  				 zip(vec(DMA_RX, DMA_SG),
  				     memWriteClients));
  
     interface SpikeHwRequest request;
        method Action reset();
  	 newReset.assertReset();
  