anchor.diff:        let rsp = DM_CPU_Rsp {ok: True, data: data};
         f_csr_rsps.enq (rsp);
         if (cur_verbosity > 1)
  -	 $display ("%0d: CPU.rl_debug_read_csr: csr %0d => 0x%0h",
  +	 $display ("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h",
   		   mcycle, csr_addr, data);
      endrule
   
  
positive.code:       f_gpr_rsps.enq (rsp);
  
        if (cur_verbosity > 1)
  	 $display ("%0d: CPU.rl_debug_write_gpr: reg %0d <= 0x%0h",
  		   mcycle, regname, data);
     endrule
  
  
negative.code:       let rsp = DM_CPU_Rsp {ok: False, data: ?};
        f_gpr_rsps.enq (rsp);
  
        if (cur_verbosity > 1) $display ("%0d: %m.rl_debug_gpr_access_busy", mcycle);
     endrule
  
     // ----------------
  