anchor.diff:      no_reset;
       port DIP = 0;
   
  -    method          reset(RST) enable((*inhigh*) en9) clocked_by (clkdiv);
  +    method          reset(RST) enable((*inhigh*) en9) clocked_by (clock);
       method          di(DI) enable((*inhigh*) en0) clocked_by (clkdiv);
       method          rden(RDEN) enable((*inhigh*) en2) clocked_by (clock);
       method          wren(WREN) enable((*inhigh*) en3) clocked_by (clock);
  
positive.code:    method Action                 delay_wren(Bit#(1) v);
     method Action                 fifo_wren(Bit#(1) v);
     method Action                 reset(Bit#(1) v);
     method Bit#(1)                fifo_wren_sync();
     method Bit#(1)                fifo_reset();
     method Bit#(10)               dataout();
  
negative.code:       method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
        method                  fifo_wren(FIFO_WREN) enable((*inhigh*) en10) clocked_by (clkdiv);
        method FIFO_WREN_SYNC   fifo_wren_sync() clocked_by (clock);
        method FIFO_RESET       fifo_reset() clocked_by(clock);
        method                  delay_wren(DELAY_WREN) enable((*inhigh*) en11) clocked_by (clkdiv);
        method                  reset(RESET) enable((*inhigh*) en17) clocked_by (clkdiv);
        method                  serreset(SERRESET) enable((*inhigh*) en16) clocked_by (clkdiv);
        method FIFO_DATAOUT  dataout() clocked_by(clkdiv);
     schedule (serreset, fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
           CF (serreset, fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  