anchor.diff:        // Save new privilege and pc for ifetch
         rg_cur_priv <= new_priv;
         rg_next_pc  <= next_pc;
  -      rg_state <= CPU_TRAP_FETCH;
  +
  +      // Note old MSTATUS.MXR for initiating FETCH in next phase
  +      rg_mstatus_MXR <= mstatus [19];
  +
  +      // Note SSTATUS.SUM for initiating FETCH in next phase
  +`ifdef ISA_PRIV_S
  +      rg_sstatus_SUM <= (csr_regfile.read_sstatus) [18];
  +`else
  +      rg_sstatus_SUM <= 0;
  +`endif
  +
  +      rg_state <= CPU_SPLIT_FETCH;
         stage1.set_full (False);
   
         // Tandem Verification and Debug related actions
  
positive.code:    Reg #(Priv_Mode)  rg_cur_priv <- mkReg (m_Priv_Mode);
     Reg #(Epoch)      rg_epoch    <- mkRegU;
  
     // Save next_pc across split-phase FENCE.I and other split-phase ops
     Reg #(WordXL) rg_next_pc <- mkRegU;
  
     // ----------------
     // Pipeline stages
  
negative.code: `endif
  	      CPU_RUNNING,          // Normal operation
  	      CPU_TRAP,
  	      CPU_SPLIT_FETCH,      // To initiate IFetch after traps/interrupts/RET
  	      CPU_CSRRX_RESTART,    // Restart pipe after a CSRRX instruction
  	      CPU_FENCE_I,          // While waiting for FENCE.I to complete in Near_Mem
  	      CPU_FENCE,            // While waiting for FENCE to complete in Near_Mem
  