anchor.diff:     Reset epReset250 <- mkAsyncReset(4, _ep.trn.reset_n, epClock250);
      Clock epClock125 = _ep.trn.clk2;
      Reset epReset125 <- mkAsyncReset(4, _ep.trn.reset_n, epClock125);
  -   Clock epClock0675 = _ep.trn.clk3;
  -   Reset epReset0675 <- mkAsyncReset(4, _ep.trn.reset_n, epClock0675);
  +   Clock epClock0625 = _ep.trn.clk3;
  +   Reset epReset0625 <- mkAsyncReset(4, _ep.trn.reset_n, epClock0625);
   
      // Extract some status info from the PCIE endpoint. These values are
      // all in the epClock250 domain, so we have to cross them into the
  
positive.code:    interface Reset reset250;
     interface Clock clock125;
     interface Reset reset125;
     interface Clock clock0675;
     interface Reset reset0675;
     interface Clock clock200;
     interface Reset reset200;
     (* prefix = "" *)
  
negative.code:    interface reset250 = epReset250;
     interface clock125 = epClock125;
     interface reset125 = epReset125;
     interface clock0625 = epClock0625;
     interface reset0625 = epReset0625;
     interface clock200 = sys_clk_200mhz_buf;
     interface reset200 = sys_clk_200mhz_reset;
  
  