anchor.diff:  
   
   module mkBsimTop();
  -   Top top <- mkZynqTop;
  +   PortalDmaTop top <- mkPortalDmaTop();
      let wf <- mkPipelineFIFO;
      let init_seq = (action 
   		      initPortal(0);
  
positive.code: // defined by user
  import Memcpy::*;
  
  interface AxiTop;
     interface StdAxi3Slave     ctrl;
     interface StdAxi3Master    m_axi;
     interface ReadOnly#(Bool)  interrupt;
     interface LEDS             leds;
  endinterface
  
  module mkAxiTop(Top);
  
     DMAIndicationProxy dmaIndicationProxy <- mkDMAIndicationProxy(9);
     // dma read channel 0 is reserved for memcpy read path
  
negative.code: endmodule
  
  (* no_default_clock, no_default_reset *)
  module [Module] mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
                            Clock sys_clk_p,     Clock sys_clk_n,
                            Reset pci_sys_reset_n)
                           (VC707_FPGA);
  
     let contentId = 64'h4563686f;
  
     let top <- mkPcieDmaTop(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n, contentId, mkPortalDmaTop);
     return top;
  endmodule: mkPcieTop
  