anchor.diff:  } FetchState deriving (Bits, Eq, FShow);
   
   typedef struct {
  +    Bool poisoned;
       Addr pc;
   } ExecuteState deriving (Bits, Eq, FShow);
   
  
positive.code:     Ehr#(4, Maybe#(FetchState)) fetchStateEhr <- mkEhr(tagged Invalid);
      Ehr#(4, Maybe#(ExecuteState)) executeStateEhr <- mkEhr(tagged Invalid);
      Ehr#(4, Maybe#(WriteBackState)) writeBackStateEhr <- mkEhr(tagged Invalid);
  
      FIFO#(VerificationPacket) verificationPackets <- mkFIFO;
  
  
negative.code:                 interrupt: isInterrupt,
                  cause: trapCause } );
  
          if (maybeNextPc matches tagged Valid .replayPc) begin
              // This instruction is not writing to the register file
              // it is either an instruction that requires flushing the pipeline
              // or it caused an exception
              fetchStateEhr[0] <= tagged Valid FetchState{ pc: replayPc };
              // kill other instructions
              if (executeStateEhr[0] matches tagged Valid .validExecuteState) begin
                  executeStateEhr[0] <= tagged Valid ExecuteState{ poisoned: True, pc: validExecuteState.pc };
              end
          end else begin
              // This instruction retired
              // write to the register file
  