anchor.diff:          slave_data.oclk(0);
           slave_data.oclkb(0);
           slave_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
  +        //slave_data.reset(iodelay_reset_inc_ce[2]);
  +        iserdes_data <= dout;
           serbvi.dataout(dout);
           dfifo.di({6'b0,dout});
       endrule
  +    //rule bozodata_rule;
  +        //serbvi.dataout(iserdes_data);
  +    //endrule
   
       rule wren_dfifo_rule;
           dfifo.wren(serbvi.fifo_wren_sync());
  +        //dfifo.wren(fifo_wren_sync);
       endrule
   
       rule serdesrule;
  
positive.code:             fwsync = dfifo_wren_r;
          else
              fwsync = bvi_fifo_wren_wire;
          //ireset_inc_ce <= sync_ric;
          iserdes_bitslip <= sync_bitslip;
          if (dstate == DIdle && dreqpipe1 == 1)
              begin
              serbvi.sync_reset_inc_ce(serbvi.ctrl_reset_inc_ce());
              sync_bitslip <= serbvi.ctrl_bitslip();
              dc = 3'b011;
              ds = DLow;
              end
          if (dstate == DValid && dcounter >= 3'b100)
              begin
              da = 1;
              ds = DLow;
  
negative.code:     Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(1)) bvi_fifo_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) iserdes_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe0 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe1 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_reset_r <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_wren_sync <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      //outputs
      Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dackint <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      ReadOnly#(Bit#(3)) samplein_null <- mkNullCrossingWire(serdes_clock, serbvi.samplein());
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
          let ds = dstate;
          let dc = dcounter;
          let da = dackint;
          let sric = sync_reset_inc_ce;
          let sbs = 0;
          let fwsync = 0;
    
          dc = dc - 1;
  