anchor.diff:     endrule
   `endif
   
  -   let top <- constructor(`CLOCK_ARG clocked_by mainclock, reset_by mainreset);
  +   PortalTop#(32, 64, PinType, NumberOfMasters) top <- mkPortalTop(`CLOCK_ARG clocked_by mainclock, reset_by mainreset);
      mkConnection(ps7, top, clocked_by mainclock, reset_by mainreset);
   
      let intr_mux <- mkInterruptMux(top.interrupt);
  
positive.code: import AxiDma            :: *;
  
  `ifdef USES_FCLK1
  `define CLOCK_DECL Clock clk1
  `define CLOCK_ARG  ps7.fclkclk[1],
  `else
  `define CLOCK_DECL
  `define CLOCK_ARG
  `endif
  
  
negative.code:    interface Vector#(4, Reset) deleteme_unused_reset;
  endinterface
  
  module mkZynqTop(ZynqTop);
     PS7 ps7 <- mkPS7();
     Clock mainclock = ps7.fclkclk[0];
     Reset mainreset = ps7.fclkreset[0];
  