anchor.diff:  `ifndef BSIM
      interface StdAxi3Master m_axi = axi_master;
   `endif
  +endmodule
  +
  +module mkZynqTop(AxiTop);
  +   let top <- mkAxiTop();
  +   return top;
   endmodule
   
   import "BDPI" function Action      initPortal(Bit#(32) d);
  
positive.code: // defined by user
  import Memcpy::*;
  
  interface Top;
     interface StdAxi3Slave     ctrl;
     interface StdAxi3Master    m_axi;
     interface ReadOnly#(Bool)  interrupt;
     interface LEDS             leds;
  endinterface
  
  module mkZynqTop(Top);
  
     DMAIndicationProxy dmaIndicationProxy <- mkDMAIndicationProxy(9);
     // dma read channel 0 is reserved for memcpy read path
  
negative.code: import StmtFSM::*;
  import FIFO::*;
  
  // for PCIE
  import Connectable       :: *;
  import Xilinx            :: *;
  import XilinxPCIE        :: *;
  import Xilinx7PcieBridge :: *;
  import PcieToAxiBridge   :: *;
  
  // portz libraries
  import AxiMasterSlave::*;
  