anchor.diff:  endmodule
   
   module mkSpiTestBench(Empty);
  +   Clock defaultClock <- exposeCurrentClock;
  +   Reset defaultReset <- exposeCurrentReset;
  +
      Bit#(20) slaveV = 20'h96ed5;
      Bit#(20) masterV = 20'h8baeb;
      let verbose = False;
   
  -   SPI#(Bit#(20)) spi <- mkSPI(4, True);
  +   SPI#(Bit#(20)) spi <- mkSPI(4, False);
      Reg#(Bit#(20)) slaveCount <- mkReg(20, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
      Reg#(Bit#(20)) slaveValue <- mkReg(slaveV, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
      Reg#(Bit#(20)) responseValue <- mkReg(0, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
  +   SyncBitIfc#(Bit#(1)) sync_sel_n <- mkSyncBits(0, defaultClock, defaultReset, spi.pins.clock, spi.pins.deleteme_unused_reset);
  +
  +   Probe#(Bit#(1)) probeSelN <- mkProbe(clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
  +   Probe#(Bit#(1)) probeMiso <- mkProbe(clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
  +   Probe#(Bit#(1)) probeMosi <- mkProbe(clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);
  +
  +   rule probePins;
  +      probeSelN <= spi.pins.sel_n;
  +      probeMosi <= spi.pins.mosi;
  +   endrule
   
      rule slaveIn if (spi.pins.sel_n == 0);
         slaveCount <= slaveCount - 1;
  
positive.code:       method Action miso(Bit#(1) v);
           misoWire <= v;
        endmethod
        interface Clock clock = invert_clk ? clockInverter.slowClock : defaultClock;
        interface Clock deleteme_unused_clock = invert_clk ? defaultClock : clockInverter.slowClock;
        interface Reset deleteme_unused_reset = defaultReset;
     endinterface: pins
  
negative.code: 
     let once <- mkOnce(action
        if(verbose) $display("master sending %h; slave sending %h", masterV, slaveV);
        $dumpvars();
        spi.request.put(masterV);
        endaction);
     rule foobar;
  