anchor.diff:  module mkPortalCtrlMemSlave#(Bit#(dataWidth) ifcId, PortalInterrupt#(dataWidth) intr)
      (PortalCtrlMemSlave#(addrWidth, dataWidth))
      provisos(Add#(d__, dataWidth, TMul#(dataWidth, 2)));
  -   
  -   AddressGenerator#(addrWidth,dataWidth) ctrlReadAddrGenerator  <- mkAddressGenerator();
  -   AddressGenerator#(addrWidth,dataWidth) ctrlWriteAddrGenerator <- mkAddressGenerator();
  -   FIFO#(MemData#(dataWidth))        ctrlWriteDataFifo <- mkFIFO();
  -   FIFO#(Bit#(MemTagSize))        ctrlWriteDoneFifo <- mkFIFO();
  +   AddressGenerator#(addrWidth,dataWidth) fifoReadAddrGenerator  <- mkAddressGenerator();
  +   AddressGenerator#(addrWidth,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();
  +   FIFO#(Bit#(MemTagSize))                fifoWriteDoneFifo <- mkFIFO();
  +   FIFO#(MemData#(dataWidth))             fifoWriteDataFifo <- mkFIFO();
      Reg#(Bit#(dataWidth)) num_portals_reg <- mkReg(0);
  -
      Reg#(Bool) interruptEnableReg <- mkReg(False);
      Reg#(Bit#(TMul#(dataWidth,2))) cycle_count <- mkReg(0);
      Reg#(Bit#(dataWidth))    snapshot <- mkReg(0);
  
positive.code: 	 endinterface
        endinterface: read_server
        interface PhysMemWriteServer write_server; 
  	 interface Put writeReq = ctrlWriteAddrGenerator.request;
  	 interface Put writeData;
  	    method Action put(MemData#(dataWidth) d);
  	       ctrlWriteDataFifo.enq(d);
  	    endmethod
  	 endinterface
  	 interface Get writeDone;
  	    method ActionValue#(Bit#(MemTagSize)) get();
  	       let tag <- toGet(ctrlWriteDoneFifo).get();
  	       return tag;
  	    endmethod
  	 endinterface
        endinterface: write_server
     endinterface: memSlave
     interface ReadOnly interrupt;
  
negative.code:       endmethod
     endinterface
  endmodule   
  
  module mkMemPortal#(Bit#(slaveDataWidth) ifcId,
  		    PipePortal#(numRequests, numIndications, slaveDataWidth) portal)(MemPortal#(slaveAddrWidth, slaveDataWidth))
  