anchor.diff:             writeRespFifo.deq;
              return writeRespFifo.first;
          endmethod
  -	method ActionValue#(Bit#(12)) bid();
  +	method ActionValue#(Bit#(idWidth)) bid();
   	    writeIdFifo.deq;
   	    return writeIdFifo.first;
   	endmethod
       endinterface
   endmodule
   
  -module mkAxi3SlaveRegFile(Axi3Slave#(addrWidth, busWidth, busWidthBytes)) provisos(Div#(busWidth,8,busWidthBytes),Add#(a__, 21, addrWidth));
  +module mkAxi3SlaveRegFile(Axi3Slave#(addrWidth, busWidth, busWidthBytes, idWidth)) provisos(Div#(busWidth,8,busWidthBytes),Add#(a__, 21, addrWidth));
          RegFile#(Bit#(21), Bit#(busWidth)) rf <- mkRegFileFull();
  -       Axi3Slave#(addrWidth, busWidth, busWidthBytes) axiSlave <- mkAxi3SlaveFromRegFile(rf);
  +       Axi3Slave#(addrWidth, busWidth, busWidthBytes, idWidth) axiSlave <- mkAxi3SlaveFromRegFile(rf);
          return axiSlave;
   endmodule
   
  
positive.code: endmodule
  
  module mkAxi3SlaveFromRegFile#(RegFile#(Bit#(regFileBusWidth), Bit#(busWidth)) rf)
                                (Axi3Slave#(addrWidth, busWidth, busWidthBytes))
                                provisos(Div#(busWidth,8,busWidthBytes),
                                         Add#(nz, regFileBusWidth, addrWidth));
      Reg#(Bit#(regFileBusWidth)) readAddrReg <- mkReg(0);
      Reg#(Bit#(regFileBusWidth)) writeAddrReg <- mkReg(0);
      Reg#(Bit#(12)) readIdReg <- mkReg(0);
      Reg#(Bit#(12)) writeIdReg <- mkReg(0);
      Reg#(Bit#(4)) readBurstCountReg <- mkReg(0);
      Reg#(Bit#(4)) writeBurstCountReg <- mkReg(0);
      FIFO#(Bit#(2)) writeRespFifo <- mkFIFO();
      FIFO#(Bit#(12)) writeIdFifo <- mkFIFO();
  
      Bool verbose = False;
      interface Axi3SlaveRead read;
          method Action readAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
                                 Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) id) if (readBurstCountReg == 0);
              if (verbose) $display("axiSlave.read.readAddr %h bc %d", addr, burstLen+1);
              readAddrReg <= truncate(addr/fromInteger(valueOf(busWidthBytes)));
  	    readIdReg <= id;
  
negative.code:    interface AxiSlaveWrite#(addrWidth, busWidth, busWidthBytes) write;
  endinterface
  
  interface Axi3SlaveRead#(type addrWidth, type busWidth, type busWidthBytes, type idWidth);
     method Action readAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
                            Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(idWidth) arid);
     method ActionValue#(Bit#(busWidth)) readData();
     method Bit#(1) last();
     method Bit#(idWidth) rid();
     // method Action readResponse(Bit#(2) responseCode);
  endinterface
  
  interface Axi3SlaveWrite#(type addrWidth, type busWidth, type busWidthBytes, type idWidth);
     method Action writeAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
                             Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(idWidth) awid);
     method Action writeData(Bit#(busWidth) data, Bit#(busWidthBytes) byteEnable, Bit#(1) last);
     method ActionValue#(Bit#(2)) writeResponse();
     method ActionValue#(Bit#(idWidth)) bid();
  endinterface
  
  interface Axi3Slave#(type addrWidth, type busWidth, type busWidthBytes, type idWidth);
     interface Axi3SlaveRead#(addrWidth, busWidth, busWidthBytes, idWidth) read;
     interface Axi3SlaveWrite#(addrWidth, busWidth, busWidthBytes, idWidth) write;
  endinterface
  
  interface AxiMasterServer#(type addrWidth, type busWidth, type busWidthBytes, type tagSize);
  