anchor.diff:  		completion.bytecount = 4;
   		completion.reqid = hdr.reqid;
   		completion.loweraddr = getLowerAddr(hdr.addr, hdr.firstbe);
  -		completion.data = data;
  +		if (byteSwapReg)
  +		    completion.data = byteSwap(data);
  +		else
  +		    completion.data = data;
   	        TLPData#(16) tlp = defaultValue;
   		tlp.data = pack(completion);
   		tlp.sof = True;
  
positive.code:     interface Get#(TLPData#(16))   tlp_out;
      interface Axi3Master#(32,32,4,12) portal;
      interface Reg#(Bool)           pipeliningEnabled;
  endinterface
  
  (* synthesize *)
  module mkPortalEngine#(PciId my_id)(PortalEngine);
      Reg#(Bool) pipeliningEnabledReg <- mkReg(False);
      Reg#(Bool) busyReg <- mkReg(False);
      Reg#(Bit#(7)) hitReg <- mkReg(0);
      Reg#(Bit#(4)) timerReg <- mkReg(0);
  
negative.code:    interface Reg#(Bool) tlpTracing;
     interface Reg#(Bool) axiEnabled;
     interface Reg#(Bool) pipeliningEnabled;
     interface Reg#(Bool) byteSwap;
     interface Reg#(Bool) axiTestEnabled;
     interface Reg#(Bit#(32)) addrLowerWord;
     interface Reg#(Bit#(32)) addrUpperWord;
  