anchor.diff:     endfunction: toAxi4MasterBits
   endinstance
   
  -instance ToAxi4SlaveBits#(Axi4SlaveBits#(49,128,6,Empty), Ps8Saxigp);
  -   function Axi4SlaveBits#(49,128,6,Empty) toAxi4SlaveBits(Ps8Saxigp s);
  -      return (interface Axi4SlaveBits#(49,128,6,Empty);
  +instance ToAxi4SlaveBits#(Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra), Ps8Saxigp);
  +   function Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra) toAxi4SlaveBits(Ps8Saxigp s);
  +      return (interface Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra);
   	 method araddr = s.araddr;
   	 method arburst = s.arburst;
   	 method arcache = s.arcache;
  +	 //method aresetn = 1; //no aresetn port in zcu
   	 method arid = s.arid;
   	 method arlen = s.arlen;
   	 method arlock = compose(s.arlock, truncate);
  
positive.code: 
  instance ConnectableWithTrace#(PS8LIB, Platform, traceType);
     module mkConnectionWithTrace#(PS8LIB psu, Platform top, traceType readout)(Empty);
        Axi4MasterBits#(40,128,16,Ps8Aruser) master = toAxi4MasterBits(psu.m_axi_gp[0]);
        PhysMemMaster#(32,32) physMemMaster <- mkPhysMemMaster(master);
        mkConnection(physMemMaster, top.slave);
  
        Axi4SlaveBits#(49,128,6,Empty) slave = toAxi4SlaveBits(psu.s_axi_gp[0]);
        PhysMemSlave#(32,DataBusWidth) physMemSlave <- mkPhysMemSlave(slave);
        mkConnection(top.masters[0], physMemSlave);
     endmodule
  endinstance
  
negative.code: 	 axiSlave.arid(axireq.id);
  	 axiSlave.arsize(axireq.size);
  	 axiSlave.arlen(axireq.len);
  	 axiSlave.arburst(2'b01);     // burst: INCR
  	 axiSlave.arcache(4'b0011);   // FIXME: 0011? 1111?
  	 axiSlave.arlock(2'b0);       // normal access
  	 axiSlave.arprot(3'b0);       // unprevileged, protected, data access
  	 axiSlave.arqos(4'b0);        // unused - default 0
  	 axiSlave.extra.aruser(1'b0); // unused
  	 arInFlight.enq(True);
        endrule
        rule rl_rready;
  	 axiSlave.rready(pack(rfifo.notFull && arInFlight.notEmpty));
        endrule
        rule rl_rdata if (axiSlave.rvalid() == 1);
  	 let ar = arInFlight.first; // implicit guard (arInFlight should not be empty to fire this rule)
  	 let last = axiSlave.rlast == 1;
  	 if (last) arInFlight.deq;
  
  	 rfifo.enq(MemData { data: truncate(axiSlave.rdata()), tag: ar?axiSlave.rid():0, last: last } );
        endrule
  
        rule rl_awvalid_awaddr;
  