anchor.diff:     interface ReadOnly#(Bit#(32)) interruptData;
   
      interface Reg#(Bool) tlpTracing;
  -   interface Reg#(Bool) axiEnabled;
  +   //jca interface Reg#(Bool) axiEnabled;
      interface Reg#(Bool) byteSwap;
      interface Reg#(Bool) use4dw;
      interface Reg#(Bit#(4)) numPortals;
  
positive.code:          // 4-bit MSIx pending bit field
           5120: return '0;                               // PBA structure (low)
           5121: return '0;                               // PBA structure (high)
           // unused addresses
           default: return 32'hbad0add0;
        endcase
  
negative.code:             4109: msix_entry[3].addr_hi  <= update_dword(msix_entry[3].addr_hi, be, dword);
              4110: msix_entry[3].msg_data <= update_dword(msix_entry[3].msg_data, be, dword);
              4111: if (be[0] == 1) msix_entry[3].masked <= unpack(dword[0]);
              //******************************** end of area referenced from xilinx_x7_pcie_wrapper.v
           endcase
        endaction
     endfunction: wr_csr
  