anchor.diff:  						  });
      endrule
   
  -   Gearbox#(BusRatio,1,Bit#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);
  -   SyncFIFOIfc#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkSyncFIFO(8, clock, reset, ddr3Controller.uiClock);
  +   Gearbox#(BusRatio,1,Bit#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, ddr3Controller.uiClock, ddr3Controller.uiReset);
  +   FIFOF#(Bit#(DataBusWidth)) dramReadFifo <- mkDualClockBramFIFOF(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);
  +   FIFOF#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
      //mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);
      rule rl_arfifo;
         let req <- toGet(arfifo).get();
  
positive.code:    endrule
     rule rl_wdata;
        let mds <- toGet(dramWriteGearbox).get();
        wdataProbe <= mds;
        ddr3Controller.slave.resp_write.put(Axi4WriteData {
  	 data: pack(mds),
  
negative.code: import Connectable::*;
  import ClientServer::*;
  import ConnectalMemory::*;
  import ConnectalBramFifo::*;
  import FIFOF::*;
  import Gearbox::*;
  import GearboxGetPut::*;
  