anchor.diff:        return TxThruDbgRec {goodputCount: goodputCount, idleCount: idleCount};
      endmethod
      method ThruDbgRec sdbg;
  -      return ThruDbgRec {data_bytes: data_bytes, sops: sopCount, eops: eopCount, idle_cycles: idle_cycles, total_cycles: cycle_cnt};
  +      return ThruDbgRec {data_bytes: data_bytes, sops: sopCount, eops: eopCount, idle_cycles: idle_cycles, total_cycles: total_cycles};
      endmethod
   endmodule
   
  
positive.code:    FIFO#(PacketDataT#(64)) readMacFifo <- mkFIFO(clocked_by rxClock, reset_by rxReset);
     SyncFIFOIfc#(EtherData) rx_fifo <- mkSyncFIFO(5, rxClock, rxReset, defaultClock);
  
     rule cycle;
        cycle_cnt <= cycle_cnt + 1;
     endrule
  
     function EtherData combine(Vector#(2, PacketDataT#(64)) v);
  
negative.code:    Reg#(Bit#(64)) idleCount <- mkReg(0);
  
     // stats
     Reg#(Bit#(64)) total_cycles <- mkReg(0, clocked_by txClock, reset_by txReset);
     Reg#(Bit#(64)) idle_cycles <- mkReg(0, clocked_by txClock, reset_by txReset);
     Reg#(Bit#(64)) sopCount <- mkReg(0, clocked_by txClock, reset_by txReset);
     Reg#(Bit#(64)) eopCount <- mkReg(0, clocked_by txClock, reset_by txReset);
     Reg#(Bit#(64)) data_bytes <- mkReg(0, clocked_by txClock, reset_by txReset);
  
     // RingBuffer Read Client
     FIFO#(EtherData) readDataFifo <- mkFIFO;
  