anchor.diff:  import Connectable::*;
   import FIFOF::*;
   import GetPut::*;
  +import Probe::*;
   import Vector::*;
   
   import AddressGenerator::*;
  
positive.code: 
     FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo <- mkSizedBRAMFIFOF(128);
     PipeIn#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) tracePipe = toPipeIn(traceFifo);
     FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo <- mkSizedBRAMFIFOF(512);
     PipeIn#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataPipe = toPipeIn(traceDataFifo);
     rule rl_trace1;
        match { .chan, .write, .req, .timestamp } <- toGet(traceFifo).get();
  
negative.code:       else
  	 md <- toGet(busReadDataFifo).get();
        readDataFifo.enq(md);
  
        readDataDest <= dest;
        readDataData <= md.data;
        readDataLast <= md.last;
        readBeatAddr <= addrBeat.addr[15:0];
        readBeatByteCount <= addrBeat.bc;
        readBeatLast <= addrBeat.last;
     endrule
  
     rule rl_wr_req;
  