anchor.diff:  endmodule
   
   module mkAxi3SlaveFromRegFile#(RegFile#(Bit#(regFileBusWidth), Bit#(busWidth)) rf)
  -                              (Axi3Slave#(addrWidth, busWidth, busWidthBytes))
  +                              (Axi3Slave#(addrWidth, busWidth, busWidthBytes, idWidth))
                                 provisos(Div#(busWidth,8,busWidthBytes),
                                          Add#(nz, regFileBusWidth, addrWidth));
       Reg#(Bit#(regFileBusWidth)) readAddrReg <- mkReg(0);
       Reg#(Bit#(regFileBusWidth)) writeAddrReg <- mkReg(0);
  -    Reg#(Bit#(12)) readIdReg <- mkReg(0);
  -    Reg#(Bit#(12)) writeIdReg <- mkReg(0);
  +    Reg#(Bit#(idWidth)) readIdReg <- mkReg(0);
  +    Reg#(Bit#(idWidth)) writeIdReg <- mkReg(0);
       Reg#(Bit#(4)) readBurstCountReg <- mkReg(0);
       Reg#(Bit#(4)) writeBurstCountReg <- mkReg(0);
       FIFO#(Bit#(2)) writeRespFifo <- mkFIFO();
  -    FIFO#(Bit#(12)) writeIdFifo <- mkFIFO();
  +    FIFO#(Bit#(idWidth)) writeIdFifo <- mkFIFO();
   
       Bool verbose = False;
       interface Axi3SlaveRead read;
           method Action readAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
  -                               Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) id) if (readBurstCountReg == 0);
  +                               Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(idWidth) id) if (readBurstCountReg == 0);
               if (verbose) $display("axiSlave.read.readAddr %h bc %d", addr, burstLen+1);
               readAddrReg <= truncate(addr/fromInteger(valueOf(busWidthBytes)));
   	    readIdReg <= id;
  
positive.code:            writeRespFifo.deq;
             return writeRespFifo.first;
         endmethod
  	method ActionValue#(Bit#(12)) bid();
  	    writeIdFifo.deq;
  	    return writeIdFifo.first;
  	endmethod
      endinterface
  endmodule
  
  module mkAxi3SlaveRegFile(Axi3Slave#(addrWidth, busWidth, busWidthBytes)) provisos(Div#(busWidth,8,busWidthBytes),Add#(a__, 21, addrWidth));
         RegFile#(Bit#(21), Bit#(busWidth)) rf <- mkRegFileFull();
         Axi3Slave#(addrWidth, busWidth, busWidthBytes) axiSlave <- mkAxi3SlaveFromRegFile(rf);
         return axiSlave;
  endmodule
  
  
negative.code: 
  module mkClientSlaveConnection#(Axi3WriteClient#(addrWidth, busWidth, busWidthBytes,idWidth) axicw,
                                  Axi3ReadClient#(addrWidth, busWidth,idWidth) axicr,
                                  Axi3Slave#(addrWidth, busWidth, busWidthBytes, idWidth) axiSlave)
                                  () provisos (Div#(busWidth, 8, busWidthBytes),
  				             Add#(1, a__, busWidth),
  					     Add#(busWidth, b__, 65),
  