anchor.diff:     // Inputs
      // clkin_100, saxi.aclk, maxi.aclk, reset, 
      saxi.aresetn,
  -   maxi.aresetn, misc.csysreq, rxi.data_p, rxi.data_n, rxi.frame_p,
  -   rxi.frame_n, rxi.lclk_p, rxi.lclk_n, txi.wr_wait_p, txi.wr_wait_n,
  +   maxi.aresetn, misc.csysreq, rx.data_p, rx.data_n, rx.frame_p,
  +   rx.frame_n, rx.lclk_p, rx.lclk_n, txi.wr_wait_p, txi.wr_wait_n,
      txi.rd_wait_p, txi.rd_wait_n, maxi.awready, saxi.awid,
      saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,
      saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,
  
positive.code:    // Inputs
     // clkin_100, saxi.aclk, maxi.aclk, reset, 
     saxi.aresetn,
     maxi.aresetn, misc.csysreq, rxi.data_p, rxi.data_n, rxi.frame_p,
     rxi.frame_n, rxi.lclk_p, rxi.lclk_n, txi.wr_wait_p, txi.wr_wait_n,
     txi.rd_wait_p, txi.rd_wait_n, maxi.awready, saxi.awid,
     saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,
     saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,
  
negative.code: 
  (* always_ready, always_enabled *)
  interface PParallellaLIB;
     interface Par_tx tx;
     interface Par_rx rx;
     interface ParMaxiGp maxi;   // this will connect to a master
     interface ParSaxiHp saxi;  // this will connect to a slave
     interface Par_misc misc;
  endinterface
  
  import "BVI" elink =
  module mkELink#(Clock maxiclk, Clock saxiclk, 
     Reset maxiclk_reset, Reset saxiclk_reset,
     Reset maxireset, Reset saxireset,
     Reset reset_chip, Reset reset_fpga)(ELink);
     // default_clock clk();
     // default_reset rst();
     input_clock maxiclk(emaxi_aclk) = maxiclk;  // assigns the verilog emaxi_aclk
  