anchor.diff:        else begin
   	 respCnt <= new_respCnt;
         end
  -      clientDataFifo[idx].enq(MemDataF { data: d.data, tag: d.tag >> valueOf(serverIdxSz), first: (respCnt == 0), last: l});
  -   endrule
  -
  -   Vector#(numServers, MemReadEngineServer#(userWidth)) rs;
  -   for(Integer i = 0; i < valueOf(numServers); i=i+1)
  -      rs[i] = (interface MemReadEngineServer#(userWidth);
  +      clientDataFifo.enq(MemDataF { data: d.data, tag: d.tag >> valueOf(serverIdxSz), first: (respCnt == 0), last: l});
  +   endrule
  +
  +   MemReadEngineServer#(userWidth) rs = (interface MemReadEngineServer#(userWidth);
   		  interface Put request;
   		     method Action put(MemengineCmd cmd);
   `ifdef SIMULATION
  
positive.code:    provisos( Mul#(TDiv#(busWidth, 8), 8, busWidth)
  	    ,Add#(1, a__, numServers)
  	    ,Add#(busWidth, 0, userWidth)
  	    ,Add#(b__, TLog#(numServers), TAdd#(1, TLog#(TMul#(cmdQDepth,numServers))))
  	    ,Add#(c__, TLog#(numServers), TLog#(TMul#(cmdQDepth, numServers)))
  	    ,Add#(d__, TLog#(numServers), MemTagSize)
  	    );
     let rv <- mkMemReadEngineBuff(valueOf(cmdQDepth) * valueOf(TExp#(BurstLenSize)));
     return rv;
  endmodule
  
negative.code: 			else
  `endif
                             begin
  			   clientRequest.enq(cmd);
  			   end
   		     endmethod
  		  endinterface
                    interface data = interface PipeOut;
  	             method MemDataF#(userWidth) first;
  	                return clientDataFifo.first;
  	             endmethod
  	             method Action deq;
  	                if (verbose) $display("mkMemReadEngineBuff::check_out: data %h clientAvail %d eob %d", clientDataFifo.first.data, clientAvail.read(), clientDataFifo.first.last);
  	                clientDataFifo.deq;
  	                clientAvail.increment(1);
  	             endmethod
  	             method Bool notEmpty = clientDataFifo.notEmpty;
                    endinterface;
  	       interface requestCycles = toPipeOut(clientCyclesFifo);
                 endinterface);
     interface readServer = rs;
     interface PipeOut readReq = toPipeOut(dmaRequest);
     interface PipeIn readData = toPipeIn(serverDataFifo);
  endmodule
  
  module mkMemReadEngineBuff#(Integer bufferSizeBytes) (MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers))
     provisos (Div#(busWidth,8,busWidthBytes),
  	     Mul#(busWidthBytes,8,busWidth),
  	     Add#(busWidth, 0, userWidth),
  	     FunnelPipesPipelined#(1, numServers, MemTypes::MemData#(userWidth), 2),
  	     FunnelPipesPipelined#(1, numServers, MemTypes::MemRequest, 2),
  	     Add#(a__, TLog#(numServers), 6)
  	     );
     let verbose = False;
  
     let clock <- exposeCurrentClock();
     let reset <- exposeCurrentReset();
  
     Integer bufferSizeBeats = bufferSizeBytes/valueOf(busWidthBytes);
  
     Vector#(numServers, MemReadChannel#(busWidth,userWidth,cmdQDepth)) readChannels <- genWithM(mkMemReadChannel(bufferSizeBytes));
     Vector#(numServers, FIFOF#(Bit#(MemTagSize))) readtagFifos <- replicateM(mkSizedFIFOF(valueOf(cmdQDepth)));
     function PipeOut#(MemRequest) readChannelDmaReadReq(Integer i);
        return readChannels[i].readReq;
     endfunction
     function MemReadEngineServer#(userWidth) readChannelServer(Integer i);
        return readChannels[i].readServer;
     endfunction
  
     FIFOF#(MemRequest) reqFifo <- mkFIFOF();
     FunnelPipe#(1,numServers,MemRequest,2) reqFunnel <- mkFunnelPipesPipelined(genWith(readChannelDmaReadReq));
     FIFOF#(MemData#(busWidth)) readDataFifo <- mkFIFOF();
     function Tuple2#(Bit#(TLog#(numServers)),MemData#(userWidth)) tagData(MemData#(userWidth) md);
        return tuple2(truncate(md.tag), md);
     endfunction
     UnFunnelPipe#(1,numServers,MemData#(userWidth),2) dataPipes <- mkUnFunnelPipesPipelined(vec(mapPipe(tagData, toPipeOut(readDataFifo))));
     // FIXME: pass this a parameter to mkMemReadChannel
     for (Integer channel = 0; channel < valueOf(numServers); channel = channel + 1)
        mkConnection(dataPipes[channel], readChannels[channel].readData);
  
     interface Vector  readServers = genWith(readChannelServer);
     interface MemReadClient dmaClient;
        interface Get    readReq = toGet(reqFunnel[0]);
        interface Put   readData = toPut(readDataFifo);
     endinterface
  
  endmodule
  