anchor.diff:          master_data.shiftin2(0);
           master_data.oclk(0);
           master_data.oclkb(0);
  -        master_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
  -        //master_data.reset(iodelay_reset_inc_ce[2]);
  +        master_data.reset(iodelay_reset_inc_ce[2]);
           slave_data.d(0);
  -        slave_data.bitslip(serbvi.bitslip());
  -        //slave_data.bitslip(iserdes_bitslip);
  +        slave_data.bitslip(iserdes_bitslip);
           slave_data.ce1(1);
           slave_data.ce2(1);
           slave_data.ddly(0);
  
positive.code:            master_data.q4(), master_data.q3(), master_data.q2(), master_data.q1()};
          slave_data.oclk(0);
          slave_data.oclkb(0);
          slave_data.reset(serbvi.iodelay_reset_inc_ce()[2]);
          //slave_data.reset(iodelay_reset_inc_ce[2]);
          iserdes_data <= dout;
          serbvi.dataout(dout);
          dfifo.di({6'b0,dout});
  
negative.code:     Reg#(Bit#(1)) fifo_wren_sync <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(1)) fifo_wren_sync_wire <- mkDWire(0);
  //, clocked_by serdes_clock, reset_by serdes_reset);
      //outputs
      Reg#(Bit#(1)) dackint <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      ReadOnly#(Bit#(3)) samplein_null <- mkNullCrossingWire(serdes_clock, serbvi.samplein());
  
      //Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      //Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(1)) iserdes_bitslip <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
      Wire#(Bit#(3)) iodelay_reset_inc_ce <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule wren_rule;
          //fifo_wren_sync_wire <= fifo_wren_sync;
          fifo_wren_sync_wire <= serbvi.fifo_wren_sync();
      endrule
      rule clkdiv_rule if (bvi_reset_reg != 0);
          let ds = dstate;
          let dc = dcounter;
  