anchor.diff:     Clock pcieClock_ = ep7.epPcieClock;
      Reset pcieReset_ = ep7.epPcieReset;
      PcieHost#(DataBusWidth, NumberOfMasters) pciehost <- mkPcieHost(
  -`ifdef PCIE3
  -         PciId{ bus:  1, dev: 1, func: 0}, //FIXME!
  -`else
  +`ifndef PCIE3
            PciId{ bus:  ep7.cfg.bus_number(), dev: ep7.cfg.device_number(), func: ep7.cfg.function_number()},
   `endif
            clocked_by pcieClock_, reset_by pcieReset_);
  
positive.code: `endif
  `endif
  endmodule: mkPcieHost
  
  interface PcieTop#(type ipins);
  `ifndef BSIM
  
negative.code:    Reset portalReset_ = epPcieReset;
  
     PcieHost#(DataBusWidth, NumberOfMasters) pciehost <- mkPcieHost(ep7.device, clocked_by portalClock_, reset_by portalReset_);
     mkConnection(ep7.tlp, pciehost.pcic, clocked_by portalClock_, reset_by portalReset_);
  
     interface PcieEndpointS5 tep7 = ep7;
     interface PcieHost tpciehost = pciehost;
  