anchor.diff:  //    endrule
   
       interface Put tlp_in;
  -        method Action put(TLPData#(16) tlp) if (!busyReg);
  +        method Action put(TLPData#(16) tlp);
   	    //$display("PortalEngine.put tlp=%h", tlp);
   	    TLPMemoryIO3DWHeader h = unpack(tlp.data);
   	    hitReg <= tlp.hit;
  
positive.code: module mkControlAndStatusRegs#( Bit#(64)  board_content_id
  			       , PciId     my_id
  			       , Integer   bytes_per_beat
  			       , Bit#(7)   rcb_mask
  			       , Bool      msix_enabled
  			       , Bool      msix_mask_all_intr
  
negative.code: 
  (* synthesize *)
  module mkPortalEngine#(PciId my_id)(PortalEngine);
      Reg#(Bool) byteSwapReg <- mkReg(True);
      Reg#(Bool) interruptRequestedReg <- mkReg(False);
      Reg#(Bool) interruptSecondHalf <- mkReg(False);
      Reg#(Bit#(7)) hitReg <- mkReg(0);
  