anchor.diff:     } DmaError deriving (Bits);
   
   // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  -module mkMMU#(Integer iid, Bool bsimMMap, MMUIndication mmuIndication)(MMU#(addrWidth))
  +module mkMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
      provisos(Log#(MaxNumSGLists, listIdxSize),
   	    Add#(listIdxSize,8, entryIdxSize),
   	    Add#(a__,addrWidth,MemOffsetSize));
  
positive.code:       let nextId <- sglId_gen.getTag;
        let resp = (fromInteger(iid) << 16) | extend(nextId);
        if (verbose) $display("mkMMU::idRequest %d", fd);
  `ifdef BSIM
        let va <- pareff_initfd(resp, fd);
  `endif
        mmuIndication.idResponse(resp);
     endmethod
     method Action idReturn(Bit#(32) sglId);
  
negative.code:    Bit#(MemOffsetSize) off;
  } ReqTup deriving (Eq,Bits,FShow);
  
  interface Pareff;
     method ActionValue#(Bit#(32)) init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);
     method ActionValue#(Bit#(32)) initfd(Bit#(32) id, Bit#(32) fd);
  endinterface
  
  `ifdef BSIM
  import "BDPI" function ActionValue#(Bit#(32)) pareff_init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);
  import "BDPI" function ActionValue#(Bit#(32)) pareff_initfd(Bit#(32) id, Bit#(32) fd);
  
  module mkPareff(SimulatorMMU);
     method ActionValue#(Bit#(32)) init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);
        let v <- pareff_init(id, handle, size);
        return v;
     endmethod
     method ActionValue#(Bit#(32)) initfd(Bit#(32) id, Bit#(32) fd);
        let v <- pareff_initfd(id, fd);
        return v;
     endmethod
  endmodule
  `else
  module mkPareff(SimulatorMMU);
     method ActionValue#(Bit#(32)) init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);
     endmethod
     method ActionValue#(Bit#(32)) initfd(Bit#(32) id, Bit#(32) fd);
     endmethod
  endmodule
  `endif
  
  
  interface MMU#(numeric type addrWidth);
     interface MMURequest request;
  