anchor.diff:  	        let hdr = writeHeaderFifo.first;
   	        writeHeaderFifo.deq;
   		writeDataFifo.enq(hdr);
  -		return extend(writeHeaderFifo.first.addr) << 2;
  +		return byteSwap(extend(writeHeaderFifo.first.addr) << 2);
   	    endmethod
   	    method Bit#(4) writeBurstLen();
   		return 0;
  
positive.code:     Reg#(Bool) pipeliningEnabledReg <- mkReg(False);
      Reg#(Bool) busyReg <- mkReg(False);
      Reg#(Bit#(7)) hitReg <- mkReg(0);
      FIFO#(TLPMemoryIO3DWHeader) readHeaderFifo <- mkFIFO;
      FIFO#(TLPMemoryIO3DWHeader) readDataFifo <- mkFIFO;
      FIFO#(TLPMemoryIO3DWHeader) writeHeaderFifo <- mkFIFO;
      FIFO#(TLPMemoryIO3DWHeader) writeDataFifo <- mkFIFO;
      FIFO#(TLPData#(16)) tlpOutFifo <- mkFIFO;
      interface Put tlp_in;
          method Action put(TLPData#(16) tlp) if (!busyReg);
  	    $display("PortalEngine.put tlp=%h", tlp);
  
negative.code: 	        writeHeaderFifo.enq(hdr_3dw);
              if (!pipeliningEnabledReg)
  	        busyReg <= True;
              timerReg <= truncate(32'hFFFFFFFF);
  	endmethod
      endinterface: tlp_in
      interface Get tlp_out = toGet(tlpOutFifo);
  