anchor.diff:        mkConnection(toGet(dmaErrorFifos[i]), toPut(dmaErrorFifo));
      rule dmaError;
         let error <- toGet(dmaErrorFifo).get();
  -      mmuIndication.error(extend(pack(error.errorType)), error.pref, extend(error.off), fromInteger(iid));
  +      mmuIndication.error(extend(pack(error.errorType)), error.pref, extend(error.off), extend(mmuid));
      endrule
   
      let page_shift0 = fromInteger(valueOf(SGListPageShift0));
  
positive.code: 	     method ActionValue#(AddrTransResponse#(addrWidth)) get();
  		let rv <- toGet(pageResponseFifos[i]).get();
  `ifdef SIMULATION
  		rv.physAddr = rv.physAddr | (fromInteger(iid)<<valueOf(addrWidth)-3);
  `endif
  		return rv;
  	     endmethod
  
negative.code:    } Stage4Params deriving (Bits);
  
  // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  module mkMMU#(Bit#(4) mmuid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))
     provisos(Log#(MaxNumSGLists, listIdxSize),
  	    Add#(listIdxSize,8, entryIdxSize),
  	    Add#(a__,addrWidth,MemOffsetSize));
  