anchor.diff:     // Trace Support
      Reg#(Bool) tlpTracingReg        <- mkReg(False);
      Reg#(Bit#(TlpTraceAddrSize)) tlpTraceLimitReg <- mkReg(0);
  +   FIFOF#(Bit#(TlpTraceAddrSize)) pcieTraceBramWrAddrFifo <- mkFIFOF();
      Reg#(Bit#(TlpTraceAddrSize)) pcieTraceBramWrAddrReg <- mkReg(0);
      Integer memorySize = 2**valueOf(TlpTraceAddrSize);
   
  
positive.code:    interface TlpTraceData tlpdata;
        interface Reg tlpTracing    = tlpTracingReg;
        interface Reg tlpTraceLimit = tlpTraceLimitReg;
        interface Reg pcieTraceBramWrAddr = pcieTraceBramWrAddrReg;
        interface Server bramServer = bramMuxReg.bramServer;
        interface Server bscanBramServer = bscanBramMux.bramServer;
     endinterface
  
negative.code: 
     rule doTracing if (fromPcie || toPcie);
        TimestampedTlpData fromttd = fromPcie ? TimestampedTlpData { timestamp: timestamp, source: 7'h04, tlp: fromPcieTlp } : unpack(0);
        let writeAddr = pcieTraceBramWrAddrReg;
        if (pcieTraceBramWrAddrFifo.notEmpty)
  	 writeAddr <- toGet(pcieTraceBramWrAddrFifo).get();
  
        fromPcieTraceBram.portA.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: writeAddr, datain: fromttd });
  
        TimestampedTlpData   tottd = toPcie ? TimestampedTlpData { timestamp: timestamp, source: 7'h08, tlp: toPcieTlp } : unpack(0);
        toPcieTraceBram.portA.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: writeAddr, datain: tottd });
  
        pcieTraceBramWrAddrReg <= writeAddr + 1;
     endrule
  
     interface Server     bus;
  