anchor.diff:     Wire#(Bool)                  goodFrame   <- mkWire;
      Wire#(Bool)                  badFrame    <- mkWire;
   
  -   Reg#(Bit#(PktAddrWidth))     wrCurrPtr   <- mkReg(0);
  +   Reg#(Bit#(depth))     wrCurrPtr   <- mkReg(0);
      Reg#(Bit#(EtherLen))         packetLen   <- mkReg(0);
      Reg#(Bool)                   inPacket    <- mkReg(False);
   
  
positive.code: `include "SynthBuilder.defines"
  
  typedef struct {
     Bit#(PktAddrWidth) addr;
     ByteStream#(n)     data;
  } ReqT#(numeric type n) deriving (Eq, Bits);
  instance FShow#(ReqT#(n));
     function Fmt fshow (ReqT#(n) req);
        return ($format(" addr=0x%x ", req.addr)
                + $format(" data=0x%x ", req.data.data)
                + $format(" user=0x%x ", req.data.user)
  
negative.code:    BRAM_Configure bramConfig = defaultValue;
     //bramConfig.memorySize = 1024;
     bramConfig.latency = 2;
     BRAM2Port#(Bit#(depth), ByteStream#(n)) memBuffer <- mkBRAM2Server(bramConfig);
  
     FIFOF#(ByteStream#(n)) fifoWriteData <- mkFIFOF;
     FIFOF#(Bit#(EtherLen)) fifoEop <- mkFIFOF;
     FIFO#(ReqT#(n, depth)) incomingReqs     <- mkFIFO;
  
     // Client
     Reg#(Bit#(depth))     rdCurrPtr   <- mkReg(0);
     Reg#(Bool)                   outPacket   <- mkReg(False);
  
     FIFOF#(Bit#(EtherLen))    fifoLen     <- mkSizedFIFOF(16);
  