anchor.diff:      endrule
       rule afsmwdelay_rule if (bvi_resets_reg.read() != 0 && astate == AWDelay);
           astate <= AEdge;
  -        serdes_setting.enq(2'b00);
  +        serdes_start.enq(0);
       endrule
       rule afsmedge_rule if (bvi_resets_reg.read() != 0 && astate == AEdge);
           serdes_end.deq();
  
positive.code: 
      rule sendup_sdes_clock;
      for (Bit#(8) i = 0; i < 5; i = i+1) begin
         serdes_v[i].reset(serdes_reset_null);
         //serdes_v[i].delay_wren(delay_wren_c_reg);
         serdes_v[i].fifo_wren(serdes_fifo_enable_null);
      end
      endrule
      
  
negative.code:     rule afsmvalid_rule if (bvi_resets_reg.read() != 0 && astate == AValid);
          maxcount <= maxcount - 1;
          astate <= A1Changed;
          serdes_start.enq(2'b11);
      endrule
      rule afsm1changed_rule if (bvi_resets_reg.read() != 0 && astate == A1Changed);
          serdes_end.deq();
  