anchor.diff:        rg_sstatus_SUM <= 0;
   `endif
   
  -      rg_state <= CPU_SPLIT_FETCH;
  +      rg_state <= CPU_START_TRAP_HANDLER;
         
         stageD.set_full (False);
         stage1.set_full (False);    fa_step_check;
  
positive.code:    Reg #(CPU_State)  rg_state    <- mkReg (CPU_RESET1);
     Reg #(Priv_Mode)  rg_cur_priv <- mkReg (m_Priv_Mode);
     Reg #(Epoch)      rg_epoch    <- mkRegU;
  
     // Save next_pc across split-phase FENCE.I and other split-phase ops. This
     // register is also used for initiating fetches on a trap or external
  
negative.code:       rg_sstatus_SUM <= 0;
  `endif
  
        rg_state <= CPU_START_TRAP_HANDLER;
  
        stage1.set_full (False);
        stage2.set_full (False);
  