anchor.diff:          idelay_type: "VARIABLE", idelay_value: 0,
           pipe_sel: "FALSE", refclk_frequency: 200, signal_pattern: "DATA"},
           defaultClock, clocked_by serdes_clock);
  +    ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
       IserdesE2 master_data <- mkISERDESE2( ISERDESE2_Config{
           data_rate: "DDR", data_width: 10,
           dyn_clk_inv_en: "FALSE", dyn_clkdiv_inv_en: "FALSE",
  
positive.code: 
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
      ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
      Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
      FIFO18 dfifo <- mkFIFO18(serdes_clock);
      IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
          cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
  
negative.code: endinterface: Iserdesbvi
  
  import "BVI" iserdes_datadeser = 
  module mkIserdesbvi#(Clock clkdiv)(Iserdesbvi);
     input_clock clkdiv (CLKDIV) = clkdiv;
     default_clock clock(CLOCK);
        method                  align_start(ALIGN_START) enable((*inhigh*) en1) clocked_by (clock);
        method ALIGN_BUSY       align_busy() clocked_by (clock);
        method ALIGNED          aligned() clocked_by (clock);
        method ISERDES_BITSLIP  bitslip() clocked_by (clkdiv);
        method SAMPLEIN samplein() clocked_by (clock);
        method IODELAY_RESET_INC_CE iodelay_reset_inc_ce() clocked_by (clkdiv);
        method                  autoalign(AUTOALIGN) enable((*inhigh*) en7) clocked_by (clock);
        method                  training(TRAINING) enable((*inhigh*) en8) clocked_by (clock);
        method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
  