anchor.diff:     endmethod
      interface unparsedOutIpv4 = toPipeOut(unparsed_out_parse_ipv4_fifo);
      interface unparsedOutVlan = toPipeOut(unparsed_out_parse_vlan_fifo);
  -   interface nextState = toPipeOut(next_state_fifo);
  -endmodule
  -
  -interface ParseVlanArbiter;
  -   interface PipeOut#(ParserState) outToFSM;
  -   interface Vector#(2, PipeIn#(ParserState)) in;
  -endinterface
  -
  -(* synthesize *)
  -module mkParseVlanArbiter(ParseVlanArbiter);
  -   FIFOF#(ParserState) state_out_fifo <- mkBypassFIFOF;
  -   Vector#(2, FIFOF#(ParserState)) state_in_fifo <- replicateM(mkBypassFIFOF);
  -
  -   (* fire_when_enabled *)
  -   rule arbitrate_outgoing_state;
  -      Bool stateSet = False;
  -      for (Integer port=0; port<2; port=port+1) begin
  -         if (!stateSet && state_in_fifo[port].notEmpty()) begin
  -            ParserState state <- toGet(state_in_fifo[port]).get;
  -            stateSet = True;
  -            state_out_fifo.enq(state);
  -         end
  -      end
  -   endrule
  -   interface in = map(toPipeIn, state_in_fifo);
  -   interface outToFSM = toPipeOut(state_out_fifo);
   endmodule
   
   // Parse second VLAN
   module mkParseVlan#(Reg#(ParserState) state, FIFOF#(EtherData) datain)(ParseVlan);
      FIFOF#(Bit#(16)) unparsed_in_fifo <- mkBypassFIFOF;
      FIFOF#(Bit#(16)) unparsed_in_fifo_vlan0 <- mkBypassFIFOF;
  -   FIFOF#(Vlan_tag_t) parsed_out_fifo <- mkSizedFIFOF(1);
      FIFOF#(Bit#(112)) unparsed_out_parse_vlan0_fifo <- mkSizedFIFOF(1);
      FIFOF#(Bit#(80)) unparsed_out_parse_vlan1_fifo <- mkSizedFIFOF(1);
   
  -   FIFOF#(ParserState) next_state_fifo <- mkBypassFIFOF;
      Wire#(Bit#(128)) packet_in_wire <- mkDWire(0);
  +   Vector#(2, Wire#(Maybe#(ParserState))) next_state_wire <- replicateM(mkDWire(tagged Invalid));
   
      let verbose = True;
      Reg#(Cycle_t) cycle <- mkReg(defaultValue);
  
positive.code:       $display("Parser::mkParseVlan ", fshow(cycle) + fshow("loading packet ") + fshow(data_current));
     endrule
  
     rule load_unparsed_in;
        let data_delayed <- toGet(unparsed_in_fifo).get;
        unparsed_in_fifo_vlan0.enq(data_delayed);
        if (verbose) $display("Parser:: ", fshow(cycle) + fshow("load unparsed in"));
     endrule
  
     mkConnection(nextStateArbiter.outToFSM, toPipeIn(next_state_fifo));
  
     Stmt parse_vlan_0 =
     // VLAN
  
negative.code:    endmethod
     interface unparsedIn = toPipeIn(unparsed_in_fifo);
     interface unparsedOut = toPipeOut(unparsed_out_fifo);
     interface parsedOut_ipv4_dstAddr = toPipeOut(parsed_ipv4_fifo);
  endmodule
  
  (* synthesize *)
  module mkParser(Parser);
     Reg#(ParserState) curr_state <- mkReg(S0);
     Reg#(Bool) started <- mkReg(False);
     FIFOF#(EtherData) data_in_fifo <- mkFIFOF;
     Wire#(Bool) start_fsm <- mkDWire(False);
  
     Empty init_state <- mkInitialState(curr_state, data_in_fifo, start_fsm);
     ParseEthernet parse_ethernet <- mkParseEthernet(curr_state, data_in_fifo);
     ParseVlan parse_vlan <- mkParseVlan(curr_state, data_in_fifo);
     ParseIpv4 parse_ipv4 <- mkParseIpv4(curr_state, data_in_fifo);
  