anchor.diff:     endmethod
      interface unparsedIn = toPipeIn(unparsed_in_fifo);
      interface unparsedOut = toPipeOut(unparsed_out_fifo);
  -   interface nextState = toPipeOut(next_state_fifo);
  +   interface parsedOut_ipv4_dstAddr = toPipeOut(parsed_ipv4_fifo);
   endmodule
   
   (* synthesize *)
   module mkParser(Parser);
      Reg#(ParserState) curr_state <- mkReg(S0);
      Reg#(Bool) started <- mkReg(False);
  -
      FIFOF#(EtherData) data_in_fifo <- mkFIFOF;
  +   Wire#(Bool) start_fsm <- mkDWire(False);
  +
  +   Empty init_state <- mkInitialState(curr_state, data_in_fifo, start_fsm);
      ParseEthernet parse_ethernet <- mkParseEthernet(curr_state, data_in_fifo);
      ParseVlan parse_vlan <- mkParseVlan(curr_state, data_in_fifo);
      ParseIpv4 parse_ipv4 <- mkParseIpv4(curr_state, data_in_fifo);
  
positive.code:       cycle.cnt <= cycle.cnt + 1;
     endrule
  
     ParseVlanArbiter nextStateArbiter <- mkParseVlanArbiter();
  
     function ParserState compute_next_state(Bit#(16) etherType);
        ParserState nextState = S0;
  
negative.code:       if (nextState0 == S3) begin
           if (verbose) $display("Parser:: ", fshow(cycle) + fshow("Vlan etherType=") + fshow(vlan0.etherType));
           unparsed_out_parse_vlan0_fifo.enq(pack(residue0));
           next_state_wire[0] <= tagged Valid nextState0;
        end
     endaction
     endseq;
  
     FSM fsm_parse_vlan_0 <- mkFSMWithPred(parse_vlan_0, state==S2);
  
     method Action start;
        fsm_parse_vlan_0.start;
  