anchor.diff:          serbvi.delay_wren(v);
       endmethod
       method Action                 fifo_wren(Bit#(1) v);
  +        bvi_fifo_wren_wire <= v;
           serbvi.fifo_wren(v);
       endmethod
       method Action                 reset(Bit#(1) v);
  
positive.code:         srval_q1: 0, srval_q2: 0, srval_q3: 0, srval_q4: 0,
          serdes_mode: "SLAVE", iobdelay: "NONE"},
          serdest, serdest_inverted.slowClock, clocked_by serdes_clock);
      Reg#(Bit#(1)) bvi_delay_wren_wire <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) bvi_reset_reg <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
  //
      Reg#(Bit#(3)) ctrl_ric <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) ctrl_fifo_reset <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ctrl_SAMPLEIN <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) tempfifo_wren <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) iserdes_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) ctrl_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  //
      Reg#(Bit#(1)) itemreq <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe0 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dreqpipe1 <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) sync_ric <- mkReg(3'b100, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) fifo_wren_sync <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dfifo_reset_r <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) dackint <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) ireset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(1)) sync_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
          let ds = dstate;
  
negative.code:         let fwsync = 0;
    
          dc = dc - 1;
          dreqpipe0 <= serbvi.itemreq();
          dreqpipe1 <= dreqpipe0;
          dfifo_reset_r <= serbvi.ctrl_fifo_reset();
          fifo_reset <= dfifo_reset_r;
          dfifo_wren_r <= bvi_fifo_wren_wire;
          if (bvi_delay_wren_wire == 1 && samplein_null[2] == 1)
              fwsync = dfifo_wren_r;
          else
              fwsync = bvi_fifo_wren_wire;
          //ireset_inc_ce <= sync_ric;
          iserdes_bitslip <= sync_bitslip;
          if (dstate == DIdle && dreqpipe1 == 1)
              begin
              serbvi.sync_reset_inc_ce(serbvi.ctrl_reset_inc_ce());
              sync_bitslip <= serbvi.ctrl_bitslip();
              dc = 3'b011;
              ds = DLow;
              end
  