anchor.diff:  module mkMemServerRW#(MemServerIndication indication,
   		      Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
   		      Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  -		      Vector#(numMMUs,MMU#(PhysAddrWidth)) mmus)
  -   (MemServer#(PhysAddrWidth, dataWidth, nMasters))
  +		      Vector#(numMMUs,MMU#(addrWidth)) mmus)
  +   (MemServer#(addrWidth, dataWidth, nMasters))
      
      provisos (Add#(1,a__,dataWidth),
   	     Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
  
positive.code:    endfunction
     Vector#(nMasters,Vector#(nwc, MemWriteClient#(dataWidth))) client_bins = genWith(selectClients(writeClients));
  
     module foo#(Integer i) (MMUAddrServer#(PhysAddrWidth,nMasters));
        let rv <- mkMMUAddrServer(mmus[i].addr[1]);
        return rv;
     endmodule
     Vector#(numMMUs,MMUAddrServer#(PhysAddrWidth,nMasters)) mmu_servers <- mapM(foo,genVector);
  
     Vector#(nMasters,MemWriteInternal#(PhysAddrWidth,dataWidth,MemServerTags)) writers;
     for(Integer i = 0; i < valueOf(nMasters); i = i+1) begin
        Vector#(numMMUs,Server#(ReqTup,Bit#(PhysAddrWidth))) ss;
        for(Integer j = 0; j < valueOf(numMMUs); j=j+1)
  	 ss[j] = mmu_servers[j].servers[i];
        writers[i] <- mkMemWriteInternal(client_bins[i], indication, ss);
  
negative.code: module mkSimpleMemServer#(Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
  			  Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  			  MemServerIndication indication,
  			  MMUIndication mmuIndication)(SimpleMemServer#(addrWidth, dataWidth,nMasters))
     provisos (Max#(nMasters,numReadClients,numReadClientsActual),
  	     Add#(numReadClients,numReadClientsNull,numReadClientsActual),
  	     Mul#(a__, nMasters, numReadClientsActual),
  