anchor.diff:  import Vector::*;
   import StmtFSM::*;
   import FIFO::*;
  +import Connectable::*;
   
   // portz libraries
   import AxiMasterSlave::*;
  
positive.code: import CtrlMux::*;
  import Portal::*;
  import Leds::*;
  
  
  // generated by tool
  
negative.code:       readData(rd);
     endrule
  endmodule
  
  (* no_default_clock, no_default_reset *)
  module mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n,
                            Clock sys_clk_p,     Clock sys_clk_n,
                            Reset pci_sys_reset_n)
                           (VC707_FPGA);
  
     let contentId = 64'h4563686f;
  
     X7PcieBridgeIfc#(8) x7pcie <- mkX7PcieBridge( pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n,
                                                   contentId );
     
     Reg#(Bool) interruptRequested <- mkReg(False, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     // instantiate user portals
     EchoIndicationProxy echoIndicationProxy <- mkEchoIndicationProxy(7, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     EchoRequestInternal echoRequestInternal <- mkEchoRequestInternal(echoIndicationProxy.ifc, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     EchoRequestWrapper echoRequestWrapper <- mkEchoRequestWrapper(1008,echoRequestInternal.ifc, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     
     Swallow swallow <- mkSwallow(clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     SwallowWrapper swallowWrapper <- mkSwallowWrapper(1009, swallow, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     
     Vector#(3,StdPortal) portals;
     portals[0] = echoIndicationProxy.portalIfc;
     portals[1] = echoRequestWrapper.portalIfc; 
     portals[2] = swallowWrapper.portalIfc; 
     
     // instantiate system directory
     Directory dir <- mkDirectory(portals, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     Vector#(1,StdPortal) directories;
     directories[0] = dir.portalIfc;
     
     // when constructing ctrl and interrupt muxes, directories must be the first argument
     let ctrl_mux <- mkAxiSlaveMux(directories,portals, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
     let interrupt <- mkInterruptMux(directories,portals, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     mkConnection(x7pcie.portal0, ctrl_mux, clocked_by x7pcie.clock125, reset_by x7pcie.reset125);
  
     rule requestInterrupt;
        if (interrupt && !interruptRequested)
  	 x7pcie.interrupt();
        interruptRequested <= interrupt;
     endrule
  
     interface pcie = x7pcie.pcie;
     //interface ddr3 = x7pcie.ddr3;
     method leds = zeroExtend({  pack(x7pcie.isCalibrated)
  			     , pack(True)
  			     , pack(False)
  			     , pack(x7pcie.isLinkUp)
  			     });
  
  endmodule: mkPcieTop
  