anchor.diff:  (* synthesize *)
   module mkProc(Proc#(DataSz));
       // Address map (some portions hard-coded in memory system
  -    // 0x0000_0000 - 0x4000_0000 : tightly coupled memory (not all used)
  +    // 0x0000_0000 - 0x2000_0000 : tightly coupled memory (not all used)
  +    // 0x2000_0000 - 0x3FFF_FFFF : rtc
       // 0x4000_0000 - 0xFFFF_FFFF : mmio
   
   `ifdef CONFIG_RV32
  
positive.code: 
      Wire#(Bool) extInterruptWire <- mkDWire(False);
  
      // Instead of using mkTightlyCoupledMemorySystem from MemorySystem.bsv, we
      // are including the mkBramIDExtMem here. This allows us to attach the RTC
      // without adding another mkServerJoiner.
  
      // Shared I/D Memory
      let sram <- mkBramIDExtMem;
  
      // This is the new way:
      FIFO#(UncachedMemReq) uncachedReqFIFO <- mkFIFO;
      FIFO#(UncachedMemResp) uncachedRespFIFO <- mkFIFO;
      let mmio_server <- mkUncachedConverter(toGPServer(uncachedReqFIFO, uncachedRespFIFO));
      let rtc_server <- mkUncachedConverter(rtc.memifc);
  
      // address decoding the dmem port of the sram for the RTC and MMIO
      function Bit#(2) whichServer(RVDMemReq r);
          if (r.addr >= 'h4000_0000) return 2;
          else if (r.addr >= 'h2000_0000) return 1;
          else return 0;
      endfunction
      function Bool getsResponse(RVDMemReq r);
          return r.op != tagged Mem St;
      endfunction
      let proc_dmem <- mkServerJoiner(whichServer, getsResponse, 2, vec(sram.dmem, rtc_server, mmio_server));
  
      Core core <- mkThreeStageCore(
                      sram.imem,
                      proc_dmem,
                      False, // inter-process interrupt
                      timer_interrupt, // timer interrupt
                      timer_value, // timer value
  
negative.code: 
  import Abstraction::*;
  import BasicMemorySystemBlocks::*;
  import BramIDMem::*;
  import Core::*;
  import MemoryMappedCSRs::*;
  import RTC::*;
  