anchor.diff:  	 let w1 = data[63:32];
   	 let head = reqHeadReg;
   	 let tail = reqTailReg;
  -	 $display("receiveReqHeadTail state=%d w0=%x w1=%x", reqState, w0, w1);
   	 if (reqState == HeadRequested) begin
  +	    reqLimitReg <= w0;
   	    reqHeadReg <= w1;
  +	    head = w1;
   	    reqState <= TailRequested;
   	 end
   	 else begin
  -	    tail = w0;
  -	    if (reqTailReg == 0)
  +	    if (reqTailReg == 0) begin
  +	       tail = w0;
   	       reqTailReg <= tail;
  -	     if (tail != reqHeadReg)
  -		reqState <= RequestMessage;
  -	     else
  -		reqState <= Idle;
  -	 end
  +	    end
  +	    if (tail != reqHeadReg)
  +	       reqState <= RequestMessage;
  +	    else
  +	       reqState <= Idle;
  +	 end
  +	 if (head != tail)
  +	    $display("receiveReqHeadTail state=%d w0=%x w1=%x", reqState, w0, w1);
         endrule
   
         rule requestMessage if (reqState == RequestMessage);
   	 Bit#(32) wordCount = reqHeadReg - reqTailReg;
  -	 if (reqTailReg < reqHeadReg)
  +	 if ((reqTailReg & 1) == 1) begin
  +	    $display("WARNING requestMessage: reqTail=%d is odd.", reqTailReg);
  +	 end
  +	 let tail = reqTailReg + wordCount;
  +	 if (reqHeadReg < reqTailReg) begin
   	    $display("requestMessage wrapped: head=%d tail=%d", reqHeadReg, reqTailReg);
  +	    wordCount = reqLimitReg - reqTailReg;
  +	    tail = 4;
  +	 end
   	 //$display("requestMessage id=%d tail=%h wordCount=%d", sglIdReg, reqTailReg, wordCount);
  -	 reqTailReg <= reqTailReg + wordCount;
  +
  +	 reqTailReg <= tail;
   	 wordCountReg <= truncate(wordCount);
   	 demuxCountReg <= truncate(wordCount);
   	 let fetchCount = wordCount;
  
positive.code:       endrule
        rule waiting if (reqState == Waiting);
  	 let done <- writeEngine.writeServers[0].response.get();
  	 $display("done waiting for write");
  	 reqState <= Idle;
        endrule
  
  
negative.code:    MemreadEngineV#(64,2,2) readEngine <- mkMemreadEngine();
     MemwriteEngineV#(64,2,2) writeEngine <- mkMemwriteEngine();
  
     Bool verbose = False;
  
     Reg#(Bit#(32)) sglIdReg <- mkReg(0);
     Reg#(Bool)     readyReg   <- mkReg(False);
  
     if (valueOf(numRequests) > 0) begin
        // read the head and tail pointers, if they are different, then read a request
        Reg#(Bit#(32)) reqLimitReg <- mkReg(0);
        Reg#(Bit#(32)) reqHeadReg <- mkReg(0);
        Reg#(Bit#(32)) reqTailReg <- mkReg(0);
        Reg#(Bit#(16)) wordCountReg <- mkReg(0);
  