anchor.diff:  import GetPut::*;
   import ClientServer::*;
   import CtrlMux::*;
  +import Gearbox::*;
  +import Clocks::*;
   
   import MIFO::*;
   import Pipe::*;
  
positive.code: 	 let head = indHeadReg;
  	 let tail = indTailReg;
  	 if (indState == HeadRequested) begin
  	    indLimitReg <= w0;
  	    indHeadReg <= w1;
  	    head = w1;
  	    indState <= TailRequested;
  	 end
  	 else begin
  	    if (indTailReg == 0) begin
  	       tail = w0;
  	       indTailReg <= tail;
  	    end
  	    if (tail != indHeadReg)
  	       indState <= RequestMessage;
  	    else
  	       indState <= Idle;
  	 end
  	 if (verbose)
  	    $display("receiveIndHeadTail state=%d w0=%x w1=%x head=%d tail=%d limit=%d", indState, w0, w1, head, tail, indLimitReg);
        endrule
  endmodule
  
  module mkSharedMemoryPortal#(PipePortal#(numRequests, numIndications, 32) portal)(SharedMemoryPortal#(64));
  
negative.code: endmodule
  
  module mkSharedMemoryIndicationPortal#(PipePortal#(numRequests, numIndications, 32) portal,
  				       MemreadServer#(64) readEngine,
  				       MemwriteServer#(64) writeEngine,
  				       Reg#(Bit#(32)) sglIdReg,
  				       Reg#(Bool)     readyReg)(SharedMemoryPortal#(64));
        // read the head and tail pointers, if they are different, then read a request
        Reg#(Bit#(16)) indLimitReg <- mkReg(0);
        Reg#(Bit#(16)) indHeadReg <- mkReg(0);
        Reg#(Bit#(16)) indTailReg <- mkReg(0);
        Reg#(Bit#(16)) wordCountReg <- mkReg(0);
        Reg#(Bit#(16)) messageWordsReg <- mkReg(0);
        Reg#(Bit#(16)) methodIdReg <- mkReg(0);
        Reg#(SharedMemoryPortalState) indState <- mkReg(Idle);
  
     let verbose = True;
  
     function Bool pipeOutNotEmpty(PipeOut#(a) po); return po.notEmpty(); endfunction
     Vector#(numIndications, Bool) readyBits = map(pipeOutNotEmpty, portal.indications);
     Bool      interruptStatus = False;
     Bit#(16)  readyChannel = -1;
     for (Integer i = 0; i < valueOf(numIndications); i = i + 1) begin
        if (readyBits[i]) begin
           interruptStatus = True;
           readyChannel = fromInteger(i);
        end
     end
  
        rule updateIndHeadTail if (indState == Idle && readyReg);
  	 readEngine.cmdServer.request.put(MemengineCmd { sglId: sglIdReg,
  