anchor.diff:  	 interface Put writeReq = ctrlWriteAddrGenerator.request;
   	 interface Put writeData;
   	    method Action put(MemData#(dataWidth) d);
  -	       let b <- ctrlWriteAddrGenerator.addrBeat.get();
  -	       //$display("mkCtrl.writeData addr=%h data=%h last=%d", b.addr, d.data, b.last);
  -	       let v = d.data;
  -	       let addr = b.addr;
  -	       if (addr == 'h000)
  -		  noAction;
  -	       if (addr == 'h004)
  -		  interruptEnableReg <= v[0] == 1'd1;
  -	       if (b.last)
  -		  ctrlWriteDoneFifo.enq(b.tag);
  +	       ctrlWriteDataFifo.enq(d);
   	    endmethod
   	 endinterface
   	 interface Get writeDone;
  
positive.code:    AddressGenerator#(addrWidth,dataWidth) fifoReadAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(addrWidth,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();
     FIFO#(Bit#(ObjectTagSize))                  fifoWriteDoneFifo <- mkFIFO();
     interface MemReadServer read_server;
        interface Put readReq;
  	 method Action put(MemRequest#(addrWidth) req);
  
negative.code:       endinterface
        interface Get readData;
  	 method ActionValue#(MemData#(dataWidth)) get();
  	    let d <- toGet(fifoReadDataFifo).get();
  	    return d;
  	 endmethod
        endinterface
     endinterface
  