anchor.diff:      Reg#(Bit#(32)) underflowReadCountReg <- mkReg(0);
       Reg#(Bit#(32)) outOfRangeReadCountReg <- mkReg(0);
       Reg#(Bit#(32)) outOfRangeWriteCount <- mkReg(0);
  -    Reg#(Vector#(3, Bit#(3))) priorities <- mkReg(replicate(0));
  -    function Bit#(3) maxPriority(); return fold(max, priorities); endfunction
  -    function Tuple2#(Bit#(iccsz), Bit#(3)) getMaxPriorityRequest();
  -        function Bit#(iccsz) channelNumber(Integer i); UInt#(iccsz) c = fromInteger(i); return pack(c); endfunction
  -        Vector#(3, Bit#(iccsz)) requests = genWith(channelNumber);
  -        function Tuple2#(Bit#(iccsz),Bit#(3)) maxreq(Tuple2#(Bit#(iccsz),Bit#(3)) a, Tuple2#(Bit#(iccsz),Bit#(3)) b);
  -           if (tpl_2(a) > tpl_2(b))
  -               return a;
  -           else
  -               return b;
  -        endfunction
  -        return fold(maxreq, zip(requests, priorities));
  -    endfunction
  -    Reg#(Tuple2#(Bit#(iccsz),Bit#(3))) maxPriorityRequest <- mkReg(tuple2(0,0));
  -    rule updateMaxPriorityRequest;
  -        maxPriorityRequest <= getMaxPriorityRequest();
  -    endrule
  -
  -    function Bool my_or(Bool a, Bool b) = a || b;
  -    function Bool read_wire (PulseWire a) = a._read;    
  +    ReadyQueue#(3, Bit#(3), Bit#(3)) readyQueue <- mkFirstReadyQueue();
  +
       // this is here to disable the warning that the put failed rule can never fire
       Reg#(Bool) putEnableReg <- mkReg(True);
       Reg#(Bool) interruptEnableReg <- mkReg(False);
  -    let       interruptStatus = (maxPriority() > 0);
  +    let       interruptStatus = (tpl_2(readyQueue.maxPriorityRequest()) > 0);
       function Bit#(32) read_wire_cvt (PulseWire a) = a._read ? 32'b1 : 32'b0;
       function Bit#(32) my_add(Bit#(32) a, Bit#(32) b) = a+b;
   
  
positive.code:         end
          axiSlaveReadDataFifo.enq(v);
      endrule
  
      ToBit32#(PutFailed$Response) putFailed$responseFifo <- mkToBit32();
      rule putFailed$axiSlaveRead if (axiSlaveReadAddrFifo.first[14] == 0 && 
                                           axiSlaveReadAddrFifo.first[13:8] == putFailed$Offset);
          axiSlaveReadAddrFifo.deq;
  
negative.code:         end
          axiSlaveReadDataFifo.enq(v);
      endrule
     rule readybits0;
      readyQueue.readyBits[0] <= heard$responseFifo.notEmpty();
     endrule
  
      rule heard2$axiSlaveRead if (axiSlaveReadAddrFifo.first[14] == 0 && 
                                           axiSlaveReadAddrFifo.first[13:8] == heard2$Offset);
          axiSlaveReadAddrFifo.deq;
  