anchor.diff:  
       rule datain_rule;
           Bit#(10) dout = 0;
  -        Bit#(10) edgeo = 0;
           for (Integer i = 0; i < 10; i = i + 1)
               dout[i] = iserdes_data[i].read();
  -        for (Integer i = 0; i < 9; i = i + 1)
  -            edgeo[i] = dout[i] ^ dout[i+1];
  -        edgeo[9] = dout[0] ^ dout[9];
  -        edge_int <= edgeo;
  -        edge_intor_reg <= pack(edgeo != 0);
           if (fifo_wren_sync.read() == 1)
               begin
               dfifo.di({6'b0,dout});
  
positive.code:     schedule (reset, di, rden, wren, dataout, empty) CF (reset, di, rden, wren, dataout, empty);
  endmodule: mkFIFO18
  
  typedef enum { DIdle, DValid} DState deriving (Bits,Eq);
  typedef enum { QIdle, QTrain, QOn, QOff} QState deriving (Bits,Eq);
  typedef enum { AIdle, ADelay, AWDelay, AEdge, ACEdge, AWait, ACompare, AValid,
       A1Changed, A1Stable, ASecond, AFound, AResetman, AStart, AAlign, ADone } AState deriving (Bits,Eq);
  
  
negative.code:     Reg#(Bit#(10)) ctrl_data_temp <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) data_init <- mkReg(0);
      Reg#(Bit#(10)) edge_init <- mkReg(0);
      Reg#(Bit#(10)) edge_int <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);
      SyncFIFOIfc#(Bit#(1)) serdes_setting <- mkSyncFIFO(2, defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
      Wire#(Bit#(1)) this_align_busy_wire <- mkDWire(0);
      Reg#(Bit#(16)) top_align_counter <- mkReg(0);
      Reg#(QState)  qstate <- mkReg(QIdle);
      Reg#(AState)  astate <- mkReg(AIdle);
      Reg#(Bit#(11)) maxcount <- mkReg(0);
  