anchor.diff:     FIFO#(Tuple2#(Bit#(serverIdxSz),Bool))           donef <- mkSizedBRAMFIFO(32); // is this the right size?
      
      Vector#(numServers, FIFO#(Bool))              outfs <- replicateM(mkSizedFIFO(1));
  -   Vector#(numServers, FIFOF#(Tuple2#(Bit#(serverIdxSz), MemengineCmd))) cmds_in <- replicateM(mkSizedFIFOF(1));
  -   FunnelPipe#(1, numServers, Tuple2#(Bit#(serverIdxSz), MemengineCmd),bpc) cmds_in_funnel <- mkFunnelPipesPipelined(map(toPipeOut,cmds_in));
  +   Vector#(numServers, FIFOF#(MemengineCmd))    cmds_in <- replicateM(mkSizedFIFOF(1));
      Vector#(numServers, FIFOF#(Bit#(dataWidth)))  write_data_buffs <- replicateM(mkSizedBRAMFIFOF(bufferSizeBeats));
      Vector#(numServers, PipeOut#(Bit#(dataWidth))) foo = map(toPipeOut, write_data_buffs); 
      BurstFunnel#(numServers,dataWidth) write_data_funnel <- mkBurstFunnel(bufferSizeBeats);
  
positive.code: 			else begin
  `endif
  			   outs0[i] <= outs0[i]+1;
  			   cmds_in[i].enq(tuple2(fromInteger(i),c));
  			   write_data_funnel.burstLen[i] <= c.burstLen >> beat_shift;
  			   //$display("(%d) %h %h %h", i, c.base, c.len, c.burstLen);
  `ifdef BSIM
  
negative.code:    
     
     Integer bufferSizeBeats = bufferSizeBytes/valueOf(dataWidthBytes);
     Vector#(numServers, Reg#(Bool))               outs1 <- replicateM(mkReg(False));
     Vector#(numServers, Reg#(Bit#(outCntSz)))     outs0 <- replicateM(mkReg(0));
     Vector#(numServers, ConfigCounter#(16))        buffCap <- replicateM(mkConfigCounter(0));
     Vector#(numServers, Reg#(MemengineCmd))        cmdRegs <- replicateM(mkReg(unpack(0)));
  
     Reg#(Bool) load_in_progress <- mkReg(False);
     FIFO#(Tuple3#(MemengineCmd,Bool,Bool))         loadf_b <- mkSizedFIFO(1);
  