anchor.diff:  	    779: tlpDataScratchpad[3] <= dword;
   	    780: tlpDataScratchpad[4] <= dword;
   	    781: tlpDataScratchpad[5] <= dword;
  -	    782: axiTestEnabledReg <= dword;
  -	    783: addrLowerWordReg <= dword;
  -	    784: addrUpperWordReg <= dword;
  -	    785: testResultReg <= dword;
  -	    786: testStateReg <= dword;
   
   	    787: pipeliningEnabledReg <= (dword != 0) ? True : False;
   	    788: axiEnabledReg <= (dword != 0) ? True : False;
  
positive.code: 	 779: return tlpDataBramResponseSlice(3);
  	 780: return tlpDataBramResponseSlice(4);
  	 781: return tlpDataBramResponseSlice(5);
  	 782: return axiTestEnabledReg;
  	 783: return addrLowerWordReg;
  	 784: return addrUpperWordReg;
  	 785: return testResultReg;
  	 786: return testStateReg;
  	 787: return pipeliningEnabledReg ? 1 : 0;
  	 788: return axiEnabledReg ? 1 : 0;
  	 789: return tlpDataBramRdAddrReg;
  
negative.code:    interface Reg pipeliningEnabled = pipeliningEnabledReg;
     interface Reg byteSwap = byteSwapReg;
     interface Reg use4dw = use4dwReg;
     interface Reg numPortals = numPortalsReg;
     interface Reg tlpDataBramWrAddr = tlpDataBramWrAddrReg;
     interface Reg tlpSeqno = tlpSeqnoReg;
     interface Reg tlpOutCount = tlpOutCountReg;
  