anchor.diff:        pcie.phy.status6(phystatus_wires[6]);
         pcie.phy.status7(phystatus_wires[7]);
      endrule
  -//`endif
   
      method Clock coreclkout_hip;
         return pcie.coreclkout.hip;
  
positive.code:       method Bit#(8) ko_cpl_spc_header;return pcie.ko.cpl_spc_header;endmethod
     endinterface
  
  `ifdef PCIES5_SIM
     interface PcieS5HipPipe hip_pipe;
        method Action rxdata(Vector#(8, Bit#(8)) a);
           writeVReg(rxdata_wires, a);
  
negative.code:    interface PcieS5Txout tx;
  endinterface
  
  interface PcieS5HipPipe;
  (* prefix="", result="rxdata" *)     method Action     rxdata    (Vector#(8, Bit#(8)) rxdata);
  (* prefix="", result="rxdatak" *)    method Action     rxdatak   (Vector#(8, Bit#(1)) rxdatak);
  (* prefix="", result="rxelecidle" *) method Action     rxelecidle(Vector#(8, Bit#(1)) rxelecidle);
  (* prefix="", result="rxstatus" *)   method Action     rxstatus  (Vector#(8, Bit#(3)) rxstatus);
  (* prefix="", result="rxvalid" *)    method Action     rxvalid   (Vector#(8, Bit#(1)) rxvalid);
  