anchor.diff:                  CSRmscycle_delta:       mscycle_delta_csr;
                   CSRmstime_delta:        mstime_delta_csr;
                   CSRmsinstret_delta:     msinstret_delta_csr;
  +                CSRmucycleh_delta:      mucycleh_delta_csr;
  +                CSRmutimeh_delta:       mutimeh_delta_csr;
  +                CSRmuinstreth_delta:    muinstreth_delta_csr;
  +                CSRmscycleh_delta:      mscycleh_delta_csr;
  +                CSRmstimeh_delta:       mstimeh_delta_csr;
  +                CSRmsinstreth_delta:    msinstreth_delta_csr;
                   default:                (readOnlyReg(64'h0));
               endcase);
       endfunction
  
positive.code:                 CSRmscycle_delta:       True;
                  CSRmstime_delta:        True;
                  CSRmsinstret_delta:     True;
                  default:                False;
              endcase);
      endfunction
  
negative.code:     // Priv 1.9 CSRs
  
      // Machine Timers and Counters
      Reg#(Data) mcycle_csr   = readOnlyReg(truncate(cycle_counter));
      Reg#(Data) mtime_csr    = readOnlyReg(truncate(time_counter));
      Reg#(Data) minstret_csr = readOnlyReg(truncate(instret_counter));
  
      // Upper 32-bits of CSRs for RV32: (these will just be unused copies of
      // the other cycle/time/instret registers for RV64)
      Reg#(Data) mcycleh_csr   = readOnlyReg(truncateLSB(cycle_counter));
      Reg#(Data) mtimeh_csr    = readOnlyReg(truncateLSB(time_counter));
      Reg#(Data) minstreth_csr = readOnlyReg(truncateLSB(instret_counter));
  
      // Machine Counter-Delta Registers
      Reg#(Bit#(64)) mucycle_delta_field   <- mkReg(0);
      Reg#(Bit#(64)) mutime_delta_field    <- mkReg(0);
      Reg#(Bit#(64)) muinstret_delta_field <- mkReg(0);
      Reg#(Bit#(64)) mscycle_delta_field   <- mkReg(0);
      Reg#(Bit#(64)) mstime_delta_field    <- mkReg(0);
      Reg#(Bit#(64)) msinstret_delta_field <- mkReg(0);
  
      Reg#(Data) mucycle_delta_csr    <- truncateReg(mucycle_delta_field);
      Reg#(Data) mutime_delta_csr     <- truncateReg(mutime_delta_field);
      Reg#(Data) muinstret_delta_csr  <- truncateReg(muinstret_delta_field);
      Reg#(Data) mscycle_delta_csr    <- truncateReg(mscycle_delta_field);
      Reg#(Data) mstime_delta_csr     <- truncateReg(mstime_delta_field);
      Reg#(Data) msinstret_delta_csr  <- truncateReg(msinstret_delta_field);
      Reg#(Data) mucycleh_delta_csr   <- truncateRegLSB(mucycle_delta_field);
      Reg#(Data) mutimeh_delta_csr    <- truncateRegLSB(mutime_delta_field);
      Reg#(Data) muinstreth_delta_csr <- truncateRegLSB(muinstret_delta_field);
      Reg#(Data) mscycleh_delta_csr   <- truncateRegLSB(mscycle_delta_field);
      Reg#(Data) mstimeh_delta_csr    <- truncateRegLSB(mstime_delta_field);
      Reg#(Data) msinstreth_delta_csr <- truncateRegLSB(msinstret_delta_field);
  
      // User FPU
      Reg#(Data) fflags_csr = addWriteSideEffect(zeroExtendReg(fflags_field), fs_field._write(2'b11));
  