anchor.diff:     interface Vector#(1,MemWriteClient#(DataBusWidth))     writeClient;
   endinterface
   
  -typedef 15 NumOutstandingRequests;
  -typedef TMul#(NumOutstandingRequests,TMul#(32,4)) BufferSizeBytes;
  +typedef 31 NumOutstandingRequests;
  +typedef TMul#(NumOutstandingRequests,1024) BufferSizeBytes;
   
   function Bit#(dsz) memdatafToData(MemDataF#(dsz) mdf); return mdf.data; endfunction
   
  
positive.code:    Vector#(numChannels, FIFO#(Tuple3#(Bit#(32),Bit#(32),Bit#(32)))) writeReqs <- replicateM(mkSizedFIFO(valueOf(NumOutstandingRequests)));
     Vector#(numChannels, FIFOF#(MemDataF#(DataBusWidth))) transferToFpgaFifo <- replicateM(mkFIFOF());
     Vector#(numChannels, FIFO#(Bit#(8))) writeTags <- replicateM(mkSizedFIFO(valueOf(NumOutstandingRequests)));
     Vector#(numChannels, FIFO#(Bit#(8))) readTags <- replicateM(mkSizedFIFO(valueOf(NumOutstandingRequests)));
     Reg#(Bit#(BurstLenSize)) writeRequestSizeReg <- mkReg(64);
     Reg#(Bit#(BurstLenSize)) readRequestSizeReg <- mkReg(256);
     Reg#(Bit#(32)) cyclesReg <- mkReg(0);
  
negative.code: import MemReadEngine::*;
  import MemWriteEngine::*;
  import HostInterface::*;
  `include "ConnectalProjectConfig.bsv"
  
  interface DmaRequest;
  