anchor.diff:      rule copyReadWriteRule (copyBusy);
          let data <- copy_read_chan.readData.get;
          //$display("copyReadWrite addr %h", copyWriteAddr);
  -       copy_write_chan.writeReq.put(DmaRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: 1, tag: copyWriteAddr[8:3]});
  +       copy_write_chan.writeReq.put(DmaRequest{pointer: copyWritePointer, address: copyWriteAddr, burstLen: 1, tag: copyWriteAddr[8:3]});
          copy_write_chan.writeData.put(DmaData{data: data.data, tag: copyWriteAddr[8:3]});
          copyWriteAddr <= copyWriteAddr + 8;
       endrule
  
positive.code:    Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
     Reg#(Bit#(DmaOffsetSize)) copyReadAddr <- mkReg(0);
     Reg#(Bit#(DmaOffsetSize)) copyWriteAddr <- mkReg(0);
     Reg#(DmaPointer) copyReadHandle <- mkReg(0);
     Reg#(DmaPointer) copyWriteHandle <- mkReg(0);
     Reg#(Bit#(32)) copyTag <- mkReg(0);
     Reg#(Bool) copyBusy <- mkReg(False);
     Reg#(Bit#(4)) cmdCtr <- mkReg(0);
  
negative.code: // The interface to the copyengine is a pair of fifos which supply and accept
  // blocks of 8 64 bit words
  // A Command:
  //  word 0: COPY[63:56]
  //  word 1: readMemPointer
  //  word 2: readAddress
  //  word 3  writeMemPointer
  //  word 4: writeAddress
  //  word 5: bytecount
  //  word 6: unused
  //  word 7: tag
  // Status
  //  word0-6 all 0
  //  word7  TAG[31:0]
  