anchor.diff:     return v;
      endmethod
   
  -   interface AxiMasterWrite axi;
  -       method ActionValue#(Bit#(32)) writeAddr() if (operationInProgress && !addressPresented);
  +   interface Axi3WriteClient axi;
  +       method ActionValue#(Axi3WriteRequest#(idWidth)) address() if (operationInProgress && !addressPresented);
              addrsBeatCount <= addrsBeatCount + 1;
              if (oneBeatAddressReg)
                  addressPresented <= True;
              let ptrValue = ptrReg;
  -           return ptrReg;
  -       endmethod
  -       method Bit#(8) writeBurstLen();
  -           return burstCountReg-1;
  -       endmethod
  -       method Bit#(3) writeBurstWidth();
  -           if (valueOf(busWidth) == 32)
  -               return 3'b010; // 3'b010: 32bit, 3'b011: 64bit, 3'b100: 128bit
  -           else if (thirtyTwoBitTransferReg)
  -               return 3'b010;
  -           else
  -               return 3'b011;
  -       endmethod
  -       method Bit#(2) writeBurstType();  // drive with 2'b01 increment address
  -           return 2'b01; // increment address
  -       endmethod
  -       method Bit#(3) writeBurstProt(); // drive with 3'b000
  -           return 3'b000;
  -       endmethod
  -       method Bit#(4) writeBurstCache(); // drive with 4'b0011
  -           return 4'b0011;
  -       endmethod
  -
  -       method ActionValue#(Bit#(busWidth)) writeData() if (operationInProgress && dfifo.notEmpty);
  +           return Axi3WriteRequest { address: ptrValue, burstLen: burstCountReg-1, id: 1};
  +       endmethod
  +
  +       method ActionValue#(Axi3WriteData#(busWidth, busWidthBytes, idWidth)) data() if (operationInProgress && dfifo.notEmpty);
              ptrReg <= ptrReg + pack(fromInteger(valueOf(busWidth)/8));
              let bc = burstCountReg;
  -           if (bc == 8'd1)
  +           if (bc == 4'd1)
              begin
                  operationInProgress <= False;
                  lastDataBeatCount <= lastDataBeatCount + 1;
  
positive.code:        return v;
     endmethod
  
     interface AxiMasterRead axi;
         method ActionValue#(Bit#(32)) readAddr() if (operationInProgress && !addressPresented);
             addrsBeatCount <= addrsBeatCount + 1;
             if (oneBeatAddressReg)
                 addressPresented <= True;
             let ptrValue = ptrReg;
             return ptrReg;
         endmethod
         method Bit#(8) readBurstLen();
             return burstCountReg-1;
         endmethod
         method Bit#(3) readBurstWidth();
             if (valueOf(busWidth) == 32)
                 return 3'b010; // 3'b010: 32bit, 3'b011: 64bit, 3'b100: 128bit
             else if (thirtyTwoBitTransferReg)
                 return 3'b010;
             else
                 return 3'b011;
         endmethod
         method Bit#(2) readBurstType();  // drive with 2'b01
             return 2'b01;
         endmethod
         method Bit#(3) readBurstProt(); // drive with 3'b000
             return 3'b000;
         endmethod
         method Bit#(4) readBurstCache(); // drive with 4'b0011
             return 4'b0011;
         endmethod
         method Action readData(Bit#(busWidth) data, Bit#(2) resp, Bit#(1) last, Bit#(1) id) if (rfifo.notFull && operationInProgress);
             let bc = burstCountReg - 1;
             if (bc == 1)
                 lastDataBeatCount <= lastDataBeatCount + 1;
  
             if (resp == 2'b00)
             begin
                 burstCountReg <= bc;
                 ptrReg <= ptrReg + pack(fromInteger(valueOf(busWidth)/8));
                 rfifo.enq(data);
                 wordsReceivedCount <= wordsReceivedCount + 1;
             end
             else
             begin
                 axiRrespFifo.enq(resp);
             end
  
             if (resp != 2'b00 || bc == 0)
                 operationInProgress <= False;
         endmethod
     endinterface
  
negative.code: 
     method Bit#(32) readStatus(Bit#(12) addr);
  
     interface Axi3WriteClient#(busWidth,busWidthBytes,idWidth) axi;
     method Action enq(Bit#(busWidth) value);
     method ActionValue#(Bit#(32)) getResponse();
  endinterface
  
  interface FifoFromAxi#(type busWidth, type idWidth);
     interface Reg#(Bit#(32)) base;
     interface Reg#(Bit#(32)) bounds;
     interface Reg#(Bit#(32)) threshold;
  