anchor.diff:      Reset defaultReset <- exposeCurrentReset();
       ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);
       Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock, serdest, serdest_inverted.slowClock, defaultClock);
  -    FIFO18 dfifo <- mkFIFO18(serdes_clock, reset_by serbvi.fifo_reset);
  +    //MakeResetIfc fifo_reset <- mkReset(2, True, serdes_clock);
  +    FIFO18 dfifo <- mkFIFO18(serdes_clock);
       MakeResetIfc iodelay_reset <- mkReset(2, True, serdes_clock, clocked_by serdes_clock, reset_by serdes_reset);
   
  +    rule dfifo_reset_rule;
  +        dfifo.reset(serbvi.fifo_reset);
  +    endrule
  +    //rule fresetrule if (serbvi.fifo_reset == 1);
  +        //fifo_reset.assertReset();
  +    //endrule
       rule resetrule if (serbvi.iodelay_reset_inc_ce()[2] == 1);
           iodelay_reset.assertReset();
       endrule
  
positive.code: 
      default_clock clock(RDCLK);
      input_clock clkdiv (WRCLK) = clkdiv;
      // reset RST;
      port DIP = 0;
  
      method          di(DI) enable((*inhigh*) en0) clocked_by (clock);
      method          rden(RDEN) enable((*inhigh*) en2) clocked_by (clock);
      method          wren(WREN) enable((*inhigh*) en3) clocked_by (clock);
      method DO       dataout() clocked_by(clock);
      method EMPTY    empty() clocked_by(clock);
     schedule (di, rden, wren, dataout, empty) CF (di, rden, wren, dataout, empty);
  endmodule: mkFIFO18
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
  
negative.code:       method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
        method                  fifo_wren(FIFO_WREN) enable((*inhigh*) en10) clocked_by (clkdiv);
        method FIFO_WREN_SYNC   fifo_wren_sync() clocked_by (clock);
        method FIFO_RESET       fifo_reset() clocked_by(clkdiv);
        method                  delay_wren(DELAY_WREN) enable((*inhigh*) en11) clocked_by (clkdiv);
        method                  reset(RESET) enable((*inhigh*) en16) clocked_by (clkdiv);
        method FIFO_DATAOUT  dataout() clocked_by(clkdiv);
     schedule (fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip)
           CF (fifo_reset, idelay_out, fifo_wren, reset, delay_wren, dataout, iodelay_reset_inc_ce, bitslip, align_busy, aligned, samplein, fifo_wren_sync, align_start, autoalign, training, manual_tap, bitslip);
  endmodule: mkIserdesbvi
  
  interface IserdesDatadeser;
  