anchor.diff:     // stage 1: address validation (latency = 1)
      FIFO#(RRec#(numClients,addrWidth))  reqFifo <- mkFIFO;
      // stage 2: write commands (maximum buffering to handle high latency writes)
  -   FIFO#(DRec#(numClients, addrWidth)) dreqFifo <- mkSizedBRAMFIFO(valueOf(TMul#(TAG_DEPTH,numClients)));
  +   FIFO#(DRec#(numClients, addrWidth)) mwDreqFifo <- mkSizedBRAMFIFO(valueOf(TMul#(TAG_DEPTH,numClients)));
      // stage 3: write data (maximum buffering, though I have no idea if any hosts will begin the next data transfer before sending the write ack)
      Vector#(numClients, FIFO#(RResp#(numClients,addrWidth))) respFifos <- replicateM(mkSizedBRAMFIFO(valueOf(TAG_DEPTH)));
      // stage 4: write done (minimal buffering required)
  
positive.code:       writeClients[client].writeDone.put(orig_tag);
     endrule
     
     interface MemWriteClient write_client;
        interface Get writeReq;
  	 method ActionValue#(MemRequest#(addrWidth)) get();
  
negative.code: 	    let client = reqFifo.first.client;
  	    let rename_tag = reqFifo.first.rename_tag;
  	    reqFifo.deq;
  	    mwDreqFifo.enq(DRec{req:req, client:client, rename_tag:rename_tag, last: False });
  	    //$display("writeReq: client=%d, rename_tag=%d", client,rename_tag);
  	    return MemRequest{addr:physAddr, burstLen:req.burstLen, tag:extend(rename_tag)};
  	 endmethod
        endinterface
        interface Get writeData;
  	 method ActionValue#(MemData#(dataWidth)) get();
              let d <- toGet(memDataFifo).get();
              return d;
  	 endmethod
        endinterface
        interface Put writeDone;
  