anchor.diff:  interface Branch_Predictor_IFC;
      method Action  reset;
   
  +   // ----------------
  +   // Request prediction for given pc; available on 'predict_rsp' on next cycle
  +
      method Action  predict_req (WordXL pc);
  +
  +   // ----------------
  +   // Response for 'predict_req' from an earlier cycle.
  +   // Args describe current instruction just now fetched in Fetch stage,
  +   // and are used to choose RAS actions if any, and size of
  +   // fall-through PC if no prediction.
   
      (* always_ready *)
      method WordXL  predict_rsp (Bool is_i32_not_i16, Instr instr);
  +
  +   // ----------------
  +   // Train BTB and RAS.
  +   // First 3 args are from current fetch, to train RAS.
  +   // cf_info arg is from Exec stage (downpipe), from an earlier (older) instruction.
   
      method Action bp_train (WordXL   pc,
   			   Bool     is_i32_not_i16,
  
positive.code: // BSV library imports
  
  import Vector    :: *;
  import BRAMCore  :: *;
  import FIFOF     :: *;
  
  
negative.code:       rg_index     <= 0;
        rg_resetting <= True;
     endmethod
  
     // ----------------
     // Request prediction for given pc; available on 'predict_rsp' on next cycle
  
     method Action  predict_req (WordXL pc) if (! rg_resetting);
        if (verbosity > 1)
  