anchor.diff:        deparser_start_time <= clk_cnt;
       end
     endrule
  -  rule clear if (!start_fsm && curr_state == StateDeparseIdle);
  +  rule stop if (!start_fsm && curr_state == StateDeparseIdle);
       if (started) begin
  -      deparse_ethernet.clear;
  -      deparse_ipv4.clear;
  +      deparse_ethernet.stop;
  +      deparse_ipv4.stop;
         started <= False;
         deparser_end_time <= clk_cnt;
       end
  
positive.code:     let data_last_cycle <- toGet(internal_fifo_144).get;
      Bit#(272) data = {data_this_cycle, data_last_cycle};
      Vector#(272, Bit#(1)) dataVec = unpack(data);
      let hdr = extract_Ipv4T(pack(takeAt(0, dataVec)));
      $display(fshow(hdr));
      parseStateFifo.enq(StateParseIpv4);
      parsed_ipv4_protocol_fifo.enq(hdr.protocol);
      next_state_wire[0] <= tagged Valid StateParseStart;
    endaction
    endseq;
    FSM fsm_parse_ipv4 <- mkFSM(stmt_parse_ipv4);
    rule start_fsm if (start_wire);
      fsm_parse_ipv4.start;
    endrule
    rule clear_fsm if (clear_wire);
      fsm_parse_ipv4.abort;
    endrule
  
    method start = start_wire.send;
    method stop = clear_wire.send;
    interface parse_ethernet = toPut(unparsed_parse_ethernet_fifo);
    interface parsedOut_ipv4_protocol = toGet(parsed_ipv4_protocol_fifo);
  endmodule
  
negative.code: 
    FIFO#(EtherData) deparse_ipv4_fifo <- mkFIFO;
    PulseWire start_wire <- mkPulseWire;
    PulseWire stop_wire <- mkPulseWire;
  
    function DeparserState compute_next_state(Bit#(16) v);
      DeparserState nextState = StateDeparseIdle;
  