anchor.diff:     interface MemMaster#(32,32) master;
      interface Axi3Slave#(40,dsz,6)  slave;
      interface Put#(Tuple2#(Bit#(64),Bit#(32))) interruptRequest;
  +   interface Client#(TLPData#(16), TLPData#(16)) pci;
   endinterface
   
  -module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId,
  -Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(dsz))
  +module [Module] mkPcieHost#(PciId my_pciId)(PcieHost#(dsz))
   provisos(
      Mul#(TDiv#(dsz, 8), 8, dsz),
       Add#(a__, TDiv#(dsz, 32), 8),
  
positive.code:    Reset epReset125 <- mkAsyncReset(4, user_reset_n, epClock125);
  
     let portalTop <- mkSynthesizeablePortalTop(clocked_by epClock125, reset_by epReset125);
     PcieHost#(DataBusWidth) pciehost <- mkPcieHost(epClock250, epReset250,
           PciId{ bus:  _ep.cfg.bus_number(), dev: _ep.cfg.device_number(), func: _ep.cfg.function_number()},
           _ep.tlp, clocked_by epClock125, reset_by epReset125);
  
     mkConnection(pciehost.master, portalTop.slave, clocked_by epClock125, reset_by epReset125);
     if (valueOf(NumberOfMasters) > 0) begin
  
negative.code:    interface master = mvec[portPortal].master;
     interface slave = sEngine.slave;
     interface interruptRequest = mvec[portPortal].interruptRequest;
     interface pci = traceif.pci;
  endmodule: mkPcieHost
  
  
  