anchor.diff:  
   (* always_ready, always_enabled *)
   interface PParallellaLIB;
  -   interface Par_txo txo;
  -   interface Par_txi txi;
  -   interface Par_rxo rxo;
  -   interface Par_rxi rxi;
  +   interface Par_tx tx;
  +   interface Par_rx rx;
      interface ParMaxiGp maxi;   // this will connect to a master
      interface ParSaxiHp saxi;  // this will connect to a slave
      interface Par_misc misc;
   endinterface
   
  -import "BVI" parallella =
  -module mkPParallellaLIB#(Clock maxiclk, Clock saxiclk, 
  +import "BVI" elink =
  +module mkELink#(Clock maxiclk, Clock saxiclk, 
      Reset maxiclk_reset, Reset saxiclk_reset,
      Reset maxireset, Reset saxireset,
  -   Reset reset_chip, Reset reset_fpga)(PParallellaLIB);
  +   Reset reset_chip, Reset reset_fpga)(ELink);
      // default_clock clk();
      // default_reset rst();
      input_clock maxiclk(emaxi_aclk) = maxiclk;  // assigns the verilog emaxi_aclk
  
positive.code:       method reset_chip reset_chip();
        method reset_fpga reset_fpga();
        method csysreq(csysreq) enable((*inhigh*) EN_csysreq);
        method cclk_p(rxi_cclk_p) enable((*inhigh*) EN_rxi_cclk_p);
        method cclk_n(rxi_cclk_n) enable((*inhigh*) EN_rxi_cclk_n);
     endinterface
     
     interface Par_txo txo;
        method data_p(txo_data_p) enable((*inhigh*) EN_txo_data_p);
        method data_n(txo_data_n) enable((*inhigh*) EN_txo_data_n);
        method frame_p(txo_frame_p) enable((*inhigh*) EN_txo_frame_p);
        method frame_n(txo_frame_n) enable((*inhigh*) EN_txo_frame_n);
        method lclk_p(txo_lclk_p) enable((*inhigh*) EN_txo_lclk_p);
        method lclk_n(txo_lclk_n) enable((*inhigh*) EN_txo_lclk_n);
     endinterface
  
     interface Par_txi txi;
        method txo_wr_wait_p wr_wait_p();
        method txo_wr_wait_n wr_wait_n();
        method txo_rd_wait_p rd_wait_p();
        method txo_rd_wait_n rd_wait_n();
     endinterface
  
     interface Par_rxi rxi;
        method rxi_data_p data_p();
        method rxi_data_n data_n();
        method rxi_frame_p frame_p();
        method rxi_frame_n frame_n();
        method rxi_lclk_p lclk_p();
        method rxi_lclk_n lclk_n();
     endinterface
   
     interface Par_rxo rxo;
        method wr_wait_p(rxo_wr_wait_p) enable((*inhigh*) EN_rxo_wr_wait_p);
        method wr_wait_n(rxo_wr_wait_n) enable((*inhigh*) EN_rxo_wr_wait_n);
        method rd_wait_p(rxo_rd_wait_p) enable((*inhigh*) EN_rxo_rd_wait_p);
        method rd_wait_n(rxo_rd_wait_n) enable((*inhigh*) EN_rxo_rd_wait_n);
     endinterface
     
     interface ParSaxiHp saxi;
  
negative.code:    saxi.arvalid, maxi.rid, maxi.rdata, maxi.rresp, maxi.rlast,
     maxi.rvalid, saxi.rready, saxi.awqos, saxi.arqos
  ) CF (
     misc.csysack, misc.cactive, misc.reset_chip, misc.reset_fpga, tx.data_p, tx.data_n,
     tx.frame_p, tx.frame_n, tx.lclk_p, tx.lclk_n, rx.wr_wait_p,
     rx.wr_wait_n, rx.rd_wait_p, rx.rd_wait_n, misc.cclk_p,
     misc.cclk_n, maxi.awid, maxi.awaddr, maxi.awlen, maxi.awsize,
     maxi.awburst, maxi.awlock, maxi.awcache, maxi.awprot,
     maxi.awvalid, saxi.awready, maxi.wid, maxi.wdata, maxi.wstrb,
     maxi.wlast, maxi.wvalid, saxi.wready, maxi.bready, saxi.bid,
  