anchor.diff:     endrule
   `endif
   
  -`ifdef DEBUG_SETRAM
  -   rule readSetram;
  -      let v <- toGet(setRam.getRead).get;
  -      indication.read_setram_result(zeroExtend(v));
  -   endrule
  -`endif
  -
      //mkConnection(parser.phvOut, ingress_port_mapping.phvIn);
   
   `ifdef MTABLE
  
positive.code:       endmethod
  
        method Action readPacketBuffer(Bit#(16) addr);
           Bit#(ByteEnableSize) firstbe = 'hff;
           Bit#(ByteEnableSize) lastbe = 'hff;
           reqFifo.enq(MemRequest {sglId: 0, offset: 0, burstLen: 16, tag:0, firstbe: firstbe, lastbe: lastbe});
        endmethod
  
        method Action writePacketBuffer(Bit#(16) addr, Bit#(64) data);
           Bit#(ByteEnableSize) firstbe = 'hff;
           Bit#(ByteEnableSize) lastbe = 'hff;
           writeReqFifo.enq(MemRequest {sglId:0, offset:0, burstLen:16, tag:0, firstbe: firstbe, lastbe: lastbe});
  
           function Bit#(32) plusi(Integer i); return fromInteger(i); endfunction
           Vector#(WordsPerBeat, Bit#(32)) v = genWith(plusi);
           writeDataFifo.enq(MemData {data: pack(v), tag:0, last:True});
        endmethod
  
  
negative.code:       interface Put writeDone = toPut(writeDoneFifo);
     endinterface);
  
     SharedBuffer#(12, 128, 1) buff <- mkSharedBuffer(vec(dmaClient), vec(dmaWriteClient), memServerIndication, mmuIndication);
  
  `ifdef DEBUG_BCAM
     BinaryCam#(1024, 9) bcam <- mkBinaryCam_1024_9();
  