anchor.diff:     interface Vector#(4, Reset) deleteme_unused_reset;
   endinterface
   
  -typedef (function Module#(PortalTop#(32, 64, ipins, 0)) mkpt()) MkPortalTop#(type ipins);
  -//typedef (function Module#(PortalTop#(32, 64, ipins, nMasters)) mkpt()) MkPortalTop#(type ipins, numeric type nMasters);
  +typedef (function Module#(PortalTop#(32, 64, ipins, nMasters)) mkpt()) MkPortalTop#(type ipins, numeric type nMasters);
   
  -module [Module] mkZynqTopFromPortal#(MkPortalTop#(ipins) constructor)(ZynqTop#(ipins));
  +module [Module] mkZynqTopFromPortal#(MkPortalTop#(ipins,nMasters) constructor)(ZynqTop#(ipins))
  +   provisos(Add#(a__,nMasters,4));
  +
      PS7 ps7 <- mkPS7();
      Clock mainclock <- mkClockBUFG(clocked_by ps7.fclkclk[0]);
      Clock clock200 <- mkClockBUFG(clocked_by ps7.fclkclk[3]);
  
positive.code:    interface zynq = ps7.pins;
     interface leds = top.leds;
     interface XADC xadc;
        method Bit#(4) gpio;
           return 0;
        endmethod
     endinterface
  
     interface I2C_Pins i2c;
        interface Inout scl = tscl.io;
        interface Inout sda = tsda.io;
     endinterface
  
     interface pins = top.pins;
  
     // these are exported to make bsc happy, and then the ports are disconnected after synthesis
     interface deleteme_unused_clock = ps7.fclkclk;
     interface deleteme_unused_reset = ps7.fclkreset;
  endmodule
  
negative.code: import Leds              :: *;
  import Top               :: *;
  import AxiMasterSlave    :: *;
  import XilinxCells       :: *;
  import XbsvXilinxCells   :: *;
  import PS7LIB::*;
  