anchor.diff:  
   (* synthesize *)
   module mkProc(Proc#(DataSz));
  -    // Assumed Address Map
  -    // 0x0000_0000 - 0x0000_FFFF : Boot ROM
  -    // 0x0001_0000 - 0x3FFF_FFFF : Internal Devices
  -    // 0x4000_0000 - 0x0000_0000 : External Devices
  -    // 0x8000_0000 -       ?     : RAM
  +    // ROM Addresses
  +    // 0x0000_0000 - 0x3FFF_FFFF
  +    Addr romBaseAddr            = 'h0000_0000;
  +    Addr rstvec                 = 'h0000_1000;
  +    Addr nmivec                 = 'h0000_1004;
  +    Addr configStringPtr        = 'h0000_100C;
  +    Addr mtvecDefault           = 'h0000_1010;
  +    // Internal Memory-Mapped IO Addresses
  +    // 0x4000_0000 - 0x5FFF_FFFF
  +    Addr mmioBaseAddr           = 'h4000_0000;
  +    Addr rtcBaseAddr            = 'h4000_0000;
  +    Addr ipiBaseAddr            = 'h4000_1000;
  +    // External Memory-Mapped IO Addresses
  +    // 0x6000_0000 - 0x7FFF_FFFF
  +    Addr externalMMIOBaseAddr   = 'h6000_0000;
  +    // DRAM Addresses
  +    // 0x8000_0000 - end of address space
  +    Addr dramBaseAddr           = 'h8000_0000;
   
  +    // This function assumes romBaseAddr < mmioBaseAddr < dramBaseAddr
       function PMA getPMA(Addr addr);
  -        if (addr < 'h0001_0000) begin
  +        if (addr < mmioBaseAddr) begin
               return IORom;
  -        end else if (addr < 'h8000_0000) begin
  +        end else if (addr < dramBaseAddr) begin
               return IODevice;
           end else begin
               return MainMemory;
           end
       endfunction
   
  -    Addr rstvec          = 'h0000_1000;
  -    Addr nmivec          = 'h0000_1004;
  -    Addr configStringPtr = 'h0000_100C;
  -    Addr mtvecDefault    = 'h0000_1010;
  -    Addr mmioBaseAddr    = 'h4000_0000;
  -    Addr rtcBaseAddr     = 'h4000_0000;
  -    Addr ipiBaseAddr     = 'h4000_1000;
  -    // DRAM at 0x8000_0000 - ?
  -    Addr dramBaseAddr    = 'h8000_0000;
  +    Wire#(Bool) extInterruptWire <- mkDWire(False);
   
       SingleCoreMemorySystem#(DataSz) memorySystem <- mkBasicMemorySystem(getPMA);
       MemoryMappedCSRs#(1) mmcsrs <- mkMemoryMappedCSRs(mmioBaseAddr);
  
positive.code:                     mmcsrs.ipi[0], // inter-process interrupt
                      mmcsrs.timerInterrupt[0], // timer interrupt
                      mmcsrs.timerValue,
                      False, // external interrupt
                      0); // hart ID
  
      // +----------------+ +---------------+
  
negative.code: import Vector::*;
  
  import ClientServerUtil::*;
  import PrintTrace::*;
  import ServerUtil::*;
  
  import Abstraction::*;
  