anchor.diff:  
      let verboseProgress = False;
   
  -   rule startReqRule if (numReqs != 0);
  +   rule startReqRule if (numReqs != 0 && counter.read() <= unpack(extend(burstLenBytes) << 3));
  +      counter.increment(unpack(extend(burstLenBytes)));
         readReqFifo.enq(MemRequest { sglId: readPointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag) });
         writeReqFifo.enq(MemRequest { sglId: writePointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag) });
   
         numReqs <= numReqs - 1;
         reqOffset <= reqOffset + extend(burstLenBytes);
         tag <= tag + 1;
  -      //$display("start numReqs", numReqs);
  +      $display("start numReqs %d offset %d", numReqs, reqOffset);
      endrule
   
      rule finish;
         let donetag <- toGet(doneFifo).get();
  -      //$display("finished num todo=%d", numDone);
  +      $display("finished num todo=%d", numDone);
         if (numDone == 1) begin
            indication.copyDone(0);
         end
  
positive.code: 	 indication.copyProgress(extend(donetag));
     endrule
  
     MemReadClient#(64) readClient = (interface MemReadClient;
        interface Get readReq = toGet(readReqFifo);
        interface Put readData = toPut(dataFifo);
     endinterface );
     MemWriteClient#(64) writeClient = (interface MemWriteClient;
        interface Get writeReq = toGet(writeReqFifo);
        interface Get writeData = toGet(dataFifo);
        interface Put writeDone = toPut(doneFifo);
  
negative.code:    Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);
     Reg#(Bit#(32))              srcGens <- mkReg(0);
  
     ConfigCounter#(16) counter          <- mkConfigCounter(0);
     FIFO#(MemRequest) readReqFifo <- mkFIFO();
     FIFO#(MemRequest) writeReqFifo <- mkFIFO();
     FIFO#(MemData#(DataBusWidth))   dataFifo <- mkSizedBRAMFIFO(1024);
  