anchor.diff:     Reg#(Bit#(32)) copyTag <- mkReg(0);
      Reg#(Bool) copyBusy <- mkReg(False);
       
  -   Stmt CopyStart = while(True)
  +   Stmt copyStart = while(True)
      seq
         while (copyBusy) noAction;
         copyTag <= f_in.deq[31:0];
  
positive.code: 
  // The interface to the copyengine is a pair of fifos which supply and accept
  // blocks of 8 64 bit words
  
  module mkCopyEngine#(ReadChan#(Bit#(64)) copy_read_chan, WriteChan#(Bit#(64)) copy_write_chan) ( Server#(Bit#(64), Bit#(64)));
     FIFO#(CommandStruct) f_in  <- mkFIFO;    // to buffer incoming requests
     FIFO#(Bit#(32)) f_out <- mkFIFO;    // to buffer outgoing responses
     Reg#(Bit#(16)) copyReadCount <- mkReg(0);
     Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
     Reg#(Bit#(40)) copyReadAddr <- mkReg(0);
  
negative.code:       for (ii <= 0; ii < 7; ii += 1)
  	 f_out.enq(0);
        f_out.enq(extend(copyTag));
        copyBusy <= False;
     endseq
        
     FSM start();
     mkAutoFSM#(copyStart)(start);
     FSM finish();
     mkAutoFSM#(copyFinish)(finish);
     
     interface Put request = toPut(f_in);
     interface Get response = toGet (f_out);
  