anchor.diff:  	 779: return tlpDataBramResponseSlice(3);
   	 780: return tlpDataBramResponseSlice(4);
   	 781: return tlpDataBramResponseSlice(5);
  -	 782: return axiTestEnabledReg;
  -	 783: return addrLowerWordReg;
  -	 784: return addrUpperWordReg;
  -	 785: return testResultReg;
  -	 786: return testStateReg;
  +	 782: return 0;
  +	 783: return 0;
  +	 784: return 0;
  +	 785: return 0;
  +	 786: return 0;
   	 787: return pipeliningEnabledReg ? 1 : 0;
   	 788: return axiEnabledReg ? 1 : 0;
   	 789: return tlpDataBramRdAddrReg;
  
positive.code:    interface Reg pipeliningEnabled = pipeliningEnabledReg;
     interface Reg byteSwap = byteSwapReg;
     interface Reg use4dw = use4dwReg;
     interface Reg axiTestEnabled = axiTestEnabledReg;
     interface Reg numPortals = numPortalsReg;
     interface Reg addrLowerWord = addrLowerWordReg;
     interface Reg addrUpperWord = addrUpperWordReg;
     interface Reg testResult = testResultReg;
     interface Reg testState = testStateReg;
     interface Reg tlpDataBramWrAddr = tlpDataBramWrAddrReg;
     interface Reg tlpSeqno = tlpSeqnoReg;
     interface Reg tlpOutCount = tlpOutCountReg;
  
negative.code: 	    779: tlpDataScratchpad[3] <= dword;
  	    780: tlpDataScratchpad[4] <= dword;
  	    781: tlpDataScratchpad[5] <= dword;
  
  	    787: pipeliningEnabledReg <= (dword != 0) ? True : False;
  	    788: axiEnabledReg <= (dword != 0) ? True : False;
  