anchor.diff:          if (!testPatternEnabled)
           begin
               let pixel = stageData.pixel;
  -            let pixelSelect = 0; //stageData.dataCount[0];
  -            if (pixelSelect == 0)
  +            //let pixelSelect = 0; //stageData.dataCount[0];
  +            //if (pixelSelect == 0)
                   pixel = unpack(d[23:0]);
  -            else
  -                pixel = unpack(d[55:32]);
  +            //else
  +                //pixel = unpack(d[55:32]);
               stageData.pixel = pixel;
           end
           rgb888StageReg <= stageData;
  
positive.code:         else if (dataEnable)
              dataCount <= dataCount + 1;
  
          bramOutStageFifo.enq(Rgb888Stage { vsync: vsync, hsync: hsync, de: dataEnable, dataCount: dataCount });
          lineBuffer.readAddr(dataCount);
  
      endrule
  
      rule bramOutStage;
          let d <- lineBuffer.readData;
  
negative.code:     method Action setNumberOfPixels(Bit#(12) pixels);
          numberOfPixels <= pixels;
      endmethod
  endmodule
  
  module mkHdmiOut(HdmiOut);
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
      Reg#(Rgb888Stage) rgb888StageReg <- mkReg(unpack(0));
      Reg#(Yuv444IntermediatesStage) yuv444IntermediatesStageReg <- mkReg(
          Yuv444IntermediatesStage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
      Reg#(Yuv444Stage) yuv444StageReg <- mkReg(
          Yuv444Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
      Reg#(Yuv422Stage) yuv422StageReg <- mkReg(
          Yuv422Stage { vsync: 0, hsync: 0, de: False, data: unpack(0) });
      Reg#(Bool) evenOddPixelReg <- mkReg(False);
  
      rule yuv444IntermediatesStage;
          let previous = rgb888StageReg;
          let pixel = previous.pixel;
          yuv444IntermediatesStageReg <= Yuv444IntermediatesStage {
              vsync: previous.vsync,
  