anchor.diff:     let wdataCnx  <- mkConnection(toGet(wdataFifo), axiRootPortMemSlave.write_server.writeData);
      let doneCnx   <- mkConnection(axiRootPortMemSlave.write_server.writeDone, toPut(doneFifo));
   
  -   rule rl_rdata;
  +   rule rl_rdata if (!inSetup);
         let rdata <- toGet(rdataFifo).get();
         if (rdata.tag == 0)
   	 driverInd.readDone(truncate(rdata.data));
      endrule
   
  -   rule rl_writeDone;
  +   rule rl_writeDone if (!inSetup);
         let tag <- toGet(doneFifo).get();
         if (tag == 0)
   	 driverInd.writeDone();
  
positive.code:    MemServerGearbox#(PcieDataBusWidth,DataBusWidth) axiGearbox <- mk1toNMemServerGearbox();
     let gearboxCnx <- mkConnection(splitter.busClient, axiGearbox.server);
  
     let requestSize = 64;
     let responseSize = 16;
     let bytesPerEntry = valueOf(TDiv#(PcieDataBusWidth,8));
     let wordsPerEntry = valueOf(TDiv#(PcieDataBusWidth,32));
  
     BRAM_Configure bramConfig = defaultValue;
     bramConfig.latency = 2;
     bramConfig.memorySize = 4096*4/bytesPerEntry; // 4 pages
     BRAM2Port#(Bit#(32),Bit#(PcieDataBusWidth)) bram <- mkBRAM2Server(bramConfig);
  
     let arbIfc <- mkFixedPriority();
     Arbiter#(3, BRAMRequest#(Bit#(32),Bit#(PcieDataBusWidth)),Bit#(PcieDataBusWidth)) arbiter <- mkArbiter(arbIfc,2);
     let arbCnx <- mkConnection(arbiter.master, bram.portB);
  
     MemServer#(PcieDataBusWidth)            bramMemA <- mkMemServerFromBram(bram.portA);
     PhysMemSlave#(32,PcieDataBusWidth)      bramMemB <- mkPhysMemSlaveFromBram(arbiter.users[0]);
     MemServerPortal          bramMemServerPortal <- mkPhysMemSlavePortal(bramMemB,bramIndication);
  
     let portB1 = arbiter.users[1];
     let portB2 = arbiter.users[2];
     Reg#(Bit#(16)) requestId <- mkReg(0);
     Reg#(Bit#(16)) responseId <- mkReg(0);
     Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);
  
negative.code:    let axiCtlReset = reset;
  `endif
  
     Reg#(Bool) inSetup <- mkReg(False);
  
  `ifndef PCIE3
     let axiRootPort <- mkAPRP(pcie_clk_100mhz_buf, reset, axiClock, axiReset, axiCtlClock, axiCtlReset);
  `else
  