anchor.diff:          pll_t.d1(imageon_oe);
           pll_t.d2(imageon_oe);
           pll_t.ce(True);
  -    endrule
  -
  -    rule trigger_rule;
  -        trigger_wire <= pack(tstate != TSend);
  -    endrule
  -
  -    rule vr_rule;
  -        vita_reset_n_o <= ~serdes_reset_reg;
       endrule
   
       rule sendup_imageon_clock;
  
positive.code:         ibufds_v[i] <- mkIBUFDS(vita_data_p[i], vita_data_n[i]);
      Vector#(5, IserdesDatadeser) serdes_v <- replicateM(mkIserdesDatadeser(serdes_clock, serdest_clk.gen_clk));
  
      Reg#(Bit#(1)) vita_reset_n_o <- mkReg(0);
      Wire#(Bit#(1)) zero_wire <- mkDWire(0);
      Wire#(Bit#(1)) one_wire <- mkDWire(1);
      Wire#(Bit#(1)) trigger_wire <- mkDWire(0);
      Vector#(3, ReadOnly#(Bit#(1))) vita_trigger_wire;
      vita_trigger_wire[2] <- mkOBUFT(zero_wire, imageon_oe);
      vita_trigger_wire[1] <- mkOBUFT(one_wire, imageon_oe);
      vita_trigger_wire[0] <- mkOBUFT(trigger_wire, imageon_oe);
      ReadOnly#(Bit#(1)) vita_reset_n_wire <- mkOBUFT(vita_reset_n_o, imageon_oe);
  
      Reg#(Bit#(1)) serdes_align_busy_temp <- mkReg(0);
      Reg#(Bit#(1)) serdes_align_busy_reg <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);
  
negative.code:     ReadOnly#(Bit#(1)) serdes_fifo_enable_null <- mkNullCrossingWire(serdes_clock, serdes_fifo_enable_reg);
      Reg#(Bit#(10)) serdes_manual_tap_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);
      Reg#(Bit#(10)) serdes_training_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);
      Reg#(Bit#(1)) serdes_reset_reg <- mkSyncReg(1, axi_clock, axi_reset, defaultClock);
      ReadOnly#(Bit#(1)) serdes_reset_null <- mkNullCrossingWire(serdes_clock, serdes_reset_reg);
      Reg#(Bit#(16)) syncgen_delay_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);
      Reg#(Bit#(32)) trigger_default_freq_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);
  