anchor.diff:  endinterface
   
   typedef struct {
  -   Bit#(22)      user;
  -   Bit#(1)       last;
  -   Bit#(8)       keep;
  -   Bit#(64)      data;
  -} AxiRx deriving (Bits, Eq);
  -
  -typedef struct {
  -   Bit#(1)       last;
  -   Bit#(8)       keep;
  -   Bit#(64)      data;
  -} AxiTx deriving (Bits, Eq);
  +   Bit#(85)      user;
  +   Bit#(1)       last;
  +   Bit#(8)       keep;
  +   Bit#(256)     data;
  +} AxiCQ deriving (Bits, Eq);
  +
  +typedef struct {
  +   Bit#(75)      user;
  +   Bit#(1)       last;
  +   Bit#(8)       keep;
  +   Bit#(256)     data;
  +} AxiRC deriving (Bits, Eq);
  +
  +typedef struct {
  +   Bit#(1)       last;
  +   Bit#(8)       keep;
  +   Bit#(256)     data;
  +   Bit#(33)      user;
  +   Bit#(1)       valid;
  +} AxiCC deriving (Bits, Eq);
  +
  +typedef struct {
  +   Bit#(60)      user;
  +   Bit#(1)       last;
  +   Bit#(8)       keep;
  +   Bit#(256)     data;
  +   Bit#(1)       valid;
  +} AxiRQ deriving (Bits, Eq);
   
   `ifdef BOARD_vc709
   typedef 8 PcieLanes;
  
positive.code: import PcieGearbox       :: *;
  
  interface PcieEndpointX7#(numeric type lanes);
     //interface PciewrapCfg#(lanes)               cfg;
     interface PciewrapPci_exp#(lanes)           pcie;
     interface PciewrapUser#(lanes)              user;
     interface PciewrapPipe#(lanes)              pipe;
  
negative.code:    PCIEParams params = defaultValue;
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
     Reset defaultResetInverted <- mkResetInverter(defaultReset, clocked_by defaultClock);
  
     PcieWrap#(PcieLanes) pcie_ep <- mkPcieWrap(defaultClock, defaultResetInverted);
  
     FIFOF#(AxiRC) fAxiRC <- mkBypassFIFOF(clocked_by pcie_ep.user_clk, reset_by noReset);
     FIFOF#(AxiCQ) fAxiCQ <- mkBypassFIFOF(clocked_by pcie_ep.user_clk, reset_by noReset);
     FIFOF#(AxiRQ) fAxiRQ <- mkBypassFIFOF(clocked_by pcie_ep.user_clk, reset_by noReset);
     FIFOF#(AxiCC) fAxiCC <- mkBypassFIFOF(clocked_by pcie_ep.user_clk, reset_by noReset);
     (* fire_when_enabled, no_implicit_conditions *)
     rule every1;
        Maybe#(Bit#(22)) rc_tready = Invalid;
        Maybe#(Bit#(22)) cq_tready = Invalid;
        if (fAxiRC.notFull) rc_tready = tagged Valid 22'h3FFFFF;
        if (fAxiCQ.notFull) cq_tready = tagged Valid 22'h3FFFFF;
        pcie_ep.m_axis_rc.tready(fromMaybe(0, rc_tready));
        pcie_ep.m_axis_cq.tready(fromMaybe(0, cq_tready));
     endrule
  
     // Drive s_axis_rq
     let rq_txready = (pcie_ep.s_axis_rq.tready != 0 && fAxiRQ.notEmpty);
  
     //(* fire_when_enabled, no_implicit_conditions *)
     rule drive_axi_rq if (rq_txready);
        let info = fAxiRQ.first; fAxiRQ.deq;
        pcie_ep.s_axis_rq.tvalid(1);
        pcie_ep.s_axis_rq.tlast(info.last);
        pcie_ep.s_axis_rq.tdata(info.data);
        pcie_ep.s_axis_rq.tkeep(info.keep);
        pcie_ep.s_axis_rq.tuser(info.user);
     endrule
  
     (* fire_when_enabled, no_implicit_conditions *)
     rule drive_axi_rq2 if (!rq_txready);
        pcie_ep.s_axis_rq.tvalid(0);
        pcie_ep.s_axis_rq.tlast(0);
        pcie_ep.s_axis_rq.tdata(0);
        pcie_ep.s_axis_rq.tkeep(0);
        pcie_ep.s_axis_rq.tuser(0);
     endrule
  
     // Drive s_axis_cc
     let cc_txready = (pcie_ep.s_axis_cc.tready != 0 && fAxiCC.notEmpty);
  
     //(* fire_when_enabled, no_implicit_conditions *)
     rule drive_axi_cc if (cc_txready);
        let info = fAxiCC.first; fAxiCC.deq;
        pcie_ep.s_axis_cc.tvalid(1);
        pcie_ep.s_axis_cc.tlast(info.last);
        pcie_ep.s_axis_cc.tdata(info.data);
        pcie_ep.s_axis_cc.tkeep(info.keep);
        pcie_ep.s_axis_cc.tuser(info.user);
     endrule
  
     (* fire_when_enabled, no_implicit_conditions *)
     rule drive_axi_cc2 if (!cc_txready);
        pcie_ep.s_axis_cc.tvalid(0);
        pcie_ep.s_axis_cc.tlast(0);
        pcie_ep.s_axis_cc.tdata(0);
        pcie_ep.s_axis_cc.tkeep(0);
        pcie_ep.s_axis_cc.tuser(0);
     endrule
  
     // Drive m_axis_rc
     (* fire_when_enabled *)
     rule sink_axi_rc if (pcie_ep.m_axis_rc.tvalid != 0);
        fAxiRC.enq(AxiRC {user: pcie_ep.m_axis_rc.tuser,
                          last: pcie_ep.m_axis_rc.tlast,
                          keep: pcie_ep.m_axis_rc.tkeep,
                          data: pcie_ep.m_axis_rc.tdata });
     endrule
  
     // Drive m_axis_cq
     (* fire_when_enabled *)
     rule sink_axi_cq if (pcie_ep.m_axis_cq.tvalid != 0);
        fAxiCQ.enq(AxiCQ {user: pcie_ep.m_axis_cq.tuser,
                          last: pcie_ep.m_axis_cq.tlast,
                          keep: pcie_ep.m_axis_cq.tkeep,
                          data: pcie_ep.m_axis_cq.tdata });
     endrule
  
     // The PCIe endpoint exports full (250MHz) and half-speed (125MHz) clocks
     Clock clock250 = pcie_ep.user_clk;
  