anchor.diff:     rule incTimestamp;
          timestamp <= timestamp + 1;
      endrule
  -   rule endTrace if (csr.tlpTracing && csr.tlpDataBramWrAddr > 2047);
  -       csr.tlpTracing <= False;
  -   endrule
  +//   rule endTrace if (csr.tlpTracing && csr.tlpTraceLimit != 0 && csr.tlpDataBramWrAddr > truncate(csr.tlpTraceLimit));
  +//       csr.tlpTracing <= False;
  +//   endrule
   
      // connect the sub-components to each other
   
  
positive.code: 	    781: tlpDataScratchpad[5] <= dword;
  
  	    792: tlpDataBramWrAddrReg <= dword;
  
              //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
              // MSIx table entries
  
negative.code:    interface ReadOnly#(Bit#(64)) interruptAddr;
     interface ReadOnly#(Bit#(32)) interruptData;
  
     interface Reg#(Bool)     tlpTracing;
     interface Reg#(Bit#(32)) tlpTraceLimit;
     interface Reg#(Bool) use4dw;
     interface Reg#(Bit#(32)) tlpDataBramWrAddr;
     interface Reg#(Bit#(32)) tlpOutCount;
  