anchor.diff:        let __x <- sglId_gen.complete;
      endrule
      
  +   // for simulators
  +   let pareff <- mkPareff();
  +
      // stage 0 (latency == 1)
      Vector#(2, FIFO#(ReqTup)) incomingReqs <- replicateM(mkFIFO);
   
  
positive.code:    } DmaError deriving (Bits);
  
  // the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined
  module mkMMU#(Integer iid, Bool bsimMMap, MMUIndication mmuIndication)(MMU#(addrWidth))
     provisos(Log#(MaxNumSGLists, listIdxSize),
  	    Add#(listIdxSize,8, entryIdxSize),
  	    Add#(a__,addrWidth,MemOffsetSize));
  
negative.code:       let nextId <- sglId_gen.getTag;
        let resp = (fromInteger(iid) << 16) | extend(nextId);
        if (verbose) $display("mkMMU::idRequest %d", fd);
        let va <- pareff.initfd(resp, fd);
        mmuIndication.idResponse(resp);
     endmethod
     method Action idReturn(Bit#(32) sglId);
  