anchor.diff:     interface MemWriteEngineServer#(userWidth) writeServer;
   endinterface
   
  -module mkMemWriteChannel#(Integer bufferSizeBytes, Integer channelNumber)(MemWriteChannel#(busWidth, userWidth, cmdQDepth))
  +module mkMemWriteChannel#(Integer bufferSizeBytes, Integer channelNumber,
  +			  PipeOut#(Bit#(MemTagSize)) writeGntPipe, PipeOut#(Bit#(MemTagSize)) writeDonePipe)
  +   (MemWriteChannel#(busWidth, userWidth, cmdQDepth))
      provisos ( Div#(busWidth,8,busWidthBytes)
   	     ,Log#(busWidthBytes,beatShift)
   	     ,Add#(1, d__, userWidth)
  
positive.code: 
     rule rlWriteData;
        match {.rc, .client_tag, .last} = inProgress.first;
        let gnt = writeGntFifo.first;
        let new_respCnt = respCnt+1;
        let lastBeat = False;
        if (new_respCnt == rc) begin
  	 respCnt <= 0;
  	 inProgress.deq();
  	 writeGntFifo.deq();
  	 serverDone.enq(tuple3(0,client_tag,last));
  	 lastBeat = True;
        end
  
negative.code:    Reg#(Bool)         reqInFlight <- mkReg(False);
     FIFOF#(MemRequest)          writeReqFifo <- mkFIFOF();
     FIFOF#(MemData#(userWidth)) writeDataFifo <- mkFIFOF();
     FunnelPipe#(1,numServers,MemRequest,2) reqFunnel <- mkFunnelPipesPipelined(genWith(writeChannelDmaWriteReq));
     FunnelPipe#(1,numServers,MemData#(userWidth),2) dataFunnel <- mkFunnelPipesPipelined(genWith(writeChannelDmaWriteData));
  
     rule rl_arbitration if (!reqInFlight);
        let req <- toGet(reqFunnel[0]).get();
  