anchor.diff:  // SOFTWARE.
   
   import Vector            :: *;
  -import Clocks          :: *;
  +import Clocks            :: *;
   import GetPut            :: *;
   import FIFO              :: *;
  -import FIFOF        :: *;
   import Connectable       :: *;
   import ClientServer      :: *;
   import Xilinx            :: *;
  -import DefaultValue    :: *;
  +import DefaultValue      :: *;
   import PcieSplitter      :: *;
   import PcieTracer        :: *;
  -import PcieGearbox    :: *;
  +import PcieGearbox       :: *;
   import XbsvXilinx7Pcie   :: *;
   import PCIEWRAPPER       :: *;
   import Portal            :: *;
  
positive.code:    interface ipins       pins;
  endinterface
  
  module [Module] mkPcieHost #(Clock epClock250, Reset epReset250, PciId my_pciId, MkPortalTop#(dsz, ipins, nMasters) mkPortalTop,
  Server#(TLPData#(8), TLPData#(8)) ep_tlp)(PcieHost#(ipins))
  provisos(
     Mul#(TDiv#(dsz, 8), 8, dsz),
  
negative.code:    mkConnection(splitter.servers[portPortal], portalEngine.tlp);
     mkConnection(portalEngine.master, portalTop.slave);
  
     if (`NumberOfMasters > 0) begin
        AxiSlaveEngine#(dsz) dmaEngine <- mkAxiSlaveEngine(my_pciId);
        Vector#(`NumberOfMasters,Axi3Master#(40,dsz,6)) m_axis;   
        m_axis[0] <- mkAxiDmaMaster(portalTop.masters[0], reset_by portalResetIfc.new_rst);
        mkConnection(splitter.servers[portAxi], dmaEngine.tlp);
        mkConnection(m_axis[0], dmaEngine.slave);
  