anchor.diff:     Reg#(Bit#(32)) tlpDataBramRdAddrReg <- mkReg(0);
      Reg#(Bit#(32)) tlpDataBramWrAddrReg <- mkReg(0);
      BRAM_Configure bramCfg = defaultValue;
  -   bramCfg.memorySize = 1024;
  -   BRAM1Port#(Bit#(10), TimestampedTlpData) tlpDataBram1Port <- mkBRAM1Server(bramCfg);
  +   bramCfg.memorySize = 2048;
  +   BRAM1Port#(Bit#(11), TimestampedTlpData) tlpDataBram1Port <- mkBRAM1Server(bramCfg);
      Reg#(TimestampedTlpData) tlpDataBramResponse <- mkReg(unpack(0));
      Vector#(6, Reg#(Bit#(32))) tlpDataScratchpad <- replicateM(mkReg(0));
      Reg#(Bit#(32)) tlpOutCountReg <- mkReg(0);
  
positive.code:    interface Reg#(Bit#(32)) tlpDataBramWrAddr;
     interface Reg#(Bit#(32)) tlpSeqno;
     interface Reg#(Bit#(32)) tlpOutCount;
     interface BRAMServer#(Bit#(10), TimestampedTlpData) tlpDataBram;
  endinterface: ControlAndStatusRegs
  
  // This module encapsulates all of the logic for instantiating and
  
negative.code:                                                  , max_payload_bytes
                                                   );
  
     rule endTrace if (csr.tlpTracing && csr.tlpDataBramWrAddr > 2047);
         csr.tlpTracing <= False;
     endrule
     rule connectEnables;
  