anchor.diff:        let tag = compReg1;
         let cli = compReg2;
         compFifo0.enq(cli);
  -      read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}});
  +      read_buffer.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, responseOnWrite: ?, datain: ?});
         compReg0 <= cnt-1;
      endrule
      
  
positive.code:       interface Put readData;
  	 method Action put(MemData#(dataWidth) response);
  	    readDataPipelineFifo.enq(response);
  	    dreqFifos.portA.request.put(BRAMRequest{write:False, address:truncate(response.tag)});
  	    beatCount <= beatCount+1;
  	 endmethod
        endinterface
  
negative.code:    // consider access to portA and portB to be conflict free **sigh** 
     rule ret;
        let tag <- toGet(retFifo).get;
        tags.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:tag, datain:False});
        comp_state <= 1 | (comp_state << 1);
     endrule
  
     rule init(!inited);
        tags.portA.request.put(BRAMRequest{write:True,address:head_ptr,responseOnWrite:False,datain:False});
        head_ptr <= head_ptr+1;
        inited <= head_ptr+1==0;
     endrule
     
     method ActionValue#(Bit#(tsz)) getTag() if (inited && (head_ptr+1 != tail_ptr));
        tags.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, address:head_ptr, datain:True});
        head_ptr <= head_ptr+1;
        return head_ptr;
     endmethod
  