anchor.diff:     endrule
   
      rule driveInputs;
  -      opmodeReg <= opmodeWire;
  +      opmode1Reg <= opmodeWire;
  +      opmode2Reg <= opmode1Reg;
  +      opmode3Reg <= opmode2Reg;
  +      opmode4Reg <= opmode3Reg;
  +
         alumodeReg <= alumodeWire;
   
         c1Reg <= cWire;
         c2Reg <= c1Reg;
         c3Reg <= c2Reg;
   
  +      //if (lastWire == 1 || last1Reg == 1 || last2Reg == 1 || last3Reg == 1 || last4Reg == 1 || last5Reg == 1)
  +	 $display("%d: a=%h b=%h c=%h p=%h", cycles, aWire, bWire, c3Reg, dsp.p());
  +
         dsp.alumode(alumodeReg);
         dsp.carryinsel(carryinselWire);
         dsp.inmode(inmodeWire);
  -      dsp.opmode(opmodeReg);
  -      //dsp.a(aWire);
  -      //dsp.b(bWire);
  -      dsp.c(c3Reg);
  +      dsp.opmode(opmode1Reg);
  +      dsp.a(aWire);
  +      dsp.b(bWire);
  +      dsp.c(c1Reg);
         //dsp.d(dWire);
   
         dsp.acin(0);
  
positive.code:    endmethod
     method Action a(Bit#(30) v);
        ce1Wire <= 1;
        dsp.a(v);
     endmethod
     method Action b(Bit#(18) v);
        dsp.b(v);
     endmethod
     method Action c(Bit#(48) v);
        cWire <= v;
  
negative.code:    Wire#(Bit#(1)) ce1Wire <- mkDWire(0);
     Reg#(Bit#(1)) ce2Reg <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1)) cepReg <- mkReg(0, reset_by optionalReset);
     Wire#(Bit#(1)) lastWire <- mkDWire(0);
     Reg#(Bit#(1))  last1Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last2Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last3Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last4Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last5Reg  <- mkReg(0, reset_by optionalReset);
  
     Reg#(Bit#(32)) cycles <- mkReg(0);
     rule cyclesRule;
        cycles <= cycles+1;
     endrule
  
     rule clock_enable_and_reset;
        ce2Reg <= ce1Wire;
        cepReg <= ce2Reg;
  
        last1Reg <= lastWire;
        last2Reg <= last1Reg;
        last3Reg <= last2Reg;
        last4Reg <= last3Reg;
        last5Reg <= last4Reg;
  
        dsp.cea1(1); // (ce1Wire);
        dsp.cea2(1); // (ce2Reg);
  