anchor.diff:     interface PcieS5Txout tx;
   endinterface
   
  -`ifdef PCIES5_SIM
   interface PcieS5HipPipe;
   (* prefix="", result="rxdata" *)     method Action     rxdata    (Vector#(8, Bit#(8)) rxdata);
  -(* prefix="", result="rxdatak" *)    method Action     rxdatak   (Vector#(9, Bit#(1)) rxdatak);
  +(* prefix="", result="rxdatak" *)    method Action     rxdatak   (Vector#(8, Bit#(1)) rxdatak);
   (* prefix="", result="rxelecidle" *) method Action     rxelecidle(Vector#(8, Bit#(1)) rxelecidle);
   (* prefix="", result="rxstatus" *)   method Action     rxstatus  (Vector#(8, Bit#(3)) rxstatus);
   (* prefix="", result="rxvalid" *)    method Action     rxvalid   (Vector#(8, Bit#(1)) rxvalid);
  
positive.code:       method sim_ltssmstate(); return pcie.sim.ltssmstate; endmethod
        method sim_pipe_rate(); return pcie.sim.pipe_rate; endmethod
     endinterface
  `endif
  
     interface PcieS5HipCtrl hip_ctrl;
        method test_in = pcie.test.in;
  
negative.code:    interface PcieS5Rxin rx;
     interface PcieS5Txout tx;
     interface PcieS5HipStatus hip_status;
     interface PcieS5HipPipe hip_pipe;
     interface PcieS5HipCtrl hip_ctrl;
     interface Clock coreclkout_hip;
  endinterface
  