anchor.diff:        pcie_ep.cfg.dsn(64'hf001ba7700000000);
         pcie_ep.cfg.ds_bus_number(0);
         pcie_ep.cfg.ds_device_number(0);
  +      pcie_ep.cfg.ds_function_number(0);
         pcie_ep.cfg.ds_port_number(0);
         pcie_ep.cfg.err_cor_in(0);
         pcie_ep.cfg.err_uncor_in(0);
  
positive.code: 
     FIFO#(Bool) intrMutex <- mkFIFO1(clocked_by pcie_ep.user_clk, reset_by user_reset_n);
     Wire#(Bool) msix_int_enable <- mkDWire(False, clocked_by pcie_ep.user_clk, reset_by user_reset_n);
  
     rule rl_intr;
        if (pcie_ep.cfg.interrupt_msix_enable[0] == 1) begin
  	 match { .addr, .data } <- toGet(intrFifo).get();
  	 pcie_ep.cfg.interrupt_msix_address(addr);
  	 pcie_ep.cfg.interrupt_msix_data(data);
  	 msix_int_enable <= True;
  	 intrMutex.enq(True);
        end
     endrule: rl_intr
     rule rl_intr_enable;
        pcie_ep.cfg.interrupt_msix_int(pack(msix_int_enable));
     endrule
  
     rule rl_intr_sent if (pcie_ep.cfg.interrupt_msix_sent() == 1|| pcie_ep.cfg.interrupt_msix_fail() == 1);
        intrMutex.deq();
  
negative.code:    // Drive s_axis_rq
     let rq_txready = (pcie_ep.s_axis_rq.tready != 0 && fAxiRq.notEmpty);
  
     Wire#(Maybe#(AxiStRq)) fAxiRqWire <- mkDWire(tagged Invalid, clocked_by pcie_ep.user_clk, reset_by user_reset_n);
  
     rule rl_axi_rq;
        if (rq_txready) begin
  	 let info = fAxiRq.first; fAxiRq.deq;
  	 fAxiRqWire <= tagged Valid info;
        end
     endrule
  
     (* fire_when_enabled, no_implicit_conditions *)
     rule drive_axi_rq;
        Bit#(1) tvalid = 0;
        Bit#(1) tlast = 0;
        Bit#(256) tdata = 0;
        Bit#(8) tkeep = 0;
        Bit#(60) tuser = 0;
        if (fAxiRqWire matches tagged Valid .x) begin
  	     tvalid = 1;
  	     tlast = pack(x.last);
  	     tdata = x.data;
  	     tkeep = x.keep;
  	     tuser = {0, x.last_be, x.first_be};
        end
        pcie_ep.s_axis_rq.tvalid(tvalid);
        pcie_ep.s_axis_rq.tlast(tlast);
        pcie_ep.s_axis_rq.tdata(tdata);
  