anchor.diff:  	     Mul#(h__, nMasters, TMax#(nMasters, numReadClientsActual)),
   	     Mul#(i__, nMasters, TMax#(nMasters, numWriteClientsActual)),
   	     Add#(e__, TLog#(b__), 6),
  -	     Add#(f__, TLog#(a__), 6)
  +	     Add#(f__, TLog#(a__), 6),
  +	     Mul#(g__, nMasters, TMax#(nMasters, TMax#(nMasters, numWriteClientsActual))),
  +	     Add#(j__, TLog#(i__), 6),
  +	     Mul#(k__, nMasters, TMax#(nMasters, TMax#(nMasters, numReadClientsActual))),
  +	     Add#(l__, TLog#(h__), 6),
  +	     Mul#(m__, nMasters, TMax#(nMasters, nMasters))
         );
   
      Vector#(numReadClientsNull, MemReadClient#(dataWidth)) nullReadClients = replicate(null_mem_read_client());
  
positive.code: 			  Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  			  MemServerIndication indication,
  			  MMUIndication mmuIndication)(SimpleMemServer#(PhysAddrWidth, dataWidth,nMasters))
     provisos (Mul#(a__, nMasters, TMax#(nMasters, numReadClients)),
  	     Mul#(b__, nMasters, TMax#(nMasters, numWriteClients)),
  	     Add#(1, c__, dataWidth),
  	     Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
  	     Add#(TLog#(TDiv#(dataWidth, 8)), d__, BurstLenSize),
  	     Mul#(e__, nMasters, TMax#(nMasters, TMax#(nMasters, numReadClients))),
  	     Mul#(f__, nMasters, TMax#(nMasters, TMax#(nMasters, numWriteClients))),
  	     Add#(g__, TLog#(b__), 6),
  	     Add#(h__, TLog#(a__), 6)
  	     );
  
     MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, mmuIndication);
  
     MemServer#(PhysAddrWidth,dataWidth,nMasters) dma <- mkMemServerRW(indication, readClients, writeClients, cons(hostMMU,nil));
  
     interface MemServerRequest memServerRequest = dma.request;
     interface MMURequest mmuRequest = hostMMU.request;
  
negative.code:    Bit#(32) pref;
     } DmaError deriving (Bits);
  
  module mkMemServer#(Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
  		    Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  		    Vector#(numMMUs,MMU#(PhysAddrWidth)) mmus,
  		    MemServerIndication indication)
     (MemServer#(PhysAddrWidth, dataWidth, nMasters))
     
     provisos (Max#(nMasters,numReadClients,numReadClientsActual),
  