anchor.diff:        phy10g.tx.parallel_data0(pack(tx_data0));
      endrule
   
  -`ifndef NUMBER_OF_10G_PORTS
  +`ifndef NUMBER_OF_ALTERA_PORTS
      Wire#(Bit#(66)) tx_data1 <- mkDWire(0, clocked_by clk_156_25, reset_by noReset);
      rule getTxFifo1;
         let v <- toGet(txFifo[1]).get;
  
positive.code:    rule tx_serial0;
        tx_serial[0] <= phy10g.tx.serial_data0;
     endrule
  `ifndef NUMBER_OF_10G_PORTS
     rule tx_serial1;
        tx_serial[1] <= phy10g.tx.serial_data1;
     endrule
  
negative.code:    rule rx_serial0;
        phy10g.rx.serial_data0(rx_serial_wire[0]);
     endrule
  `ifndef NUMBER_OF_ALTERA_PORTS
     rule rx_serial1;
        phy10g.rx.serial_data1(rx_serial_wire[1]);
     endrule
  