anchor.diff:  import SimDma::*;
   import IfcNames::*;
   import BuildVector::*;
  +import AxiBits::*;
  +import FIFOF::*;
  +import CFFIFO::*;
   
   `include "ConnectalProjectConfig.bsv"
   
  
positive.code:    interface PinType pins;
     interface AwsF1ShCl sh_cl;
     interface AwsF1ClSh cl_sh;
  endinterface
  
  (* no_default_clock, no_default_reset, clock_prefix="", reset_prefix="" *)
  module mkAwsF1Top#(Clock clk_main_a0, Clock clk_extra_a1, Clock clk_extra_a2,
         Clock  clk_extra_b0, Clock clk_extra_b1, Clock clk_extra_c0, Clock clk_extra_c1,
         Reset kernel_rst_n, Reset rst_main_n
         )(AwsF1Top);
  
negative.code:    let lMemServerIndicationOutputNoc <- mkPortalMsgIndication(extend(pack(PlatformIfcNames_MemServerIndicationH2S)), lMemServerIndicationOutput.portalIfc.indications, lMemServerIndicationOutput.portalIfc.messageSize, clocked_by defaultClock, reset_by defaultReset);
     let lMemServerRequestInputNoc <- mkPortalMsgRequest(extend(pack(PlatformIfcNames_MemServerRequestS2H)), lMemServerRequestInput.portalIfc.requests, clocked_by defaultClock, reset_by defaultReset);
  
     Axi4SlaveLiteBits#(32,32) sdaSlave <- mkAxi4SlaveLiteBitsFromPhysMemSlave(top.slave, clocked_by defaultClock, reset_by defaultReset);
  
     interface AwsF1ClSh cl_sh;
        method id0 = 32'hF000_1D0F; // 32'hc100_1be7;
        method id1 = 32'h1D51_FEDD; // 32'hc101_1be7;
     endinterface
  
     interface sda = sdaSlave;
  
  `ifdef PinType
     interface pins = top.pins;
  