anchor.diff:  
   package Pcie3EndpointX7;
   
  +import BRAMFIFO          ::*;
   import Clocks            ::*;
   import Vector            ::*;
   import BuildVector       ::*;
  
positive.code:    Pcie3Cfg_phy_link_status,
     Pcie3Cfg_pl_status_change,
     Pcie3Cfg_power_state_change_interrupt,
     Pcie3Cfg_rcb_status
     } Pcie3CfgType deriving (Bits,Eq);
  
  (* synthesize *)
  
negative.code: 	 pcie_ep.cfg.interrupt_msix_data(data);
  	 msix_int_enable <= True;
  	 intrMutex.enq(True);
        end
     endrule: rl_intr
     rule rl_intr_enable;
        pcie_ep.cfg.interrupt_msix_int(pack(msix_int_enable));
     endrule
  
  