anchor.diff:     PcieHostTop host <- mkPcieHostTop(pci_sys_clk_p, pci_sys_clk_n, sys_clk_p, sys_clk_n, pci_sys_reset_n);
   
   `ifdef IMPORT_HOSTIF
  -   let portalTop <- mkSynthesizeablePortalTop(host, clocked_by host.tepClock125, reset_by host.tepReset125);
  +   PortalTop#(40, DataBusWidth, PinType, NumberOfMasters) portalTop <- mkPortalTop(host, clocked_by host.tepClock125, reset_by host.tepReset125);
   `else
  -   let portalTop <- mkSynthesizeablePortalTop(clocked_by host.tepClock125, reset_by host.tepReset125);
  +   PortalTop#(40, DataBusWidth, PinType, NumberOfMasters) portalTop <- mkPortalTop(clocked_by host.tepClock125, reset_by host.tepReset125);
   `endif
      mkConnection(host.tpciehost.master, portalTop.slave, clocked_by host.tepClock125, reset_by host.tepReset125);
      if (valueOf(NumberOfMasters) > 0) begin
  
positive.code:    interface PcieHost tpciehost = pciehost;
  endmodule
  
  `ifndef BSIM
  (* no_default_clock, no_default_reset *)
  `endif
  
negative.code:    interface BscanTop bscanif = lbscan.loc[0];
  endmodule: mkPcieHost
  
  interface PcieTop#(type ipins);
  `ifndef BSIM
     (* prefix="PCIE" *)
  