anchor.diff:     interface Reg use4dw = use4dwReg;
      interface Reg tlpDataBramWrAddr = tlpDataBramWrAddrReg;
      interface Reg tlpOutCount = tlpOutCountReg;
  -   interface BRAMServer tlpDataBram = tlpDataBram1Port.portA;
  +   interface BRAMServer tlpDataBram = bscanBram.server;
   endmodule: mkControlAndStatusRegs
   
   // The PCIe-to-AXI bridge puts all of the elements together
  
positive.code:    function Action do_write(UInt#(30) addr, Vector#(4,Tuple2#(Bit#(4),Bit#(32))) value);
        action
           if ((addr % 8192) == 768) begin
  	     tlpDataBram1Port.portA.request.put(BRAMRequest{ write: False, responseOnWrite: False, address: truncate(tlpDataBramRdAddrReg), datain: unpack(0)});
  	     tlpDataBramRdAddrReg <= tlpDataBramRdAddrReg + 1;
  	 end else if ((addr % 8192) == 792) begin
  	     // update tplDataBramWrAddrReg and write back scratchpad
  
negative.code: 	 782: return zeroExtend(rcb_mask);
  	 783: return zeroExtend(pack(max_read_req_bytes));
  	 784: return zeroExtend(pack(max_payload_bytes));
  	 792: return extend(tlpDataBramWrAddrReg);
  	 793: return extend(tlpTraceLimitReg);
  	 795: return portalResetIfc.isAsserted() ? 1 : 0;
  
           //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
  