anchor.diff:  `endif
   
   	       // Machine mode
  -	       csr_addr_mvendorid:  noAction;
  -	       csr_addr_marchid:    noAction;
  -	       csr_addr_mimpid:     noAction;
  -	       csr_addr_mhartid:    noAction;
  +	       csr_addr_mvendorid:  result = mvendorid;    // hardwired
  +	       csr_addr_marchid:    result = marchid;      // hardwired
  +	       csr_addr_mimpid:     result = mimpid;       // hardwired
  +	       csr_addr_mhartid:    result = mhartid;      // hardwired
   	       csr_addr_mstatus:    begin
   				      result <- csr_mstatus.fav_write (misa, wordxl);
   				    end
  -	       csr_addr_misa:       noAction;
  +	       csr_addr_misa:       begin
  +				       result = misa_to_word (misa);
  +				    end
   	       csr_addr_mie:        begin
   				       result <- csr_mie.fav_write (misa, wordxl);
   				    end
  
positive.code: 	       csr_addr_sstatus:    begin
  				       result <- csr_mstatus.fav_sstatus_write (misa, wordxl);
  				    end
  	       csr_addr_sedeleg:    noAction;               // Hardwired to 0 (no delegation)
  	       csr_addr_sideleg:    noAction;               // Hardwired to 0 (no delegation)
  	       csr_addr_sie:        begin
  				       result <- csr_mie.fav_sie_write (misa, wordxl);
  				    end
  
negative.code: 				       result    = mtvec_to_word (mtvec);
  				       rg_stvec <= mtvec;
  				    end
  	       csr_addr_scounteren: result = 0;    // Hardwired to zero
  
  	       csr_addr_sscratch:   begin
  				       result       = wordxl;
  