anchor.diff:     clockParams.clkout0_buffer = True;
      clockParams.clkout2_buffer = True;
      ClockGenerator7 clockGen <- mkClockGenerator7Adv(clockParams, clocked_by b2c.c);
  -*/
       //mmcm_i ( .CLKINSEL(1'd1), .RST(1'b0), .PWRDWN(0), .DCLK(0), .DADDR( 7'd0), .DEN(0), .DWE(0), .DI(16'd0), .PSCLK(0), .PSEN(0), .PSINCDEC(0));
      //.LOCKED(clockGen.locked),
      //PIPE_DCLK_IN clockGen.clkout0);
  
positive.code:     end
  */
  ////////JJJJJJJJJJJJJJJJJJJJ
     Clock defaultClock <- exposeCurrentClock();
     //PCIE_X7#(lanes)                           pcie_ep             <- mkXilinx7PCIE(params, clockGen.clkout0, clockGen.clkout1, clockGen.clkout2, pack(clockGen.locked));
     PCIE_X7#(lanes)                           pcie_ep             <- mkXilinx7PCIE(params, defaultClock, defaultClock, defaultClock, 1'b0);
     C2B c2b <- mkC2B(pcie_ep.txoutclk);
     rule txoutrule;
        b2c.inputclock(c2b.o());
     endrule
  
negative.code:    /// Design Elements
     ////////////////////////////////////////////////////////////////////////////////
     B2C1 b2c <- mkB2C1();
     ClockGenerator7AdvParams clockParams = defaultValue;
     clockParams.bandwidth          = "OPTIMIZED";
     clockParams.compensation       = "ZHOLD";
  