anchor.diff:              iserdes_data[6].read(), iserdes_data[5].read(), iserdes_data[4].read(),
               iserdes_data[3].read(), iserdes_data[2].read(), iserdes_data[1].read(),
               iserdes_data[0].read()};
  +        dackint_last <= dackint.read();
  +        if (dackint.read() == 1 && dackint_last == 0)
  +            ctrl_data <= dout;
           serbvi.dataout(dout);
           serbvi.dackint(dackint.read());
           dfifo.di({6'b0,dout});
  
positive.code:     SyncBitIfc#(Bit#(1)) fifo_wren_sync <- mkSyncBitToCC(serdes_clock, serdes_reset);
      Vector#(10, SyncBitIfc#(Bit#(1))) iserdes_data <-  replicateM(mkSyncBitToCC(serdes_clock, serdes_reset));
      SyncBitIfc#(Bit#(1)) dackint <- mkSyncBitToCC(serdes_clock, serdes_reset);
      //Reg#(Bit#(10)) iserdes_data0 <-  mkReg(0);
      //Reg#(Bit#(1)) dackint0 <- mkReg(0);
  
      Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  
      rule wrensyncr_rule if (bvi_reset_reg == 0);
          dfifo_wren_r <= 0;
  
negative.code:     method                  training(TRAINING) enable((*inhigh*) en8) clocked_by (clock);
      method                  manual_tap(MANUAL_TAP) enable((*inhigh*) en9) clocked_by (clock);
      method                  reset(RESET) enable((*inhigh*) en17) clocked_by (clkdiv) reset_by(clkdiv_reset);
      method                  dataout(CTRL_DATA) enable((*inhigh*) en18) clocked_by(clock);
      method ITEMREQ_o        itemreq() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method CTRL_BITSLIP_o   ctrl_bitslip() clocked_by(clkdiv) reset_by(clkdiv_reset);
      method CTRL_FIFO_RESET_o   ctrl_fifo_reset() clocked_by(clkdiv) reset_by(clkdiv_reset);
  