anchor.diff:        debugReg <= False;
      endrule
   
  -   rule loadChannel if (valueOf(numReadClients) > 0);
  +   rule loadChannel if (valueOf(numReadClients) > 0 && !isConfiguring);
         DMAAddressRequest req = unpack(0);
         if (valueOf(numReadClients) > 0)
   	 req <- readClients[selectReg].readReq.get();
  -      $display("dmaread.loadClient activeChan=%d handle=%h addr=%h burst=%h", selectReg, req.handle, req.address, req.burstLen);
  -
  -      reqFifo.enq(req);
  +      $display("dmaread.loadChannel activeChan=%d handle=%h addr=%h burst=%h", selectReg, req.handle, req.address, req.burstLen);
  +
  +      lreqFifo.enq(req);
         chanFifo.enq(selectReg);
         sgl.addrReq(truncate(req.handle),req.address);
      endrule
      
  -   rule checkSglResp;
  +   rule checkSglResp if (!debugReg);
         let physAddr <- sgl.addrResp();
  +      let req = lreqFifo.first();
  +      lreqFifo.deq();
         if (physAddr == 0) begin
   	 // squash request
  -	 reqFifo.deq();
  -	 dmaIndication.badAddr(reqFifo.first.handle, reqFifo.first.address);
  +	 dmaIndication.badAddr(req.handle, req.address);
         end
         else begin
  +	 reqFifo.enq(req);
   	 paFifo.enq(physAddr);
         end
      endrule
   
  -   method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr);
  -      sgl.page(truncate(tabsel), off, addr);
  -   endmethod
  -   
  -   method Action readSglist(Bit#(32) pref, Bit#(40) addr) if (!debugReg);
  -      debugReg <= True;
  -      sgl.addrReq(truncate(pref), addr);
  -   endmethod
  +   interface ConfigureSglist configure;
  +       method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr) if (isConfiguring);
  +	  sgl.page(truncate(tabsel), off, addr);
  +       endmethod
  +
  +       method Action readSglist(Bit#(32) pref, Bit#(40) addr) if (!debugReg);
  +	  debugReg <= True;
  +	  sgl.addrReq(truncate(pref), addr);
  +       endmethod
  +      method Action configuring(Bool c);
  +	 isConfiguring <= c;
  +      endmethod
  +   endinterface
   
      interface DMARead read;
         method ActionValue#(DmaDbgRec) dbg();
  
positive.code: 	    respFifo.enq(activeChan);
  	 end
  
  	 burstReg <= burstLen-1;
  
  	 Bit#(1) last = burstLen == 1 ? 1'b1 : 1'b0;
  
negative.code: module mkAxiDMAWriteInternal#(Integer numRequests, Vector#(numWriteClients, DMAWriteClient#(dsz)) writeClients,
  			      DMAIndication dmaIndication)(AxiDMAWriteInternal#(dsz,dbytes))
     provisos(Add#(1,a__,dsz),
  	    Mul#(dbytes,8,dsz),
  	    Add#(b__, TAdd#(dsz, 8), 128));
     SGListMMU sgl <- mkSGListMMU();
     
     FIFO#(DMAAddressRequest) lreqFifo <- mkPipelineFIFO();
     FIFO#(DMAAddressRequest) reqFifo <- mkFIFO();
     FIFO#(DMAAddressRequest) dreqFifo <- mkSizedFIFO(numRequests);
     FIFO#(Bit#(40))        paFifo     <- mkFIFO();
  