anchor.diff:      Divider divider <- mkDivider;
       Reg#(Bool) dividerPending <- mkReg(False);
   
  +    Reg#(Bool) irqEnabled <- mkReg(False);
  +    Reg#(Bit#(32)) irqMask <- mkRegU;
  +    Reg#(Bit#(24)) irqReturnAddr <- mkRegU;
  +    RWire#(Bit#(32)) irqIn <- mkRWire;
  +
       Reg#(Bool) clearCache <- mkReg(False);
   
       mkConnection(cache.busClient.request, masterAdapter.busServer.request);
       mkConnection(masterAdapter.busServer.response, cache.busClient.response);
       mkConnection(cache.instCache.response, toPut(instFIFO));
       mkConnection(cache.dataCache.response, toPut(dataFIFO));
  +
  +    rule getIrq;
  +        let irq <- masterAdapter.irqGet.get;
  +        if(irqEnabled)
  +            irqIn.wset(irq);
  +    endrule
   
       rule clearTheCaches(clearCache);
           clearCache <= False;
  
positive.code:                 case (s.sc)
                      20'h0000: $finish();
                      20'h0001: $display("[syscall 1] %h", rf.rd1(4));
                      20'h00ff: clearCache <= True;
                  endcase
              tagged ILLEGAL : $display("Exec error: Invalid instruction %h at pc=%h", pack(inst), pc);
          endcase
  
negative.code:         trace($format("[Fetch %h]", fetchPC));
          cache.instCache.request.put(AvalonRequest{command: Read, addr: fetchPC, data: ?});
          execPC.enq(fetchPC);
          if(irqIn.wget matches tagged Valid .irq)
            begin
              fetchPC <= 'h080;
              irqReturnAddr <= fetchPC + 1;
              irqMask <= irq;
              irqEnabled <= False;
            end
          else
            begin
              fetchPC <= fetchPC + 1;
            end
      endrule
  
      rule fetchJump(jumpTo.notEmpty && !clearCache);
          trace($format("[Fetch %h] [jump %h]", fetchPC, jumpTo.first));
          cache.instCache.request.put(AvalonRequest{command: Read, addr: fetchPC, data: ?});
          execPC.enq(fetchPC);
          if(irqIn.wget matches tagged Valid .irq)
            begin
              fetchPC <= 'h080;
              irqReturnAddr <= jumpTo.first;
              irqMask <= irq;
              irqEnabled <= False;
            end
          else
            begin
              fetchPC <= jumpTo.first;
            end
          jumpTo.deq;
      endrule
  
  