anchor.diff:      Maybe#(SpecTag) spec_tag;
   } AluExeToFinish deriving(Bits, Eq, FShow);
   
  -typedef struct {
  -    Addr pc;
  -    Addr nextPc;
  -    IType iType;
  -    Bool taken;
  -    DirPredTrainInfo dpTrain;
  -    Bool mispred;
  -} AluExeTrainBP deriving(Bits, Eq, FShow);
  -
   // XXX currently ALU/Br should not have any exception, so we don't have cause feild above
   // TODO FIXME In future, if branch target is unaligned to 4 bytes, we may have exception
   // and probably JR/JAL should NOT write dst reg when exception happens
  
positive.code:     // index to send bypass, ordering doesn't matter
      Integer exeSendBypassPort = 0;
      Integer finishSendBypassPort = 1;
  
      // train BP in a new cycle
      FIFO#(AluExeTrainBP) trainBPQ <- mkFIFO;
  
  `ifdef PERF_COUNT
      // performance counters
  
negative.code:             // since we can only do 1 training in a cycle, split the rule
              // XXX not training JAL, reduce chance of conflicts
              if(x.iType == Jr || x.iType == Br) begin
                  inIfc.fetch_train_predictors(FetchTrainBP {
                      pc: x.controlFlow.pc,
                      nextPc: x.controlFlow.nextPc,
                      iType: x.iType,
  