anchor.diff:  // blocks of 8 64 bit words
   // A Command:
   //  word 0: COPY[63:56] TAG[31:0]
  -//  word 1: readAddress[39:0]
  -//  word 2: writeAddress[39:0]
  -//  word 3: bytecount[15:0'
  +//  word 1: readMemHandle[63:32]
  +//  word 1: readAddress[23:0]
  +//  word 2  writeMemHandle[63:32]
  +//  word 2: writeAddress[23:0]
  +//  word 3: bytecount[15:0]
   //  word 4-7 unused
   // Status
   //  word0-6 all 0
  
positive.code:    FIFO#(Bit#(64)) f_out <- mkSizedFIFO(16);    // to buffer outgoing responses
     Reg#(Bit#(16)) copyReadCount <- mkReg(0);
     Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
     Reg#(Bit#(40)) copyReadAddr <- mkReg(0);
     Reg#(Bit#(40)) copyWriteAddr <- mkReg(0);
     Reg#(Bit#(32)) copyTag <- mkReg(0);
     Reg#(Bool) copyBusy <- mkReg(False);
      
  
negative.code:     rule copyReadWriteRule (copyBusy);
         let data <- copy_read_chan.readData.get;
         $display("copyReadWrite addr %h", copyWriteAddr);
         copy_write_chan.writeReq.put(DMAAddressRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: extend(1), tag: truncate(copyWriteAddr >> 3)});
         copy_write_chan.writeData.put(DMAData{data: data.data, tag: copyWriteAddr >> 3});
         copyWriteAddr <= copyWriteAddr + 8;
      endrule
      
  