anchor.diff:     endrule: intr_ifc_ctl
   
      // Build the PCIe-to-AXI bridge
  -   PcieToAxiBridge#(BPB)  bridge <- mkPcieToAxiBridge_4( contentId
  +   PcieToAxiBridge#(BPB)  bridge <- mkPcieToAxiBridge( contentId
   						       , my_id
   						       , max_read_req_bytes
   						       , max_payload_bytes
  
positive.code: // This module builds the transactor hierarchy, the clock
  // generation logic and the PCIE-to-port logic.
  (* no_default_clock, no_default_reset *)
  module mkX7PcieBridge#( Clock pci_sys_clk_p, Clock pci_sys_clk_n
  		       , Clock sys_clk_p,    Clock sys_clk_n
  		       , Reset pci_sys_reset
  
negative.code: endmodule: mkControlAndStatusRegs
  
  // The PCIe-to-AXI bridge puts all of the elements together
  module mkPcieToAxiBridge#( Bit#(64)  board_content_id
  			 , PciId     my_id
  			 , UInt#(13) max_read_req_bytes
  