anchor.diff:           3: return fromInteger(major_rev);
            4: return pack(buildVersion);
            5: return pack(epochTime);
  -         6: return {23'd0,pack(is_board_number_assigned),4'd0,pack(board_number)};
  +         //jca 6: return {23'd0,pack(is_board_number_assigned),4'd0,pack(board_number)};
            7: return {24'd0,fromInteger(bytes_per_beat)};
            8: return board_content_id[31:0];
            9: return board_content_id[63:32];
  -         64: return 0;
  -         512: return 0;
  -         513: return 0;
  -         514: return 0;
  -         515: return 0;
  +         //jca 64: return 0;
  +         //jca 512: return 0;
  +         //jca 513: return 0;
  +         //jca 514: return 0;
  +         //jca 515: return 0;
   	 768: return 0;
  -	 769: return 0;
  -	 770: return 0;
  -	 771: return 0;
  -	 772: return 0;
  -	 773: return 0;
  +	 //jca 769: return 0;
  +	 //jca 770: return 0;
  +	 //jca 771: return 0;
  +	 //jca 772: return 0;
  +	 //jca 773: return 0;
   	 774: return tlpSeqnoReg;
   	 775: return (tlpTracingReg ? 1 : 0);
   	 776: return tlpDataBramResponseSlice(0);
  
positive.code:    function Action wr_csr(UInt#(30) addr, Bit#(4) be, Bit#(32) dword);
        action
           case (addr % 8192)
              // board identification
              6:  begin
                     if (be[0] == 1) board_number             <= unpack(dword[3:0]);
                     if (be[1] == 1) is_board_number_assigned <= unpack(dword[8]);
                  end
  	    774: tlpSeqnoReg <= dword;
  	    775: tlpTracingReg <= (dword != 0) ? True : False;
  	    776: tlpDataScratchpad[0] <= dword;
  
negative.code:    Integer minor_rev = 0;
  
     // Registers and their default values
     //jca Reg#(Bool)            is_board_number_assigned <- mkReg(False);
     //jca Reg#(UInt#(4))        board_number             <- mkReg(15);
     Vector#(4,MSIX_Entry) msix_entry               <- replicateM(mkMSIXEntry);
  
     Reg#(Bool) tlpTracingReg <- mkReg(False);
     //jca Reg#(Bool) axiEnabledReg <- mkReg(False);
     Reg#(Bool) byteSwapReg <- mkReg(False);
     Reg#(Bool) use4dwReg <- mkReg(True);
     Reg#(Bit#(4)) numPortalsReg <- mkReg(1);
  