anchor.diff:     Clock portalClock = clock125;
      Reset portalReset = reset125;
   `endif
  -//   // The PCIE endpoint is processing TLPData#(8)s at 250MHz.  The
  -//   // AXI bridge is accepting TLPData#(16)s at 125 MHz. The
  -//   // connection between the endpoint and the AXI contains GearBox
  -//   // instances for the TLPData#(8)@250 <--> TLPData#(16)@125
  -//   // conversion.
  +   // The PCIE endpoint is processing TLPData#(8)s at 250MHz.  The
  +   // AXI bridge is accepting TLPData#(16)s at 125 MHz. The
  +   // connection between the endpoint and the AXI contains GearBox
  +   // instances for the TLPData#(8)@250 <--> TLPData#(16)@125
  +   // conversion.
      PcieGearbox gb <- mkPcieGearbox(clock250, reset250, portalClock, portalReset);
   //   mkConnection(tlp8, gb.tlp, clocked_by portalClock, reset_by portalReset);
   
  
positive.code:    PCIEParams params = defaultValue;
     Clock defaultClock <- exposeCurrentClock();
     Reset defaultReset <- exposeCurrentReset();
  
     PcieWrap#(PcieLanes) pcie_ep <- mkPcieWrap(defaultClock, defaultReset);
  
     //FIFOF#(AxiTx)             fAxiTx              <- mkBypassFIFOF(clocked_by pcie_ep.user.clk_out, reset_by noReset);
     //FIFOF#(AxiRx)             fAxiRx              <- mkBypassFIFOF(clocked_by pcie_ep.user.clk_out, reset_by noReset);
  
     (* fire_when_enabled, no_implicit_conditions *)
     rule every1;
  //      pcie_ep.fc.sel(0 /*RECEIVE_BUFFER_AVAILABLE_SPACE*/);
  //      pcie_ep.cfg.config_space_enable(1'b1);
  //      pcie_ep.cfg.dsn({ 32'h0000_0001, {{ 8'h1 } , 24'h000A35 }});
  //      pcie_ep.cfg.link_training_enable(1'b1);
  //      pcie_ep.rx.np_ok(1);
  //      pcie_ep.rx.np_req(1);
  //      pcie_ep.tx.cfg_gnt(1);
  //      pcie_ep.s_axis_tx.tuser(4'b0);
  //      pcie_ep.m_axis_rx.tready(pack(fAxiRx.notFull));
     endrule
  //   rule every2;
  //      pcie_ep.pipe_mmcm_lock_in(pack(clockGen.locked));
  //   endrule
  
  //   Clock txoutclk_buf <- mkClockBUFG(clocked_by pcie_ep.pipe_txoutclk_out);
  //
  //   C2B c2b <- mkC2B(txoutclk_buf);
  //   rule txoutrule;
  //      b2c.inputclock(c2b.o());
  //   endrule
  
  //   let txready = (pcie_ep.s_axis_tx.tready != 0 && fAxiTx.notEmpty);
  //
  //   //(* fire_when_enabled, no_implicit_conditions *)
  //   rule drive_axi_tx if (txready);
  //      let info = fAxiTx.first; fAxiTx.deq;
  //      pcie_ep.s_axis_tx.tvalid(1);
  //      pcie_ep.s_axis_tx.tlast(info.last);
  //      pcie_ep.s_axis_tx.tdata(info.data);
  //      pcie_ep.s_axis_tx.tkeep(info.keep);
  //   endrule
  //
  //   (* fire_when_enabled, no_implicit_conditions *)
  //   rule drive_axi_tx2 if (!txready);
  //      pcie_ep.s_axis_tx.tvalid(0);
  //      pcie_ep.s_axis_tx.tlast(0);
  //      pcie_ep.s_axis_tx.tdata(0);
  //      pcie_ep.s_axis_tx.tkeep(0);
  //   endrule
  //
  //   (* fire_when_enabled *)
  //   rule sink_axi_rx if (pcie_ep.m_axis_rx.tvalid != 0);
  //      fAxiRx.enq(AxiRx {user: pcie_ep.m_axis_rx.tuser,
  //                        last: pcie_ep.m_axis_rx.tlast,
  //                        keep: pcie_ep.m_axis_rx.tkeep,
  //                        data: pcie_ep.m_axis_rx.tdata });
  //   endrule
  
     // The PCIe endpoint exports full (250MHz) and half-speed (125MHz) clocks
     Clock clock250 = pcie_ep.user_clk;
  
negative.code: endinterface
  
  typedef struct {
     Bit#(85)      user;
     Bit#(1)       last;
     Bit#(8)       keep;
     Bit#(256)     data;
  } AxiCQ deriving (Bits, Eq);
  
  typedef struct {
     Bit#(75)      user;
     Bit#(1)       last;
     Bit#(8)       keep;
     Bit#(256)     data;
  } AxiRC deriving (Bits, Eq);
  
  typedef struct {
     Bit#(1)       last;
     Bit#(8)       keep;
     Bit#(256)     data;
     Bit#(33)      user;
     Bit#(1)       valid;
  } AxiCC deriving (Bits, Eq);
  
  typedef struct {
     Bit#(60)      user;
     Bit#(1)       last;
     Bit#(8)       keep;
     Bit#(256)     data;
     Bit#(1)       valid;
  } AxiRQ deriving (Bits, Eq);
  
  `ifdef BOARD_vc709
  typedef 8 PcieLanes;
  