anchor.diff:  	 cache: 4'b0011, //ignored
   	 lock: 2'b00,    //ignored
   	 qos: 4'b0000    //ignored
  -	 });
  +	 };
  +      arfifo.enq(req);
         dramReadOffset <= dramReadOffset + 1;
      endrule
   
      rule rl_rdata;
         let resp <- ddr3Controller.slave.resp_read.get();
         Vector#(BusRatio, Bit#(DataBusWidth)) data = unpack(resp.data);
  +      rdataProbe <= data;
         dramReadGearbox.enq(data);
      endrule
      FIFOF#(Bit#(DataBusWidth)) slackFifo <- mkFIFOF();
  
positive.code: import AxiDma::*;
  import ConnectalConfig::*;
  import HostInterface::*;
  
  interface Ddr3TestRequest;
     method Action startWriteDram(Bit#(32) sglId);
  
negative.code:    endrule
     rule rl_wdata;
        let mds <- toGet(dramWriteGearbox).get();
        wdataProbe <= mds;
        ddr3Controller.slave.resp_write.put(Axi4WriteData {
  	 data: pack(mds),
  	 byteEnable: maxBound,
  