anchor.diff:     Reg#(Bit#(4)) alumodeReg <- mkReg(0);
      Wire#(Bit#(3)) carryinselWire <- mkDWire(0);
      Wire#(Bit#(5)) inmodeWire <- mkDWire(0);
  -   Wire#(Bit#(7)) opmodeWire <- mkDWire(7'h35);
  -   Reg#(Bit#(7)) opmodeReg <- mkReg(7'h35);
  +   Wire#(Bit#(7)) opmodeWire <- mkDWire(7'h20);
  +   Reg#(Bit#(7)) opmode1Reg <- mkReg(0);
  +   Reg#(Bit#(7)) opmode2Reg <- mkReg(0);
  +   Reg#(Bit#(7)) opmode3Reg <- mkReg(0);
  +   Reg#(Bit#(7)) opmode4Reg <- mkReg(0);
   
      Wire#(Bit#(30)) aWire <- mkDWire(0);
      Wire#(Bit#(18)) bWire <- mkDWire(0);
  
positive.code:    Wire#(Bit#(1)) ce1Wire <- mkDWire(0);
     Reg#(Bit#(1)) ce2Reg <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1)) cepReg <- mkReg(0, reset_by optionalReset);
     Wire#(Bit#(1)) last1Wire <- mkDWire(0);
     Reg#(Bit#(1))  last2Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last3Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last4Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last5Reg  <- mkReg(0, reset_by optionalReset);
     Reg#(Bit#(1))  last6Reg  <- mkReg(0, reset_by optionalReset);
  
     rule clock_enable_and_reset;
        ce2Reg <= ce1Wire;
        cepReg <= ce2Reg;
  
        last2Reg <= last1Wire;
        last3Reg <= last2Reg;
        last4Reg <= last3Reg;
        last5Reg <= last4Reg;
        last6Reg <= last5Reg;
  
        dsp.cea1(1); // (ce1Wire);
        dsp.cea2(1); // (ce2Reg);
  
negative.code:    method Action d(Bit#(25) v);
        dsp.d(v);
     endmethod
     method Bit#(48) p() if (last5Reg == 1);
        return dsp.p();
     endmethod
     method Action last(Bit#(1) v);
        lastWire <= v;
     endmethod
  endmodule
  