anchor.diff:  	 method Action put(MemRequest#(addrWidth) req);
   	    req_ars.enq(MemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag});
   	    req_ar_fifo.enq(?);
  -	    rs <= truncate(psel(req.addr)); 
  +	    rs.enq(truncate(psel(req.addr)));
  +	    if (req.burstLen > 1) $display("**** \n\n mkSlaveMux.readReq len=%d \n\n ****", req.burstLen);
  +	    //$display("mkSlaveMux.readReq addr=%h aw=%d psel=%h", req.addr, valueOf(aw), psel(req.addr));
   	 endmethod
         endinterface
         interface Get readData;
   	 method ActionValue#(ObjectData#(dataWidth)) get();
  -	    let rv <- ifcs[rs].read_server.readData.get();
  +	    let rv <- ifcs[rs.first].read_server.readData.get();
   	    req_ar_fifo.deq;
  +	    rs.deq();
  +	    //$display("mkSlaveMux.readData rs=%d data=%h", rs.first, rv.data);
   	    return rv;
   	 endmethod
         endinterface
  
positive.code: 
     FIFO#(MemRequest#(aw)) req_ars <- mkSizedFIFO(1);
     FIFO#(void) req_ar_fifo <- mkSizedFIFO(1);
     Reg#(Bit#(TLog#(numSlaves))) rs <- mkReg(0);
  
     FIFO#(MemRequest#(aw)) req_aws <- mkSizedFIFO(1);
     FIFO#(void) req_aw_fifo <- mkSizedFIFO(1);
     Reg#(Bit#(TLog#(numSlaves))) ws <- mkReg(0);
  
     rule req_aw;
        let req <- toGet(req_aws).get;
        ifcs[ws].write_server.writeReq.put(req);
     endrule
  
     rule req_ar;
        let req <- toGet(req_ars).get;
        ifcs[rs].read_server.readReq.put(req);
     endrule
  
     interface MemWriteServer write_server;
  
negative.code:    
     FIFO#(MemRequest#(aw)) req_ars <- mkSizedFIFO(1);
     FIFO#(void) req_ar_fifo <- mkSizedFIFO(1);
     FIFO#(Bit#(TLog#(numInputs))) rs <- mkFIFO();
     
     FIFO#(MemRequest#(aw)) req_aws <- mkSizedFIFO(1);
     FIFO#(void) req_aw_fifo <- mkSizedFIFO(1);
     FIFO#(Bit#(TLog#(numInputs))) ws <- mkFIFO();
     
     rule req_aw;
        let req <- toGet(req_aws).get;
        ifcs[ws.first].write_server.writeReq.put(req);
     endrule
           
     rule req_ar;
        let req <- toGet(req_ars).get;
        ifcs[rs.first].read_server.readReq.put(req);
     endrule
     
     interface MemWriteServer write_server;
        interface Put writeReq;
  	 method Action put(MemRequest#(addrWidth) req);
  	    req_aws.enq(MemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag});
  	    if (req.burstLen > 1) $display("**** \n\n mkSlaveMux.writeReq len=%d \n\n ****", req.burstLen);
  	    req_aw_fifo.enq(?);
  	    ws.enq(truncate(psel(req.addr)));
  	    //$display("mkSlaveMux.writeReq addr=%h aw=%d psel=%h", req.addr, valueOf(aw), psel(req.addr));
  	 endmethod
        endinterface
        interface Put writeData;
  	 method Action put(ObjectData#(dataWidth) wdata);
  	    ifcs[ws.first].write_server.writeData.put(wdata);
  	 endmethod
        endinterface
        interface Get writeDone;
  	 method ActionValue#(Bit#(6)) get();
  	    let rv <- ifcs[ws.first].write_server.writeDone.get();
  	    req_aw_fifo.deq;
  	    ws.deq();
  	    return rv;
  	 endmethod
        endinterface
  