anchor.diff:     Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) copyReadAddr <- mkReg(0);
      Reg#(Bit#(DmaOffsetSize)) copyWriteAddr <- mkReg(0);
  -   Reg#(DmaPointer) copyReadHandle <- mkReg(0);
  -   Reg#(DmaPointer) copyWriteHandle <- mkReg(0);
  +   Reg#(DmaPointer) copyReadPointer <- mkReg(0);
  +   Reg#(DmaPointer) copyWritePointer <- mkReg(0);
      Reg#(Bit#(32)) copyTag <- mkReg(0);
      Reg#(Bool) copyBusy <- mkReg(False);
      Reg#(Bit#(4)) cmdCtr <- mkReg(0);
  
positive.code:     rule copyReadWriteRule (copyBusy);
         let data <- copy_read_chan.readData.get;
         //$display("copyReadWrite addr %h", copyWriteAddr);
         copy_write_chan.writeReq.put(DmaRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: 1, tag: copyWriteAddr[8:3]});
         copy_write_chan.writeData.put(DmaData{data: data.data, tag: copyWriteAddr[8:3]});
         copyWriteAddr <= copyWriteAddr + 8;
      endrule
  
negative.code:       while(True)
  	 seq
  	    while (copyBusy) noAction;
  	    f_in.deq();  // word 0
  	    action
  	       copyReadPointer <= truncate(f_in.first());
  	       f_in.deq();  // word 1
  	    endaction
  	    action
  	       copyReadAddr <= truncate(f_in.first());
  	       f_in.deq();  // word 2
  	    endaction
  	    action
  	       copyWritePointer <= truncate(f_in.first());
  	       f_in.deq(); // word 3
  	    endaction
  	    action
  	       copyWriteAddr <= truncate(f_in.first());
  	       f_in.deq();  // word 4
  	    endaction
  	    action
  	       copyReadCount <= f_in.first()[15:0];
  	       copyWriteCount <= f_in.first()[15:0];
  	       f_in.deq();  // word 5
  	    endaction
  	       f_in.deq;  // discard word 6
  	    action
  	       copyTag <= truncate(f_in.first());
  	       f_in.deq;  // word 7
  	    endaction
  	    
  	    //$display("copyStart from %h to %h count %h",
  