anchor.diff:      {  4,-13, 22,-31, 38,-46, 54,-61, 67,-73, 78,-82, 85,-88, 90,-90 }
   };
   
  +// External interface
   interface IDct32;
  +   method Action setSize(Bit#(2) dsize);
      interface Put#(Vector#(2, Vector#(32, Bit#(9)))) io_in;
  -   interface Get#(Vector#(4, Bit#(16))) io_out;
  +   interface Get#(Vector#(32, Bit#(16))) io_out;
   endinterface
   
   interface IDct32Core#(numeric type a);
  -   method Bit#(16) dct(Vector#(16, Bit#(a)) x, Bit#(5) idx);
  +   method Vector#(15, Bit#(16)) dct(Vector#(16, Bit#(a)) x, Bit#(5) idx);
   endinterface
  +
   
   module mkDct32Core(IDct32Core#(a))
      provisos(
  -      Add#(_x, 9, a),
         Add#(0, 8, b),
         Add#(1, c, TAdd#(a, b)),
         Add#(c, 1, c1),
         Add#(c, 2, c2),
         Add#(a, 10/*(5-1+6)*/, bs),
  -      Add#(shift, 16, bs),
  -      Add#(0, TExp#(TSub#(shift, 1)), round)
  +      Add#(shift32, 16, bs),
  +      Add#(1, shift16, shift32),
  +      Add#(2, shift8, shift32),
  +      Add#(3, shift4, shift32),
  +      Add#(0, TExp#(TSub#(shift32, 1)), round),
  +      Add#(_x1, 9, a),
  +      Add#(_x2, 16, c),
  +      Add#(_x3, 16, c1),
  +      Add#(_x4, 16, c2)
      );
   
      Vector#(16, SMUL#(a,b)) smul <- replicateM(mkSMUL);
   
  -   method Bit#(16) dct(Vector#(16, Bit#(a)) x, Bit#(5) idx);
  +   method Vector#(15, Bit#(16)) dct(Vector#(16, Bit#(a)) x, Bit#(5) idx);
         Bit#(c) x0[16];
         for(Integer i = 0; i < 16; i = i + 1)
            x0[i] = smul[i].c(x[i], fromInteger(g_t32[idx][i]));
  
positive.code:       for(Integer i = 0; i < 2; i = i + 1)
           x3[i] = sExtend(x2[2 * i + 0]) + sExtend(x2[2 * i + 1]);
  
        Bit#(bs) sum = sExtend(x3[0]) + sExtend(x3[1]) + fromInteger(valueOf(round));
  
        return truncate(sum >> valueOf(shift));
     endmethod
  endmodule
  
  (* synthesize *)
  module mkDct32(IDct32);
     FIFOF#(Vector#(2, Vector#(32, Bit#(10)))) fifo_in <- mkPipelineFIFOF;         // [E[0..15] O[0..15]]
     FIFOF#(Vector#(4, Bit#(16))) fifo_out <- mkPipelineFIFOF;
  
  
     Reg#(Bit#(16)) cycles <- mkReg(0);
  
negative.code:       syncCol <= {syncCol[0], w_syncCol};
     endrule
  
  
     rule pre_2D({syncCol[1],colCnt[4:0]} != 0);
        Vector#(32, Bit#(16)) x;
        Vector#(32, Bit#(17)) y;
  
  