anchor.diff:              let cric = 3'b011;
               retrycounter <= retrycounter - 1;
               start_handshake.enq(1);
  -            //if (start_handshake == 0 && edge_intor_reg == 1)
               if (edge_intor_reg == 1)
                   begin
                   data_init <= ctrl_data;
  
positive.code:         sync_bitslip <= ctrl_bitslip_serdes.read();
          dstate <= DValid;
          dcounter <= 3;
          iserdes_bitslip <= sync_bitslip;
      endrule
      rule state1_rule if (bvi_reset_reg != 0 && dstate == DValid);
          dcounter <= dcounter - 1;
          if (dcounter[2] == 1)
              begin
              dackint.send(1);
              dstate <= DLow;
              end
          Bit#(3) sric = sync_reset_inc_ce;
          sric[0] = 0;
          sric[1] = 0;
          sync_reset_inc_ce <= sric;
          sync_bitslip <= 0;
          iserdes_bitslip <= sync_bitslip;
      endrule
      rule state2_rule if (bvi_reset_reg != 0 && dstate == DLow);
          dackint.send(0);
          dstate <= DIdle;
          Bit#(3) sric = sync_reset_inc_ce;
          sric[0] = 0;
          sric[1] = 0;
          sync_reset_inc_ce <= sric;
          sync_bitslip <= 0;
          iserdes_bitslip <= sync_bitslip;
      endrule
  
      rule setrule;
  
negative.code:     method Action           ibufdso(Bit#(1) v);
      method Bit#(1)          align_busy();
      method Bit#(1)          aligned();
      method Bit#(3)          samplein();
      method Action           delay_wren(Bit#(1) v);
      method Action           fifo_wren(Bit#(1) v);
      method Action           reset(Bit#(1) v);
  