anchor.diff:      rule copyReadWriteRule (copyBusy);
          let data <- copy_read_chan.readData.get;
          $display("copyReadWrite addr %h", copyWriteAddr);
  -       copy_write_chan.writeReq.put(copyWriteAddr);
  -       copy_write_chan.writeData.put(data);
  +       copy_write_chan.writeReq.put(DMAAddressRequest{handle: copyWriteHandle, address: copyWriteAddr, burstLen: extend(1), tag: truncate(copyWriteAddr >> 3)});
  +       copy_write_chan.writeData.put(DMAData{data: data.data, tag: copyWriteAddr >> 3});
          copyWriteAddr <= copyWriteAddr + 8;
       endrule
       
  
positive.code: // blocks of 8 64 bit words
  // A Command:
  //  word 0: COPY[63:56] TAG[31:0]
  //  word 1: readAddress[39:0]
  //  word 2: writeAddress[39:0]
  //  word 3: bytecount[15:0'
  //  word 4-7 unused
  // Status
  //  word0-6 all 0
  
negative.code:    FIFO#(Bit#(64)) f_out <- mkSizedFIFO(16);    // to buffer outgoing responses
     Reg#(Bit#(16)) copyReadCount <- mkReg(0);
     Reg#(Bit#(16)) copyWriteCount <- mkReg(0);
     Reg#(Bit#(DmaAddrSize)) copyReadAddr <- mkReg(0);
     Reg#(Bit#(DmaAddrSize)) copyWriteAddr <- mkReg(0);
     Reg#(DmaMemHandle) copyReadHandle <- mkReg(0);
     Reg#(DmaMemHandle) copyWriteHandle <- mkReg(0);
     Reg#(Bit#(32)) copyTag <- mkReg(0);
     Reg#(Bool) copyBusy <- mkReg(False);
      
  