anchor.diff:                                                              , msix_enabled
                                                               , msix_mask_all_intr
                                                               , msi_enabled
  +							    , dispatcher.tlp_portal_drop_count
  +							    , dispatcher.tlp_axi_drop_count
   							    , portalResetIfc
                                                               );
      Reg#(Bit#(32)) timestamp <- mkReg(0);
  
positive.code:    interface Get#(TLPData#(16)) tlp_out_to_portal;
     interface Get#(TLPData#(16)) tlp_out_to_axi;
  
     // activity indicators
     (* always_ready *)
     method Bool read_tlp();
  
negative.code: 	 794: return extend(tlpTraceLimitReg);
  	 795: return portalResetIfc.isAsserted() ? 1 : 0;
  
  	 900: return tlp_portal_drop_count;
  	 901: return tlp_axi_drop_count;
  
           //******************************** start of area referenced from xilinx_x7_pcie_wrapper.v
           // 4-entry MSIx table
           4096: return msix_entry[0].addr_lo;            // entry 0 lower address
  