anchor.diff:        else if (regist == 2) rbufferfirst <= addr;
         else if (regist == 3) rbufferlast <= addr;
         else if (regist == 4) rbuffermask <= addr;
  +      else if (regist == 5) rmemhandle <= truncate(addr);
         else renable <= (addr[0] != 0);
      endmethod
      
  
positive.code:    interface Reg bufferfirst = rbufferfirst;
     interface Reg bufferlast = rbufferlast;
     interface Reg enable = renable;
  
  endmodule
  
negative.code: 
  module mkRingBuffer(RingBuffer);
     
     Reg#(Bit#(DmaAddrSize)) rbufferbase <- mkReg(0);
     Reg#(Bit#(DmaAddrSize)) rbufferend <- mkReg(0);
     Reg#(Bit#(DmaAddrSize)) rbufferfirst <- mkReg(0);
     Reg#(Bit#(DmaAddrSize)) rbufferlast <- mkReg(0);
     Reg#(Bit#(DmaAddrSize)) rbuffermask <- mkReg(0);
     Reg#(DmaMemHandle) rmemhandle <- mkReg(0);
     Reg#(Bool) renable <- mkReg(False);
     
     interface RingBufferConfig configifc;
  