anchor.diff:  		tlp.eof = True;
   		tlp.be = 16'hFFFF;
   		tlp.hit = hitReg;
  -		tlpFifo.enq(tlp);
  +		tlpOutFifo.enq(tlp);
   	    endmethod
   	endinterface: read
       endinterface: axi
  
positive.code:     interface Axi3Master#(32,32,4,12) axi;
  endinterface
  
  module mkAxiEngine#(PciId my_id)(AxiEngine);
      Reg#(Bit#(7)) hitReg <- mkReg(0);
      FIFO#(TLPMemoryIO3DWHeader) readHeaderFifo <- mkFIFO;
      FIFO#(TLPMemoryIO3DWHeader) readDataFifo <- mkFIFO;
      FIFO#(TLPMemoryIO3DWHeader) writeHeaderFifo <- mkFIFO;
      FIFO#(TLPMemoryIO3DWHeader) writeDataFifo <- mkFIFO;
      Reg#(TLPLength) readLengthReg <- mkReg(0);
      FIFO#(TLPData#(16)) tlpFifo <- mkFIFO;
      interface Put tlp_in;
          method Action put(TLPData#(16) tlp) if (readLengthReg == 0);
  	    $display("AxiEngine.put tlp=%h", tlp);
  	    TLPMemoryIO3DWHeader h = unpack(tlp.data);
  	    hitReg <= tlp.hit;
  	    readLengthReg <= h.length << 2;
  	    TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);
  	    if (hdr_3dw.format == MEM_READ_3DW_NO_DATA)
  	        readHeaderFifo.enq(hdr_3dw);
  
negative.code: 		completion.tag = truncate(id);
  		completion.bytecount = 4;
  		completion.reqid = hdr.reqid;
  		completion.loweraddr = truncate(hdr.addr << 2); // getLowerAddr(hdr.addr, hdr.firstbe);
  		completion.data = data;
  	        TLPData#(16) tlp = defaultValue;
  		tlp.data = pack(completion);
  