anchor.diff:  	interface Axi3SlaveRead read;
   	   method Action readAddr(Bit#(40) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
   				  Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) arid);
  -               TLPMemory4DWHeader hdr_4dw = defaultValue;
  -	       hdr_4dw.format = MEM_READ_4DW_NO_DATA;
  -	       hdr_4dw.tag = truncate(arid);
  -	       hdr_4dw.reqid = my_id;
  -	       hdr_4dw.nosnoop = SNOOPING_REQD;
  -	       hdr_4dw.addr = addr[40-1:2];
  -	       hdr_4dw.length = 1;
  -	       hdr_4dw.firstbe = 4'hf;
  -	       hdr_4dw.lastbe = 0;
   	       TLPData#(16) tlp = defaultValue;
  -	       tlp.data = pack(hdr_4dw);
   	       tlp.sof = True;
   	       tlp.eof = True;
   	       tlp.hit = 7'h00;
  -	       tlp.be = 16'hffff;
  +	       TLPLength tlplen = 2*(extend(burstLen) + 1);
  +	       if (True || use4dwReg) begin
  +		   TLPMemory4DWHeader hdr_4dw = defaultValue;
  +		   hdr_4dw.format = MEM_READ_4DW_NO_DATA;
  +		   hdr_4dw.tag = truncate(arid);
  +		   hdr_4dw.reqid = my_id;
  +		   hdr_4dw.nosnoop = SNOOPING_REQD;
  +		   hdr_4dw.addr = addr[40-1:2];
  +		   hdr_4dw.length = tlplen;
  +		   hdr_4dw.firstbe = 4'hf;
  +		   hdr_4dw.lastbe = 4'hf;
  +		   tlp.data = pack(hdr_4dw);
  +		   tlp.be = 16'hffff;
  +	       end
  +	       else begin
  +		   TLPMemoryIO3DWHeader hdr_3dw = defaultValue;
  +		   hdr_3dw.format = MEM_READ_3DW_NO_DATA;
  +		   hdr_3dw.tag = truncate(arid);
  +		   hdr_3dw.reqid = my_id;
  +		   hdr_3dw.nosnoop = SNOOPING_REQD;
  +		   hdr_3dw.addr = addr[32-1:2];
  +		   hdr_3dw.length = tlplen;
  +		   hdr_3dw.firstbe = 4'hf;
  +		   hdr_3dw.lastbe = 4'hf;
  +		   tlp.data = pack(hdr_3dw);
  +		   tlp.be = 16'hfff0;
  +	       end
   	       tlpOutFifo.enq(tlp);
              endmethod: readAddr
   	   method ActionValue#(Bit#(64)) readData();
  -	       let hdr = completionFifo.first;
  -	       completionFifo.deq;
  -	       return extend(hdr.data);
  +	      let data_v = completionMimo.first;
  +	      completionMimo.deq(2);
  +	      completionTagMimo.deq(2);
  +              Bit#(64) v;
  +	      v[31:0] = byteSwap(data_v[0]);
  +	      v[63:32] = byteSwap(data_v[1]);
  +	      return extend(v);
              endmethod: readData
   	   method Bit#(1) last();
   	       return 1;
              endmethod: last
   	   method Bit#(12) rid();
  -	       return zeroExtend(completionFifo.first.tag);
  +	       return zeroExtend(completionTagMimo.first[0]);
              endmethod: rid
   	   // method Action readResponse(Bit#(2) responseCode);
   	endinterface: read
       endinterface: slave
      method Bool tlpOutFifoNotEmpty() = tlpOutFifo.notEmpty;
  +   interface Reg use4dw = use4dwReg;
   endmodule: mkAxiSlaveEngine
   
   typedef enum {
  
positive.code:    interface Reg#(Bool) axiEnabled;
     interface Reg#(Bool) pipeliningEnabled;
     interface Reg#(Bool) byteSwap;
     interface Reg#(Bit#(4)) numPortals;
     interface Reg#(Bit#(32)) axiTestEnabled;
     interface Reg#(Bit#(32)) addrLowerWord;
  
negative.code:        csr.tlpTracing <= False;
     endrule
     rule connectEnables;
        dispatcher.axiEnabled <= csr.axiEnabled;
        portalEngine.pipeliningEnabled <= csr.pipeliningEnabled;
        portalEngine.byteSwap <= csr.byteSwap;
        axiSlaveEngine.use4dw <= csr.use4dw;
     endrule
  
     // connect the sub-components to each other
  