anchor.diff:     interface ReadOnly#(Bit#(32)) interruptData;
   
      interface Reg#(Bool) tlpTracing;
  -   interface Reg#(Bool) axiEnabled;
  +   //jca interface Reg#(Bool) axiEnabled;
      interface Reg#(Bool) byteSwap;
      interface Reg#(Bool) use4dw;
      interface Reg#(Bit#(4)) numPortals;
  
positive.code:          3: return fromInteger(major_rev);
           4: return pack(buildVersion);
           5: return pack(epochTime);
           6: return {23'd0,pack(is_board_number_assigned),4'd0,pack(board_number)};
           7: return {24'd0,fromInteger(bytes_per_beat)};
           8: return board_content_id[31:0];
           9: return board_content_id[63:32];
           64: return 0;
           512: return 0;
           513: return 0;
           514: return 0;
           515: return 0;
  	 768: return 0;
  	 769: return 0;
  	 770: return 0;
  	 771: return 0;
  	 772: return 0;
  	 773: return 0;
  	 774: return tlpSeqnoReg;
  	 775: return (tlpTracingReg ? 1 : 0);
  	 776: return tlpDataBramResponseSlice(0);
  
negative.code:             4109: msix_entry[3].addr_hi  <= update_dword(msix_entry[3].addr_hi, be, dword);
              4110: msix_entry[3].msg_data <= update_dword(msix_entry[3].msg_data, be, dword);
              4111: if (be[0] == 1) msix_entry[3].masked <= unpack(dword[0]);
              //******************************** end of area referenced from xilinx_x7_pcie_wrapper.v
           endcase
        endaction
     endfunction: wr_csr
  