anchor.diff:     // ----------------------------------------------------------------
      // Non-architectural state, for this model
   
  -   //FIFOF#(Decoded_Instr)   fifo_f2e    <- mkPipelineFIFOF;
  -   //FIFOF#(Exec2Wb_t)       fifo_e2w    <- mkPipelineFIFOF;
  -   Reg#(Maybe#(Decoded_Instr)) rg_f2e  <- mkDReg(tagged Invalid);
  -   Reg#(Maybe#(Exec2Wb_t))     rg_e2w  <- mkDReg(tagged Invalid);
  +   FIFOF#(Decoded_Instr)   fifo_f2e    <- mkPipelineFIFOF;
  +   FIFOF#(Exec2Wb_t)       fifo_e2w    <- mkPipelineFIFOF;
   
      // ----------------------------------------------------------------
      // Scoreboard map
  -   Ehr#(2, Bool)  rg_scoreGPRs[numRegs];
  +   Reg#(Bool)  rg_scoreGPRs[numRegs][2];
      for(Integer i = 0; i < numRegs; i = i + 1)
  -      rg_scoreGPRs[i] <- mkEhr(False);
  +      rg_scoreGPRs[i] <- mkCReg(2, False);
   
      // ----------------------------------------------------------------
      // Read a CSR
  
positive.code: // BSV project imports
  
  import ISA_Decls :: *;    // Instruction encodings
  import Ehr       :: *;
  
  // ================================================================
  // Memory interface for CPU
  
negative.code:    // Instruction fetch
     //(* conflict_free="rl_fetch, rl_exec, rl_write_back" *)
     rule rl_fetch(cpu_enabled);
        if (cfg_verbose > 1) $display("[%7d] rl_fetch : Read instruction PC = 0x%08h", csr_cycle, pc);
        memory.imem_req(pc);
  
        let next_pc = fromMaybe(pc + 4, rw_pc.wget);
        pc <= next_pc;
     endrule
  
     // ----------------------------------------------------------------
  