anchor.diff:     Reg#(Bool)     readyReg   <- mkReg(False);
   
      if (valueOf(numRequests) > 0) begin
  -      let readPortal <- mkSharedMemoryRequestPortal(portal, readEngine, writeEngine, sglIdReg, readyReg);
  +      let readPortal <- mkSharedMemoryRequestPortal(portal, readEngine.read_servers[0], writeEngine.write_servers[0], sglIdReg, readyReg);
      end
      if (valueOf(numIndications) > 0) begin
      end
  
positive.code: 
  	 reqTailReg <= tail;
  	 wordCountReg <= truncate(wordCount);
  	 readEngine.readServers[0].request.put(MemengineCmd {sglId: sglIdReg,
  							     base: extend(reqTailReg << 2),
  							     burstLen: 16,
  							     len: wordCount << 2
  							     });
  	 reqState <= MessageHeaderRequested;
        endrule
  
        MIFO#(4,1,4,Bit#(32)) readMifo <- mkMIFO();
        rule demuxwords if (readMifo.enqReady());
  	 let data <- toGet(readEngine.dataPipes[0]).get();
  	 Vector#(2,Bit#(32)) dvec = unpack(data);
  	 let enqCount = 2;
  	 Vector#(4,Bit#(32)) dvec4;
  
negative.code: 	 if (verbose)
  	    $display("updateTail: tail=%d", reqTailReg);
  	 // update the tail pointer
  	 writeEngine.cmdServer.request.put(MemengineCmd {sglId: sglIdReg,
  							 base: 8,
  							 len: 8,
  							 burstLen: 8
  							 });
  	 writeEngine.dataPipe.enq(extend(reqTailReg));
  	 reqState <= Waiting;
        endrule
        rule waiting if (reqState == Waiting);
  	 let done <- writeEngine.cmdServer.response.get();
  	 reqState <= Idle;
        endrule
  
        rule consumeResponse;
  	 let response <- readEngine.cmdServer.response.get();
        endrule
  endmodule
  
  