anchor.diff:  interface HdmiDisplayRequest;
      method Action startFrameBuffer0(Int#(32) base);
      method Action getTransferStats();
  +   method Action setTraceTransfers(Bool trace);
   endinterface
   interface HdmiDisplayIndication;
      method Action transferStarted(Bit#(32) count);
  
positive.code:    Reg#(Bit#(32)) transferCycles <- mkReg(0);
     Reg#(Bit#(48)) transferSumOfCycles<- mkReg(0);
  
     rule notransfer if (referenceReg matches tagged Invalid);
        vsyncFifo.deq();
     endrule
     rule startTransfer if (referenceReg matches tagged Valid .reference);
        memreadEngine.start(reference, 0, (1080*1920)*4, 64);
        hdmiDisplayIndication.transferStarted(transferCount);
        transferCycles <= 0;
        vsyncFifo.deq();
     endrule
  
negative.code:     HdmiGenerator hdmiGen <- mkHdmiGenerator(defaultClock, defaultReset,
  					     vsyncPulse, hdmiInternalIndication, clocked_by hdmi_clock, reset_by hdmi_reset);
     
     SyncFIFOIfc#(Bit#(64)) synchronizer <- mkSyncFIFO(32, defaultClock, defaultReset, hdmi_clock);
     rule doGet;
        let v = mrFifo.first();
        mrFifo.deq();
        synchronizer.enq(v);
     endrule
     Reg#(Bit#(1)) evenOdd <- mkReg(0, clocked_by hdmi_clock, reset_by hdmi_reset);
     Reg#(Vector#(2,Bit#(32))) doublePixelReg <- mkReg(unpack(0), clocked_by hdmi_clock, reset_by hdmi_reset);
     rule doPut; // if (mimo.enqReadyN(2));
        Vector#(2,Bit#(32)) doublePixel = doublePixelReg;
        let pixel = doublePixel[evenOdd];
        if (evenOdd == 0) begin
  	 doublePixel = unpack(synchronizer.first);
  	 synchronizer.deq;
  	 pixel = doublePixel[0];
        end
        evenOdd <= evenOdd + 1;
        hdmiGen.request.put(pixel);
     endrule      
  
     FIFOF#(Bool) vsyncFifo <- mkFIFOF();
  