anchor.diff:        interface Put writeReq;
   	 method Action put(MemRequest#(addrWidth) req);
   	    req_aws.enq(MemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag});
  -	    req_aw_fifo.enq(?);
   	    if (req.burstLen > 1) $display("**** \n\n mkMemSlaveMux.writeReq len=%d \n\n ****", req.burstLen);
   	    //$display("mkMemSlaveMux.writeReq addr=%h selWidth=%d aw=%d psel=%h", req.addr, valueOf(selWidth), valueOf(aw), psel(req.addr));
   	    ws.enq(truncate(psel(req.addr)));
  
positive.code:       return a[(port_sel_low-1):0];
     endfunction
  
     FIFO#(MemRequest#(aw)) req_ars <- mkSizedFIFO(1);
     FIFO#(void) req_ar_fifo <- mkSizedFIFO(1);
     FIFO#(Bit#(TLog#(numSlaves))) rs <- mkFIFO();
  
     FIFO#(MemRequest#(aw)) req_aws <- mkSizedFIFO(1);
     FIFO#(void) req_aw_fifo <- mkSizedFIFO(1);
     FIFO#(Bit#(TLog#(numSlaves))) ws <- mkFIFO();
  
     rule req_aw;
        let req <- toGet(req_aws).get;
  
negative.code:       interface Put readReq;
  	 method Action put(MemRequest#(addrWidth) req);
  	    req_ars.enq(MemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag});
  	    //$display("mkMemSlaveMux.readReq addr=%h aw=%d psel=%h", req.addr, valueOf(aw), psel(req.addr));
  	    if (req.burstLen > 1) $display("**** \n\n mkMemSlaveMux.readReq len=%d \n\n ****", req.burstLen);
  	    rs.enq(truncate(psel(req.addr)));
  