anchor.diff:      endrule
   
   
  -    ToBit32#(Heard$Response) heard$responseFifo <- mkToBit32();
       rule heard$axiSlaveRead if (axiSlaveReadAddrFifo.first[14] == 0 && 
                                            axiSlaveReadAddrFifo.first[13:8] == heard$Offset);
           axiSlaveReadAddrFifo.deq;
  
positive.code: import FIFO::*;
  import Zynq::*;
  import PcieToAxiBridge::*;
  
  
  
  typedef struct {
  
negative.code:         end
          axiSlaveReadDataFifo.enq(v);
      endrule
     rule readybits1;
        readyQueue.readyBits[1] <= heard2$responseFifo.notEmpty();
     endrule
  
      rule putFailed$axiSlaveRead if (axiSlaveReadAddrFifo.first[14] == 0 && 
                                           axiSlaveReadAddrFifo.first[13:8] == putFailed$Offset);
          axiSlaveReadAddrFifo.deq;
  