anchor.diff:        endinterface
         interface Get readData;
   	 method ActionValue#(MemData#(dataWidth)) get();
  -	    let b <- fifoReadAddrGenerator.addrBeat.get();
  -	    let v = 0;
  -	    if (b.addr[7:0] == 0)
  -	       v <- toGet(methodPipe).get();
  -	    else if (b.addr[7:0] == 4)
  -	       v = extend(pack(methodPipe.notEmpty()));
  -	    //$display("mkPipeOutMemSlave.readData.get addr=%h data=%h", b.addr, data);
  -	    return MemData { data: v, tag: b.tag, last: b.last };
  +	    let d <- toGet(fifoReadDataFifo).get();
  +	    return d;
   	 endmethod
         endinterface
      endinterface
  
positive.code: 	 interface Put writeReq = ctrlWriteAddrGenerator.request;
  	 interface Put writeData;
  	    method Action put(MemData#(dataWidth) d);
  	       let b <- ctrlWriteAddrGenerator.addrBeat.get();
  	       //$display("mkCtrl.writeData addr=%h data=%h last=%d", b.addr, d.data, b.last);
  	       let v = d.data;
  	       let addr = b.addr;
  	       if (addr == 'h000)
  		  noAction;
  	       if (addr == 'h004)
  		  interruptEnableReg <= v[0] == 1'd1;
  	       if (b.last)
  		  ctrlWriteDoneFifo.enq(b.tag);
  	    endmethod
  	 endinterface
  	 interface Get writeDone;
  
negative.code: module mkPortalCtrlMemSlave#(Vector#(numIndications, PipeOut#(Bit#(dataWidth))) indicationPipes)(PortalCtrlMemSlave#(addrWidth, dataWidth));
     AddressGenerator#(addrWidth,dataWidth) ctrlReadAddrGenerator  <- mkAddressGenerator();
     AddressGenerator#(addrWidth,dataWidth) ctrlWriteAddrGenerator <- mkAddressGenerator();
     FIFO#(MemData#(dataWidth))        ctrlWriteDataFifo <- mkFIFO();
     FIFO#(Bit#(ObjectTagSize))        ctrlWriteDoneFifo <- mkFIFO();
  
      // indication-specific state
  