anchor.diff:  	     Mul#(nrc, nMasters, numReadClients),
   	     Add#(b__, TLog#(nrc), 6),
   	     Add#(c__, TLog#(nwc), 6),
  -	     Add#(TLog#(TDiv#(dataWidth, 8)), d__, BurstLenSize)
  +	     Add#(TLog#(TDiv#(dataWidth, 8)), d__, BurstLenSize),
  +             Add#(e__, addrWidth, 64),
  +             Add#(f__, 12, addrWidth),
  +             Add#(1, f__, g__)
   	     );
   
  -   MemServer#(PhysAddrWidth,dataWidth,nMasters) reader <- mkMemServerR(indication,  readClients, mmus);
  -   MemServer#(PhysAddrWidth,dataWidth,nMasters) writer <- mkMemServerW(indication, writeClients, mmus);
  -   
  -   function PhysMemMaster#(PhysAddrWidth,dataWidth) mkm(Integer i) = (interface PhysMemMaster#(PhysAddrWidth,dataWidth);
  +   MemServer#(addrWidth,dataWidth,nMasters) reader <- mkMemServerR(indication,  readClients, mmus);
  +   MemServer#(addrWidth,dataWidth,nMasters) writer <- mkMemServerW(indication, writeClients, mmus);
  +   
  +   function PhysMemMaster#(addrWidth,dataWidth) mkm(Integer i) = (interface PhysMemMaster#(addrWidth,dataWidth);
   								 interface PhysMemReadClient read_client = reader.masters[i].read_client;
   								 interface PhysMemWriteClient write_client = writer.masters[i].write_client;
   							      endinterface);
  
positive.code: module mkSimpleMemServer#(Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,
  			  Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  			  MemServerIndication indication,
  			  MMUIndication mmuIndication)(SimpleMemServer#(PhysAddrWidth, dataWidth,nMasters))
     provisos (Max#(nMasters,numReadClients,numReadClientsActual),
  	     Add#(numReadClients,numReadClientsNull,numReadClientsActual),
  	     Mul#(a__, nMasters, numReadClientsActual),
  
negative.code: 	
  module mkMemServerW#(MemServerIndication indication,
  		     Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,
  		     Vector#(numMMUs,MMU#(addrWidth)) mmus)
     (MemServer#(addrWidth, dataWidth, nMasters))
     
     provisos (Add#(1,a__,dataWidth),
  	     Mul#(TDiv#(dataWidth, 8), 8, dataWidth),
  	     Mul#(nwc, nMasters, numWriteClients),
  	     Add#(b__, TLog#(nwc), 6),
               Add#(c__, addrWidth, 64),
               Add#(d__, 12, addrWidth),
               Add#(1, d__, e__)
  	     );
  
     FIFO#(Bit#(32))   addrReqFifo <- mkFIFO;
  