anchor.diff:     interface rx_clkout = out_rx_clk;
   
      interface Status status;
  -      method Vector#(np, Bit#(1)) rx_ready();
  -         Vector#(np, Bit#(1)) ret_val = map(getBit(rst.rx.ready), genVector);
  -         return ret_val;
  -      endmethod
  -
  -      method Vector#(np, Bit#(1)) tx_ready();
  -         Vector#(np, Bit#(1)) ret_val = map(getBit(rst.tx.ready), genVector);
  -         return ret_val;
  -      endmethod
  -
  -      method Vector#(np, Bit#(1)) pll_locked();
  -         Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.pll.locked), genVector);
  -         return ret_val;
  -      endmethod
  -
  -      method Vector#(np, Bit#(1)) rx_is_lockedtodata();
  -         Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtodata), genVector);
  -         return ret_val;
  -      endmethod
  -
  -      method Vector#(np, Bit#(1)) rx_is_lockedtoref();
  -         Vector#(np, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtoref), genVector);
  +      method Vector#(PortNum, Bit#(1)) rx_ready();
  +         Vector#(PortNum, Bit#(1)) ret_val = map(getBit(rst.rx_r.eady), genVector);
  +         return ret_val;
  +      endmethod
  +
  +      method Vector#(PortNum, Bit#(1)) tx_ready();
  +         Vector#(PortNum, Bit#(1)) ret_val = map(getBit(rst.tx_r.eady), genVector);
  +         return ret_val;
  +      endmethod
  +
  +      method Vector#(PortNum, Bit#(1)) pll_locked();
  +         Vector#(PortNum, Bit#(1)) ret_val = map(getBit(xcvr.pll.locked), genVector);
  +         return ret_val;
  +      endmethod
  +
  +      method Vector#(PortNum, Bit#(1)) rx_is_lockedtodata();
  +         Vector#(PortNum, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtodata), genVector);
  +         return ret_val;
  +      endmethod
  +
  +      method Vector#(PortNum, Bit#(1)) rx_is_lockedtoref();
  +         Vector#(PortNum, Bit#(1)) ret_val = map(getBit(xcvr.rx.is_lockedtoref), genVector);
            return ret_val;
         endmethod
      endinterface
  
positive.code:    endrule
  
     /* connect all three components */
     Vector#(np, B2C1) tx_clk;
     Vector#(np, B2C1) rx_clk;
     for (Integer i=0; i < valueOf(np); i=i+1) begin
        tx_clk[i] <- mkB2C1();
        rx_clk[i] <- mkB2C1();
     end
  
     rule out_pma_clk;
        for (Integer i=0; i < valueOf(np); i=i+1) begin
           tx_clk[i].inputclock(xcvr.tx.pma_clkout[i]);
           rx_clk[i].inputclock(xcvr.rx.pma_clkout[i]);
        end
     endrule
  
     Vector#(np, Clock) out_tx_clk;
     Vector#(np, Clock) out_rx_clk;
     for (Integer i=0; i< valueOf(np); i=i+1) begin
        out_tx_clk[i] = tx_clk[i].c;
        out_rx_clk[i] = rx_clk[i].c;
     end
  
     Vector#(np, Wire#(Bit#(1))) rx_serial_wires <- replicateM(mkDWire(0));
  
     function Bit#(1) getBit(Bit#(n) data, Integer i);
        return data[i];
  
negative.code:    endinterface
  endmodule
  
  endpackage: EthPma
  