anchor.diff:  	 //$display("burstLen=%d dreqFifo.first.last=%d last=%d\n", burstLen, dreqFifo.first.last, last);
         end
         Bit#(TLog#(numTags)) tt = truncate(response_tag);
  -      read_buffer.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last}, address:{tt,truncate(burstLen)}});
  +      readBufferBram.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: otag, last: last}, address:{tt,truncate(burstLen)}});
         if (last) begin
   	 tag_gen.returnTag(truncate(response_tag));
         end
  
positive.code:       interface Put readData;
  	 method Action put(MemData#(dataWidth) response);
  	    readDataPipelineFifo.enq(response);
  	    dreqFifos.portA.request.put(BRAMRequest{write:False, address:truncate(response.tag), datain: ?, responseOnWrite: ?});
  	    beatCount <= beatCount+1;
  	 endmethod
        endinterface
  
negative.code:    // stage 1: address validation (latency = 1)
     FIFO#(RRec#(numServers,addrWidth))  reqFifo <- mkFIFO;
     // stage 2: read commands
     BRAM2Port#(Bit#(TLog#(numTags)), DRec#(numServers,addrWidth)) dreqBram <- mkBRAM2Server(defaultValue);
     BRAM2Port#(Bit#(TAdd#(TLog#(numTags),TSub#(BurstLenSize,beatShift))), MemData#(dataWidth)) readBufferBram <- mkBRAM2Server(defaultValue);
     // stage 3: read data 
     FIFO#(MemData#(dataWidth)) readDataPipelineFifo <- mkFIFO;
     
  