anchor.diff:  // prefix of the signals "tx"
   // Hopefully this is what importbvi.py would do
   (* always_ready, always_enabled *)
  -interface Par_tx;
  +interface Par_txo;
      method Action data_p(Bit#(8) v);
      method Action data_n(Bit#(8) v);
      method Action frame_p(Bit#(1) v);
      method Action frame_n(Bit#(1) v);
      method Action lclk_p(Bit#(1) v);
      method Action lclk_n(Bit#(1) v);
  +endinterface
  +
  +interface Par_txi;
      method Bit#(1) wr_wait_p();
      method Bit#(1) wr_wait_n();
      method Bit#(1) rd_wait_p();
  
positive.code:    Reset reset_chip, Reset reset_fpga)(ELink);
     // default_clock clk();
     // default_reset rst();
     input_clock maxiclk(emaxi_aclk) = maxiclk;  // assigns the verilog emaxi_aclk
     input_clock saxiclk(s_axi_aclk) = saxiclk;  // assigns the verilog s_axi_aclk
     input_reset maxiclk_reset() = maxiclk_reset; /* from clock*/
     input_reset saxiclk_reset() = saxiclk_reset; /* from clock*/
  
negative.code: endinterface
  
  (* always_ready, always_enabled *)
  interface Par_rxi;
     method Bit#(8) data_p();
     method Bit#(8) data_n();
     method Bit#(1) frame_p();
     method Bit#(1) frame_n();
     method Bit#(1) lclk_p();
     method Bit#(1) lclk_n();
  endinterface
  
  interface Par_Rxo
     method Action wr_wait_p(Bit#(1) v);
     method Action wr_wait_n(Bit#(1) v);
     method Action rd_wait_p(Bit#(1) v);
  