anchor.diff:          fifo_reset <= fifo_reset_sync.read();
       endrule
   
  -    rule clear_fifo if (sync_reset_inc_ce[2] == 1);
  +    rule clear_fifo if (astate_idle.read() == 1);
           dfifo.clear();
       endrule
       rule setrule;
  -        delaye2.reset(sync_reset_inc_ce[2]);
  +        delaye2.reset(astate_idle.read());
           delaye2.cinvctrl(0);
           delaye2.cntvaluein(0);
           delaye2.ld(0);
  
positive.code: 
  typedef enum { QIdle, QTrain, QOff} QState deriving (Bits,Eq);
  typedef enum { AIdle, ADelay, AWDelay, AEdge, ACEdge, AWait, ACompare, AValid,
       A1Changed, A1Stable, ASecond, AFound, AResetman, AStart, AAlign, ADone } AState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, TrainRotate trainrot)(IserdesDatadeser);
  
negative.code:         master_data.shiftin2(0);
          master_data.oclk(0);
          master_data.oclkb(0);
          master_data.reset(astate_idle.read());
          slave_data.d(0);
          slave_data.bitslip(sync_bitslip);
          slave_data.ce1(1);
  