anchor.diff:              fwsync = dfifo_wren_r;
           else
               fwsync = bvi_fifo_wren_wire;
  +        sric[0] = 0;
           sric[1] = 0;
  -        sric[2] = 0;
  -        iodelay_reset_inc_ce <= sync_reset_inc_ce;
  -        iserdes_bitslip <= sync_bitslip;
  +        //iodelay_reset_inc_ce <= sync_reset_inc_ce;
  +        //iserdes_bitslip <= sync_bitslip;
  +        iodelay_reset_inc_ce <= serbvi.iodelay_reset_inc_ce();
  +        iserdes_bitslip <= serbvi.bitslip();
           if (dstate == DIdle && dreqpipe1 == 1)
               begin
               sric = serbvi.ctrl_reset_inc_ce();
  
positive.code:     //endrule
  
      rule wren_dfifo_rule;
          dfifo.wren(serbvi.fifo_wren_sync());
          //dfifo.wren(fifo_wren_sync);
      endrule
  
      rule serdesrule;
  
negative.code:         master_data.shiftin2(0);
          master_data.oclk(0);
          master_data.oclkb(0);
          master_data.reset(iodelay_reset_inc_ce[2]);
          slave_data.d(0);
          slave_data.bitslip(iserdes_bitslip);
          slave_data.ce1(1);
          slave_data.ce2(1);
          slave_data.ddly(0);
  