anchor.diff:      method Action      wvalid(Bit#(1) v);
   endinterface
   (* always_ready, always_enabled *)
  -interface AxiethbviS_axi_lite;
  -    method Action      clk(Bit#(1) v);
  -    method Action      resetn(Bit#(1) v);
  -endinterface
  -(* always_ready, always_enabled *)
   interface AxiethbviSgmii;
       method Action      rxn(Bit#(1) v);
       method Action      rxp(Bit#(1) v);
  
positive.code:     interface AxiethbviRxuserclk     rxuserclk2;
      interface AxiethbviRxuserclk     rxuserclk;
      interface AxiethbviS_axi     s_axi;
      interface AxiethbviS_axi_lite     s_axi_lite;
      interface AxiStreamSlave#(32)     s_axis_txc;
      interface AxiStreamSlave#(32)     s_axis_txd;
      interface AxiethbviSgmii     sgmii;
  
negative.code:     interface AxiethbviUserclk     userclk;
  endinterface
  import "BVI" axi_ethernet_0 =
  module mkAxiEthBvi#(Clock s_axi_clk, Reset s_axi_reset)(AxiEthBvi);
      default_clock clk();
      default_reset rst();
      input_clock (s_axi_lite_clk) = s_axi_clk;
      input_reset (s_axi_lite_resetn) = s_axi_reset;
      interface AxiethbviAxi     axi;
          method rxd_arstn(axi_rxd_arstn) enable((*inhigh*) EN_axi_rxd_arstn);
          method rxs_arstn(axi_rxs_arstn) enable((*inhigh*) EN_axi_rxs_arstn);
  