anchor.diff:     FIFOF#(BRAMRequest#(Bit#(LineBufferAddrSize),Int#(16))) lineBufferRequestFifo <- mkFIFOF();
      FIFOF#(Int#(16))                                        lineBufferResponseFifo <- mkFIFOF();
      FIFOF#(BRAMRequest#(Bit#(LineBufferAddrSize),Int#(16))) lineBufferWriteFifo <- mkFIFOF();
  -   FIFOF#(BRAMRequest#(Bit#(LineBufferAddrSize),Int#(16))) topBufferRequestFifo <- mkFIFOF();
  -   FIFOF#(Int#(16))                                        topBufferResponseFifo <- mkFIFOF();
  -   FIFOF#(BRAMRequest#(Bit#(LineBufferAddrSize),Int#(16))) topBufferWriteFifo <- mkFIFOF();
  +   BRAM2Port#(Bit#(LineBufferAddrSize),Int#(16)) topBuffer <- mkBRAM2Server(defaultValue);
   
      FIFOF#(InnerProdParam) innerProdRequestFifo <- mkFIFOF();
      FIFOF#(InnerProdResponse) innerProdResponseFifo <- mkFIFOF();
  
positive.code:    let ipDriver <- mkIPDriver();
     mkConnection(ipDriver.lineBufferReadClient, lineBuffer.portB);
     mkConnection(ipDriver.lineBufferWriteClient, lineBuffer.portA);
     mkConnection(ipDriver.topBufferReadClient, topBuffer.portB);
     mkConnection(ipDriver.topBufferWriteClient, topBuffer.portA);
     mkConnection(ipDriver.innerProdRequest, toPipeIn(inputFifo));
     mkConnection(toPipeOut(bramFifo), ipDriver.innerProdResponse);
  
  
negative.code:    rule topBufferReadRule;
        let addr <- toGet(topBufferReadIterator.pipe).get();
        if (verbose) $display("topBufferReadRule: addr=%h", addr);
        topBuffer.portB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: addr, datain: 0});
     endrule
     rule topBufferResponseRule;
        let v <- topBuffer.portB.response.get();
        writeDataGearbox.enq(vec(pack(v)));
     endrule
     Reg#(Bit#(32)) wrrCount <- mkReg(0);
     rule writeReqRule;
        let offset <- toGet(colWriteBackIterator.pipe).get();
  