anchor.diff:  
      interface PhysMemReadServer read_server;
         interface Put readReq;
  -	 method Action put(PhysMemRequest#(busAddrWidth) req);
  +	 method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);
               if (verbose) $display("%d axiSlave.read.readAddr %h bc %d", cycles, req.addr, req.burstLen);
   	    readAddrGenerator.request.put(req);
   	 endmethod
  
positive.code:    FIFO#(Bool)     readLastFifo <- mkFIFO();
     AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
     AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
     Bool verbose = False;
  
      Reg#(Bit#(32)) cycles      <- mkReg(0);
      rule count;
  
negative.code: import MemTypes::*;
  import AddressGenerator::*;
  import BRAM::*;
  import Memory::*;
  
  
  module mkPhysMemToBram#(BRAMServer#(Bit#(bramAddrWidth), Bit#(busDataWidth)) br) (PhysMemSlave#(busAddrWidth, busDataWidth))
  