anchor.diff:  module mkAxiDMAWriteInternal#(Integer numRequests, Vector#(numWriteClients, DMAWriteClient#(dsz)) writeClients,
   			      DMAIndication dmaIndication)(AxiDMAWriteInternal#(dsz,dbytes))
      provisos(Add#(1,a__,dsz),
  -	    Mul#(dbytes,8,dsz),
  -	    Add#(b__, TAdd#(dsz, 8), 128));
  +	    Mul#(dbytes,8,dsz));
      SGListMMU sgl <- mkSGListMMU();
      
      FIFO#(DMAAddressRequest) lreqFifo <- mkPipelineFIFO();
  
positive.code: 		       Vector#(numWriteClients, DMAWriteClient#(dsz)) writeClients)
     (AxiDMAServer#(dsz,dbytes))
     provisos (Add#(1,a__,dsz),
  	     Mul#(dbytes,8,dsz),
  	     Add#(dsz, b__, 120));
  
     AxiDMAReadInternal#(dsz,dbytes) reader <- mkAxiDMAReadInternal(numRequests, readClients, dmaIndication);
     AxiDMAWriteInternal#(dsz,dbytes) writer <- mkAxiDMAWriteInternal(numRequests, writeClients, dmaIndication);
  
negative.code: module mkAxiDMAReadInternal#(Integer numRequests, Vector#(numReadClients, DMAReadClient#(dsz)) readClients,
  			     DMAIndication dmaIndication)(AxiDMAReadInternal#(dsz,dbytes))
     provisos(Add#(1,a__,dsz),
  	    Mul#(dbytes,8,dsz));
     
     SGListMMU sgl <- mkSGListMMU();
     
  