anchor.diff:     
      rule writeDoneComp0;
         let tag <- tag_gen.complete;
  -      respFifos.portB.request.put(BRAMRequest{write:False, address:tag});
  +      respFifos.portB.request.put(BRAMRequest{write:False, address:tag, responseOnWrite: ?, datain: ?});
      endrule
      
      rule writeDoneComp1;
  
positive.code:       interface Put readData;
  	 method Action put(MemData#(dataWidth) response);
  	    readDataPipelineFifo.enq(response);
  	    dreqFifos.portA.request.put(BRAMRequest{write:False, address:truncate(response.tag)});
  	    beatCount <= beatCount+1;
  	 endmethod
        endinterface
  
negative.code:    
     rule complete_burst0;
        let tag <- tag_gen.complete;
        dreqFifos.portB.request.put(BRAMRequest{write:False, address:tag, responseOnWrite: ?, datain: ?});      
        compFifo1.enq(tag);
     endrule
     
  