anchor.diff:     			else if (sglid_outofrange(req.sglId))
   			   dmaErrorFifo.enq(DmaError { errorType: DmaErrorSGLIdOutOfRange_w, pref: req.sglId });
      			else if (stopv[req.tag[5:4]] == False) begin
  -   			   lreqFifo.enq(LRec{req:req, client:fromInteger(i)});
  +   			   clientRequest.enq(LRec{req:req, client:fromInteger(i)});
      			   mmus[mmusel].request.put(ReqTup{id:truncate(req.sglId),off:req.offset});
      			end
   		     endmethod
   		  endinterface
   		  interface Put writeData = toPut(clientWriteData[i]);
   		  interface Get writeDone;
  -		     method ActionValue#(Bit#(MemTagSize)) get if (respFifos_buff.first.client == fromInteger(i));
  -			respFifos_buff.deq;
  -			return respFifos_buff.first.orig_tag;
  +		     method ActionValue#(Bit#(MemTagSize)) get if (clientResponse.first.client == fromInteger(i));
  +			clientResponse.deq;
  +			return clientResponse.first.orig_tag;
   		     endmethod
   		  endinterface
   	       endinterface);
  
positive.code:       interface Put writeDone;
  	 method Action put(Bit#(MemTagSize) resp);
  	    tag_gen.returnTag(truncate(resp));
  	    if (debug) $display("mkMemWriteInternal::writeDone: resp=%d", resp);
  	 endmethod
        endinterface
     endinterface
  
negative.code: 
     rule complete_burst0;
        let tag <- tag_gen.complete;
        serverProcessing.portB.request.put(BRAMRequest{write:False, address:tag, datain: ?, responseOnWrite: ?});
        serverTag.enq(tag);
        if(verbose) $display("mkMemReadInternal::complete_burst0 %h", tag);
     endrule
     
     rule complete_burst1a if (compCountReg==0);
        let drq <- serverProcessing.portB.response.get;
        let req_burstLen = drq.req_burstLen;
        let client = drq.client;
        let cnt = req_burstLen >> beat_shift;
        let tag <- toGet(serverTag).get;
        if(killv[drq.req_tag[5:4]] == False) begin
  	 clientSelect.enq(extend(client));
  	 clientData.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        end
        compCountReg <= cnt-1;
        compTagReg <= tag;
        compClientReg <= client;
        compTileReg <= drq.req_tag[5:4];
        if(verbose) $display("mkMemReadInternal::complete_burst1a %h", client);
     endrule
  
     rule complete_burst1b if (compCountReg > 0);
        let cnt = compCountReg;
        let tag = compTagReg;
        let client = compClientReg;
        if(killv[compTileReg] == False) begin
  	 clientSelect.enq(extend(client));
  	 clientData.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});
        end
        compCountReg <= cnt-1;
        if(verbose) $display("mkMemReadInternal::complete_burst1b count %h", compCountReg);
     endrule
           
     rule checkMmuResp;
        let req = clientRequest.first.req;
        let client = clientRequest.first.client;
        let physAddr <- mmus[req.sglId[31:16]].response.get;
        let rename_tag <- tag_gen.getTag;
        clientRequest.deq();
        serverRequest.enq(RRec{req:req, pa:physAddr, client:client, rename_tag:extend(rename_tag)});
        if (verbose) $display("mkMemReadInternal::checkMmuResp: client=%d, rename_tag=%d", client,rename_tag);
        if (verbose) $display("mkMemReadInternal::mmuResp %d %d", client, cycle_cnt-last_mmuResp);
        last_mmuResp <= cycle_cnt;
     endrule
     
     rule read_data;
        let response <- toGet(serverData).get();
        Bit#(MemTagSize) response_tag = response.tag;
        let drq <- serverProcessing.portA.response.get;
        let otag = drq.req_tag;
        let burstLen = burstReg;
        let first =    firstReg;
  