anchor.diff:     endinterface
   endmodule
   
  +module mkPhysMemToBramBE#(BRAMServerBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), n) br) (PhysMemSlave#(busAddrWidth, busDataWidth))
  +   provisos(Add#(a__, bramAddrWidth, busAddrWidth)
  +           ,Add#(n, 0, ByteEnableSize)
  +           ,Div#(busDataWidth, 8, b__)
  +           ,Add#(`DataBusWidth, 0, busDataWidth)
  +           );
  +
  +   FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();
  +   FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();
  +   FIFO#(Bool)     readLastFifo <- mkFIFO();
  +   FIFOF#(Bit#(ByteEnableSize)) readByteEnableFifo <- mkFIFOF;
  +   FIFOF#(Bit#(ByteEnableSize)) writeByteEnableFifo <- mkFIFOF;
  +
  +   AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();
  +   AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();
  +   let verbose = False;
  +
  +    Reg#(Bit#(32)) cycles      <- mkReg(0);
  +    rule count;
  +       cycles <= cycles + 1;
  +    endrule
  +
  +   rule read_req;
  +      let addrBeat <- readAddrGenerator.addrBeat.get();
  +      let addr = addrBeat.addr;
  +      let tag = addrBeat.tag;
  +      let burstCount = addrBeat.bc;
  +      readTagFifo.enq(tag);
  +      readLastFifo.enq(addrBeat.last);
  +      Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));
  +      br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:regFileAddr, datain:?});
  +      if (verbose) $display("%d read_server.readData (a) %h %d last=%d", cycles, addr, burstCount, addrBeat.last);
  +   endrule
  +
  +   interface PhysMemReadServer read_server;
  +      interface Put readReq;
  +	 method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);
  +            if (verbose) $display("%d read_server.readAddr %h bc %d fbe %x lbe %x", cycles, req.addr, req.burstLen, req.firstbe, req.lastbe);
  +	    readAddrGenerator.request.put(req);
  +            readByteEnableFifo.enq(reqLastByteEnable(req));
  +	 endmethod
  +      endinterface
  +      interface Get readData;
  +	 method ActionValue#(MemData#(busDataWidth)) get();
  +   	    let tag = readTagFifo.first;
  +	    readTagFifo.deq;
  +	    readLastFifo.deq;
  +            let data <- br.response.get;
  +            let byteEnable <- toGet(readByteEnableFifo).get();
  +            let newdata = updateDataWithMask(0, data, byteEnable);
  +            if (verbose) $display("%d read_server.readData (b) %h, %h", cycles, data, newdata);
  +            return MemData { data: newdata, tag: tag, last: readLastFifo.first };
  +	 endmethod
  +      endinterface
  +   endinterface
  +   interface PhysMemWriteServer write_server;
  +      interface Put writeReq;
  +	 method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);
  +	    writeAddrGenerator.request.put(req);
  +            writeByteEnableFifo.enq(reqLastByteEnable(req));
  +            if (verbose) $display("%d write_server.writeAddr %h bc %d fbe %x lbe %x", cycles, req.addr, req.burstLen, req.firstbe, req.lastbe);
  +	 endmethod
  +      endinterface
  +      interface Put writeData;
  +	 method Action put(MemData#(busDataWidth) resp);
  +	    let addrBeat <- writeAddrGenerator.addrBeat.get();
  +	    let addr = addrBeat.addr;
  +	    Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));
  +            let byteEnable <- toGet(writeByteEnableFifo).get();
  +            br.request.put(BRAMRequestBE{writeen:byteEnable, responseOnWrite:False, address:regFileAddr, datain:resp.data});
  +            if (verbose) $display("%d write_server.writeData %h %h %d", cycles, addr, resp.data, addrBeat.bc);
  +            if (addrBeat.last)
  +               writeTagFifo.enq(addrBeat.tag);
  +	 endmethod
  +      endinterface
  +      interface Get writeDone;
  +	 method ActionValue#(Bit#(6)) get();
  +	    writeTagFifo.deq;
  +            return writeTagFifo.first;
  +	 endmethod
  +      endinterface
  +   endinterface
  +endmodule
  +
  
positive.code:    endinterface
     interface PhysMemWriteServer write_server;
        interface Put writeReq;
  	 method Action put(PhysMemRequest#(busAddrWidth) req);
  	    writeAddrGenerator.request.put(req);
              if (verbose) $display("%d write_server.writeAddr %h bc %d", cycles, req.addr, req.burstLen);
  	 endmethod
  
negative.code: 
     interface PhysMemReadServer read_server;
        interface Put readReq;
  	 method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);
              if (verbose) $display("%d axiSlave.read.readAddr %h bc %d", cycles, req.addr, req.burstLen);
  	    readAddrGenerator.request.put(req);
  	 endmethod
  