anchor.diff:      Integer exeSendBypassPort = 0;
       Integer finishSendBypassPort = 1;
   
  +    // train BP in a new cycle
  +    FIFO#(AluExeTrainBP) trainBPQ <- mkFIFO;
  +
   `ifdef PERF_COUNT
       // performance counters
       Count#(Data) exeRedirectBrCnt <- mkCount(0);
  
positive.code:     // speculation
      Maybe#(SpecTag) spec_tag;
  } AluExeToFinish deriving(Bits, Eq, FShow);
  
  // XXX currently ALU/Br should not have any exception, so we don't have cause feild above
  // TODO FIXME In future, if branch target is unaligned to 4 bytes, we may have exception
  
negative.code:             inIfc.redirect_action(x.controlFlow.nextPc, x.spec_tag, x.tag);
              // must be a branch, train branch predictor
              doAssert(x.iType == Jr || x.iType == Br, "only jr and br can mispredict");
              trainBPQ.enq(AluExeTrainBP {
                  pc: x.controlFlow.pc,
                  nextPc: x.controlFlow.nextPc,
                  iType: x.iType,
                  taken: x.controlFlow.taken,
                  dpTrain: x.dpTrain,
                  mispred: True
              });
  `ifdef PERF_COUNT
              // performance counter
              if(inIfc.doStats) begin
  