anchor.diff:     (* always_ready *)
      method Bool write_tlp();
      (* always_ready *)
  -   method Bool axi_read_tlp();
  -   (* always_ready *)
  -   method Bool axi_write_tlp();
  -   (* always_ready *)
  -   method Bool axi_tlp();
  -   (* always_ready *)
      method Bool completion_tlp();
  +
  +   interface Reg#(Bool) axiEnabled;
   
   endinterface: TLPDispatcher
   
  
positive.code:    BRAM1Port#(Bit#(7), TimestampedTlpData) tlpDataBram1Port <- mkBRAM1Server(bramCfg);
     Reg#(TimestampedTlpData) tlpDataBramResponse <- mkReg(unpack(0));
     Vector#(6, Reg#(Bit#(32))) tlpDataScratchpad <- replicateM(mkReg(0));
     Reg#(Bit#(32)) tlpOutCountReg <- mkReg(0);
     Reg#(Bit#(32)) axiReadCountReg <- mkReg(0);
     Reg#(Bit#(32)) axiWriteCountReg <- mkReg(0);
     Reg#(Bit#(32)) axiTlpCountReg <- mkReg(0);
  
negative.code: 
     method Bool read_tlp       = is_read;
     method Bool write_tlp      = is_write;
     method Bool completion_tlp = is_completion;
     interface Reg axiEnabled = axiEnabledReg;
  endmodule: mkTLPDispatcher
  
  // Multiple sources of TLP packets must all share the PCIe bus. There
  