anchor.diff:     // Inputs
      // clkin_100, saxi.aclk, maxi.aclk, reset, 
      saxi.aresetn,
  -   maxi.aresetn, misc.csysreq, rxi.data_p, rxi.data_n, rxi.frame_p,
  -   rxi.frame_n, rxi.lclk_p, rxi.lclk_n, txi.wr_wait_p, txi.wr_wait_n,
  +   maxi.aresetn, misc.csysreq, rx.data_p, rx.data_n, rx.frame_p,
  +   rx.frame_n, rx.lclk_p, rx.lclk_n, txi.wr_wait_p, txi.wr_wait_n,
      txi.rd_wait_p, txi.rd_wait_n, maxi.awready, saxi.awid,
      saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,
      saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,
  
positive.code:    
     
  schedule (
     misc.csysack, misc.cactive, misc.reset_chip, misc.reset_fpga, txo.data_p, txo.data_n,
     txo.frame_p, txo.frame_n, txo.lclk_p, txo.lclk_n, rxo.wr_wait_p,
     rxo.wr_wait_n, rxo.rd_wait_p, rxo.rd_wait_n, rxi.cclk_p,
     rxi.cclk_n, maxi.awid, maxi.awaddr, maxi.awlen, maxi.awsize,
     maxi.awburst, maxi.awlock, maxi.awcache, maxi.awprot,
     maxi.awvalid, saxi.awready, maxi.wid, maxi.wdata, maxi.wstrb,
     maxi.wlast, maxi.wvalid, saxi.wready, maxi.bready, saxi.bid,
  
negative.code:    // Inputs
     // clkin_100, saxi.aclk, maxi.aclk, reset, 
     saxi.aresetn,
     maxi.aresetn, misc.csysreq, rx.data_p, rx.data_n, rx.frame_p,
     rx.frame_n, rx.lclk_p, rx.lclk_n, txi.wr_wait_p, txi.wr_wait_n,
     txi.rd_wait_p, txi.rd_wait_n, maxi.awready, saxi.awid,
     saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,
     saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,
  