anchor.diff:          astate <= as;
       endrule
       rule afsmdelay_rule if (bvi_resets_reg.read() != 0 && astate == ADelay);
  -        end_handshake.deq();
  +        serdes_end.deq();
           gencounter <= 15;
           astate <= AWDelay;
       endrule
  
positive.code:         master_data.shiftin2(0);
          master_data.oclk(0);
          master_data.oclkb(0);
          master_data.reset(iodelay_reset_inc_ce[2]);
          slave_data.d(0);
          slave_data.bitslip(sync_bitslip);
          slave_data.ce1(1);
  
negative.code:         astate <= as;
      endrule
      rule afsmwait_rule if (bvi_resets_reg.read() != 0 && astate == AWait);
          serdes_end.deq();
          let as = astate;
          let gc = gencounter;
          if (gencounter >= 'h8000)
  