anchor.diff:      interface Put#(TLPData#(16))   tlp_in;
       interface Get#(TLPData#(16))   tlp_out;
       interface Axi3Master#(32,32,4,12) portal;
  -    interface Reg#(Bool)           pipeliningEnabled;
       interface Reg#(Bool)           byteSwap;
       interface Reg#(Bool)           interruptRequested;
       interface Reg#(Bit#(64))       interruptAddr;
  
positive.code: 
     Reg#(Bool) tlpTracingReg <- mkReg(False);
     Reg#(Bool) axiEnabledReg <- mkReg(False);
     Reg#(Bool) pipeliningEnabledReg <- mkReg(False);
     Reg#(Bool) byteSwapReg <- mkReg(False);
     Reg#(Bool) use4dwReg <- mkReg(True);
     Reg#(Bit#(4)) numPortalsReg <- mkReg(1);
  
negative.code: 	 784: return zeroExtend(pack(max_payload_bytes));
  	 785: return 0;
  	 786: return 0;
  	 787: return 0;
  	 788: return axiEnabledReg ? 1 : 0;
  	 789: return tlpDataBramRdAddrReg;
  	 790: return msix_enabled ? 1 : 0;
  