anchor.diff:  
       rule afsminit_rule if (bvi_resets_reg.read() == 0);
           start_handshake.clear();
  -        //busy_align_i <= 0;
           ctrl_reset_inc_ce <= 3'b100;
           ctrl_bitslip <= 0;
           ctrl_samplein_i <= 3'b000;
  
positive.code:     Reg#(HState)  hstate <- mkReg(HIdle);
      Reg#(Bit#(6)) hcounter <- mkReg(0);
      Reg#(Bit#(1)) edge_intor_reg <- mkReg(0);
      SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
      Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
      Wire#(Bit#(1)) this_align_busy_wire <- mkDWire(0);
      FIFO#(Bit#(1)) this_start_align_reg <- mkFIFO();
  
negative.code:     rule handhigh1_rule if (bvi_resets_reg.read() != 0 && hstate == HHigh && dackint.read() == 1);
          hcounter <= 0;
          hstate <= HLow;
      endrule
      rule handlow_rule if (bvi_resets_reg.read() != 0 && hstate == HLow);
          if (dackint.read() == 0 || hcounter >= 'h20)
  