anchor.diff:     Reg#(Bit#(40)) bufferfirst <- mkReg(0);
      Reg#(Bit#(40)) bufferlast <- mkReg(0);
      Reg#(Bit#(40)) buffermask <- mkReg(0);
  +   Reg#(Bool) hwenable <- mkReg(False);
      
      interface RingBufferConfig configifc;
      method Action set(Bit#(2) regist, Bit#(40) addr);
  
positive.code:       else if (regist == 1) bufferend <= addr;
        else if (regist == 2) bufferfirst <= addr;
        else if (regist == 3) bufferlast <= addr;
        else buffermask <= addr;
     endmethod
     
     method Bit#(40) get(Bit#(2) regist);
        if (regist == 0) return (bufferbase);
        else if (regist == 1) return (bufferend);
        else if (regist == 2) return (bufferfirst);
        else return(bufferlast);
     endmethod
     endinterface
  
  
negative.code:    return (((bufferfirst + 64) & buffermask) != bufferlast);
     endmethod
  
     method Action push(UInt#(8) num);
     bufferfirst <= (bufferfirst + num) & buffermask;
     endmethod
  
     method Action pop(UInt#(8) num);
     bufferlast <= (bufferlast + num) & buffermask;
     endmethod
   
     interface Reg bufferFirst = bufferFirst;
     interface Reg bufferLast = bufferlast;
     interface Reg enable = hwenable;
  
  endmodule
  