anchor.diff:     endinterface
   
      interface Axi3ReadClient m_axi_read;
  -      method ActionValue#(Axi3ReadRequest#(40,12)) address() if (!debugReg);
  +      method ActionValue#(Axi3ReadRequest#(40,12)) address();
   	 let req = reqFifo.first();
   	 reqFifo.deq();
   	 let physAddr = paFifo.first();
  
positive.code: module mkAxiDMAWriteInternal#(Integer numRequests, Vector#(numWriteClients, DMAWriteClient#(dsz)) writeClients,
  			      DMAIndication dmaIndication)(AxiDMAWriteInternal#(dsz,dbytes))
     provisos(Add#(1,a__,dsz),
  	    Mul#(dbytes,8,dsz));
     SGListMMU sgl <- mkSGListMMU();
     
     FIFO#(DMAAddressRequest) reqFifo <- mkFIFO();
     FIFO#(DMAAddressRequest) dreqFifo <- mkSizedFIFO(numRequests);
     FIFO#(Bit#(40))        paFifo     <- mkFIFO();
  
negative.code:       debugReg <= False;
     endrule
  
     rule loadChannel if (valueOf(numWriteClients) > 0 && !isConfiguring);
        DMAAddressRequest req = unpack(0);
        if (valueOf(numWriteClients) > 0)
  	 req <- writeClients[selectReg].writeReq.get();
        $display("dmawrite.loadChannel activeChan=%d handle=%h addr=%h burst=%h debugReq=%d", selectReg, req.handle, req.address, req.burstLen, debugReg);
  
        lreqFifo.enq(req);
        chanFifo.enq(selectReg);
        sgl.addrReq(truncate(req.handle),req.address);
     endrule
     
     rule checkSglResp if (!debugReg);
        let physAddr <- sgl.addrResp();
        let req = lreqFifo.first();
        lreqFifo.deq();
        if (physAddr == 0) begin
  	 // squash request
  	 $display("dmaWrite: badAddr handle=%d addr=%h physAddr=%h", req.handle, req.address, physAddr);
  	 dmaIndication.badAddr(req.handle, req.address);
        end
        else begin
  	 reqFifo.enq(req);
  	 paFifo.enq(physAddr);
        end
     endrule
  
     interface ConfigureSglist configure;
        method Action page(Bit#(32) tabsel, Bit#(32) off, Bit#(40) addr) if (isConfiguring);
  	 sgl.page(truncate(tabsel), off, addr);
        endmethod
  
        method Action readSglist(Bit#(32) pref, Bit#(40) addr) if (!debugReg);
  	 debugReg <= True;
  	 sgl.addrReq(truncate(pref), addr);
        endmethod
        method Action configuring(Bool c);
  	 isConfiguring <= c;
        endmethod
     endinterface
  
     interface DMAWrite write;
        method ActionValue#(DmaDbgRec) dbg();
  