anchor.diff:          slave_data.oclkb(0);
           slave_data.reset(iodelay_reset_inc_ce[2]);
           iserdes_data <= dout;
  -        serbvi.dataout(dout);
  +        serbvi.dataout(iserdes_data);
           dfifo.di({6'b0,dout});
       endrule
  -    //rule bozodata_rule;
  -        //serbvi.dataout(iserdes_data);
  -    //endrule
   
       rule wren_dfifo_rule;
           dfifo.wren(fifo_wren_sync_wire);
  
positive.code: 
      Clock defaultClock <- exposeCurrentClock();
      Reset defaultReset <- exposeCurrentReset();
      Iserdesbvi serbvi <- mkIserdesbvi(serdes_clock);
      FIFO18 dfifo <- mkFIFO18(serdes_clock);
      IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {
          cinvctrl_sel: "FALSE", delay_src: "IDATAIN",
  
negative.code:         sync_reset_inc_ce <= sric;
          sync_bitslip <= sbs;
          fifo_wren_sync <= fwsync;
      endrule
      rule dackint_rule;
          serbvi.dackint(dackint);
      endrule
  
  