anchor.diff:     interface doubleReset = epReset125;
         
   endmodule
  -
  +`endif
   
   `ifndef BSIM
   (* no_default_clock, no_default_reset *)
  
positive.code: `endif
  endinterface
  
  module mkPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pci_sys_reset_n)(PcieHostTop);
  
  `ifdef BSIM
     let dc <- exposeCurrentClock;
     let dr <- exposeCurrentReset;
     Clock epClock125 = dc;
  
negative.code:       put_tlp(foo);
        //$display("to_bdpi");
     endrule
     interface Clock tepClock125 = epClock125;
     interface Reset tepReset125 = epReset125;
     interface PcieHost tpciehost = pciehost;
  endmodule
  `else // not BSIM
  (* synthesize, no_default_clock, no_default_reset *)
  module mkPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pci_sys_reset_n)(PcieHostTop);
     Clock sys_clk_200mhz <- mkClockIBUFDS(sys_clk_p, sys_clk_n);
     Clock sys_clk_200mhz_buf <- mkClockBUFG(clocked_by sys_clk_200mhz);
     Clock pci_clk_100mhz_buf <- mkClockIBUFDS_GTE2(True, pci_sys_clk_p, pci_sys_clk_n);
  