anchor.diff:  
       Reg#(Data) sptbr_csr    = concatReg2(asid_field, sptbr_ppn_field);
   
  +    // TODO: Support 32-bit ISA
       Reg#(Data) scycle_csr   = readOnlyReg(mcycle_csr + mscycle_delta_csr);
       Reg#(Data) stime_csr    = readOnlyReg(mtime_csr + mstime_delta_csr);
       Reg#(Data) sinstret_csr = readOnlyReg(minstret_csr + msinstret_delta_csr);
  
positive.code:     // Supervisor
      Reg#(Data) sstatus_csr =  concatReg20(
              sd_field,
              readOnlyReg(0),
              vm_field,
              readOnlyReg(4'b0),
              readOnlyReg(1'b0), pum_field, readOnlyReg(1'b0), // memory privilege
  
negative.code:     Reg#(Data) fcsr_csr   = addWriteSideEffect(zeroExtendReg(concatReg2(frm_field, fflags_field)), fs_field._write(2'b11));
  
      // User Timers and Counters
      // TODO: support 32-bit ISA
      Reg#(Data) cycle_csr   = readOnlyReg(mcycle_csr + mucycle_delta_csr);
      Reg#(Data) time_csr    = readOnlyReg(mtime_csr + mutime_delta_csr);
      Reg#(Data) instret_csr = readOnlyReg(minstret_csr + muinstret_delta_csr);
  