anchor.diff:     Bool write_allowed = !write_operation_in_progress && space_for_read;
   
      Reg#(Bool) tlpTracingReg <- mkReg(False);
  +   Reg#(Bool) axiEnabledReg <- mkReg(False);
  +   Reg#(Bool) pipeliningEnabledReg <- mkReg(False);
      Reg#(Bit#(32)) tlpSeqnoReg <- mkReg(0);
      Reg#(Bit#(32)) tlpDataBramRdAddrReg <- mkReg(0);
      Reg#(Bit#(32)) tlpDataBramWrAddrReg <- mkReg(0);
  
positive.code: 	 784: return 0;
  	 785: return 0;
  	 786: return 0;
  	 787: return 0;
  	 788: return tlpOutCountReg;
  	 789: return tlpDataBramRdAddrReg;
  	 790: return axiReadCountReg;
  	 791: return axiWriteCountReg;
  
negative.code: 	        readHeaderFifo.enq(hdr_3dw);
  	    else
  	        writeHeaderFifo.enq(hdr_3dw);
              if (!pipeliningEnabledReg)
  	        busyReg <= True;
  	endmethod
      endinterface: tlp_in
      interface Get tlp_out = toGet(tlpOutFifo);
      interface Axi3Master axi;
  	interface Axi3MasterWrite write;
  