anchor.diff:          let sbs = 0;
     
           dc = dc - 1;
  -        dreqpipe0 <= serbvi.itemreq();
  +        //dreqpipe0 <= serbvi.itemreq();
  +        dreqpipe0 <= item_req_wire.read();
           dreqpipe1 <= dreqpipe0;
           dfifo_reset_r <= serbvi.ctrl_fifo_reset();
           fifo_reset <= dfifo_reset_r;
  
positive.code: endmodule: mkFIFO18
  
  typedef enum { DIdle, DValid, DLow} DState deriving (Bits,Eq);
  
  module mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,
      Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, Bit#(1) rden)(IserdesDatadeser);
  
negative.code:     Reg#(Bit#(1)) iserdes_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(3)) iodelay_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
      Reg#(Bit#(10)) ctrl_data <- mkReg(0);
      Reg#(HState)  hstate <- mkReg(HIdle);
      Reg#(Bit#(6)) hcounter <- mkReg(0);
      SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  
      rule reset_clock_rule;
          bvi_resets_reg.send(bvi_reset_reg);
      endrule
  
      rule wrensyncr_rule if (bvi_reset_reg == 0);
          dfifo_wren_r <= 0;
  