anchor.diff:  
   endmodule
   
  -module mkBRAMWriteClient#(BRAMServer#(bramIdx,Bit#(busWidth)) br)(BRAMWriteClient#(bramIdx,busWidth))
  -   
  -   provisos(Eq#(bramIdx),
  -	    Bits#(bramIdx, a__),
  +module mkBRAMWriteClient#(BRAMServer#(bramIdx,d) br)(BRAMWriteClient#(bramIdx,busWidth))
  +   
  +   provisos(Bits#(d,dsz),
  +	    Div#(busWidth,dsz,nd),
  +	    Mul#(nd,dsz,busWidth),
  +	    Add#(1,a__,nd),
  +	    Add#(1, b__, TMul#(2, nd)),
  +	    Add#(nd, c__, TMul#(2, nd)),
  +	    Eq#(bramIdx),
  +	    Bits#(bramIdx, d__),
   	    Ord#(bramIdx),
   	    Arith#(bramIdx));
  +
  +   Clock clk <- exposeCurrentClock;
  +   Reset rst <- exposeCurrentReset;
   
      FIFO#(void) f <- mkSizedFIFO(1);
      Reg#(bramIdx) n <- mkReg(0);
  
positive.code:    Reg#(DmaPointer) ptr <- mkReg(0);
     Reg#(Bit#(DmaOffsetSize)) woff <- mkReg(0);
     Reg#(Bit#(DmaOffsetSize)) wbase <- mkReg(0);
     
     let writeFifo <- mkFIFOF;
     MemwriteEngine#(busWidth) we <- mkMemwriteEngine(writeFifo);
     let bus_width_in_bytes = fromInteger(valueOf(busWidth)/8);
     
  
negative.code:    endrule
  
     rule bramResp;
        d rv <- br.response.get;
        gb.enq(cons(pack(rv), nil));
     endrule
     
     rule loadReq(i < n);
  