anchor.diff:     method Action wren(Bit#(1) wren);
      method Bit#(data_width) dout();
      method Action rden(Bit#(1) rden);
  +   method Bit#(9) wrcount();
  +   method Bit#(9) rdcount();
   endinterface
   
   import "BVI" FIFO_DUALCLOCK_MACRO =
  
positive.code:    method wren(WREN) enable ((*inhigh*)EN_wren);
     method DO dout();
     method rden(RDEN) enable ((*inhigh*)EN_rden);
     schedule (empty, full, dout, din, wren, rden) CF (empty, full, dout, din, wren, rden);
  endmodule
  
  module mkSizedBRAMFIFOF#(Integer m)(FIFOF#(t))
  
negative.code:    Wire#(Bit#(1)) wrenWire <- mkDWire(0);
     Vector#(TDiv#(sizet,72),Wire#(Bit#(72))) dinWires <- replicateM(mkDWire(0));
  
     for (Integer i = 0; i < valueOf(TDiv#(sizet,72)); i = i+1) begin
        Reg#(Bit#(9)) rdcount <- mkReg(0);
        Reg#(Bit#(9)) wrcount <- mkReg(0);
        rule enables;
  	 fifos[i].rden(rdenWire);
  	 fifos[i].wren(wrenWire);
        endrule
        rule counts;
  	 rdcount <= fifos[i].rdcount();
  	 wrcount <= fifos[i].wrcount();
        endrule
     end
  
     function Bool fifoNotEmpty(Integer i); return fifos[i].empty == 0; endfunction
     function Bool fifoNotFull(Integer i); return fifos[i].full == 0; endfunction
  