anchor.diff:        endmethod
         method Action din(Bit#(1) v) if (countreg > 0);
   	 countreg <= countreg - 1;
  -         Bit#(awidth) newshiftreg = { v, shiftreg[valueOf(awidth)-1:1] };
  +	 Bit#(awidth) newshiftreg = { v, shiftreg[valueOf(awidth)-1:1] };
   	 shiftreg <= newshiftreg;
  -         if (countreg == 1) begin
  +	 if (countreg == 1) begin
   	    resultFifo.enq(unpack(newshiftreg));
   	    selreg <= 1;
   	 end
         endmethod
  -   interface Clock clk = spiClock;
  +      interface Clock clock = defaultClock;
  +      interface Clock invertedClock = clockInverter.slowClock;
      endinterface: pins
      interface clock = clockInverter.slowClock;
      interface reset = spiReset;
  
positive.code:     method Bit#(1) dout();
      method Bit#(1) sel();
      method Action din(Bit#(1) v);
     // inverted clock
     interface Clock clk; 
  endinterface: SpiPins
  
  interface SPI#(type a);
  
negative.code: 
  module mkSpiShifter(SPI#(a)) provisos(Bits#(a,awidth),Add#(1,awidth1,awidth),Log#(awidth,logawidth));
  
     Clock defaultClock <- exposeCurrentClock;
     ClockDividerIfc clockInverter <- mkClockInverter;
     Clock spiClock = clockInverter.slowClock;
     Reset spiReset <-  mkAsyncResetFromCR(2, clockInverter.slowClock);
  