anchor.diff:     rule rl_wdata;
         let mds <- toGet(dramWriteGearbox).get();
         function Bit#(DataBusWidth) md_data(Integer i); return mds[i].data; endfunction
  -      Vector#(4, Bit#(DataBusWidth)) data = genWith(md_data);
  +      Vector#(BusRatio, Bit#(DataBusWidth)) data = genWith(md_data);
         ddr3Controller.slave.resp_write.put(Axi4WriteData {
   	 data: pack(data),
   	 byteEnable: maxBound,
  
positive.code:       let sglId <- toGet(readReqFifo).get();
        we.writeServers[0].request.put(MemengineCmd { sglId: sglId,
  						   base: 0,
  						   burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,DataBusWidth))),
  						   len: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),
  						   tag: 0
  						   });
        ddr3re.readServers[0].request.put(MemengineCmd { sglId: 0,
  						      base: 0,
  						      burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,DataBusWidth))),
  						      len: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),
  						      tag: 0
  						      });
     endrule
  
negative.code:    FIFOF#(Bit#(32))   writeReqFifo <- mkFIFOF();
     FIFOF#(Bit#(32))   readReqFifo <- mkFIFOF();
  
     Gearbox#(1,BusRatio,MemData#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);
     SyncFIFOIfc#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkSyncFIFO(4, clock, reset, ddr3Controller.uiClock);
     SyncFIFOIfc#(Axi4WriteResponse#(6)) bfifo <- mkSyncFIFO(4, ddr3Controller.uiClock, ddr3Controller.uiReset, clock);
     mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);
  