anchor.diff:      Reg#(Bit#(6)) hcounter <- mkReg(0);
       Reg#(Bit#(1)) edge_intor_reg <- mkReg(0);
       SyncBitIfc#(Bit#(1)) item_req_wire <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  +    Reg#(Bit#(1)) this_aligned_reg <- mkReg(0);
  +    Reg#(Bit#(1)) this_start_align_reg <- mkReg(0);
  +    Reg#(Bit#(16)) serdes_counter <- mkReg(0);
  +    Reg#(QState)  qstate <- mkReg(QIdle);
   
       rule trainrot_rule;
           serbvi.train0(trainrot[0]);
  
positive.code:         serbvi.train8(trainrot[8]);
          serbvi.train9(trainrot[9]);
      endrule
  
      rule reset_clock_rule;
          bvi_resets_reg.send(bvi_reset_reg);
  
negative.code:             fwsync = bvi_fifo_wren_wire;
          fifo_wren_sync.send(fwsync);
          iodelay_reset_inc_ce <= sync_reset_inc_ce;
      endrule
  
      rule clkdiv_rule if (bvi_reset_reg != 0);
  