anchor.diff:  
      // RC.
      Reg#(DWCount) rg_dwcount <- mkRegU(clocked_by pcie_ep.user_clk, reset_by user_reset_n);
  -
  -   rule rl_rc_header (fAxiRc.first.sop);
  +   Reg#(Bool) even <- mkReg(True, clocked_by pcie_ep.user_clk, reset_by user_reset_n);
  +
  +   rule rl_rc_header (fAxiRc.first.sop && even);
         RCDescriptor rc_desc = unpack(fAxiRc.first.data [95:0]);
  -      Bit#(32) data = fAxiRc.first.data[128+32-1:128];
  +      // RC descriptor always 96 bytes with first data word in bits 127:96                                                                                            
  +      Bit#(32) data = fAxiRc.first.data[127:96] | 32'hbeef0000;
         TLPData#(16) tlp16 = convertRCDescriptorToTLP16(rc_desc, data);
         rg_dwcount <= (rc_desc.dwcount == 0) ? 0 : rc_desc.dwcount - 1;
         frc.enq(tlp16);
  -      fAxiRc.deq;
  -   endrule
  -
  -   rule rl_rc_data ((!(fAxiRc.first.sop)) && (rg_dwcount != 0));
  +      let e = False;
  +      if (rc_desc.dwcount == 0 || rc_desc.dwcount == 1) begin
  +        fAxiRc.deq;
  +        e = True;
  +      end
  +      even <= e;
  +   endrule
  +
  +   rule rl_rc_data ((!even || !(fAxiRc.first.sop)) && (rg_dwcount != 0));
         Bit#(16) be16;
         case (rg_dwcount)
            1: be16 = 16'hF000;
  
positive.code:       rq_last_be <= last_be;
        fAxiRq.enq(AxiStRq {data: zeroExtend(pack(rq_desc)), //FIXME:
                         last: frq_tlps.first.eof,
                         keep: 8'hFF,
                         first_be: first_be,
                         last_be: last_be});
        frq_tlps.deq;
  
negative.code:          3: be16 = 16'hFFF0;
           default: be16 = 16'hFFFF;
        endcase
        let last = (rg_dwcount <= 4);
        let data = (even) ? fAxiRc.first.data[127:0]: fAxiRc.first.data[255:128];
        TLPData#(16) tlp16 = TLPData{sof: False,
                                     eof: last,
                                     hit: 0,
                                     be: be16,
                                     data: pack(data)};
        frc.enq(tlp16);
        if (last || !even)
           fAxiRc.deq;
        even <= (last) ? True : !even;
     endrule
  
     Reg#(DWCount) cc_dwcount <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);
  