anchor.diff:  import BRAM           :: *;
   import FIFOF          :: *;
   import GetPut         :: *;
  +import Connectable    :: *;
   import PCIE           :: *;
   import Clocks         :: *;
   import PcieTracer     :: *;
  
positive.code:       readResponseFifo.enq(MemData { data: data, tag: beat.tag, last: beat.last });
     endrule
  
     rule writeDataRule;
        let beat <- csrWag.addrBeat.get();
        let addr = beat.addr;
  
negative.code: 	    775: tlpdata.tlpTracing <= (dword != 0) ? True : False;
  
  	    768: begin
  		    bramRequestFifo.enq(BRAMRequest{ write: False, responseOnWrite: False, address: bramMuxRdAddrReg, datain: ?});
  		    bramMuxRdAddrReg <= bramMuxRdAddrReg + 1;
  		 end
  	    792: tlpdata.pcieTraceBramWrAddr <= truncate(dword);
  