anchor.diff:     // connect_bd_net -net tx_ifg_delay_1 [get_bd_ports tx_ifg_delay] [get_bd_pins eth_mac/tx_ifg_delay]
   
   
  -   interface m_axis_rxd = buffer.axi_str_rxd;
  -   //interface m_axis_rxs = buffer.axi_str_rxs;
  -   interface s_axis_txd = buffer.axi_str_txd;
  -   //interface s_axis_txc = buffer.axi_str_txc;
  +   interface m_axis_rxd = trimodemac.rx_axis_mac;
  +   interface s_axis_txd = trimodemac.tx_axis_mac;
  +   interface rx = trimodemac.rx;
  +   interface tx = trimodemac.tx;
      interface s_axi = trimodemac.s_axi;
      interface mac   = trimodemac.mac;
   
  
positive.code: 
  import GetPut::*;
  import Clocks::*;
  import Connectable::*;
  import AxiBits::*;
  import AxiStream::*;
  import AxiEthBufferBvi::*;
  import TriModeEthMacBvi::*;
  import GigEthPcsPmaBvi::*;
  import AxiEth1000BaseX::*;
  
  interface AxiEthSubsystem;
     interface AxiStreamMaster#(32) m_axis_rxd;
     interface AxiStreamMaster#(32) m_axis_rxs;
     interface AxiStreamSlave#(32)  s_axis_txd;
     interface AxiStreamSlave#(32)  s_axis_txc;
     interface TrimodeethbviS_axi s_axi;
     interface TrimodeethbviMac mac;
     interface AxiethbviSfp sfp;
     interface AxiethbviMgt mgt;
     interface GigethpcspmabviSignal signal;
     interface GigethpcspmabviMmcm mmcm;
  endinterface
  
  module mkAxiEthBvi#(Clock axis_clk, Clock ref_clk)(AxiEthSubsystem);
     let reset <- exposeCurrentReset;
  
  
negative.code:   // connect_bd_net -net pcs_pma_userclk2_out [get_bd_ports userclk2_out] [get_bd_pins eth_buf/GTX_CLK] [get_bd_pins eth_mac/gtx_clk] [get_bd_pins pcs_pma/userclk2_out]
     Clock gtx_clk = pcs.userclk2.out;
  
     let trimodemac <- mkTriModeMacBvi(gtx_clk, axis_clk, reset, reset, reset, reset);
  
    // connect_bd_intf_net -intf_net eth_mac_gmii [get_bd_intf_pins eth_mac/gmii] [get_bd_intf_pins pcs_pma/gmii_pcs_pma]
     let gmiiConnection <- mkConnection(trimodemac.gmii, pcs.gmii);
  