anchor.diff:     interface PhysMemWriteClient client;
         interface Get writeReq;
   	 method ActionValue#(PhysMemRequest#(addrWidth)) get();
  -	    let req = reqFifo.first.req;
  -	    let physAddr = reqFifo.first.pa;
  -	    let client = reqFifo.first.client;
  -	    let rename_tag = reqFifo.first.rename_tag;
  -	    reqFifo.deq;
  -	    dreqFifo.enq(DRec{req_tag:req.tag, req_burstLen: req.burstLen, client:client, rename_tag:rename_tag, last: (req.burstLen == fromInteger(valueOf(dataWidthBytes))) });
  +	    let req = serverRequest.first.req;
  +	    let physAddr = serverRequest.first.pa;
  +	    let client = serverRequest.first.client;
  +	    let rename_tag = serverRequest.first.rename_tag;
  +	    serverRequest.deq;
  +	    serverProcessing.enq(DRec{req_tag:req.tag, req_burstLen: req.burstLen, client:client, rename_tag:rename_tag, last: (req.burstLen == fromInteger(valueOf(dataWidthBytes))) });
   	    //$display("mkMemWriteInternal::writeReq: client=%d, rename_tag=%d", client,rename_tag);
   	    return PhysMemRequest{addr:physAddr, burstLen:req.burstLen, tag:extend(rename_tag)};
   	 endmethod
  
positive.code:    Reg#(Bit#(TLog#(numTags)))    compTagReg <- mkReg(0);
     Reg#(Bit#(TLog#(TMax#(1,numServers)))) compClientReg <- mkReg(0);
     Reg#(Bit#(2))                 compTileReg <- mkReg(0);
     FIFO#(Bit#(TAdd#(1,TLog#(TMax#(1,numServers))))) compFifo0 <- mkFIFO;
     FIFO#(Bit#(TLog#(numTags)))   compFifo1 <- mkFIFO;
     
     // performance analytics 
     Reg#(Bit#(64)) cycle_cnt <- mkReg(0);
  
negative.code:    endrule
  
     rule checkMmuResp;
        let req = clientRequest.first.req;
        let client = clientRequest.first.client;
        let physAddr <- mmus[req.sglId[31:16]].response.get;
        let rename_tag <- tag_gen.getTag;
        clientRequest.deq();
        serverRequest.enq(RRec{req:req, pa:physAddr, client:client, rename_tag:extend(rename_tag)});
        //if (verbose) $display("mkMemWriteInternal::checkMmuResp: client=%d, rename_tag=%d", client,rename_tag);
        if (verbose) $display("mkMemWriteInternal::mmuResp %d %d", client, cycle_cnt-last_mmuResp);
        last_mmuResp <= cycle_cnt;
     endrule
     
  