anchor.diff:        end
      end
   
  -   rule updateIndWrPtrRdPtr if (state == Idle && readyReg);
  +   rule updateIndRdWrPtr if (state == Idle && readyReg);
         readEngine[0].request.put(
             MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});
         state <= WrPtrRequested;
      endrule
   
  -   rule receiveIndWrPtrRdPtr if (state == WrPtrRequested || state == RdPtrRequested);
  +   rule receiveIndRdWrPtr if (state == WrPtrRequested || state == RdPtrRequested);
         let md <- toGet(readEngine[0].data).get();
         let data = md.data;
         let w0 = data[31:0];
  
positive.code:             state <= Idle;
        end
        if (verbose)
           $display("receiveReqWrPtrRdPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limit);
     endrule
  
     rule requestMessage if (state == RequestMessage);
  
negative.code:             //state <= Idle;
        end
        if (verbose)
           $display("receiveIndRdWrPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d", state, w0, w1, wrPtr, rdPtr, limitReg);
     endrule
  
     rule send64bits;
  