anchor.diff:     // ----------------------------------------------------------------
      // Instruction decode
      (* conflict_free="rl_decode, rl_exec" *)
  -   rule rl_decode(rg_f2d matches tagged Valid .xPC);
  +   rule rl_decode(fifo_d2e.notFull &&& rg_f2d matches tagged Valid .xPC);
         let instr <- memory.imem_resp;
   
         if (cfg_verbose > 1) $display("[%7d] rl_decode: pc = 0x%08h, instr = %h", csr_cycle, xPC, instr);
         Decoded_Instr  decoded = fv_decode(xPC, instr, rf_GPRs);
  -      Decoded_Fields fields  = fv_decode_fields(decoded.instr);
  +
  +      fifo_d2e.enq( decoded );
  +
  +      pc[0] <= fv_fall_through_pc(xPC);
  +   endrule
  +
  +   // ---------------- EXECUTE
  +   // Receive instruction from IMem; handle exception if any, else execute it;
  +
  +   //(* no_implicit_conditions *)
  +   rule rl_exec(fifo_d2e.notEmpty && fifo_e2w.notFull);
  +      let decoded = fifo_d2e.first;
  +
  +      // ----------------------------------------------------------------
  +      // Instruction fields decode
  +      Decoded_Fields fields   = fv_decode_fields(decoded.instr);
   
         // Calculate dependency register
         let score1 = False;
         let score2 = False;
      
         if (decoded.op.rs1 matches tagged Valid .x &&& x != 0)
  -         score1 = rg_scoreGPRs[x][2];
  +         score1 = rg_scoreGPRs[x];
      
         if (decoded.op.rs2 matches tagged Valid .x &&& x != 0)
  -         score2 = rg_scoreGPRs[x][2];
  +         score2 = rg_scoreGPRs[x];
   
         let score_conflict = score1 || score2;
   
         if (cfg_verbose > 2) begin
  -         $write("[%7d] rl_decode: Scoreboard = [", csr_cycle);
  +         $write("[%7d] rl_exec  : Scoreboard = [", csr_cycle);
            for(Integer i = 0; i < numRegs; i = i + 1) begin
  -            $write("%1d, ", rg_scoreGPRs[i][2] ? 1 : 0);
  +            $write("%1d, ", rg_scoreGPRs[i] ? 1 : 0);
            end
            $write("], dst = %d, rs1 = %d, rs2 = %d\n", fields.rd, fields.rs1, fields.rs2);
         end
   
  -      if (!score_conflict) begin
  -         fifo_d2e.enq( decoded );
  -         pc[0] <= fv_fall_through_pc(xPC);
  +      if (decoded.pc != pcEpoch) begin
  +         if (cfg_verbose > 1) $display("[%7d] rl_exec  : STALL Ignore pc = 0x%08h, instr = 0x%08h, epoch = 0x%08h", csr_cycle, decoded.pc, decoded.instr, pcEpoch);
  +         fifo_d2e.deq;
  +      end
  +      else if (score_conflict) begin
  +         if (cfg_verbose > 1) $display("[%7d] rl_exec  : STALL Conflict pc = 0x%08h, instr = 0x%h, Epoch = 0x%08h", csr_cycle, decoded.pc, decoded.instr, pcEpoch);
         end
         else begin
  -         if (cfg_verbose > 1) $display("[%7d] rl_decode: STALL register score conflict replay pc = 0x%08h, instr = 0x%08h", csr_cycle, decoded.pc, decoded.instr);
  -      end
  -   endrule
  -
  -
  -   // ---------------- EXECUTE
  -   // Receive instruction from IMem; handle exception if any, else execute it;
  -
  -   //(* no_implicit_conditions *)
  -   rule rl_exec(fifo_d2e.notEmpty && fifo_e2w.notFull);
  -      let decoded = fifo_d2e.first;
  -      fifo_d2e.deq;
  -
  -      // ----------------------------------------------------------------
  -      // Instruction fields decode
  -      Decoded_Fields fields   = fv_decode_fields(decoded.instr);
  -
  -      if (decoded.pc == pcEpoch) begin
            if (cfg_verbose > 1) $display("[%7d] rl_exec  : pc = 0x%08h, instr = 0x%08h", csr_cycle, decoded.pc, decoded.instr);
   
            // Update dependency flag for $rd
            if (  fields.opcode7 != op_BRANCH
               && fields.opcode7 != op_STORE) begin
  -               rg_scoreGPRs[fields.rd][1] <= True;
  +               rw_scoreGPRsSet.wset(fields.rd);
            end
   
            fa_exec(decoded, fields);
  +         fifo_d2e.deq;
   
            // ---------------- FINISH: increment csr_instret or record explicit CSRRx update of csr_instret
            csr_instret <= csr_instret + 1;
  -      end
  -      else begin
  -         if (cfg_verbose > 1) $display("[%7d] rl_exec  : STALL Ignore pc = 0x%08h, instr = 0x%h, Epoch = 0x%08h", csr_cycle, decoded.pc, decoded.instr, pcEpoch);
         end
      endrule
   
  
positive.code:    // ================================================================
     // The CPU's top-level logic
  
     // ---------------- FETCH
     // Issue instruction request and decode
  
     // ----------------------------------------------------------------
     // Instruction fetch
     //(* conflict_free="rl_fetch, rl_exec, rl_write_back" *)
     rule rl_fetch(cpu_enabled);
        if (cfg_verbose > 1) $display("[%7d] rl_fetch : Read instruction pc = 0x%08h", csr_cycle, pc[2]);
        memory.imem_req(pc[2]);
  
negative.code: 
     // ----------------------------------------------------------------
     // Scoreboard map
     Reg#(Bool)        rg_scoreGPRs[numRegs];
     for(Integer i = 0; i < numRegs; i = i + 1)
        rg_scoreGPRs[i] <- mkReg(False);
     RWire#(RegName)   rw_scoreGPRsSet   <- mkRWire;
     RWire#(RegName)   rw_scoreGPRsReset <- mkRWire;
  
     // ----------------------------------------------------------------
     // Read a CSR
  