anchor.diff:     endinterface
      method Bit#(1) data_out();
         // the output lines are all OR'ed together when going back to the BSCAN core
  -      return shiftReg[0];
  +      if (selectedj.read())
  +          return shiftReg[0];
  +      else
  +          return 0;
      endmethod
   endmodule
  
positive.code: 
     Reg#(Bit#(asz)) addrReg <- mkReg(0);
     Reg#(Bool) readData <- mkReg(False);
  
     Reg#(Bit#(dsz)) shiftReg <- mkReg(0, clocked_by bscan.tck, reset_by bscan.rst);
     SyncBitIfc#(Bit#(dsz)) tojtag <- mkSyncBits(0, defaultClock, defaultReset, bscan.tck, bscan.rst);
     SyncBitIfc#(Bit#(dsz)) fromjtag <- mkSyncBits(0, bscan.tck, bscan.rst, defaultClock, defaultReset);
     SyncPulseIfc startWrite <- mkSyncHandshake(bscan.tck, bscan.rst, defaultClock);
  
     let readNext = startWrite.pulse() || bscan.first();
  
     rule capturer if(bscan.capture() == 1);
         shiftReg <= tojtag.read();
     endrule
     rule shiftrule if (bscan.shift() == 1);
         shiftReg <= { bscan.tdi(), shiftReg[dsz-1:1] };
     endrule
     rule sendwrite if(bscan.sel() == 1 && bscan.update() == 1);
         startWrite.send();
         fromjtag.send(shiftReg);
     endrule
  
     rule addrRule if (readNext);
         let v = fromInteger(0);  // first time USER1, reset address
         if (startWrite.pulse())
             v = addrReg + 1;
         addrReg <= v;
     endrule
     rule readClear;
         readData <= readNext;
     endrule
  
     interface BRAMClient bramClient;
        interface Get request;
  	 method ActionValue#(BRAMRequest#(atype,dtype)) get() if (startWrite.pulse() || readData);
              return BRAMRequest {write:!readData, responseOnWrite:False, address:unpack(addrReg), datain:unpack(fromjtag.read())};
  	 endmethod
        endinterface
  
negative.code:    interface Clock    tck;
     method Bit#(1)     reset();
     method Bit#(1)     capture();
     method Bit#(1)     shift();
     method Bit#(1)     tdi();
     method Action      tdo(Bit#(1) v);
     method Bit#(1)     update();
     method Bool        first();
  endinterface
  module mkBscanTop#(Integer bus)(BscanTop);
     Clock defaultClock <- exposeCurrentClock();
  