anchor.diff:        pcie.pld.clk(c2b.o());
      endrule
   
  -//`ifdef PCIES5_SIM
      (* no_implicit_conditions *)
      rule pcie_rx;
         pcie.rx.in0(rx_in_wires[0]);
  
positive.code:       method sim_ltssmstate(); return pcie.sim.ltssmstate; endmethod
        method sim_pipe_rate(); return pcie.sim.pipe_rate; endmethod
     endinterface
  `endif
  
     interface PcieS5HipCtrl hip_ctrl;
        method test_in = pcie.test.in;
  
negative.code:       method Bit#(8) ko_cpl_spc_header;return pcie.ko.cpl_spc_header;endmethod
     endinterface
  
     interface PcieS5HipPipe hip_pipe;
        method Action rxdata(Vector#(8, Bit#(8)) a);
           writeVReg(rxdata_wires, a);
  