anchor.diff:     Reg#(Bool) route_to_portal <- mkReg(False);
      Reg#(Bool) route_to_axi <- mkReg(False);
   
  -   Reg#(Bool) axiEnabledReg <- mkReg(False);
  +   //jca Reg#(Bool) axiEnabledReg <- mkReg(False);
   
      PulseWire is_read       <- mkPulseWire();
      PulseWire is_write      <- mkPulseWire();
  
positive.code: 	    780: tlpDataScratchpad[4] <= dword;
  	    781: tlpDataScratchpad[5] <= dword;
  
  	    788: axiEnabledReg <= (dword != 0) ? True : False;
  	    789: tlpDataBramRdAddrReg <= dword;
  	    792: tlpDataBramWrAddrReg <= dword;
  	    794: byteSwapReg <= (dword != 0) ? True : False;
  	    796: numPortalsReg <= truncate(dword);
  
              // MSIx table entries
              4096: msix_entry[0].addr_lo  <= update_dword(msix_entry[0].addr_lo, be, (dword & 32'hfffffffc));
              4097: msix_entry[0].addr_hi  <= update_dword(msix_entry[0].addr_hi, be, dword);
  
negative.code:    method Bool read_tlp       = is_read;
     method Bool write_tlp      = is_write;
     method Bool completion_tlp = is_completion;
     //jca interface Reg axiEnabled = axiEnabledReg;
  endmodule: mkTLPDispatcher
  
  // Multiple sources of TLP packets must all share the PCIe bus. There
  