anchor.diff:  
       Reg#(Data) sptbr_csr    = concatReg2(asid_field, sptbr_ppn_field);
   
  +    // TODO: Support 32-bit ISA
       Reg#(Data) scycle_csr   = readOnlyReg(mcycle_csr + mscycle_delta_csr);
       Reg#(Data) stime_csr    = readOnlyReg(mtime_csr + mstime_delta_csr);
       Reg#(Data) sinstret_csr = readOnlyReg(minstret_csr + msinstret_delta_csr);
  
positive.code:     Reg#(Bit#(3)) frm_field     <- mkReg(0);
  
      // vm fields
      Reg#(Bit#(26)) asid_field      <- mkReg(0);
      Reg#(Bit#(38)) sptbr_ppn_field <- mkReg(0);
  
      // trap delegation fields
      Reg#(Bit#(12)) sedeleg_field <- mkReg(0);
  
negative.code:     // Priv 1.9 CSRs
  
      // Machine Timers and Counters
      // TODO: support 32-bit ISA
      Reg#(Data) mcycle_csr   = readOnlyReg(truncate(cycle_counter));
      Reg#(Data) mtime_csr    = readOnlyReg(truncate(mtime));
      Reg#(Data) minstret_csr = readOnlyReg(truncate(instret_counter));
  
      // Machine Counter-Delta Registers
      // TODO: support 32-bit ISA
      Reg#(Data) mucycle_delta_csr   <- mkReg(0);
      Reg#(Data) mutime_delta_csr    <- mkReg(0);
      Reg#(Data) muinstret_delta_csr <- mkReg(0);
  