anchor.diff:  // BSV library imports
   
   import Vector    :: *;
  +import RegFile   :: *;
   import BRAMCore  :: *;
   import FIFOF     :: *;
   
  
positive.code: interface Branch_Predictor_IFC;
     method Action  reset;
  
     method Action  predict_req (WordXL pc);
  
     (* always_ready *)
     method WordXL  predict_rsp (Bool is_i32_not_i16, Instr instr);
  
     method Action bp_train (WordXL   pc,
  			   Bool     is_i32_not_i16,
  
negative.code:       rg_pc <= pc;
     endmethod
  
     // ----------------
     // Response for 'predict_req' from an earlier cycle.
     // Args describe current instruction just now fetched in Fetch stage,
     // and are used to choose RAS actions if any, and size of
     // fall-through PC if no prediction.
  
     method WordXL  predict_rsp (Bool is_i32_not_i16, Instr instr);
        WordXL pred_pc   = bogus_PC;    // default: no prediction, invalid PC
        let    btb_entry = btb_bramcore2.a.read;
  
        // Check if prediction is from RAS pop (JALR returns)
        match { .do_pop, .*, .* } = fn_ras_actions (bogus_PC, is_i32_not_i16, instr);
        if (do_pop)
  	 pred_pc = rg_ras [0];    // Top of RAS (will be popped in bp_train())
  
        // Look for BTB hit if no result from RAS
        if (   (pred_pc == bogus_PC)
  	  && (btb_entry.valid)
  	  && (btb_entry.pc_tag == fn_pc_to_tag (rg_pc))) begin
  	 pred_pc = { btb_entry.predicted_pc, 1'b0 };
        end
  
        // Default prediction: fallthrough
        if (pred_pc == bogus_PC)
  	 pred_pc = rg_pc + (is_i32_not_i16 ? 4 : 2);
  
        return pred_pc;
     endmethod
  
     // ----------------
     // Train BTB and RAS.
     // First 3 args are from current fetch, to train RAS.
     // cf_info arg is from Exec stage (downpipe), from an earlier (older) instruction.
  
     method Action bp_train (WordXL   pc,
  			   Bool     is_i32_not_i16,
  