anchor.diff:     interface PhysMemWriteServer write_server; 
         interface Put writeReq;
            method Action put(PhysMemRequest#(40) req); // if (writeBurstCount == 0);
  -	    let burstLen = req.burstLen >> beat_shift;
  +	    Bit#(WriteDataBurstLenSize) burstLen = truncate(req.burstLen >> beat_shift);
   	    let addr = req.addr;
   	    let awid = req.tag;
   	    let writeIs3dw = False;
  
positive.code:    endrule
  
     Reg#(Bool) writeDataCntAboveThreshold <- mkReg(False);
     rule noheader if (!tlpWriteHeaderFifo.notEmpty());
        writeDataCntAboveThreshold <= False;
     endrule
  
negative.code:    `define AVALON
  `endif
  
  typedef 64 WriteDataMimoSize;
  typedef TAdd#(1,TLog#(WriteDataMimoSize)) WriteDataBurstLenSize;
  module mkMemSlaveEngine#(PciId my_id)(MemSlaveEngine#(buswidth))
     provisos (Div#(buswidth, 8, busWidthBytes),
  	     Div#(buswidth, 32, busWidthWords),
  