anchor.diff:     interface Axi3SlaveWrite write;
         method Action writeAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
   			      Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache,
  -			      Bit#(12) awid);
  +			      Bit#(idWidth) awid);
   	 Bit#(TLog#(numInputs)) wsv = truncate(addr[19:16]); 
   	 inputs[wsv].write.writeAddr(addr,burstLen,burstWidth,burstType,burstProt,burstCache,awid);
   	 ws <= wsv;
  
positive.code:    interface AxiSlaveWrite#(addrWidth, busWidth, busWidthBytes) write;
  endinterface
  
  interface Axi3SlaveRead#(type addrWidth, type busWidth, type busWidthBytes);
     method Action readAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
                            Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) arid);
     method ActionValue#(Bit#(busWidth)) readData();
     method Bit#(1) last();
     method Bit#(12) rid();
     // method Action readResponse(Bit#(2) responseCode);
  endinterface
  
  interface Axi3SlaveWrite#(type addrWidth, type busWidth, type busWidthBytes);
     method Action writeAddr(Bit#(addrWidth) addr, Bit#(4) burstLen, Bit#(3) burstWidth,
                             Bit#(2) burstType, Bit#(3) burstProt, Bit#(4) burstCache, Bit#(12) awid);
     method Action writeData(Bit#(busWidth) data, Bit#(busWidthBytes) byteEnable, Bit#(1) last);
     method ActionValue#(Bit#(2)) writeResponse();
     method ActionValue#(Bit#(12)) bid();
  endinterface
  
  interface Axi3Slave#(type addrWidth, type busWidth, type busWidthBytes);
     interface Axi3SlaveRead#(addrWidth, busWidth, busWidthBytes) read;
     interface Axi3SlaveWrite#(addrWidth, busWidth, busWidthBytes) write;
  endinterface
  
  interface AxiMasterServer#(type addrWidth, type busWidth, type busWidthBytes, type tagSize);
  
negative.code:    endinterface
  endmodule
  
  instance Connectable#(Axi3Master#(addrWidth, busWidth,busWidthBytes,idWidth), Axi3Slave#(addrWidth, busWidth,busWidthBytes,idWidth));
      module mkConnection#(Axi3Master#(addrWidth, busWidth,busWidthBytes,idWidth) m, Axi3Slave#(addrWidth, busWidth,busWidthBytes,idWidth) s)(Empty);
  	Reg#(Bit#(8)) writeBurstCountReg <- mkReg(0);
  	Bool verbose = True;
  
  