anchor.diff:      interface AxiStreamSlave#(32)     s_axis_s2mm;
   endinterface
   import "BVI" axi_dma_0 =
  -module mkAxiDmaBvi#(Clock m_axi_mm2s_aclk, Clock m_axi_s2mm_aclk, Clock m_axi_sg_aclk, Clock s_axi_lite_aclk)(AxiDmaBvi);
  +module mkAxiDmaBvi#(Clock m_axi_mm2s_aclk, Clock m_axi_s2mm_aclk, Clock m_axi_sg_aclk, Clock s_axi_lite_aclk, Reset axi_reset)(AxiDmaBvi);
       default_clock clk();
       default_reset rst();
       input_clock (m_axi_mm2s_aclk) = m_axi_mm2s_aclk;
       input_clock (m_axi_s2mm_aclk) = m_axi_s2mm_aclk;
       input_clock (m_axi_sg_aclk) = m_axi_sg_aclk;
      input_clock (s_axi_lite_aclk) = s_axi_lite_aclk;
  -    interface AxidmabviAxi     axi;
  -        method axi_dma_tstvec dma_tstvec();
  -        method resetn(axi_resetn) enable((*inhigh*) EN_axi_resetn);
  +   input_reset (axi_resetn) = axi_reset;
  +    interface AxidmabviAxiDma     axi_dma;
  +        method axi_dma_tstvec tstvec();
       endinterface
       interface AxidmabviM_axi_mm2s     m_axi_mm2s;
           method m_axi_mm2s_araddr araddr();
  
positive.code:     method araddr = m.araddr;
        method arburst = m.arburst;
        method arcache = m.arcache;
        //method aresetn = no_reset;
        method Bit#(tagWidth)     arid(); return 0; endmethod
        method arlen = m.arlen;
        //method arlock = m.arlock;
  
negative.code: import AxiStream::*;
  
  (* always_ready, always_enabled *)
  interface AxidmabviAxiDma;
      method Bit#(32)     tstvec();
  endinterface
  (* always_ready, always_enabled *)
  interface AxidmabviM_axi_mm2s;
  