anchor.diff:  interface FMComms1Pins;
      interface FMComms1ADCPins adcpins;
      interface FMComms1DACPins dacpins;
  +   method Bit#(1) ad9548_ref_p();
  +   method Bit#(1) ad9548_ref_n();
  +   
   //   (* prefix="" *)
   endinterface
   
  +/* clk1 is the FCLKCLK1 controlled by software */
   
  -module mkPortalTop(PortalTop#(addrWidth,64,FMComms1Pins,1))
  +module mkPortalTop#(Clock clk1)(PortalTop#(addrWidth,64,FMComms1Pins,1))
         provisos(Add#(addrWidth, a__, 52),
   	    Add#(b__, addrWidth, 64),
   	    Add#(c__, 12, addrWidth),
  
positive.code:    interface FMComms1Pins pins;
        interface FMCOmms1ADCPins adcpins = adc.pins;
        interface FMCOmms1ADCPins dacpins = dac.pins;
     endinterface
  endmodule : mkPortalTop
  
negative.code: 	    Add#(e__, c__, 40),
  	    Add#(f__, addrWidth, 40));
  
     Bit#(1) ref_clk_bit <- mkC2B(clk1);
     Wire#(Bit#(1)) ref_clk_wire <- mkDWire(0);
     
     rule senddown_clk;
        ref_clk_wire <= clk;
     endrule
  
     DiffPair ref_clk <- mkxOBUFDS(ref_clk_wire);
  
     FMComms1ADC adc <- mkFMComms1ADC();
     FMComms1DAC dac <- mkFMComms1DAC();
  