anchor.diff:     endmodule
   endinstance
   
  -(* synthesize *)
  -module mkSpiTap#(Bit#(32) id)(SpiTap);
  +module mkSpiReg#(Bit#(32) id)(SpiReg#(a))
  +   provisos(Bits#(a,asize),
  +      Add#(a__, asize, 32));
      Reg#(bit) frameinbit <- mkReg(0);
      Reg#(bit) datainbit <- mkReg(0);
      Wire#(bit) dataoutwire <- mkDWire(0);
      
      Reg#(Bit#(6)) count <- mkReg(0);
      Reg#(Bit#(32)) shifter <- mkReg(0);
  -   Reg#(Bit#(32)) address <- mkReg(0);
  -   Reg#(Bit#(32)) data <- mkReg(0);
  +   Reg#(Bool) addressmatch <- mkReg(False);
  +   Reg#(Bool) iswrite <- mkReg(False);
  +   Reg#(Bit#(asize)) data <- mkReg(0);
      
      rule handleFrame;
         if (frameinbit == 0)
  -	 count <= 0;
  +	 begin
  +            count <= 0;
  +	    addressmatch <= False;
  +	 end
         else
   	 count <= count + 1;
      endrule
  
positive.code:       tmp[31] = datainbit;
        shifter <= tmp;
        if (count == 31) 
  	 address <= tmp;
        if ((count == 63) && (address[31:1] == id[31:1]) && (address[0] == 1))
  	 data <= tmp;
        if ((count[5] == 1) && (address[31:1] == id[31:1]) && (address[0] == 0))
  	 dataoutwire <= data[count & 31];
        else
  	 dataoutwire <= datainbit;
     endrule
  
     interface SpiTapIn in;
     
        method Action frame(bit i );
  	 frameinbit <= i ;
        endmethod
  
        method Action data( bit i );
  	 datainbit <= i;
        endmethod
  
     endinterface
     
     interface SpiTapOut out;
     
        method bit frame();
  	 return frameinbit;
        endmethod
     
        method bit data();
  	 return dataoutwire;
        endmethod
  
     endinterface
  
negative.code:    interface SpiTapOut out;
  endinterface
  
  interface SpiReg#(type a);
     interface SpiTap tap;
     interface Reg#(a) r;
  endinterface
  
  instance Connectable#(SpiTapOut, SpiTapIn);
     module mkConnection#(SpiTapOut out, SpiTapIn in)(Empty);
        rule move_data;
  