anchor.diff:      Wire#(Bit#(1)) bvi_delay_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       Wire#(Bit#(1)) bvi_reset_reg <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       SyncBitIfc#(Bit#(1)) bvi_resets_reg <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);
  -    Wire#(Bit#(1)) bvi_fifo_wren_wire <- mkDWire(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) dcounter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
  -    Reg#(DState)  dstate <- mkReg(DIdle, clocked_by serdes_clock, reset_by serdes_reset);
  +    Reg#(Bit#(1)) serdes_running <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) fifo_reset <- mkReg(1, clocked_by serdes_clock, reset_by serdes_reset);
       SyncBitIfc#(Bit#(1)) dfifo_reset_r <- mkSyncBit(defaultClock, defaultReset, serdes_clock);
  -    Reg#(Bit#(1)) dfifo_wren_r <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(1)) sync_bitslip <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) sync_reset_inc_ce <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);
       Reg#(Bit#(3)) ctrl_sample <- mkReg(0);
  
positive.code:     rule qfsmreset_rule if (bvi_resets_reg.read() == 0);
          this_aligned_reg <= 0;
          qstate <= QIdle;
          serdes_counter <= 0;
          ctrl_sample <= 0;
          start_alignment_fsm.clear();
      endrule
  
      rule qfsmidle_rule if (bvi_resets_reg.read() != 0 && qstate == QIdle
               && align_start == 1);
          serdes_counter <= 0;
          qstate <= QTrain;
      endrule
      rule qfsmqtrain_rule if (bvi_resets_reg.read() != 0 && qstate == QTrain);
          start_alignment_fsm.enq(1);
          qstate <= QOn;
      endrule
      rule qfsmqon_rule if (bvi_resets_reg.read() != 0 && qstate == QOn);
          qstate <= QOff;
      endrule
      rule qfsmqoff1_rule if (bvi_resets_reg.read() != 0 && qstate == QOff && serdes_counter <= 'h7fff);
          ctrl_sample <= ctrl_samplein_i;
          this_aligned_reg <= 1;
          qstate <= QIdle;
      endrule
      rule qfsmqoff2_rule if (bvi_resets_reg.read() != 0 && qstate == QOff && serdes_counter > 'h7fff);
          serdes_counter <= serdes_counter + 1;
          qstate <= QTrain;
      endrule
  
  
negative.code:     endrule
  
      //*************************** serdes setting FSM *****************
      rule serdes_idle_rule if (bvi_reset_reg != 0 && serdes_running == 0);
          serdes_setting.deq();
          Bit#(3) sric = 0;
          for (Integer i = 0; i < 3; i = i + 1)
              sric[i] = serdes_reset_inc_ce[i].read();
          sync_reset_inc_ce <= sric;
          sync_bitslip <= serdes_bitslip.read();
          serdes_running <= 1;
          dcounter <= 3;
      endrule
  
      rule serdes_running_rule if (bvi_reset_reg != 0 && serdes_running == 1);
          dcounter <= dcounter - 1;
          if (dcounter[2] == 1)
              begin
              ctrl_data <= ctrl_data_temp;
              Bit#(10) edgeo = 0;
              for (Integer i = 0; i < 9; i = i + 1)
                  edgeo[i] = ctrl_data_temp[i] ^ ctrl_data_temp[i+1];
              edgeo[9] = ctrl_data_temp[0] ^ ctrl_data_temp[9];
              edge_int <= edgeo;
              serdes_end.enq(1);
              serdes_running <= 0;
              end
          sync_reset_inc_ce <= {sync_reset_inc_ce[2], 2'b0};
          sync_bitslip <= 0;
  