anchor.diff:     // Feed a new PC into StageF (instruction fetch)
      // Set rg_halt on debugger stop request or dcsr.step step request
   
  -   function Action fa_start_ifetch (Epoch epoch, Maybe #(WordXL)  m_old_pc,  WordXL  next_pc, Priv_Mode priv);
  +   function Action fa_start_ifetch (
  +        Epoch epoch
  +      , Maybe #(WordXL)  m_old_pc
  +      , WordXL  next_pc
  +      , Priv_Mode priv
  +      , Bit #(1) mstatus_MXR
  +      , Bit #(1) sstatus_SUM);
         action
   	 // Initiate the fetch
  -`ifdef ISA_PRIV_S
  -	 Bit #(1) sstatus_SUM = (csr_regfile.read_sstatus) [18];
  -`else
  -	 Bit #(1) sstatus_SUM = 0;
  -`endif
  -	 Bit #(1) mstatus_MXR = mstatus [19];
   	 stageF.enq (epoch,
   		     m_old_pc,
   		     next_pc,
  
positive.code:       // Save new privilege and pc for ifetch
        rg_cur_priv <= new_priv;
        rg_next_pc  <= next_pc;
        rg_state    <= CPU_TRAP_FETCH;
  
        stage1.set_full (False);
        stage2.set_full (False);
  
negative.code:       // Resume pipe
        rg_state <= CPU_RUNNING;
  
        // MSTATUS.MXR for initiating FETCH
        Bit #(1) mstatus_MXR = mstatus [19];
        Bit #(1) sstatus_SUM = 0;
  
        // SSTATUS.SUM for initiating FETCH
  `ifdef ISA_PRIV_S
        sstatus_SUM = (csr_regfile.read_sstatus) [18];
  `else
        sstatus_SUM = 0;
  `endif
  
        let new_epoch <- fav_update_epoch;
        let m_old_pc   = tagged Invalid;
        fa_start_ifetch (
             new_epoch
           , m_old_pc
           , rg_next_pc
           , rg_cur_priv
           , mstatus_MXR
           , sstatus_SUM);
        stageF.set_full (True);
  
        stageD.set_full (False);
  