anchor.diff:        mc.app.sr_req(0);
         mc.app.zq_req(0);
      endrule
  -   
  +
      interface slave = axiSlaveCommon.server;
      interface Ddr3Pins ddr3;
         interface AxiDdr3Ddr3 ddr3 = mc.ddr3;
  
positive.code: 
     //fixme mc.aresetn
  
     AxiDdr3     mc <- mkAxiDdr3(clk200, mcReset);
     let ui_reset_n <- mkResetInverter(mc.ui_clk_sync_rst, clocked_by mc.ui_clk);
     let axiBits = toAxiSlaveBits(mc.s_axi);
     Axi4SlaveCommon#(Ddr3AddrWidth,Ddr3DataWidth,6,Empty) axiSlaveCommon <- mkAxi4SlaveGather(axiBits, clocked_by mc.ui_clk, reset_by ui_reset_n);
  
  
negative.code: import ClientServer    ::*;
  import AxiDdr3Wrapper  ::*;
  import AxiBits         ::*;
  import AxiGather       ::*;
  import Axi4MasterSlave ::*;
  import ConnectalClocks ::*;
  `include "ConnectalProjectConfig.bsv"
  