 
 // [8A] ADC A, D
 def op_8A() {
-  *A = om_adc8(*A, *C);
+  *A = om_adc8(*A, *D);
 }
 
 // [8B] ADC A, E

  // open_rom("/Users/mehcode/Workspace/gb-test-roms/cpu_instrs/individual/06-ld r,r.gb");
  // open_rom("/Users/mehcode/Workspace/gb-test-roms/cpu_instrs/individual/07-jr,jp,call,ret,rst.gb");
  // open_rom("/Users/mehcode/Workspace/gb-test-roms/cpu_instrs/individual/08-misc instrs.gb");
  open_rom("/Users/mehcode/Workspace/gb-test-roms/cpu_instrs/individual/09-op r,r.gb");
  // open_rom("/Users/mehcode/Workspace/gb-test-roms/cpu_instrs/individual/10-bit ops.gb");
  // open_rom("/Users/mehcode/Workspace/gb-test-roms/cpu_instrs/individual/11-op a,(hl).gb");

  reset();

// Shift Right
def om_shr(n: uint8, arithmetic: bool): uint8 {
  let r = if arithmetic {
    if (n & 0x80) != 0 {
      (n >> 1) | 0x80;
    } else {
      (n >> 1);
    }
  } else {
    (n >> 1);
  };
