   if (firsttime) {
     // * using an external clock source ATmega2560 has a bug that causes the first match ignored
     // WORKAROUND: toggle T5 to go beyond the first
-    for (int i = 0; i < syncTime[vidmode][SYNC_TIME_VSYNC] + 1; i++) {
+    for (int i = 0; i < syncTime[vidmode][SYNC_TIME_VSYNC]; i++) {
       TCCR4C |= _BV(FOC4C); TCCR4C |= _BV(FOC4C);
     }
     firsttime = false;
-  } else {
-    TCCR4C |= _BV(FOC4C); TCCR4C |= _BV(FOC4C);
   }
-  
+
+  TCCR4C |= _BV(FOC4C); TCCR4C |= _BV(FOC4C);
+
   if (syncTime[vidmode][SYNC_TIME_STRETCH] != 0) {
     // number of ticks the 2nd last HSYNC before VSYNC longer than others
     clock_stretch = syncTime[vidmode][SYNC_TIME_STRETCH] - 13; // updating TCNT4 requires 13 clock cycles (81.25ns)

  // the following registers can be set properly only after WGMn is set
  OCR4B = syncTime[vidmode][SYNC_TIME_HSYNC] - 3; // MATCH
  OCR4C = syncTime[vidmode][SYNC_TIME_HSYNC] - 5; // ADVANCE MATCH
  TCNT4 = syncTime[vidmode][SYNC_TIME_HSYNC] - 7; // START
  ICR4 = syncTime[vidmode][SYNC_TIME_HSYNC] - 1; // TOP
  interrupts();
  TCCR4B |= _BV(CS40); // CS4[2:0] = 1 (no prescaling)

 * D45 (OC5B/PL4) ------------------------- VSYNC
 * 
 */
volatile uint16_t clock_stretch;

ISR(TIMER5_COMPC_vect) {
  // compare match interrupt service routine (Timer 5 C)
  noInterrupts(); // temporary disable other high priority interrupts
  TCNT4 -= clock_stretch; // this statement takes AVR microcontroller 13 clock cycles to update TCNT4 io location
  interrupts(); // enable other interrupts again
}

void StartSyncSignal(int vidmode)
