   bool last_reverse;
 
   bool ext_clock_received;
-
-  bool display_changed[6];
 
   struct DU_SEQ_Parameter_Values {
     int8_t stage_pitch[8];

        display_gate(last_stage, DUINO_SSD1306::Black);
      }

      last_gate = gate;
      last_stage = stage;
      display_changed[2] = true;
    }

    // update clock from input

          display->fill_rect(16 * stage_selected + 1, 49, 5, 7, DUINO_SSD1306::White);
          display->draw_char(16 * stage_selected + 1, 49, '0' + params.vals.stage_steps[stage_selected],
              DUINO_SSD1306::Black);
          display->display(16 * stage_selected + 1, 16 * stage_selected + 5, 6, 7);
          break;
        case 4: // gate
          params.vals.stage_gate[stage_selected] += v;
