         }
         break;
       case GATE_EXT1:
-        gate = cv_read(CI2) > DIGITAL_THRESH;
+        gate = gt_read(GT1);
         break;
       case GATE_EXT2:
-        gate = cv_read(CI3) > DIGITAL_THRESH;
+        gate = gt_read(GT2);
         break;
     }
 

    step %= seq_values.stage_steps[stage];
    if(!step)
    {
      stage++;
      stage %= seq_values.stage_count;
    }
    retrigger = true;

    update_clock();

    // draw global elements
    for(uint8_t i = 0; i < 6; ++i)
    {
      display->draw_vline(2 + i, 18 - i, i + 1, DUINO_SSD1306::White);
    }
    display->draw_char(10, 12, '0' + params.vals.stage_count, DUINO_SSD1306::White);
    display->draw_char(22, 12, params.vals.diradd_mode ? 'A' : 'D', DUINO_SSD1306::White);
    display->draw_char(30, 12, 0x10, DUINO_SSD1306::White);
    for(uint8_t i = 0; i < 2; ++i)
    {
      display->draw_vline(59 + i * 25, 12, 7, DUINO_SSD1306::White);
