     }
     last_gate = false;
     last_stage = 0;
+    last_diradd_mode = false;
+    last_reverse = false;
 
     // draw top line
     display->draw_du_logo_sm(0, 0, DUINO_SSD1306::White);

    update_clock();

    // draw global elements
    display->draw_char(10, 12, '0' + params.vals.stage_count, DUINO_SSD1306::White);
    display->draw_char(22, 12, params.vals.diradd_mode ? 'A' : 'D', DUINO_SSD1306::White);
    for(uint8_t i = 0; i < 2; ++i)
    {
      display->draw_vline(59 + i * 25, 12, 7, DUINO_SSD1306::White);

      }
    }

    // display reverse/address
    if(seq_values.diradd_mode != last_diradd_mode
        || (!seq_values.diradd_mode && reverse != last_reverse)
        || (seq_values.diradd_mode && stage != last_stage))
    {
      display_reverse_address(30, 12);
      last_diradd_mode = seq_values.diradd_mode;
      last_reverse = reverse;
      display_changed[1] = true;
    }

    // display gate
    if(gate != last_gate || stage != last_stage)
    {
