   uint8_t stage_slew;
   int8_t stage_count;
   uint8_t diradd_mode;
-  uint8_t slew_rate;
-  uint8_t gate_time;
+  int8_t slew_rate;
+  int8_t gate_time;
   int8_t clock_bpm;
 };
 

      display->draw_hline(57 + i * 22, 8, 16, DUINO_SSD1306::White);
      display->draw_vline(73 + i * 22, 2, 7, DUINO_SSD1306::White);
    }
    display_clock(100, 2, clock_bpm, DUINO_SSD1306::White);

    // draw step elements

        case 5: // slew
          if(v < 0)
          {
            stage_slew &= ~(1 << stage_selected);
          }
          else if(v > 0)
          {
            stage_slew |= (1 << stage_selected);
          }
          seq_values.stage_slew[stage_selected] = (bool)((stage_slew >> stage_selected) & 1);
          display->fill_rect(16 * stage_selected + 1, 59, 14, 4, DUINO_SSD1306::Black);
          display->fill_rect(16 * stage_selected + 2 + 6 * (~(stage_slew >> stage_selected) & 1), 60, 6, 2,
              DUINO_SSD1306::White);  
          break;
      }

      // mark save box
      if(main_selected)
      {
        display->fill_rect(123, 2, 3, 3, DUINO_SSD1306::Black);
      }

      display_changed = (bool)main_selected;
