   {
     gt_attach_interrupt(GT3, clock_isr, CHANGE);
     gt_attach_interrupt(GT4, reset_isr, RISING);
+
+    gate = clock_gate = retrigger = false;
   }
 
   virtual void loop()

              seq_values.clock_ext = !(bool)params.vals.clock_bpm;
              display->fill_rect(99, 1, 19, 9, DUINO_SSD1306::White);
              display_clock(100, 2, params.vals.clock_bpm, DUINO_SSD1306::Black);
              break;
          }
          break;

    }

    // set gate state
    switch(seq_values.stage_gate[cached_stage])
    {
      case GATE_NONE:
