    
  Hardware:
    
- Board Type:
-   ZPUino Vanilla Variant for your hardware type
-   
  Special Application Notes:
  Detailed notes for using the JTAG Logic Analyzer
  The network server will make a connection with Channel A of the Papilio, which is connected to the JTAG port of the FPGA, and will forward all data to the Logic Analyzer client.
-   1) Load the bit file:  sketchdir://LX9/papilio_pro.bit
+   1) Load the bit file
    2) Start the JTAG server
-     For Windows: sketchdir://papilio-prog-jtag-server/papilio-prog-jtag-server.exe
+     For Windows: tools://papilio-prog-jtag-server/papilio-prog-jtag-server.exe
      For Linux: Coming soon
    3) Start Logic Analyzer client:
-     For Windows: sketchdir://ols-0.9.7/run.bat
+     For Windows: tools://Logic_Analyzer.sh
      For Linux: Coming soon 
    4) In the OLS Capture Settings - Connection page set the following:
        a)Connection Type = Network

  pinMode(WAL5, OUTPUT);
  pinMode(WAL6, OUTPUT);
  pinMode(WAL7, OUTPUT);  
  GPIODATA(0) = 170;
}

void loop() {
  // put your main code here, to run repeatedly: 
//  if (mySerial1.available()) {
//   Serial.write(mySerial1.read()); 
//  }
//  if (Serial.available()) {
//   mySerial1.write(Serial.read()); 
//  }  
  GPIODATA(0) = counter;
  counter++;
  if (counter >= 255)
    counter == 0;

  Serial.println("Hello");
  delay(1);

  //bscanSerial.print("1");

}

 This example code is in the public domain.
 */

int counter = 0;

void setup() {
  // put your setup code here, to run once:
  pinMode(WAL0, OUTPUT);
  pinMode(WAL1, OUTPUT);
  pinMode(WAL2, OUTPUT);
