             } while(!bus_state.ro_control.flags.sync);
         }
         instr_trigger.clear();
+    }
+
+    if(ex_trigger.triggered()) {
+        if(halt_switch.state()) {
+            claim_bus();
+            cursor_addr = panel_switches.flags.address;
+            bus_state.address = cursor_addr;
+            update_bus(false);
+        }
+        ex_trigger.clear();
+    }
+
+    if(ex_nx_trigger.triggered()) {
+        if(halt_switch.state()) {
+            claim_bus();
+            cursor_addr ++;
+            bus_state.address = cursor_addr;
+            update_bus(false);
+        }
+        ex_nx_trigger.clear();
+    }
+
+    if(dpst_trigger.triggered()) {
+        if(halt_switch.state()) {
+            claim_bus();
+            bus_state.address = cursor_addr;
+            update_bus(false);
+
+            // Now assert data bus
+            digitalWrite(PIN_R_WBAR, LOW);
+            digitalWrite(PIN_DOEBAR, LOW);
+
+            bus_state.address = cursor_addr;
+            bus_state.data = panel_switches.vals.a0_7;
+            update_bus(false);
+
+            digitalWrite(PIN_R_WBAR, HIGH);
+            digitalWrite(PIN_DOEBAR, HIGH);
+        }
+        dpst_trigger.clear();
+    }
+
+    if(dpst_nx_trigger.triggered()) {
+        if(halt_switch.state()) {
+            claim_bus();
+
+            cursor_addr++;
+            bus_state.address = cursor_addr;
+            update_bus(false);
+
+            // Now assert data bus
+            digitalWrite(PIN_R_WBAR, LOW);
+            digitalWrite(PIN_DOEBAR, LOW);
+
+            bus_state.address = cursor_addr;
+            bus_state.data = panel_switches.vals.a0_7;
+            update_bus(false);
+
+            digitalWrite(PIN_R_WBAR, HIGH);
+            digitalWrite(PIN_DOEBAR, HIGH);
+        }
+        dpst_nx_trigger.clear();
     }
 
     /*

            unsigned halt : 1;
            unsigned reset : 1;

            unsigned address : 24;
        } flags;
        struct {
            byte ctrl, a0_7, a8_15, a16_24;

    dpy_transfer(MX7219_DIGIT_0 + 5, digit5);
}

static void update_bus(bool do_load) {
    BusState new_state = bus_state;

    SPI.beginTransaction(SPISettings(SPI_SPEED, MSBFIRST, SPI_MODE0));

    // Load Addr and Data busses into shift reg.
    digitalWrite(PIN_ADLOAD, HIGH);
    digitalWrite(PIN_BUSSSBAR, LOW);
    // "transfer" a byte to ensure at least one SCK +ve going edge. The Data
    // and Address buses are sampled at this point.
    SPI.transfer(0);
    digitalWrite(PIN_BUSSSBAR, HIGH);
    digitalWrite(PIN_ADLOAD, LOW);

    // Exchange bytes over SPI. Control bus is sampled at this point.
    digitalWrite(PIN_BUSSSBAR, LOW);
    new_state.ro_control.val = SPI.transfer(0) & 0b1111111;
    new_state.data = SPI.transfer(bus_state.data);

    uint32_t prev_addr = bus_state.address;
    new_state.address = 0;
    new_state.address |=
        ((uint32_t)(SPI.transfer((prev_addr >> 16) & 0xff))) << 16;
    new_state.address |=
        ((uint32_t)(SPI.transfer((prev_addr >> 8) & 0xff))) << 8;
    new_state.address |=
        (uint32_t)(SPI.transfer(prev_addr & 0xff));

    // Transfer contents of Address and Data shift reg to output.
