     // set gate and clock states
     gt_out(GT5, gate);
     gt_out(GT6, cached_clock_gate);
+
+    // update reverse setting
+    if(!seq_values.diradd_mode)
+    {
+      reverse = cv_read(CI1) > DIGITAL_THRESH;
+    }
+  }
+
+  uint8_t address_to_stage()
+  {
+    int8_t stage = (int8_t)cv_read(CI1) * 1.6;
+    if(stage < 0)
+    {
+      stage = 0;
+    }
+    else if(stage > 7)
+    {
+      stage = 7;
+    }
+    return (uint8_t)stage;
   }
 
  private:

    update_clock();

    // draw global elements
    display->draw_char(10, 12, '0' + params.vals.stage_count, DUINO_SSD1306::White);
    display->draw_char(22, 12, params.vals.diradd_mode ? 'A' : 'D', DUINO_SSD1306::White);
    for(uint8_t i = 0; i < 2; ++i)
    {
      display->draw_vline(59 + i * 25, 12, 7, DUINO_SSD1306::White);

        }
        break;
      case GATE_EXT1:
        gate = gt_read(GT1);
        break;
      case GATE_EXT2:
        gate = gt_read(GT2);
        break;
    }

