 void tdc7200Channel::ready_next() {
     // needs to set the enable bit (START_MEAS in CONFIG1)
     // clears interrupt bits
-    delayMicroseconds(1000);  // was 10ms  
-    write(CONFIG1, 0x83);  // was 0x83 Measurement mode 2 - force cal
+    delayMicroseconds(1);  // was 10ms  
+    write(CONFIG1, 0x83);     // was 0x83 Measurement mode 2 - force cal
 }
 
 

// TICC.ino - master sketch file

// TICC Time interval Counter based on TICC Shield using TDC7200
// version 0.60 -- 29 July 2016

// Copyright John Ackermann N8UR 2016
// Portions Copyright George Byrkit K9TRV 2016

  delay(5);  // 1.5ms minimum recommended to allow chip LDO to stabilize
  
  
  write(CONFIG2, 0x81);  // SHOULD BE 0x80 for Cal2 (20 clocks, 1 meas cycle, 1 stop) but that doesn't work
 // write(INT_MASK, 0x01);  // was 0x01 disable clock overflow interrupts, allow only measurement interrupt
  
  
