     dpy_transfer(MX7219_DIGIT_0 + 5, digit5);
 }
 
-static void update_bus() {
+static void update_bus(bool do_load) {
+    BusState new_state = bus_state;
+
     SPI.beginTransaction(SPISettings(SPI_SPEED, MSBFIRST, SPI_MODE0));
 
     // Load Addr and Data busses into shift reg.
     digitalWrite(PIN_ADLOAD, HIGH);
     digitalWrite(PIN_BUSSSBAR, LOW);
-    // "transfer" a byte to ensure at least one SCK +ve going edge. The Data and
-    // Address buses are sampled at this point.
+    // "transfer" a byte to ensure at least one SCK +ve going edge. The Data
+    // and Address buses are sampled at this point.
     SPI.transfer(0);
     digitalWrite(PIN_BUSSSBAR, HIGH);
     digitalWrite(PIN_ADLOAD, LOW);
 
     // Exchange bytes over SPI. Control bus is sampled at this point.
     digitalWrite(PIN_BUSSSBAR, LOW);
-    bus_state.ro_control.val = SPI.transfer(0) & 0b1111111;
-    bus_state.data = SPI.transfer(bus_state.data);
+    new_state.ro_control.val = SPI.transfer(0) & 0b1111111;
+    new_state.data = SPI.transfer(bus_state.data);
 
     uint32_t prev_addr = bus_state.address;
-    bus_state.address = 0;
-    bus_state.address |=
+    new_state.address = 0;
+    new_state.address |=
         ((uint32_t)(SPI.transfer((prev_addr >> 16) & 0xff))) << 16;
-    bus_state.address |=
+    new_state.address |=
         ((uint32_t)(SPI.transfer((prev_addr >> 8) & 0xff))) << 8;
-    bus_state.address |=
+    new_state.address |=
         (uint32_t)(SPI.transfer(prev_addr & 0xff));
 
     // Transfer contents of Address and Data shift reg to output.

    }

    if(instr_trigger.triggered()) {
        if(halt_switch.state()) {
            do {
                digitalWrite(PIN_STEP, HIGH);
                digitalWrite(PIN_STEP, LOW);

            unsigned halt : 1;
            unsigned reset : 1;

            unsigned long address : 24;
        } flags;
        struct {
            byte ctrl, a0_7, a8_15, a16_24;
