   // the following registers can be set properly only after WGMn is set
   OCR4B = syncTime[vidmode][SYNC_TIME_HSYNC] - 3; // MATCH
   OCR4C = syncTime[vidmode][SYNC_TIME_HSYNC] - 5; // ADVANCE MATCH
-  TCNT4 = syncTime[vidmode][SYNC_TIME_HSYNC] - 7; // START
+  TCNT4 = syncTime[vidmode][SYNC_TIME_HSYNC] - 6; // START
   ICR4 = syncTime[vidmode][SYNC_TIME_HSYNC] - 1; // TOP
   interrupts();
   TCCR4B |= _BV(CS40); // CS4[2:0] = 1 (no prescaling)

  if (firsttime) {
    // * using an external clock source ATmega2560 has a bug that causes the first match ignored
    // WORKAROUND: toggle T5 to go beyond the first
    for (int i = 0; i < syncTime[vidmode][SYNC_TIME_VSYNC] + 1; i++) {
      TCCR4C |= _BV(FOC4C); TCCR4C |= _BV(FOC4C);
    }
    firsttime = false;
  } else {
    TCCR4C |= _BV(FOC4C); TCCR4C |= _BV(FOC4C);
  }
  
  if (syncTime[vidmode][SYNC_TIME_STRETCH] != 0) {
    // number of ticks the 2nd last HSYNC before VSYNC longer than others
    clock_stretch = syncTime[vidmode][SYNC_TIME_STRETCH] - 13; // updating TCNT4 requires 13 clock cycles (81.25ns)

  TIMSK5 = 0; // disable timer 5 interrupts
  TCCR5B = 0;
  TCCR5A = _BV(COM5B0); // toggle on compare match
  DDRL |= _BV(4); // set OC5B to output
  noInterrupts();
  if (!(PINL & _BV(4))) { // toggle if LOW
    TCCR5C |= _BV(FOC5B);
  }
  interrupts();

  // Timer 4 (HSYNC)
  TCCR4B = 0;
  TCCR4A = _BV(COM4B0) | _BV(COM4C0); // toggle on compare match
  DDRH |= _BV(4) | _BV(5); // set OC4B and OC4C to output
  noInterrupts();
  if (!(PINH & _BV(4)) || !(PINH & _BV(5))) { // toggle if LOW
    TCCR4C |= (PINH & _BV(4) ? 0 : _BV(FOC4B)) | (PINH & _BV(5) ? 0 : _BV(FOC4C));
  }
  interrupts();
}

