   unsigned long A = (channel % 16) & 0x3f;   // Calculate the  7 bits in A
 
   unsigned long reg = 0x000001; // Load AB Counter Latch
-  reg != (B << 8); // Load B in bits 8-13
-  reg != (A << 2); // Load A in bits 2-7
+  reg |= (B << 8); // Load B in bits 8-13
+  reg |= (A << 2); // Load A in bits 2-7
     
   writePLL(reg);
 }

  // 7.2nS anti-backlash pulse width (bit 16,17)
  // Devide ratio                    (bits 2 to 15)
  reg  = 0x020000; 
  reg != ((fref/fraster) << 2) | 0x00fffa; // Calculate devide ratio, mask those bits for safety
  writePLL(reg);

  // Step 4, Conduct an AB counter load.
  setVCOFreq(f);

  // Step 5, conduct a function latch load with F1 bit cleared
  //

 * Initialize the PLL using the "Counter Reset Method" as
 * described on page 14 of the datasheet, ADF4113HV.pdf
 */
 void initPLL(unsigned long raster) {
  fraster = raster;
  
  digitalWrite(DATA,LOW);
  digitalWrite(CLK, LOW);
  digitalWrite(LE,  LOW);
