       display_reverse_address(30, 12);
       last_diradd_mode = seq_values.diradd_mode;
       last_reverse = reverse;
-      display->display(30, 34, 1, 2);
+      Display.display(30, 34, 1, 2);
     }
 
     // display gate


  DU_SEQ_Parameters params;

  uint8_t cached_stage, cached_step;
  bool cached_clock_gate, cached_retrigger;
  unsigned long clock_time;

  uint8_t main_selected;  // 0 - save, 1 - top, 2 - pitch, 3 - steps, 4 - gate, 5 - slew
  uint8_t top_selected;   // 0 - count, 1 - dir/add, 2 - slew, 3 - gate, 4 - clock
  uint8_t stage_selected;

  bool last_gate;
  uint8_t last_stage;

    gt_attach_interrupt(GT4, reset_isr, FALLING);

    // draw top line
    Display.draw_du_logo_sm(0, 0, DUINO_SH1106::White);
    Display.draw_text(16, 0, "SEQ", DUINO_SH1106::White);

    // draw save box
    Display.fill_rect(widget_save_->x() + 1, widget_save_->y() + 1, 5, 5, DUINO_SH1106::White);

    // load settings
    load_params(0, params.bytes, 30);
