           display->fill_rect(16 * stage_selected + 8, 49, 7, 7, DUINO_SSD1306::White);
           display->draw_icon_7(16 * stage_selected + 8, 49, gate_mode_icons,
               (GateMode)params.vals.stage_gate[stage_selected], DUINO_SSD1306::Black);
-          display_changed[4] = true;
+          display->display(16 * stage_selected + 8, 16 * stage_selected + 14, 6, 7);
           break;
         case 5: // slew
           if(v < 0)

        display_gate(last_stage, DUINO_SSD1306::Black);
      }

      last_gate = gate;
      last_stage = stage;
      display_changed[2] = true;
    }

    // update clock from input

              seq_values.gate_ms = params.vals.gate_time * (uint16_t)(seq_values.clock_period / 8000);
              display->fill_rect(85, 13, 16, 5, DUINO_SSD1306::White);
              display_gate_time(85, 13, params.vals.gate_time, DUINO_SSD1306::Black);
              display->display(85, 100, 1, 2);
              break;
            case 4: // clock
              params.vals.clock_bpm += v;
