anchor.diff:  Value
   “okay”
   “disabled”
  -
   “fail”
  -
   “fail-sss”
   
   Description
  
positive.code: • No I/O device mappings (see 5.4.3, Initial I/O Mappings (IIO)) are required.
  • For CPUs with address translation always enabled:
  
  Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
  Page 57 of 108
  
  Version 1.1 – 7 March 2011
  
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  Power.org ePAPR
  
  The Secondary IMA (SIMA) mapping (described in 5.3, Initial Mapped Areas) in the
  MMU shall map effective address 0 to the entry_addr field in the spin table,
  
negative.code: implement the interrupt priority mechanism.
  Usage legend: R=Required, O=Optional, OR=Optional but Recommended, SD=See Definition
  
  ===== interrupt Specifiers
  
  The interrupts property of interrupt children of the "epapr,hv-pic" node
  consists of two cells encoded as follows:
  
  <interrupt-src-number flags>
  
  Where:
  * interrupt-src-number specifies the interrupt source number that may be
    used in the hcalls to configure and manage the interrupt source
  * flags describes the level-sense encoding of the interrupt, encoded as:
  Table 7-8, epapr,hv-pic interrupt specifier flags encoding
  Bits
  31
  