anchor.diff:  IR=0,DR=0 real mode (see note 1)
   IS=0,DS=0 address space 0 (see note 1)
   SF=0, CM=0, ICM=0 32-bit mode
  +----
  +
   The state of any additional MSR bits is defined in the
   applicable processor supplement specification.
  -Effective address of the device tree image.
  +|R3 | Effective address of the device tree image.
   Note: This address shall be 8 bytes aligned in memory.
  -0
  -0
  -ePAPR magic value—to distinguish from non-ePAPRcompliant firmware
  -• For Book III-E CPUs shall be 0x45504150
  -• For non-Book III-E CPUs shall be 0x65504150
  -
  -
  -
  -R7
  -R8
  -R9
  -TCR
  -other registers
  -
  -
  -
  -shall be the size of the boot IMA in bytes
  -0
  -0
  -WRC=0, no watchdog timer reset will occur (see note 2)
  -implementation dependent
  +|R4 |0
  +|R5 |0
  +|R6 a|
  +ePAPR magic value—to distinguish from non-ePAPR compliant firmware
  +
  +* For Book III-E CPUs shall be 0x45504150
  +* For non-Book III-E CPUs shall be 0x65504150
  +|R7 |shall be the size of the boot IMA in bytes
  +|R8 |0
  +|R9 |0
  +|TCR |WRC=0, no watchdog timer reset will occur (see note 2)
  +|other registers |implementation dependent
  +|===
   
   Note 1: Applicable only to CPUs that define these bits
  +
   Note 2: Applicable to Book III-E CPUs only
  -On a multi-threaded processor that supports [Category: Embedded Multi-Threading], the client
  -program shall be entered on thread zero with the register values defined in the preceding table. All
  -other threads shall be disabled and shall have register values set as defined in the preceding table
  -except as follows:
  -•
  -•
  -•
  -•
  -
  -R3 shall be zero.
  -R6 shall be zero.
  -R7 shall be zero.
  -PC shall be 0x4.
  -
  -Programming Note
  -The boot program is expected to place a store instruction at effective address 0x0 and a branch-to-self
  -instruction at effective address 0x4. The store instruction is expected to be used to set a shared
  -variable indicating that the thread has reached the branch-to-self instruction and is ready to be
  -disabled.
  -
  +
  +On a multi-threaded processor that supports [Category: Embedded
  +Multi-Threading], the client program shall be entered on thread zero
  +with the register values defined in the preceding table. All other
  +threads shall be disabled and shall have register values set as defined
  +in the preceding table except as follows:
  +
  +* R3 shall be zero.
  +* R6 shall be zero.
  +* R7 shall be zero.
  +* PC shall be 0x4.
  +
  +.Programming Note
  +****
  +The boot program is expected to place a store instruction at effective
  +address 0x0 and a branch-to-self instruction at effective address 0x4.
  +The store instruction is expected to be used to set a shared variable
  +indicating that the thread has reached the branch-to-self instruction
  +and is ready to be disabled.
  +****
   
   ==== I/O Devices State
  -
  +The boot program shall leave all devices with the following conditions true:
  +
  +* All devices: no DMA and not interrupting
  +* Host bridges: responding to config cycles and passing through config
  +  cycles to children
   
   ==== Initial I/O Mappings (IIO)
  -
  -The boot program shall leave all devices with the following conditions true:
  -• All devices: no DMA and not interrupting
  -• Host bridges: responding to config cycles and passing through config cycles to children
  -
   A boot program might pass a client program a device tree containing
   device nodes with a virtual-reg property (see 2.3.7, virtual-reg). The
   virtual-reg property describes an Initial I/O (or IIO) mapping set up by
   firmware, and the value is the effective address of a device's
  -registers.  For Book III-E CPUs, effective to physical address mappings
  +registers.
  +
  +For Book III-E CPUs, effective to physical address mappings
   shall be present in the CPU's MMU to map any IIO. An IIO has the
   following requirements on Book III-E CPUs:
  +
   1. An IIO shall be virtually and physically contiguous.
   2. An IIO shall map the effective address in virtual-reg to the physical
      address at which the device appears at the point of entry.
  
positive.code: Before starting a client program on the boot cpu, the boot program shall
  set certain properties in the device tree passed to the client as
  follows:
  • Each secondary CPU's cpu node shall have a status property with a value of “disabled”.
  • Each secondary CPU's cpu node shall have an enable-method property.
  • For each secondary cpu node with an enable-method value of “spin-table”, the cpu node
  shall have a cpu-release-addr property that describes the address of the applicable spin table
  entry to release the CPU.
  
  For secondary CPUs with address translation always enabled (e.g., Book
  III-E), the boot program shall set up an address mapping in the
  
negative.code: be available for client use on the platform in question.
  
  == Client Program Boot Requirements
  === Boot and Secondary CPUs
  A boot cpu is the CPU on which control is transferred from the boot
  program to a client program.  Other CPUs that belong to the client
  program are considered secondary CPUs.
  
  For a partition with multiple CPUs in an SMP configuration, one CPU
  shall be designated as the boot cpu. The unit address of the CPU node
  for the boot cpu is set in the boot_cpuid_phys field of the flattened
  device tree header (see section 8.2, Header).
  
  === Device Tree
  A boot program shall load a device tree image into the client program's
  memory before transferring control to the client on the boot cpu. The
  logical structure of the device tree shall comply with the requirements
  specified in section 3.1 (Base Device Node Types). The physical
  structure of the device tree image shall comply with the requirements
  specified in chapter 8 (Flat Device Tree Physical Structure).
  
  The loaded device tree image shall be aligned on an 8-byte boundary in
  the client's memory.
  
  === Initial Mapped Areas
  CPUs that implement the Power ISA Book III-E embedded environment, which
  run with address translation always enabled, have some unique boot
  requirements related to initial memory mappings.  This section
  introduces the concept of an Initial Mapped Area (or IMA), which is
  applicable to Book III-E CPUs.
  
  A client program's IMA is a region of memory that contains the entry
  points for a client program.  Both boot CPUs and secondary CPUs begin
  client program execution in an IMA. The terms Boot IMA (BIMA) and
  Secondary IMA (SIMA) are used to distinguish the IMAs for boot CPUs and
  secondary CPUs where necessary.
  
  All IMAs have the following requirements:
  
  1. An IMA shall be virtually and physically contiguous
  2. An IMA shall start at effective address zero (0) which shall be
     mapped to a physical address naturally aligned to the size of the IMA.
  3. The mapping shall not be invalidated except by a client program's
     explicit action (i.e., not subject to broadcast invalidates from
     other CPUs)
  4. The Translation ID (TID) field in the TLB entry or entries shall be zero.
  5. The memory and cache access attributes (WIMGE) have the following requirements:
  * WIMG = 001x
  * E=0 (i.e., big-endian)
  * VLE (if implemented) is set to 0
  6. An IMA may be mapped by a TLB entry larger than the IMA size,
  provided the MMU guarded attribute is set (G=1)
  7. An IMA may span multiple TLB entries.
  
  .Programming Note
  ****
  Those CPUs with an IPROT capable TLB should use the IPROT facility to ensure
  requirement #3.
  ****
  
  === CPU Entry Point Requirements
  This section describes the state of the processor and system when a boot
  program passes control to a client program.
  
  ==== Boot CPU Initial Register State
  A boot CPU shall have its initial register values set as described in
  the following table.
  
  .Table 5-1 Boot CPU initial register values
  [options="header", width="65", cols="^15,40"]
  |===
  |Register | Value
  |MSR a|
  ----
  PR=0 supervisor state
  EE=0 interrupts disabled
  ME=0 machine check interrupt disabled
  