anchor.diff:  program to client program interface definition, combined with minimum system
   requirements that facilitate the development of a wide variety of embedded
   systems based on CPUs that implement the Power architecture as defined in the
  -Power ISA(TM)<<1>>.
  +Power ISA(TM)<<b1>>.
   
   This specification is targeted towards the requirements of embedded
   systems. An embedded system typically consists of system hardware, an
  
positive.code: compatible interrupt controllers. An open PIC interrupt controller
  implements the open PIC architecture (developed jointly by AMD and
  Cyrix) and specified in The Open Programmable Interrupt Controller (PIC)
  Register Interface Specification Revision 1.2 <<18>>.
  
  Interrupt specifiers in an open PIC interrupt domain are encoded with
  two cells. The first cell defines the interrupt number. The second cell
  
negative.code: === Relationship to IEEE(TM) 1275
  The {spec} is loosely related to the IEEE 1275 Open Firmware
  standard—_IEEE Standard for Boot (Initialization Configuration)
  Firmware: Core Requirements and Practices_ <<b1>>.
  
  The original IEEE 1275 specification and its derivatives such as CHRP
  <<b10>> and PAPR <<b16>> address problems of general purpose
  computers, such as how a single version of an operating system can work
  on several different computers within the same family and the problem of
  loading an operating system from user-installed I/O devices.
  