anchor.diff:  spins until the branch_address field in the spin table is updated
   specifying that the core is released.
   
  -A spin table is a table data structure consisting of 1 entry per CPU where each entry is defined as
  -follows:
  +A spin table is a table data structure consisting of 1 entry per CPU
  +where each entry is defined as follows:
  +
   [verse]
   struct {
   	uint64_t entry_addr;
  
positive.code:    (i.e., not subject to broadcast invalidates from other partitions).
  4. The Translation ID (TID) field in the TLB entry shall be zero.
  5. The memory and cache access attributes (WIMGE) have the following requirements:
  • WIMG shall be suitable for accessing the device in question. Typically I=1, G=1.
  • E=0 (i.e., big-endian)
  6. An IIO shall be large enough to cover all of device's registers.
  7. Multiple devices may share an IIO.
  
  
negative.code: 8. The MMU mappings for the BIMA and all IIOs shall be such that the
     TLBs can accommodate a reasonable number of additional mappings.
  
  .Programming Notes
  ****
  * A boot program might wish to select BIMA size based on client image layout in order to
  satisfy requirement #2
  * Client can determine physical address of IMA by either of two methods:
  1. tlbsx on EA 0, then read and parse TLB entry
  2. from the optional initial-mapped-area property on a memory node
  ****
  
  === Symmetric Multiprocessing (SMP) Boot Requirements
  ==== Overview
  For CPUs in an SMP configuration, one CPU shall be designated the boot
  CPU and initialized as described in section 5.4, CPU Entry Point
  Requirements. All other CPUs are considered secondary.
  
  A boot program passes control to a client program on the boot CPU only.
  At the time the client program is started, all secondary CPUs shall in a
  quiescent state. A quiescent CPU is in a state where it cannot interfere
  with the normal operation of other CPUs, nor can its state be affected
  by the normal operation of other running CPUs, except by an explicit
  method for enabling or re-enabling the quiescent CPU. The status
  property of the quiescent CPU's cpu node in the device tree shall have a
  value of “disabled” (see 3.7.1, General Properties of CPU nodes).
  
  Secondary CPUs may be started using the spin table or
  implementation-specific mechanisms described in the following sections.
  
  ==== Spin Table
  ===== Overview
  