anchor.diff:  memory that is appropriate for the platform. If the spin loop and table
   reside in a memory region belonging to a client program, the memory
   occupied by the loop and table shall be marked reserved in the device
  -tree’s DTB memory reservation block (see section 8.3, Memory Reservation
  +tree's DTB memory reservation block (see section 8.3, Memory Reservation
   Block).
   
   Before starting a client program on the boot cpu, the boot program shall
   set certain properties in the device tree passed to the client as
   follows:
  -• Each secondary CPU’s cpu node shall have a status property with a value of “disabled”.
  -• Each secondary CPU’s cpu node shall have an enable-method property.
  +• Each secondary CPU's cpu node shall have a status property with a value of “disabled”.
  +• Each secondary CPU's cpu node shall have an enable-method property.
   • For each secondary cpu node with an enable-method value of “spin-table”, the cpu node
   shall have a cpu-release-addr property that describes the address of the applicable spin table
   entry to release the CPU.
   
   For secondary CPUs with address translation always enabled (e.g., Book
   III-E), the boot program shall set up an address mapping in the
  -secondary CPU’s MMU for the spin loop and table.
  +secondary CPU's MMU for the spin loop and table.
   
   The boot program shall place a spinning CPU in a quiescent state where
   it cannot interfere with the normal operation of other CPUs, nor can its
  
positive.code: o
  
  FDT_END_NODE (0x00000002)
  The FDT_END_NODE token marks the end of a node’s representation. This token has no
  extra data; so it is followed immediately by the next token, which may be any token except
  FDT_PROP.
  
  
negative.code: A boot program might pass a client program a device tree containing
  device nodes with a virtual-reg property (see 2.3.7, virtual-reg). The
  virtual-reg property describes an Initial I/O (or IIO) mapping set up by
  firmware, and the value is the effective address of a device's
  registers.  For Book III-E CPUs, effective to physical address mappings
  shall be present in the CPU's MMU to map any IIO. An IIO has the
  following requirements on Book III-E CPUs:
  1. An IIO shall be virtually and physically contiguous.
  2. An IIO shall map the effective address in virtual-reg to the physical
     address at which the device appears at the point of entry.
  3. An IIO shall not be invalidated except by client's explicit action
     (i.e., not subject to broadcast invalidates from other partitions).
  4. The Translation ID (TID) field in the TLB entry shall be zero.
  5. The memory and cache access attributes (WIMGE) have the following requirements:
  • WIMG shall be suitable for accessing the device in question. Typically I=1, G=1.
  • E=0 (i.e., big-endian)
  6. An IIO shall be large enough to cover all of device's registers.
  7. Multiple devices may share an IIO.
  
  ==== Boot CPU Entry Requirements: Real Mode
  