anchor.diff:  spins until the branch_address field in the spin table is updated
   specifying that the core is released.
   
  -A spin table is a table data structure consisting of 1 entry per CPU where each entry is defined as
  -follows:
  +A spin table is a table data structure consisting of 1 entry per CPU
  +where each entry is defined as follows:
  +
   [verse]
   struct {
   	uint64_t entry_addr;
  
positive.code: 
  The spin table fields are defined as follows:
  
  entry_addr. Specifies the physical address of the client entry point for the spin table code to
  branch to. The boot program's spin loop must wait until the least significant bit of
  entry_addr is zero.
  
  r3. Contains the value to put in the r3 register at secondary cpu entry. The high 32-bits are
  ignored on 32-bit chip implementations. 64-bit chip implementations however shall load all
  64-bits
  
  pir. Contains a value to load into the PIR (processor identification) register for those CPUs
  with writable PIR.
  
  Before a secondary CPU enters a spin loop, the spin table fields shall
  be set with these initial values:
  Field
  entry_addr
  r3
  pir
  
  
  
  Initial Value
  0x1
  Value of the reg property from the CPU node in the device
  tree that corresponds to this CPU.
  A valid PIR value, different on each CPU within the same
  partition.
  
  The spin table shall be cache-line size aligned in memory.
  The boot program and client program shall ensure that all virtual pages through which the spin table
  can be accessed have storage control attributes such that all accesses to the spin table are not Write
  Through Required, not Caching Inhibited, Memory Coherence Required, and either not Guarded or
  Guarded (i.e., WIMG = 0b001x). Further, if the E storage attribute is supported, it shall be set to BigEndian (E = 0), and if the VLE storage attribute is supported, it shall be set to 0.
  Programming Note
  Some older boot programs perform Caching Inhibited and not Memory Coherence Required accesses
  to the spin table, taking advantage of implementation-specific knowledge of the behavior of accesses
  to shared storage with conflicting Caching Inhibited attribute values. If compatibility with such boot
  programs is required, client programs should use dcbf to flush a spin table entry from the caches both
  before and after accessing the spin table entry.
  
  ===== Boot Program Requirements
  The boot program shall place a spin loop and spin table into an area of
  
negative.code: Before starting a client program on the boot cpu, the boot program shall
  set certain properties in the device tree passed to the client as
  follows:
  
  * Each secondary CPU's cpu node shall have a status property with a
    value of “disabled”.
  * Each secondary CPU's cpu node shall have an enable-method property.
  * For each secondary cpu node with an enable-method value of
    “spin-table”, the cpu node shall have a cpu-release-addr property that
    describes the address of the applicable spin table entry to release
    the CPU.
  
  For secondary CPUs with address translation always enabled (e.g., Book
  III-E), the boot program shall set up an address mapping in the
  