anchor.diff:  Before starting a client program on the boot cpu, the boot program shall
   set certain properties in the device tree passed to the client as
   follows:
  -• Each secondary CPU's cpu node shall have a status property with a value of “disabled”.
  -• Each secondary CPU's cpu node shall have an enable-method property.
  -• For each secondary cpu node with an enable-method value of “spin-table”, the cpu node
  -shall have a cpu-release-addr property that describes the address of the applicable spin table
  -entry to release the CPU.
  +
  +* Each secondary CPU's cpu node shall have a status property with a
  +  value of “disabled”.
  +* Each secondary CPU's cpu node shall have an enable-method property.
  +* For each secondary cpu node with an enable-method value of
  +  “spin-table”, the cpu node shall have a cpu-release-addr property that
  +  describes the address of the applicable spin table entry to release
  +  the CPU.
   
   For secondary CPUs with address translation always enabled (e.g., Book
   III-E), the boot program shall set up an address mapping in the
  
positive.code: IR=0,DR=0 real mode (see note 1)
  IS=0,DS=0 address space 0 (see note 1)
  SF=0, CM=0, ICM=0 32-bit mode
  The state of any additional MSR bits is defined in the
  applicable processor supplement specification.
  Effective address of the device tree image.
  Note: This address shall be 8 bytes aligned in memory.
  0
  0
  ePAPR magic value—to distinguish from non-ePAPRcompliant firmware
  • For Book III-E CPUs shall be 0x45504150
  • For non-Book III-E CPUs shall be 0x65504150
  
  
  
  R7
  R8
  R9
  TCR
  other registers
  
  
  
  shall be the size of the boot IMA in bytes
  0
  0
  WRC=0, no watchdog timer reset will occur (see note 2)
  implementation dependent
  
  Note 1: Applicable only to CPUs that define these bits
  Note 2: Applicable to Book III-E CPUs only
  On a multi-threaded processor that supports [Category: Embedded Multi-Threading], the client
  program shall be entered on thread zero with the register values defined in the preceding table. All
  other threads shall be disabled and shall have register values set as defined in the preceding table
  except as follows:
  •
  •
  •
  •
  
  R3 shall be zero.
  R6 shall be zero.
  R7 shall be zero.
  PC shall be 0x4.
  
  Programming Note
  The boot program is expected to place a store instruction at effective address 0x0 and a branch-to-self
  instruction at effective address 0x4. The store instruction is expected to be used to set a shared
  variable indicating that the thread has reached the branch-to-self instruction and is ready to be
  disabled.
  
  
  ==== I/O Devices State
  
  
  ==== Initial I/O Mappings (IIO)
  
  The boot program shall leave all devices with the following conditions true:
  • All devices: no DMA and not interrupting
  • Host bridges: responding to config cycles and passing through config cycles to children
  
  A boot program might pass a client program a device tree containing
  device nodes with a virtual-reg property (see 2.3.7, virtual-reg). The
  virtual-reg property describes an Initial I/O (or IIO) mapping set up by
  firmware, and the value is the effective address of a device's
  registers.  For Book III-E CPUs, effective to physical address mappings
  shall be present in the CPU's MMU to map any IIO. An IIO has the
  following requirements on Book III-E CPUs:
  1. An IIO shall be virtually and physically contiguous.
  2. An IIO shall map the effective address in virtual-reg to the physical
     address at which the device appears at the point of entry.
  
negative.code: 
  The spin table fields are defined as follows:
  
  [horizontal]
  entry_addr:: Specifies the physical address of the client entry point
  for the spin table code to branch to. The boot program's spin loop must
  wait until the least significant bit of entry_addr is zero.
  
  r3:: Contains the value to put in the r3 register at secondary cpu
  entry. The high 32-bits are ignored on 32-bit chip implementations.
  64-bit chip implementations however shall load all 64-bits
  
  pir:: Contains a value to load into the PIR (processor identification)
  register for those CPUs with writable PIR.
  
  Before a secondary CPU enters a spin loop, the spin table fields shall
  be set with these initial values:
  
  [options="header"]
  |===
  |Field |Initial Value
  |entry_addr | 0x1
  |r3 | Value of the reg property from the CPU node in the device
  tree that corresponds to this CPU.
  |pir | A valid PIR value, different on each CPU within the same
  partition.
  |===
  
  The spin table shall be cache-line size aligned in memory.
  
  The boot program and client program shall ensure that all virtual pages
  through which the spin table can be accessed have storage control
  attributes such that all accesses to the spin table are not Write
  Through Required, not Caching Inhibited, Memory Coherence Required, and
  either not Guarded or Guarded (i.e., WIMG = 0b001x). Further, if the E
  storage attribute is supported, it shall be set to BigEndian (E = 0),
  and if the VLE storage attribute is supported, it shall be set to 0.
  
  .Programming Note
  ****
  Some older boot programs perform Caching Inhibited and not Memory
  Coherence Required accesses to the spin table, taking advantage of
  implementation-specific knowledge of the behavior of accesses to shared
  storage with conflicting Caching Inhibited attribute values. If
  compatibility with such boot programs is required, client programs
  should use dcbf to flush a spin table entry from the caches both before
  and after accessing the spin table entry.
  ****
  
  ===== Boot Program Requirements
  The boot program shall place a spin loop and spin table into an area of
  