anchor.diff:  : R, ( rs1 rs2 rd opmask -- )
   	4 ALIGN (rd) (rs2) (rs1) W, ;
   
  +	\ Immediate instructions are also employed by the various load
  +	\ instructions as well.
   : I, ( rs1 imm rd opmask -- )
   	4 ALIGN (rd) (imm12) (rs1) W, ;
   
  -: S, ( rs1 rs2 imm opmask -- )
  +	\ Note that we swap the two source registers for store instructions.
  +	\ This is for the benefit of human beings trying to code in assembly
  +	\ language directly.  The RISC-V ISA says that the store instructions
  +	\ take data from rs2 and store them into address rs1+imm.  Swapping the
  +	\ registers minimizes surprises for the human coder, as it preserves 
  +	\ the convention that the destination of an instruction is closest to
  +	\ the instruction.
  +: S, ( rs2 rs1 imm opmask -- )
   	4 ALIGN
   	OVER 31 AND 7 LSHIFT OR
   	SWAP 5 RSHIFT 25 LSHIFT OR
  -	(rs2) (rs1) W, ;
  +	(rs1) (rs2) W, ;
   
   : SB, ( rs1 rs2 disp opmask -- )
   	4 ALIGN
  
positive.code: \ Observe that the RISC-V architecture is a LITTLE-ENDIAN instruction set
  \ architecture.
  
  : (b,) ( c -- )		bc @ image + C!  1 bc +! ;
  : B, ( c -- )		1 room (b,) ;
  
  HEX
  
negative.code: 
  : room ( n -- )		bc @ + /image U> ABORT" Image overflow" ;
  
  	\ CAREFUL!!
  	\ These assume we're running on a little-endian, 32-bit Forth host.
  : IB! ( c bo -- )	image + C! ;
  : IH! ( h bo -- )	2DUP IB! 1+ SWAP 8 RSHIFT SWAP IB! ;
  : IW! ( w bo -- )	image + ! ;
  : ID! ( d bo -- )	>R SWAP R> image + 2! ;
  
  	\ CAREFUL!!
  	\ These assume we're running on a little-endian, 32-bit Forth host.
  : IB@ ( bo -- c )	image + C@ ;
  : IH@ ( bo -- h )	DUP IB@ SWAP 1+ IB@ 8 LSHIFT OR ;
  : IW@ ( bo -- w )	image + @ ;
  : ID@ ( bo -- d )	image + 2@ SWAP ;
  
  \ B, H, W, and D, place a byte, half-word, word, or double-word (8, 16, 32,
  \ or 64 bit, respectively) values verbatim into the image buffer.
  \ 
  