anchor.diff:  #
   PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
   PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
  -## PRESET,PAPI_L1_STM,NOT_DERIVED,L1D:ALLOCATED_IN_M
  -## PRESET,PAPI_L1_STM,NOT_DERIVED,L2_TRANS:RFO
   PRESET,PAPI_L1_STM,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL
   PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
  -#  PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I:READS
  -#  PRESET,PAPI_L1_ICR,NOT_DERIVED,L1I:READS
  -#  PRESET,PAPI_L1_ICH,NOT_DERIVED,L1I:HITS
  -#r PRESET,PAPI_L1_TCM,DERIVED_SUB,L2_RQSTS:REFERENCES,L2_RQSTS:ALL_PF
   PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE:MISSES,L1D:REPLACEMENT
   #
  -#r PRESET,PAPI_L2_DCM,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS
   PRESET,PAPI_L2_DCM,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS
  -#  PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:LD_MISS
   PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS
   PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT
   PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
  -PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_RD_HIT,L2_RQSTS:RFO_HITS
  -## PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_TRANS:RFO
   PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL
   PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
   PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
   PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
   PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
   PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
  -#  PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:REFERENCES,L2_RQSTS:MISS
  -#  PRESET,PAPI_L2_TCH,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_RD_HIT
  -#r PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES
   PRESET,PAPI_L2_TCA,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
   PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
  -PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFO_ANY
  -#
  -#r PRESET,PAPI_L3_DCA,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS
  +#
   PRESET,PAPI_L3_DCA,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS
  -#r PRESET,PAPI_L3_DCR,NOT_DERIVED,L2_RQSTS:LD_MISS
   PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
   PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
  -## PRESET,PAPI_L3_DCW,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_RFO
   PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
   PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
  -#  PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS
   PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
   PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
  -#r PRESET,PAPI_L3_TCR,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:CODE_RD_MISS
   PRESET,PAPI_L3_TCR,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:RFO_MISS
   PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
   #
  
positive.code: PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:ALL_BRANCHES
  PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_MISP_RETIRED:ALL_BRANCHES
  #
  PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK
  PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:CAUSES_A_WALK
  #
  PRESET,PAPI_FDV_INS,NOT_DERIVED,ARITH:FPU_DIV
  PRESET,PAPI_STL_ICY,NOT_DERIVED,ILD_STALL:IQ_FULL
  PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_LOADS
  PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_STORES
  #PRESET,PAPI_FP_INS,DERIVED_ADD,FP_COMP_OPS_EXE:X87,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE
  #PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:X87,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE
  PRESET,PAPI_FP_INS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE
  PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE
  
  #
  CPU,Intel Core2
  CPU,Intel Core
  
negative.code: PRESET,PAPI_L1_TCR,DERIVED_ADD,L1D_CACHE_LD:MESI,L1I:READS
  PRESET,PAPI_L2_TCW,NOT_DERIVED,L1D_CACHE_ST:MESI
  #
  # Intel SandyBridge and IvyBridge
  CPU,snb
  CPU,snb_ep
  CPU,ivb
  