anchor.diff:  PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS
   PRESET,PAPI_BR_TKN,NOT_DERIVED,PC_BRANCH_EXECUTED
   PRESET,PAPI_STL_ICY,NOT_DERIVED,CYCLES_INST_STALL
  -
  +#
   CPU,arm_ac9
  +#
   PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_OUT_OF_RENAME_STAGE
   PRESET,PAPI_TOT_IIS,NOT_DERIVED,MAIN_UNIT_EXECUTED_INST
   PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
  
positive.code: PRESET,PAPI_BR_MSP,DERIVED_ADD,BRANCH_FLUSH_TH0,BRANCH_FLUSH_TH1
  PRESET,PAPI_BR_INS,DERIVED_ADD,BRANCH_COMMIT_TH0,BRANCH_COMMIT_TH1
  #
  
  CPU,arm_ac8
  PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXECUTED
  PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
  PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE
  
negative.code: PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS
  PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL
  PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS
  #
  CPU,mips_74k
  #
  PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES
  PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS
  PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE_ACCESSES
  PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE_MISSES
  PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESSES
  PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_MISSES
  PRESET,PAPI_L1_TCA,DERIVED_ADD,DCACHE_ACCESSES,ICACHE_ACCESSES
  PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE_MISSES,DCACHE_MISSES
  PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_CACHE_ACCESSES
  PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISSES
  PRESET,PAPI_FP_INS,NOT_DERIVED,FPU_INSNS
  PRESET,PAPI_INT_INS,NOT_DERIVED,INTEGER_INSNS
  PRESET,PAPI_LD_INS,NOT_DERIVED,LOAD_INSNS
  PRESET,PAPI_SR_INS,NOT_DERIVED,STORE_INSNS
  PRESET,PAPI_TLB_IM,NOT_DERIVED,JTLB_INSN_MISSES
  PRESET,PAPI_TLB_DM,NOT_DERIVED,JTLB_DATA_MISSES
  PRESET,PAPI_BR_CN,NOT_DERIVED,COND_BRANCH_INSNS
  PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_INSNS
  PRESET,PAPI_CSR_FAL,NOT_DERIVED,FAILED_SC_INSNS
  PRESET,PAPI_CSR_TOT,NOT_DERIVED,SC_INSNS
  PRESET,PAPI_FUL_ICY,NOT_DERIVED,DUAL_ISSUE_CYCLES
  PRESET,PAPI_STL_CCY,NOT_DERIVED,NO_INSN_CYCLES
  PRESET,PAPI_FUL_CCY,NOT_DERIVED,TWO_INSNS_CYCLES
  #
  CPU,MIPSICE9A
  #
  PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
  PRESET,PAPI_TOT_INS,NOT_DERIVED,CPU_INSEXEC
  PRESET,PAPI_L1_ICA,NOT_DERIVED,CPU_INSFETCH
  PRESET,PAPI_LD_INS,NOT_DERIVED,CPU_LOAD
  PRESET,PAPI_SR_INS,NOT_DERIVED,CPU_STORE
  PRESET,PAPI_CSR_FAL,NOT_DERIVED,CPU_SCFAIL
  PRESET,PAPI_CSR_TOT,NOT_DERIVED,CPU_SC
  PRESET,PAPI_FP_INS,NOT_DERIVED,CPU_FLOAT
  PRESET,PAPI_BR_INS,NOT_DERIVED,CPU_BRANCH
  PRESET,PAPI_TLB_IM,NOT_DERIVED,CPU_ITLBMISS
  PRESET,PAPI_TLB_TL,NOT_DERIVED,CPU_TLBTRAP
  PRESET,PAPI_TLB_DM,NOT_DERIVED,CPU_DTLBMISS
  PRESET,PAPI_BR_MSP,NOT_DERIVED,CPU_MISPRED
  PRESET,PAPI_L1_ICM,NOT_DERIVED,CPU_ICMISS
  PRESET,PAPI_L1_DCM,NOT_DERIVED,CPU_DCMISS
  PRESET,PAPI_MEM_SCY,NOT_DERIVED,CPU_MSTALL
  PRESET,PAPI_FUL_ICY,NOT_DERIVED,CPU_INSDUAL
  #
  CPU,MIPSICE9B
  #
  PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
  PRESET,PAPI_TOT_INS,NOT_DERIVED,CPU_INSEXEC
  PRESET,PAPI_L1_ICA,NOT_DERIVED,CPU_INSFETCH
  PRESET,PAPI_LD_INS,NOT_DERIVED,CPU_LOAD
  PRESET,PAPI_SR_INS,NOT_DERIVED,CPU_STORE
  PRESET,PAPI_CSR_FAL,NOT_DERIVED,CPU_SCFAIL
  PRESET,PAPI_CSR_TOT,NOT_DERIVED,CPU_SC
  PRESET,PAPI_FP_INS,NOT_DERIVED,CPU_FPARITH
  PRESET,PAPI_BR_INS,NOT_DERIVED,CPU_BRANCH
  PRESET,PAPI_TLB_IM,NOT_DERIVED,CPU_ITLBMISS
  PRESET,PAPI_TLB_TL,NOT_DERIVED,CPU_TLBTRAP
  PRESET,PAPI_TLB_DM,NOT_DERIVED,CPU_DTLBMISS
  PRESET,PAPI_BR_MSP,NOT_DERIVED,CPU_MISPRED
  PRESET,PAPI_L1_ICM,NOT_DERIVED,CPU_ICMISS
  PRESET,PAPI_L1_DCM,NOT_DERIVED,CPU_DCMISS
  PRESET,PAPI_MEM_SCY,NOT_DERIVED,CPU_MSTALL
  PRESET,PAPI_FUL_ICY,NOT_DERIVED,CPU_INSDUAL
  PRESET,PAPI_L2_TCM,NOT_DERIVED,CPU_L2MISSALL
  PRESET,PAPI_L2_TCA,NOT_DERIVED,CPU_L2REQ
  