anchor.diff:        :w20 :w21 :w22 :w23 :w24 :w25 :w26 :w27 :w28 :w29
         :w30)
        :gpr-32)
  +    ((:s0 :s1 :s2 :s3 :s4 :s5 :s6 :s7 :s8 :s9
  +      :s10 :s11 :s12 :s13 :s14 :s15 :s16 :s17 :s18 :s19
  +      :s20 :s21 :s22 :s23 :s24 :s25 :s26 :s27 :s28 :s29
  +      :s30 :s31)
  +     :fp-32)
  +    ((:d0 :d1 :d2 :d3 :d4 :d5 :d6 :d7 :d8 :d9
  +      :d10 :d11 :d12 :d13 :d14 :d15 :d16 :d17 :d18 :d19
  +      :d20 :d21 :d22 :d23 :d24 :d25 :d26 :d27 :d28 :d29
  +      :d30 :d31)
  +     :fp-64)
       (:wsp :wsp)
       (:sp :sp)
       (:wzr :wzr)
  
positive.code:                             (ash (register-number mhs) +rn-shift+)
                              (ash (register-number rhs) +rm-shift+)))
    (return-from instruction t))
  
negative.code:   (when restrict-to
      (assert (member (register-class register) restrict-to)))
    (ecase register
      ((:x0 :w0 :d0 :s0) 0)
      ((:x1 :w1 :d1 :s1) 1)
      ((:x2 :w2 :d2 :s2) 2)
      ((:x3 :w3 :d3 :s3) 3)
      ((:x4 :w4 :d4 :s4) 4)
      ((:x5 :w5 :d5 :s5) 5)
      ((:x6 :w6 :d6 :s6) 6)
      ((:x7 :w7 :d7 :s7) 7)
      ((:x8 :w8 :d8 :s8) 8)
      ((:x9 :w9 :d9 :s9) 9)
      ((:x10 :w10 :d10 :s10) 10)
      ((:x11 :w11 :d11 :s11) 11)
      ((:x12 :w12 :d12 :s12) 12)
      ((:x13 :w13 :d13 :s13) 13)
      ((:x14 :w14 :d14 :s14) 14)
      ((:x15 :w15 :d15 :s15) 15)
      ((:x16 :w16 :d16 :s16) 16)
      ((:x17 :w17 :d17 :s17) 17)
      ((:x18 :w18 :d18 :s18) 18)
      ((:x19 :w19 :d19 :s19) 19)
      ((:x20 :w20 :d20 :s20) 20)
      ((:x21 :w21 :d21 :s21) 21)
      ((:x22 :w22 :d22 :s22) 22)
      ((:x23 :w23 :d23 :s23) 23)
      ((:x24 :w24 :d24 :s24) 24)
      ((:x25 :w25 :d25 :s25) 25)
      ((:x26 :w26 :d26 :s26) 26)
      ((:x27 :w27 :d27 :s27) 27)
      ((:x28 :w28 :d28 :s28) 28)
      ((:x29 :w29 :d29 :s29) 29)
      ((:x30 :w30 :d30 :s30) 30)
      ((:wzr :xzr :sp :d31 :s31) 31)))
  
  (defun parse-address (address)
    (assert (consp address))
  