anchor.diff:                              (ash (register-number mhs) +rn-shift+)
                               (ash (register-number rhs) +rm-shift+)))
     (return-from instruction t))
  +
  +(define-instruction scvtf (lhs rhs)
  +  (check-register-class lhs :fp-64 :fp-32)
  +  (check-register-class rhs :gpr-64 :gpr-32)
  +  (emit-instruction (logior (if (eql (register-class rhs) :gpr-64)
  +                                #x80000000
  +                                #x00000000)
  +                            #x1E220000
  +                            (if (eql (register-class lhs) :fp-64)
  +                                #x00400000
  +                                #x00000000)
  +                            (ash (register-number rhs) +rn-shift+)
  +                            (ash (register-number lhs) +rd-shift+)))
  +  (return-from instruction t))
  +
  +(define-instruction fmov (lhs rhs)
  +  (let ((lhs-class (register-class lhs))
  +        (rhs-class (register-class rhs)))
  +    (multiple-value-bind (sf type rmode opcode)
  +        (cond ((and (eql lhs-class :fp-32)
  +                    (eql rhs-class :gpr-32))
  +               (values #b0 #b00 #b00 #b111))
  +              ((and (eql lhs-class :gpr-32)
  +                    (eql rhs-class :fp-32))
  +               (values #b0 #b00 #b00 #b111))
  +              ((and (eql lhs-class :fp-64)
  +                    (eql rhs-class :gpr-64))
  +               (values #b1 #b01 #b00 #b111))
  +              ((and (eql lhs-class :gpr-64)
  +                    (eql rhs-class :fp-64))
  +               (values #b1 #b01 #b00 #b110))
  +              (t
  +               (error "Unsupported FMOV operand combination ~S and ~S."
  +                      lhs rhs)))
  +      (emit-instruction (logior (ash sf 31)
  +                                #x1E260000
  +                                (ash type 22)
  +                                (ash rmode 19)
  +                                (ash opcode 16)
  +                                (ash (register-number rhs) +rn-shift+)
  +                                (ash (register-number lhs) +rd-shift+)))
  +      (return-from instruction t))))
  
positive.code:   (when restrict-to
      (assert (member (register-class register) restrict-to)))
    (ecase register
      ((:x0 :w0) 0)
      ((:x1 :w1) 1)
      ((:x2 :w2) 2)
      ((:x3 :w3) 3)
      ((:x4 :w4) 4)
      ((:x5 :w5) 5)
      ((:x6 :w6) 6)
      ((:x7 :w7) 7)
      ((:x8 :w8) 8)
      ((:x9 :w9) 9)
      ((:x10 :w10) 10)
      ((:x11 :w11) 11)
      ((:x12 :w12) 12)
      ((:x13 :w13) 13)
      ((:x14 :w14) 14)
      ((:x15 :w15) 15)
      ((:x16 :w16) 16)
      ((:x17 :w17) 17)
      ((:x18 :w18) 18)
      ((:x19 :w19) 19)
      ((:x20 :w20) 20)
      ((:x21 :w21) 21)
      ((:x22 :w22) 22)
      ((:x23 :w23) 23)
      ((:x24 :w24) 24)
      ((:x25 :w25) 25)
      ((:x26 :w26) 26)
      ((:x27 :w27) 27)
      ((:x28 :w28) 28)
      ((:x29 :w29) 29)
      ((:x30 :w30) 30)
      ((:wzr :xzr :sp) 31)))
  
  (defun parse-address (address)
    (assert (consp address))
  
negative.code:       :w20 :w21 :w22 :w23 :w24 :w25 :w26 :w27 :w28 :w29
        :w30)
       :gpr-32)
      ((:s0 :s1 :s2 :s3 :s4 :s5 :s6 :s7 :s8 :s9
        :s10 :s11 :s12 :s13 :s14 :s15 :s16 :s17 :s18 :s19
        :s20 :s21 :s22 :s23 :s24 :s25 :s26 :s27 :s28 :s29
        :s30 :s31)
       :fp-32)
      ((:d0 :d1 :d2 :d3 :d4 :d5 :d6 :d7 :d8 :d9
        :d10 :d11 :d12 :d13 :d14 :d15 :d16 :d17 :d18 :d19
        :d20 :d21 :d22 :d23 :d24 :d25 :d26 :d27 :d28 :d29
        :d30 :d31)
       :fp-64)
      (:wsp :wsp)
      (:sp :sp)
      (:wzr :wzr)
  