     0 4 LOAD32 rc-absolute-ppc-2/2 rt-primitive jit-rel
     4 MTLR
     BLRL
-    jit-load-context
+    jit-restore-context
 ] jit-primitive jit-define
 
 [ 0 BL rc-relative-ppc-3 rt-xt-pic jit-rel ] jit-word-call jit-define

: jit-save-context ( -- )
    4 vm-reg 0 LWZ
    1 4 0 STW
    ds-reg vm-reg 8 STW
    rs-reg vm-reg 12 STW ;

: jit-load-context ( -- )
    4 vm-reg 0 LWZ
    ds-reg vm-reg 8 LWZ
    rs-reg vm-reg 12 LWZ ;

[
    0 3 LOAD32 rc-absolute-ppc-2/2 rt-literal jit-rel

[
    [ BNE ] [ 0 B rc-relative-ppc-3 rt-xt jit-rel ] jit-conditional*
] pic-hit jit-define

! Inline cache miss entry points
: jit-load-return-address ( -- ) 6 MFLR ;

! These are always in tail position with an existing stack
! frame, and the stack. The frame setup takes this into account.
: jit-inline-cache-miss ( -- )
    jit-save-context
    3 6 MR
    4 vm-reg MR
    0 5 LOAD32 "inline_cache_miss" f rc-absolute-ppc-2/2 jit-dlsym
    5 MTLR
    BLRL
    jit-restore-context ;

[ jit-load-return-address jit-inline-cache-miss ]
[ 3 MTLR BLRL ]
[ 3 MTCTR BCTR ]
\ inline-cache-miss define-sub-primitive*

[ jit-inline-cache-miss ]
[ 3 MTLR BLRL ]
[ 3 MTCTR BCTR ]
\ inline-cache-miss-tail define-sub-primitive*

! ! ! Megamorphic caches

