anchor.diff:    begin i2c-busy? 0= until
   ;
   
  -
  -
   \ debugging
   : i2c? cr I2C1-CR1 h@ hex. I2C1-CR2 h@ hex. I2C1-SR1 h@ hex. I2C1-SR2 h@ hex. ;
   
   \ Low level register setting and checking
  -: i2c-DR!     ( c -- )  I2C1-DR c! ;                 \ Writes data register
  -: i2c-DR@     (  -- c ) I2C1-DR c@ ;                 \ Writes data register
  +: i2c-DR!     ( c -- )  I2C1-DR c! ;            \ Writes data register
  +: i2c-DR@     (  -- c ) I2C1-DR c@ ;            \ Writes data register
   : i2c-start!  ( -- )    8 bit I2C1-CR1 hbis! ;
   : i2c-stop!   ( -- )    9 bit I2C1-CR1 hbis! ;
  -: i2c-AF-0 ( -- )  10 bit I2C1-SR1 hbic! ;      \ Clars AF flag
  -: i2c-START-0 ( -- )   8 bit I2C1-CR1 hbic! ;      \ Clears START condition
  +: i2c-AF-0 ( -- )  10 bit I2C1-SR1 hbic! ;      \ Clears AF flag
  +: i2c-START-0 ( -- )   8 bit I2C1-CR1 hbic! ;   \ Clears START condition
   : i2c-SR1-flag? ( u -- ) I2C1-SR1 hbit@ ;
   : i2c-ACK-1 ( -- ) 10 bit I2C1-CR1 hbis! ;
   : i2c-ACK-0 ( -- ) 10 bit I2C1-CR1 hbic! ;
  
positive.code: 
  : i2c-xfer ( u -- nak) \ prepares for an nbyte reply. Use after i2c-addr. Stops i2c after completion.
      dup i2c.cnt !
      case     
        2 of    \ cnt = 2
          i2c-start  \ set start bit,  wait for start condition
  
  
negative.code: : i2c-POS-0 ( -- ) 11 bit I2C1-CR1 hbic! ;
  
  \ Low level status checking
  : i2c-sb?  ( -- b)   0  bit i2c-SR1-flag? ;     \ Gets start bit flag
  : i2c-nak? ( -- b)   10 bit i2c-SR1-flag? ;     \ Gets AF bit flag
  : i2c-TxE? ( -- b)   7  bit i2c-SR1-flag? ;     \ TX register empty
  : i2c-ADDR? ( -- b)  1  bit i2c-SR1-flag? ;     \ ADDR bit
  : i2c-MSL? ( -- b)   0  bit I2C1-SR2 hbit@ ;    \ MSL bit
  
  : i2c-SR1-wait ( u -- ) begin dup i2c-SR1-flag? until drop ; \ Waits until SR1 meets bit mask
  : i2c-SR1-!wait ( u -- ) begin dup i2c-SR1-flag? 0= until drop ;
  
  0  bit constant i2c-SR1-SB
  