Commit 6982428d by Stefan Tauner

### User manual: rename and split files to match chapter order again

parent c277e393
 ... ... @@ -325,112 +325,3 @@ generated by majority voting over the three \ac{TMR} domains. Faults in \ac{TMR} domain 0 are masked and thus are not visible. When \ac{TMR} is enabled, the LEDs on the board show (1) if an error is detected by the voter (one domain disagrees with the others) and (2) in which voter (Red, Green, Blue) the error is detected. \section{Yosys Demo} Another demo design was implemented in Verilog in order todemonstrate the interoperability with the open-source synthesis framework Yosys~\footnote{http://www.clifford.at/yosys/,~visited on September 14, 2017} and the IceStorm toolchain~\footnote{http://www.clifford.at/icestorm/,~visited on September 14, 2017}. The target board for this design is the \emph{HX8K Breakout Board}~\footnote{http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx,~visited on September 14, 2017} offered by Lattice Semiconductor Corp. Additionally, a VGA DAC extension board such as the XESS StickIt VGA module~\footnote{http://www.xess.com/shop/product/stickit-vga/,~visited on September 14, 2017} is needed. The design generates SVGA 800x600 output with 36~MHz pixel clock generated by an iCE40 PLL from the 12~MHz on-board oscillator. It moves the content of a BRAM in a circular motion on the screen. On the 8 on-board LEDs the current state of the 8-bit frame counter is shown. \subsection{Hardware Setup} \begin{minipage}[h]{\linewidth} \centering \begin{minipage}{0.45\linewidth} FIJI uses the FTDI chip on the breakout board to communicate with the fault injection logic. The VGA extension board shall be connected to the 40 pin extension header as shown in Figure~\ref{fig:hx8k_connections}. The pin connections are also documented in the physical constraint files for the initial and the instrumented implementations. \end{minipage} \hspace{0.05\linewidth} \begin{minipage}{0.45\linewidth} \begin{figure}[H] \centering \includegraphics[height=20em]{img/hx8k_j2.pdf} \caption{HX8K Connections} \label{fig:hx8k_connections} \end{figure} \end{minipage} \end{minipage} \subsection{Software Setup} The Yosys Demo requires a Linux system with the \texttt{yosys}, \texttt{arachne-pnr}, and the IceStorm binaries (\texttt{icepack}, \ldots) in the system's execution path. The entire instrumentation process is directed by GNU make. As Yosys does not support VHDL as an input language, Synplify is required to synthesize the FIJI logic and the wrapper. The original synthesis step, the entire netlist instrumentation process, as well as the final synthesis step combining the wrapper and the instrumented netlist, is handled by Yosys. Furthermore, a \texttt{FIJI\_ROOT} environment variable shall point to the root directory where FIJI was cloned from the git repository. \subsection{Executing the Demo Flow} The entire instrumentation process is executed by two Makefiles (to be executed in that order): \begin{enumerate} \item The initial synthesis step as well as the FIJI Setup and the FIJI Instrument tool are executed by the Makfile found in \texttt{docs/demos/tinyvga/impl/original/}. Run \begin{lstlisting}[style=shell,gobble=12] $make fiji-instrument \end{lstlisting} to synthesize the RTL design to a Verilog netlist, call FIJI Setup, and finally instrument the netlist as required. A FIJI configuration for some faults has already been provided. If necessary, select the correct nets/drivers (other Yosys versions might generate a differing netlist). The optional target \texttt{prog} generates a bitstream for the original design and downloads it to a connected HX8K breakout board. \item The second synthesis step, as well as run-time fault injection is executed by the Makefile found in the directory \texttt{docs/demos/tinyvga/impl/instrumented/}. To download the instrumented design to a connected board and launch FIJI EE subsequently, execute \begin{lstlisting}[style=shell,gobble=12]$ make prog && make fiji-launch \end{lstlisting} in this directory. This Makefile automatically synthesizes the VHDL parts to a netlist using Synplify (the command and options are defined in this file), combines the FIJI logic and the instrumented netlist using Yosys, and finally generates a bitstream for the HX8K device using the IceStorm tools. \end{enumerate} \subsection{Run-Time Fault Injection} The provided FIJI configuration instruments the MSBs of the three VGA color signals, as well as the row and column addresses for the image source on-chip RAM. Once the design is downloaded and the FIJI EE GUI is launched, the following things may be done: \begin{enumerate} \item Configure the correct serial device to communicate with the FIJI hardware. A udev rule that symlinks the HX8K board to \texttt{/dev/ttyHX8K} may be useful. \item Check the connectivity by pressing the \emph{Update} button. If no error message is shown in the logging box, the design is ready for fault injection. \item Perform sequence, manual, or random fault injections. Faults are immediately visible by distorted VGA output. Since the provided FIJI configuration does not alter the VGA timing, this should work with all monitors. \end{enumerate}
 \section{Yosys Demo} Another demo design was implemented in Verilog in order todemonstrate the interoperability with the open-source synthesis framework Yosys~\footnote{http://www.clifford.at/yosys/,~visited on September 14, 2017} and the IceStorm toolchain~\footnote{http://www.clifford.at/icestorm/,~visited on September 14, 2017}. The target board for this design is the \emph{HX8K Breakout Board}~\footnote{http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx,~visited on September 14, 2017} offered by Lattice Semiconductor Corp. Additionally, a VGA DAC extension board such as the XESS StickIt VGA module~\footnote{http://www.xess.com/shop/product/stickit-vga/,~visited on September 14, 2017} is needed. The design generates SVGA 800x600 output with 36~MHz pixel clock generated by an iCE40 PLL from the 12~MHz on-board oscillator. It moves the content of a BRAM in a circular motion on the screen. On the 8 on-board LEDs the current state of the 8-bit frame counter is shown. \subsection{Hardware Setup} \begin{minipage}[h]{\linewidth} \centering \begin{minipage}{0.45\linewidth} FIJI uses the FTDI chip on the breakout board to communicate with the fault injection logic. The VGA extension board shall be connected to the 40 pin extension header as shown in Figure~\ref{fig:hx8k_connections}. The pin connections are also documented in the physical constraint files for the initial and the instrumented implementations. \end{minipage} \hspace{0.05\linewidth} \begin{minipage}{0.45\linewidth} \begin{figure}[H] \centering \includegraphics[height=20em]{img/hx8k_j2.pdf} \caption{HX8K Connections} \label{fig:hx8k_connections} \end{figure} \end{minipage} \end{minipage} \subsection{Software Setup} The Yosys Demo requires a Linux system with the \texttt{yosys}, \texttt{arachne-pnr}, and the IceStorm binaries (\texttt{icepack}, \ldots) in the system's execution path. The entire instrumentation process is directed by GNU make. As Yosys does not support VHDL as an input language, Synplify is required to synthesize the FIJI logic and the wrapper. The original synthesis step, the entire netlist instrumentation process, as well as the final synthesis step combining the wrapper and the instrumented netlist, is handled by Yosys. Furthermore, a \texttt{FIJI\_ROOT} environment variable shall point to the root directory where FIJI was cloned from the git repository. \subsection{Executing the Demo Flow} The entire instrumentation process is executed by two Makefiles (to be executed in that order): \begin{enumerate} \item The initial synthesis step as well as the FIJI Setup and the FIJI Instrument tool are executed by the Makfile found in \texttt{docs/demos/tinyvga/impl/original/}. Run \begin{lstlisting}[style=shell,gobble=12] $make fiji-instrument \end{lstlisting} to synthesize the RTL design to a Verilog netlist, call FIJI Setup, and finally instrument the netlist as required. A FIJI configuration for some faults has already been provided. If necessary, select the correct nets/drivers (other Yosys versions might generate a differing netlist). The optional target \texttt{prog} generates a bitstream for the original design and downloads it to a connected HX8K breakout board. \item The second synthesis step, as well as run-time fault injection is executed by the Makefile found in the directory \texttt{docs/demos/tinyvga/impl/instrumented/}. To download the instrumented design to a connected board and launch FIJI EE subsequently, execute \begin{lstlisting}[style=shell,gobble=12]$ make prog && make fiji-launch \end{lstlisting} in this directory. This Makefile automatically synthesizes the VHDL parts to a netlist using Synplify (the command and options are defined in this file), combines the FIJI logic and the instrumented netlist using Yosys, and finally generates a bitstream for the HX8K device using the IceStorm tools. \end{enumerate} \subsection{Run-Time Fault Injection} The provided FIJI configuration instruments the MSBs of the three VGA color signals, as well as the row and column addresses for the image source on-chip RAM. Once the design is downloaded and the FIJI EE GUI is launched, the following things may be done: \begin{enumerate} \item Configure the correct serial device to communicate with the FIJI hardware. A udev rule that symlinks the HX8K board to \texttt{/dev/ttyHX8K} may be useful. \item Check the connectivity by pressing the \emph{Update} button. If no error message is shown in the logging box, the design is ready for fault injection. \item Perform sequence, manual, or random fault injections. Faults are immediately visible by distorted VGA output. Since the provided FIJI configuration does not alter the VGA timing, this should work with all monitors. \end{enumerate}
 ... ... @@ -25,7 +25,8 @@ \input{content/05-instrumentation.tex} \input{content/06-synthesis.tex} \input{content/07-runtime.tex} \input{content/08-demo.tex} \input{content/08-demo_tmr.tex} \input{content/09-demo_yosys.tex} \newpage % Bibliography ... ... @@ -53,8 +54,8 @@ \newpage \appendix \input{content/09-appendix-LFSR.tex} \input{content/10-appendix-resources.tex} \input{content/appendix-01-LFSR.tex} \input{content/appendix-02-resources.tex} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \end{document}
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