hwt/serializer/verilog/utils.py
def verilogTypeOfSig(signalItem):
    """
    Check if is register or wire
    """
    driver_cnt = len(signalItem.drivers)
    if signalItem._const or driver_cnt > 1 or\
       arr_any(signalItem.drivers, _isEventDependentDriver):
        return SIGNAL_TYPE.REG
    else:
        if driver_cnt == 1:
            d = signalItem.drivers[0]
            if not isinstance(d, (Assignment, PortItem)):
                return SIGNAL_TYPE.REG

        return SIGNAL_TYPE.WIRE
def verilogTypeOfSig(signalItem):
    """
    Check if is register or wire
    """
    driver_cnt = len(signalItem.drivers)
    if signalItem._const or driver_cnt > 1 or\
       arr_any(signalItem.drivers, _isEventDependentDriver):
        return SIGNAL_TYPE.REG
    else:
        if driver_cnt == 1:
            d = signalItem.drivers[0]
            if not isinstance(d, (Assignment, PortItem)):
                return SIGNAL_TYPE.REG

        return SIGNAL_TYPE.WIRE
def verilogTypeOfSig ( signalItem ) : driver_cnt = len ( signalItem . drivers ) if signalItem . _const or driver_cnt > 1 or arr_any ( signalItem . drivers , _isEventDependentDriver ) : return SIGNAL_TYPE . REG else : if driver_cnt == 1 : d = signalItem . drivers [ 0 ] if not isinstance ( d , ( Assignment , PortItem ) ) : return SIGNAL_TYPE . REG return SIGNAL_TYPE . WIRE
Check if is register or wire
Check if is register or wire