The Cell Broad Engine (BE) Processor has unique memory access architecture besides its powerful computing engines. Many computing-intensive applications have been ported to Cell BE successfully. But memory-intensive applications are rarely investigated except for several micro benchmarks. Since Cell BE has powerful software visible DMA engine, this paper studies on whether Cell BE is suit for applica- tions with large amount of random memory accesses. Two benchmarks, GUPS and SSCA#2, are used. The latter is a rather complex one that in representative of real world graph analysis applications. We find both benchmarks have good performance on Cell BE based IBM QS20 22. Com- pared with 2 conventional multi-processor systems with the same core thread number, GUPS is about 40-80 fast and SSCA#2 about 17-30 fast. The dynamic load balanc- ing and software pipeline for optimizing SSCA#2 are intro- duced. Based on the experiment, the potential of Cell BE for random access is analyzed in detail as well as its limita- tions of memory controller, atomic engine and TLB manage- ment.Our research shows although more programming effort are needed, Cell BE has the potencial for irregular memory access applications.
@cite_1: Multi-core processors are a shift of paradigm in computer architecture that promises a dramatic increase in performance. But multi-core processors also bring an unprecedented level of complexity in algorithmic design and software development. In this paper we describe the challenges and design choices involved in parallelizing a breadth-first search (BFS) algorithm on a state-of-the-art multi-core processor, the Cell Broadband Engine (Cell BE). Our experiments obtained on a pre-production Cell BE board running at 3.2 GHz show almost linear speedups when using multiple synergistic processing units, and an impressive level of performance when compared to other processors. The Cell BE is typically an order of magnitude faster than conventional processors, such as the AMD Opteron and the Intel Pentium 4 and Woodcrest, an order of magnitude faster than the MTA-2 multi-threaded processor, and two orders of magnitude faster than a BlueGene L processor.
@cite_1 designed a delicate lock-free BFS algorithm on Cell BE. The algorithm depends on a bitmap in SPU's on-chip memory. During the optimization of SSCA2 over Cell BE, we found the main obstacle was the global atomic update. Each atomic operation will pause the pipeline with idle waiting. However it is not easy to design a lock-free algorithm due to the amount of globally random data updates. The process of SSCA2 need @math and @math set to be updated at the same time during the BFS expansion. These data structure are too large to fit in the on-chip memory.