@Test public void testGetNetSynthNetlist() throws JSONException, IOException, CelloException { final JSONArray motifs = YosysDataUtils.getMotifLibrary(NetSynthUtilsTest.targetData); final Path dir = Files.createTempDirectory("cello_"); final Netlist n = NetSynthUtils.getNetSynthNetlist(NetSynthUtilsTest.netlist, motifs, dir.toString()); final String output = dir.toString() + Utils.getFileSeparator() + NetSynthUtilsTest.netlist.getInputFilename() + "_netSynth.json"; NetlistUtils.writeJsonForNetlist(n, output); FileUtils.deleteDirectory(dir.toFile()); }
public static Netlist getNetSynthNetlist( final Netlist netlist, final JSONArray motifs, final String outputDir) throws JSONException, IOException, CelloException { Netlist rtn = null; final Path path = NetSynthUtils.initResources(); final NetSynth n = new NetSynth("netSynth", path.toString() + Utils.getFileSeparator(), outputDir); final String verilog = NetSynthUtils.getVerilog(netlist); final String verilogFilePath = outputDir + Utils.getFileSeparator() + Utils.getFilename(netlist.getInputFilename()) + ".struct.v"; Utils.writeToFile(verilog, verilogFilePath); final List<NetSynthSwitch> args = new ArrayList<>(); args.add(NetSynthSwitch.output_or); final org.json.JSONArray m = NetSynthUtils.getMotifJson(motifs); final DAGW dagw = n.runNetSynth(verilogFilePath, args, m); n.cleanDirectory(); FileUtils.deleteDirectory(path.toFile()); rtn = new Netlist(); rtn.setName(netlist.getName()); rtn.setType(netlist.getType()); rtn.setIdx(netlist.getIdx()); rtn.setInputFilename(netlist.getInputFilename()); rtn.setResultNetlistData(new ResultNetlistData(netlist.getResultNetlistData())); final Map<Gate, NetlistNode> nodeMap = new HashMap<>(); final NodeNamer nNamer = new NodeNamer(); final EdgeNamer eNamer = new EdgeNamer(); for (final Wire w : dagw.Wires) { final NetlistEdge e = new NetlistEdge(); NetlistNode src = nodeMap.get(w.to); if (w.to.equals(w.from)) { continue; } if (w.to.name.isEmpty()) { w.to.name = nNamer.next(); } if (src == null) { src = new NetlistNode(); src.setName(w.to.name); src.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.to.type)); nodeMap.put(w.to, src); rtn.addVertex(src); } NetlistNode dst = nodeMap.get(w.from); if (w.from.name.isEmpty()) { w.from.name = nNamer.next(); } if (dst == null) { dst = new NetlistNode(); dst.setName(w.from.name); dst.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.from.type)); nodeMap.put(w.from, dst); rtn.addVertex(dst); } e.setSrc(src); e.setDst(dst); e.setName(eNamer.next(src, dst)); dst.addInEdge(e); src.addOutEdge(e); rtn.addEdge(e); } return rtn; }
NetSynthUtils { public static Netlist getNetSynthNetlist( final Netlist netlist, final JSONArray motifs, final String outputDir) throws JSONException, IOException, CelloException { Netlist rtn = null; final Path path = NetSynthUtils.initResources(); final NetSynth n = new NetSynth("netSynth", path.toString() + Utils.getFileSeparator(), outputDir); final String verilog = NetSynthUtils.getVerilog(netlist); final String verilogFilePath = outputDir + Utils.getFileSeparator() + Utils.getFilename(netlist.getInputFilename()) + ".struct.v"; Utils.writeToFile(verilog, verilogFilePath); final List<NetSynthSwitch> args = new ArrayList<>(); args.add(NetSynthSwitch.output_or); final org.json.JSONArray m = NetSynthUtils.getMotifJson(motifs); final DAGW dagw = n.runNetSynth(verilogFilePath, args, m); n.cleanDirectory(); FileUtils.deleteDirectory(path.toFile()); rtn = new Netlist(); rtn.setName(netlist.getName()); rtn.setType(netlist.getType()); rtn.setIdx(netlist.getIdx()); rtn.setInputFilename(netlist.getInputFilename()); rtn.setResultNetlistData(new ResultNetlistData(netlist.getResultNetlistData())); final Map<Gate, NetlistNode> nodeMap = new HashMap<>(); final NodeNamer nNamer = new NodeNamer(); final EdgeNamer eNamer = new EdgeNamer(); for (final Wire w : dagw.Wires) { final NetlistEdge e = new NetlistEdge(); NetlistNode src = nodeMap.get(w.to); if (w.to.equals(w.from)) { continue; } if (w.to.name.isEmpty()) { w.to.name = nNamer.next(); } if (src == null) { src = new NetlistNode(); src.setName(w.to.name); src.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.to.type)); nodeMap.put(w.to, src); rtn.addVertex(src); } NetlistNode dst = nodeMap.get(w.from); if (w.from.name.isEmpty()) { w.from.name = nNamer.next(); } if (dst == null) { dst = new NetlistNode(); dst.setName(w.from.name); dst.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.from.type)); nodeMap.put(w.from, dst); rtn.addVertex(dst); } e.setSrc(src); e.setDst(dst); e.setName(eNamer.next(src, dst)); dst.addInEdge(e); src.addOutEdge(e); rtn.addEdge(e); } return rtn; } }
NetSynthUtils { public static Netlist getNetSynthNetlist( final Netlist netlist, final JSONArray motifs, final String outputDir) throws JSONException, IOException, CelloException { Netlist rtn = null; final Path path = NetSynthUtils.initResources(); final NetSynth n = new NetSynth("netSynth", path.toString() + Utils.getFileSeparator(), outputDir); final String verilog = NetSynthUtils.getVerilog(netlist); final String verilogFilePath = outputDir + Utils.getFileSeparator() + Utils.getFilename(netlist.getInputFilename()) + ".struct.v"; Utils.writeToFile(verilog, verilogFilePath); final List<NetSynthSwitch> args = new ArrayList<>(); args.add(NetSynthSwitch.output_or); final org.json.JSONArray m = NetSynthUtils.getMotifJson(motifs); final DAGW dagw = n.runNetSynth(verilogFilePath, args, m); n.cleanDirectory(); FileUtils.deleteDirectory(path.toFile()); rtn = new Netlist(); rtn.setName(netlist.getName()); rtn.setType(netlist.getType()); rtn.setIdx(netlist.getIdx()); rtn.setInputFilename(netlist.getInputFilename()); rtn.setResultNetlistData(new ResultNetlistData(netlist.getResultNetlistData())); final Map<Gate, NetlistNode> nodeMap = new HashMap<>(); final NodeNamer nNamer = new NodeNamer(); final EdgeNamer eNamer = new EdgeNamer(); for (final Wire w : dagw.Wires) { final NetlistEdge e = new NetlistEdge(); NetlistNode src = nodeMap.get(w.to); if (w.to.equals(w.from)) { continue; } if (w.to.name.isEmpty()) { w.to.name = nNamer.next(); } if (src == null) { src = new NetlistNode(); src.setName(w.to.name); src.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.to.type)); nodeMap.put(w.to, src); rtn.addVertex(src); } NetlistNode dst = nodeMap.get(w.from); if (w.from.name.isEmpty()) { w.from.name = nNamer.next(); } if (dst == null) { dst = new NetlistNode(); dst.setName(w.from.name); dst.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.from.type)); nodeMap.put(w.from, dst); rtn.addVertex(dst); } e.setSrc(src); e.setDst(dst); e.setName(eNamer.next(src, dst)); dst.addInEdge(e); src.addOutEdge(e); rtn.addEdge(e); } return rtn; }  }
NetSynthUtils { public static Netlist getNetSynthNetlist( final Netlist netlist, final JSONArray motifs, final String outputDir) throws JSONException, IOException, CelloException { Netlist rtn = null; final Path path = NetSynthUtils.initResources(); final NetSynth n = new NetSynth("netSynth", path.toString() + Utils.getFileSeparator(), outputDir); final String verilog = NetSynthUtils.getVerilog(netlist); final String verilogFilePath = outputDir + Utils.getFileSeparator() + Utils.getFilename(netlist.getInputFilename()) + ".struct.v"; Utils.writeToFile(verilog, verilogFilePath); final List<NetSynthSwitch> args = new ArrayList<>(); args.add(NetSynthSwitch.output_or); final org.json.JSONArray m = NetSynthUtils.getMotifJson(motifs); final DAGW dagw = n.runNetSynth(verilogFilePath, args, m); n.cleanDirectory(); FileUtils.deleteDirectory(path.toFile()); rtn = new Netlist(); rtn.setName(netlist.getName()); rtn.setType(netlist.getType()); rtn.setIdx(netlist.getIdx()); rtn.setInputFilename(netlist.getInputFilename()); rtn.setResultNetlistData(new ResultNetlistData(netlist.getResultNetlistData())); final Map<Gate, NetlistNode> nodeMap = new HashMap<>(); final NodeNamer nNamer = new NodeNamer(); final EdgeNamer eNamer = new EdgeNamer(); for (final Wire w : dagw.Wires) { final NetlistEdge e = new NetlistEdge(); NetlistNode src = nodeMap.get(w.to); if (w.to.equals(w.from)) { continue; } if (w.to.name.isEmpty()) { w.to.name = nNamer.next(); } if (src == null) { src = new NetlistNode(); src.setName(w.to.name); src.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.to.type)); nodeMap.put(w.to, src); rtn.addVertex(src); } NetlistNode dst = nodeMap.get(w.from); if (w.from.name.isEmpty()) { w.from.name = nNamer.next(); } if (dst == null) { dst = new NetlistNode(); dst.setName(w.from.name); dst.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.from.type)); nodeMap.put(w.from, dst); rtn.addVertex(dst); } e.setSrc(src); e.setDst(dst); e.setName(eNamer.next(src, dst)); dst.addInEdge(e); src.addOutEdge(e); rtn.addEdge(e); } return rtn; }  static String escapeSpecialCharacters(final String str); static String getVerilog(final Netlist netlist); static String getNodeType(final Gate.GateType type); static Netlist getNetSynthNetlist(
      final Netlist netlist, final JSONArray motifs, final String outputDir); }
NetSynthUtils { public static Netlist getNetSynthNetlist( final Netlist netlist, final JSONArray motifs, final String outputDir) throws JSONException, IOException, CelloException { Netlist rtn = null; final Path path = NetSynthUtils.initResources(); final NetSynth n = new NetSynth("netSynth", path.toString() + Utils.getFileSeparator(), outputDir); final String verilog = NetSynthUtils.getVerilog(netlist); final String verilogFilePath = outputDir + Utils.getFileSeparator() + Utils.getFilename(netlist.getInputFilename()) + ".struct.v"; Utils.writeToFile(verilog, verilogFilePath); final List<NetSynthSwitch> args = new ArrayList<>(); args.add(NetSynthSwitch.output_or); final org.json.JSONArray m = NetSynthUtils.getMotifJson(motifs); final DAGW dagw = n.runNetSynth(verilogFilePath, args, m); n.cleanDirectory(); FileUtils.deleteDirectory(path.toFile()); rtn = new Netlist(); rtn.setName(netlist.getName()); rtn.setType(netlist.getType()); rtn.setIdx(netlist.getIdx()); rtn.setInputFilename(netlist.getInputFilename()); rtn.setResultNetlistData(new ResultNetlistData(netlist.getResultNetlistData())); final Map<Gate, NetlistNode> nodeMap = new HashMap<>(); final NodeNamer nNamer = new NodeNamer(); final EdgeNamer eNamer = new EdgeNamer(); for (final Wire w : dagw.Wires) { final NetlistEdge e = new NetlistEdge(); NetlistNode src = nodeMap.get(w.to); if (w.to.equals(w.from)) { continue; } if (w.to.name.isEmpty()) { w.to.name = nNamer.next(); } if (src == null) { src = new NetlistNode(); src.setName(w.to.name); src.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.to.type)); nodeMap.put(w.to, src); rtn.addVertex(src); } NetlistNode dst = nodeMap.get(w.from); if (w.from.name.isEmpty()) { w.from.name = nNamer.next(); } if (dst == null) { dst = new NetlistNode(); dst.setName(w.from.name); dst.getResultNetlistNodeData().setNodeType(NetSynthUtils.getNodeType(w.from.type)); nodeMap.put(w.from, dst); rtn.addVertex(dst); } e.setSrc(src); e.setDst(dst); e.setName(eNamer.next(src, dst)); dst.addInEdge(e); src.addOutEdge(e); rtn.addEdge(e); } return rtn; }  static String escapeSpecialCharacters(final String str); static String getVerilog(final Netlist netlist); static String getNodeType(final Gate.GateType type); static Netlist getNetSynthNetlist(
      final Netlist netlist, final JSONArray motifs, final String outputDir);  }