@Test public void testGetVerilog() { NetSynthUtils.getVerilog(NetSynthUtilsTest.netlist); }
public static String getVerilog(final Netlist netlist) { String rtn = ""; final Collection<String> input = new ArrayList<>(); final Collection<String> output = new ArrayList<>(); for (int i = 0; i < netlist.getNumVertex(); i++) { final NetlistNode node = netlist.getVertexAtIdx(i); if (LSResultsUtils.isPrimaryInput(node)) { input.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } if (LSResultsUtils.isPrimaryOutput(node)) { output.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } } final String i = String.join(", ", input); final String o = String.join(", ", output); rtn += String.format("module %s (input %s, output %s);", netlist.getName(), i, o); rtn += Utils.getNewLine() + Utils.getNewLine(); for (int j = 0; j < netlist.getNumEdge(); j++) { final NetlistEdge e = netlist.getEdgeAtIdx(j); if (input.contains(e.getSrc().getName())) { continue; } if (output.contains(e.getDst().getName())) { continue; } rtn += Utils.getTabCharacter(); rtn += String.format("wire %s;", NetSynthUtils.escapeSpecialCharacters(e.getName())); rtn += Utils.getNewLine(); } rtn += Utils.getNewLine(); LSResultNetlistUtils.setVertexTypeUsingLSResult(netlist); final SinkDFS<NetlistNode, NetlistEdge, Netlist> DFS = new SinkDFS<>(netlist); NetlistNode node = null; while ((node = DFS.getNextVertex()) != null) { if (LSResultsUtils.isPrimaryInput(node)) { continue; } final String nodeType = node.getResultNetlistNodeData().getNodeType().toLowerCase(); for (int k = 0; k < node.getNumOutEdge(); k++) { final NetlistEdge e = node.getOutEdgeAtIdx(k); final NetlistNode dst = e.getDst(); String y = ""; final Collection<String> args = new ArrayList<>(); if (LSResultsUtils.isPrimaryOutput(dst)) { y = NetSynthUtils.escapeSpecialCharacters(dst.getName()); } else { y = NetSynthUtils.escapeSpecialCharacters(e.getName()); } for (int l = 0; l < node.getNumInEdge(); l++) { final NetlistEdge f = node.getInEdgeAtIdx(l); final NetlistNode src = f.getSrc(); if (LSResultsUtils.isPrimaryInput(src)) { args.add(NetSynthUtils.escapeSpecialCharacters(src.getName())); } else { args.add(NetSynthUtils.escapeSpecialCharacters(f.getName())); } } rtn += Utils.getTabCharacter(); rtn += String.format("%s (%s, %s);", nodeType, y, String.join(", ", args)); rtn += Utils.getNewLine(); } } rtn += Utils.getNewLine(); rtn += "endmodule"; rtn += Utils.getNewLine(); return rtn; }
NetSynthUtils { public static String getVerilog(final Netlist netlist) { String rtn = ""; final Collection<String> input = new ArrayList<>(); final Collection<String> output = new ArrayList<>(); for (int i = 0; i < netlist.getNumVertex(); i++) { final NetlistNode node = netlist.getVertexAtIdx(i); if (LSResultsUtils.isPrimaryInput(node)) { input.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } if (LSResultsUtils.isPrimaryOutput(node)) { output.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } } final String i = String.join(", ", input); final String o = String.join(", ", output); rtn += String.format("module %s (input %s, output %s);", netlist.getName(), i, o); rtn += Utils.getNewLine() + Utils.getNewLine(); for (int j = 0; j < netlist.getNumEdge(); j++) { final NetlistEdge e = netlist.getEdgeAtIdx(j); if (input.contains(e.getSrc().getName())) { continue; } if (output.contains(e.getDst().getName())) { continue; } rtn += Utils.getTabCharacter(); rtn += String.format("wire %s;", NetSynthUtils.escapeSpecialCharacters(e.getName())); rtn += Utils.getNewLine(); } rtn += Utils.getNewLine(); LSResultNetlistUtils.setVertexTypeUsingLSResult(netlist); final SinkDFS<NetlistNode, NetlistEdge, Netlist> DFS = new SinkDFS<>(netlist); NetlistNode node = null; while ((node = DFS.getNextVertex()) != null) { if (LSResultsUtils.isPrimaryInput(node)) { continue; } final String nodeType = node.getResultNetlistNodeData().getNodeType().toLowerCase(); for (int k = 0; k < node.getNumOutEdge(); k++) { final NetlistEdge e = node.getOutEdgeAtIdx(k); final NetlistNode dst = e.getDst(); String y = ""; final Collection<String> args = new ArrayList<>(); if (LSResultsUtils.isPrimaryOutput(dst)) { y = NetSynthUtils.escapeSpecialCharacters(dst.getName()); } else { y = NetSynthUtils.escapeSpecialCharacters(e.getName()); } for (int l = 0; l < node.getNumInEdge(); l++) { final NetlistEdge f = node.getInEdgeAtIdx(l); final NetlistNode src = f.getSrc(); if (LSResultsUtils.isPrimaryInput(src)) { args.add(NetSynthUtils.escapeSpecialCharacters(src.getName())); } else { args.add(NetSynthUtils.escapeSpecialCharacters(f.getName())); } } rtn += Utils.getTabCharacter(); rtn += String.format("%s (%s, %s);", nodeType, y, String.join(", ", args)); rtn += Utils.getNewLine(); } } rtn += Utils.getNewLine(); rtn += "endmodule"; rtn += Utils.getNewLine(); return rtn; } }
NetSynthUtils { public static String getVerilog(final Netlist netlist) { String rtn = ""; final Collection<String> input = new ArrayList<>(); final Collection<String> output = new ArrayList<>(); for (int i = 0; i < netlist.getNumVertex(); i++) { final NetlistNode node = netlist.getVertexAtIdx(i); if (LSResultsUtils.isPrimaryInput(node)) { input.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } if (LSResultsUtils.isPrimaryOutput(node)) { output.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } } final String i = String.join(", ", input); final String o = String.join(", ", output); rtn += String.format("module %s (input %s, output %s);", netlist.getName(), i, o); rtn += Utils.getNewLine() + Utils.getNewLine(); for (int j = 0; j < netlist.getNumEdge(); j++) { final NetlistEdge e = netlist.getEdgeAtIdx(j); if (input.contains(e.getSrc().getName())) { continue; } if (output.contains(e.getDst().getName())) { continue; } rtn += Utils.getTabCharacter(); rtn += String.format("wire %s;", NetSynthUtils.escapeSpecialCharacters(e.getName())); rtn += Utils.getNewLine(); } rtn += Utils.getNewLine(); LSResultNetlistUtils.setVertexTypeUsingLSResult(netlist); final SinkDFS<NetlistNode, NetlistEdge, Netlist> DFS = new SinkDFS<>(netlist); NetlistNode node = null; while ((node = DFS.getNextVertex()) != null) { if (LSResultsUtils.isPrimaryInput(node)) { continue; } final String nodeType = node.getResultNetlistNodeData().getNodeType().toLowerCase(); for (int k = 0; k < node.getNumOutEdge(); k++) { final NetlistEdge e = node.getOutEdgeAtIdx(k); final NetlistNode dst = e.getDst(); String y = ""; final Collection<String> args = new ArrayList<>(); if (LSResultsUtils.isPrimaryOutput(dst)) { y = NetSynthUtils.escapeSpecialCharacters(dst.getName()); } else { y = NetSynthUtils.escapeSpecialCharacters(e.getName()); } for (int l = 0; l < node.getNumInEdge(); l++) { final NetlistEdge f = node.getInEdgeAtIdx(l); final NetlistNode src = f.getSrc(); if (LSResultsUtils.isPrimaryInput(src)) { args.add(NetSynthUtils.escapeSpecialCharacters(src.getName())); } else { args.add(NetSynthUtils.escapeSpecialCharacters(f.getName())); } } rtn += Utils.getTabCharacter(); rtn += String.format("%s (%s, %s);", nodeType, y, String.join(", ", args)); rtn += Utils.getNewLine(); } } rtn += Utils.getNewLine(); rtn += "endmodule"; rtn += Utils.getNewLine(); return rtn; }  }
NetSynthUtils { public static String getVerilog(final Netlist netlist) { String rtn = ""; final Collection<String> input = new ArrayList<>(); final Collection<String> output = new ArrayList<>(); for (int i = 0; i < netlist.getNumVertex(); i++) { final NetlistNode node = netlist.getVertexAtIdx(i); if (LSResultsUtils.isPrimaryInput(node)) { input.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } if (LSResultsUtils.isPrimaryOutput(node)) { output.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } } final String i = String.join(", ", input); final String o = String.join(", ", output); rtn += String.format("module %s (input %s, output %s);", netlist.getName(), i, o); rtn += Utils.getNewLine() + Utils.getNewLine(); for (int j = 0; j < netlist.getNumEdge(); j++) { final NetlistEdge e = netlist.getEdgeAtIdx(j); if (input.contains(e.getSrc().getName())) { continue; } if (output.contains(e.getDst().getName())) { continue; } rtn += Utils.getTabCharacter(); rtn += String.format("wire %s;", NetSynthUtils.escapeSpecialCharacters(e.getName())); rtn += Utils.getNewLine(); } rtn += Utils.getNewLine(); LSResultNetlistUtils.setVertexTypeUsingLSResult(netlist); final SinkDFS<NetlistNode, NetlistEdge, Netlist> DFS = new SinkDFS<>(netlist); NetlistNode node = null; while ((node = DFS.getNextVertex()) != null) { if (LSResultsUtils.isPrimaryInput(node)) { continue; } final String nodeType = node.getResultNetlistNodeData().getNodeType().toLowerCase(); for (int k = 0; k < node.getNumOutEdge(); k++) { final NetlistEdge e = node.getOutEdgeAtIdx(k); final NetlistNode dst = e.getDst(); String y = ""; final Collection<String> args = new ArrayList<>(); if (LSResultsUtils.isPrimaryOutput(dst)) { y = NetSynthUtils.escapeSpecialCharacters(dst.getName()); } else { y = NetSynthUtils.escapeSpecialCharacters(e.getName()); } for (int l = 0; l < node.getNumInEdge(); l++) { final NetlistEdge f = node.getInEdgeAtIdx(l); final NetlistNode src = f.getSrc(); if (LSResultsUtils.isPrimaryInput(src)) { args.add(NetSynthUtils.escapeSpecialCharacters(src.getName())); } else { args.add(NetSynthUtils.escapeSpecialCharacters(f.getName())); } } rtn += Utils.getTabCharacter(); rtn += String.format("%s (%s, %s);", nodeType, y, String.join(", ", args)); rtn += Utils.getNewLine(); } } rtn += Utils.getNewLine(); rtn += "endmodule"; rtn += Utils.getNewLine(); return rtn; }  static String escapeSpecialCharacters(final String str); static String getVerilog(final Netlist netlist); static String getNodeType(final Gate.GateType type); static Netlist getNetSynthNetlist(
      final Netlist netlist, final JSONArray motifs, final String outputDir); }
NetSynthUtils { public static String getVerilog(final Netlist netlist) { String rtn = ""; final Collection<String> input = new ArrayList<>(); final Collection<String> output = new ArrayList<>(); for (int i = 0; i < netlist.getNumVertex(); i++) { final NetlistNode node = netlist.getVertexAtIdx(i); if (LSResultsUtils.isPrimaryInput(node)) { input.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } if (LSResultsUtils.isPrimaryOutput(node)) { output.add(NetSynthUtils.escapeSpecialCharacters(node.getName())); } } final String i = String.join(", ", input); final String o = String.join(", ", output); rtn += String.format("module %s (input %s, output %s);", netlist.getName(), i, o); rtn += Utils.getNewLine() + Utils.getNewLine(); for (int j = 0; j < netlist.getNumEdge(); j++) { final NetlistEdge e = netlist.getEdgeAtIdx(j); if (input.contains(e.getSrc().getName())) { continue; } if (output.contains(e.getDst().getName())) { continue; } rtn += Utils.getTabCharacter(); rtn += String.format("wire %s;", NetSynthUtils.escapeSpecialCharacters(e.getName())); rtn += Utils.getNewLine(); } rtn += Utils.getNewLine(); LSResultNetlistUtils.setVertexTypeUsingLSResult(netlist); final SinkDFS<NetlistNode, NetlistEdge, Netlist> DFS = new SinkDFS<>(netlist); NetlistNode node = null; while ((node = DFS.getNextVertex()) != null) { if (LSResultsUtils.isPrimaryInput(node)) { continue; } final String nodeType = node.getResultNetlistNodeData().getNodeType().toLowerCase(); for (int k = 0; k < node.getNumOutEdge(); k++) { final NetlistEdge e = node.getOutEdgeAtIdx(k); final NetlistNode dst = e.getDst(); String y = ""; final Collection<String> args = new ArrayList<>(); if (LSResultsUtils.isPrimaryOutput(dst)) { y = NetSynthUtils.escapeSpecialCharacters(dst.getName()); } else { y = NetSynthUtils.escapeSpecialCharacters(e.getName()); } for (int l = 0; l < node.getNumInEdge(); l++) { final NetlistEdge f = node.getInEdgeAtIdx(l); final NetlistNode src = f.getSrc(); if (LSResultsUtils.isPrimaryInput(src)) { args.add(NetSynthUtils.escapeSpecialCharacters(src.getName())); } else { args.add(NetSynthUtils.escapeSpecialCharacters(f.getName())); } } rtn += Utils.getTabCharacter(); rtn += String.format("%s (%s, %s);", nodeType, y, String.join(", ", args)); rtn += Utils.getNewLine(); } } rtn += Utils.getNewLine(); rtn += "endmodule"; rtn += Utils.getNewLine(); return rtn; }  static String escapeSpecialCharacters(final String str); static String getVerilog(final Netlist netlist); static String getNodeType(final Gate.GateType type); static Netlist getNetSynthNetlist(
      final Netlist netlist, final JSONArray motifs, final String outputDir);  }