The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process-scalability. However, the D-LDO inherently suffers from limit cycle oscillation (LCO). To address this issue, the modes and amplitudes of LCO are calculated in this work and verified by SPICE simulation in a 65-nm CMOS process. An LCO reduction technique for the D-LDO is then proposed, by adding two unit power transistors in parallel with the main power MOS array as a feedforward path. This technique sets the LCO mode to 1 and effectively reduces the ripple amplitude for a wide (0.5-20 mA) load current range. When compared with the dead-zone scheme, this technique minimizes LCO with negligible circuit complexity and design difficulty.