This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-mu m CMOS technology to illustrate the verification approach.