This paper presents a new environment for characterizing foundry CMOS device models and analog basic blocks. This environment can also be used to design some analog basic building blocks. It designs analog circuits by dividing them into a set of basic building blocks connected together, where each block is optimized separately considering other blocks' loading and/or boundary conditions. It can run over different technologies using foundry models and simulation measurements without approximations, hand calculations or simplified equations. The efficiency of the complete flow is evaluated through designing a single-ended two-stage operational amplifier over 180nm, 130nm, 90nm, 65nm and 40nm technologies.