The 2-D analytical solution of electrostatic potential and enhanced drain current is modeled for a dual metal surround gate junctionless transistor (DMSGJLT) by solving the Poisson equation using the parabolic approximation technique. The gate engineered DMSGJLT produces an increase in the mobility of electrons in the channel. Enhancement in drain current of 35 mu A is obtained than single metal JLT for the same dimension. Due to that, the gain increases, short channel effects and leakage current decreases. The electrostatic potential, threshold voltage, drain current, transconductance, drain-induced barrier lowering, power and delay predicted by the analytical solution have excellent agreement with the simulation results obtained from Technology Computer-Aided Design. The analytical modeling provides useful insight on physics of short channel effects. The inverter circuit is implemented with a DMSGJLT and is compared with that of a single metal device. The noise margin analysis is made for the inverter circuit employing both dual metal and single metal devices. It is found that gate engineering improves the noise margin to a much extend and due to this, the voltage loss is also improved with a DMSGJLT.