Dc-dc converters often exhibit undesirable oscillations due to their nonlinear dynamics. Digitally controlled converters have further degrees of nonlinearity in terms of quantization in the analog to digital converter and the digital pulse width modulator, giving rise to the well known phenomenon of limit cycle oscillations. In this study, a different and hitherto unreported class of oscillations in digitally controlled converters has been reported, and its origin has been traced to asymmetric saturation in the duty cycle. The study attempts to provide physical insights behind this phenomenon of saturation generated oscillation (SGO), and to identify the converter-system components responsible for it. The challenges in the traditional stability analysis of such a system are highlighted, followed by a simplified analysis leading to the calculation of the oscillation-free operating-zone, and some of the effects of system parameters on the SGO. The results have been used to show some potential ways in which the oscillation can be avoided by using SGO-immune designs. Simulation and experimental results have been provided to illustrate the points and substantiate the claims.