To achieve a squarewave output from a direct digital synthesizer (DDS) without analog signal processing, the lower order bits in the DDS accumulator are used to properly position the rising and falling edges of the accumulator most significant bit (MSB). A digital technique called "time filtering" is proposed to individually manipulate each rising and falling edge on the accumulator MSB. T his technique is shown to achieve the design goals. Design parameters necessary to meet spurious suppression requirements are presented.