A new sub-space max-monomial modeling scheme for CMOS transistors in sub-micron technologies is proposed to improve the modeling accuracy. Major electrical parameters of CMOS transistors in each sub-space from the design space are modeled with max-monomials. This approach is demonstrated to have a better accuracy for sub-micron technologies than singlespace models. Sub-space modeling based geometric programming power optimization has been successfully applied to three different op-amps in 0.18 mu m technology. HSPICE simulation results show that sub-space modeling based GP optimization can allow efficient and accurate analog design. Computational effort can be managed to an acceptable level when searching sub-spaces for transistors by using practical constraints. An efficient scheme in dealing with non-convex constraint inherent in Kirchhoff's voltage law is suggested in this paper. By using this scheme, the nonconvex constraint, such as posynomial equality, can be relaxed to a convex constraint without affecting the result.