This paper presents a digital Active Gate Drive (AGD) methodology for power semiconductor devices. The inherent latency limitation of digital signal processing systems is addressed by a sequential optimization procedure that uses voltage and current signals recorded at the previous switching edge to develop an optimized gate drive waveform for the next switching edge. Experimental results using a half-bridge circuit operating at 180 V/100 A show that the proposed scheme is capable of minimizing switching losses whilst constraining the overvoltage peaks occurring at turn-on and turn-off to as low as 200 V and 300 V respectively.