This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 W from a 800 mV power supply.