FinFET technologies are becoming the mainstream process as technology scales down. Based on 28-nm bulk-Si FinFETs and planar transistors, three-dimensional technology computer-aided design (TCAD) simulations are performed to investigate the charge collection mechanisms and single-event transient (SET) pulse widths for nanoscale devices. Simulation results show that charge collection and SET pulse widths for FinFETs are smaller than those of the planar device. An overall analysis indicates that for P-hits, the reduced charge collection in p-FinFET is induced mainly by the narrow sensitivity drain volumes when ion linear energy transfer (LETs) less than 20 MeV cm(2)/mg; however, the parasitic bipolar amplification effect presents an important effect on the charge reduction for higher ion LETs. An in-depth analysis shows that the reduced bipolar amplification effect in p-FinFET is owing to the conduction channel (fin body) rather than source/drain region. Due to a parasitic reversed bipolar effect, the single-event response for N-hit is less sensitive than that for P-hit. Moreover, comparisons of the temperature dependence of SET pulse width in both FinFETs and planar devices is carried out, which indicate that the SET pulse width in PMOS shows stronger temperature dependence than that in p-FinFET. This gives a new insight into the single-event effects (SEE) in FinFETs, which can provide guidelines for future radiation-hardened applications of FinFET-based circuits.