Reversible logic has gained its importance in the field of low power digital design. In any digital system, the comparator plays an important role in determining whether the two referenced numbers are either equal, greater or lesser. This work deals with optimization of existing reversible comparator designs and also proposes a new multiplexer-based logic for the design of reversible comparator along with design methodology for n-bit comparators. The proposed design is optimized for multiple performance parameters compared to the existing state-of-the-art designs. The proposed multiplexer-based design has 51.9% improvement in quantum cost, 50% in garbage outputs and 62% in ancilla inputs. These optimized designs find application predominantly in the field of quantum computing for low power signal processing, parallel computing, memories, digital system design and multi-processing.