Image coding systems currently undergoing standardisation within ISO and CCITT are the final outcome of a process of incremental improvements to classical hybrid (transform-predictive) algorithms. The task of VLSI architecture synthesis for these complete systems is made somewhat awkward due to the unstructured, irregular and non-modular nature of these algorithms. An ad hoc methodology for pruning the architectural search space, directed by the goal of minimizing the overall internal memory, leads to a strongly control-flow solution, using a pipeline scheme more efficient than with the original signal-flow graph. A generic image coding processor using a parallel programmable architecture is another solution. It may be inferred that second generation image coding techniques should be designed with massive fine-grain parallelism in view, if they are to take advantage of the full potential of dedicated VLSI implementations.