This paper further develops the concept of very large size flash-memory-based pulsewidth-modulated (PWM) algorithms for three-phase inverters. Such algorithms differ from the conventional counter-based implementation, and they follow a preprogrammed optimal PWM pattern that is read from a very large size memory with magnitude and phase as coordinates. Any sequence of states is thus possible within a PWM sampling interval. A novel digital structure has been built around the newly released flash memory integrated circuits. The paper demonstrates the feasibility of operation at any PWM sampling frequency up to 20 kHz when using gigabit-size flash memory integrated circuits along any low-cost microcontroller with an SPI peripheral. To empower the concept, a multioptimal PWM has been proposed and implemented on a 2-Gbit memory table. The harmonics of the phase currents are reduced by more than 40% while a constant PWM sampling frequency is maintained in order to comply with the conventional vector control methods for grid or motor applications.