In this paper we present an FPGA implementation of 5/3 Discrete Wavelet Transform (DWT), which is used in image compression. The 5/3 lifting-based wavelet transform is modeled and simulated using MATLAB. DSP implementation methodologies are used to optimize the required hardware. The signal flow graph and dependence graph are derived and optimized to implement the hardware description of the circuit in Verilog. The circuit code then has been synthesized and realized using Field Programmable Gate Array (FPGA) of FLEX10KE family. Post-synthesis simulations confirm the circuit operation and efficiency.