A high performance interface circuit of sigma-delta accelerometer with low harmonic distortion used many kinds of circuit processing techniques is presented in this work. Multi-bit, dynamic element matching, correlated-double-sampling and electrostatic force feedback linearization circuit are used simultaneously in order to achieve the design indicators. Because of the usage of multi-bit, the design to operational amplifier (OPA) becomes easier, and only a single-stage folded-cascode amplifier is used in the modulator, the OSR is only 64. It highly reduced the difficulty of circuit. The test results indicate that the chip area is only about 10mm(2) and the power dissipation is 10mW with a sampling frequency of 60 kHz. The dynamic range (DR) of the system can be lower than -130 dB, the SNR and SNDR reach to -120 dB and -110 dB respectively with a resolution about 17 bits when referred to 3g full scale DC acceleration under CMOS 0.5 mu m process. The dc nonlinearity of it is 0.2%. This paper realizes an approach which can both simplify the design of the interface circuit and improve the performance of it.