This paper presents sub-threshold, bulk-driven two-stage cascode compensated operational transconductor, which drive load up to 60 pF. The input core in the first stage uses a bulk-driven source-degenerated, gate-regenerated class AB flipped voltage follower (FVF), which ensures rail-to-rail linear input signal drive capability in its unity gain configuration. The self-cascode load of input stage followed by a common source (CS) second stage having simple current source load, have enhanced overall gain around 100 dB. at 1 mHz. Instead of Miller compensation, cascode compensation has been implemented by using two capacitors (C-c/2) each of value 4 pF in this OTA. It has increased its phase margin and gain bandwidth as compared to Miller compensation, under identical load and total compensation capacitors. It ensured better rail-to-rail linearity (THD < -44 dB) at 200 Hz frequency consuming around 74 nW power from +/- 250 mV dual power supply. Another three-stage OTA is also proposed, which includes one additional CS class AB buffer at the output of OTA1, to drive R-C shunt load. This buffered OTA is additionally nested Miller compensated using capacitor (C-NMC) of 0.2 pF. This buffering enhances slew rate and gain bandwidth (GBW) by two-times as compared to un-buffered structure at the cost of power. The Cadence VIRTUOSO environment using UMC 0.18 mu m CMOS process technology has been used to simulate the proposed circuits. (C) 2016 Elsevier Ltd. All rights reserved.