In this work, we designed a Visitor Counting Machine (VCM) in terms of power efficient circuit using family of three different IO Standards which are LVTTL, Mobile DDR, HSUL_12. These three different IO Standards are compared with each other on the basis of Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to search the most power efficient one. In order to find the most efficient circuitry, we collected the data of power consumption of these three IO standards and then compare them. We have analysed our circuitry at different frequencies of 0.1GHz, 1GHz, 10GHz & 100GHz. In our experiment, there is 99.27% power saving when 0.1GHz is used in place of 100GHz using Mobile DDR and we also concluded that when we replace LVTTL by HSUL at 10GHz Frequency, power saving of 96.10% is achieved. To design this energy efficient Visitor Counting Machine, we are using Verilog as HDL, Xilinx ISE 14.2 simulator with Artix-7 FPGA.