This paper presents hybrid cascode compensation with current amplifiers (HCCCA) for nano-scale area-efficient three-stage amplifiers driving ultra-large capacitive loads. The total compensation capacitor is split and placed among two high-speed feedback loops, each with a unique current amplifier. By using HCCCA, the load-dependent non-dominant poles are pushed to much higher frequencies, thereby achieving improved performance especially for heavy capacitive loads. The employed current amplifiers make it possible to significantly reduce the physical size of the compensation capacitors and to save more silicon area. The effectiveness of the proposed technique has been verified in 90-nm CMOS process, where an HCCCA amplifier prototype is designed to drive up to 10 nF load capacitor using a compensation capacitor of only 0.5 pF. It achieves a 1.0 MHz gain-bandwidth product and 0.19 V/A mu s slew-rate while consuming 80 A mu W power from a 1.2 V supply. The achieved large-signal and small-signal performance metrics are superior to those topologies reported in the literature.