This paper presents a Buffered Edge Reconfigurable Cell Array (BERCA) architecture and its applications. A distinctive feature of this architecture is its dual mode of operations. A reconfigurable cell in this array can operate in either blocking mode or non-blocking mode. This renders it amenable to efficient dataflow computation. A small buffer is attached to each link of a BERCA to enable synchronized computation in the style of a systolic array. An approach is devised to map a signal flow graph onto a BERCA array. Unlike previous systolic array mapping methods, this approach is able to map irregular graphs and regular graphs (as specified by simple recurrence equations). It opens up a wide range of applications for our BERCA.