In this paper, parasitic resistance and capacitance of lateral nanowire field effect transistor (NWFET) are studied in detail. Parasitic components of NWFET are modeled and extracted using 3D Technology computer-aided design (TCAD) simulation tool. From the extraction results, extension length was turned out to be dominant factor determining intrinsic gate delay. Not only single nanowire-FET but also trench contact structure of 3-stacked nanowire-FET is also investigated in view of parasitic constituents. Based on the extracted parasitic resistance and capacitance, optimal source/drain extension length is obtained considering two parasitic components which have inverse trend with change of extension length.