An 8th-order Cheybshev-II ladder active-RC BPF was fabricated in a 40 nm CMOS low-leakage digital process. A new technique to design for zero capacitance spread (ZCS) is reported to enable the application of integrator frequency compensation (IFC). Combined with wideband op-amps employing a current-reusing, split-path feed-forward compensation (FFC) technique, significant power savings is achieved in a standard 40 nm CMOS process. The BPF measures a center frequency (CF) of 85-225 MHz and four programmable bandwidth-to-center frequency (BW/CF) ratios of 5%-40%. Both the CF and BW/CF ratio are digitally programmable. It also measures a maximum in-band IIP3 of 31 dBm at 0 dB gain and a maximum in-band frequency-response deviation of 0.2 dB while consuming 33 mA from a 1.5 V supply.