Due to technology scaling, the design of the conventional-type analog-to-digital converter (ADC), which uses an operational amplifier as one of its building blocks, becomes more difficult. In this brief, new techniques to design time-based ADC (TADC), which uses a voltage-controlled oscillator (VCO), are proposed. The VCO is followed by a time-to-digital converter, implemented in a Sigma Delta architecture. A novel architecture, using a multibit, nonlinear internal quantizer and a feedback digital-to-time converter, implemented by using phase interpolation, is employed to compensate the nonlinear transfer curve of the VCO. Dynamic element matching and calibration are used to improve the robustness of the TADC against mismatch. The TADC uses an implicit sample and hold that relaxes the bounds on input frequency. A TADC implemented in 0.13-mu m CMOS technology achieves a measured signal-to-noise + distortion ratio of 60.2 dB and a dynamic range of 11 b for a bandwidth of 2 MHz.