This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-mu m CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits' power consumptions are 60 and 75 mu W, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.