The operational amplifier (OP-AMP) is a really significant and a widely used building block in analog and mixed signal circuit design. Since the performance of OP-AMP in an integrated circuit affects the overall performance of the system, therefore, the power consumption of OP-AMP needs to be reduced. The designs of low-power circuits require the reduction in the internal power supply voltage and minimum interconnection of parasitic elements. Considering the requirements of low-power low-voltage and high efficient circuit, an ultra-low-power low-voltage two stage CMOS OP-AMP with very high open-loop gain (DC gain) and high Unity-Gain Bandwidth (UGB) is proposed here to achieve accuracy and fast settling requirements giving 0.7 V power supply. In this work, high open-loop gain with fast settling time is attained through Cascode technique while the Unity-Gain Bandwidth is enhanced with the help of gain-stage in Miller capacitor feedback path. The proposed OP-AMP provides an open-loop gain of 92 dB, Unity-Gain Bandwidth of 230 MHz, having power consumption of only 20.6 mu W. All the simulations have been performed using Cadence in 45 nm technology.