Functional electrical stimulation has been widely used for the restoration of bladder functions after spinal cord injury or other neurological disorders. However, most of the neuroprostheses for bladder control are still imperfect due to lack of the feedback information about the state of the controlled bladder. The purpose of this study is to develop an implantable system which allows us to stimulate the nerves and record the nerve signals related to the condition of the bladder. The proposed stimulator consists of three parts: a digital-to-analog converter (DAC), a current driver, and a switch network. Using the same current source with a switch network eliminates the need for separate current sources for anodic and cathodic sections and reduce the need for interconnect lines of control signals which is an area-saved and power-efficient configuration. A symmetrical regulated cascode current driver is used to implement a high voltage compliance and a high output impedance which improves its ability with load. The amplitude, frequency and the pulse width of the stimulating current are adjusted by encoding the DAC and switch sequences, respectively. In addition, we also present two-stage fully differential capacitively-coupled amplifiers for neural recording. The neural amplifier's parameters are carefully chosen according to the characteristics of neural signal; meanwhile, we analyzed theoretically the main noise sources, especially the pseudo-resistor in the feedback path which gives little attention by previous studies. The integrated neural stimulating and recording frontend for bladder control prosthesis has been designed and simulated, using a TSMC's 0.18-mu m CMOS process. The proposed stimulator can provide a symmetrical cathodic-first biphasic current pulse with interphasic gap, a low headroom voltage of 0.168 V corresponding to 2.48 mA full-scale current, an adjustable pulse width of 100-500 mu s and frequency of 1-40 Hz. The recording amplifier with a low input-referred noise of 3.62 mu V, an NEF of 3.88 and a low power dissipation of 7.2 mu W has a gain of 61.6 dB and a frequency bandwidth from 300 Hz to 5.3 kHz. Both circuit analysis and simulations are presented to examine the performance of the proposed designs.