This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 mu m CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW.