The paper represents a design procedure of basic two stage CMOS operational amplifier using Miller compensation technique. The LtSpice simulation tool is used to present system result at low capacitive load with different characteristics. The Miller capacitor creates an undesirable right-half-plane (RHP) zero due a non inverting feedforward signal path is induced in the input of the second stage towards its output, which can be eliminated by using voltage buffer. My work shows the two stage amplifier with Miller compensation techniques, simulated using LtSpice simulation tool for 180, 130 and 90 nm CMOS technology process. When a 10-pF capacitive load is drive, the amplifier achieves voltage gain approximate 20 % more with exactly double gain bandwidth (GBW) which shows phase margin of 44.8 degrees, 49.06 degrees, and 53.70 degrees, slew rate of 44.48, 10.29, and 9.77 V/mu s, with dissipating power value of 830 mu W at 2.5 V, 504.06 mu W at 1.5 V, 486 mu W at 1.2 V supply voltage for 180 nm, 130 nm, 90 nm CMOS technology, respectively.