In this paper, a low voltage low dropout (LDO) regulator is designed and simulated in 0.13 mu m CMOS technology, which converts an input voltage of 1.2V into a stable regulated output voltage of 1.1 V using Ng-Spice circuit simulator. The two stage operational amplifier (Op-Amp) is used as an error amplifier (EA). Here, the Artificial Bee Colony (ABC) evolutionary algorithm based optimizer is demonstrated for solving the problem of the device sizing and other parameters of Op-Amp and optimization. This approach for designing two stage Op-Amp circuit does not require any analytical calculations and handles non-linear effects of sub-micron devices very effectively. The designed LDO is tested for a change in load current for 0-100 mA and it is found that the power supply rejection ratio (PSRR) is found to be 78.5 dB at 1 KHz and 28.7 dB at 10 MHz. The settling time of less than 1 mu sec observed during testing of line and load regulations.