Four-dimensional (4-D) infinite impulse response frequency hyper-planar filter and a digital VLSI architecture for real time light field based depth filtering applications is proposed. A signal flow graph based on discrete spatial integrators is introduced, which leads to improved sensitivity properties for perturbations in filter coefficients. First order sensitivity analysis of filter transfer function shows a 92.9 % reduction of maximum gain error in frequency response with 12 bits of fractional precision, when compared with a direct-form architecture. Prototype FPGA hardware-in-the-loop co-simulations are performed for two different light field geometries. Register transfer level design validation is carried out via FPGA hardware emulation with a host computer providing memory buffers, and the full-design emulation is carried out on a standalone Berkely Emulation Engine (BEE3), operating at 36.44 and 37.31 MHz for the two light field geometries, respectively. 45 nm CMOS implementation is carried out up to the synthesis level, yielding operating frequencies of 154.4 and 153.3 MHz (correspondingly frame rates of 1.15 and 18.286 Hz) for the two light field geometries, respectively.