This paper introduces a technique to derive a wordlevel abstraction of the function implemented by a combinational logic circuit. The abstraction provides a canonical representation of the function as a polynomial Z = F(A) over the finite field F-2k, where Z and A represent the k-bit output and input bit-vectors (words) of the circuit, respectively. This canonical abstraction can be utilized for formal verification and equivalence checking of combinational circuits. Our approach to abstraction is based upon concepts from computational commutative algebra and algebraic geometry. We show that the abstraction Z = F(A) can be derived by computing a Grobner basis of the polynomials corresponding to the circuit, using a specific elimination term order derived from the circuit's topology. Computing Grobner bases using elimination term orders is infeasible for large circuits. To overcome this limitation, we describe an efficient symbolic computation to derive the word-level polynomial. Our algorithms exploit: 1) the structure of the circuit; 2) the properties of Grobner bases; 3) characteristics of finite fields F-2k; and 4) modern algorithms from symbolic algebra, to derive the canonical polynomial representation. This approach is employed to verify (and detect bugs in) large combinational finite field arithmetic circuits, where contemporary verification techniques are known to be infeasible.