The kinetics of trap generation during negativebias temperature instability (NBTI) stress in pMOSFETs, as governed by the double interface H-H-2 reaction-diffusion (RD) model, is incorporated for the first time in a commercial technology computer-aided design (TCAD) software, and used for simulating degradation in various device architectures. The calibrated TCAD framework is shown to successfully explain the measured impact of interface trap generation (Delta N-IT) in bulk silicon FinFETs for wide range of stress bias and temperature. The impact of device design on NBTI degradation is explored by comparing the simulated trap generation kinetics in bulk FinFET, silicon on insulator FinFET, and gate all around nanowire FET devices having different geometries. The simulated predictions agree well with the experimental observations reported in the literature. The proposed TCAD framework would enable performance-reliability co-optimization during device design for advanced technology nodes.