This paper describes the design and verification of phase lock loop (PLL) components within the framework of a front-end for digital satellite radio diversity reception. First, the functionality of the implemented PLL is described by a block diagram. Second, individual PLL components are presented and analysed. Altogether a voltage controlled oscillator (VCO), an automatic amplitude control (AAC), a buffer stage, a TSCP logic as well as a DCVSL-R high-speed by-two-divider, a multi-modulus divider (MMD), and a phase-frequency detector are developed. The frequency tuning range of the PLL is between 4.34 and 4.70 GHz and hence the VCO tuning range has to be around 4 to 5 GHz. Beyond this, the VCO's post-layout phase noise is -100.50 dBc/Hz at 1 MHz under nominal environmental conditions and the post-layout yield analysis predicts 99.773%. Additionally, the VCO and the AAC are connected. Due to that additional AAC feedback circuit, the current consumption as well as the VCO output amplitude decrease. The overall system simulation shows the settling process of the PLL for the tri-state and the five-state mode of the PFD. Finally the VCO performance is compared with other state-of-the-art LC-VCOs.