A fully-integrated tuner for digital satellite audio radio applications using a second-zero-IF dual conversion architecture was realized in a 0.2 mu m SiGe BiCMOS technology. An autonomous RF-AGC and a channel decoder IC controlled IF-AGC were used to optimize the signal path gain for a wide range of input signal levels. A single PLL drives both RF and IF mixers, resulting in a smaller die area and lower power dissipation. Down-converting the signal to baseband further reduces tuner's power due to a lower required ADC sampling frequency and resolution. Providing a digital baseband I/Q output allows the implementation of the channel decode IC in a standard digital CMOS process, reducing the overall receiver cost. SDARS tuner performance includes: 5dB noise figure, 55dB image rejection, -100dBm input sensitivity, +15dBm IIP3 at min gain, 40/60dB RF/IF AGC range, 120mA current consumption from a 3.3V supply and 15mm(2) die area.