A 12-bit low power successive approximation ADC has been designed and fabricated in 0.35 A mu m, poly-poly capacitor AMS technology. The SAR ADC is targeted for bridge type pressure sensor in wireless sensor node applications. An improved cascaded inverter based comparator is used for its lower power consumption at reduced supply voltage of 1.3 V. A modified SAR digital circuit has been incorporated to accommodate a higher input range of 1.8 V for the ADC . For a given noise floor, the higher input range of ADC ensures enhanced SNR performance relaxing the constraint on sensor interface circuit preceding to the ADC. Also a novel switching scheme is used in the feedback of comparator to reduce the charge injection induced offset without sacrificing the useful bandwidth of ADC. The inverter based comparator consumes 2 A mu W of power while operating at a speed of 1.6 MHz. The comparator does not make use of any offset cancellation techniques. By suitably choosing the capacitor array of inherent DAC, the calibration techniques have been avoided for the ADC. The ADC achieves an effective number of bits of 10.01 while consuming 6.69 A mu W at a conversion speed of 100 KHz. The FOM of the whole ADC is found to be 64.8 fJ/conversion-step. The active area occupied by the ADC is 0.170625 mm(2) (375 A mu m x 455 A mu m).