In this paper, a CMOS low-power high-speed low-error four-quadrant analog multiplier based on a simple current squarer circuit, is presented. The new squarer circuit consists of a MOS transistor which operating in saturation region and a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. The performance of the proposed design has been simulated using HSPICE software in 0.18 mu m TSMC CMOS technology. Simulation results with +/- 0.7 V DC supply voltages show that the linearity error is 0.35%, the -3dB bandwidth is 903 MHz, the THD is 0.3% (at 1 MHz), maximum and static power consumption are 41.25 mu W and 14.5 mu W, respectively. Monte Carlo analysis with 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are also performed to verify the satisfactory robustness and reliability of the proposed work.