Clock gating is an effective way to reduce the dynamic power in digital sequential circuits. In this paper, a gate-level activity correlation-based clustering clock-gating (CCG) technique is proposed for digital filters. The CCG technique exploits the correlations between flip-flops, and determines how to group the flip-flops for clock gating. An Activity Correlation Matrix (ACMtx) is introduced to describe the correlations between the flip-flops, and a greedy clustering algorithm is proposed to find an optimised clustering scheme as well. Experiments on ISCAS'89 benchmarks show that the proposed technique can reduce power consumption by 5.08% on average, on top of existing technique. For the circuits with large numbers of flip-flops, our proposed technique can save 15.84% more power on average.