An analytical model for the silicon-on-insulator (SOI) tunnel field-effect transistor (FET) with linearly graded workfunction-modulated gate is proposed to improve device performance through subthreshold slope (SS) optimization. The surface potential of the suggested model is analyzed using the two-dimensional (2-D) Poisson equation with imposed channel boundary conditions. Other electrical parameters such as the electric field, drain current, transconductance, and SS are evaluated to examine the performance of the model. Moreover, the performance in terms of the SS and values for the proposed model with downscaling of gate oxide thickness and silicon body thickness are also investigated and the results compared with results for a conventional tunnel FET (TFET) model. The present model exhibits significant reduction in subthreshold slope () and improvement in performance. The accuracy of the model is verified against 2-D technology computer-aided design (TCAD) model simulations.