NanoMagnet logic (NML) is among the emerging technologies that might replace CMOS in the next decades. According to its physical characteristics, to better exploit the potential of this technology-and of other similar ones-the use of parallel architectures with regular layout that avoid long interconnection signals is advised. Systolic arrays (SAs) are among these architectures, being composed of a grid of equal processing elements that are locally interconnected. However, they are usually implemented to execute only a small set of algorithms, and for this reason, throughout the years, they have not been an appealing solution for CMOS. To seriously analyze the potentials of NML, complex architectures must be conceived, and their physical implementation explored considering realistic technological constraints. With the increasing complexity of NML circuits, two issues, then, are noticed: 1) the need for a regular structure arises, that at the same time helps to reduce the intrinsic pipelining nature of NML and can be configured to be used for several applications without developing a dedicated design for each algorithm and 2) the capability to synthesize, place and route NML circuits is fundamental to demonstrate the feasibility of the architecture in two important conditions: efficiently managing the complexity of the design and sticking to the characteristics that are technologically feasible at the time of writing. In this paper, we address these issues presenting a new reconfigurable SA that can be programmed to execute different algorithms, and we provide two examples to show its working principle. Moreover, the array is synthesized and simulated with the aid of the first real tool for nanotechnology circuits that we have conceived, Torino Politecnico Nanotechnology tool. The joint contribution at both the architectural and physical design levels gives a relevant step forward to the state of the art in the demonstration of this emerging technology potential.