We propose an analog front-end integrated circuit (IC) design for a readout IC (ROIC), which applies a fixed-voltage-bias sensing method with a capacitance transimpedance amplifier (CTIA) to an input stage in order to simplify the circuit structure of the ROIC and the IR sensor characteristic control. For a sample-and-hold stage, in order to display and control a signal detected by the IR sensor using a 2-D focal plane array, a differential delta sampling circuit is proposed, which effectively removes the fixed pattern noise. In addition, a two-stage variable-gain amplifier equipped with a rail-to-rail fully differential operational amplifier is applied to the ROIC to achieve high voltage sensitivity. The output characteristic of the proposed device is 30.84 mV/K and the linearity error rate is less than 0.07%. After checking the performance of the ROIC using an HSPICE simulation, the chip is manufactured and measured using the United Microelectronics Corporation Japan 0.35-mu m standard CMOS process to confirm that the simulation results from the actual design are in close agreement with the measurement results.