In this paper, a new low power, low noise operational amplifier dedicated to implantable biomedical applications is introduced. The amplifier is designed to minimize input referred noise and power consnmption. To rednce inpnt thermal noise, we use the EKV Model to set the bias currents of the transistors. To rednce the flicker noise, PMOS inpnt transistors with large gate areas and operating in weak inversion are used. The noise rednction techniqne of switched biasing is then applied, which involves switching the transistor periodically between accnmnlation (cntoff) and inversion region. This helps to fnrther reduce the flicker noise of the transistors. The use of switched biasing allows ns to rednce the inpnt noise, withont having to increase the current and thus allows us to avoid the problem of trading power with noise. Using this techniqne, we are able to achieve an extremely low input noise of 2.89/mu V-rms in the desired bandwidth, at a small snpply cnrrent of 4.8/mu A. The additional circuitry required for switched biasing consumes minimal power, and the average power consnmption of the amplifier is 15.174/mu W, which makes it ideal for implantable applications. The gain of the amplifier is 76.2dB in the required frequency range, with a phase margin of 74 degrees and a CMRR greater than 120dB at all frequencies. The circuit is designed using the TSMC 0.18/mu m process, in the Analog Design Environment of Cadence Virtuoso. The performance of the circuit is studied at all process corners, namely TT, FF, SS, SF and FS. The simulations are carried out at 36.9 degrees C, the normal human body temperature.