For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using full-digital circuits, which deals with only two voltage levels (i.e., V (in)-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation along with high scalability. The circuit architecture is completely digital, using a ring-delay-line (RDL) driven by an input voltage V (in) as its power supply. Resolutions can be controlled by setting its conversion time T (cv), resulting in 16 bit (1 kS/s, 34 mu W) and 6 bit (1 MS/s, 48 mu W) with a prototype IC in a low-cost 0.65-mu m (650-nm) digital CMOS, achieving the sensor digitizer (sensor-digitization product) of a pressure sensor ASIC. The all-digital structure has been scaled into a 0.18-mu m technology, and the test IC presented a higher performance with 28 mu V/LSB (160-kS/s). Finally, as an RF digitization application, the circuit is demonstrated to realize the time-domain processing of an RF signal, working as both mixer and ADC, achieving minimum/maximum detectable sensitivity of 0.7-mu Vrms/100-mVrms, respectively, for a 40-kHz sine wave at the LNA input terminal of a 0.18-mu m digital CMOS one-chip radio-controlled clock receiver IC.