This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mB1C) or Differential m Binary with 1 Mark Insertion (DmB1M) line code. In the proposed procedure for mB1C line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rare equal to 1/(m+1) times the mB1C line rate.