The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multi-core architectures. The main idea is to supply nominal (high) off-chip voltage to a multi-core processor where cores are then "voltage-stacked" to generate a near-threshold (low) voltage based on Kirchhoff's voltage law through charge recycling. However this implicit down-conversion can be affected by the current imbalance between the cores. A push-pull switched-capacitor regulator has been designed to keep the mid voltage close to the near-threshold value of half-V-dd. Stacked-voltage domain with its self-regulation capability combined with push-pull based switch capacitor regulator has shown an average efficiency of more than 90% for 2:1 down conversion with workload imbalance varying up to 50% of I-load.