A very high gain (137 dB) two stage CMOS operational amplifier having structural simplicity of classical Widlar architecture has been presented. The differential input stage of proposed operational amplifier has been modified by incorporating inverse aspect ratio self cascode structures biased to operate in subthreshold region, to minimize the classical compensation capacitor to 0.1 pF and results in considerable saving in occupied chip area. P-SPICE simulations in 0.25 mu m CMOS technology at +/- 1 V supply have been carried out to compare the performance of proposed operational amplifier with previously reported designs. The proposed operational amplifier demonstrated better gain-bandwidth product of 1.37 MHz, low power consumption of 21 mu W and occupied smaller chip area of < 400 (mu m)(2).