This paper describes a variable output voltage, multi-phase switched capacitor step-up DC-DC converter with a digital voltage regulation scheme, implemented in CMOS VLSI technology. The number of conversion ratios generated using n flying capacitors is of the order of 2(n). A scheme for selection of switch is presented. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are obtained and compared with the cadence spectre simulation results. The step-up open loop converter circuit for one of the gain is described and analysed by varying the switching frequency. An open loop converter efficiency of about 78% is achieved with 4% bottom plate parasitic capacitance for a load current of 1 mA and input voltage of 0.6 V at 4 MHz of switching frequency for a gain of 4/3. The voltage regulation scheme for a desired output voltage is designed with a digital control circuit using inherent capacitive DAC which can interpolate through various gain configuration for n = 2 flying capacitor and is simulated in Cadence Analog-Mixed Signal Flow using 180nm CMOS technology. The layout design using MIM cap has been done and back annotation results are presented.