drivers/c/timers.c
bool gp_timer_config_start_16(uint32_t base_addr, uint32_t modeA, uint32_t modeB, bool count_up, bool enable_interrupts)
{
  uint32_t timer_rcgc_mask;
  uint32_t timer_pr_mask;
  TIMER0_Type *gp_timer;
  
  // Verify the base address.
  if ( ! verify_base_addr(base_addr) )
  {
    return false;
  }
  // get the correct RCGC and PR masks for the base address
  get_clock_masks(base_addr, &timer_rcgc_mask, &timer_pr_mask);
  
  // Turn on the clock for the timer
  SYSCTL->RCGCTIMER |= timer_rcgc_mask;

  // Wait for the timer to turn on
  while( (SYSCTL->PRTIMER & timer_pr_mask) == 0) {};
  
  // Type cast the base address to a TIMER0_Type struct
  gp_timer = (TIMER0_Type *)base_addr;
  
	//disable timers
  gp_timer->CTL &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); 
	// configure for 2 16 bit timers
	gp_timer->CFG = TIMER_CFG_16_BIT;
   
	//clear, then set timerA's mode, direction, load register value, and prescalar
	gp_timer->TAMR &= 0x0;
	gp_timer->TAMR |= modeA;
	gp_timer->TAMR |= (count_up << 4);	
	gp_timer->TAILR = TEN_MS;
	gp_timer->TAPR = PRESCALAR_TEN;
	
  //clear, then set timerB's mode, direction, load register value, and prescalar		
	gp_timer->TBMR &= 0x0;
	gp_timer->TBMR|= modeB;
	gp_timer->TBMR |= (count_up << 4);	
	gp_timer->TBILR = TWENTY_MS;
	gp_timer->TBPR = PRESCALAR_TWENTY;
		
	//clear any existing interrupts
	gp_timer->ICR |= TIMER_ICR_TATOCINT;
	gp_timer->ICR |= TIMER_ICR_TBTOCINT;
	
	if (enable_interrupts) {
	  gp_timer->IMR = TIMER_IMR_TATOIM | TIMER_IMR_TBTOIM;  //enable the MIS register
		
		//We are prioritizing the timers to be less important than the ADC conversion interupt		
		//set the priority and enable interrupt in the NVIC
		NVIC_SetPriority(TIMER0A_IRQn, 1);
		NVIC_EnableIRQ(TIMER0A_IRQn);
		
		NVIC_SetPriority(TIMER0B_IRQn, 1);
		NVIC_EnableIRQ(TIMER0B_IRQn);
	}
	
	//enable the timers
	gp_timer->CTL |= TIMER_CTL_TAEN;
	gp_timer->CTL |= TIMER_CTL_TBEN;
  return true;  
}
//*****************************************************************************
// Configure a general purpose timer to be a 16-bit timer.  
//
// Paramters
//  base_address          The base address of a general purpose timer
//
//  modeA                  bit mask for Periodic, One-Shot, or Capture for timer A
//
//  modeB                  bit mask for Periodic, One-Shot, or Capture for timer B
//
//  count_up              When true, the timer counts up.  When false, it counts
//                        down
//
//  enable_interrupts     When set to true, the timer generates and interrupt
//                        when the timer expires.  When set to false, the timer
//                        does not generate interrupts.
//
//The function returns true if the base_addr is a valid general purpose timer
//This also starts the timer
//*****************************************************************************
Configure a general purpose timer to be a 16-bit timer.
Paramters
base_address          The base address of a general purpose timer

modeA                  bit mask for Periodic, One-Shot, or Capture for timer A

modeB                  bit mask for Periodic, One-Shot, or Capture for timer B

count_up              When true, the timer counts up.  When false, it counts
down

enable_interrupts     When set to true, the timer generates and interrupt
when the timer expires.  When set to false, the timer
does not generate interrupts.

The function returns true if the base_addr is a valid general purpose timer
This also starts the timer
Configure a general purpose timer to be a 16 - bit timer . Paramters base_address The base address of a general purpose timer modeA bit mask for Periodic One - Shot or Capture for timer A modeB bit mask for Periodic One - Shot or Capture for timer B count_up When true the timer counts up . When false it counts down enable_interrupts When set to true the timer generates and interrupt when the timer expires . When set to false the timer does not generate interrupts . The function returns true if the base_addr is a valid general purpose timer This also starts the timer
bool gp_timer_config_start_16(uint32_t base_addr, uint32_t modeA, uint32_t modeB, bool count_up, bool enable_interrupts)
{
  uint32_t timer_rcgc_mask;
  uint32_t timer_pr_mask;
  TIMER0_Type *gp_timer;
  if ( ! verify_base_addr(base_addr) )
  {
    return false;
  }
  get_clock_masks(base_addr, &timer_rcgc_mask, &timer_pr_mask);
  SYSCTL->RCGCTIMER |= timer_rcgc_mask;
  while( (SYSCTL->PRTIMER & timer_pr_mask) == 0) {};
  gp_timer = (TIMER0_Type *)base_addr;
  gp_timer->CTL &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); 
	gp_timer->CFG = TIMER_CFG_16_BIT;
	gp_timer->TAMR &= 0x0;
	gp_timer->TAMR |= modeA;
	gp_timer->TAMR |= (count_up << 4);	
	gp_timer->TAILR = TEN_MS;
	gp_timer->TAPR = PRESCALAR_TEN;
	gp_timer->TBMR &= 0x0;
	gp_timer->TBMR|= modeB;
	gp_timer->TBMR |= (count_up << 4);	
	gp_timer->TBILR = TWENTY_MS;
	gp_timer->TBPR = PRESCALAR_TWENTY;
	gp_timer->ICR |= TIMER_ICR_TATOCINT;
	gp_timer->ICR |= TIMER_ICR_TBTOCINT;
	if (enable_interrupts) {
	  gp_timer->IMR = TIMER_IMR_TATOIM | TIMER_IMR_TBTOIM;  
		NVIC_SetPriority(TIMER0A_IRQn, 1);
		NVIC_EnableIRQ(TIMER0A_IRQn);
		NVIC_SetPriority(TIMER0B_IRQn, 1);
		NVIC_EnableIRQ(TIMER0B_IRQn);
	}
	gp_timer->CTL |= TIMER_CTL_TAEN;
	gp_timer->CTL |= TIMER_CTL_TBEN;
  return true;  
}
bool gp_timer_config_start_16 ( uint32_t base_addr , uint32_t modeA , uint32_t modeB , bool count_up , bool enable_interrupts ) { uint32_t timer_rcgc_mask ; uint32_t timer_pr_mask ; TIMER0_Type * gp_timer ; if ( ! verify_base_addr ( base_addr ) ) { return false ; } get_clock_masks ( base_addr , & timer_rcgc_mask , & timer_pr_mask ) ; SYSCTL -> RCGCTIMER |= timer_rcgc_mask ; while ( ( SYSCTL -> PRTIMER & timer_pr_mask ) == 0 ) { } ; gp_timer = ( TIMER0_Type * ) base_addr ; gp_timer -> CTL &= ~ ( TIMER_CTL_TAEN | TIMER_CTL_TBEN ) ; gp_timer -> CFG = TIMER_CFG_16_BIT ; gp_timer -> TAMR &= 0x0 ; gp_timer -> TAMR |= modeA ; gp_timer -> TAMR |= ( count_up << 4 ) ; gp_timer -> TAILR = TEN_MS ; gp_timer -> TAPR = PRESCALAR_TEN ; gp_timer -> TBMR &= 0x0 ; gp_timer -> TBMR |= modeB ; gp_timer -> TBMR |= ( count_up << 4 ) ; gp_timer -> TBILR = TWENTY_MS ; gp_timer -> TBPR = PRESCALAR_TWENTY ; gp_timer -> ICR |= TIMER_ICR_TATOCINT ; gp_timer -> ICR |= TIMER_ICR_TBTOCINT ; if ( enable_interrupts ) { gp_timer -> IMR = TIMER_IMR_TATOIM | TIMER_IMR_TBTOIM ; NVIC_SetPriority ( TIMER0A_IRQn , 1 ) ; NVIC_EnableIRQ ( TIMER0A_IRQn ) ; NVIC_SetPriority ( TIMER0B_IRQn , 1 ) ; NVIC_EnableIRQ ( TIMER0B_IRQn ) ; } gp_timer -> CTL |= TIMER_CTL_TAEN ; gp_timer -> CTL |= TIMER_CTL_TBEN ; return true ; }
Configure a general purpose timer to be a 16-bit timer.
Configure a general purpose timer to be a 16 - bit timer .
// Verify the base address. // get the correct RCGC and PR masks for the base address // Turn on the clock for the timer // Wait for the timer to turn on // Type cast the base address to a TIMER0_Type struct //disable timers // configure for 2 16 bit timers //clear, then set timerA's mode, direction, load register value, and prescalar //clear, then set timerB's mode, direction, load register value, and prescalar		 //clear any existing interrupts //enable the MIS register //We are prioritizing the timers to be less important than the ADC conversion interupt		 //set the priority and enable interrupt in the NVIC //enable the timers