libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
{
  uint16_t tmpccmr1 = 0;
  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
  tmpccmr1 = TIMx->CCMR1;
  /* Reset the OC2CE Bit */
  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
  /* Enable or Disable the Output Compare Clear Bit */
  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
  /* Write to TIMx CCMR1 register */
  TIMx->CCMR1 = tmpccmr1;
}
/**
  * @brief  Clears or safeguards the OCREF2 signal on an external event
  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
  *   This parameter can be one of the following values:
  *     @arg TIM_OCClear_Enable: TIM Output clear enable
  *     @arg TIM_OCClear_Disable: TIM Output clear disable
  * @retval None
  */
@brief  Clears or safeguards the OCREF2 signal on an external event
@param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
@param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
This parameter can be one of the following values:
@arg TIM_OCClear_Enable: TIM Output clear enable
@arg TIM_OCClear_Disable: TIM Output clear disable
@retval None
@brief Clears or safeguards the OCREF2 signal on an external event @param TIMx : where x can be 1 2 3 4 5 or 8 to select the TIM peripheral . @param TIM_OCClear : new state of the Output Compare Clear Enable Bit . This parameter can be one of the following values : @arg TIM_OCClear_Enable : TIM Output clear enable @arg TIM_OCClear_Disable : TIM Output clear disable @retval None
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
{
  uint16_t tmpccmr1 = 0;
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
  tmpccmr1 = TIMx->CCMR1;
  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
  TIMx->CCMR1 = tmpccmr1;
}
void TIM_ClearOC2Ref ( TIM_TypeDef * TIMx , uint16_t TIM_OCClear ) { uint16_t tmpccmr1 = 0 ; assert_param ( IS_TIM_LIST3_PERIPH ( TIMx ) ) ; assert_param ( IS_TIM_OCCLEAR_STATE ( TIM_OCClear ) ) ; tmpccmr1 = TIMx -> CCMR1 ; tmpccmr1 &= ( uint16_t ) ~ ( ( uint16_t ) TIM_CCMR1_OC2CE ) ; tmpccmr1 |= ( uint16_t ) ( TIM_OCClear << 8 ) ; TIMx -> CCMR1 = tmpccmr1 ; }
@brief  Clears or safeguards the OCREF2 signal on an external event
 @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
@brief Clears or safeguards the OCREF2 signal on an external event @param TIMx : where x can be 1 2 3 4 5 or 8 to select the TIM peripheral .
/* Check the parameters */ /* Reset the OC2CE Bit */ /* Enable or Disable the Output Compare Clear Bit */ /* Write to TIMx CCMR1 register */