libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
{
  uint16_t tmpccmr2 = 0;
  /* Check the parameters */
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
  tmpccmr2 = TIMx->CCMR2;
  /* Reset the OC3PE Bit */
  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
  /* Enable or Disable the Output Compare Preload feature */
  tmpccmr2 |= TIM_OCPreload;
  /* Write to TIMx CCMR2 register */
  TIMx->CCMR2 = tmpccmr2;
}
/**
  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
  *   This parameter can be one of the following values:
  *     @arg TIM_OCPreload_Enable
  *     @arg TIM_OCPreload_Disable
  * @retval None
  */
@brief  Enables or disables the TIMx peripheral Preload register on CCR3.
@param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
@param  TIM_OCPreload: new state of the TIMx peripheral Preload register
This parameter can be one of the following values:
@arg TIM_OCPreload_Enable
@arg TIM_OCPreload_Disable
@retval None
@brief Enables or disables the TIMx peripheral Preload register on CCR3 . @param TIMx : where x can be 1 2 3 4 5 or 8 to select the TIM peripheral . @param TIM_OCPreload : new state of the TIMx peripheral Preload register This parameter can be one of the following values : @arg TIM_OCPreload_Enable @arg TIM_OCPreload_Disable @retval None
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
{
  uint16_t tmpccmr2 = 0;
  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
  tmpccmr2 = TIMx->CCMR2;
  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
  tmpccmr2 |= TIM_OCPreload;
  TIMx->CCMR2 = tmpccmr2;
}
void TIM_OC3PreloadConfig ( TIM_TypeDef * TIMx , uint16_t TIM_OCPreload ) { uint16_t tmpccmr2 = 0 ; assert_param ( IS_TIM_LIST3_PERIPH ( TIMx ) ) ; assert_param ( IS_TIM_OCPRELOAD_STATE ( TIM_OCPreload ) ) ; tmpccmr2 = TIMx -> CCMR2 ; tmpccmr2 &= ( uint16_t ) ~ ( ( uint16_t ) TIM_CCMR2_OC3PE ) ; tmpccmr2 |= TIM_OCPreload ; TIMx -> CCMR2 = tmpccmr2 ; }
@brief  Enables or disables the TIMx peripheral Preload register on CCR3.
@brief Enables or disables the TIMx peripheral Preload register on CCR3 .
/* Check the parameters */ /* Reset the OC3PE Bit */ /* Enable or Disable the Output Compare Preload feature */ /* Write to TIMx CCMR2 register */