fn write_ir(&mut self, data: &[u8], len: usize) -> Result<(), DebugProbeError> {
        log::debug!("Write IR: {:?}, len={}", data, len);

        // Check the bit length, enough data has to be
        // available
        if data.len() * 8 < len {
            todo!("Proper error for incorrect length");
        }

        // At least one bit has to be sent
        if len < 1 {
            todo!("Proper error for incorrect length");
        }

        let tms_enter_ir_shift = [true, true, false, false];

        // The last bit will be transmitted when exiting the shift state,
        // so we need to stay in the shift stay for one period less than
        // we have bits to transmit
        let tms_data = iter::repeat(false).take(len - 1);

        let tms_enter_idle = [true, true, false];

        let mut tms = Vec::with_capacity(tms_enter_ir_shift.len() + len + tms_enter_ir_shift.len());

        tms.extend_from_slice(&tms_enter_ir_shift);
        tms.extend(tms_data);
        tms.extend_from_slice(&tms_enter_idle);

        let tdi_enter_ir_shift = [false, false, false, false];

        // This is one less than the enter idle for tms, because
        // the last bit is transmitted when exiting the IR shift state
        let tdi_enter_idle = [false, false];

        let mut tdi = Vec::with_capacity(tdi_enter_ir_shift.len() + tdi_enter_idle.len() + len);

        tdi.extend_from_slice(&tdi_enter_ir_shift);

        let num_bytes = len / 8;

        let num_bits = len - (num_bytes * 8);

        for bytes in &data[..num_bytes] {
            let mut byte = *bytes;

            for _ in 0..8 {
                tdi.push(byte & 1 == 1);

                byte >>= 1;
            }
        }

        if num_bits > 0 {
            let mut remaining_byte = data[num_bytes];

            for _ in 0..num_bits {
                tdi.push(remaining_byte & 1 == 1);
                remaining_byte >>= 1;
            }
        }

        tdi.extend_from_slice(&tdi_enter_idle);

        log::trace!("tms: {:?}", tms);
        log::trace!("tdi: {:?}", tdi);

        let jlink = self.handle.get_mut().unwrap();
        let response = jlink.jtag_io(tms, tdi)?;

        log::trace!("Response: {:?}", response);

        if len >= 8 {
            return Err(DebugProbeError::NotImplemented(
                "Not yet implemented for IR registers larger than 8 bit",
            ));
        }

        self.current_ir_reg = data[0] as u32;

        // Maybe we could return the previous state of the IR register here...

        Ok(())
    }
/// Write IR register with the specified data. The
/// IR register might have an odd length, so the dta
/// will be truncated to `len` bits. If data has less
/// than `len` bits, an error will be returned.
Write IR register with the specified data. The
IR register might have an odd length, so the dta
will be truncated to `len` bits. If data has less
than `len` bits, an error will be returned.
Write IR register with the specified data . The IR register might have an odd length so the dta will be truncated to ` len ` bits . If data has less than ` len ` bits an error will be returned .
fn write_ir(&mut self, data: &[u8], len: usize) -> Result<(), DebugProbeError> {
        log::debug!("Write IR: {:?}, len={}", data, len);
        // Check the bit length, enough data has to be
        // available
        if data.len() * 8 < len {
            todo!("Proper error for incorrect length");
        }
        // At least one bit has to be sent
        if len < 1 {
            todo!("Proper error for incorrect length");
        }
        let tms_enter_ir_shift = [true, true, false, false];
        // The last bit will be transmitted when exiting the shift state,
        // so we need to stay in the shift stay for one period less than
        // we have bits to transmit
        let tms_data = iter::repeat(false).take(len - 1);
        let tms_enter_idle = [true, true, false];
        let mut tms = Vec::with_capacity(tms_enter_ir_shift.len() + len + tms_enter_ir_shift.len());
        tms.extend_from_slice(&tms_enter_ir_shift);
        tms.extend(tms_data);
        tms.extend_from_slice(&tms_enter_idle);
        let tdi_enter_ir_shift = [false, false, false, false];
        // This is one less than the enter idle for tms, because
        // the last bit is transmitted when exiting the IR shift state
        let tdi_enter_idle = [false, false];
        let mut tdi = Vec::with_capacity(tdi_enter_ir_shift.len() + tdi_enter_idle.len() + len);
        tdi.extend_from_slice(&tdi_enter_ir_shift);
        let num_bytes = len / 8;
        let num_bits = len - (num_bytes * 8);
        for bytes in &data[..num_bytes] {
            let mut byte = *bytes;
            for _ in 0..8 {
                tdi.push(byte & 1 == 1);
                byte >>= 1;
            }
        }
        if num_bits > 0 {
            let mut remaining_byte = data[num_bytes];
            for _ in 0..num_bits {
                tdi.push(remaining_byte & 1 == 1);
                remaining_byte >>= 1;
            }
        }
        tdi.extend_from_slice(&tdi_enter_idle);
        log::trace!("tms: {:?}", tms);
        log::trace!("tdi: {:?}", tdi);
        let jlink = self.handle.get_mut().unwrap();
        let response = jlink.jtag_io(tms, tdi)?;
        log::trace!("Response: {:?}", response);
        if len >= 8 {
            return Err(DebugProbeError::NotImplemented(
                "Not yet implemented for IR registers larger than 8 bit",
            ));
        }
        self.current_ir_reg = data[0] as u32;
        // Maybe we could return the previous state of the IR register here...
        Ok(())
    }
fn write_ir ( & mut self , data : & [ u8 ] , len : usize ) -> Result < ( ) , DebugProbeError > { log :: debug ! ( " " data len ) ; // Check the bit length, enough data has to be // available if data . len ( ) * 8 < len { todo ! ( " " ) ; } // At least one bit has to be sent if len < 1 { todo ! ( " " ) ; } let tms_enter_ir_shift = [ true , true , false , false ] ; // The last bit will be transmitted when exiting the shift state, // so we need to stay in the shift stay for one period less than // we have bits to transmit let tms_data = iter :: repeat ( false ) . take ( len - 1 ) ; let tms_enter_idle = [ true , true , false ] ; let mut tms = Vec :: with_capacity ( tms_enter_ir_shift . len ( ) + len + tms_enter_ir_shift . len ( ) ) ; tms . extend_from_slice ( & tms_enter_ir_shift ) ; tms . extend ( tms_data ) ; tms . extend_from_slice ( & tms_enter_idle ) ; let tdi_enter_ir_shift = [ false , false , false , false ] ; // This is one less than the enter idle for tms, because // the last bit is transmitted when exiting the IR shift state let tdi_enter_idle = [ false , false ] ; let mut tdi = Vec :: with_capacity ( tdi_enter_ir_shift . len ( ) + tdi_enter_idle . len ( ) + len ) ; tdi . extend_from_slice ( & tdi_enter_ir_shift ) ; let num_bytes = len / 8 ; let num_bits = len - ( num_bytes * 8 ) ; for bytes in & data [ .. num_bytes ] { let mut byte = * bytes ; for _ in 0 .. 8 { tdi . push ( byte & 1 == 1 ) ; byte >>= 1 ; } } if num_bits > 0 { let mut remaining_byte = data [ num_bytes ] ; for _ in 0 .. num_bits { tdi . push ( remaining_byte & 1 == 1 ) ; remaining_byte >>= 1 ; } } tdi . extend_from_slice ( & tdi_enter_idle ) ; log :: trace ! ( " " tms ) ; log :: trace ! ( " " tdi ) ; let jlink = self . handle . get_mut ( ) . unwrap ( ) ; let response = jlink . jtag_io ( tms , tdi ) ? ; log :: trace ! ( " " response ) ; if len >= 8 { return Err ( DebugProbeError :: NotImplemented ( " " , ) ) ; } self . current_ir_reg = data [ 0 ] as u32 ; // Maybe we could return the previous state of the IR register here... Ok ( ( ) ) }
Write IR register with the specified data.
Write IR register with the specified data .
&mut self
data
&[u8]
len
usize
&mut self
data
&[u8]
len
usize