fn put_input_in_rse<C: LowerCtx<I = Inst>>(
    ctx: &mut C,
    input: InsnInput,
    narrow_mode: NarrowValueMode,
) -> ResultRSE {
    let inputs = ctx.get_input(input.insn, input.input);
    if let Some((insn, 0)) = inputs.inst {
        let op = ctx.data(insn).opcode();
        let out_ty = ctx.output_ty(insn, 0);
        let out_bits = ty_bits(out_ty);

        // Is this a zero-extend or sign-extend and can we handle that with a register-mode operator?
        if op == Opcode::Uextend || op == Opcode::Sextend {
            let sign_extend = op == Opcode::Sextend;
            let inner_ty = ctx.input_ty(insn, 0);
            let inner_bits = ty_bits(inner_ty);
            assert!(inner_bits < out_bits);
            if match (sign_extend, narrow_mode) {
                // A single zero-extend or sign-extend is equal to itself.
                (_, NarrowValueMode::None) => true,
                // Two zero-extends or sign-extends in a row is equal to a single zero-extend or sign-extend.
                (false, NarrowValueMode::ZeroExtend32) | (false, NarrowValueMode::ZeroExtend64) => {
                    true
                }
                (true, NarrowValueMode::SignExtend32) | (true, NarrowValueMode::SignExtend64) => {
                    true
                }
                // A zero-extend and a sign-extend in a row is not equal to a single zero-extend or sign-extend
                (false, NarrowValueMode::SignExtend32) | (false, NarrowValueMode::SignExtend64) => {
                    false
                }
                (true, NarrowValueMode::ZeroExtend32) | (true, NarrowValueMode::ZeroExtend64) => {
                    false
                }
            } {
                let extendop = match (sign_extend, inner_bits) {
                    (true, 8) => ExtendOp::SXTB,
                    (false, 8) => ExtendOp::UXTB,
                    (true, 16) => ExtendOp::SXTH,
                    (false, 16) => ExtendOp::UXTH,
                    (true, 32) => ExtendOp::SXTW,
                    (false, 32) => ExtendOp::UXTW,
                    _ => unreachable!(),
                };
                let reg =
                    put_input_in_reg(ctx, InsnInput { insn, input: 0 }, NarrowValueMode::None);
                return ResultRSE::RegExtend(reg, extendop);
            }
        }

        // If `out_ty` is smaller than 32 bits and we need to zero- or sign-extend,
        // then get the result into a register and return an Extend-mode operand on
        // that register.
        if narrow_mode != NarrowValueMode::None
            && ((narrow_mode.is_32bit() && out_bits < 32)
                || (!narrow_mode.is_32bit() && out_bits < 64))
        {
            let reg = put_input_in_reg(ctx, input, NarrowValueMode::None);
            let extendop = match (narrow_mode, out_bits) {
                (NarrowValueMode::SignExtend32, 1) | (NarrowValueMode::SignExtend64, 1) => {
                    ExtendOp::SXTB
                }
                (NarrowValueMode::ZeroExtend32, 1) | (NarrowValueMode::ZeroExtend64, 1) => {
                    ExtendOp::UXTB
                }
                (NarrowValueMode::SignExtend32, 8) | (NarrowValueMode::SignExtend64, 8) => {
                    ExtendOp::SXTB
                }
                (NarrowValueMode::ZeroExtend32, 8) | (NarrowValueMode::ZeroExtend64, 8) => {
                    ExtendOp::UXTB
                }
                (NarrowValueMode::SignExtend32, 16) | (NarrowValueMode::SignExtend64, 16) => {
                    ExtendOp::SXTH
                }
                (NarrowValueMode::ZeroExtend32, 16) | (NarrowValueMode::ZeroExtend64, 16) => {
                    ExtendOp::UXTH
                }
                (NarrowValueMode::SignExtend64, 32) => ExtendOp::SXTW,
                (NarrowValueMode::ZeroExtend64, 32) => ExtendOp::UXTW,
                _ => unreachable!(),
            };
            return ResultRSE::RegExtend(reg, extendop);
        }
    }

    ResultRSE::from_rs(put_input_in_rs(ctx, input, narrow_mode))
}
/// Lower an instruction input to a reg or reg/shift, or reg/extend operand.
/// This does not actually codegen the source instruction; it just uses the
/// vreg into which the source instruction will generate its value.
///
/// See note on `put_input_in_rs` for a description of `narrow_mode`.
Lower an instruction input to a reg or reg/shift, or reg/extend operand.
This does not actually codegen the source instruction; it just uses the
vreg into which the source instruction will generate its value.

See note on `put_input_in_rs` for a description of `narrow_mode`.
Lower an instruction input to a reg or reg / shift or reg / extend operand . This does not actually codegen the source instruction ; it just uses the vreg into which the source instruction will generate its value . See note on ` put_input_in_rs ` for a description of ` narrow_mode ` .
fn put_input_in_rse<C: LowerCtx<I = Inst>>(
    ctx: &mut C,
    input: InsnInput,
    narrow_mode: NarrowValueMode,
) -> ResultRSE {
    let inputs = ctx.get_input(input.insn, input.input);
    if let Some((insn, 0)) = inputs.inst {
        let op = ctx.data(insn).opcode();
        let out_ty = ctx.output_ty(insn, 0);
        let out_bits = ty_bits(out_ty);
        // Is this a zero-extend or sign-extend and can we handle that with a register-mode operator?
        if op == Opcode::Uextend || op == Opcode::Sextend {
            let sign_extend = op == Opcode::Sextend;
            let inner_ty = ctx.input_ty(insn, 0);
            let inner_bits = ty_bits(inner_ty);
            assert!(inner_bits < out_bits);
            if match (sign_extend, narrow_mode) {
                // A single zero-extend or sign-extend is equal to itself.
                (_, NarrowValueMode::None) => true,
                // Two zero-extends or sign-extends in a row is equal to a single zero-extend or sign-extend.
                (false, NarrowValueMode::ZeroExtend32) | (false, NarrowValueMode::ZeroExtend64) => {
                    true
                }
                (true, NarrowValueMode::SignExtend32) | (true, NarrowValueMode::SignExtend64) => {
                    true
                }
                // A zero-extend and a sign-extend in a row is not equal to a single zero-extend or sign-extend
                (false, NarrowValueMode::SignExtend32) | (false, NarrowValueMode::SignExtend64) => {
                    false
                }
                (true, NarrowValueMode::ZeroExtend32) | (true, NarrowValueMode::ZeroExtend64) => {
                    false
                }
            } {
                let extendop = match (sign_extend, inner_bits) {
                    (true, 8) => ExtendOp::SXTB,
                    (false, 8) => ExtendOp::UXTB,
                    (true, 16) => ExtendOp::SXTH,
                    (false, 16) => ExtendOp::UXTH,
                    (true, 32) => ExtendOp::SXTW,
                    (false, 32) => ExtendOp::UXTW,
                    _ => unreachable!(),
                };
                let reg =
                    put_input_in_reg(ctx, InsnInput { insn, input: 0 }, NarrowValueMode::None);
                return ResultRSE::RegExtend(reg, extendop);
            }
        }
        // If `out_ty` is smaller than 32 bits and we need to zero- or sign-extend,
        // then get the result into a register and return an Extend-mode operand on
        // that register.
        if narrow_mode != NarrowValueMode::None
            && ((narrow_mode.is_32bit() && out_bits < 32)
                || (!narrow_mode.is_32bit() && out_bits < 64))
        {
            let reg = put_input_in_reg(ctx, input, NarrowValueMode::None);
            let extendop = match (narrow_mode, out_bits) {
                (NarrowValueMode::SignExtend32, 1) | (NarrowValueMode::SignExtend64, 1) => {
                    ExtendOp::SXTB
                }
                (NarrowValueMode::ZeroExtend32, 1) | (NarrowValueMode::ZeroExtend64, 1) => {
                    ExtendOp::UXTB
                }
                (NarrowValueMode::SignExtend32, 8) | (NarrowValueMode::SignExtend64, 8) => {
                    ExtendOp::SXTB
                }
                (NarrowValueMode::ZeroExtend32, 8) | (NarrowValueMode::ZeroExtend64, 8) => {
                    ExtendOp::UXTB
                }
                (NarrowValueMode::SignExtend32, 16) | (NarrowValueMode::SignExtend64, 16) => {
                    ExtendOp::SXTH
                }
                (NarrowValueMode::ZeroExtend32, 16) | (NarrowValueMode::ZeroExtend64, 16) => {
                    ExtendOp::UXTH
                }
                (NarrowValueMode::SignExtend64, 32) => ExtendOp::SXTW,
                (NarrowValueMode::ZeroExtend64, 32) => ExtendOp::UXTW,
                _ => unreachable!(),
            };
            return ResultRSE::RegExtend(reg, extendop);
        }
    }
    ResultRSE::from_rs(put_input_in_rs(ctx, input, narrow_mode))
}
fn put_input_in_rse < C : LowerCtx < I = Inst > > ( ctx : & mut C , input : InsnInput , narrow_mode : NarrowValueMode , ) -> ResultRSE { let inputs = ctx . get_input ( input . insn , input . input ) ; if let Some ( ( insn , 0 ) ) = inputs . inst { let op = ctx . data ( insn ) . opcode ( ) ; let out_ty = ctx . output_ty ( insn , 0 ) ; let out_bits = ty_bits ( out_ty ) ; // Is this a zero-extend or sign-extend and can we handle that with a register-mode operator? if op == Opcode :: Uextend || op == Opcode :: Sextend { let sign_extend = op == Opcode :: Sextend ; let inner_ty = ctx . input_ty ( insn , 0 ) ; let inner_bits = ty_bits ( inner_ty ) ; assert ! ( inner_bits out_bits ) ; if match ( sign_extend , narrow_mode ) { // A single zero-extend or sign-extend is equal to itself. ( _ , NarrowValueMode :: None ) => true , // Two zero-extends or sign-extends in a row is equal to a single zero-extend or sign-extend. ( false , NarrowValueMode :: ZeroExtend32 ) | ( false , NarrowValueMode :: ZeroExtend64 ) => { true } ( true , NarrowValueMode :: SignExtend32 ) | ( true , NarrowValueMode :: SignExtend64 ) => { true } // A zero-extend and a sign-extend in a row is not equal to a single zero-extend or sign-extend ( false , NarrowValueMode :: SignExtend32 ) | ( false , NarrowValueMode :: SignExtend64 ) => { false } ( true , NarrowValueMode :: ZeroExtend32 ) | ( true , NarrowValueMode :: ZeroExtend64 ) => { false } } { let extendop = match ( sign_extend , inner_bits ) { ( true , 8 ) => ExtendOp :: SXTB , ( false , 8 ) => ExtendOp :: UXTB , ( true , 16 ) => ExtendOp :: SXTH , ( false , 16 ) => ExtendOp :: UXTH , ( true , 32 ) => ExtendOp :: SXTW , ( false , 32 ) => ExtendOp :: UXTW , _ => unreachable ! ( ) , } ; let reg = put_input_in_reg ( ctx , InsnInput { insn , input : 0 } , NarrowValueMode :: None ) ; return ResultRSE :: RegExtend ( reg , extendop ) ; } } // If `out_ty` is smaller than 32 bits and we need to zero- or sign-extend, // then get the result into a register and return an Extend-mode operand on // that register. if narrow_mode != NarrowValueMode :: None && ( ( narrow_mode . is_32bit ( ) && out_bits < 32 ) || ( ! narrow_mode . is_32bit ( ) && out_bits < 64 ) ) { let reg = put_input_in_reg ( ctx , input , NarrowValueMode :: None ) ; let extendop = match ( narrow_mode , out_bits ) { ( NarrowValueMode :: SignExtend32 , 1 ) | ( NarrowValueMode :: SignExtend64 , 1 ) => { ExtendOp :: SXTB } ( NarrowValueMode :: ZeroExtend32 , 1 ) | ( NarrowValueMode :: ZeroExtend64 , 1 ) => { ExtendOp :: UXTB } ( NarrowValueMode :: SignExtend32 , 8 ) | ( NarrowValueMode :: SignExtend64 , 8 ) => { ExtendOp :: SXTB } ( NarrowValueMode :: ZeroExtend32 , 8 ) | ( NarrowValueMode :: ZeroExtend64 , 8 ) => { ExtendOp :: UXTB } ( NarrowValueMode :: SignExtend32 , 16 ) | ( NarrowValueMode :: SignExtend64 , 16 ) => { ExtendOp :: SXTH } ( NarrowValueMode :: ZeroExtend32 , 16 ) | ( NarrowValueMode :: ZeroExtend64 , 16 ) => { ExtendOp :: UXTH } ( NarrowValueMode :: SignExtend64 , 32 ) => ExtendOp :: SXTW , ( NarrowValueMode :: ZeroExtend64 , 32 ) => ExtendOp :: UXTW , _ => unreachable ! ( ) , } ; return ResultRSE :: RegExtend ( reg , extendop ) ; } } ResultRSE :: from_rs ( put_input_in_rs ( ctx , input , narrow_mode ) ) }
Lower an instruction input to a reg or reg/shift, or reg/extend operand.
Lower an instruction input to a reg or reg / shift or reg / extend operand .
ctx
&mut C
input
InsnInput
narrow_mode
NarrowValueMode
ctx
&mut C
input
InsnInput
narrow_mode
NarrowValueMode