pub fn ioapic_establish_route(_gsi: u64, _core: u64) {
    use crate::memory::vspace::MapAction;
    use crate::memory::{paddr_to_kernel_vaddr, PAddr};

    for io_apic in atopology::MACHINE_TOPOLOGY.io_apics() {
        let addr = PAddr::from(io_apic.address as u64);

        let mut inst =
            unsafe { x86::apic::ioapic::IoApic::new(paddr_to_kernel_vaddr(addr).as_usize()) };
        trace!(
            "This IOAPIC supports {} Interrupts",
            inst.supported_interrupts()
        );

        for i in 0..inst.supported_interrupts() {
            let gsi = io_apic.global_irq_base + i as u32;
            if gsi < 16 {
                trace!(
                    "Enable irq {} which maps to GSI#{}",
                    i,
                    io_apic.global_irq_base + i as u32
                );
                if i != 2 && i != 1 {
                    inst.enable(i, 0);
                }
            }
        }
    }
}
/// Establishes a route for a GSI on the IOAPIC.
///
/// # TODO
/// Currently this just enables everything and routes it to
/// core 0. This is because, we should probably just support MSI(X)
/// and don't invest a lot in legacy interrupts...
Establishes a route for a GSI on the IOAPIC.
Establishes a route for a GSI on the IOAPIC .
pub fn ioapic_establish_route(_gsi: u64, _core: u64) {
    use crate::memory::vspace::MapAction;
    use crate::memory::{paddr_to_kernel_vaddr, PAddr};
    for io_apic in atopology::MACHINE_TOPOLOGY.io_apics() {
        let addr = PAddr::from(io_apic.address as u64);
        let mut inst =
            unsafe { x86::apic::ioapic::IoApic::new(paddr_to_kernel_vaddr(addr).as_usize()) };
        trace!(
            "This IOAPIC supports {} Interrupts",
            inst.supported_interrupts()
        );
        for i in 0..inst.supported_interrupts() {
            let gsi = io_apic.global_irq_base + i as u32;
            if gsi < 16 {
                trace!(
                    "Enable irq {} which maps to GSI#{}",
                    i,
                    io_apic.global_irq_base + i as u32
                );
                if i != 2 && i != 1 {
                    inst.enable(i, 0);
                }
            }
        }
    }
}
pub fn ioapic_establish_route ( _gsi : u64 , _core : u64 ) { use crate :: memory :: vspace :: MapAction ; use crate :: memory :: { paddr_to_kernel_vaddr , PAddr } ; for io_apic in atopology :: MACHINE_TOPOLOGY . io_apics ( ) { let addr = PAddr :: from ( io_apic . address as u64 ) ; let mut inst = unsafe { x86 :: apic :: ioapic :: IoApic :: new ( paddr_to_kernel_vaddr ( addr ) . as_usize ( ) ) } ; trace ! ( " " inst supported_interrupts ( ) ) ; for i in 0 .. inst . supported_interrupts ( ) { let gsi = io_apic . global_irq_base + i as u32 ; if gsi < 16 { trace ! ( " " i io_apic global_irq_base i as u32 ) ; if i != 2 && i != 1 { inst . enable ( i , 0 ) ; } } } } }
Establishes a route for a GSI on the IOAPIC.
Establishes a route for a GSI on the IOAPIC .
_gsi
u64
_core
u64
_gsi
u64
_core
u64
todo
Currently this just enables everything and routes it to
core 0. This is because, we should probably just support MSI(X)
and don't invest a lot in legacy interrupts
Currently this just enables everything and routes it to core 0 . This is because we should probably just support MSI ( X ) and don ' t invest a lot in legacy interrupts