pub fn end_transmission(&mut self, stop: bool) -> Result<(), I2cError> {
    let peripheral_ptr;
    unsafe {peripheral_ptr = stm32f4::stm32f446::Peripherals::steal();}
    let _sr: u32;
  
    match self.core {
      1 => {
        let i2c1 = &peripheral_ptr.I2C1;
        i2c1.cr1.write(|w| w.start().set_bit());
        while i2c1.sr1.read().sb().is_no_start() {}
        i2c1.dr.write(|w| w.dr().bits(self.tx_addr));
        while i2c1.sr1.read().addr().is_not_match() {
          if let Err(error) = scan_i2c_error(i2c1.sr1.read().bits() as u16) {return Err(error);}
        }
        _sr = i2c1.sr2.read().bits();
        for byte in self.tx_buffer.iter() {
          i2c1.dr.write(|w| w.dr().bits(*byte));
          while i2c1.sr1.read().tx_e().is_not_empty() {
            if let Err(error) = scan_i2c_error(i2c1.sr1.read().bits() as u16) {return Err(error);}
          }
        }
        if stop {i2c1.cr1.write(|w| w.stop().set_bit());}
        else {i2c1.cr1.write(|w| w.start().set_bit());}
      },
      2 => {
        let i2c2 = &peripheral_ptr.I2C2;
        i2c2.cr1.write(|w| w.start().set_bit());
        while i2c2.sr1.read().sb().is_no_start() {}
        i2c2.dr.write(|w| w.dr().bits(self.tx_addr));
        while i2c2.sr1.read().addr().is_not_match() {
          if let Err(error) = scan_i2c_error(i2c2.sr1.read().bits() as u16) {return Err(error);}
        }
        _sr= i2c2.sr2.read().bits();
        for byte in self.tx_buffer.iter() {
          i2c2.dr.write(|w| w.dr().bits(*byte));
          while i2c2.sr1.read().tx_e().is_not_empty() {
            if let Err(error) = scan_i2c_error(i2c2.sr1.read().bits() as u16) {return Err(error);}
          }
        }
        if stop {i2c2.cr1.write(|w| w.stop().set_bit());}
        else {i2c2.cr1.write(|w| w.start().set_bit());}
      },
      3 => {
        let i2c3 = &peripheral_ptr.I2C3;
        i2c3.cr1.write(|w| w.start().set_bit());
        while i2c3.sr1.read().sb().is_no_start() {}
        i2c3.dr.write(|w| w.dr().bits(self.tx_addr));
        while i2c3.sr1.read().addr().is_not_match() {
          if let Err(error) = scan_i2c_error(i2c3.sr1.read().bits() as u16) {return Err(error);}
        }
        _sr = i2c3.sr2.read().bits();
        for byte in self.tx_buffer.iter() {
          i2c3.dr.write(|w| w.dr().bits(*byte));
          while i2c3.sr1.read().tx_e().is_not_empty() {
            if let Err(error) = scan_i2c_error(i2c3.sr1.read().bits() as u16) {return Err(error);}
          }
        }
        if stop {i2c3.cr1.write(|w| w.stop().set_bit());}
        else {i2c3.cr1.write(|w| w.start().set_bit());}
      },
      _ => panic!("I2C{} is not a valid core! | .send_bytes(...)", self.core)
    };

    return Ok(());
  }
/// Burst tranfers the bytes in the tx buffer to the slave. Specify if a stop bit should be send. Normally this
/// should be true. It can be false if you want to communicate with multiple slaves simultaniously.
/// Returns an error-enum if problems with the connection are detected.
Burst tranfers the bytes in the tx buffer to the slave. Specify if a stop bit should be send. Normally this
should be true. It can be false if you want to communicate with multiple slaves simultaniously.
Returns an error-enum if problems with the connection are detected.
Burst tranfers the bytes in the tx buffer to the slave . Specify if a stop bit should be send . Normally this should be true . It can be false if you want to communicate with multiple slaves simultaniously . Returns an error - enum if problems with the connection are detected .
pub fn end_transmission(&mut self, stop: bool) -> Result<(), I2cError> {
    let peripheral_ptr;
    unsafe {peripheral_ptr = stm32f4::stm32f446::Peripherals::steal();}
    let _sr: u32;
    match self.core {
      1 => {
        let i2c1 = &peripheral_ptr.I2C1;
        i2c1.cr1.write(|w| w.start().set_bit());
        while i2c1.sr1.read().sb().is_no_start() {}
        i2c1.dr.write(|w| w.dr().bits(self.tx_addr));
        while i2c1.sr1.read().addr().is_not_match() {
          if let Err(error) = scan_i2c_error(i2c1.sr1.read().bits() as u16) {return Err(error);}
        }
        _sr = i2c1.sr2.read().bits();
        for byte in self.tx_buffer.iter() {
          i2c1.dr.write(|w| w.dr().bits(*byte));
          while i2c1.sr1.read().tx_e().is_not_empty() {
            if let Err(error) = scan_i2c_error(i2c1.sr1.read().bits() as u16) {return Err(error);}
          }
        }
        if stop {i2c1.cr1.write(|w| w.stop().set_bit());}
        else {i2c1.cr1.write(|w| w.start().set_bit());}
      },
      2 => {
        let i2c2 = &peripheral_ptr.I2C2;
        i2c2.cr1.write(|w| w.start().set_bit());
        while i2c2.sr1.read().sb().is_no_start() {}
        i2c2.dr.write(|w| w.dr().bits(self.tx_addr));
        while i2c2.sr1.read().addr().is_not_match() {
          if let Err(error) = scan_i2c_error(i2c2.sr1.read().bits() as u16) {return Err(error);}
        }
        _sr= i2c2.sr2.read().bits();
        for byte in self.tx_buffer.iter() {
          i2c2.dr.write(|w| w.dr().bits(*byte));
          while i2c2.sr1.read().tx_e().is_not_empty() {
            if let Err(error) = scan_i2c_error(i2c2.sr1.read().bits() as u16) {return Err(error);}
          }
        }
        if stop {i2c2.cr1.write(|w| w.stop().set_bit());}
        else {i2c2.cr1.write(|w| w.start().set_bit());}
      },
      3 => {
        let i2c3 = &peripheral_ptr.I2C3;
        i2c3.cr1.write(|w| w.start().set_bit());
        while i2c3.sr1.read().sb().is_no_start() {}
        i2c3.dr.write(|w| w.dr().bits(self.tx_addr));
        while i2c3.sr1.read().addr().is_not_match() {
          if let Err(error) = scan_i2c_error(i2c3.sr1.read().bits() as u16) {return Err(error);}
        }
        _sr = i2c3.sr2.read().bits();
        for byte in self.tx_buffer.iter() {
          i2c3.dr.write(|w| w.dr().bits(*byte));
          while i2c3.sr1.read().tx_e().is_not_empty() {
            if let Err(error) = scan_i2c_error(i2c3.sr1.read().bits() as u16) {return Err(error);}
          }
        }
        if stop {i2c3.cr1.write(|w| w.stop().set_bit());}
        else {i2c3.cr1.write(|w| w.start().set_bit());}
      },
      _ => panic!("I2C{} is not a valid core! | .send_bytes(...)", self.core)
    };
    return Ok(());
  }
pub fn end_transmission ( & mut self , stop : bool ) -> Result < ( ) , I2cError > { let peripheral_ptr ; unsafe { peripheral_ptr = stm32f4 :: stm32f446 :: Peripherals :: steal ( ) ; } let _sr : u32 ; match self . core { 1 => { let i2c1 = & peripheral_ptr . I2C1 ; i2c1 . cr1 . write ( | w | w . start ( ) . set_bit ( ) ) ; while i2c1 . sr1 . read ( ) . sb ( ) . is_no_start ( ) { } i2c1 . dr . write ( | w | w . dr ( ) . bits ( self . tx_addr ) ) ; while i2c1 . sr1 . read ( ) . addr ( ) . is_not_match ( ) { if let Err ( error ) = scan_i2c_error ( i2c1 . sr1 . read ( ) . bits ( ) as u16 ) { return Err ( error ) ; } } _sr = i2c1 . sr2 . read ( ) . bits ( ) ; for byte in self . tx_buffer . iter ( ) { i2c1 . dr . write ( | w | w . dr ( ) . bits ( * byte ) ) ; while i2c1 . sr1 . read ( ) . tx_e ( ) . is_not_empty ( ) { if let Err ( error ) = scan_i2c_error ( i2c1 . sr1 . read ( ) . bits ( ) as u16 ) { return Err ( error ) ; } } } if stop { i2c1 . cr1 . write ( | w | w . stop ( ) . set_bit ( ) ) ; } else { i2c1 . cr1 . write ( | w | w . start ( ) . set_bit ( ) ) ; } } , 2 => { let i2c2 = & peripheral_ptr . I2C2 ; i2c2 . cr1 . write ( | w | w . start ( ) . set_bit ( ) ) ; while i2c2 . sr1 . read ( ) . sb ( ) . is_no_start ( ) { } i2c2 . dr . write ( | w | w . dr ( ) . bits ( self . tx_addr ) ) ; while i2c2 . sr1 . read ( ) . addr ( ) . is_not_match ( ) { if let Err ( error ) = scan_i2c_error ( i2c2 . sr1 . read ( ) . bits ( ) as u16 ) { return Err ( error ) ; } } _sr = i2c2 . sr2 . read ( ) . bits ( ) ; for byte in self . tx_buffer . iter ( ) { i2c2 . dr . write ( | w | w . dr ( ) . bits ( * byte ) ) ; while i2c2 . sr1 . read ( ) . tx_e ( ) . is_not_empty ( ) { if let Err ( error ) = scan_i2c_error ( i2c2 . sr1 . read ( ) . bits ( ) as u16 ) { return Err ( error ) ; } } } if stop { i2c2 . cr1 . write ( | w | w . stop ( ) . set_bit ( ) ) ; } else { i2c2 . cr1 . write ( | w | w . start ( ) . set_bit ( ) ) ; } } , 3 => { let i2c3 = & peripheral_ptr . I2C3 ; i2c3 . cr1 . write ( | w | w . start ( ) . set_bit ( ) ) ; while i2c3 . sr1 . read ( ) . sb ( ) . is_no_start ( ) { } i2c3 . dr . write ( | w | w . dr ( ) . bits ( self . tx_addr ) ) ; while i2c3 . sr1 . read ( ) . addr ( ) . is_not_match ( ) { if let Err ( error ) = scan_i2c_error ( i2c3 . sr1 . read ( ) . bits ( ) as u16 ) { return Err ( error ) ; } } _sr = i2c3 . sr2 . read ( ) . bits ( ) ; for byte in self . tx_buffer . iter ( ) { i2c3 . dr . write ( | w | w . dr ( ) . bits ( * byte ) ) ; while i2c3 . sr1 . read ( ) . tx_e ( ) . is_not_empty ( ) { if let Err ( error ) = scan_i2c_error ( i2c3 . sr1 . read ( ) . bits ( ) as u16 ) { return Err ( error ) ; } } } if stop { i2c3 . cr1 . write ( | w | w . stop ( ) . set_bit ( ) ) ; } else { i2c3 . cr1 . write ( | w | w . start ( ) . set_bit ( ) ) ; } } , _ => panic ! ( " " self core ) } ; return Ok ( ( ) ) ; }
Burst tranfers the bytes in the tx buffer to the slave.
Burst tranfers the bytes in the tx buffer to the slave .
&mut self
stop
bool
&mut self
stop
bool