pub fn add_library(&self, name: Name, asts: &'ast [Ast<'ast>]) -> LibRef {
        let id = LibRef::new(NodeId::alloc());
        self.sb.libs.borrow_mut().insert(id, (name, asts));

        // Pass on the VHDL nodes to the VHDL scoreboard.
        let vhdl_ast = asts
            .iter()
            .flat_map(|v| match *v {
                Ast::Vhdl(ref a) => a.iter(),
                _ => [].iter(),
            })
            .collect();
        self.vhdl()
            .add_library(name, vhdl::score::LibRef::new(id.into()), vhdl_ast);

        // Pass on the SystemVerilog nodes to the VHDL scoreboard.
        let svlog_ast = asts.iter().filter_map(|v| match *v {
            Ast::Svlog(ref a) => Some(a),
            _ => None,
        });
        self.svlog.add_files(svlog_ast);

        id
    }
/// Add a library to the scoreboard.
Add a library to the scoreboard.
Add a library to the scoreboard .
pub fn add_library(&self, name: Name, asts: &'ast [Ast<'ast>]) -> LibRef {
        let id = LibRef::new(NodeId::alloc());
        self.sb.libs.borrow_mut().insert(id, (name, asts));
        // Pass on the VHDL nodes to the VHDL scoreboard.
        let vhdl_ast = asts
            .iter()
            .flat_map(|v| match *v {
                Ast::Vhdl(ref a) => a.iter(),
                _ => [].iter(),
            })
            .collect();
        self.vhdl()
            .add_library(name, vhdl::score::LibRef::new(id.into()), vhdl_ast);
        // Pass on the SystemVerilog nodes to the VHDL scoreboard.
        let svlog_ast = asts.iter().filter_map(|v| match *v {
            Ast::Svlog(ref a) => Some(a),
            _ => None,
        });
        self.svlog.add_files(svlog_ast);
        id
    }
pub fn add_library ( & self , name : Name , asts : & ' ast [ Ast < ' ast > ] ) -> LibRef { let id = LibRef :: new ( NodeId :: alloc ( ) ) ; self . sb . libs . borrow_mut ( ) . insert ( id , ( name , asts ) ) ; // Pass on the VHDL nodes to the VHDL scoreboard. let vhdl_ast = asts . iter ( ) . flat_map ( | v | match * v { Ast :: Vhdl ( ref a ) => a . iter ( ) , _ => [ ] . iter ( ) , } ) . collect ( ) ; self . vhdl ( ) . add_library ( name , vhdl :: score :: LibRef :: new ( id . into ( ) ) , vhdl_ast ) ; // Pass on the SystemVerilog nodes to the VHDL scoreboard. let svlog_ast = asts . iter ( ) . filter_map ( | v | match * v { Ast :: Svlog ( ref a ) => Some ( a ) , _ => None , } ) ; self . svlog . add_files ( svlog_ast ) ; id }
Add a library to the scoreboard.
Add a library to the scoreboard .
&self
name
Name
asts
&'ast [Ast<'ast>]
&self
name
Name
asts
&'ast [Ast<'ast>]