pub fn replace_insns_from_regalloc(&mut self, result: RegAllocResult<Self>) {
        self.final_block_order = compute_final_block_order(self);

        // Record the spillslot count and clobbered registers for the ABI/stack
        // setup code.
        self.abi.set_num_spillslots(result.num_spill_slots as usize);
        self.abi
            .set_clobbered(result.clobbered_registers.map(|r| Writable::from_reg(*r)));

        // We want to move instructions over in final block order, using the new
        // block-start map given by the regalloc.
        let block_ranges: Vec<(usize, usize)> =
            block_ranges(result.target_map.elems(), result.insns.len());
        let mut final_insns = vec![];
        let mut final_block_ranges = vec![(0, 0); self.num_blocks()];

        for block in &self.final_block_order {
            let (start, end) = block_ranges[*block as usize];
            let final_start = final_insns.len() as InsnIndex;

            if *block == self.entry {
                // Start with the prologue.
                final_insns.extend(self.abi.gen_prologue().into_iter());
            }

            for i in start..end {
                let insn = &result.insns[i];

                // Elide redundant moves at this point (we only know what is
                // redundant once registers are allocated).
                if is_redundant_move(insn) {
                    continue;
                }

                // Whenever encountering a return instruction, replace it
                // with the epilogue.
                let is_ret = insn.is_term() == MachTerminator::Ret;
                if is_ret {
                    final_insns.extend(self.abi.gen_epilogue().into_iter());
                } else {
                    final_insns.push(insn.clone());
                }
            }
            let final_end = final_insns.len() as InsnIndex;
            final_block_ranges[*block as usize] = (final_start, final_end);
        }

        self.insts = final_insns;
        self.block_ranges = final_block_ranges;
    }
/// Take the results of register allocation, with a sequence of
/// instructions including spliced fill/reload/move instructions, and replace
/// the VCode with them.
Take the results of register allocation, with a sequence of
instructions including spliced fill/reload/move instructions, and replace
the VCode with them.
Take the results of register allocation with a sequence of instructions including spliced fill / reload / move instructions and replace the VCode with them .
pub fn replace_insns_from_regalloc(&mut self, result: RegAllocResult<Self>) {
        self.final_block_order = compute_final_block_order(self);
        // Record the spillslot count and clobbered registers for the ABI/stack
        // setup code.
        self.abi.set_num_spillslots(result.num_spill_slots as usize);
        self.abi
            .set_clobbered(result.clobbered_registers.map(|r| Writable::from_reg(*r)));
        // We want to move instructions over in final block order, using the new
        // block-start map given by the regalloc.
        let block_ranges: Vec<(usize, usize)> =
            block_ranges(result.target_map.elems(), result.insns.len());
        let mut final_insns = vec![];
        let mut final_block_ranges = vec![(0, 0); self.num_blocks()];
        for block in &self.final_block_order {
            let (start, end) = block_ranges[*block as usize];
            let final_start = final_insns.len() as InsnIndex;
            if *block == self.entry {
                // Start with the prologue.
                final_insns.extend(self.abi.gen_prologue().into_iter());
            }
            for i in start..end {
                let insn = &result.insns[i];
                // Elide redundant moves at this point (we only know what is
                // redundant once registers are allocated).
                if is_redundant_move(insn) {
                    continue;
                }
                // Whenever encountering a return instruction, replace it
                // with the epilogue.
                let is_ret = insn.is_term() == MachTerminator::Ret;
                if is_ret {
                    final_insns.extend(self.abi.gen_epilogue().into_iter());
                } else {
                    final_insns.push(insn.clone());
                }
            }
            let final_end = final_insns.len() as InsnIndex;
            final_block_ranges[*block as usize] = (final_start, final_end);
        }
        self.insts = final_insns;
        self.block_ranges = final_block_ranges;
    }
pub fn replace_insns_from_regalloc ( & mut self , result : RegAllocResult < Self > ) { self . final_block_order = compute_final_block_order ( self ) ; // Record the spillslot count and clobbered registers for the ABI/stack // setup code. self . abi . set_num_spillslots ( result . num_spill_slots as usize ) ; self . abi . set_clobbered ( result . clobbered_registers . map ( | r | Writable :: from_reg ( * r ) ) ) ; // We want to move instructions over in final block order, using the new // block-start map given by the regalloc. let block_ranges : Vec < ( usize , usize ) > = block_ranges ( result . target_map . elems ( ) , result . insns . len ( ) ) ; let mut final_insns = vec ! [ ] ; let mut final_block_ranges = vec ! [ ( 0 0 ) self num_blocks ( ) ] ; for block in & self . final_block_order { let ( start , end ) = block_ranges [ * block as usize ] ; let final_start = final_insns . len ( ) as InsnIndex ; if * block == self . entry { // Start with the prologue. final_insns . extend ( self . abi . gen_prologue ( ) . into_iter ( ) ) ; } for i in start .. end { let insn = & result . insns [ i ] ; // Elide redundant moves at this point (we only know what is // redundant once registers are allocated). if is_redundant_move ( insn ) { continue ; } // Whenever encountering a return instruction, replace it // with the epilogue. let is_ret = insn . is_term ( ) == MachTerminator :: Ret ; if is_ret { final_insns . extend ( self . abi . gen_epilogue ( ) . into_iter ( ) ) ; } else { final_insns . push ( insn . clone ( ) ) ; } } let final_end = final_insns . len ( ) as InsnIndex ; final_block_ranges [ * block as usize ] = ( final_start , final_end ) ; } self . insts = final_insns ; self . block_ranges = final_block_ranges ; }
Take the results of register allocation, with a sequence of
instructions including spliced fill/reload/move instructions, and replace
the VCode with them.
Take the results of register allocation with a sequence of instructions including spliced fill / reload / move instructions and replace the VCode with them .
&mut self
result
RegAllocResult<Self>
&mut self
result
RegAllocResult<Self>