pub fn receive(&mut self, buffer: &mut [u8]) -> Result<u16, E> {
        // Busy wait for a packet
        loop {
            let eir = common::EIR(self.read_control_register(common::Register::EIR)?);

            // TODO check for error conditions
            debug_assert!(eir.rxerif() == 0);

            if eir.pktif() == 1 {
                break;
            }
        }

        // prepare to read buffer memory
        let curr_packet = if self.next_packet == NONE {
            RXST
        } else {
            self.next_packet
        };

        // read out the first 6 bytes
        let mut temp_buf: [u8; 6] = unsafe { mem::uninitialized() };
        self.read_buffer_memory(Some(curr_packet), &mut temp_buf)?;

        // next packet pointer
        let next_packet = u16::from_parts(temp_buf[0], temp_buf[1]);
        self.next_packet = next_packet;

        // status vector
        let status = RxStatus(LE::read_u32(&temp_buf[2..]));

        let n = status.byte_count() as u16;
        // NOTE exclude the CRC (4 bytes)
        let end = n - Self::CRC_SZ;
        self.read_buffer_memory(None, &mut buffer[..usize(end)])?;

        // update ERXRDPT
        // due to Errata issue 11 we must write an odd address to ERXRDPT
        // we know that ERXST = 0, that ERXND is odd and that next_packet is even
        let rxrdpt = next_packet.checked_sub(1).unwrap_or(self.rxnd);
        self.write_control_register(bank0::Register::ERXRDPTL, rxrdpt.low())?;
        self.write_control_register(bank0::Register::ERXRDPTH, rxrdpt.high())?;

        // decrease the packet count
        self.write_control_register(
            common::Register::ECON2,
            common::ECON2::default().pktdec(1).bits(),
        )?;

        Ok(end)
    }
/// Copies a received frame into the specified `buffer`
///
/// Returns the size of the frame
///
/// **NOTE** If there's no pending packet this method will *block* until a new packet arrives
Copies a received frame into the specified `buffer`
Returns the size of the frame

NOTE** If there's no pending packet this method will *block* until a new packet arrives
Copies a received frame into the specified ` buffer ` Returns the size of the frame NOTE ** If there ' s no pending packet this method will * block * until a new packet arrives
pub fn receive(&mut self, buffer: &mut [u8]) -> Result<u16, E> {
        // Busy wait for a packet
        loop {
            let eir = common::EIR(self.read_control_register(common::Register::EIR)?);
            // TODO check for error conditions
            debug_assert!(eir.rxerif() == 0);
            if eir.pktif() == 1 {
                break;
            }
        }
        // prepare to read buffer memory
        let curr_packet = if self.next_packet == NONE {
            RXST
        } else {
            self.next_packet
        };
        // read out the first 6 bytes
        let mut temp_buf: [u8; 6] = unsafe { mem::uninitialized() };
        self.read_buffer_memory(Some(curr_packet), &mut temp_buf)?;
        // next packet pointer
        let next_packet = u16::from_parts(temp_buf[0], temp_buf[1]);
        self.next_packet = next_packet;
        // status vector
        let status = RxStatus(LE::read_u32(&temp_buf[2..]));
        let n = status.byte_count() as u16;
        // NOTE exclude the CRC (4 bytes)
        let end = n - Self::CRC_SZ;
        self.read_buffer_memory(None, &mut buffer[..usize(end)])?;
        // update ERXRDPT
        // due to Errata issue 11 we must write an odd address to ERXRDPT
        // we know that ERXST = 0, that ERXND is odd and that next_packet is even
        let rxrdpt = next_packet.checked_sub(1).unwrap_or(self.rxnd);
        self.write_control_register(bank0::Register::ERXRDPTL, rxrdpt.low())?;
        self.write_control_register(bank0::Register::ERXRDPTH, rxrdpt.high())?;
        // decrease the packet count
        self.write_control_register(
            common::Register::ECON2,
            common::ECON2::default().pktdec(1).bits(),
        )?;
        Ok(end)
    }
pub fn receive ( & mut self , buffer : & mut [ u8 ] ) -> Result < u16 , E > { // Busy wait for a packet loop { let eir = common :: EIR ( self . read_control_register ( common :: Register :: EIR ) ? ) ; // TODO check for error conditions debug_assert ! ( eir rxerif ( ) 0 ) ; if eir . pktif ( ) == 1 { break ; } } // prepare to read buffer memory let curr_packet = if self . next_packet == NONE { RXST } else { self . next_packet } ; // read out the first 6 bytes let mut temp_buf : [ u8 ; 6 ] = unsafe { mem :: uninitialized ( ) } ; self . read_buffer_memory ( Some ( curr_packet ) , & mut temp_buf ) ? ; // next packet pointer let next_packet = u16 :: from_parts ( temp_buf [ 0 ] , temp_buf [ 1 ] ) ; self . next_packet = next_packet ; // status vector let status = RxStatus ( LE :: read_u32 ( & temp_buf [ 2 .. ] ) ) ; let n = status . byte_count ( ) as u16 ; // NOTE exclude the CRC (4 bytes) let end = n - Self :: CRC_SZ ; self . read_buffer_memory ( None , & mut buffer [ .. usize ( end ) ] ) ? ; // update ERXRDPT // due to Errata issue 11 we must write an odd address to ERXRDPT // we know that ERXST = 0, that ERXND is odd and that next_packet is even let rxrdpt = next_packet . checked_sub ( 1 ) . unwrap_or ( self . rxnd ) ; self . write_control_register ( bank0 :: Register :: ERXRDPTL , rxrdpt . low ( ) ) ? ; self . write_control_register ( bank0 :: Register :: ERXRDPTH , rxrdpt . high ( ) ) ? ; // decrease the packet count self . write_control_register ( common :: Register :: ECON2 , common :: ECON2 :: default ( ) . pktdec ( 1 ) . bits ( ) , ) ? ; Ok ( end ) }
Copies a received frame into the specified `buffer`
Returns the size of the frame
Copies a received frame into the specified ` buffer ` Returns the size of the frame
&mut self
buffer
&mut [u8]
&mut self
buffer
&mut [u8]