fn show_uart_info(debug: &mut dyn core::fmt::Write, uart: *const pac::uart1::RegisterBlock) {
    let cpr = unsafe { (*uart).cpr.read() }.bits();
    let ucv = unsafe { (*uart).ucv.read() }.bits();
    let ctr = unsafe { (*uart).ctr.read() }.bits();
    writeln!(debug, "UART1: Designware UART version {}.{}.{}",
             char::from((ucv >> 24) as u8),
             char::from(((ucv >> 16) & 0xff) as u8),
             char::from(((ucv >> 8) & 0xff) as u8),
             ).unwrap();
    write!(debug, "UART1: Features").unwrap();
    write!(debug, " APB {} bits", match cpr & 3 {
        0 => 8,
        1 => 16,
        2 => 32,
        _ => 0,
    }).unwrap();
    let flags = [
        (4, "AFCE"),
        (5, "THRE"),
        (6, "SIR"),
        (7, "SIR_LP"),
        (8, "ADDITIONAL_FEAT"),
        (9, "FIFO_ACCESS"),
        (10, "FIFO_STAT"),
        (11, "SHADOW"),
        (12, "UART_ADD_ENCODED_PARAMS"),
        (13, "DMA_EXTRA"),
    ];
    for (bit, name) in &flags {
        if (cpr & (1u32 << bit)) != 0u32 {
            write!(debug, " {}", name).unwrap();
        }
    }
    write!(debug, " UART {} bytes", ((cpr >> 16) & 0xff) * 16).unwrap();
    writeln!(debug).unwrap();
    writeln!(debug, "UART1: CTR {:08x}", ctr).unwrap();
}
/** Show some information about Designware UART. */
Show some information about Designware UART.
Show some information about Designware UART .
fn show_uart_info(debug: &mut dyn core::fmt::Write, uart: *const pac::uart1::RegisterBlock) {
    let cpr = unsafe { (*uart).cpr.read() }.bits();
    let ucv = unsafe { (*uart).ucv.read() }.bits();
    let ctr = unsafe { (*uart).ctr.read() }.bits();
    writeln!(debug, "UART1: Designware UART version {}.{}.{}",
             char::from((ucv >> 24) as u8),
             char::from(((ucv >> 16) & 0xff) as u8),
             char::from(((ucv >> 8) & 0xff) as u8),
             ).unwrap();
    write!(debug, "UART1: Features").unwrap();
    write!(debug, " APB {} bits", match cpr & 3 {
        0 => 8,
        1 => 16,
        2 => 32,
        _ => 0,
    }).unwrap();
    let flags = [
        (4, "AFCE"),
        (5, "THRE"),
        (6, "SIR"),
        (7, "SIR_LP"),
        (8, "ADDITIONAL_FEAT"),
        (9, "FIFO_ACCESS"),
        (10, "FIFO_STAT"),
        (11, "SHADOW"),
        (12, "UART_ADD_ENCODED_PARAMS"),
        (13, "DMA_EXTRA"),
    ];
    for (bit, name) in &flags {
        if (cpr & (1u32 << bit)) != 0u32 {
            write!(debug, " {}", name).unwrap();
        }
    }
    write!(debug, " UART {} bytes", ((cpr >> 16) & 0xff) * 16).unwrap();
    writeln!(debug).unwrap();
    writeln!(debug, "UART1: CTR {:08x}", ctr).unwrap();
}
fn show_uart_info ( debug : & mut dyn core :: fmt :: Write , uart : * const pac :: uart1 :: RegisterBlock ) { let cpr = unsafe { ( * uart ) . cpr . read ( ) } . bits ( ) ; let ucv = unsafe { ( * uart ) . ucv . read ( ) } . bits ( ) ; let ctr = unsafe { ( * uart ) . ctr . read ( ) } . bits ( ) ; writeln ! ( debug " " char from ( ( ucv 24 ) as u8 ) char from ( ( ( ucv 16 ) 0xff ) as u8 ) char from ( ( ( ucv 8 ) 0xff ) as u8 ) ) . unwrap ( ) ; write ! ( debug " " ) . unwrap ( ) ; write ! ( debug " " match cpr 3 { 0 8 1 16 2 32 0 } ) . unwrap ( ) ; let flags = [ ( 4 , " " ) , ( 5 , " " ) , ( 6 , " " ) , ( 7 , " " ) , ( 8 , " " ) , ( 9 , " " ) , ( 10 , " " ) , ( 11 , " " ) , ( 12 , " " ) , ( 13 , " " ) , ] ; for ( bit , name ) in & flags { if ( cpr & ( 1u32 << bit ) ) != 0u32 { write ! ( debug " " name ) . unwrap ( ) ; } } write ! ( debug " " ( ( cpr 16 ) 0xff ) 16 ) . unwrap ( ) ; writeln ! ( debug ) . unwrap ( ) ; writeln ! ( debug " " ctr ) . unwrap ( ) ; }
Show some information about Designware UART.
Show some information about Designware UART .
debug
&mut dyn core::fmt::Write
uart
*const pac::uart1::RegisterBlock
debug
&mut dyn core::fmt::Write
uart
*const pac::uart1::RegisterBlock