fn l1_write_back(&mut self, victim_cache_line: L1CacheLine, l1_index: u64) {
		let mut write_back_address = 0 as u64;
		// [ tag | index | 000000 ]
		write_back_address = write_back_address
			| (victim_cache_line.tag << (L1_CACHE_INDEX_BITS + L1_CACHE_OFFSET_BITS))
			| (l1_index << L1_CACHE_OFFSET_BITS);

		// Write back to L2
		// Latency for checking
		self.clock = self.clock.wrapping_add(L1_CACHE_HIT_LATENCY as u64);
		// Latency for checking
		self.clock = self.clock.wrapping_add(L2_CACHE_HIT_LATENCY as u64);
		match self.l2_cache.read_line_info(write_back_address) {
			Ok(l2_way) => {
				let l2_index: u64 =
					(write_back_address >> L2_CACHE_OFFSET_BITS) & ((1 << L2_CACHE_INDEX_BITS) - 1);
				self.l2_cache.data[l2_index as usize].data[l2_way as usize].data_blocks =
					victim_cache_line.data_blocks;
				self.l2_cache.data[l2_index as usize].data[l2_way as usize].l1_inclusive = false;
			}
			_ => {}
		}
	}
/// Write back method for L1 cache
///
/// # Arguments
/// * `victim_cache_line`: the line needs to be written back
/// * `index`: index of the line
Write back method for L1 cache
Write back method for L1 cache
fn l1_write_back(&mut self, victim_cache_line: L1CacheLine, l1_index: u64) {
		let mut write_back_address = 0 as u64;
		// [ tag | index | 000000 ]
		write_back_address = write_back_address
			| (victim_cache_line.tag << (L1_CACHE_INDEX_BITS + L1_CACHE_OFFSET_BITS))
			| (l1_index << L1_CACHE_OFFSET_BITS);
		// Write back to L2
		// Latency for checking
		self.clock = self.clock.wrapping_add(L1_CACHE_HIT_LATENCY as u64);
		// Latency for checking
		self.clock = self.clock.wrapping_add(L2_CACHE_HIT_LATENCY as u64);
		match self.l2_cache.read_line_info(write_back_address) {
			Ok(l2_way) => {
				let l2_index: u64 =
					(write_back_address >> L2_CACHE_OFFSET_BITS) & ((1 << L2_CACHE_INDEX_BITS) - 1);
				self.l2_cache.data[l2_index as usize].data[l2_way as usize].data_blocks =
					victim_cache_line.data_blocks;
				self.l2_cache.data[l2_index as usize].data[l2_way as usize].l1_inclusive = false;
			}
			_ => {}
		}
	}
fn l1_write_back ( & mut self , victim_cache_line : L1CacheLine , l1_index : u64 ) { let mut write_back_address = 0 as u64 ; // [ tag | index | 000000 ] write_back_address = write_back_address | ( victim_cache_line . tag << ( L1_CACHE_INDEX_BITS + L1_CACHE_OFFSET_BITS ) ) | ( l1_index << L1_CACHE_OFFSET_BITS ) ; // Write back to L2 // Latency for checking self . clock = self . clock . wrapping_add ( L1_CACHE_HIT_LATENCY as u64 ) ; // Latency for checking self . clock = self . clock . wrapping_add ( L2_CACHE_HIT_LATENCY as u64 ) ; match self . l2_cache . read_line_info ( write_back_address ) { Ok ( l2_way ) => { let l2_index : u64 = ( write_back_address >> L2_CACHE_OFFSET_BITS ) & ( ( 1 << L2_CACHE_INDEX_BITS ) - 1 ) ; self . l2_cache . data [ l2_index as usize ] . data [ l2_way as usize ] . data_blocks = victim_cache_line . data_blocks ; self . l2_cache . data [ l2_index as usize ] . data [ l2_way as usize ] . l1_inclusive = false ; } _ => { } } }
Write back method for L1 cache
Write back method for L1 cache
&mut self
victim_cache_line
L1CacheLine
l1_index
u64