fn subcomponent_instances<'a>(comp: &component::Component) -> D<'a> {
    let doc = comp
        .structure
        .component_iterator()
        .filter_map(|(idx, node)| {
            if let NodeData::Cell(cell) = &node.data {
                Some((node, idx, cell))
            } else {
                None
            }
        })
        .map(|(node, idx, cell)| {
            subcomponent_sig(&node.name, &cell)
                .append(D::space())
                .append(
                    D::line()
                        .append(signature_connections(
                            &node.signature,
                            &comp,
                            idx,
                        ))
                        .nest(4)
                        .append(D::line())
                        .parens(),
                )
                .append(";")
        });
    D::intersperse(doc, D::line().append(D::line()))
}
//==========================================
//        Subcomponent Instance Functions
//==========================================
/// Generate Verilog for each subcomponent instanstiation and
/// wire up all the ports.
Subcomponent Instance Functions
Generate Verilog for each subcomponent instanstiation and
wire up all the ports.
Subcomponent Instance Functions Generate Verilog for each subcomponent instanstiation and wire up all the ports .
fn subcomponent_instances<'a>(comp: &component::Component) -> D<'a> {
    let doc = comp
        .structure
        .component_iterator()
        .filter_map(|(idx, node)| {
            if let NodeData::Cell(cell) = &node.data {
                Some((node, idx, cell))
            } else {
                None
            }
        })
        .map(|(node, idx, cell)| {
            subcomponent_sig(&node.name, &cell)
                .append(D::space())
                .append(
                    D::line()
                        .append(signature_connections(
                            &node.signature,
                            &comp,
                            idx,
                        ))
                        .nest(4)
                        .append(D::line())
                        .parens(),
                )
                .append(";")
        });
    D::intersperse(doc, D::line().append(D::line()))
}
fn subcomponent_instances < ' a > ( comp : & component :: Component ) -> D < ' a > { let doc = comp . structure . component_iterator ( ) . filter_map ( | ( idx , node ) | { if let NodeData :: Cell ( cell ) = & node . data { Some ( ( node , idx , cell ) ) } else { None } } ) . map ( | ( node , idx , cell ) | { subcomponent_sig ( & node . name , & cell ) . append ( D :: space ( ) ) . append ( D :: line ( ) . append ( signature_connections ( & node . signature , & comp , idx , ) ) . nest ( 4 ) . append ( D :: line ( ) ) . parens ( ) , ) . append ( " " ) } ) ; D :: intersperse ( doc , D :: line ( ) . append ( D :: line ( ) ) ) }
Subcomponent Instance Functions
Generate Verilog for each subcomponent instanstiation and
wire up all the ports.
Subcomponent Instance Functions Generate Verilog for each subcomponent instanstiation and wire up all the ports .
comp
&component::Component