fn signature_connections<'a>(
    sig: &ast::Signature,
    comp: &component::Component,
    idx: NodeIndex,
) -> D<'a> {
    // wire up all the incoming edges
    let all = sig.inputs.iter().chain(sig.outputs.iter()).map(|portdef| {
        // if portdef is named `clk`, wire up `clk`
        if &portdef.name == "clk" {
            D::text(".").append("clk").append(D::text("clk").parens())
        } else {
            D::text(".")
                .append(D::text(portdef.name.to_string()))
                .append(
                    D::text(format!(
                        "{}_{}",
                        comp.structure.get_node(idx).name.to_string(),
                        portdef.name.to_string()
                    ))
                    .parens(),
                )
        }
    });

    D::intersperse(all, D::text(",").append(D::line()))
}
/// Generates Verilog for connection ports to wires.
Generates Verilog for connection ports to wires.
Generates Verilog for connection ports to wires .
fn signature_connections<'a>(
    sig: &ast::Signature,
    comp: &component::Component,
    idx: NodeIndex,
) -> D<'a> {
    // wire up all the incoming edges
    let all = sig.inputs.iter().chain(sig.outputs.iter()).map(|portdef| {
        // if portdef is named `clk`, wire up `clk`
        if &portdef.name == "clk" {
            D::text(".").append("clk").append(D::text("clk").parens())
        } else {
            D::text(".")
                .append(D::text(portdef.name.to_string()))
                .append(
                    D::text(format!(
                        "{}_{}",
                        comp.structure.get_node(idx).name.to_string(),
                        portdef.name.to_string()
                    ))
                    .parens(),
                )
        }
    });
    D::intersperse(all, D::text(",").append(D::line()))
}
fn signature_connections < ' a > ( sig : & ast :: Signature , comp : & component :: Component , idx : NodeIndex , ) -> D < ' a > { // wire up all the incoming edges let all = sig . inputs . iter ( ) . chain ( sig . outputs . iter ( ) ) . map ( | portdef | { // if portdef is named `clk`, wire up `clk` if & portdef . name == " " { D :: text ( " " ) . append ( " " ) . append ( D :: text ( " " ) . parens ( ) ) } else { D :: text ( " " ) . append ( D :: text ( portdef . name . to_string ( ) ) ) . append ( D :: text ( format ! ( " " comp structure get_node ( idx ) name to_string ( ) portdef name to_string ( ) ) ) . parens ( ) , ) } } ) ; D :: intersperse ( all , D :: text ( " " ) . append ( D :: line ( ) ) ) }
Generates Verilog for connection ports to wires.
Generates Verilog for connection ports to wires .
sig
&ast::Signature
comp
&component::Component
idx
NodeIndex