fn add_reg(&mut self, reg1: u8, reg2: u8)
	{
		let v1 = self.v[reg1 as usize];
		let v2 = self.v[reg2 as usize];

		self.v[0xF] = if (v1 as u16) + (v2 as u16) > 0xFF { 1 } else { 0 }; // Carry flag to VF
		self.v[reg1 as usize] = v1.wrapping_add(v2);
	}
/// Set Vreg1 = Vreg1 + Vreg2, set VF = carry.
/// The values of Vreg1 and Vreg2 are added together. If the result is greater than 8 bits, VF is set to 1, otherwise 0. Only the lowest 8 bits of the result are kept, and stored in Vreg1.
Set Vreg1 = Vreg1 + Vreg2, set VF = carry.
The values of Vreg1 and Vreg2 are added together. If the result is greater than 8 bits, VF is set to 1, otherwise 0. Only the lowest 8 bits of the result are kept, and stored in Vreg1.
Set Vreg1 = Vreg1 + Vreg2 set VF = carry . The values of Vreg1 and Vreg2 are added together . If the result is greater than 8 bits VF is set to 1 otherwise 0 . Only the lowest 8 bits of the result are kept and stored in Vreg1 .
fn add_reg(&mut self, reg1: u8, reg2: u8)
	{
		let v1 = self.v[reg1 as usize];
		let v2 = self.v[reg2 as usize];
		self.v[0xF] = if (v1 as u16) + (v2 as u16) > 0xFF { 1 } else { 0 }; // Carry flag to VF
		self.v[reg1 as usize] = v1.wrapping_add(v2);
	}
fn add_reg ( & mut self , reg1 : u8 , reg2 : u8 ) { let v1 = self . v [ reg1 as usize ] ; let v2 = self . v [ reg2 as usize ] ; self . v [ 0xF ] = if ( v1 as u16 ) + ( v2 as u16 ) > 0xFF { 1 } else { 0 } ; // Carry flag to VF self . v [ reg1 as usize ] = v1 . wrapping_add ( v2 ) ; }
Set Vreg1 = Vreg1 + Vreg2, set VF = carry.
Set Vreg1 = Vreg1 + Vreg2 set VF = carry .
&mut self
reg1
u8
reg2
u8