fn primitive_implemenations<'a>(
    prog: &ast::NamespaceDef,
    context: &context::Context,
) -> Result<D<'a>> {
    let docs = prog
        .components
        .iter()
        .map(|c| c.cells.iter())
        .flatten()
        .filter_map(|s| match s {
            Cell::Prim { data } => Some(&data.instance.name),
            _ => None,
        })
        .unique()
        .map(|name| {
            context.library_context.definitions[&name]
                .implementation
                .iter()
                .find_map(|im| match im {
                    Implementation::Verilog { data } => {
                        Some(D::text(data.code.to_string()))
                    }
                })
                .ok_or_else(|| {
                    Error::MissingImplementation("Verilog", name.clone())
                })
        })
        .collect::<Result<Vec<_>>>()?;
    Ok(D::intersperse(docs, D::line().append(D::line())))
}
/// Collects all of the Verilog implementations specified in the library
/// file.
Collects all of the Verilog implementations specified in the library
file.
Collects all of the Verilog implementations specified in the library file .
fn primitive_implemenations<'a>(
    prog: &ast::NamespaceDef,
    context: &context::Context,
) -> Result<D<'a>> {
    let docs = prog
        .components
        .iter()
        .map(|c| c.cells.iter())
        .flatten()
        .filter_map(|s| match s {
            Cell::Prim { data } => Some(&data.instance.name),
            _ => None,
        })
        .unique()
        .map(|name| {
            context.library_context.definitions[&name]
                .implementation
                .iter()
                .find_map(|im| match im {
                    Implementation::Verilog { data } => {
                        Some(D::text(data.code.to_string()))
                    }
                })
                .ok_or_else(|| {
                    Error::MissingImplementation("Verilog", name.clone())
                })
        })
        .collect::<Result<Vec<_>>>()?;
    Ok(D::intersperse(docs, D::line().append(D::line())))
}
fn primitive_implemenations < ' a > ( prog : & ast :: NamespaceDef , context : & context :: Context , ) -> Result < D < ' a > > { let docs = prog . components . iter ( ) . map ( | c | c . cells . iter ( ) ) . flatten ( ) . filter_map ( | s | match s { Cell :: Prim { data } => Some ( & data . instance . name ) , _ => None , } ) . unique ( ) . map ( | name | { context . library_context . definitions [ & name ] . implementation . iter ( ) . find_map ( | im | match im { Implementation :: Verilog { data } => { Some ( D :: text ( data . code . to_string ( ) ) ) } } ) . ok_or_else ( | | { Error :: MissingImplementation ( " " , name . clone ( ) ) } ) } ) . collect :: < Result < Vec < _ > > > ( ) ? ; Ok ( D :: intersperse ( docs , D :: line ( ) . append ( D :: line ( ) ) ) ) }
Collects all of the Verilog implementations specified in the library
file.
Collects all of the Verilog implementations specified in the library file .
prog
&ast::NamespaceDef
context
&context::Context