fn csrrc(cpu: &mut Cpu, addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_csr(word);
    let t = match cpu.csr.read(o.csr, addr, &cpu.privilege) {
        Ok(data) => data as i64,
        Err(e) => return Err(e),
    };
    let data = (signed(cpu, t) & !cpu.x[o.rs1 as usize]) as u64;
    match cpu.csr.write(o.csr, data, addr, &cpu.privilege) {
        Ok(need_update_mmu_addressing_mode) => {
            if need_update_mmu_addressing_mode {
                cpu.mmu.update_addressing_mode(data);
            }
            cpu.x[o.rd as usize] = signed(cpu, t);
            Ok(())
        }
        Err(e) => Err(e),
    }
}
/// [csrrc rd,offset,rs1]
/// The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR,
/// zero- extends the value to XLEN bits, and writes it to integer register rd. The initial
/// value in integer register rs1 is treated as a bit mask that specifies bit positions to
/// be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to
/// be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected.
[csrrc rd,offset,rs1]
The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR,
zero- extends the value to XLEN bits, and writes it to integer register rd. The initial
value in integer register rs1 is treated as a bit mask that specifies bit positions to
be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to
be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected.
[ csrrc rd offset rs1 ] The CSRRC ( Atomic Read and Clear Bits in CSR ) instruction reads the value of the CSR zero - extends the value to XLEN bits and writes it to integer register rd . The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR . Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR if that CSR bit is writable . Other bits in the CSR are unaffected .
fn csrrc(cpu: &mut Cpu, addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_csr(word);
    let t = match cpu.csr.read(o.csr, addr, &cpu.privilege) {
        Ok(data) => data as i64,
        Err(e) => return Err(e),
    };
    let data = (signed(cpu, t) & !cpu.x[o.rs1 as usize]) as u64;
    match cpu.csr.write(o.csr, data, addr, &cpu.privilege) {
        Ok(need_update_mmu_addressing_mode) => {
            if need_update_mmu_addressing_mode {
                cpu.mmu.update_addressing_mode(data);
            }
            cpu.x[o.rd as usize] = signed(cpu, t);
            Ok(())
        }
        Err(e) => Err(e),
    }
}
fn csrrc ( cpu : & mut Cpu , addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_csr ( word ) ; let t = match cpu . csr . read ( o . csr , addr , & cpu . privilege ) { Ok ( data ) => data as i64 , Err ( e ) => return Err ( e ) , } ; let data = ( signed ( cpu , t ) & ! cpu . x [ o . rs1 as usize ] ) as u64 ; match cpu . csr . write ( o . csr , data , addr , & cpu . privilege ) { Ok ( need_update_mmu_addressing_mode ) => { if need_update_mmu_addressing_mode { cpu . mmu . update_addressing_mode ( data ) ; } cpu . x [ o . rd as usize ] = signed ( cpu , t ) ; Ok ( ( ) ) } Err ( e ) => Err ( e ) , } }
[csrrc rd,offset,rs1]
The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR,
zero- extends the value to XLEN bits, and writes it to integer register rd.
[ csrrc rd offset rs1 ] The CSRRC ( Atomic Read and Clear Bits in CSR ) instruction reads the value of the CSR zero - extends the value to XLEN bits and writes it to integer register rd .
cpu
&mut Cpu
addr
u64
word
u32