fn run<SPI, CS, RESET>(
    device: &mut MyDevice<ChipInterface<SPI, CS, RESET>>,
) -> Result<(), LowLevelError>
where
    SPI: Transfer<u8> + Write<u8>,
    CS: OutputPin,
    RESET: OutputPin,
{
    // We read the manufacturer
    let id = device.registers().id().read()?;

    // Print the id. It is marked with `#[generate(Debug)]`,
    // so it should only show all fields
    println!("{:?}", id);

    // Is it known?
    if id.manufacturer()? == Manufacturer::CarmineCrystal && id.version() == 6 && id.edition() == 5
    {
        // Yes, set pin 0 to output
        device
            .registers()
            .mode()
            .modify_index(2, |r, w| {
                println!("{:?}", r);
                w.mode(PinMode::Output)
            })?;
        // Enable output on pin 0
        device
            .registers()
            .port()
            .write(|w| w.output_0(Bit::Set).mask_0(Bit::Set))?;
        // Enable output on pin 1
        device.registers().port().write(|w| {
            w.output_1(Bit::Set);
            w.mask_1(Bit::Set);
            w
        })?;
        // Set the polarity to Active Low and enable it
        device.registers().irq_settings().modify(|r, w| {
            // Print the current value. It is not marked with `#[generate(Debug)]`,
            // so it should only show the raw value
            println!("{:?}", r);
            w.irq_enabled(Bit::Set);
            w.polarity(IrqPolarity::ActiveLow);
            w
        })?;
        // Disable the irq status bit
        device
            .registers()
            .irq_settings()
            .modify(|_, w| w.irq_status(Bit::Cleared))?;
    }

    Ok(())
}
/// Does some random register things to showcase how everything works
Does some random register things to showcase how everything works
Does some random register things to showcase how everything works
fn run<SPI, CS, RESET>(
    device: &mut MyDevice<ChipInterface<SPI, CS, RESET>>,
) -> Result<(), LowLevelError>
where
    SPI: Transfer<u8> + Write<u8>,
    CS: OutputPin,
    RESET: OutputPin,
{
    // We read the manufacturer
    let id = device.registers().id().read()?;
    // Print the id. It is marked with `#[generate(Debug)]`,
    // so it should only show all fields
    println!("{:?}", id);
    // Is it known?
    if id.manufacturer()? == Manufacturer::CarmineCrystal && id.version() == 6 && id.edition() == 5
    {
        // Yes, set pin 0 to output
        device
            .registers()
            .mode()
            .modify_index(2, |r, w| {
                println!("{:?}", r);
                w.mode(PinMode::Output)
            })?;
        // Enable output on pin 0
        device
            .registers()
            .port()
            .write(|w| w.output_0(Bit::Set).mask_0(Bit::Set))?;
        // Enable output on pin 1
        device.registers().port().write(|w| {
            w.output_1(Bit::Set);
            w.mask_1(Bit::Set);
            w
        })?;
        // Set the polarity to Active Low and enable it
        device.registers().irq_settings().modify(|r, w| {
            // Print the current value. It is not marked with `#[generate(Debug)]`,
            // so it should only show the raw value
            println!("{:?}", r);
            w.irq_enabled(Bit::Set);
            w.polarity(IrqPolarity::ActiveLow);
            w
        })?;
        // Disable the irq status bit
        device
            .registers()
            .irq_settings()
            .modify(|_, w| w.irq_status(Bit::Cleared))?;
    }
    Ok(())
}
fn run < SPI , CS , RESET > ( device : & mut MyDevice < ChipInterface < SPI , CS , RESET > > , ) -> Result < ( ) , LowLevelError > where SPI : Transfer < u8 > + Write < u8 > , CS : OutputPin , RESET : OutputPin , { // We read the manufacturer let id = device . registers ( ) . id ( ) . read ( ) ? ; // Print the id. It is marked with `#[generate(Debug)]`, // so it should only show all fields println ! ( " " id ) ; // Is it known? if id . manufacturer ( ) ? == Manufacturer :: CarmineCrystal && id . version ( ) == 6 && id . edition ( ) == 5 { // Yes, set pin 0 to output device . registers ( ) . mode ( ) . modify_index ( 2 , | r , w | { println ! ( " " r ) ; w . mode ( PinMode :: Output ) } ) ? ; // Enable output on pin 0 device . registers ( ) . port ( ) . write ( | w | w . output_0 ( Bit :: Set ) . mask_0 ( Bit :: Set ) ) ? ; // Enable output on pin 1 device . registers ( ) . port ( ) . write ( | w | { w . output_1 ( Bit :: Set ) ; w . mask_1 ( Bit :: Set ) ; w } ) ? ; // Set the polarity to Active Low and enable it device . registers ( ) . irq_settings ( ) . modify ( | r , w | { // Print the current value. It is not marked with `#[generate(Debug)]`, // so it should only show the raw value println ! ( " " r ) ; w . irq_enabled ( Bit :: Set ) ; w . polarity ( IrqPolarity :: ActiveLow ) ; w } ) ? ; // Disable the irq status bit device . registers ( ) . irq_settings ( ) . modify ( | _ , w | w . irq_status ( Bit :: Cleared ) ) ? ; } Ok ( ( ) ) }
Does some random register things to showcase how everything works
Does some random register things to showcase how everything works
device
&mut MyDevice<ChipInterface<SPI, CS, RESET>>