pub fn bitwidth<'a>(width: u64) -> Result<D<'a>> {
    match width.cmp(&1) {
        Ordering::Less => unreachable!(),
        Ordering::Equal => Ok(D::nil()),
        Ordering::Greater => {
            Ok(D::text(format!("[{}:0]", width - 1)).append(D::space()))
        }
    }
}
/// Turn u64 into a formatted Verilog bitwidth specifier.
Turn u64 into a formatted Verilog bitwidth specifier.
Turn u64 into a formatted Verilog bitwidth specifier .
pub fn bitwidth<'a>(width: u64) -> Result<D<'a>> {
    match width.cmp(&1) {
        Ordering::Less => unreachable!(),
        Ordering::Equal => Ok(D::nil()),
        Ordering::Greater => {
            Ok(D::text(format!("[{}:0]", width - 1)).append(D::space()))
        }
    }
}
pub fn bitwidth < ' a > ( width : u64 ) -> Result < D < ' a > > { match width . cmp ( & 1 ) { Ordering :: Less => unreachable ! ( ) , Ordering :: Equal => Ok ( D :: nil ( ) ) , Ordering :: Greater => { Ok ( D :: text ( format ! ( " " width 1 ) ) . append ( D :: space ( ) ) ) } } }
Turn u64 into a formatted Verilog bitwidth specifier.
Turn u64 into a formatted Verilog bitwidth specifier .
width
u64