fn fetch(&mut self) -> Result<(ByteInstruction, bool), String> {
        let pc = self.cpu.update_instruction_address();
        let mut instruction = self.instruction_cache.get_cached(pc)?;
        let mut start = tag::from(instruction);
        if !tag::has_cached(start) {
            let raw = self.memory.get_instr_word(pc)?;
            let decoded = decode_thumb(raw, InstructionContext::new(pc, self.cpu.itstate.position()));
            instruction = decoded.0;
            start = tag::from(instruction);
            if decoded.1 {
                self.instruction_cache.write_cache_wide(pc, instruction);
            } else {
                self.instruction_cache.write_cache_narrow(pc, instruction);
            }
        }
        let wide = tag::is_wide(start);
        self.cpu.inc_pc(wide);
        return Ok((instruction, wide));
    }
/**
     * Fetch: This stage
     * 1. Retrieves the address of the instruction to be executed
     * 2. Updates the PC value visible to instructions to be this + 4
     * 3. Attempts to find a cached instruction
     * 3a. If not cached, fetches direct bytes and decodes into the intermediate bytecode format
     * 3b. Caches decoded instruction
     * 4. Updates instruction pointed to by instruction PC to next instruction
     * 5. Returns fetched intermediate bytecode instruction & bool of width
     */
This stage
1. Retrieves the address of the instruction to be executed
2. Updates the PC value visible to instructions to be this + 4
3. Attempts to find a cached instruction
3a. If not cached, fetches direct bytes and decodes into the intermediate bytecode format
3b. Caches decoded instruction
4. Updates instruction pointed to by instruction PC to next instruction
5. Returns fetched intermediate bytecode instruction & bool of width
This stage 1 . Retrieves the address of the instruction to be executed 2 . Updates the PC value visible to instructions to be this + 4 3 . Attempts to find a cached instruction 3a . If not cached fetches direct bytes and decodes into the intermediate bytecode format 3b . Caches decoded instruction 4 . Updates instruction pointed to by instruction PC to next instruction 5 . Returns fetched intermediate bytecode instruction & bool of width
fn fetch(&mut self) -> Result<(ByteInstruction, bool), String> {
        let pc = self.cpu.update_instruction_address();
        let mut instruction = self.instruction_cache.get_cached(pc)?;
        let mut start = tag::from(instruction);
        if !tag::has_cached(start) {
            let raw = self.memory.get_instr_word(pc)?;
            let decoded = decode_thumb(raw, InstructionContext::new(pc, self.cpu.itstate.position()));
            instruction = decoded.0;
            start = tag::from(instruction);
            if decoded.1 {
                self.instruction_cache.write_cache_wide(pc, instruction);
            } else {
                self.instruction_cache.write_cache_narrow(pc, instruction);
            }
        }
        let wide = tag::is_wide(start);
        self.cpu.inc_pc(wide);
        return Ok((instruction, wide));
    }
fn fetch ( & mut self ) -> Result < ( ByteInstruction , bool ) , String > { let pc = self . cpu . update_instruction_address ( ) ; let mut instruction = self . instruction_cache . get_cached ( pc ) ? ; let mut start = tag :: from ( instruction ) ; if ! tag :: has_cached ( start ) { let raw = self . memory . get_instr_word ( pc ) ? ; let decoded = decode_thumb ( raw , InstructionContext :: new ( pc , self . cpu . itstate . position ( ) ) ) ; instruction = decoded . 0 ; start = tag :: from ( instruction ) ; if decoded . 1 { self . instruction_cache . write_cache_wide ( pc , instruction ) ; } else { self . instruction_cache . write_cache_narrow ( pc , instruction ) ; } } let wide = tag :: is_wide ( start ) ; self . cpu . inc_pc ( wide ) ; return Ok ( ( instruction , wide ) ) ; }
Fetch: This stage
 1.
Fetch : This stage 1 .
&mut self