pub fn max_speed(self, acr: &mut ACR, pwr: &mut PWR) -> Clocks {
        let rcc = unsafe { &*RCC::ptr() };

        // Configure PLL
        rcc.pllcfgr.modify(|_, w| unsafe {
            let val = rcc.pllcfgr.read().bits() | 0b01000000;
            w.bits(val);

            w.pllm()
                .bits(0b0001000)
                .plln()
                .bits(180)
                .pllp()
                .bits(0b00)
                .pllsrc()
                .hsi()
                .pllq()
                .bits(0b0010)
        });

        // Switch to overdrive mode and select SCALE_3 voltage output
        pwr.cr
            .write(|w| unsafe { w.odswen().set_bit().vos().bits(0b11) });
        // Wait for the switch
        while pwr.csr.read().odswrdy().bit_is_set() {}

        // Enable overdrive mode
        pwr.cr.write(|w| w.oden().set_bit());
        // Wait for activation
        while pwr.csr.read().odrdy().bit_is_set() {}

        rcc.cfgr.modify(|_, w| unsafe {
            // Enable PLL
            w
                // APB high-speed prescaler (APB2)
                .ppre2()
                .bits(0b100)
                // APB Low speed prescaler (APB1)
                .ppre1()
                .bits(0b101)
                // AHB prescaler
                .hpre()
                .bits(0b0000)
        });

        // Enable PLL
        rcc.cr.write(|w| w.pllon().set_bit());
        // Wait for PLL ready
        while rcc.cr.read().pllrdy().bit_is_clear() {}

        // Configure the wait states
        acr.acr().write(|w| unsafe { w.latency().bits(5) });

        while acr.acr().read().latency().bits() != 5 {}
        /*
        let reg: *mut u8 = 0x40023808 as *mut _;

        unsafe {
            let val = *reg | 0b10;
            *reg = val;
        }*/

        rcc.cfgr.modify(|_, w| unsafe {
            w.sw().bits(0b10) // Select PLL as system clock
        });

        while !rcc.cfgr.read().sw().is_pll() {}

        Clocks {
            hclk: Hertz(180_000_000),
            pclk1: Hertz(45_000_000),
            pclk2: Hertz(90_000_000),
            ppre1: 0b101,
            ppre2: 0b100,
            sysclk: Hertz(180_000_000),
        }
    }
/// Set the maximum speed on all clocks.
Set the maximum speed on all clocks.
Set the maximum speed on all clocks .
pub fn max_speed(self, acr: &mut ACR, pwr: &mut PWR) -> Clocks {
        let rcc = unsafe { &*RCC::ptr() };
        // Configure PLL
        rcc.pllcfgr.modify(|_, w| unsafe {
            let val = rcc.pllcfgr.read().bits() | 0b01000000;
            w.bits(val);
            w.pllm()
                .bits(0b0001000)
                .plln()
                .bits(180)
                .pllp()
                .bits(0b00)
                .pllsrc()
                .hsi()
                .pllq()
                .bits(0b0010)
        });
        // Switch to overdrive mode and select SCALE_3 voltage output
        pwr.cr
            .write(|w| unsafe { w.odswen().set_bit().vos().bits(0b11) });
        // Wait for the switch
        while pwr.csr.read().odswrdy().bit_is_set() {}
        // Enable overdrive mode
        pwr.cr.write(|w| w.oden().set_bit());
        // Wait for activation
        while pwr.csr.read().odrdy().bit_is_set() {}
        rcc.cfgr.modify(|_, w| unsafe {
            // Enable PLL
            w
                // APB high-speed prescaler (APB2)
                .ppre2()
                .bits(0b100)
                // APB Low speed prescaler (APB1)
                .ppre1()
                .bits(0b101)
                // AHB prescaler
                .hpre()
                .bits(0b0000)
        });
        // Enable PLL
        rcc.cr.write(|w| w.pllon().set_bit());
        // Wait for PLL ready
        while rcc.cr.read().pllrdy().bit_is_clear() {}
        // Configure the wait states
        acr.acr().write(|w| unsafe { w.latency().bits(5) });
        while acr.acr().read().latency().bits() != 5 {}
        /*
        let reg: *mut u8 = 0x40023808 as *mut _;
        unsafe {
            let val = *reg | 0b10;
            *reg = val;
        }*/
        rcc.cfgr.modify(|_, w| unsafe {
            w.sw().bits(0b10) // Select PLL as system clock
        });
        while !rcc.cfgr.read().sw().is_pll() {}
        Clocks {
            hclk: Hertz(180_000_000),
            pclk1: Hertz(45_000_000),
            pclk2: Hertz(90_000_000),
            ppre1: 0b101,
            ppre2: 0b100,
            sysclk: Hertz(180_000_000),
        }
    }
pub fn max_speed ( self , acr : & mut ACR , pwr : & mut PWR ) -> Clocks { let rcc = unsafe { & * RCC :: ptr ( ) } ; // Configure PLL rcc . pllcfgr . modify ( | _ , w | unsafe { let val = rcc . pllcfgr . read ( ) . bits ( ) | 0b01000000 ; w . bits ( val ) ; w . pllm ( ) . bits ( 0b0001000 ) . plln ( ) . bits ( 180 ) . pllp ( ) . bits ( 0b00 ) . pllsrc ( ) . hsi ( ) . pllq ( ) . bits ( 0b0010 ) } ) ; // Switch to overdrive mode and select SCALE_3 voltage output pwr . cr . write ( | w | unsafe { w . odswen ( ) . set_bit ( ) . vos ( ) . bits ( 0b11 ) } ) ; // Wait for the switch while pwr . csr . read ( ) . odswrdy ( ) . bit_is_set ( ) { } // Enable overdrive mode pwr . cr . write ( | w | w . oden ( ) . set_bit ( ) ) ; // Wait for activation while pwr . csr . read ( ) . odrdy ( ) . bit_is_set ( ) { } rcc . cfgr . modify ( | _ , w | unsafe { // Enable PLL w // APB high-speed prescaler (APB2) . ppre2 ( ) . bits ( 0b100 ) // APB Low speed prescaler (APB1) . ppre1 ( ) . bits ( 0b101 ) // AHB prescaler . hpre ( ) . bits ( 0b0000 ) } ) ; // Enable PLL rcc . cr . write ( | w | w . pllon ( ) . set_bit ( ) ) ; // Wait for PLL ready while rcc . cr . read ( ) . pllrdy ( ) . bit_is_clear ( ) { } // Configure the wait states acr . acr ( ) . write ( | w | unsafe { w . latency ( ) . bits ( 5 ) } ) ; while acr . acr ( ) . read ( ) . latency ( ) . bits ( ) != 5 { } /*
        let reg: *mut u8 = 0x40023808 as *mut _;

        unsafe {
            let val = *reg | 0b10;
            *reg = val;
        }*/ rcc . cfgr . modify ( | _ , w | unsafe { w . sw ( ) . bits ( 0b10 ) // Select PLL as system clock } ) ; while ! rcc . cfgr . read ( ) . sw ( ) . is_pll ( ) { } Clocks { hclk : Hertz ( 180_000_000 ) , pclk1 : Hertz ( 45_000_000 ) , pclk2 : Hertz ( 90_000_000 ) , ppre1 : 0b101 , ppre2 : 0b100 , sysclk : Hertz ( 180_000_000 ) , } }
Set the maximum speed on all clocks.
Set the maximum speed on all clocks .
self
acr
&mut ACR
pwr
&mut PWR