fn exit(&mut self) {
		// Exit

		#[cfg(feature = "dramsim")]
		{
			send_request(
				format!(
					"{:016x} {} {}",
					0xffff_ffff_ffff_ffffu64,
					"END",
					self.cpu.read_csr_raw(CSR_MCYCLE_ADDRESS)
				)
				.as_str(),
			);
			terminate_pipe();
		}
		//
		println!(
			"total Latency = {} cycles",
			self.cpu.read_csr_raw(CSR_MCYCLE_ADDRESS)
		);
		// L1 Cache hit/miss
		let l1_hit_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER3_ADDRESS);
		let l1_miss_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER4_ADDRESS);
		// L2 Cache hit/miss
		let _l2_hit_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER5_ADDRESS);
		let l2_miss_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER6_ADDRESS);
		println!(
			"Cache Hit rate = {}%",
			100f32 * (1f32 - (l2_miss_num as f32 / (l1_hit_num + l1_miss_num) as f32))
		);
		println!(
			"Cache Miss rate = {}%",
			((l2_miss_num * 100) as f32 / (l1_hit_num + l1_miss_num) as f32) as f32
		);

		// Average hit latency
		println!(
			"Cache Hit Latency = {} cycles",
			(l1_hit_num as f32 * L1_CACHE_HIT_LATENCY as f32
				+ l1_miss_num as f32 * L2_CACHE_HIT_LATENCY as f32)
				/ (l1_hit_num as f32 + l1_miss_num as f32)
		);

		// Average miss latency
		println!(
			"Cache Miss Latency = {} cycles",
			(self.cpu.mmu.dram_latency as f32) / (l2_miss_num as f32)
		);

		let exit_time = SystemTime::now()
			.duration_since(SystemTime::UNIX_EPOCH)
			.unwrap()
			.as_secs_f64();
		// Total run time
		println!("Real run time = {} seconds", (exit_time - self.run_time));
		process::exit(0);
	}
/// Exit method. Prints needed output
///
Exit method. Prints needed output
Exit method . Prints needed output
fn exit(&mut self) {
		// Exit
		#[cfg(feature = "dramsim")]
		{
			send_request(
				format!(
					"{:016x} {} {}",
					0xffff_ffff_ffff_ffffu64,
					"END",
					self.cpu.read_csr_raw(CSR_MCYCLE_ADDRESS)
				)
				.as_str(),
			);
			terminate_pipe();
		}
		//
		println!(
			"total Latency = {} cycles",
			self.cpu.read_csr_raw(CSR_MCYCLE_ADDRESS)
		);
		// L1 Cache hit/miss
		let l1_hit_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER3_ADDRESS);
		let l1_miss_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER4_ADDRESS);
		// L2 Cache hit/miss
		let _l2_hit_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER5_ADDRESS);
		let l2_miss_num = self.cpu.read_csr_raw(CSR_HPMCOUNTER6_ADDRESS);
		println!(
			"Cache Hit rate = {}%",
			100f32 * (1f32 - (l2_miss_num as f32 / (l1_hit_num + l1_miss_num) as f32))
		);
		println!(
			"Cache Miss rate = {}%",
			((l2_miss_num * 100) as f32 / (l1_hit_num + l1_miss_num) as f32) as f32
		);
		// Average hit latency
		println!(
			"Cache Hit Latency = {} cycles",
			(l1_hit_num as f32 * L1_CACHE_HIT_LATENCY as f32
				+ l1_miss_num as f32 * L2_CACHE_HIT_LATENCY as f32)
				/ (l1_hit_num as f32 + l1_miss_num as f32)
		);
		// Average miss latency
		println!(
			"Cache Miss Latency = {} cycles",
			(self.cpu.mmu.dram_latency as f32) / (l2_miss_num as f32)
		);
		let exit_time = SystemTime::now()
			.duration_since(SystemTime::UNIX_EPOCH)
			.unwrap()
			.as_secs_f64();
		// Total run time
		println!("Real run time = {} seconds", (exit_time - self.run_time));
		process::exit(0);
	}
fn exit ( & mut self ) { // Exit # [ cfg ( feature " " ) ] { send_request ( format ! ( " " 0xffff_ffff_ffff_ffffu64 " " self cpu read_csr_raw ( CSR_MCYCLE_ADDRESS ) ) . as_str ( ) , ) ; terminate_pipe ( ) ; } // println ! ( " " self cpu read_csr_raw ( CSR_MCYCLE_ADDRESS ) ) ; // L1 Cache hit/miss let l1_hit_num = self . cpu . read_csr_raw ( CSR_HPMCOUNTER3_ADDRESS ) ; let l1_miss_num = self . cpu . read_csr_raw ( CSR_HPMCOUNTER4_ADDRESS ) ; // L2 Cache hit/miss let _l2_hit_num = self . cpu . read_csr_raw ( CSR_HPMCOUNTER5_ADDRESS ) ; let l2_miss_num = self . cpu . read_csr_raw ( CSR_HPMCOUNTER6_ADDRESS ) ; println ! ( " " 100f32 ( 1f32 ( l2_miss_num as f32 ( l1_hit_num l1_miss_num ) as f32 ) ) ) ; println ! ( " " ( ( l2_miss_num 100 ) as f32 ( l1_hit_num l1_miss_num ) as f32 ) as f32 ) ; // Average hit latency println ! ( " " ( l1_hit_num as f32 L1_CACHE_HIT_LATENCY as f32 l1_miss_num as f32 L2_CACHE_HIT_LATENCY as f32 ) ( l1_hit_num as f32 l1_miss_num as f32 ) ) ; // Average miss latency println ! ( " " ( self cpu mmu dram_latency as f32 ) ( l2_miss_num as f32 ) ) ; let exit_time = SystemTime :: now ( ) . duration_since ( SystemTime :: UNIX_EPOCH ) . unwrap ( ) . as_secs_f64 ( ) ; // Total run time println ! ( " " ( exit_time self run_time ) ) ; process :: exit ( 0 ) ; }
Exit method.
Exit method .
&mut self