pub unsafe fn ff_instruction_cmp_b(rs1: u8, rs2: u8, op: FlexfloatOpCmp, fpmode_dst: bool) -> bool {
    let env_fp8_dst: flexfloat_desc_t = if fpmode_dst { env_fp8alt } else { env_fp8 };

    let ff_a: *mut flexfloat_t = &mut flexfloat_t {
        value: 0.0,
        desc: env_fp8_dst,
    };
    let ff_b: *mut flexfloat_t = &mut flexfloat_t {
        value: 0.0,
        desc: env_fp8_dst,
    };

    flexfloat_set_bits(ff_a, rs1 as u64);
    flexfloat_set_bits(ff_b, rs2 as u64);

    let res: bool = match op {
        FlexfloatOpCmp::Feq => ff_eq(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Flt => ff_lt(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fle => ff_le(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fge => ff_ge(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fgt => ff_gt(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fne => ff_neq(ff_a, ff_b), // 1 or 0 to int reg (32bit)
    };

    res
}
/// fp8 and fp8alt comparison instruction emulation
fp8 and fp8alt comparison instruction emulation
fp8 and fp8alt comparison instruction emulation
pub unsafe fn ff_instruction_cmp_b(rs1: u8, rs2: u8, op: FlexfloatOpCmp, fpmode_dst: bool) -> bool {
    let env_fp8_dst: flexfloat_desc_t = if fpmode_dst { env_fp8alt } else { env_fp8 };
    let ff_a: *mut flexfloat_t = &mut flexfloat_t {
        value: 0.0,
        desc: env_fp8_dst,
    };
    let ff_b: *mut flexfloat_t = &mut flexfloat_t {
        value: 0.0,
        desc: env_fp8_dst,
    };
    flexfloat_set_bits(ff_a, rs1 as u64);
    flexfloat_set_bits(ff_b, rs2 as u64);
    let res: bool = match op {
        FlexfloatOpCmp::Feq => ff_eq(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Flt => ff_lt(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fle => ff_le(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fge => ff_ge(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fgt => ff_gt(ff_a, ff_b), // 1 or 0 to int reg (32bit)
        FlexfloatOpCmp::Fne => ff_neq(ff_a, ff_b), // 1 or 0 to int reg (32bit)
    };
    res
}
pub unsafe fn ff_instruction_cmp_b ( rs1 : u8 , rs2 : u8 , op : FlexfloatOpCmp , fpmode_dst : bool ) -> bool { let env_fp8_dst : flexfloat_desc_t = if fpmode_dst { env_fp8alt } else { env_fp8 } ; let ff_a : * mut flexfloat_t = & mut flexfloat_t { value : 0.0 , desc : env_fp8_dst , } ; let ff_b : * mut flexfloat_t = & mut flexfloat_t { value : 0.0 , desc : env_fp8_dst , } ; flexfloat_set_bits ( ff_a , rs1 as u64 ) ; flexfloat_set_bits ( ff_b , rs2 as u64 ) ; let res : bool = match op { FlexfloatOpCmp :: Feq => ff_eq ( ff_a , ff_b ) , // 1 or 0 to int reg (32bit) FlexfloatOpCmp :: Flt => ff_lt ( ff_a , ff_b ) , // 1 or 0 to int reg (32bit) FlexfloatOpCmp :: Fle => ff_le ( ff_a , ff_b ) , // 1 or 0 to int reg (32bit) FlexfloatOpCmp :: Fge => ff_ge ( ff_a , ff_b ) , // 1 or 0 to int reg (32bit) FlexfloatOpCmp :: Fgt => ff_gt ( ff_a , ff_b ) , // 1 or 0 to int reg (32bit) FlexfloatOpCmp :: Fne => ff_neq ( ff_a , ff_b ) , // 1 or 0 to int reg (32bit) } ; res }
fp8 and fp8alt comparison instruction emulation
fp8 and fp8alt comparison instruction emulation
rs1
u8
rs2
u8
op
FlexfloatOpCmp
fpmode_dst
bool