fn wire_id_from_node<'a>(node: &Node, port: String) -> D<'a> {
    match &node.data {
        NodeData::Cell(..) => {
            D::text(format!("{}_{}", node.name.to_string(), port))
        }
        NodeData::Port => D::text(port),
        NodeData::Hole(name) => {
            unreachable!(format!("Structure has a hole: {}", name.id))
        }
        NodeData::Constant(n) => D::text(format!("{}'d{}", n.width, n.val)),
    }
}
/// Generates a Verilog identifier for a (Node, String).
///  * NodeData::Cell(..) => name_port
///  * NodeData::Port => port
///  * NodeData::Hole => impossible!
///  * NodeData::Constant({width: w, value: v}) => w'dv
Generates a Verilog identifier for a (Node, String).
Generates a Verilog identifier for a ( Node String ) .
fn wire_id_from_node<'a>(node: &Node, port: String) -> D<'a> {
    match &node.data {
        NodeData::Cell(..) => {
            D::text(format!("{}_{}", node.name.to_string(), port))
        }
        NodeData::Port => D::text(port),
        NodeData::Hole(name) => {
            unreachable!(format!("Structure has a hole: {}", name.id))
        }
        NodeData::Constant(n) => D::text(format!("{}'d{}", n.width, n.val)),
    }
}
fn wire_id_from_node < ' a > ( node : & Node , port : String ) -> D < ' a > { match & node . data { NodeData :: Cell ( .. ) => { D :: text ( format ! ( " " node name to_string ( ) port ) ) } NodeData :: Port => D :: text ( port ) , NodeData :: Hole ( name ) => { unreachable ! ( format ( " " name id ) ) } NodeData :: Constant ( n ) => D :: text ( format ! ( " " n width n val ) ) , } }
Generates a Verilog identifier for a (Node, String).
Generates a Verilog identifier for a ( Node String ) .
node
&Node
port
String