fn wire_declarations<'a>(comp: &component::Component) -> Result<D<'a>> {
    let wires = comp
        .structure
        .component_iterator()
        // filter for cells because we don't need to declare wires for ports
        .filter_map(|(_idx, node)| match &node.data {
            NodeData::Cell(_) => Some(node),
            _ => None,
        })
        // extract name, portdef from input / output of signature
        .map(|node| {
            node.signature
                .inputs
                .iter()
                .map(move |pd| (&node.name, pd))
                .chain(
                    node.signature
                        .outputs
                        .iter()
                        .map(move |pd| (&node.name, pd)),
                )
        })
        .flatten()
        // XXX(sam), definitely could use `test` here
        .map(|(name, portdef)| {
            Ok(D::text("logic")
                .keyword_color()
                .append(D::space())
                .append(bitwidth(portdef.width)?)
                .append(format!(
                    "{}_{}",
                    name.to_string(),
                    portdef.name.to_string()
                ))
                .append(";"))
        })
        .collect::<Result<Vec<_>>>()?;
    Ok(D::intersperse(wires, D::line()))
}
//==========================================
//        Wire Declaration Functions
//==========================================
/// Generate all the wire declarations for `comp`
Wire Declaration Functions
Generate all the wire declarations for `comp`
Wire Declaration Functions Generate all the wire declarations for ` comp `
fn wire_declarations<'a>(comp: &component::Component) -> Result<D<'a>> {
    let wires = comp
        .structure
        .component_iterator()
        // filter for cells because we don't need to declare wires for ports
        .filter_map(|(_idx, node)| match &node.data {
            NodeData::Cell(_) => Some(node),
            _ => None,
        })
        // extract name, portdef from input / output of signature
        .map(|node| {
            node.signature
                .inputs
                .iter()
                .map(move |pd| (&node.name, pd))
                .chain(
                    node.signature
                        .outputs
                        .iter()
                        .map(move |pd| (&node.name, pd)),
                )
        })
        .flatten()
        // XXX(sam), definitely could use `test` here
        .map(|(name, portdef)| {
            Ok(D::text("logic")
                .keyword_color()
                .append(D::space())
                .append(bitwidth(portdef.width)?)
                .append(format!(
                    "{}_{}",
                    name.to_string(),
                    portdef.name.to_string()
                ))
                .append(";"))
        })
        .collect::<Result<Vec<_>>>()?;
    Ok(D::intersperse(wires, D::line()))
}
fn wire_declarations < ' a > ( comp : & component :: Component ) -> Result < D < ' a > > { let wires = comp . structure . component_iterator ( ) // filter for cells because we don't need to declare wires for ports . filter_map ( | ( _idx , node ) | match & node . data { NodeData :: Cell ( _ ) => Some ( node ) , _ => None , } ) // extract name, portdef from input / output of signature . map ( | node | { node . signature . inputs . iter ( ) . map ( move | pd | ( & node . name , pd ) ) . chain ( node . signature . outputs . iter ( ) . map ( move | pd | ( & node . name , pd ) ) , ) } ) . flatten ( ) // XXX(sam), definitely could use `test` here . map ( | ( name , portdef ) | { Ok ( D :: text ( " " ) . keyword_color ( ) . append ( D :: space ( ) ) . append ( bitwidth ( portdef . width ) ? ) . append ( format ! ( " " name to_string ( ) portdef name to_string ( ) ) ) . append ( " " ) ) } ) . collect :: < Result < Vec < _ > > > ( ) ? ; Ok ( D :: intersperse ( wires , D :: line ( ) ) ) }
Wire Declaration Functions
Generate all the wire declarations for `comp`
Wire Declaration Functions Generate all the wire declarations for ` comp `
comp
&component::Component