pub fn cycle(&mut self, bus_cell: &InfCell<Bus>) {
        let bus = bus_cell.get_mut();
        let bus_ref = bus_cell.get_mut();
        let mut cpu = &mut bus.cpu;
        let mut pia = &mut bus.pia;
        
        // === OSC CLOCK === //
        //TODO: TIA stuff here
        if !self.vblank && self.cycles.color_clock >= 68 && bus.tia.cycles.frame_counter > 0 {
            let pixel = self.cycles.color_clock - 68;
            let dot = pixel / 4;
            let pf_bit = self.pf_lut(dot, self.ctrlpf & 0b1 != 0);
            let color = self.color_lut(pf_bit);
            //println!("scan: {}, pixel: {}, dot: {}, pf_bit: {}, color: {:08X}", self.cycles.scanline, pixel, dot, pf_bit, color);
            
            self.framebuffer[self.cycles.pixel_index()] = color;
            
            //self.framebuffer[self.cycles.pixel_index()] = ((self.pf0 as u32) << 16) | ((self.pf1 as u32) << 8) | (self.pf2 as u32);
        }
        
        //self.debug_color_clock();
        
        cpu.rdy = !self.wsync;
        
        if self.cycles.div3 == 0 {
            // === Phi 0 CLOCK === //
            //println!("Cycles: {}", self.cycles.frame_cpu_counter);
            self.cycles.frame_cpu_counter += 1;
            
            cpu.cycle(bus_cell);
            
            // === Phi 2 CLOCK === //
            pia.cycle(bus_cell);
        }
        
        self.debug_playfield();
        
        //println!("FRAME: {}, SCANLINE: {}, HORIZ: {}, INTIM: {:02X}, INTIM_COUNTER: {:04X}, INTERVAL: {} ({})", self.cycles.frame_counter, self.cycles.scanline, self.cycles.color_clock, bus.pia.intim, bus.pia.intim_counter, bus.pia.intim_interval, bus.pia.intim_interval_active);
        self.cycles.osc_cycle();
        if self.cycles.color_clock == 0 {
            self.wsync = false;
        }
        if self.vsync_trigger && !self.vsync {
            self.cycles.frame_cpu_counter = 0;
            self.cycles.scanline = 0;
            println!("new frame, color_clock: {}", self.cycles.color_clock);
            self.cycles.color_clock = 0;
            self.cycles.frame_counter += 1;
            //println!("=================================================================");
            //println!("======================= NEW FRAME STARTED =======================");
            //println!("=================================================================");
            self.vsync_trigger = false;
        }
    }
/// Perform one clock cycle of the TIA chip. This chip contains a clock divider which
/// drives the CPU's PHI0 clock input. This function should not be called from within
/// the CPU.
/// 
/// In respect to real time, this function should be called approx 3,584,160 (3.58 MHz) times
/// per second.
/// 
/// The TIA will process its clock first, and then depending on the divider, will clock the CPU.
Perform one clock cycle of the TIA chip. This chip contains a clock divider which
drives the CPU's PHI0 clock input. This function should not be called from within
the CPU.

In respect to real time, this function should be called approx 3,584,160 (3.58 MHz) times
per second.

The TIA will process its clock first, and then depending on the divider, will clock the CPU.
Perform one clock cycle of the TIA chip . This chip contains a clock divider which drives the CPU ' s PHI0 clock input . This function should not be called from within the CPU . In respect to real time this function should be called approx 3 584 160 ( 3 . 58 MHz ) times per second . The TIA will process its clock first and then depending on the divider will clock the CPU .
pub fn cycle(&mut self, bus_cell: &InfCell<Bus>) {
        let bus = bus_cell.get_mut();
        let bus_ref = bus_cell.get_mut();
        let mut cpu = &mut bus.cpu;
        let mut pia = &mut bus.pia;
        // === OSC CLOCK === //
        //TODO: TIA stuff here
        if !self.vblank && self.cycles.color_clock >= 68 && bus.tia.cycles.frame_counter > 0 {
            let pixel = self.cycles.color_clock - 68;
            let dot = pixel / 4;
            let pf_bit = self.pf_lut(dot, self.ctrlpf & 0b1 != 0);
            let color = self.color_lut(pf_bit);
            //println!("scan: {}, pixel: {}, dot: {}, pf_bit: {}, color: {:08X}", self.cycles.scanline, pixel, dot, pf_bit, color);
            self.framebuffer[self.cycles.pixel_index()] = color;
            //self.framebuffer[self.cycles.pixel_index()] = ((self.pf0 as u32) << 16) | ((self.pf1 as u32) << 8) | (self.pf2 as u32);
        }
        //self.debug_color_clock();
        cpu.rdy = !self.wsync;
        if self.cycles.div3 == 0 {
            // === Phi 0 CLOCK === //
            //println!("Cycles: {}", self.cycles.frame_cpu_counter);
            self.cycles.frame_cpu_counter += 1;
            cpu.cycle(bus_cell);
            // === Phi 2 CLOCK === //
            pia.cycle(bus_cell);
        }
        self.debug_playfield();
        //println!("FRAME: {}, SCANLINE: {}, HORIZ: {}, INTIM: {:02X}, INTIM_COUNTER: {:04X}, INTERVAL: {} ({})", self.cycles.frame_counter, self.cycles.scanline, self.cycles.color_clock, bus.pia.intim, bus.pia.intim_counter, bus.pia.intim_interval, bus.pia.intim_interval_active);
        self.cycles.osc_cycle();
        if self.cycles.color_clock == 0 {
            self.wsync = false;
        }
        if self.vsync_trigger && !self.vsync {
            self.cycles.frame_cpu_counter = 0;
            self.cycles.scanline = 0;
            println!("new frame, color_clock: {}", self.cycles.color_clock);
            self.cycles.color_clock = 0;
            self.cycles.frame_counter += 1;
            //println!("=================================================================");
            //println!("======================= NEW FRAME STARTED =======================");
            //println!("=================================================================");
            self.vsync_trigger = false;
        }
    }
pub fn cycle ( & mut self , bus_cell : & InfCell < Bus > ) { let bus = bus_cell . get_mut ( ) ; let bus_ref = bus_cell . get_mut ( ) ; let mut cpu = & mut bus . cpu ; let mut pia = & mut bus . pia ; // === OSC CLOCK === // //TODO: TIA stuff here if ! self . vblank && self . cycles . color_clock >= 68 && bus . tia . cycles . frame_counter > 0 { let pixel = self . cycles . color_clock - 68 ; let dot = pixel / 4 ; let pf_bit = self . pf_lut ( dot , self . ctrlpf & 0b1 != 0 ) ; let color = self . color_lut ( pf_bit ) ; //println!("scan: {}, pixel: {}, dot: {}, pf_bit: {}, color: {:08X}", self.cycles.scanline, pixel, dot, pf_bit, color); self . framebuffer [ self . cycles . pixel_index ( ) ] = color ; //self.framebuffer[self.cycles.pixel_index()] = ((self.pf0 as u32) << 16) | ((self.pf1 as u32) << 8) | (self.pf2 as u32); } //self.debug_color_clock(); cpu . rdy = ! self . wsync ; if self . cycles . div3 == 0 { // === Phi 0 CLOCK === // //println!("Cycles: {}", self.cycles.frame_cpu_counter); self . cycles . frame_cpu_counter += 1 ; cpu . cycle ( bus_cell ) ; // === Phi 2 CLOCK === // pia . cycle ( bus_cell ) ; } self . debug_playfield ( ) ; //println!("FRAME: {}, SCANLINE: {}, HORIZ: {}, INTIM: {:02X}, INTIM_COUNTER: {:04X}, INTERVAL: {} ({})", self.cycles.frame_counter, self.cycles.scanline, self.cycles.color_clock, bus.pia.intim, bus.pia.intim_counter, bus.pia.intim_interval, bus.pia.intim_interval_active); self . cycles . osc_cycle ( ) ; if self . cycles . color_clock == 0 { self . wsync = false ; } if self . vsync_trigger && ! self . vsync { self . cycles . frame_cpu_counter = 0 ; self . cycles . scanline = 0 ; println ! ( " " self cycles color_clock ) ; self . cycles . color_clock = 0 ; self . cycles . frame_counter += 1 ; //println!("================================================================="); //println!("======================= NEW FRAME STARTED ======================="); //println!("================================================================="); self . vsync_trigger = false ; } }
Perform one clock cycle of the TIA chip.
Perform one clock cycle of the TIA chip .
&mut self
bus_cell
&InfCell<Bus>