fn addi(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_i(word);
    cpu.x[o.rd as usize] = signed(cpu, cpu.x[o.rs1 as usize].wrapping_add(o.imm));
    Ok(())
}
//==============================================================================
// Integer Register-Immediate Instructions (RV32I/RV64I)
//==============================================================================
/// [addi rd,rs1,imm]
/// ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overfl ow is ignored and
/// the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV
/// rd, rs1 assembler pseudoinstruction.
Integer Register-Immediate Instructions (RV32I/RV64I)
[addi rd,rs1,imm]
ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overfl ow is ignored and
the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV
rd, rs1 assembler pseudoinstruction.
Integer Register - Immediate Instructions ( RV32I / RV64I ) [ addi rd rs1 imm ] ADDI adds the sign - extended 12 - bit immediate to register rs1 . Arithmetic overfl ow is ignored and the result is simply the low XLEN bits of the result . ADDI rd rs1 0 is used to implement the MV rd rs1 assembler pseudoinstruction .
fn addi(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_i(word);
    cpu.x[o.rd as usize] = signed(cpu, cpu.x[o.rs1 as usize].wrapping_add(o.imm));
    Ok(())
}
fn addi ( cpu : & mut Cpu , _addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_i ( word ) ; cpu . x [ o . rd as usize ] = signed ( cpu , cpu . x [ o . rs1 as usize ] . wrapping_add ( o . imm ) ) ; Ok ( ( ) ) }
Integer Register-Immediate Instructions (RV32I/RV64I)
[addi rd,rs1,imm]
ADDI adds the sign-extended 12-bit immediate to register rs1.
Integer Register - Immediate Instructions ( RV32I / RV64I ) [ addi rd rs1 imm ] ADDI adds the sign - extended 12 - bit immediate to register rs1 .
cpu
&mut Cpu
_addr
u64
word
u32