fn store_bytes(&mut self, v_address: u64, value: u64, width: u64) -> Result<(), Trap> {
		debug_assert!(
			width == 1 || width == 2 || width == 4 || width == 8,
			"Width must be 1, 2, 4, or 8. {:X}",
			width
		);
		match (v_address & 0xfff) <= (0x1000 - width) {
			true => match self.translate_address(v_address, &MemoryAccessType::Write) {
				Ok(p_address) => {
					// Store to cache
					// @TODO: store buffer
					// Get allocated cache line's way index
					#[cfg(feature = "debug-cache")]
					println!(
						"\nstore 0x{:x} of {}bytes @ 0x{:x}",
						value, width, p_address
					);

					// pre-parse index
					let l1_index: u64 =
						(p_address >> L1_CACHE_OFFSET_BITS) & ((1 << L1_CACHE_INDEX_BITS) - 1);
					let _l1_tag: u64 = p_address >> (L1_CACHE_INDEX_BITS + L1_CACHE_OFFSET_BITS);
					let l1_offset = p_address & ((1 << L1_CACHE_OFFSET_BITS) - 1);

					let l1_way = match self.aquire_cache_line(p_address) {
						Ok(l1_way) => l1_way,
						Err(trap) => return Err(trap),
					};

					// Update cache line
					self.l1_cache.data[l1_index as usize].data[l1_way as usize]
						.set(l1_offset, width, value);

					Ok(())
				}
				Err(()) => Err(Trap {
					trap_type: TrapType::StorePageFault,
					value: v_address,
				}),
			},
			false => {
				for i in 0..width {
					match self.store(v_address.wrapping_add(i), ((value >> (i * 8)) & 0xff) as u8) {
						Ok(()) => {}
						Err(e) => return Err(e),
					}
				}
				Ok(())
			}
		}
	}
/// Stores multiple bytes. This method takes virtual address and translates
/// into physical address inside.
///
/// # Arguments
/// * `v_address` Virtual address
/// * `value` data written
/// * `width` Must be 1, 2, 4, or 8
Stores multiple bytes. This method takes virtual address and translates
into physical address inside.
Stores multiple bytes . This method takes virtual address and translates into physical address inside .
fn store_bytes(&mut self, v_address: u64, value: u64, width: u64) -> Result<(), Trap> {
		debug_assert!(
			width == 1 || width == 2 || width == 4 || width == 8,
			"Width must be 1, 2, 4, or 8. {:X}",
			width
		);
		match (v_address & 0xfff) <= (0x1000 - width) {
			true => match self.translate_address(v_address, &MemoryAccessType::Write) {
				Ok(p_address) => {
					// Store to cache
					// @TODO: store buffer
					// Get allocated cache line's way index
					#[cfg(feature = "debug-cache")]
					println!(
						"\nstore 0x{:x} of {}bytes @ 0x{:x}",
						value, width, p_address
					);
					// pre-parse index
					let l1_index: u64 =
						(p_address >> L1_CACHE_OFFSET_BITS) & ((1 << L1_CACHE_INDEX_BITS) - 1);
					let _l1_tag: u64 = p_address >> (L1_CACHE_INDEX_BITS + L1_CACHE_OFFSET_BITS);
					let l1_offset = p_address & ((1 << L1_CACHE_OFFSET_BITS) - 1);
					let l1_way = match self.aquire_cache_line(p_address) {
						Ok(l1_way) => l1_way,
						Err(trap) => return Err(trap),
					};
					// Update cache line
					self.l1_cache.data[l1_index as usize].data[l1_way as usize]
						.set(l1_offset, width, value);
					Ok(())
				}
				Err(()) => Err(Trap {
					trap_type: TrapType::StorePageFault,
					value: v_address,
				}),
			},
			false => {
				for i in 0..width {
					match self.store(v_address.wrapping_add(i), ((value >> (i * 8)) & 0xff) as u8) {
						Ok(()) => {}
						Err(e) => return Err(e),
					}
				}
				Ok(())
			}
		}
	}
fn store_bytes ( & mut self , v_address : u64 , value : u64 , width : u64 ) -> Result < ( ) , Trap > { debug_assert ! ( width 1 width 2 width 4 width 8 " " width ) ; match ( v_address & 0xfff ) <= ( 0x1000 - width ) { true => match self . translate_address ( v_address , & MemoryAccessType :: Write ) { Ok ( p_address ) => { // Store to cache // @TODO: store buffer // Get allocated cache line's way index # [ cfg ( feature " " ) ] println ! ( " \n " value width p_address ) ; // pre-parse index let l1_index : u64 = ( p_address >> L1_CACHE_OFFSET_BITS ) & ( ( 1 << L1_CACHE_INDEX_BITS ) - 1 ) ; let _l1_tag : u64 = p_address >> ( L1_CACHE_INDEX_BITS + L1_CACHE_OFFSET_BITS ) ; let l1_offset = p_address & ( ( 1 << L1_CACHE_OFFSET_BITS ) - 1 ) ; let l1_way = match self . aquire_cache_line ( p_address ) { Ok ( l1_way ) => l1_way , Err ( trap ) => return Err ( trap ) , } ; // Update cache line self . l1_cache . data [ l1_index as usize ] . data [ l1_way as usize ] . set ( l1_offset , width , value ) ; Ok ( ( ) ) } Err ( ( ) ) => Err ( Trap { trap_type : TrapType :: StorePageFault , value : v_address , } ) , } , false => { for i in 0 .. width { match self . store ( v_address . wrapping_add ( i ) , ( ( value >> ( i * 8 ) ) & 0xff ) as u8 ) { Ok ( ( ) ) => { } Err ( e ) => return Err ( e ) , } } Ok ( ( ) ) } } }
Stores multiple bytes.
Stores multiple bytes .
&mut self
v_address
u64
value
u64
width
u64