pub fn init(&mut self)
	{
		let self_inten = self.inten.load(Ordering::Relaxed);
		let self_lnctl = self.lnctl.load(Ordering::Relaxed);
		let self_data = self.data.load(Ordering::Relaxed);
		let self_fifoctl = self.fifoctl.load(Ordering::Relaxed);
		let self_modemctl = self.modemctl.load(Ordering::Relaxed);
		unsafe
		{
			// Disable interrupts:
			self_inten.write(0x00);
			// Enable DLAB:
			self_lnctl.write(0x80);
			// Configure DLL/DLM to set maximum speed to 38400 b/s:
			self_data.write(0x03);
			self_inten.write(0x00);
			// Disable DLAB, set data word-length to 8 bits:
			self_lnctl.write(0x03);
			// Enable FIFO, clear TX/RX queues, set interrupt watermark to 14 bytes:
			self_fifoctl.write(0xC7);
			// Declare data as being ready for the terminal, request permission to send, enable aux. output number 2 as CPU interrupt line:
			self_modemctl.write(0x0B);
			// Enable interrupts:
			self_inten.write(0x01);
		}
	}
// Initialize memory-mapped UART interface
Initialize memory-mapped UART interface
Initialize memory - mapped UART interface
pub fn init(&mut self)
	{
		let self_inten = self.inten.load(Ordering::Relaxed);
		let self_lnctl = self.lnctl.load(Ordering::Relaxed);
		let self_data = self.data.load(Ordering::Relaxed);
		let self_fifoctl = self.fifoctl.load(Ordering::Relaxed);
		let self_modemctl = self.modemctl.load(Ordering::Relaxed);
		unsafe
		{
			// Disable interrupts:
			self_inten.write(0x00);
			// Enable DLAB:
			self_lnctl.write(0x80);
			// Configure DLL/DLM to set maximum speed to 38400 b/s:
			self_data.write(0x03);
			self_inten.write(0x00);
			// Disable DLAB, set data word-length to 8 bits:
			self_lnctl.write(0x03);
			// Enable FIFO, clear TX/RX queues, set interrupt watermark to 14 bytes:
			self_fifoctl.write(0xC7);
			// Declare data as being ready for the terminal, request permission to send, enable aux. output number 2 as CPU interrupt line:
			self_modemctl.write(0x0B);
			// Enable interrupts:
			self_inten.write(0x01);
		}
	}
pub fn init ( & mut self ) { let self_inten = self . inten . load ( Ordering :: Relaxed ) ; let self_lnctl = self . lnctl . load ( Ordering :: Relaxed ) ; let self_data = self . data . load ( Ordering :: Relaxed ) ; let self_fifoctl = self . fifoctl . load ( Ordering :: Relaxed ) ; let self_modemctl = self . modemctl . load ( Ordering :: Relaxed ) ; unsafe { // Disable interrupts: self_inten . write ( 0x00 ) ; // Enable DLAB: self_lnctl . write ( 0x80 ) ; // Configure DLL/DLM to set maximum speed to 38400 b/s: self_data . write ( 0x03 ) ; self_inten . write ( 0x00 ) ; // Disable DLAB, set data word-length to 8 bits: self_lnctl . write ( 0x03 ) ; // Enable FIFO, clear TX/RX queues, set interrupt watermark to 14 bytes: self_fifoctl . write ( 0xC7 ) ; // Declare data as being ready for the terminal, request permission to send, enable aux. output number 2 as CPU interrupt line: self_modemctl . write ( 0x0B ) ; // Enable interrupts: self_inten . write ( 0x01 ) ; } }
Initialize memory-mapped UART interface
Initialize memory - mapped UART interface
&mut self