fn handle_write(&mut self, offset: u8, value: u8) -> io::Result<()> {
        match offset as u8 {
            DLAB_LOW if self.is_dlab_set() => {
                self.baud_divisor = (self.baud_divisor & 0xff00) | u16::from(value)
            }
            DLAB_HIGH if self.is_dlab_set() => {
                self.baud_divisor = (self.baud_divisor & 0x00ff) | (u16::from(value) << 8)
            }
            DATA => {
                if self.is_loop() {
                    if self.in_buffer.len() < LOOP_SIZE {
                        self.in_buffer.push_back(value);
                        self.recv_data()?;
                    }
                } else {
                    if let Some(out) = self.out.as_mut() {
                        out.write_all(&[value])?;
                        out.flush()?;
                    }
                    self.thr_empty()?;
                }
            }
            IER => self.interrupt_enable = value & IER_FIFO_BITS,
            LCR => self.line_control = value,
            MCR => self.modem_control = value,
            SCR => self.scratch = value,
            _ => {}
        }
        Ok(())
    }
// Handles a write request from the driver.
Handles a write request from the driver.
Handles a write request from the driver .
fn handle_write(&mut self, offset: u8, value: u8) -> io::Result<()> {
        match offset as u8 {
            DLAB_LOW if self.is_dlab_set() => {
                self.baud_divisor = (self.baud_divisor & 0xff00) | u16::from(value)
            }
            DLAB_HIGH if self.is_dlab_set() => {
                self.baud_divisor = (self.baud_divisor & 0x00ff) | (u16::from(value) << 8)
            }
            DATA => {
                if self.is_loop() {
                    if self.in_buffer.len() < LOOP_SIZE {
                        self.in_buffer.push_back(value);
                        self.recv_data()?;
                    }
                } else {
                    if let Some(out) = self.out.as_mut() {
                        out.write_all(&[value])?;
                        out.flush()?;
                    }
                    self.thr_empty()?;
                }
            }
            IER => self.interrupt_enable = value & IER_FIFO_BITS,
            LCR => self.line_control = value,
            MCR => self.modem_control = value,
            SCR => self.scratch = value,
            _ => {}
        }
        Ok(())
    }
fn handle_write ( & mut self , offset : u8 , value : u8 ) -> io :: Result < ( ) > { match offset as u8 { DLAB_LOW if self . is_dlab_set ( ) => { self . baud_divisor = ( self . baud_divisor & 0xff00 ) | u16 :: from ( value ) } DLAB_HIGH if self . is_dlab_set ( ) => { self . baud_divisor = ( self . baud_divisor & 0x00ff ) | ( u16 :: from ( value ) << 8 ) } DATA => { if self . is_loop ( ) { if self . in_buffer . len ( ) < LOOP_SIZE { self . in_buffer . push_back ( value ) ; self . recv_data ( ) ? ; } } else { if let Some ( out ) = self . out . as_mut ( ) { out . write_all ( & [ value ] ) ? ; out . flush ( ) ? ; } self . thr_empty ( ) ? ; } } IER => self . interrupt_enable = value & IER_FIFO_BITS , LCR => self . line_control = value , MCR => self . modem_control = value , SCR => self . scratch = value , _ => { } } Ok ( ( ) ) }
Handles a write request from the driver.
Handles a write request from the driver .
&mut self
offset
u8
value
u8