pub fn new(rng: pac::RNG, clk: Clk, rcc: &mut pac::RCC) -> Rng {
        rcc.ccipr.modify(|_, w| w.rngsel().variant(clk));
        Self::enable_clock(rcc);
        rcc.ahb3rstr.modify(|_, w| w.rngrst().set_bit());
        rcc.ahb3rstr.modify(|_, w| w.rngrst().clear_bit());

        // RNG configuration A
        // see table 131 "RNG configurations" in the reference manual
        rng.cr.write(|w| {
            w.condrst().set_bit();
            w.nistc().set_bit();
            w.rng_config1().config_a();
            w.clkdiv().bits(0x0);
            w.rng_config2().config_a_b();
            w.rng_config3().config_a();
            w.ced().enabled();
            w.ie().disabled(); // interrupt enable
            w.rngen().set_bit()
        });

        rng.cr.write(|w| {
            w.condrst().clear_bit();
            w.nistc().set_bit();
            w.rng_config1().config_a();
            w.clkdiv().bits(0x0);
            w.rng_config2().config_a_b();
            w.rng_config3().config_a();
            w.ced().clear_bit();
            w.ie().disabled(); // interrupt enable
            w.rngen().set_bit()
        });

        // when CONDRST is set to 0 by software its value goes to 0 when the
        // reset process is done.
        // It takes about 2 AHB clock cycles + 2 RNG clock cycles
        while rng.cr.read().condrst().bit_is_set() {}

        Rng { rng, err_cnt: 0 }
    }
/// Create a new `Rng` driver from a RNG peripheral.
///
/// This will select the clock source, enable clocks, and reset the RNG
/// peripheral.
///
/// This will **NOT** enable the selected clock source, when in doubt use
/// MSI because it is enabled with power-on-reset.
///
/// # Example
///
/// ```no_run
/// use stm32wlxx_hal::{
///     pac,
///     rng::{Clk, Rng},
/// };
///
/// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
///
/// let mut rng = Rng::new(dp.RNG, Clk::MSI, &mut dp.RCC);
/// ```
Create a new `Rng` driver from a RNG peripheral.
This will select the clock source, enable clocks, and reset the RNG
peripheral.

This will **NOT** enable the selected clock source, when in doubt use
MSI because it is enabled with power-on-reset.
Create a new ` Rng ` driver from a RNG peripheral . This will select the clock source enable clocks and reset the RNG peripheral . This will ** NOT ** enable the selected clock source when in doubt use MSI because it is enabled with power - on - reset .
pub fn new(rng: pac::RNG, clk: Clk, rcc: &mut pac::RCC) -> Rng {
        rcc.ccipr.modify(|_, w| w.rngsel().variant(clk));
        Self::enable_clock(rcc);
        rcc.ahb3rstr.modify(|_, w| w.rngrst().set_bit());
        rcc.ahb3rstr.modify(|_, w| w.rngrst().clear_bit());
        // RNG configuration A
        // see table 131 "RNG configurations" in the reference manual
        rng.cr.write(|w| {
            w.condrst().set_bit();
            w.nistc().set_bit();
            w.rng_config1().config_a();
            w.clkdiv().bits(0x0);
            w.rng_config2().config_a_b();
            w.rng_config3().config_a();
            w.ced().enabled();
            w.ie().disabled(); // interrupt enable
            w.rngen().set_bit()
        });
        rng.cr.write(|w| {
            w.condrst().clear_bit();
            w.nistc().set_bit();
            w.rng_config1().config_a();
            w.clkdiv().bits(0x0);
            w.rng_config2().config_a_b();
            w.rng_config3().config_a();
            w.ced().clear_bit();
            w.ie().disabled(); // interrupt enable
            w.rngen().set_bit()
        });
        // when CONDRST is set to 0 by software its value goes to 0 when the
        // reset process is done.
        // It takes about 2 AHB clock cycles + 2 RNG clock cycles
        while rng.cr.read().condrst().bit_is_set() {}
        Rng { rng, err_cnt: 0 }
    }
pub fn new ( rng : pac :: RNG , clk : Clk , rcc : & mut pac :: RCC ) -> Rng { rcc . ccipr . modify ( | _ , w | w . rngsel ( ) . variant ( clk ) ) ; Self :: enable_clock ( rcc ) ; rcc . ahb3rstr . modify ( | _ , w | w . rngrst ( ) . set_bit ( ) ) ; rcc . ahb3rstr . modify ( | _ , w | w . rngrst ( ) . clear_bit ( ) ) ; // RNG configuration A // see table 131 "RNG configurations" in the reference manual rng . cr . write ( | w | { w . condrst ( ) . set_bit ( ) ; w . nistc ( ) . set_bit ( ) ; w . rng_config1 ( ) . config_a ( ) ; w . clkdiv ( ) . bits ( 0x0 ) ; w . rng_config2 ( ) . config_a_b ( ) ; w . rng_config3 ( ) . config_a ( ) ; w . ced ( ) . enabled ( ) ; w . ie ( ) . disabled ( ) ; // interrupt enable w . rngen ( ) . set_bit ( ) } ) ; rng . cr . write ( | w | { w . condrst ( ) . clear_bit ( ) ; w . nistc ( ) . set_bit ( ) ; w . rng_config1 ( ) . config_a ( ) ; w . clkdiv ( ) . bits ( 0x0 ) ; w . rng_config2 ( ) . config_a_b ( ) ; w . rng_config3 ( ) . config_a ( ) ; w . ced ( ) . clear_bit ( ) ; w . ie ( ) . disabled ( ) ; // interrupt enable w . rngen ( ) . set_bit ( ) } ) ; // when CONDRST is set to 0 by software its value goes to 0 when the // reset process is done. // It takes about 2 AHB clock cycles + 2 RNG clock cycles while rng . cr . read ( ) . condrst ( ) . bit_is_set ( ) { } Rng { rng , err_cnt : 0 } }
Create a new `Rng` driver from a RNG peripheral.
Create a new ` Rng ` driver from a RNG peripheral .
rng
pac::RNG
clk
Clk
rcc
&mut pac::RCC
example


let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap().

let mut rng = Rng::new(dp.RNG, Clk::MSI, &mut dp.RCC);
```
let mut dp : pac :: Peripherals = pac :: Peripherals :: take () . unwrap () . let mut rng = Rng :: new ( dp . RNG Clk :: MSI &mut dp . RCC ) ; ` ` `