fn gen_assigns<'a>(
    node: &Node,
    port: String,
    edges: Vec<(EdgeData, &Node)>,
) -> D<'a> {
    let unguarded_drivers = edges
        .iter()
        .filter(|(ed, _)| {
            ed.guard.is_none() || ed.guard.as_ref().unwrap().provably_true()
        })
        .count();

    // Error if there is more than one unguarded driver.
    if unguarded_drivers > 1 {
        panic!(
            "Multiple unguarded drivers for {}.{}",
            node.name.to_string(),
            port
        );
    }

    // Error if there is an unguarded driver along with other guarded drivers.
    if unguarded_drivers == 1 && edges.len() > 1 {
        panic!(
            "{}.{} driven by both unguarded and guarded drivers",
            node.name.to_string(),
            port
        );
    }

    if unguarded_drivers == 1 {
        let (el, src_node) = &edges[0];
        let dest = wire_id_from_node(node, port);
        dest.append(" = ")
            .append(wire_id_from_node(src_node, el.src.port_name().to_string()))
            .append(";")
    } else {
        let pre = wire_id_from_node(&node, port).append(" = ");
        let default = D::line()
            .nest(2)
            .append(pre.clone().append("'0").append(";"))
            .append(D::line());
        edges
            .iter()
            // Sort by the destination port names. This is required for
            // deterministic outputs.
            .sorted_by(|e1, e2| Ord::cmp(&e1.0.src, &e2.0.src))
            .fold(default, |acc, (el, node)| {
                let cond = D::text("if ").keyword_color().append(
                    el.guard
                        .as_ref()
                        .map(|g| guard(&g, ParenCtx::Not).parens())
                        .unwrap_or_else(D::nil),
                );
                let assign = pre
                    .clone()
                    .append(wire_id_from_node(
                        &node,
                        el.src.port_name().to_string(),
                    ))
                    .append(";");
                cond.append(D::line().nest(2).append(assign))
                    .append(D::line())
                    .append(D::text("else ").keyword_color())
                    .append(acc)
            })
    }
}
/// Generate a sequence of ternary assignments into the (node, port) using
/// edges. Generated code looks like:
/// node.port = g1 ? n1.p1 : g2 ? n2.p2 ...
Generate a sequence of ternary assignments into the (node, port) using
edges. Generated code looks like:
node.port = g1 .
Generate a sequence of ternary assignments into the ( node port ) using edges . Generated code looks like : node . port = g1 .
fn gen_assigns<'a>(
    node: &Node,
    port: String,
    edges: Vec<(EdgeData, &Node)>,
) -> D<'a> {
    let unguarded_drivers = edges
        .iter()
        .filter(|(ed, _)| {
            ed.guard.is_none() || ed.guard.as_ref().unwrap().provably_true()
        })
        .count();
    // Error if there is more than one unguarded driver.
    if unguarded_drivers > 1 {
        panic!(
            "Multiple unguarded drivers for {}.{}",
            node.name.to_string(),
            port
        );
    }
    // Error if there is an unguarded driver along with other guarded drivers.
    if unguarded_drivers == 1 && edges.len() > 1 {
        panic!(
            "{}.{} driven by both unguarded and guarded drivers",
            node.name.to_string(),
            port
        );
    }
    if unguarded_drivers == 1 {
        let (el, src_node) = &edges[0];
        let dest = wire_id_from_node(node, port);
        dest.append(" = ")
            .append(wire_id_from_node(src_node, el.src.port_name().to_string()))
            .append(";")
    } else {
        let pre = wire_id_from_node(&node, port).append(" = ");
        let default = D::line()
            .nest(2)
            .append(pre.clone().append("'0").append(";"))
            .append(D::line());
        edges
            .iter()
            // Sort by the destination port names. This is required for
            // deterministic outputs.
            .sorted_by(|e1, e2| Ord::cmp(&e1.0.src, &e2.0.src))
            .fold(default, |acc, (el, node)| {
                let cond = D::text("if ").keyword_color().append(
                    el.guard
                        .as_ref()
                        .map(|g| guard(&g, ParenCtx::Not).parens())
                        .unwrap_or_else(D::nil),
                );
                let assign = pre
                    .clone()
                    .append(wire_id_from_node(
                        &node,
                        el.src.port_name().to_string(),
                    ))
                    .append(";");
                cond.append(D::line().nest(2).append(assign))
                    .append(D::line())
                    .append(D::text("else ").keyword_color())
                    .append(acc)
            })
    }
}
fn gen_assigns < ' a > ( node : & Node , port : String , edges : Vec < ( EdgeData , & Node ) > , ) -> D < ' a > { let unguarded_drivers = edges . iter ( ) . filter ( | ( ed , _ ) | { ed . guard . is_none ( ) || ed . guard . as_ref ( ) . unwrap ( ) . provably_true ( ) } ) . count ( ) ; // Error if there is more than one unguarded driver. if unguarded_drivers > 1 { panic ! ( " " node name to_string ( ) port ) ; } // Error if there is an unguarded driver along with other guarded drivers. if unguarded_drivers == 1 && edges . len ( ) > 1 { panic ! ( " " node name to_string ( ) port ) ; } if unguarded_drivers == 1 { let ( el , src_node ) = & edges [ 0 ] ; let dest = wire_id_from_node ( node , port ) ; dest . append ( " " ) . append ( wire_id_from_node ( src_node , el . src . port_name ( ) . to_string ( ) ) ) . append ( " " ) } else { let pre = wire_id_from_node ( & node , port ) . append ( " " ) ; let default = D :: line ( ) . nest ( 2 ) . append ( pre . clone ( ) . append ( " " ) . append ( " " ) ) . append ( D :: line ( ) ) ; edges . iter ( ) // Sort by the destination port names. This is required for // deterministic outputs. . sorted_by ( | e1 , e2 | Ord :: cmp ( & e1 . 0 . src , & e2 . 0 . src ) ) . fold ( default , | acc , ( el , node ) | { let cond = D :: text ( " " ) . keyword_color ( ) . append ( el . guard . as_ref ( ) . map ( | g | guard ( & g , ParenCtx :: Not ) . parens ( ) ) . unwrap_or_else ( D :: nil ) , ) ; let assign = pre . clone ( ) . append ( wire_id_from_node ( & node , el . src . port_name ( ) . to_string ( ) , ) ) . append ( " " ) ; cond . append ( D :: line ( ) . nest ( 2 ) . append ( assign ) ) . append ( D :: line ( ) ) . append ( D :: text ( " " ) . keyword_color ( ) ) . append ( acc ) } ) } }
Generate a sequence of ternary assignments into the (node, port) using
edges.
Generate a sequence of ternary assignments into the ( node port ) using edges .
node
&Node
port
String
edges
Vec<(EdgeData, &Node)>