fn div(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_r(word);
    cpu.x[o.rd as usize] = match cpu.x[o.rs2 as usize] {
        0 => -1,
        _ => signed(
            cpu,
            cpu.x[o.rs1 as usize].wrapping_div(cpu.x[o.rs2 as usize]),
        ),
    };
    Ok(())
}
/// [div rd,rs1,rs2]
/// DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer
/// division of rs1 by rs2, rounding towards zero.
[div rd,rs1,rs2]
DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer
division of rs1 by rs2, rounding towards zero.
[ div rd rs1 rs2 ] DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2 rounding towards zero .
fn div(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_r(word);
    cpu.x[o.rd as usize] = match cpu.x[o.rs2 as usize] {
        0 => -1,
        _ => signed(
            cpu,
            cpu.x[o.rs1 as usize].wrapping_div(cpu.x[o.rs2 as usize]),
        ),
    };
    Ok(())
}
fn div ( cpu : & mut Cpu , _addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_r ( word ) ; cpu . x [ o . rd as usize ] = match cpu . x [ o . rs2 as usize ] { 0 => - 1 , _ => signed ( cpu , cpu . x [ o . rs1 as usize ] . wrapping_div ( cpu . x [ o . rs2 as usize ] ) , ) , } ; Ok ( ( ) ) }
[div rd,rs1,rs2]
DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer
division of rs1 by rs2, rounding towards zero.
[ div rd rs1 rs2 ] DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2 rounding towards zero .
cpu
&mut Cpu
_addr
u64
word
u32