fn csrrw(cpu: &mut Cpu, addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_csr(word);
    let t = match cpu.csr.read(o.csr, addr, &cpu.privilege) {
        Ok(data) => data as i64,
        Err(e) => return Err(e),
    };
    let data = unsigned(cpu, cpu.x[o.rs1 as usize]);
    match cpu.csr.write(o.csr, data, addr, &cpu.privilege) {
        Ok(need_update_mmu_addressing_mode) => {
            if need_update_mmu_addressing_mode {
                cpu.mmu.update_addressing_mode(data);
            }
            cpu.x[o.rd as usize] = signed(cpu, t);
            Ok(())
        }
        Err(e) => Err(e),
    }
}
//==============================================================================
// Control and Status Register (CSR) Instructions.
//==============================================================================
/// [csrrw rd,offset,rs1]
/// The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the
/// CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends
/// the value to XLEN bits, then writes it to integer register rd. The initial
/// value in rs1 is written to the CSR. If rd=x0, then the instruction shall not
/// read the CSR and shall not cause any of the side effects that might occur on a CSR read.
Control and Status Register (CSR) Instructions.
[csrrw rd,offset,rs1]
The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the
CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends
the value to XLEN bits, then writes it to integer register rd. The initial
value in rs1 is written to the CSR. If rd=x0, then the instruction shall not
read the CSR and shall not cause any of the side effects that might occur on a CSR read.
Control and Status Register ( CSR ) Instructions . [ csrrw rd offset rs1 ] The CSRRW ( Atomic Read / Write CSR ) instruction atomically swaps values in the CSRs and integer registers . CSRRW reads the old value of the CSR zero - extends the value to XLEN bits then writes it to integer register rd . The initial value in rs1 is written to the CSR . If rd = x0 then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read .
fn csrrw(cpu: &mut Cpu, addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_csr(word);
    let t = match cpu.csr.read(o.csr, addr, &cpu.privilege) {
        Ok(data) => data as i64,
        Err(e) => return Err(e),
    };
    let data = unsigned(cpu, cpu.x[o.rs1 as usize]);
    match cpu.csr.write(o.csr, data, addr, &cpu.privilege) {
        Ok(need_update_mmu_addressing_mode) => {
            if need_update_mmu_addressing_mode {
                cpu.mmu.update_addressing_mode(data);
            }
            cpu.x[o.rd as usize] = signed(cpu, t);
            Ok(())
        }
        Err(e) => Err(e),
    }
}
fn csrrw ( cpu : & mut Cpu , addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_csr ( word ) ; let t = match cpu . csr . read ( o . csr , addr , & cpu . privilege ) { Ok ( data ) => data as i64 , Err ( e ) => return Err ( e ) , } ; let data = unsigned ( cpu , cpu . x [ o . rs1 as usize ] ) ; match cpu . csr . write ( o . csr , data , addr , & cpu . privilege ) { Ok ( need_update_mmu_addressing_mode ) => { if need_update_mmu_addressing_mode { cpu . mmu . update_addressing_mode ( data ) ; } cpu . x [ o . rd as usize ] = signed ( cpu , t ) ; Ok ( ( ) ) } Err ( e ) => Err ( e ) , } }
Control and Status Register (CSR) Instructions.
Control and Status Register ( CSR ) Instructions .
cpu
&mut Cpu
addr
u64
word
u32