fn l2_write_back(&mut self, victim_cache_line: L2CacheLine, index: u64) {
		let mut write_back_address = 0 as u64;
		// [ tag | index | 000000 ]
		write_back_address = write_back_address
			| (victim_cache_line.tag << (L2_CACHE_INDEX_BITS + L2_CACHE_OFFSET_BITS))
			| (index << L2_CACHE_OFFSET_BITS);

		// Reuse current memory interface
		// @TODO: optimize
		for i in 0..(L2_CACHE_BLOCK_SIZE / 8) as u64 {
			self.memory
				.write_doubleword(write_back_address + i * 8, victim_cache_line.get(i * 8, 8));
		}

		// Latency for checking
		self.clock = self.clock.wrapping_add(L2_CACHE_HIT_LATENCY as u64);

		// Trace memory access
		self.memory_access_trace.push(MemoryAccessTrace {
			address: write_back_address,
			operation: MemoryAccessType::Write,
			cycle: self.clock,
		});

		#[cfg(feature = "dramsim")]
		{
			// Communicate with dramsim through pipe
			// @TODO: Blocked
			send_request(
				format!("{:016x} {} {}", write_back_address, "WRITE", self.clock).as_str(),
			);
			#[cfg(feature = "debug-dramsim")]
			println!(
				"Send {:?}",
				format!("{:016x} {} {}", write_back_address, "WRITE", self.clock)
			);

			let response_string = get_response();
			#[cfg(feature = "debug-dramsim")]
			println!("Resp {:?}", response_string);

			// Latency for accessing memory
			let dram_clk = response_string
				.split(" ")
				.last()
				.unwrap()
				.parse::<u64>()
				.unwrap();
			if dram_clk <= self.clock {
				panic!("Reverse dram clk!!!");
			} else {
				self.dram_latency += dram_clk - self.clock;
				self.clock = dram_clk;
			}
		}
		#[cfg(not(feature = "dramsim"))]
		{
			self.clock = self.clock.wrapping_add(L2_CACHE_MISS_LATENCY as u64);
		}
	}
/// Write back method for L2 cache
///
/// # Arguments
/// * `victim_cache_line`: the line needs to be written back
/// * `index`: index of the line
Write back method for L2 cache
Write back method for L2 cache
fn l2_write_back(&mut self, victim_cache_line: L2CacheLine, index: u64) {
		let mut write_back_address = 0 as u64;
		// [ tag | index | 000000 ]
		write_back_address = write_back_address
			| (victim_cache_line.tag << (L2_CACHE_INDEX_BITS + L2_CACHE_OFFSET_BITS))
			| (index << L2_CACHE_OFFSET_BITS);
		// Reuse current memory interface
		// @TODO: optimize
		for i in 0..(L2_CACHE_BLOCK_SIZE / 8) as u64 {
			self.memory
				.write_doubleword(write_back_address + i * 8, victim_cache_line.get(i * 8, 8));
		}
		// Latency for checking
		self.clock = self.clock.wrapping_add(L2_CACHE_HIT_LATENCY as u64);
		// Trace memory access
		self.memory_access_trace.push(MemoryAccessTrace {
			address: write_back_address,
			operation: MemoryAccessType::Write,
			cycle: self.clock,
		});
		#[cfg(feature = "dramsim")]
		{
			// Communicate with dramsim through pipe
			// @TODO: Blocked
			send_request(
				format!("{:016x} {} {}", write_back_address, "WRITE", self.clock).as_str(),
			);
			#[cfg(feature = "debug-dramsim")]
			println!(
				"Send {:?}",
				format!("{:016x} {} {}", write_back_address, "WRITE", self.clock)
			);
			let response_string = get_response();
			#[cfg(feature = "debug-dramsim")]
			println!("Resp {:?}", response_string);
			// Latency for accessing memory
			let dram_clk = response_string
				.split(" ")
				.last()
				.unwrap()
				.parse::<u64>()
				.unwrap();
			if dram_clk <= self.clock {
				panic!("Reverse dram clk!!!");
			} else {
				self.dram_latency += dram_clk - self.clock;
				self.clock = dram_clk;
			}
		}
		#[cfg(not(feature = "dramsim"))]
		{
			self.clock = self.clock.wrapping_add(L2_CACHE_MISS_LATENCY as u64);
		}
	}
fn l2_write_back ( & mut self , victim_cache_line : L2CacheLine , index : u64 ) { let mut write_back_address = 0 as u64 ; // [ tag | index | 000000 ] write_back_address = write_back_address | ( victim_cache_line . tag << ( L2_CACHE_INDEX_BITS + L2_CACHE_OFFSET_BITS ) ) | ( index << L2_CACHE_OFFSET_BITS ) ; // Reuse current memory interface // @TODO: optimize for i in 0 .. ( L2_CACHE_BLOCK_SIZE / 8 ) as u64 { self . memory . write_doubleword ( write_back_address + i * 8 , victim_cache_line . get ( i * 8 , 8 ) ) ; } // Latency for checking self . clock = self . clock . wrapping_add ( L2_CACHE_HIT_LATENCY as u64 ) ; // Trace memory access self . memory_access_trace . push ( MemoryAccessTrace { address : write_back_address , operation : MemoryAccessType :: Write , cycle : self . clock , } ) ; # [ cfg ( feature " " ) ] { // Communicate with dramsim through pipe // @TODO: Blocked send_request ( format ! ( " " write_back_address " " self clock ) . as_str ( ) , ) ; # [ cfg ( feature " " ) ] println ! ( " " format ( " " write_back_address " " self clock ) ) ; let response_string = get_response ( ) ; # [ cfg ( feature " " ) ] println ! ( " " response_string ) ; // Latency for accessing memory let dram_clk = response_string . split ( " " ) . last ( ) . unwrap ( ) . parse :: < u64 > ( ) . unwrap ( ) ; if dram_clk <= self . clock { panic ! ( " " ) ; } else { self . dram_latency += dram_clk - self . clock ; self . clock = dram_clk ; } } # [ cfg ( not ( feature " " ) ) ] { self . clock = self . clock . wrapping_add ( L2_CACHE_MISS_LATENCY as u64 ) ; } }
Write back method for L2 cache
Write back method for L2 cache
&mut self
victim_cache_line
L2CacheLine
index
u64