fn flw(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_i(word);
    let data = match cpu
        .mmu
        .read32(cpu.x[o.rs1 as usize].wrapping_add(o.imm) as u64)
    {
        Ok(d) => f64::from_bits(d as i32 as i64 as u64),
        Err(e) => return Err(e),
    };
    cpu.f[o.rd as usize] = data;
    Ok(())
}
/// [flw rd,offset(rs1)]
/// The FLW instruction loads a single-precision floating-point value
/// from memory into floating-point register rd.
[flw rd,offset(rs1)]
The FLW instruction loads a single-precision floating-point value
from memory into floating-point register rd.
[ flw rd offset ( rs1 ) ] The FLW instruction loads a single - precision floating - point value from memory into floating - point register rd .
fn flw(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_i(word);
    let data = match cpu
        .mmu
        .read32(cpu.x[o.rs1 as usize].wrapping_add(o.imm) as u64)
    {
        Ok(d) => f64::from_bits(d as i32 as i64 as u64),
        Err(e) => return Err(e),
    };
    cpu.f[o.rd as usize] = data;
    Ok(())
}
fn flw ( cpu : & mut Cpu , _addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_i ( word ) ; let data = match cpu . mmu . read32 ( cpu . x [ o . rs1 as usize ] . wrapping_add ( o . imm ) as u64 ) { Ok ( d ) => f64 :: from_bits ( d as i32 as i64 as u64 ) , Err ( e ) => return Err ( e ) , } ; cpu . f [ o . rd as usize ] = data ; Ok ( ( ) ) }
[flw rd,offset(rs1)]
The FLW instruction loads a single-precision floating-point value
from memory into floating-point register rd.
[ flw rd offset ( rs1 ) ] The FLW instruction loads a single - precision floating - point value from memory into floating - point register rd .
cpu
&mut Cpu
_addr
u64
word
u32