fn sll(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_r(word);
    let shamt = match cpu.xlen {
        Xlen::X64 => cpu.x[o.rs2 as usize] & 0x3f,
        Xlen::X32 => cpu.x[o.rs2 as usize] & 0x1f,
    };
    cpu.x[o.rd as usize] = signed(cpu, cpu.x[o.rs1 as usize] << shamt);
    Ok(())
}
/// [sll rd,rs1,rs2]
/// SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in
/// register rs1 by the shift amount held in the lower 5 bits of register rs2.
[sll rd,rs1,rs2]
SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in
register rs1 by the shift amount held in the lower 5 bits of register rs2.
[ sll rd rs1 rs2 ] SLL SRL and SRA perform logical left logical right and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2 .
fn sll(cpu: &mut Cpu, _addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_r(word);
    let shamt = match cpu.xlen {
        Xlen::X64 => cpu.x[o.rs2 as usize] & 0x3f,
        Xlen::X32 => cpu.x[o.rs2 as usize] & 0x1f,
    };
    cpu.x[o.rd as usize] = signed(cpu, cpu.x[o.rs1 as usize] << shamt);
    Ok(())
}
fn sll ( cpu : & mut Cpu , _addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_r ( word ) ; let shamt = match cpu . xlen { Xlen :: X64 => cpu . x [ o . rs2 as usize ] & 0x3f , Xlen :: X32 => cpu . x [ o . rs2 as usize ] & 0x1f , } ; cpu . x [ o . rd as usize ] = signed ( cpu , cpu . x [ o . rs1 as usize ] << shamt ) ; Ok ( ( ) ) }
[sll rd,rs1,rs2]
SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in
register rs1 by the shift amount held in the lower 5 bits of register rs2.
[ sll rd rs1 rs2 ] SLL SRL and SRA perform logical left logical right and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2 .
cpu
&mut Cpu
_addr
u64
word
u32