fn jal(cpu: &mut Cpu, addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_j(word);
    cpu.x[o.rd as usize] = signed(cpu, cpu.pc as i64);
    cpu.pc = addr.wrapping_add(o.imm);
    Ok(())
}
//==============================================================================
// Control Transfer Instructions
//==============================================================================
/// [jal rd,offset]
/// JAL stores the address of the instruction following the jump (pc+4) into register rd.
/// The standard software calling convention uses x1 as the return address register and
/// x5 as an alternate link register.
Control Transfer Instructions
[jal rd,offset]
JAL stores the address of the instruction following the jump (pc+4) into register rd.
The standard software calling convention uses x1 as the return address register and
x5 as an alternate link register.
Control Transfer Instructions [ jal rd offset ] JAL stores the address of the instruction following the jump ( pc + 4 ) into register rd . The standard software calling convention uses x1 as the return address register and x5 as an alternate link register .
fn jal(cpu: &mut Cpu, addr: u64, word: u32) -> Result<(), Trap> {
    let o = parse_type_j(word);
    cpu.x[o.rd as usize] = signed(cpu, cpu.pc as i64);
    cpu.pc = addr.wrapping_add(o.imm);
    Ok(())
}
fn jal ( cpu : & mut Cpu , addr : u64 , word : u32 ) -> Result < ( ) , Trap > { let o = parse_type_j ( word ) ; cpu . x [ o . rd as usize ] = signed ( cpu , cpu . pc as i64 ) ; cpu . pc = addr . wrapping_add ( o . imm ) ; Ok ( ( ) ) }
Control Transfer Instructions
[jal rd,offset]
JAL stores the address of the instruction following the jump (pc+4) into register rd.
Control Transfer Instructions [ jal rd offset ] JAL stores the address of the instruction following the jump ( pc + 4 ) into register rd .
cpu
&mut Cpu
addr
u64
word
u32