fn emit_std_enc_enc(
    sink: &mut MachBuffer<Inst>,
    prefixes: LegacyPrefixes,
    opcodes: u32,
    mut num_opcodes: usize,
    enc_g: u8,
    enc_e: u8,
    rex: RexFlags,
) {
    // EncG and EncE can be derived from registers of any class, and they
    // don't even have to be from the same class.  For example, for an
    // integer-to-FP conversion insn, one might be RegClass::I64 and the other
    // RegClass::V128.

    // The legacy prefixes.
    prefixes.emit(sink);

    // The rex byte.
    rex.emit_two_op(sink, enc_g, enc_e);

    // All other prefixes and opcodes.
    while num_opcodes > 0 {
        num_opcodes -= 1;
        sink.put1(((opcodes >> (num_opcodes << 3)) & 0xFF) as u8);
    }

    // Now the mod/rm byte.  The instruction we're generating doesn't access
    // memory, so there is no SIB byte or immediate -- we're done.
    sink.put1(encode_modrm(3, enc_g & 7, enc_e & 7));
}
/// This is the core 'emit' function for instructions that do not reference memory.
///
/// This is conceptually the same as emit_modrm_sib_enc_ge, except it is for the case where the E
/// operand is a register rather than memory.  Hence it is much simpler.
This is the core 'emit' function for instructions that do not reference memory.
This is conceptually the same as emit_modrm_sib_enc_ge, except it is for the case where the E
operand is a register rather than memory.  Hence it is much simpler.
This is the core ' emit ' function for instructions that do not reference memory . This is conceptually the same as emit_modrm_sib_enc_ge except it is for the case where the E operand is a register rather than memory . Hence it is much simpler .
fn emit_std_enc_enc(
    sink: &mut MachBuffer<Inst>,
    prefixes: LegacyPrefixes,
    opcodes: u32,
    mut num_opcodes: usize,
    enc_g: u8,
    enc_e: u8,
    rex: RexFlags,
) {
    // EncG and EncE can be derived from registers of any class, and they
    // don't even have to be from the same class.  For example, for an
    // integer-to-FP conversion insn, one might be RegClass::I64 and the other
    // RegClass::V128.
    // The legacy prefixes.
    prefixes.emit(sink);
    // The rex byte.
    rex.emit_two_op(sink, enc_g, enc_e);
    // All other prefixes and opcodes.
    while num_opcodes > 0 {
        num_opcodes -= 1;
        sink.put1(((opcodes >> (num_opcodes << 3)) & 0xFF) as u8);
    }
    // Now the mod/rm byte.  The instruction we're generating doesn't access
    // memory, so there is no SIB byte or immediate -- we're done.
    sink.put1(encode_modrm(3, enc_g & 7, enc_e & 7));
}
fn emit_std_enc_enc ( sink : & mut MachBuffer < Inst > , prefixes : LegacyPrefixes , opcodes : u32 , mut num_opcodes : usize , enc_g : u8 , enc_e : u8 , rex : RexFlags , ) { // EncG and EncE can be derived from registers of any class, and they // don't even have to be from the same class.  For example, for an // integer-to-FP conversion insn, one might be RegClass::I64 and the other // RegClass::V128. // The legacy prefixes. prefixes . emit ( sink ) ; // The rex byte. rex . emit_two_op ( sink , enc_g , enc_e ) ; // All other prefixes and opcodes. while num_opcodes > 0 { num_opcodes -= 1 ; sink . put1 ( ( ( opcodes >> ( num_opcodes << 3 ) ) & 0xFF ) as u8 ) ; } // Now the mod/rm byte.  The instruction we're generating doesn't access // memory, so there is no SIB byte or immediate -- we're done. sink . put1 ( encode_modrm ( 3 , enc_g & 7 , enc_e & 7 ) ) ; }
This is the core 'emit' function for instructions that do not reference memory.
This is the core ' emit ' function for instructions that do not reference memory .
sink
&mut MachBuffer<Inst>
prefixes
LegacyPrefixes
opcodes
u32
num_opcodes
usize
enc_g
u8
enc_e
u8
rex
RexFlags
sink
&mut MachBuffer<Inst>
prefixes
LegacyPrefixes
opcodes
u32
num_opcodes
usize
enc_g
u8
enc_e
u8
rex
RexFlags