pub fn vir_type_for_type_id(&self, typeid: TypeId) -> VIRType {
        let clif_name = match &self.typeenv.types[typeid.index()] {
            &isle::sema::Type::Primitive(_, sym, _) | &isle::sema::Type::Enum { name: sym, .. } => {
                self.typeenv.syms[sym.index()].clone()
            }
        };
        match clif_name.as_str() {
            "Type" => VIRType::Int,
            "Imm12" => VIRType::BitVector(12),
            "Imm64" => VIRType::BitVector(64),
            "ImmShift" => VIRType::BitVector(6),
            "ImmLogic" => VIRType::BitVector(12),
            "u64" => VIRType::BitVector(64),
            "u8" => VIRType::BitVector(8),
            "MoveWideConst" => VIRType::BitVector(16),
            "OperandSize" => self.ty.clone(),
            // TODO: should probably update this logic to use an actual
            // register width for some of these
            "Reg" | "Inst" | "Value" | "ValueRegs" | "InstructionData" => self.ty.clone(),

            // For now, hard code errors for these types that we later want to
            // explicitly mark as unsafe.
            "Opcode" => unreachable!(),
            "ALUOp" => unreachable!(),
            "ValueArray2" => unreachable!(),
            _ => unimplemented!("ty: {}", clif_name),
        }
    }
/// An approximation for now: types from CLIF type names
An approximation for now: types from CLIF type names
An approximation for now : types from CLIF type names
pub fn vir_type_for_type_id(&self, typeid: TypeId) -> VIRType {
        let clif_name = match &self.typeenv.types[typeid.index()] {
            &isle::sema::Type::Primitive(_, sym, _) | &isle::sema::Type::Enum { name: sym, .. } => {
                self.typeenv.syms[sym.index()].clone()
            }
        };
        match clif_name.as_str() {
            "Type" => VIRType::Int,
            "Imm12" => VIRType::BitVector(12),
            "Imm64" => VIRType::BitVector(64),
            "ImmShift" => VIRType::BitVector(6),
            "ImmLogic" => VIRType::BitVector(12),
            "u64" => VIRType::BitVector(64),
            "u8" => VIRType::BitVector(8),
            "MoveWideConst" => VIRType::BitVector(16),
            "OperandSize" => self.ty.clone(),
            // TODO: should probably update this logic to use an actual
            // register width for some of these
            "Reg" | "Inst" | "Value" | "ValueRegs" | "InstructionData" => self.ty.clone(),
            // For now, hard code errors for these types that we later want to
            // explicitly mark as unsafe.
            "Opcode" => unreachable!(),
            "ALUOp" => unreachable!(),
            "ValueArray2" => unreachable!(),
            _ => unimplemented!("ty: {}", clif_name),
        }
    }
pub fn vir_type_for_type_id ( & self , typeid : TypeId ) -> VIRType { let clif_name = match & self . typeenv . types [ typeid . index ( ) ] { & isle :: sema :: Type :: Primitive ( _ , sym , _ ) | & isle :: sema :: Type :: Enum { name : sym , .. } => { self . typeenv . syms [ sym . index ( ) ] . clone ( ) } } ; match clif_name . as_str ( ) { " " => VIRType :: Int , " " => VIRType :: BitVector ( 12 ) , " " => VIRType :: BitVector ( 64 ) , " " => VIRType :: BitVector ( 6 ) , " " => VIRType :: BitVector ( 12 ) , " " => VIRType :: BitVector ( 64 ) , " " => VIRType :: BitVector ( 8 ) , " " => VIRType :: BitVector ( 16 ) , " " => self . ty . clone ( ) , // TODO: should probably update this logic to use an actual // register width for some of these " " | " " | " " | " " | " " => self . ty . clone ( ) , // For now, hard code errors for these types that we later want to // explicitly mark as unsafe. " " => unreachable ! ( ) , " " => unreachable ! ( ) , " " => unreachable ! ( ) , _ => unimplemented ! ( " " clif_name ) , } }
An approximation for now: types from CLIF type names
An approximation for now : types from CLIF type names
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