fn _disable(&self) {
        if self._active() {
            self._detach();
        }

        self.state.map(|state| {
            if *state != State::Reset {
                unsafe {
                    USBCON_USBE.write(false);

                    disable_clock(Clock::PBB(PBBClock::USBC));
                    disable_clock(Clock::HSB(HSBClock::USBC));
                }
                *state = State::Reset;
            }
        });
    }
/// Disable the controller, its interrupt, and its clocks
Disable the controller, its interrupt, and its clocks
Disable the controller its interrupt and its clocks
fn _disable(&self) {
        if self._active() {
            self._detach();
        }
        self.state.map(|state| {
            if *state != State::Reset {
                unsafe {
                    USBCON_USBE.write(false);
                    disable_clock(Clock::PBB(PBBClock::USBC));
                    disable_clock(Clock::HSB(HSBClock::USBC));
                }
                *state = State::Reset;
            }
        });
    }
fn _disable ( & self ) { if self . _active ( ) { self . _detach ( ) ; } self . state . map ( | state | { if * state != State :: Reset { unsafe { USBCON_USBE . write ( false ) ; disable_clock ( Clock :: PBB ( PBBClock :: USBC ) ) ; disable_clock ( Clock :: HSB ( HSBClock :: USBC ) ) ; } * state = State :: Reset ; } } ) ; }
Disable the controller, its interrupt, and its clocks
Disable the controller its interrupt and its clocks
&self
&self