pub fn dummy_cycles(mut self, cycles: u8) -> Self {
            debug_assert!(
                cycles < 32,
                "Hardware only supports 0-31 dummy cycles"
            );

            self.dummy_cycles = cycles;
            self
        }
/// Specify the number of dummy cycles in between the address and data
/// phases.
///
/// Hardware supports 0-31 dummy cycles.
///
/// # Note
///
/// With zero dummy cycles, the QUADSPI peripheral will erroneously drive the
/// output pins for an extra half clock cycle before IO is swapped from
/// output to input. Refer to
/// <https://github.com/quartiq/stabilizer/issues/101> for more information.
Specify the number of dummy cycles in between the address and data
phases.

Hardware supports 0-31 dummy cycles.
Specify the number of dummy cycles in between the address and data phases . Hardware supports 0 - 31 dummy cycles .
pub fn dummy_cycles(mut self, cycles: u8) -> Self {
            debug_assert!(
                cycles < 32,
                "Hardware only supports 0-31 dummy cycles"
            );
            self.dummy_cycles = cycles;
            self
        }
pub fn dummy_cycles ( mut self , cycles : u8 ) -> Self { debug_assert ! ( cycles 32 " " ) ; self . dummy_cycles = cycles ; self }
Specify the number of dummy cycles in between the address and data
phases.
Specify the number of dummy cycles in between the address and data phases .
mut self
cycles
u8
mut self
cycles
u8
note
With zero dummy cycles, the QUADSPI peripheral will erroneously drive the
output pins for an extra half clock cycle before IO is swapped from
output to input. Refer to
for more information.
With zero dummy cycles the QUADSPI peripheral will erroneously drive the output pins for an extra half clock cycle before IO is swapped from output to input . Refer to for more information .