pub fn handle_interrupt(&mut self) {
        if ISR.read() & 1 == 1 {
            // A CRC error has occurred
        }

        if DMAISR.read() & 1 == 1 {
            // A DMA transfer has completed

            if self.get_tcr().interrupt_enabled() {
                if let Some(client) = self.get_client() {
                    let result = post_process(SR.read(), self.alg.get());
                    client.receive_result(result);
                }

                // Disable the unit
                MR.write(Mode::disabled().0);

                // Reset CTRL.IEN (for our own statekeeping)
                self.set_descriptor(0, TCR::default(), 0);

                // Disable DMA interrupt
                DMAIDR.write(1);

                // Disable DMA channel
                DMADIS.write(1);
            }
        }
    }
/// Handle an interrupt from the CRCCU
Handle an interrupt from the CRCCU
Handle an interrupt from the CRCCU
pub fn handle_interrupt(&mut self) {
        if ISR.read() & 1 == 1 {
            // A CRC error has occurred
        }
        if DMAISR.read() & 1 == 1 {
            // A DMA transfer has completed
            if self.get_tcr().interrupt_enabled() {
                if let Some(client) = self.get_client() {
                    let result = post_process(SR.read(), self.alg.get());
                    client.receive_result(result);
                }
                // Disable the unit
                MR.write(Mode::disabled().0);
                // Reset CTRL.IEN (for our own statekeeping)
                self.set_descriptor(0, TCR::default(), 0);
                // Disable DMA interrupt
                DMAIDR.write(1);
                // Disable DMA channel
                DMADIS.write(1);
            }
        }
    }
pub fn handle_interrupt ( & mut self ) { if ISR . read ( ) & 1 == 1 { // A CRC error has occurred } if DMAISR . read ( ) & 1 == 1 { // A DMA transfer has completed if self . get_tcr ( ) . interrupt_enabled ( ) { if let Some ( client ) = self . get_client ( ) { let result = post_process ( SR . read ( ) , self . alg . get ( ) ) ; client . receive_result ( result ) ; } // Disable the unit MR . write ( Mode :: disabled ( ) . 0 ) ; // Reset CTRL.IEN (for our own statekeeping) self . set_descriptor ( 0 , TCR :: default ( ) , 0 ) ; // Disable DMA interrupt DMAIDR . write ( 1 ) ; // Disable DMA channel DMADIS . write ( 1 ) ; } } }
Handle an interrupt from the CRCCU
Handle an interrupt from the CRCCU
&mut self
&mut self