pub fn write_then_read(
        &mut self,
        address: u8,
        wr_buffer: &[u8],
        rd_buffer: &mut [u8],
    ) -> Result<(), Error> {
        // Conservative compiler fence to prevent optimizations that do not
        // take in to account actions by DMA. The fence has been placed here,
        // before any DMA action has started.
        compiler_fence(SeqCst);

        self.0
            .address
            .write(|w| unsafe { w.address().bits(address) });

        // Set up DMA buffers.
        unsafe {
            self.set_tx_buffer(wr_buffer)?;
            self.set_rx_buffer(rd_buffer)?;
        }

        // Clear events
        self.0.events_stopped.reset();
        self.0.events_error.reset();
        self.clear_errorsrc();

        // Start write+read operation.
        self.0.shorts.write(|w| {
            w.lasttx_startrx().enabled();
            w.lastrx_stop().enabled();
            w
        });
        // `1` is a valid value to write to task registers.
        self.0.tasks_starttx.write(|w| unsafe { w.bits(1) });

        self.wait();

        // Conservative compiler fence to prevent optimizations that do not
        // take in to account actions by DMA. The fence has been placed here,
        // after all possible DMA actions have completed.
        compiler_fence(SeqCst);

        self.read_errorsrc()?;

        let bad_write = self.0.txd.amount.read().bits() != wr_buffer.len() as u32;
        let bad_read = self.0.rxd.amount.read().bits() != rd_buffer.len() as u32;

        if bad_write {
            return Err(Error::Transmit);
        }

        if bad_read {
            return Err(Error::Receive);
        }

        Ok(())
    }
/// Write data to an I2C slave, then read data from the slave without
/// triggering a stop condition between the two.
///
/// The buffers must have a length of at most 255 bytes on the nRF52832
/// and at most 65535 bytes on the nRF52840.
Write data to an I2C slave, then read data from the slave without
triggering a stop condition between the two.

The buffers must have a length of at most 255 bytes on the nRF52832
and at most 65535 bytes on the nRF52840.
Write data to an I2C slave then read data from the slave without triggering a stop condition between the two . The buffers must have a length of at most 255 bytes on the nRF52832 and at most 65535 bytes on the nRF52840 .
pub fn write_then_read(
        &mut self,
        address: u8,
        wr_buffer: &[u8],
        rd_buffer: &mut [u8],
    ) -> Result<(), Error> {
        // Conservative compiler fence to prevent optimizations that do not
        // take in to account actions by DMA. The fence has been placed here,
        // before any DMA action has started.
        compiler_fence(SeqCst);
        self.0
            .address
            .write(|w| unsafe { w.address().bits(address) });
        // Set up DMA buffers.
        unsafe {
            self.set_tx_buffer(wr_buffer)?;
            self.set_rx_buffer(rd_buffer)?;
        }
        // Clear events
        self.0.events_stopped.reset();
        self.0.events_error.reset();
        self.clear_errorsrc();
        // Start write+read operation.
        self.0.shorts.write(|w| {
            w.lasttx_startrx().enabled();
            w.lastrx_stop().enabled();
            w
        });
        // `1` is a valid value to write to task registers.
        self.0.tasks_starttx.write(|w| unsafe { w.bits(1) });
        self.wait();
        // Conservative compiler fence to prevent optimizations that do not
        // take in to account actions by DMA. The fence has been placed here,
        // after all possible DMA actions have completed.
        compiler_fence(SeqCst);
        self.read_errorsrc()?;
        let bad_write = self.0.txd.amount.read().bits() != wr_buffer.len() as u32;
        let bad_read = self.0.rxd.amount.read().bits() != rd_buffer.len() as u32;
        if bad_write {
            return Err(Error::Transmit);
        }
        if bad_read {
            return Err(Error::Receive);
        }
        Ok(())
    }
pub fn write_then_read ( & mut self , address : u8 , wr_buffer : & [ u8 ] , rd_buffer : & mut [ u8 ] , ) -> Result < ( ) , Error > { // Conservative compiler fence to prevent optimizations that do not // take in to account actions by DMA. The fence has been placed here, // before any DMA action has started. compiler_fence ( SeqCst ) ; self . 0 . address . write ( | w | unsafe { w . address ( ) . bits ( address ) } ) ; // Set up DMA buffers. unsafe { self . set_tx_buffer ( wr_buffer ) ? ; self . set_rx_buffer ( rd_buffer ) ? ; } // Clear events self . 0 . events_stopped . reset ( ) ; self . 0 . events_error . reset ( ) ; self . clear_errorsrc ( ) ; // Start write+read operation. self . 0 . shorts . write ( | w | { w . lasttx_startrx ( ) . enabled ( ) ; w . lastrx_stop ( ) . enabled ( ) ; w } ) ; // `1` is a valid value to write to task registers. self . 0 . tasks_starttx . write ( | w | unsafe { w . bits ( 1 ) } ) ; self . wait ( ) ; // Conservative compiler fence to prevent optimizations that do not // take in to account actions by DMA. The fence has been placed here, // after all possible DMA actions have completed. compiler_fence ( SeqCst ) ; self . read_errorsrc ( ) ? ; let bad_write = self . 0 . txd . amount . read ( ) . bits ( ) != wr_buffer . len ( ) as u32 ; let bad_read = self . 0 . rxd . amount . read ( ) . bits ( ) != rd_buffer . len ( ) as u32 ; if bad_write { return Err ( Error :: Transmit ) ; } if bad_read { return Err ( Error :: Receive ) ; } Ok ( ( ) ) }
Write data to an I2C slave, then read data from the slave without
triggering a stop condition between the two.
Write data to an I2C slave then read data from the slave without triggering a stop condition between the two .
&mut self
address
u8
wr_buffer
&[u8]
rd_buffer
&mut [u8]
&mut self
address
u8
wr_buffer
&[u8]
rd_buffer
&mut [u8]