pub fn rmr_request(&self, entry_point: u32, aarch64: bool) -> Result<(), Error> {
        if let Some(rvbar_reg) = self.soc_info.get_rvbar_reg() {
            let rmr_mode: u32 = (1 << 1) | (if aarch64 { 1 } else { 0 });

            let arm_code: [u32; LCODE_ARM_RMR_WORDS] = [
                // ldr    r0, [rvbar_reg]
                0x_e5_9f_00_28_u32.to_le(),
                // ldr    r1, [entry_point]
                0x_e5_9f_10_28_u32.to_le(),
                // str    r1, [r0]
                0x_e5_80_10_00_u32.to_le(),
                // dsb    sy
                0x_f5_7f_f0_4f_u32.to_le(),
                // isb    sy
                0x_f5_7f_f0_6f_u32.to_le(),
                // ldr    r1, [rmr_mode]
                0x_e5_9f_10_1c_u32.to_le(),
                // mrc    15, 0, r0, cr12, cr0, {2}
                0x_ee_1c_0f_50_u32.to_le(),
                // orr    r0, r0, r1
                0x_e1_80_00_01_u32.to_le(),
                // mcr    15, 0, r0, cr12, cr0, {2}
                0x_ee_0c_0f_50_u32.to_le(),
                // isb    sy
                0x_f5_7f_f0_6f_u32.to_le(),
                // loop:  wfi
                0x_e3_20_f0_03_u32.to_le(),
                // b      <loop>
                0x_ea_ff_ff_fd_u32.to_le(),
                rvbar_reg.to_le(),
                entry_point.to_le(),
                rmr_mode.to_le(),
            ];

            self.fel_write(self.soc_info.get_scratch_addr(), u32_as_u8(&arm_code))
                .context("unable to write ARM code to scratch address")?;
            self.fel_execute(self.soc_info.get_scratch_addr())
                .context("unable to execute ARM code")?;
            Ok(())
        } else {
            bail!(
                "can't issue RMR request, the SoC ({}) does not support RVBAR or it's unknown",
                self.soc_info.get_name()
            );
        }
    }
/// Perform FEL RMR request.
///
/// This function stores a given entry point to the `RVBAR` address for *CPU0*, and then writes
/// the Reset Management Register to request a warm boot.
/// It is useful with some *AArch64* transitions, e.g. when passing control to ARM Trusted
/// Firmware (ATF) during the boot process of Pine64.
///
/// The code was inspired by
/// [U-boot](https://github.com/apritzel/u-boot/commit/fda6bd1bf285c44f30ea15c7e6231bf53c31d4a8)
Perform FEL RMR request.
This function stores a given entry point to the `RVBAR` address for *CPU0*, and then writes
the Reset Management Register to request a warm boot.
It is useful with some *AArch64* transitions, e.g. when passing control to ARM Trusted
Firmware (ATF) during the boot process of Pine64.

The code was inspired by
[U-boot]
Perform FEL RMR request . This function stores a given entry point to the ` RVBAR ` address for * CPU0 * and then writes the Reset Management Register to request a warm boot . It is useful with some * AArch64 * transitions e . g . when passing control to ARM Trusted Firmware ( ATF ) during the boot process of Pine64 . The code was inspired by [ U - boot ]
pub fn rmr_request(&self, entry_point: u32, aarch64: bool) -> Result<(), Error> {
        if let Some(rvbar_reg) = self.soc_info.get_rvbar_reg() {
            let rmr_mode: u32 = (1 << 1) | (if aarch64 { 1 } else { 0 });
            let arm_code: [u32; LCODE_ARM_RMR_WORDS] = [
                // ldr    r0, [rvbar_reg]
                0x_e5_9f_00_28_u32.to_le(),
                // ldr    r1, [entry_point]
                0x_e5_9f_10_28_u32.to_le(),
                // str    r1, [r0]
                0x_e5_80_10_00_u32.to_le(),
                // dsb    sy
                0x_f5_7f_f0_4f_u32.to_le(),
                // isb    sy
                0x_f5_7f_f0_6f_u32.to_le(),
                // ldr    r1, [rmr_mode]
                0x_e5_9f_10_1c_u32.to_le(),
                // mrc    15, 0, r0, cr12, cr0, {2}
                0x_ee_1c_0f_50_u32.to_le(),
                // orr    r0, r0, r1
                0x_e1_80_00_01_u32.to_le(),
                // mcr    15, 0, r0, cr12, cr0, {2}
                0x_ee_0c_0f_50_u32.to_le(),
                // isb    sy
                0x_f5_7f_f0_6f_u32.to_le(),
                // loop:  wfi
                0x_e3_20_f0_03_u32.to_le(),
                // b      <loop>
                0x_ea_ff_ff_fd_u32.to_le(),
                rvbar_reg.to_le(),
                entry_point.to_le(),
                rmr_mode.to_le(),
            ];
            self.fel_write(self.soc_info.get_scratch_addr(), u32_as_u8(&arm_code))
                .context("unable to write ARM code to scratch address")?;
            self.fel_execute(self.soc_info.get_scratch_addr())
                .context("unable to execute ARM code")?;
            Ok(())
        } else {
            bail!(
                "can't issue RMR request, the SoC ({}) does not support RVBAR or it's unknown",
                self.soc_info.get_name()
            );
        }
    }
pub fn rmr_request ( & self , entry_point : u32 , aarch64 : bool ) -> Result < ( ) , Error > { if let Some ( rvbar_reg ) = self . soc_info . get_rvbar_reg ( ) { let rmr_mode : u32 = ( 1 << 1 ) | ( if aarch64 { 1 } else { 0 } ) ; let arm_code : [ u32 ; LCODE_ARM_RMR_WORDS ] = [ // ldr    r0, [rvbar_reg] 0x_e5_9f_00_28_u32 . to_le ( ) , // ldr    r1, [entry_point] 0x_e5_9f_10_28_u32 . to_le ( ) , // str    r1, [r0] 0x_e5_80_10_00_u32 . to_le ( ) , // dsb    sy 0x_f5_7f_f0_4f_u32 . to_le ( ) , // isb    sy 0x_f5_7f_f0_6f_u32 . to_le ( ) , // ldr    r1, [rmr_mode] 0x_e5_9f_10_1c_u32 . to_le ( ) , // mrc    15, 0, r0, cr12, cr0, {2} 0x_ee_1c_0f_50_u32 . to_le ( ) , // orr    r0, r0, r1 0x_e1_80_00_01_u32 . to_le ( ) , // mcr    15, 0, r0, cr12, cr0, {2} 0x_ee_0c_0f_50_u32 . to_le ( ) , // isb    sy 0x_f5_7f_f0_6f_u32 . to_le ( ) , // loop:  wfi 0x_e3_20_f0_03_u32 . to_le ( ) , // b      <loop> 0x_ea_ff_ff_fd_u32 . to_le ( ) , rvbar_reg . to_le ( ) , entry_point . to_le ( ) , rmr_mode . to_le ( ) , ] ; self . fel_write ( self . soc_info . get_scratch_addr ( ) , u32_as_u8 ( & arm_code ) ) . context ( " " ) ? ; self . fel_execute ( self . soc_info . get_scratch_addr ( ) ) . context ( " " ) ? ; Ok ( ( ) ) } else { bail ! ( " " self soc_info get_name ( ) ) ; } }
Perform FEL RMR request.
Perform FEL RMR request .
&self
entry_point
u32
aarch64
bool
&self
entry_point
u32
aarch64
bool