pub fn write(&mut self, loc: u16, val: u8) {
        let l = loc as usize - 0x8000;
        // print!("PPU Write: [{:04X}] = {:02X}. During mode {:?}\n", loc, val, self.get_mode());
        match self.get_mode() {
            Mode::VRAM => self.vram[l] = val, // TODO: do nothing
            _ => self.vram[l] = val,
        }
    }
// Both read and write expect loc to be in the address range 0x8000..=0x9FFF

Both read and write expect loc to be in the address range 0x8000..=0x9FFF
Both read and write expect loc to be in the address range 0x8000 .. = 0x9FFF
pub fn write(&mut self, loc: u16, val: u8) {
        let l = loc as usize - 0x8000;
        // print!("PPU Write: [{:04X}] = {:02X}. During mode {:?}\n", loc, val, self.get_mode());
        match self.get_mode() {
            Mode::VRAM => self.vram[l] = val, // TODO: do nothing
            _ => self.vram[l] = val,
        }
    }
pub fn write ( & mut self , loc : u16 , val : u8 ) { let l = loc as usize - 0x8000 ; // print!("PPU Write: [{:04X}] = {:02X}. During mode {:?}\n", loc, val, self.get_mode());
 match self . get_mode ( ) { Mode :: VRAM => self . vram [ l ] = val , // TODO: do nothing
 _ => self . vram [ l ] = val , } }
Both read and write expect loc to be in the address range 0x8000..=0x9FFF
Both read and write expect loc to be in the address range 0x8000 .. = 0x9FFF
&mut self
loc
u16
val
u8
&mut self
loc
u16
val
u8