fn sdram_unchecked<CHIP: SdramChip, BANK: Into<SdramTargetBank>>(
        self,
        bank: BANK,
        chip: CHIP,
        prec: rec::Fmc,
        clocks: &CoreClocks,
    ) -> Sdram<FMC, CHIP> {
        let fmc = self.fmc(prec, clocks);
        Sdram::new_unchecked(fmc, bank, chip)
    }
/// A new SDRAM memory via the Flexible Memory Controller
A new SDRAM memory via the Flexible Memory Controller
A new SDRAM memory via the Flexible Memory Controller
fn sdram_unchecked<CHIP: SdramChip, BANK: Into<SdramTargetBank>>(
        self,
        bank: BANK,
        chip: CHIP,
        prec: rec::Fmc,
        clocks: &CoreClocks,
    ) -> Sdram<FMC, CHIP> {
        let fmc = self.fmc(prec, clocks);
        Sdram::new_unchecked(fmc, bank, chip)
    }
fn sdram_unchecked < CHIP : SdramChip , BANK : Into < SdramTargetBank > > ( self , bank : BANK , chip : CHIP , prec : rec :: Fmc , clocks : & CoreClocks , ) -> Sdram < FMC , CHIP > { let fmc = self . fmc ( prec , clocks ) ; Sdram :: new_unchecked ( fmc , bank , chip ) }
A new SDRAM memory via the Flexible Memory Controller
A new SDRAM memory via the Flexible Memory Controller
self
bank
BANK
chip
CHIP
prec
rec::Fmc
clocks
&CoreClocks
self
bank
BANK
chip
CHIP
prec
rec::Fmc
clocks
&CoreClocks