pub(super) fn write(self, ctx: &mut impl CpuContext, val: u8) {
        trace!("Operand8::write {} -> {}", val, self);
        match self {
            Self::A => ctx.cpustate_mut().regs.acc = val,
            Self::B => ctx.cpustate_mut().regs.b = val,
            Self::C => ctx.cpustate_mut().regs.c = val,
            Self::D => ctx.cpustate_mut().regs.d = val,
            Self::E => ctx.cpustate_mut().regs.e = val,
            Self::H => ctx.cpustate_mut().regs.h = val,
            Self::L => ctx.cpustate_mut().regs.l = val,
            Self::AddrHL => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrBC => {
                let addr = ctx.cpustate().regs.bc();
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrDE => {
                let addr = ctx.cpustate().regs.de();
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrHLInc => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_add(1));
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrHLDec => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_sub(1));
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::Immediate => panic!("Immediates cannot be used as store destinations"),
            Self::AddrImmediate => {
                let addr = Operand16::Immediate.read(ctx);
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrRelC => {
                let addr = 0xFF00 + ctx.cpustate().regs.c as u16;
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrRelImmediate => {
                let addr = 0xFF00 + Self::Immediate.read(ctx) as u16;
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
        }
    }
/// Write this operand to the CPU context, yielding for memory access if needed.
Write this operand to the CPU context, yielding for memory access if needed.
Write this operand to the CPU context yielding for memory access if needed .
pub(super) fn write(self, ctx: &mut impl CpuContext, val: u8) {
        trace!("Operand8::write {} -> {}", val, self);
        match self {
            Self::A => ctx.cpustate_mut().regs.acc = val,
            Self::B => ctx.cpustate_mut().regs.b = val,
            Self::C => ctx.cpustate_mut().regs.c = val,
            Self::D => ctx.cpustate_mut().regs.d = val,
            Self::E => ctx.cpustate_mut().regs.e = val,
            Self::H => ctx.cpustate_mut().regs.h = val,
            Self::L => ctx.cpustate_mut().regs.l = val,
            Self::AddrHL => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrBC => {
                let addr = ctx.cpustate().regs.bc();
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrDE => {
                let addr = ctx.cpustate().regs.de();
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrHLInc => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_add(1));
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrHLDec => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_sub(1));
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::Immediate => panic!("Immediates cannot be used as store destinations"),
            Self::AddrImmediate => {
                let addr = Operand16::Immediate.read(ctx);
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrRelC => {
                let addr = 0xFF00 + ctx.cpustate().regs.c as u16;
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
            Self::AddrRelImmediate => {
                let addr = 0xFF00 + Self::Immediate.read(ctx) as u16;
                ctx.yield1m();
                ctx.mem_mut().write(addr.into(), val)
            }
        }
    }
pub ( super ) fn write ( self , ctx : & mut impl CpuContext , val : u8 ) { trace ! ( " " val self ) ; match self { Self :: A => ctx . cpustate_mut ( ) . regs . acc = val , Self :: B => ctx . cpustate_mut ( ) . regs . b = val , Self :: C => ctx . cpustate_mut ( ) . regs . c = val , Self :: D => ctx . cpustate_mut ( ) . regs . d = val , Self :: E => ctx . cpustate_mut ( ) . regs . e = val , Self :: H => ctx . cpustate_mut ( ) . regs . h = val , Self :: L => ctx . cpustate_mut ( ) . regs . l = val , Self :: AddrHL => { let addr = ctx . cpustate ( ) . regs . hl ( ) ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: AddrBC => { let addr = ctx . cpustate ( ) . regs . bc ( ) ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: AddrDE => { let addr = ctx . cpustate ( ) . regs . de ( ) ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: AddrHLInc => { let addr = ctx . cpustate ( ) . regs . hl ( ) ; ctx . yield1m ( ) ; ctx . cpustate_mut ( ) . regs . set_hl ( addr . wrapping_add ( 1 ) ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: AddrHLDec => { let addr = ctx . cpustate ( ) . regs . hl ( ) ; ctx . yield1m ( ) ; ctx . cpustate_mut ( ) . regs . set_hl ( addr . wrapping_sub ( 1 ) ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: Immediate => panic ! ( " " ) , Self :: AddrImmediate => { let addr = Operand16 :: Immediate . read ( ctx ) ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: AddrRelC => { let addr = 0xFF00 + ctx . cpustate ( ) . regs . c as u16 ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } Self :: AddrRelImmediate => { let addr = 0xFF00 + Self :: Immediate . read ( ctx ) as u16 ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . into ( ) , val ) } } }
Write this operand to the CPU context, yielding for memory access if needed.
Write this operand to the CPU context yielding for memory access if needed .
self
ctx
&mut impl CpuContext
val
u8
self
ctx
&mut impl CpuContext
val
u8