fn clock_irq_counter(&mut self, a12: bool, cycle_count: i32, cpu: &mut cpu::Cpu) {
        // if current a12 is high and a12 was low on previous read/write (a12 has risen)
        if a12 {
            if !self.bits.prev_a12.is_true() {
                // ignore a12 rise if there was another a12 rise 6 or fewer cycles ago
                if (cycle_count - self.cycle_count_at_prev_a12_high) as u32 > 6 {
                    if self.bits.irq_reload.is_true() || self.irq_counter == 0 {
                        // reload counter
                        self.irq_counter = self.irq_latch;
                        self.bits.irq_reload.set(0);
                    } else {
                        // decrement
                        self.irq_counter -= 1;
                    }

                    if self.irq_counter == 0 && self.bits.irq_enable.is_true() {
                        // if not already triggering cpu irq
                        if !self.bits.trigger_irq.is_true() {
                            self.bits.trigger_irq.set(1);
                            // increment 'irq' on cpu
                            cpu.irq += 1;
                        }
                    }
                }
            }

            self.cycle_count_at_prev_a12_high = cycle_count;
        }

        self.bits.prev_a12.set(a12 as u8);
    }
// clocks the irq counter depending on the state of a12 and the time since the
// last a12 rise. may trigger a cpu irq. called when 'read()'ing, 'write()'ing
// and 'set_address()'ing (see the 'PpuAddressBus trait impl below)
clocks the irq counter depending on the state of a12 and the time since the
last a12 rise. may trigger a cpu irq.
clocks the irq counter depending on the state of a12 and the time since the last a12 rise . may trigger a cpu irq .
fn clock_irq_counter(&mut self, a12: bool, cycle_count: i32, cpu: &mut cpu::Cpu) {
        // if current a12 is high and a12 was low on previous read/write (a12 has risen)
        if a12 {
            if !self.bits.prev_a12.is_true() {
                // ignore a12 rise if there was another a12 rise 6 or fewer cycles ago
                if (cycle_count - self.cycle_count_at_prev_a12_high) as u32 > 6 {
                    if self.bits.irq_reload.is_true() || self.irq_counter == 0 {
                        // reload counter
                        self.irq_counter = self.irq_latch;
                        self.bits.irq_reload.set(0);
                    } else {
                        // decrement
                        self.irq_counter -= 1;
                    }
                    if self.irq_counter == 0 && self.bits.irq_enable.is_true() {
                        // if not already triggering cpu irq
                        if !self.bits.trigger_irq.is_true() {
                            self.bits.trigger_irq.set(1);
                            // increment 'irq' on cpu
                            cpu.irq += 1;
                        }
                    }
                }
            }
            self.cycle_count_at_prev_a12_high = cycle_count;
        }
        self.bits.prev_a12.set(a12 as u8);
    }
fn clock_irq_counter ( & mut self , a12 : bool , cycle_count : i32 , cpu : & mut cpu :: Cpu ) { // if current a12 is high and a12 was low on previous read/write (a12 has risen) if a12 { if ! self . bits . prev_a12 . is_true ( ) { // ignore a12 rise if there was another a12 rise 6 or fewer cycles ago if ( cycle_count - self . cycle_count_at_prev_a12_high ) as u32 > 6 { if self . bits . irq_reload . is_true ( ) || self . irq_counter == 0 { // reload counter self . irq_counter = self . irq_latch ; self . bits . irq_reload . set ( 0 ) ; } else { // decrement self . irq_counter -= 1 ; } if self . irq_counter == 0 && self . bits . irq_enable . is_true ( ) { // if not already triggering cpu irq if ! self . bits . trigger_irq . is_true ( ) { self . bits . trigger_irq . set ( 1 ) ; // increment 'irq' on cpu cpu . irq += 1 ; } } } } self . cycle_count_at_prev_a12_high = cycle_count ; } self . bits . prev_a12 . set ( a12 as u8 ) ; }
clocks the irq counter depending on the state of a12 and the time since the
last a12 rise.
clocks the irq counter depending on the state of a12 and the time since the last a12 rise .
&mut self
a12
bool
cycle_count
i32
cpu
&mut cpu::Cpu
&mut self
a12
bool
cycle_count
i32
cpu
&mut cpu::Cpu