pub fn simulate_trace<F>(
    code: &[u8],
    mut trace_func: F,
    semihost_func: Box<dyn FnMut(&SemihostingCommand) -> SemihostingResponse + 'static>,
    itm_file: Option<Box<dyn io::Write + 'static>>,
    map: Option<MemoryMapConfig>,
    flash_size: usize,
) -> Result<SimulationStatistics, SimulationError>
where
    F: FnMut(&Processor),
{
    let mut processor = Processor::new();
    processor.itm(itm_file);
    processor.semihost(Some(semihost_func));
    processor.memory_map(map);
    processor.flash_memory(flash_size, code);
    processor.cache_instructions();

    let start = Instant::now();

    processor.reset().unwrap();
    processor.state.set_bit(0, true); // running

    while processor.state & 1 == 1 {
        while processor.state == 0b01 {
            //running, !sleeping
            processor.last_pc = processor.get_pc();
            processor.step();
            trace_func(&processor);
        }
        processor.last_pc = processor.get_pc();
        while processor.state == 0b11 {
            //running, sleeping
            processor.step_sleep();
        }
    }

    let end = Instant::now();

    Ok(SimulationStatistics {
        instruction_count: processor.instruction_count,
        cycle_count: processor.cycle_count,
        duration: end.duration_since(start),
    })
}
///
/// Run System simulation with tracing support
///
Run System simulation with tracing support
Run System simulation with tracing support
pub fn simulate_trace<F>(
    code: &[u8],
    mut trace_func: F,
    semihost_func: Box<dyn FnMut(&SemihostingCommand) -> SemihostingResponse + 'static>,
    itm_file: Option<Box<dyn io::Write + 'static>>,
    map: Option<MemoryMapConfig>,
    flash_size: usize,
) -> Result<SimulationStatistics, SimulationError>
where
    F: FnMut(&Processor),
{
    let mut processor = Processor::new();
    processor.itm(itm_file);
    processor.semihost(Some(semihost_func));
    processor.memory_map(map);
    processor.flash_memory(flash_size, code);
    processor.cache_instructions();
    let start = Instant::now();
    processor.reset().unwrap();
    processor.state.set_bit(0, true); // running
    while processor.state & 1 == 1 {
        while processor.state == 0b01 {
            //running, !sleeping
            processor.last_pc = processor.get_pc();
            processor.step();
            trace_func(&processor);
        }
        processor.last_pc = processor.get_pc();
        while processor.state == 0b11 {
            //running, sleeping
            processor.step_sleep();
        }
    }
    let end = Instant::now();
    Ok(SimulationStatistics {
        instruction_count: processor.instruction_count,
        cycle_count: processor.cycle_count,
        duration: end.duration_since(start),
    })
}
pub fn simulate_trace < F > ( code : & [ u8 ] , mut trace_func : F , semihost_func : Box < dyn FnMut ( & SemihostingCommand ) -> SemihostingResponse + ' static > , itm_file : Option < Box < dyn io :: Write + ' static > > , map : Option < MemoryMapConfig > , flash_size : usize , ) -> Result < SimulationStatistics , SimulationError > where F : FnMut ( & Processor ) , { let mut processor = Processor :: new ( ) ; processor . itm ( itm_file ) ; processor . semihost ( Some ( semihost_func ) ) ; processor . memory_map ( map ) ; processor . flash_memory ( flash_size , code ) ; processor . cache_instructions ( ) ; let start = Instant :: now ( ) ; processor . reset ( ) . unwrap ( ) ; processor . state . set_bit ( 0 , true ) ; // running while processor . state & 1 == 1 { while processor . state == 0b01 { //running, !sleeping processor . last_pc = processor . get_pc ( ) ; processor . step ( ) ; trace_func ( & processor ) ; } processor . last_pc = processor . get_pc ( ) ; while processor . state == 0b11 { //running, sleeping processor . step_sleep ( ) ; } } let end = Instant :: now ( ) ; Ok ( SimulationStatistics { instruction_count : processor . instruction_count , cycle_count : processor . cycle_count , duration : end . duration_since ( start ) , } ) }
Run System simulation with tracing support
Run System simulation with tracing support
code
&[u8]
trace_func
F
semihost_func
Box<dyn FnMut(&SemihostingCommand) -> SemihostingResponse + 'static>
itm_file
Option<Box<dyn io::Write + 'static>>
map
Option<MemoryMapConfig>
flash_size
usize
code
&[u8]
trace_func
F
semihost_func
Box<dyn FnMut(&SemihostingCommand) -> SemihostingResponse + 'static>
itm_file
Option<Box<dyn io::Write + 'static>>
map
Option<MemoryMapConfig>
flash_size
usize