fn emit(&self, sink: &mut MachBuffer<Self>, flags: &Flags, state: &mut Self::State) {
        let mut operands = vec![];

        for operand in &self.operands {
            let idx = operand.get_index();
            operands.push(idx as u32);
        }

        let mut opcode_len = 1 + operands.len() as u32;
        if self.result_type.is_some() {
            opcode_len += 1;
        }

        if self.result_id.is_some() {
            opcode_len += 1;
        }

        sink.put4((self.op as u32) | (opcode_len << 16));

        if let Some(r) = self.result_type {
            sink.put4(r);
        }

        if let Some(r) = self.result_id {
            let idx = r.to_reg().get_index();
            sink.put4(idx as u32);
        }

        for op in operands {
            sink.put4(op);
        }
    }
/// Unlike most ISA's, SPIR-V is relatively straight forward, all opcodes have the exact same
/// binary representation. Since SPIR-V already has virtual registers, there is no real need
/// for us to translate them (yet) so we just use the virtual register index from the CLIF
/// as the SPIR-V register index for now.
Unlike most ISA's, SPIR-V is relatively straight forward, all opcodes have the exact same
binary representation. Since SPIR-V already has virtual registers, there is no real need
for us to translate them (yet) so we just use the virtual register index from the CLIF
as the SPIR-V register index for now.
Unlike most ISA ' s SPIR - V is relatively straight forward all opcodes have the exact same binary representation . Since SPIR - V already has virtual registers there is no real need for us to translate them ( yet ) so we just use the virtual register index from the CLIF as the SPIR - V register index for now .
fn emit(&self, sink: &mut MachBuffer<Self>, flags: &Flags, state: &mut Self::State) {
        let mut operands = vec![];
        for operand in &self.operands {
            let idx = operand.get_index();
            operands.push(idx as u32);
        }
        let mut opcode_len = 1 + operands.len() as u32;
        if self.result_type.is_some() {
            opcode_len += 1;
        }
        if self.result_id.is_some() {
            opcode_len += 1;
        }
        sink.put4((self.op as u32) | (opcode_len << 16));
        if let Some(r) = self.result_type {
            sink.put4(r);
        }
        if let Some(r) = self.result_id {
            let idx = r.to_reg().get_index();
            sink.put4(idx as u32);
        }
        for op in operands {
            sink.put4(op);
        }
    }
fn emit ( & self , sink : & mut MachBuffer < Self > , flags : & Flags , state : & mut Self :: State ) { let mut operands = vec ! [ ] ; for operand in & self . operands { let idx = operand . get_index ( ) ; operands . push ( idx as u32 ) ; } let mut opcode_len = 1 + operands . len ( ) as u32 ; if self . result_type . is_some ( ) { opcode_len += 1 ; } if self . result_id . is_some ( ) { opcode_len += 1 ; } sink . put4 ( ( self . op as u32 ) | ( opcode_len << 16 ) ) ; if let Some ( r ) = self . result_type { sink . put4 ( r ) ; } if let Some ( r ) = self . result_id { let idx = r . to_reg ( ) . get_index ( ) ; sink . put4 ( idx as u32 ) ; } for op in operands { sink . put4 ( op ) ; } }
Unlike most ISA's, SPIR-V is relatively straight forward, all opcodes have the exact same
binary representation.
Unlike most ISA ' s SPIR - V is relatively straight forward all opcodes have the exact same binary representation .
&self
sink
&mut MachBuffer<Self>
flags
&Flags
state
&mut Self::State
&self
sink
&mut MachBuffer<Self>
flags
&Flags
state
&mut Self::State