pub(crate) fn load(
        ty: Type,
        from_addr: impl Into<SyntheticAmode>,
        to_reg: Writable<Reg>,
        ext_kind: ExtKind,
    ) -> Inst {
        let rc = to_reg.to_reg().get_class();
        match rc {
            RegClass::I64 => {
                let ext_mode = match ty.bytes() {
                    1 => Some(ExtMode::BQ),
                    2 => Some(ExtMode::WQ),
                    4 => Some(ExtMode::LQ),
                    8 => None,
                    _ => unreachable!("the type should never use a scalar load: {}", ty),
                };
                if let Some(ext_mode) = ext_mode {
                    // Values smaller than 64 bits must be extended in some way.
                    match ext_kind {
                        ExtKind::SignExtend => {
                            Inst::movsx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
                        }
                        ExtKind::ZeroExtend => {
                            Inst::movzx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
                        }
                        ExtKind::None => panic!(
                            "expected an extension kind for extension mode: {:?}",
                            ext_mode
                        ),
                    }
                } else {
                    // 64-bit values can be moved directly.
                    Inst::mov64_m_r(from_addr, to_reg)
                }
            }
            RegClass::V128 => {
                let opcode = match ty {
                    types::F32 => SseOpcode::Movss,
                    types::F64 => SseOpcode::Movsd,
                    types::F32X4 => SseOpcode::Movups,
                    types::F64X2 => SseOpcode::Movupd,
                    _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu,
                    _ => unimplemented!("unable to load type: {}", ty),
                };
                Inst::xmm_unary_rm_r(opcode, RegMem::mem(from_addr), to_reg)
            }
            _ => panic!("unable to generate load for register class: {:?}", rc),
        }
    }
/// Choose which instruction to use for loading a register value from memory. For loads smaller
/// than 64 bits, this method expects a way to extend the value (i.e. [ExtKind::SignExtend],
/// [ExtKind::ZeroExtend]); loads with no extension necessary will ignore this.
Choose which instruction to use for loading a register value from memory. For loads smaller
than 64 bits, this method expects a way to extend the value ; loads with no extension necessary will ignore this.
Choose which instruction to use for loading a register value from memory . For loads smaller than 64 bits this method expects a way to extend the value ; loads with no extension necessary will ignore this .
pub(crate) fn load(
        ty: Type,
        from_addr: impl Into<SyntheticAmode>,
        to_reg: Writable<Reg>,
        ext_kind: ExtKind,
    ) -> Inst {
        let rc = to_reg.to_reg().get_class();
        match rc {
            RegClass::I64 => {
                let ext_mode = match ty.bytes() {
                    1 => Some(ExtMode::BQ),
                    2 => Some(ExtMode::WQ),
                    4 => Some(ExtMode::LQ),
                    8 => None,
                    _ => unreachable!("the type should never use a scalar load: {}", ty),
                };
                if let Some(ext_mode) = ext_mode {
                    // Values smaller than 64 bits must be extended in some way.
                    match ext_kind {
                        ExtKind::SignExtend => {
                            Inst::movsx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
                        }
                        ExtKind::ZeroExtend => {
                            Inst::movzx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
                        }
                        ExtKind::None => panic!(
                            "expected an extension kind for extension mode: {:?}",
                            ext_mode
                        ),
                    }
                } else {
                    // 64-bit values can be moved directly.
                    Inst::mov64_m_r(from_addr, to_reg)
                }
            }
            RegClass::V128 => {
                let opcode = match ty {
                    types::F32 => SseOpcode::Movss,
                    types::F64 => SseOpcode::Movsd,
                    types::F32X4 => SseOpcode::Movups,
                    types::F64X2 => SseOpcode::Movupd,
                    _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu,
                    _ => unimplemented!("unable to load type: {}", ty),
                };
                Inst::xmm_unary_rm_r(opcode, RegMem::mem(from_addr), to_reg)
            }
            _ => panic!("unable to generate load for register class: {:?}", rc),
        }
    }
pub ( crate ) fn load ( ty : Type , from_addr : impl Into < SyntheticAmode > , to_reg : Writable < Reg > , ext_kind : ExtKind , ) -> Inst { let rc = to_reg . to_reg ( ) . get_class ( ) ; match rc { RegClass :: I64 => { let ext_mode = match ty . bytes ( ) { 1 => Some ( ExtMode :: BQ ) , 2 => Some ( ExtMode :: WQ ) , 4 => Some ( ExtMode :: LQ ) , 8 => None , _ => unreachable ! ( " " ty ) , } ; if let Some ( ext_mode ) = ext_mode { // Values smaller than 64 bits must be extended in some way. match ext_kind { ExtKind :: SignExtend => { Inst :: movsx_rm_r ( ext_mode , RegMem :: mem ( from_addr ) , to_reg ) } ExtKind :: ZeroExtend => { Inst :: movzx_rm_r ( ext_mode , RegMem :: mem ( from_addr ) , to_reg ) } ExtKind :: None => panic ! ( " " ext_mode ) , } } else { // 64-bit values can be moved directly. Inst :: mov64_m_r ( from_addr , to_reg ) } } RegClass :: V128 => { let opcode = match ty { types :: F32 => SseOpcode :: Movss , types :: F64 => SseOpcode :: Movsd , types :: F32X4 => SseOpcode :: Movups , types :: F64X2 => SseOpcode :: Movupd , _ if ty . is_vector ( ) && ty . bits ( ) == 128 => SseOpcode :: Movdqu , _ => unimplemented ! ( " " ty ) , } ; Inst :: xmm_unary_rm_r ( opcode , RegMem :: mem ( from_addr ) , to_reg ) } _ => panic ! ( " " rc ) , } }
Choose which instruction to use for loading a register value from memory.
Choose which instruction to use for loading a register value from memory .
ty
Type
from_addr
impl Into<SyntheticAmode>
to_reg
Writable<Reg>
ext_kind
ExtKind
ty
Type
from_addr
impl Into<SyntheticAmode>
to_reg
Writable<Reg>
ext_kind
ExtKind