pub fn deep_sleep_ready() -> bool {
    unsafe {
        (*PM_REGS).hsbmask.get() & !(DEEP_SLEEP_HSBMASK) == 0
            && (*PM_REGS).pbamask.get() & !(DEEP_SLEEP_PBAMASK) == 0
            && (*PM_REGS).pbbmask.get() & !(DEEP_SLEEP_PBBMASK) == 0
            && gpio::INTERRUPT_COUNT.load(Ordering::Relaxed) == 0
    }
}
/// Determines if the chip can safely go into deep sleep without preventing
/// currently active peripherals from operating.
///
/// We look at the PM's clock mask registers and compare them against a set of
/// known masks that include no peripherals that can't operate in deep
/// sleep (or that have no function during sleep). Specifically:
///
///   * HSB may only have clocks for the flash (and PicoCache) and APBx bridges on.
///
///   * PBA may not have _any_ clocks on.
///
///   * PBB may only have clocks for the flash and HRAMC1 (also flash related) on.
///
///   * PBC and PBD may have any clocks on.
///
/// This means it is the responsibility of each peripheral to disable it's clock
/// mask whenever it is idle.
///
/// We also special case GPIO (which is in PBCMASK), and just see if any interrupts are pending
/// through the INTERRUPT_COUNT variable.
Determines if the chip can safely go into deep sleep without preventing
currently active peripherals from operating.

We look at the PM's clock mask registers and compare them against a set of
known masks that include no peripherals that can't operate in deep
sleep (or that have no function during sleep). Specifically.

HSB may only have clocks for the flash (and PicoCache) and APBx bridges on.

PBA may not have _any_ clocks on.

PBB may only have clocks for the flash and HRAMC1 (also flash related) on.

PBC and PBD may have any clocks on.

This means it is the responsibility of each peripheral to disable it's clock
mask whenever it is idle.

We also special case GPIO (which is in PBCMASK), and just see if any interrupts are pending
through the INTERRUPT_COUNT variable.
Determines if the chip can safely go into deep sleep without preventing currently active peripherals from operating . We look at the PM ' s clock mask registers and compare them against a set of known masks that include no peripherals that can ' t operate in deep sleep ( or that have no function during sleep ) . Specifically . HSB may only have clocks for the flash ( and PicoCache ) and APBx bridges on . PBA may not have _any_ clocks on . PBB may only have clocks for the flash and HRAMC1 ( also flash related ) on . PBC and PBD may have any clocks on . This means it is the responsibility of each peripheral to disable it ' s clock mask whenever it is idle . We also special case GPIO ( which is in PBCMASK ) and just see if any interrupts are pending through the INTERRUPT_COUNT variable .
pub fn deep_sleep_ready() -> bool {
    unsafe {
        (*PM_REGS).hsbmask.get() & !(DEEP_SLEEP_HSBMASK) == 0
            && (*PM_REGS).pbamask.get() & !(DEEP_SLEEP_PBAMASK) == 0
            && (*PM_REGS).pbbmask.get() & !(DEEP_SLEEP_PBBMASK) == 0
            && gpio::INTERRUPT_COUNT.load(Ordering::Relaxed) == 0
    }
}
pub fn deep_sleep_ready ( ) -> bool { unsafe { ( * PM_REGS ) . hsbmask . get ( ) & ! ( DEEP_SLEEP_HSBMASK ) == 0 && ( * PM_REGS ) . pbamask . get ( ) & ! ( DEEP_SLEEP_PBAMASK ) == 0 && ( * PM_REGS ) . pbbmask . get ( ) & ! ( DEEP_SLEEP_PBBMASK ) == 0 && gpio :: INTERRUPT_COUNT . load ( Ordering :: Relaxed ) == 0 } }
Determines if the chip can safely go into deep sleep without preventing
currently active peripherals from operating.
Determines if the chip can safely go into deep sleep without preventing currently active peripherals from operating .