pub unsafe fn enable(&self) -> Option<u32> {
        // 23 and lower are used
        static mut MSI_IRQ: u32 = 23;

        let orig = self.read(PCI_COMMAND, 2);
        // IO Space | MEM Space | Bus Mastering | Special Cycles | PCI Interrupt Disable
        self.write(PCI_COMMAND, orig | 0x40f);

        // find MSI cap
        let mut msi_found = false;
        let mut cap_ptr = self.read(PCI_CAP_PTR, 1);
        let mut assigned_irq = None;
        while cap_ptr > 0 {
            let cap_id = self.read(cap_ptr, 1);
            if cap_id == PCI_CAP_ID_MSI {
                // The manual Volume 3 Chapter 10.11 Message Signalled Interrupts
                // 0 is (usually) the apic id of the bsp.
                self.write(cap_ptr + PCI_MSI_ADDR, 0xfee00000 | (0 << 12));
                MSI_IRQ += 1;
                let irq = MSI_IRQ;
                assigned_irq = Some(irq);
                // we offset all our irq numbers by 32
                self.write(cap_ptr + PCI_MSI_DATA, irq + 32);

                // enable MSI interrupt, assuming 64bit for now
                let orig_ctrl = self.read(cap_ptr + PCI_MSI_CTRL_CAP, 4);
                self.write(cap_ptr + PCI_MSI_CTRL_CAP, orig_ctrl | 0x10000);
                debug!(
                    "MSI control {:#b}, enabling MSI interrupts",
                    orig_ctrl >> 16
                );
                msi_found = true;
                break;
            }
            debug!(
                "PCI device has cap id {} at {:#X}",
                self.read(cap_ptr, 1),
                cap_ptr
            );
            cap_ptr = self.read(cap_ptr + 1, 1);
        }

        if !msi_found {
            // Use PCI legacy interrupt instead
            // IO Space | MEM Space | Bus Mastering | Special Cycles
            self.write(PCI_COMMAND, orig | 0xf);
            let line = self.read(PCI_INTERRUPT_LINE, 1);
            let pin = self.read(PCI_INTERRUPT_PIN, 1);
            debug!(
                "MSI not found, using PCI interrupt line {} pin {}",
                line, pin
            );
        }

        assigned_irq
    }
/// Enable the pci tag and its interrupt
/// Return assigned MSI interrupt number when applicable
Enable the pci tag and its interrupt
Return assigned MSI interrupt number when applicable
Enable the pci tag and its interrupt Return assigned MSI interrupt number when applicable
pub unsafe fn enable(&self) -> Option<u32> {
        // 23 and lower are used
        static mut MSI_IRQ: u32 = 23;
        let orig = self.read(PCI_COMMAND, 2);
        // IO Space | MEM Space | Bus Mastering | Special Cycles | PCI Interrupt Disable
        self.write(PCI_COMMAND, orig | 0x40f);
        // find MSI cap
        let mut msi_found = false;
        let mut cap_ptr = self.read(PCI_CAP_PTR, 1);
        let mut assigned_irq = None;
        while cap_ptr > 0 {
            let cap_id = self.read(cap_ptr, 1);
            if cap_id == PCI_CAP_ID_MSI {
                // The manual Volume 3 Chapter 10.11 Message Signalled Interrupts
                // 0 is (usually) the apic id of the bsp.
                self.write(cap_ptr + PCI_MSI_ADDR, 0xfee00000 | (0 << 12));
                MSI_IRQ += 1;
                let irq = MSI_IRQ;
                assigned_irq = Some(irq);
                // we offset all our irq numbers by 32
                self.write(cap_ptr + PCI_MSI_DATA, irq + 32);
                // enable MSI interrupt, assuming 64bit for now
                let orig_ctrl = self.read(cap_ptr + PCI_MSI_CTRL_CAP, 4);
                self.write(cap_ptr + PCI_MSI_CTRL_CAP, orig_ctrl | 0x10000);
                debug!(
                    "MSI control {:#b}, enabling MSI interrupts",
                    orig_ctrl >> 16
                );
                msi_found = true;
                break;
            }
            debug!(
                "PCI device has cap id {} at {:#X}",
                self.read(cap_ptr, 1),
                cap_ptr
            );
            cap_ptr = self.read(cap_ptr + 1, 1);
        }
        if !msi_found {
            // Use PCI legacy interrupt instead
            // IO Space | MEM Space | Bus Mastering | Special Cycles
            self.write(PCI_COMMAND, orig | 0xf);
            let line = self.read(PCI_INTERRUPT_LINE, 1);
            let pin = self.read(PCI_INTERRUPT_PIN, 1);
            debug!(
                "MSI not found, using PCI interrupt line {} pin {}",
                line, pin
            );
        }
        assigned_irq
    }
pub unsafe fn enable ( & self ) -> Option < u32 > { // 23 and lower are used static mut MSI_IRQ : u32 = 23 ; let orig = self . read ( PCI_COMMAND , 2 ) ; // IO Space | MEM Space | Bus Mastering | Special Cycles | PCI Interrupt Disable self . write ( PCI_COMMAND , orig | 0x40f ) ; // find MSI cap let mut msi_found = false ; let mut cap_ptr = self . read ( PCI_CAP_PTR , 1 ) ; let mut assigned_irq = None ; while cap_ptr > 0 { let cap_id = self . read ( cap_ptr , 1 ) ; if cap_id == PCI_CAP_ID_MSI { // The manual Volume 3 Chapter 10.11 Message Signalled Interrupts // 0 is (usually) the apic id of the bsp. self . write ( cap_ptr + PCI_MSI_ADDR , 0xfee00000 | ( 0 << 12 ) ) ; MSI_IRQ += 1 ; let irq = MSI_IRQ ; assigned_irq = Some ( irq ) ; // we offset all our irq numbers by 32 self . write ( cap_ptr + PCI_MSI_DATA , irq + 32 ) ; // enable MSI interrupt, assuming 64bit for now let orig_ctrl = self . read ( cap_ptr + PCI_MSI_CTRL_CAP , 4 ) ; self . write ( cap_ptr + PCI_MSI_CTRL_CAP , orig_ctrl | 0x10000 ) ; debug ! ( " " orig_ctrl 16 ) ; msi_found = true ; break ; } debug ! ( " " self read ( cap_ptr 1 ) cap_ptr ) ; cap_ptr = self . read ( cap_ptr + 1 , 1 ) ; } if ! msi_found { // Use PCI legacy interrupt instead // IO Space | MEM Space | Bus Mastering | Special Cycles self . write ( PCI_COMMAND , orig | 0xf ) ; let line = self . read ( PCI_INTERRUPT_LINE , 1 ) ; let pin = self . read ( PCI_INTERRUPT_PIN , 1 ) ; debug ! ( " " line pin ) ; } assigned_irq }
Enable the pci tag and its interrupt
Return assigned MSI interrupt number when applicable
Enable the pci tag and its interrupt Return assigned MSI interrupt number when applicable
&self
&self