fn smi_write(&mut self, reg: u8, val: u16) {
        while self.eth_mac.macmdioar.read().mb().bit_is_set() {}
        self.eth_mac
            .macmdiodr
            .write(|w| unsafe { w.md().bits(val) });
        self.eth_mac.macmdioar.modify(|_, w| unsafe {
            w.pa()
                .bits(self.eth_phy_addr)
                .rda()
                .bits(reg)
                .goc()
                .bits(0b01) // write
                .cr()
                .bits(self.clock_range)
                .mb()
                .set_bit()
        });
        while self.eth_mac.macmdioar.read().mb().bit_is_set() {}
    }
/// Write a register over SMI.
Write a register over SMI.
Write a register over SMI .
fn smi_write(&mut self, reg: u8, val: u16) {
        while self.eth_mac.macmdioar.read().mb().bit_is_set() {}
        self.eth_mac
            .macmdiodr
            .write(|w| unsafe { w.md().bits(val) });
        self.eth_mac.macmdioar.modify(|_, w| unsafe {
            w.pa()
                .bits(self.eth_phy_addr)
                .rda()
                .bits(reg)
                .goc()
                .bits(0b01) // write
                .cr()
                .bits(self.clock_range)
                .mb()
                .set_bit()
        });
        while self.eth_mac.macmdioar.read().mb().bit_is_set() {}
    }
fn smi_write ( & mut self , reg : u8 , val : u16 ) { while self . eth_mac . macmdioar . read ( ) . mb ( ) . bit_is_set ( ) { } self . eth_mac . macmdiodr . write ( | w | unsafe { w . md ( ) . bits ( val ) } ) ; self . eth_mac . macmdioar . modify ( | _ , w | unsafe { w . pa ( ) . bits ( self . eth_phy_addr ) . rda ( ) . bits ( reg ) . goc ( ) . bits ( 0b01 ) // write . cr ( ) . bits ( self . clock_range ) . mb ( ) . set_bit ( ) } ) ; while self . eth_mac . macmdioar . read ( ) . mb ( ) . bit_is_set ( ) { } }
Write a register over SMI.
Write a register over SMI .
&mut self
reg
u8
val
u16
&mut self
reg
u8
val
u16