pub fn init(spi: SPI, cs: CS, delay: Delay<TIM5, 1_000_000>) -> Result<Self, Error<SPI, CS>> {
        let mut this = Self { spi, cs, delay };
        this.reset_device()?;
        let status = this.read_status()?;
        info!("Flash::init: status = {:?}", status);

        // Here we don't expect any writes to be in progress, and the latch must
        // also be deasserted.

        if !(status & (Status::BUSY | Status::WEL)).is_empty() {
            return Err(Error::UnexpectedStatus);
        }
        Ok(this)
    }
/// Creates a new 25-series flash driver.
///
/// # Parameters
///
/// * **`spi`**: An SPI master. Must be configured to operate in the correct
///   mode for the device.
/// * **`cs`**: The **C**hip-**S**elect Pin connected to the `\CS`/`\CE` pin
///   of the flash chip. Will be driven low when accessing the device.
Creates a new 25-series flash driver.
Creates a new 25 - series flash driver .
pub fn init(spi: SPI, cs: CS, delay: Delay<TIM5, 1_000_000>) -> Result<Self, Error<SPI, CS>> {
        let mut this = Self { spi, cs, delay };
        this.reset_device()?;
        let status = this.read_status()?;
        info!("Flash::init: status = {:?}", status);
        // Here we don't expect any writes to be in progress, and the latch must
        // also be deasserted.
        if !(status & (Status::BUSY | Status::WEL)).is_empty() {
            return Err(Error::UnexpectedStatus);
        }
        Ok(this)
    }
pub fn init ( spi : SPI , cs : CS , delay : Delay < TIM5 , 1_000_000 > ) -> Result < Self , Error < SPI , CS > > { let mut this = Self { spi , cs , delay } ; this . reset_device ( ) ? ; let status = this . read_status ( ) ? ; info ! ( " " status ) ; // Here we don't expect any writes to be in progress, and the latch must // also be deasserted. if ! ( status & ( Status :: BUSY | Status :: WEL ) ) . is_empty ( ) { return Err ( Error :: UnexpectedStatus ) ; } Ok ( this ) }
Creates a new 25-series flash driver.
Creates a new 25 - series flash driver .
spi
SPI
cs
CS
delay
Delay<TIM5, 1_000_000>
spi
SPI
cs
CS
delay
Delay<TIM5, 1_000_000>