fn configure_and_enable_dfll48m(sysctrl: &mut SYSCTRL, use_external_crystal: bool) {
    // Turn it off while we configure it.
    // Note that we need to turn off on-demand mode and
    // disable it here, rather than just reseting the ctrl
    // register, otherwise our configuration attempt fails.
    sysctrl.dfllctrl.write(|w| w.ondemand().clear_bit());
    wait_for_dfllrdy(sysctrl);

    if use_external_crystal {
        sysctrl.dfllmul.write(|w| unsafe {
            w.cstep().bits(31);
            w.fstep().bits(511);
            // scaling factor between the clocks
            w.mul().bits(((48_000_000u32 + 32768 / 2) / 32768) as u16)
        });

        // Turn it on
        sysctrl.dfllctrl.write(|w| {
            // always on
            w.ondemand().clear_bit();

            // closed loop mode
            w.mode().set_bit();

            w.waitlock().set_bit();

            // Disable quick lock
            w.qldis().set_bit()
        });
    } else {
        // Apply calibration
        let coarse = super::calibration::dfll48m_coarse_cal();
        let fine = 0x1ff;

        sysctrl.dfllval.write(|w| unsafe {
            w.coarse().bits(coarse);
            w.fine().bits(fine)
        });

        sysctrl.dfllmul.write(|w| unsafe {
            w.cstep().bits(coarse / 4);
            w.fstep().bits(10);
            // scaling factor between the clocks
            w.mul().bits((48_000_000u32 / 32768) as u16)
        });

        // Turn it on
        sysctrl.dfllctrl.write(|w| {
            // always on
            w.ondemand().clear_bit();

            // closed loop mode
            w.mode().set_bit();

            // chill cycle disable
            w.ccdis().set_bit();

            // usb correction is not set due to instability issues around
            // USB bus resets. TODO(twitchyliquid64): Maybe switch to OSC8M?
            //
            // TODO usb correction (still active for samd11??)
            #[cfg(feature = "samd11")]
            w.usbcrm().set_bit();

            // bypass coarse lock (have calibration data)
            w.bplckc().set_bit()
        });
    }

    wait_for_dfllrdy(sysctrl);

    // and finally enable it!
    sysctrl.dfllctrl.modify(|_, w| w.enable().set_bit());

    #[cfg(feature = "samd21")]
    if use_external_crystal {
        // wait for lock
        while sysctrl.pclksr.read().dflllckc().bit_is_clear()
            || sysctrl.pclksr.read().dflllckf().bit_is_clear()
        {}
    }

    wait_for_dfllrdy(sysctrl);
}
/// Configure the dfll48m to operate at 48Mhz
Configure the dfll48m to operate at 48Mhz
Configure the dfll48m to operate at 48Mhz
fn configure_and_enable_dfll48m(sysctrl: &mut SYSCTRL, use_external_crystal: bool) {
    // Turn it off while we configure it.
    // Note that we need to turn off on-demand mode and
    // disable it here, rather than just reseting the ctrl
    // register, otherwise our configuration attempt fails.
    sysctrl.dfllctrl.write(|w| w.ondemand().clear_bit());
    wait_for_dfllrdy(sysctrl);
    if use_external_crystal {
        sysctrl.dfllmul.write(|w| unsafe {
            w.cstep().bits(31);
            w.fstep().bits(511);
            // scaling factor between the clocks
            w.mul().bits(((48_000_000u32 + 32768 / 2) / 32768) as u16)
        });
        // Turn it on
        sysctrl.dfllctrl.write(|w| {
            // always on
            w.ondemand().clear_bit();
            // closed loop mode
            w.mode().set_bit();
            w.waitlock().set_bit();
            // Disable quick lock
            w.qldis().set_bit()
        });
    } else {
        // Apply calibration
        let coarse = super::calibration::dfll48m_coarse_cal();
        let fine = 0x1ff;
        sysctrl.dfllval.write(|w| unsafe {
            w.coarse().bits(coarse);
            w.fine().bits(fine)
        });
        sysctrl.dfllmul.write(|w| unsafe {
            w.cstep().bits(coarse / 4);
            w.fstep().bits(10);
            // scaling factor between the clocks
            w.mul().bits((48_000_000u32 / 32768) as u16)
        });
        // Turn it on
        sysctrl.dfllctrl.write(|w| {
            // always on
            w.ondemand().clear_bit();
            // closed loop mode
            w.mode().set_bit();
            // chill cycle disable
            w.ccdis().set_bit();
            // usb correction is not set due to instability issues around
            // USB bus resets. TODO(twitchyliquid64): Maybe switch to OSC8M?
            //
            // TODO usb correction (still active for samd11??)
            #[cfg(feature = "samd11")]
            w.usbcrm().set_bit();
            // bypass coarse lock (have calibration data)
            w.bplckc().set_bit()
        });
    }
    wait_for_dfllrdy(sysctrl);
    // and finally enable it!
    sysctrl.dfllctrl.modify(|_, w| w.enable().set_bit());
    #[cfg(feature = "samd21")]
    if use_external_crystal {
        // wait for lock
        while sysctrl.pclksr.read().dflllckc().bit_is_clear()
            || sysctrl.pclksr.read().dflllckf().bit_is_clear()
        {}
    }
    wait_for_dfllrdy(sysctrl);
}
fn configure_and_enable_dfll48m ( sysctrl : & mut SYSCTRL , use_external_crystal : bool ) { // Turn it off while we configure it. // Note that we need to turn off on-demand mode and // disable it here, rather than just reseting the ctrl // register, otherwise our configuration attempt fails. sysctrl . dfllctrl . write ( | w | w . ondemand ( ) . clear_bit ( ) ) ; wait_for_dfllrdy ( sysctrl ) ; if use_external_crystal { sysctrl . dfllmul . write ( | w | unsafe { w . cstep ( ) . bits ( 31 ) ; w . fstep ( ) . bits ( 511 ) ; // scaling factor between the clocks w . mul ( ) . bits ( ( ( 48_000_000u32 + 32768 / 2 ) / 32768 ) as u16 ) } ) ; // Turn it on sysctrl . dfllctrl . write ( | w | { // always on w . ondemand ( ) . clear_bit ( ) ; // closed loop mode w . mode ( ) . set_bit ( ) ; w . waitlock ( ) . set_bit ( ) ; // Disable quick lock w . qldis ( ) . set_bit ( ) } ) ; } else { // Apply calibration let coarse = super :: calibration :: dfll48m_coarse_cal ( ) ; let fine = 0x1ff ; sysctrl . dfllval . write ( | w | unsafe { w . coarse ( ) . bits ( coarse ) ; w . fine ( ) . bits ( fine ) } ) ; sysctrl . dfllmul . write ( | w | unsafe { w . cstep ( ) . bits ( coarse / 4 ) ; w . fstep ( ) . bits ( 10 ) ; // scaling factor between the clocks w . mul ( ) . bits ( ( 48_000_000u32 / 32768 ) as u16 ) } ) ; // Turn it on sysctrl . dfllctrl . write ( | w | { // always on w . ondemand ( ) . clear_bit ( ) ; // closed loop mode w . mode ( ) . set_bit ( ) ; // chill cycle disable w . ccdis ( ) . set_bit ( ) ; // usb correction is not set due to instability issues around // USB bus resets. TODO(twitchyliquid64): Maybe switch to OSC8M? // // TODO usb correction (still active for samd11??) # [ cfg ( feature " " ) ] w . usbcrm ( ) . set_bit ( ) ; // bypass coarse lock (have calibration data) w . bplckc ( ) . set_bit ( ) } ) ; } wait_for_dfllrdy ( sysctrl ) ; // and finally enable it! sysctrl . dfllctrl . modify ( | _ , w | w . enable ( ) . set_bit ( ) ) ; # [ cfg ( feature " " ) ] if use_external_crystal { // wait for lock while sysctrl . pclksr . read ( ) . dflllckc ( ) . bit_is_clear ( ) || sysctrl . pclksr . read ( ) . dflllckf ( ) . bit_is_clear ( ) { } } wait_for_dfllrdy ( sysctrl ) ; }
Configure the dfll48m to operate at 48Mhz
Configure the dfll48m to operate at 48Mhz
sysctrl
&mut SYSCTRL
use_external_crystal
bool
sysctrl
&mut SYSCTRL
use_external_crystal
bool