fn pci_config_reset(&mut self) -> Result<()> {
        let mut cmd = le_read_u16(&self.pci_config.config, COMMAND as usize)?;
        cmd &= !(COMMAND_IO_SPACE
            | COMMAND_MEMORY_SPACE
            | COMMAND_BUS_MASTER
            | COMMAND_INTERRUPT_DISABLE);
        le_write_u16(&mut self.pci_config.config, COMMAND as usize, cmd)?;

        let mut data = vec![0u8; 2];
        LittleEndian::write_u16(&mut data, cmd);
        self.vfio_device
            .write_region(data.as_slice(), self.config_offset, COMMAND as u64)?;

        for i in 0..PCI_ROM_SLOT {
            let offset = BAR_0 as usize + REG_SIZE * i as usize;
            let v = le_read_u32(&self.pci_config.config, offset)?;
            if v & BAR_IO_SPACE as u32 != 0 {
                le_write_u32(&mut self.pci_config.config, offset, v & !IO_BASE_ADDR_MASK)?;
            } else {
                le_write_u32(
                    &mut self.pci_config.config,
                    offset,
                    v & !MEM_BASE_ADDR_MASK as u32,
                )?;
            }
        }

        Ok(())
    }
/// Disable I/O, MMIO, bus master and INTx states, And clear host device bar size information.
/// Guest OS can get residual addresses from the host if not clear bar size.
Disable I/O, MMIO, bus master and INTx states, And clear host device bar size information.
Guest OS can get residual addresses from the host if not clear bar size.
Disable I / O MMIO bus master and INTx states And clear host device bar size information . Guest OS can get residual addresses from the host if not clear bar size .
fn pci_config_reset(&mut self) -> Result<()> {
        let mut cmd = le_read_u16(&self.pci_config.config, COMMAND as usize)?;
        cmd &= !(COMMAND_IO_SPACE
            | COMMAND_MEMORY_SPACE
            | COMMAND_BUS_MASTER
            | COMMAND_INTERRUPT_DISABLE);
        le_write_u16(&mut self.pci_config.config, COMMAND as usize, cmd)?;
        let mut data = vec![0u8; 2];
        LittleEndian::write_u16(&mut data, cmd);
        self.vfio_device
            .write_region(data.as_slice(), self.config_offset, COMMAND as u64)?;
        for i in 0..PCI_ROM_SLOT {
            let offset = BAR_0 as usize + REG_SIZE * i as usize;
            let v = le_read_u32(&self.pci_config.config, offset)?;
            if v & BAR_IO_SPACE as u32 != 0 {
                le_write_u32(&mut self.pci_config.config, offset, v & !IO_BASE_ADDR_MASK)?;
            } else {
                le_write_u32(
                    &mut self.pci_config.config,
                    offset,
                    v & !MEM_BASE_ADDR_MASK as u32,
                )?;
            }
        }
        Ok(())
    }
fn pci_config_reset ( & mut self ) -> Result < ( ) > { let mut cmd = le_read_u16 ( & self . pci_config . config , COMMAND as usize ) ? ; cmd &= ! ( COMMAND_IO_SPACE | COMMAND_MEMORY_SPACE | COMMAND_BUS_MASTER | COMMAND_INTERRUPT_DISABLE ) ; le_write_u16 ( & mut self . pci_config . config , COMMAND as usize , cmd ) ? ; let mut data = vec ! [ 0u8 2 ] ; LittleEndian :: write_u16 ( & mut data , cmd ) ; self . vfio_device . write_region ( data . as_slice ( ) , self . config_offset , COMMAND as u64 ) ? ; for i in 0 .. PCI_ROM_SLOT { let offset = BAR_0 as usize + REG_SIZE * i as usize ; let v = le_read_u32 ( & self . pci_config . config , offset ) ? ; if v & BAR_IO_SPACE as u32 != 0 { le_write_u32 ( & mut self . pci_config . config , offset , v & ! IO_BASE_ADDR_MASK ) ? ; } else { le_write_u32 ( & mut self . pci_config . config , offset , v & ! MEM_BASE_ADDR_MASK as u32 , ) ? ; } } Ok ( ( ) ) }
Disable I/O, MMIO, bus master and INTx states, And clear host device bar size information.
Disable I / O MMIO bus master and INTx states And clear host device bar size information .
&mut self
&mut self