pub fn release(&mut self) {
        let x = self.tdidx;
        assert!(self.td[x].tdes3 & EMAC_DES3_OWN == 0); // Owned by us

        let address = ptr::addr_of!(self.tbuf[x]) as u32;

        // Read format
        self.td[x].tdes0 = address; // Buffer 1
        self.td[x].tdes1 = 0; // Not used
        assert!(self.td[x].tdes2 & !EMAC_TDES2_B1L == 0); // Not used
        assert!(self.td[x].tdes2 & EMAC_TDES2_B1L > 0); // Length must be valid
        self.td[x].tdes3 = 0;
        self.td[x].tdes3 |= EMAC_DES3_FD; // FD: Contains first buffer of packet
        self.td[x].tdes3 |= EMAC_DES3_LD; // LD: Contains last buffer of packet
        self.td[x].tdes3 |= EMAC_DES3_OWN; // Give the DMA engine ownership

        // Ensure changes to the descriptor are committed before
        // DMA engine sees tail pointer store
        cortex_m::asm::dsb();

        // Move the tail pointer (TPR) to the next descriptor
        let x = (x + 1) % TD;
        unsafe {
            let dma = &*stm32::ETHERNET_DMA::ptr();
            dma.dmactx_dtpr
                .write(|w| w.bits(&(self.td[x]) as *const _ as u32));
        }

        self.tdidx = x;
    }
/// Release the next TDes to the DMA engine for transmission
Release the next TDes to the DMA engine for transmission
Release the next TDes to the DMA engine for transmission
pub fn release(&mut self) {
        let x = self.tdidx;
        assert!(self.td[x].tdes3 & EMAC_DES3_OWN == 0); // Owned by us
        let address = ptr::addr_of!(self.tbuf[x]) as u32;
        // Read format
        self.td[x].tdes0 = address; // Buffer 1
        self.td[x].tdes1 = 0; // Not used
        assert!(self.td[x].tdes2 & !EMAC_TDES2_B1L == 0); // Not used
        assert!(self.td[x].tdes2 & EMAC_TDES2_B1L > 0); // Length must be valid
        self.td[x].tdes3 = 0;
        self.td[x].tdes3 |= EMAC_DES3_FD; // FD: Contains first buffer of packet
        self.td[x].tdes3 |= EMAC_DES3_LD; // LD: Contains last buffer of packet
        self.td[x].tdes3 |= EMAC_DES3_OWN; // Give the DMA engine ownership
        // Ensure changes to the descriptor are committed before
        // DMA engine sees tail pointer store
        cortex_m::asm::dsb();
        // Move the tail pointer (TPR) to the next descriptor
        let x = (x + 1) % TD;
        unsafe {
            let dma = &*stm32::ETHERNET_DMA::ptr();
            dma.dmactx_dtpr
                .write(|w| w.bits(&(self.td[x]) as *const _ as u32));
        }
        self.tdidx = x;
    }
pub fn release ( & mut self ) { let x = self . tdidx ; assert ! ( self td [ x ] tdes3 EMAC_DES3_OWN 0 ) ; // Owned by us let address = ptr :: addr_of ! ( self tbuf [ x ] ) as u32 ; // Read format self . td [ x ] . tdes0 = address ; // Buffer 1 self . td [ x ] . tdes1 = 0 ; // Not used assert ! ( self td [ x ] tdes2 EMAC_TDES2_B1L 0 ) ; // Not used assert ! ( self td [ x ] tdes2 EMAC_TDES2_B1L 0 ) ; // Length must be valid self . td [ x ] . tdes3 = 0 ; self . td [ x ] . tdes3 |= EMAC_DES3_FD ; // FD: Contains first buffer of packet self . td [ x ] . tdes3 |= EMAC_DES3_LD ; // LD: Contains last buffer of packet self . td [ x ] . tdes3 |= EMAC_DES3_OWN ; // Give the DMA engine ownership // Ensure changes to the descriptor are committed before // DMA engine sees tail pointer store cortex_m :: asm :: dsb ( ) ; // Move the tail pointer (TPR) to the next descriptor let x = ( x + 1 ) % TD ; unsafe { let dma = & * stm32 :: ETHERNET_DMA :: ptr ( ) ; dma . dmactx_dtpr . write ( | w | w . bits ( & ( self . td [ x ] ) as * const _ as u32 ) ) ; } self . tdidx = x ; }
Release the next TDes to the DMA engine for transmission
Release the next TDes to the DMA engine for transmission
&mut self
&mut self