pub fn freeze(self, acr: &mut ACR) -> Clocks {
        let pllmul = (2 * self.sysclk.unwrap_or(HSI)) / HSI;
        let pllmul = cmp::min(cmp::max(pllmul, 2), 16);
        let pllmul_bits = if pllmul == 2 {
            None
        } else {
            Some(pllmul as u8 - 2)
        };

        let sysclk = pllmul * HSI / 2;

        assert!(sysclk <= 72_000_000);

        let hpre_bits = self
            .hclk
            .map(|hclk| match sysclk / hclk {
                0 => unreachable!(),
                1 => 0b0111,
                2 => 0b1000,
                3...5 => 0b1001,
                6...11 => 0b1010,
                12...39 => 0b1011,
                40...95 => 0b1100,
                96...191 => 0b1101,
                192...383 => 0b1110,
                _ => 0b1111,
            }).unwrap_or(0b0111);

        let hclk = sysclk / (1 << (hpre_bits - 0b0111));

        assert!(hclk <= 72_000_000);

        let ppre1_bits = self
            .pclk1
            .map(|pclk1| match hclk / pclk1 {
                0 => unreachable!(),
                1 => 0b011,
                2 => 0b100,
                3...5 => 0b101,
                6...11 => 0b110,
                _ => 0b111,
            }).unwrap_or(0b011);

        let ppre1 = 1 << (ppre1_bits - 0b011);
        let pclk1 = hclk / u32(ppre1);

        assert!(pclk1 <= 45_000_000);

        let ppre2_bits = self
            .pclk2
            .map(|pclk2| match hclk / pclk2 {
                0 => unreachable!(),
                1 => 0b011,
                2 => 0b100,
                3...5 => 0b101,
                6...11 => 0b110,
                _ => 0b111,
            }).unwrap_or(0b011);

        let ppre2 = 1 << (ppre2_bits - 0b011);
        let pclk2 = hclk / u32(ppre2);

        assert!(pclk2 <= 90_000_000);

        // adjust flash wait states
        acr.acr().write(|w| {
            w.latency().bits(if sysclk <= 24_000_000 {
                0b000
            } else if sysclk <= 48_000_000 {
                0b001
            } else {
                0b010
            })
        });

        let rcc = unsafe { &*RCC::ptr() };
        if let Some(pllmul_bits) = pllmul_bits {
            // use PLL as source
            rcc.cfgr
                .modify(|_, w| unsafe { w.hpre().bits(pllmul_bits) });
            // rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) });

            // Enable PLL
            rcc.cr.write(|w| w.pllon().set_bit());

            while rcc.cr.read().pllrdy().bit_is_clear() {}

            // SW: PLL selected as system clock
            rcc.cfgr.modify(|_, w| unsafe {
                w.ppre2()
                    .bits(ppre2_bits)
                    .ppre1()
                    .bits(ppre1_bits)
                    .hpre()
                    .bits(hpre_bits)
                    .sw()
                    .bits(0b10)
            });
        } else {
            // use HSI as source

            // SW: HSI selected as system clock
            rcc.cfgr.write(|w| unsafe {
                w.ppre2()
                    .bits(ppre2_bits)
                    .ppre1()
                    .bits(ppre1_bits)
                    .hpre()
                    .bits(hpre_bits)
                    .sw()
                    .bits(0b00)
            });
        }

        Clocks {
            hclk: Hertz(hclk),
            pclk1: Hertz(pclk1),
            pclk2: Hertz(pclk2),
            ppre1,
            ppre2,
            sysclk: Hertz(sysclk),
        }
    }
/// Freezes the clock configuration, making it effective
/// TODO - this needs work
Freezes the clock configuration, making it effective
TODO - this needs work
Freezes the clock configuration making it effective TODO - this needs work
pub fn freeze(self, acr: &mut ACR) -> Clocks {
        let pllmul = (2 * self.sysclk.unwrap_or(HSI)) / HSI;
        let pllmul = cmp::min(cmp::max(pllmul, 2), 16);
        let pllmul_bits = if pllmul == 2 {
            None
        } else {
            Some(pllmul as u8 - 2)
        };
        let sysclk = pllmul * HSI / 2;
        assert!(sysclk <= 72_000_000);
        let hpre_bits = self
            .hclk
            .map(|hclk| match sysclk / hclk {
                0 => unreachable!(),
                1 => 0b0111,
                2 => 0b1000,
                3...5 => 0b1001,
                6...11 => 0b1010,
                12...39 => 0b1011,
                40...95 => 0b1100,
                96...191 => 0b1101,
                192...383 => 0b1110,
                _ => 0b1111,
            }).unwrap_or(0b0111);
        let hclk = sysclk / (1 << (hpre_bits - 0b0111));
        assert!(hclk <= 72_000_000);
        let ppre1_bits = self
            .pclk1
            .map(|pclk1| match hclk / pclk1 {
                0 => unreachable!(),
                1 => 0b011,
                2 => 0b100,
                3...5 => 0b101,
                6...11 => 0b110,
                _ => 0b111,
            }).unwrap_or(0b011);
        let ppre1 = 1 << (ppre1_bits - 0b011);
        let pclk1 = hclk / u32(ppre1);
        assert!(pclk1 <= 45_000_000);
        let ppre2_bits = self
            .pclk2
            .map(|pclk2| match hclk / pclk2 {
                0 => unreachable!(),
                1 => 0b011,
                2 => 0b100,
                3...5 => 0b101,
                6...11 => 0b110,
                _ => 0b111,
            }).unwrap_or(0b011);
        let ppre2 = 1 << (ppre2_bits - 0b011);
        let pclk2 = hclk / u32(ppre2);
        assert!(pclk2 <= 90_000_000);
        // adjust flash wait states
        acr.acr().write(|w| {
            w.latency().bits(if sysclk <= 24_000_000 {
                0b000
            } else if sysclk <= 48_000_000 {
                0b001
            } else {
                0b010
            })
        });
        let rcc = unsafe { &*RCC::ptr() };
        if let Some(pllmul_bits) = pllmul_bits {
            // use PLL as source
            rcc.cfgr
                .modify(|_, w| unsafe { w.hpre().bits(pllmul_bits) });
            // rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) });
            // Enable PLL
            rcc.cr.write(|w| w.pllon().set_bit());
            while rcc.cr.read().pllrdy().bit_is_clear() {}
            // SW: PLL selected as system clock
            rcc.cfgr.modify(|_, w| unsafe {
                w.ppre2()
                    .bits(ppre2_bits)
                    .ppre1()
                    .bits(ppre1_bits)
                    .hpre()
                    .bits(hpre_bits)
                    .sw()
                    .bits(0b10)
            });
        } else {
            // use HSI as source
            // SW: HSI selected as system clock
            rcc.cfgr.write(|w| unsafe {
                w.ppre2()
                    .bits(ppre2_bits)
                    .ppre1()
                    .bits(ppre1_bits)
                    .hpre()
                    .bits(hpre_bits)
                    .sw()
                    .bits(0b00)
            });
        }
        Clocks {
            hclk: Hertz(hclk),
            pclk1: Hertz(pclk1),
            pclk2: Hertz(pclk2),
            ppre1,
            ppre2,
            sysclk: Hertz(sysclk),
        }
    }
pub fn freeze ( self , acr : & mut ACR ) -> Clocks { let pllmul = ( 2 * self . sysclk . unwrap_or ( HSI ) ) / HSI ; let pllmul = cmp :: min ( cmp :: max ( pllmul , 2 ) , 16 ) ; let pllmul_bits = if pllmul == 2 { None } else { Some ( pllmul as u8 - 2 ) } ; let sysclk = pllmul * HSI / 2 ; assert ! ( sysclk 72_000_000 ) ; let hpre_bits = self . hclk . map ( | hclk | match sysclk / hclk { 0 => unreachable ! ( ) , 1 => 0b0111 , 2 => 0b1000 , 3 ... 5 => 0b1001 , 6 ... 11 => 0b1010 , 12 ... 39 => 0b1011 , 40 ... 95 => 0b1100 , 96 ... 191 => 0b1101 , 192 ... 383 => 0b1110 , _ => 0b1111 , } ) . unwrap_or ( 0b0111 ) ; let hclk = sysclk / ( 1 << ( hpre_bits - 0b0111 ) ) ; assert ! ( hclk 72_000_000 ) ; let ppre1_bits = self . pclk1 . map ( | pclk1 | match hclk / pclk1 { 0 => unreachable ! ( ) , 1 => 0b011 , 2 => 0b100 , 3 ... 5 => 0b101 , 6 ... 11 => 0b110 , _ => 0b111 , } ) . unwrap_or ( 0b011 ) ; let ppre1 = 1 << ( ppre1_bits - 0b011 ) ; let pclk1 = hclk / u32 ( ppre1 ) ; assert ! ( pclk1 45_000_000 ) ; let ppre2_bits = self . pclk2 . map ( | pclk2 | match hclk / pclk2 { 0 => unreachable ! ( ) , 1 => 0b011 , 2 => 0b100 , 3 ... 5 => 0b101 , 6 ... 11 => 0b110 , _ => 0b111 , } ) . unwrap_or ( 0b011 ) ; let ppre2 = 1 << ( ppre2_bits - 0b011 ) ; let pclk2 = hclk / u32 ( ppre2 ) ; assert ! ( pclk2 90_000_000 ) ; // adjust flash wait states acr . acr ( ) . write ( | w | { w . latency ( ) . bits ( if sysclk <= 24_000_000 { 0b000 } else if sysclk <= 48_000_000 { 0b001 } else { 0b010 } ) } ) ; let rcc = unsafe { & * RCC :: ptr ( ) } ; if let Some ( pllmul_bits ) = pllmul_bits { // use PLL as source rcc . cfgr . modify ( | _ , w | unsafe { w . hpre ( ) . bits ( pllmul_bits ) } ) ; // rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) }); // Enable PLL rcc . cr . write ( | w | w . pllon ( ) . set_bit ( ) ) ; while rcc . cr . read ( ) . pllrdy ( ) . bit_is_clear ( ) { } // SW: PLL selected as system clock rcc . cfgr . modify ( | _ , w | unsafe { w . ppre2 ( ) . bits ( ppre2_bits ) . ppre1 ( ) . bits ( ppre1_bits ) . hpre ( ) . bits ( hpre_bits ) . sw ( ) . bits ( 0b10 ) } ) ; } else { // use HSI as source // SW: HSI selected as system clock rcc . cfgr . write ( | w | unsafe { w . ppre2 ( ) . bits ( ppre2_bits ) . ppre1 ( ) . bits ( ppre1_bits ) . hpre ( ) . bits ( hpre_bits ) . sw ( ) . bits ( 0b00 ) } ) ; } Clocks { hclk : Hertz ( hclk ) , pclk1 : Hertz ( pclk1 ) , pclk2 : Hertz ( pclk2 ) , ppre1 , ppre2 , sysclk : Hertz ( sysclk ) , } }
Freezes the clock configuration, making it effective
TODO - this needs work
Freezes the clock configuration making it effective TODO - this needs work
self
acr
&mut ACR
self
acr
&mut ACR