fn add16(ctx: &mut impl CpuContext, arg: Operand16) {
    // 16 bit add never modifies the zero flag.
    const MASK: Flags = Flags::all().difference(Flags::ZERO);

    let lhs = ctx.cpustate().regs.hl();
    let rhs = arg.read(ctx); // This will always be a register in practice.

    let mut flags = Flags::empty();
    if (lhs & 0x7ff) + (rhs & 0x7ff) > 0x7ff {
        flags |= Flags::HALFCARRY;
    }
    let (res, carry) = lhs.overflowing_add(rhs);
    flags |= Flags::check_carry(carry);

    ctx.cpustate_mut().regs.set_hl(res);
    ctx.cpustate_mut().regs.flags.merge(flags, MASK);
}
/// Implements 16 bit register add into HL. Never sets the zero flag and clears the subtract flag,
/// but does set carry and half-carry based on the upper byte of the operation (as if it was
/// performed by running the pseudo-instructions `add l,<arg-low>; adc h,<arg-high>`.
Implements 16 bit register add into HL. Never sets the zero flag and clears the subtract flag,
but does set carry and half-carry based on the upper byte of the operation (as if it was
performed by running the pseudo-instructions `add l,; adc h,`.
Implements 16 bit register add into HL . Never sets the zero flag and clears the subtract flag but does set carry and half - carry based on the upper byte of the operation ( as if it was performed by running the pseudo - instructions ` add l ; adc h ` .
fn add16(ctx: &mut impl CpuContext, arg: Operand16) {
    // 16 bit add never modifies the zero flag.
    const MASK: Flags = Flags::all().difference(Flags::ZERO);
    let lhs = ctx.cpustate().regs.hl();
    let rhs = arg.read(ctx); // This will always be a register in practice.
    let mut flags = Flags::empty();
    if (lhs & 0x7ff) + (rhs & 0x7ff) > 0x7ff {
        flags |= Flags::HALFCARRY;
    }
    let (res, carry) = lhs.overflowing_add(rhs);
    flags |= Flags::check_carry(carry);
    ctx.cpustate_mut().regs.set_hl(res);
    ctx.cpustate_mut().regs.flags.merge(flags, MASK);
}
fn add16 ( ctx : & mut impl CpuContext , arg : Operand16 ) { // 16 bit add never modifies the zero flag. const MASK : Flags = Flags :: all ( ) . difference ( Flags :: ZERO ) ; let lhs = ctx . cpustate ( ) . regs . hl ( ) ; let rhs = arg . read ( ctx ) ; // This will always be a register in practice. let mut flags = Flags :: empty ( ) ; if ( lhs & 0x7ff ) + ( rhs & 0x7ff ) > 0x7ff { flags |= Flags :: HALFCARRY ; } let ( res , carry ) = lhs . overflowing_add ( rhs ) ; flags |= Flags :: check_carry ( carry ) ; ctx . cpustate_mut ( ) . regs . set_hl ( res ) ; ctx . cpustate_mut ( ) . regs . flags . merge ( flags , MASK ) ; }
Implements 16 bit register add into HL.
Implements 16 bit register add into HL .
ctx
&mut impl CpuContext
arg
Operand16
ctx
&mut impl CpuContext
arg
Operand16