pub fn release(&mut self) {
        let x = self.rdidx;
        assert!(self.rd[x].rdes3 & EMAC_DES3_OWN == 0); // Owned by us

        let address = ptr::addr_of!(self.rbuf[x]) as u32;

        // Read format
        self.rd[x].rdes0 = address; // Buffer 1
        self.rd[x].rdes1 = 0; // Reserved
        self.rd[x].rdes2 = 0; // Marked as invalid
        self.rd[x].rdes3 = 0;
        self.rd[x].rdes3 |= EMAC_DES3_OWN; // Give the DMA engine ownership
        self.rd[x].rdes3 |= EMAC_RDES3_BUF1V; // BUF1V: 1st buffer address is valid
        self.rd[x].rdes3 |= EMAC_RDES3_IOC; // IOC: Interrupt on complete

        // Ensure changes to the descriptor are committed before
        // DMA engine sees tail pointer store
        cortex_m::asm::dsb();

        // Move the tail pointer (TPR) to this descriptor
        unsafe {
            let dma = &*stm32::ETHERNET_DMA::ptr();
            dma.dmacrx_dtpr
                .write(|w| w.bits(&(self.rd[x]) as *const _ as u32));
        }

        // Update active descriptor
        self.rdidx = (x + 1) % RD;
    }
/// Release the next RDes to the DMA engine
Release the next RDes to the DMA engine
Release the next RDes to the DMA engine
pub fn release(&mut self) {
        let x = self.rdidx;
        assert!(self.rd[x].rdes3 & EMAC_DES3_OWN == 0); // Owned by us
        let address = ptr::addr_of!(self.rbuf[x]) as u32;
        // Read format
        self.rd[x].rdes0 = address; // Buffer 1
        self.rd[x].rdes1 = 0; // Reserved
        self.rd[x].rdes2 = 0; // Marked as invalid
        self.rd[x].rdes3 = 0;
        self.rd[x].rdes3 |= EMAC_DES3_OWN; // Give the DMA engine ownership
        self.rd[x].rdes3 |= EMAC_RDES3_BUF1V; // BUF1V: 1st buffer address is valid
        self.rd[x].rdes3 |= EMAC_RDES3_IOC; // IOC: Interrupt on complete
        // Ensure changes to the descriptor are committed before
        // DMA engine sees tail pointer store
        cortex_m::asm::dsb();
        // Move the tail pointer (TPR) to this descriptor
        unsafe {
            let dma = &*stm32::ETHERNET_DMA::ptr();
            dma.dmacrx_dtpr
                .write(|w| w.bits(&(self.rd[x]) as *const _ as u32));
        }
        // Update active descriptor
        self.rdidx = (x + 1) % RD;
    }
pub fn release ( & mut self ) { let x = self . rdidx ; assert ! ( self rd [ x ] rdes3 EMAC_DES3_OWN 0 ) ; // Owned by us let address = ptr :: addr_of ! ( self rbuf [ x ] ) as u32 ; // Read format self . rd [ x ] . rdes0 = address ; // Buffer 1 self . rd [ x ] . rdes1 = 0 ; // Reserved self . rd [ x ] . rdes2 = 0 ; // Marked as invalid self . rd [ x ] . rdes3 = 0 ; self . rd [ x ] . rdes3 |= EMAC_DES3_OWN ; // Give the DMA engine ownership self . rd [ x ] . rdes3 |= EMAC_RDES3_BUF1V ; // BUF1V: 1st buffer address is valid self . rd [ x ] . rdes3 |= EMAC_RDES3_IOC ; // IOC: Interrupt on complete // Ensure changes to the descriptor are committed before // DMA engine sees tail pointer store cortex_m :: asm :: dsb ( ) ; // Move the tail pointer (TPR) to this descriptor unsafe { let dma = & * stm32 :: ETHERNET_DMA :: ptr ( ) ; dma . dmacrx_dtpr . write ( | w | w . bits ( & ( self . rd [ x ] ) as * const _ as u32 ) ) ; } // Update active descriptor self . rdidx = ( x + 1 ) % RD ; }
Release the next RDes to the DMA engine
Release the next RDes to the DMA engine
&mut self
&mut self