pub(super) fn write(self, ctx: &mut impl CpuContext, val: u16) {
        trace!("Operand16::write {} -> {}", val, self);
        match self {
            Self::BC => ctx.cpustate_mut().regs.set_bc(val),
            Self::DE => ctx.cpustate_mut().regs.set_de(val),
            Self::HL => ctx.cpustate_mut().regs.set_hl(val),
            Self::AF => ctx.cpustate_mut().regs.set_af(val),
            Self::Sp => ctx.cpustate_mut().regs.sp = val,
            Self::Immediate => panic!("Immediates cannot be used as store destinations"),
            Self::AddrImmediate => {
                let [low, high] = val.to_le_bytes();
                let mut addr = Wrapping(Self::Immediate.read(ctx));
                ctx.yield1m();
                ctx.mem_mut().write(addr.0.into(), low);
                addr += Wrapping(1u16);
                ctx.yield1m();
                ctx.mem_mut().write(addr.0.into(), high);
            }
        }
    }
/// Write this operand to the CPU context, yielding for memory access if needed.
Write this operand to the CPU context, yielding for memory access if needed.
Write this operand to the CPU context yielding for memory access if needed .
pub(super) fn write(self, ctx: &mut impl CpuContext, val: u16) {
        trace!("Operand16::write {} -> {}", val, self);
        match self {
            Self::BC => ctx.cpustate_mut().regs.set_bc(val),
            Self::DE => ctx.cpustate_mut().regs.set_de(val),
            Self::HL => ctx.cpustate_mut().regs.set_hl(val),
            Self::AF => ctx.cpustate_mut().regs.set_af(val),
            Self::Sp => ctx.cpustate_mut().regs.sp = val,
            Self::Immediate => panic!("Immediates cannot be used as store destinations"),
            Self::AddrImmediate => {
                let [low, high] = val.to_le_bytes();
                let mut addr = Wrapping(Self::Immediate.read(ctx));
                ctx.yield1m();
                ctx.mem_mut().write(addr.0.into(), low);
                addr += Wrapping(1u16);
                ctx.yield1m();
                ctx.mem_mut().write(addr.0.into(), high);
            }
        }
    }
pub ( super ) fn write ( self , ctx : & mut impl CpuContext , val : u16 ) { trace ! ( " " val self ) ; match self { Self :: BC => ctx . cpustate_mut ( ) . regs . set_bc ( val ) , Self :: DE => ctx . cpustate_mut ( ) . regs . set_de ( val ) , Self :: HL => ctx . cpustate_mut ( ) . regs . set_hl ( val ) , Self :: AF => ctx . cpustate_mut ( ) . regs . set_af ( val ) , Self :: Sp => ctx . cpustate_mut ( ) . regs . sp = val , Self :: Immediate => panic ! ( " " ) , Self :: AddrImmediate => { let [ low , high ] = val . to_le_bytes ( ) ; let mut addr = Wrapping ( Self :: Immediate . read ( ctx ) ) ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . 0 . into ( ) , low ) ; addr += Wrapping ( 1u16 ) ; ctx . yield1m ( ) ; ctx . mem_mut ( ) . write ( addr . 0 . into ( ) , high ) ; } } }
Write this operand to the CPU context, yielding for memory access if needed.
Write this operand to the CPU context yielding for memory access if needed .
self
ctx
&mut impl CpuContext
val
u16
self
ctx
&mut impl CpuContext
val
u16