pub fn with_internal_8mhz(
        gclk: GCLK,
        pm: &mut PM,
        sysctrl: &mut SYSCTRL,
        nvmctrl: &mut NVMCTRL,
    ) -> Self {
        let mut state = State { gclk };

        // No wait states needed <= 24 MHz @ 3.3v (ref. 37.12 NVM characteristics)
        #[cfg(feature = "samd21")]
        set_flash_manual_write(nvmctrl);

        // Get rid of unused warning
        #[cfg(not(feature = "samd21"))]
        let _ = nvmctrl;

        enable_gclk_apb(pm);

        state.reset_gclk();

        // Enable 8 MHz source -> GCLK0
        state.set_gclk_divider_and_source(GCLK0, 1, OSC8M, false);

        // Reset various dividers back to 1
        sysctrl.osc8m.modify(|_, w| {
            w.presc()._0();
            w.ondemand().clear_bit()
        });
        pm.cpusel.write(|w| w.cpudiv().div1());
        pm.apbasel.write(|w| w.apbadiv().div1());
        pm.apbbsel.write(|w| w.apbbdiv().div1());
        pm.apbcsel.write(|w| w.apbcdiv().div1());

        Self {
            state,
            gclks: [
                OSC8M_FREQ,
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
            ],
            used_clocks: 0,
        }
    }
/// Reset the clock controller, configure the system to run at 8Mhz from
/// internal 8 MHz RC clock (no PLL) and reset various clock dividers.
Reset the clock controller, configure the system to run at 8Mhz from
internal 8 MHz RC clock (no PLL) and reset various clock dividers.
Reset the clock controller configure the system to run at 8Mhz from internal 8 MHz RC clock ( no PLL ) and reset various clock dividers .
pub fn with_internal_8mhz(
        gclk: GCLK,
        pm: &mut PM,
        sysctrl: &mut SYSCTRL,
        nvmctrl: &mut NVMCTRL,
    ) -> Self {
        let mut state = State { gclk };
        // No wait states needed <= 24 MHz @ 3.3v (ref. 37.12 NVM characteristics)
        #[cfg(feature = "samd21")]
        set_flash_manual_write(nvmctrl);
        // Get rid of unused warning
        #[cfg(not(feature = "samd21"))]
        let _ = nvmctrl;
        enable_gclk_apb(pm);
        state.reset_gclk();
        // Enable 8 MHz source -> GCLK0
        state.set_gclk_divider_and_source(GCLK0, 1, OSC8M, false);
        // Reset various dividers back to 1
        sysctrl.osc8m.modify(|_, w| {
            w.presc()._0();
            w.ondemand().clear_bit()
        });
        pm.cpusel.write(|w| w.cpudiv().div1());
        pm.apbasel.write(|w| w.apbadiv().div1());
        pm.apbbsel.write(|w| w.apbbdiv().div1());
        pm.apbcsel.write(|w| w.apbcdiv().div1());
        Self {
            state,
            gclks: [
                OSC8M_FREQ,
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
                Hertz(0),
            ],
            used_clocks: 0,
        }
    }
pub fn with_internal_8mhz ( gclk : GCLK , pm : & mut PM , sysctrl : & mut SYSCTRL , nvmctrl : & mut NVMCTRL , ) -> Self { let mut state = State { gclk } ; // No wait states needed <= 24 MHz @ 3.3v (ref. 37.12 NVM characteristics) # [ cfg ( feature " " ) ] set_flash_manual_write ( nvmctrl ) ; // Get rid of unused warning # [ cfg ( not ( feature " " ) ) ] let _ = nvmctrl ; enable_gclk_apb ( pm ) ; state . reset_gclk ( ) ; // Enable 8 MHz source -> GCLK0 state . set_gclk_divider_and_source ( GCLK0 , 1 , OSC8M , false ) ; // Reset various dividers back to 1 sysctrl . osc8m . modify ( | _ , w | { w . presc ( ) . _0 ( ) ; w . ondemand ( ) . clear_bit ( ) } ) ; pm . cpusel . write ( | w | w . cpudiv ( ) . div1 ( ) ) ; pm . apbasel . write ( | w | w . apbadiv ( ) . div1 ( ) ) ; pm . apbbsel . write ( | w | w . apbbdiv ( ) . div1 ( ) ) ; pm . apbcsel . write ( | w | w . apbcdiv ( ) . div1 ( ) ) ; Self { state , gclks : [ OSC8M_FREQ , Hertz ( 0 ) , Hertz ( 0 ) , Hertz ( 0 ) , Hertz ( 0 ) , Hertz ( 0 ) , Hertz ( 0 ) , Hertz ( 0 ) , ] , used_clocks : 0 , } }
Reset the clock controller, configure the system to run at 8Mhz from
internal 8 MHz RC clock (no PLL) and reset various clock dividers.
Reset the clock controller configure the system to run at 8Mhz from internal 8 MHz RC clock ( no PLL ) and reset various clock dividers .
gclk
GCLK
pm
&mut PM
sysctrl
&mut SYSCTRL
nvmctrl
&mut NVMCTRL
gclk
GCLK
pm
&mut PM
sysctrl
&mut SYSCTRL
nvmctrl
&mut NVMCTRL