fn into_pre_div(div: u8) -> cfgr2::PREDIV_A {
    match div {
        1 => cfgr2::PREDIV_A::DIV1,
        2 => cfgr2::PREDIV_A::DIV2,
        3 => cfgr2::PREDIV_A::DIV3,
        4 => cfgr2::PREDIV_A::DIV4,
        5 => cfgr2::PREDIV_A::DIV5,
        6 => cfgr2::PREDIV_A::DIV6,
        7 => cfgr2::PREDIV_A::DIV7,
        8 => cfgr2::PREDIV_A::DIV8,
        9 => cfgr2::PREDIV_A::DIV9,
        10 => cfgr2::PREDIV_A::DIV10,
        11 => cfgr2::PREDIV_A::DIV11,
        12 => cfgr2::PREDIV_A::DIV12,
        13 => cfgr2::PREDIV_A::DIV13,
        14 => cfgr2::PREDIV_A::DIV14,
        15 => cfgr2::PREDIV_A::DIV15,
        16 => cfgr2::PREDIV_A::DIV16,
        _ => unreachable!(),
    }
}
/// Convert pll divisor into equivalent register field type
Convert pll divisor into equivalent register field type
Convert pll divisor into equivalent register field type
fn into_pre_div(div: u8) -> cfgr2::PREDIV_A {
    match div {
        1 => cfgr2::PREDIV_A::DIV1,
        2 => cfgr2::PREDIV_A::DIV2,
        3 => cfgr2::PREDIV_A::DIV3,
        4 => cfgr2::PREDIV_A::DIV4,
        5 => cfgr2::PREDIV_A::DIV5,
        6 => cfgr2::PREDIV_A::DIV6,
        7 => cfgr2::PREDIV_A::DIV7,
        8 => cfgr2::PREDIV_A::DIV8,
        9 => cfgr2::PREDIV_A::DIV9,
        10 => cfgr2::PREDIV_A::DIV10,
        11 => cfgr2::PREDIV_A::DIV11,
        12 => cfgr2::PREDIV_A::DIV12,
        13 => cfgr2::PREDIV_A::DIV13,
        14 => cfgr2::PREDIV_A::DIV14,
        15 => cfgr2::PREDIV_A::DIV15,
        16 => cfgr2::PREDIV_A::DIV16,
        _ => unreachable!(),
    }
}
fn into_pre_div ( div : u8 ) -> cfgr2 :: PREDIV_A { match div { 1 => cfgr2 :: PREDIV_A :: DIV1 , 2 => cfgr2 :: PREDIV_A :: DIV2 , 3 => cfgr2 :: PREDIV_A :: DIV3 , 4 => cfgr2 :: PREDIV_A :: DIV4 , 5 => cfgr2 :: PREDIV_A :: DIV5 , 6 => cfgr2 :: PREDIV_A :: DIV6 , 7 => cfgr2 :: PREDIV_A :: DIV7 , 8 => cfgr2 :: PREDIV_A :: DIV8 , 9 => cfgr2 :: PREDIV_A :: DIV9 , 10 => cfgr2 :: PREDIV_A :: DIV10 , 11 => cfgr2 :: PREDIV_A :: DIV11 , 12 => cfgr2 :: PREDIV_A :: DIV12 , 13 => cfgr2 :: PREDIV_A :: DIV13 , 14 => cfgr2 :: PREDIV_A :: DIV14 , 15 => cfgr2 :: PREDIV_A :: DIV15 , 16 => cfgr2 :: PREDIV_A :: DIV16 , _ => unreachable ! ( ) , } }
Convert pll divisor into equivalent register field type
Convert pll divisor into equivalent register field type
div
u8
div
u8