fn vco_setup_iterative() {
        let rcc = MockRcc::new();

        let pllsrc = 25_000_000; // PLL source frequency eg. 25MHz crystal
        let pll_p_target = 240_000_000; // PLL output frequency (P_CK)
        let pll_q_target = 120_000_000; // PLL output frequency (Q_CK)
        let pll_r_target = 30_000_000; // PLL output frequency (R_CK)
        println!(
            "PLL2/3 {} MHz -> {} MHz",
            pllsrc as f32 / 1e6,
            pll_p_target as f32 / 1e6
        );

        // ----------------------------------------

        // VCO Setup
        println!("ITERATIVE");
        let (ref_x_ck, pll_x_m, pll_x_p, vco_ck_target) = vco_setup! {
            ITERATIVE: pllsrc, pll_p_target, rcc, vcosel, pllrge
        };
        // Feedback divider. Integer only
        let pll_x_n = vco_ck_target / ref_x_ck;
        // Resulting achieved vco_ck
        let vco_ck_achieved = calc_vco_ck(ref_x_ck, pll_x_n, 0);
        // {Q,R} output clocks
        let pll_x_q = calc_ck_div(
            PllConfigStrategy::Iterative,
            vco_ck_target,
            pll_q_target,
        );
        let pll_x_r = calc_ck_div(
            PllConfigStrategy::Iterative,
            vco_ck_target,
            pll_r_target,
        );

        // ----------------------------------------

        // Input
        println!("M Divider {}", pll_x_m);
        let input = pllsrc as f32 / pll_x_m as f32;
        println!("==> Input {} MHz", input / 1e6);
        println!();
        assert_eq!(input, 5e6);

        println!("VCO CK Target {} MHz", vco_ck_target as f32 / 1e6);
        println!("VCO CK Achieved {} MHz", pll_x_n as f32 * input / 1e6);
        println!();

        // Output
        println!("P Divider {}", pll_x_p);
        let output_p = pll_x_n as f32 * input / pll_x_p as f32;
        println!("==> Output P {} MHz", output_p / 1e6);
        println!();
        assert_eq!(output_p, 240e6);

        let output_q = vco_ck_achieved as f32 / pll_x_q as f32;
        println!("Q Divider {}", pll_x_q);
        println!("==> Output Q {} MHz", output_q / 1e6);
        println!();
        assert_eq!(output_q, pll_q_target as f32);

        let output_r = vco_ck_achieved as f32 / pll_x_r as f32;
        println!("R Divider {}", pll_x_r);
        println!("==> Output R {} MHz", output_r / 1e6);
        println!();
        assert_eq!(output_r, pll_r_target as f32);
    }
/// Test PFD input frequency PLL and VCO output frequency
Test PFD input frequency PLL and VCO output frequency
Test PFD input frequency PLL and VCO output frequency
fn vco_setup_iterative() {
        let rcc = MockRcc::new();
        let pllsrc = 25_000_000; // PLL source frequency eg. 25MHz crystal
        let pll_p_target = 240_000_000; // PLL output frequency (P_CK)
        let pll_q_target = 120_000_000; // PLL output frequency (Q_CK)
        let pll_r_target = 30_000_000; // PLL output frequency (R_CK)
        println!(
            "PLL2/3 {} MHz -> {} MHz",
            pllsrc as f32 / 1e6,
            pll_p_target as f32 / 1e6
        );
        // ----------------------------------------
        // VCO Setup
        println!("ITERATIVE");
        let (ref_x_ck, pll_x_m, pll_x_p, vco_ck_target) = vco_setup! {
            ITERATIVE: pllsrc, pll_p_target, rcc, vcosel, pllrge
        };
        // Feedback divider. Integer only
        let pll_x_n = vco_ck_target / ref_x_ck;
        // Resulting achieved vco_ck
        let vco_ck_achieved = calc_vco_ck(ref_x_ck, pll_x_n, 0);
        // {Q,R} output clocks
        let pll_x_q = calc_ck_div(
            PllConfigStrategy::Iterative,
            vco_ck_target,
            pll_q_target,
        );
        let pll_x_r = calc_ck_div(
            PllConfigStrategy::Iterative,
            vco_ck_target,
            pll_r_target,
        );
        // ----------------------------------------
        // Input
        println!("M Divider {}", pll_x_m);
        let input = pllsrc as f32 / pll_x_m as f32;
        println!("==> Input {} MHz", input / 1e6);
        println!();
        assert_eq!(input, 5e6);
        println!("VCO CK Target {} MHz", vco_ck_target as f32 / 1e6);
        println!("VCO CK Achieved {} MHz", pll_x_n as f32 * input / 1e6);
        println!();
        // Output
        println!("P Divider {}", pll_x_p);
        let output_p = pll_x_n as f32 * input / pll_x_p as f32;
        println!("==> Output P {} MHz", output_p / 1e6);
        println!();
        assert_eq!(output_p, 240e6);
        let output_q = vco_ck_achieved as f32 / pll_x_q as f32;
        println!("Q Divider {}", pll_x_q);
        println!("==> Output Q {} MHz", output_q / 1e6);
        println!();
        assert_eq!(output_q, pll_q_target as f32);
        let output_r = vco_ck_achieved as f32 / pll_x_r as f32;
        println!("R Divider {}", pll_x_r);
        println!("==> Output R {} MHz", output_r / 1e6);
        println!();
        assert_eq!(output_r, pll_r_target as f32);
    }
fn vco_setup_iterative ( ) { let rcc = MockRcc :: new ( ) ; let pllsrc = 25_000_000 ; // PLL source frequency eg. 25MHz crystal let pll_p_target = 240_000_000 ; // PLL output frequency (P_CK) let pll_q_target = 120_000_000 ; // PLL output frequency (Q_CK) let pll_r_target = 30_000_000 ; // PLL output frequency (R_CK) println ! ( " " pllsrc as f32 1e6 pll_p_target as f32 1e6 ) ; // ---------------------------------------- // VCO Setup println ! ( " " ) ; let ( ref_x_ck , pll_x_m , pll_x_p , vco_ck_target ) = vco_setup ! { ITERATIVE pllsrc pll_p_target rcc vcosel pllrge } ; // Feedback divider. Integer only let pll_x_n = vco_ck_target / ref_x_ck ; // Resulting achieved vco_ck let vco_ck_achieved = calc_vco_ck ( ref_x_ck , pll_x_n , 0 ) ; // {Q,R} output clocks let pll_x_q = calc_ck_div ( PllConfigStrategy :: Iterative , vco_ck_target , pll_q_target , ) ; let pll_x_r = calc_ck_div ( PllConfigStrategy :: Iterative , vco_ck_target , pll_r_target , ) ; // ---------------------------------------- // Input println ! ( " " pll_x_m ) ; let input = pllsrc as f32 / pll_x_m as f32 ; println ! ( " " input 1e6 ) ; println ! ( ) ; assert_eq ! ( input 5e6 ) ; println ! ( " " vco_ck_target as f32 1e6 ) ; println ! ( " " pll_x_n as f32 input 1e6 ) ; println ! ( ) ; // Output println ! ( " " pll_x_p ) ; let output_p = pll_x_n as f32 * input / pll_x_p as f32 ; println ! ( " " output_p 1e6 ) ; println ! ( ) ; assert_eq ! ( output_p 240e6 ) ; let output_q = vco_ck_achieved as f32 / pll_x_q as f32 ; println ! ( " " pll_x_q ) ; println ! ( " " output_q 1e6 ) ; println ! ( ) ; assert_eq ! ( output_q pll_q_target as f32 ) ; let output_r = vco_ck_achieved as f32 / pll_x_r as f32 ; println ! ( " " pll_x_r ) ; println ! ( " " output_r 1e6 ) ; println ! ( ) ; assert_eq ! ( output_r pll_r_target as f32 ) ; }
Test PFD input frequency PLL and VCO output frequency
Test PFD input frequency PLL and VCO output frequency