pub fn new(
        mclk: &mut MCLK,
        qspi: QSPI,
        _sck: impl AnyPin<Id = PB10>,
        _cs: impl AnyPin<Id = PB11>,
        _io0: impl AnyPin<Id = PA08>,
        _io1: impl AnyPin<Id = PA09>,
        _io2: impl AnyPin<Id = PA10>,
        _io3: impl AnyPin<Id = PA11>,
    ) -> Qspi<OneShot> {
        mclk.apbcmask.modify(|_, w| w.qspi_().set_bit());
        // Enable the clocks for the qspi peripheral in single data rate mode.
        mclk.ahbmask.modify(|_, w| {
            w.qspi_().set_bit();
            w.qspi_2x_().clear_bit()
        });

        let _sck = _sck.into().into_alternate();
        let _cs = _cs.into().into_alternate();
        let _io0 = _io0.into().into_alternate();
        let _io1 = _io1.into().into_alternate();
        let _io2 = _io2.into().into_alternate();
        let _io3 = _io3.into().into_alternate();

        qspi.ctrla.write(|w| w.swrst().set_bit());
        qspi.baud.write(|w| unsafe {
            // TODO get system clock value instead of hardcoding
            //(120_000_000u32 / 4_000_000u32) = 30 = BAUD + 1
            // BAUD = 29
            w.baud().bits(29); // 4Mhz
                               // SPI MODE 0
            w.cpol().clear_bit();
            w.cpha().clear_bit()
        });

        qspi.ctrlb.write(|w| {
            w.mode().memory();
            w.csmode().noreload();
            w.csmode().lastxfer();
            w.datalen()._8bits()
        });

        qspi.ctrla.modify(|_, w| w.enable().set_bit());

        Self {
            qspi,
            _sck,
            _cs,
            _io0,
            _io1,
            _io2,
            _io3,
            _mode: PhantomData,
        }
    }
/// Enable the clocks for the qspi peripheral in single data rate mode
/// assuming 120mhz system clock, for 4mhz spi mode 0 operation.
Enable the clocks for the qspi peripheral in single data rate mode
assuming 120mhz system clock, for 4mhz spi mode 0 operation.
Enable the clocks for the qspi peripheral in single data rate mode assuming 120mhz system clock for 4mhz spi mode 0 operation .
pub fn new(
        mclk: &mut MCLK,
        qspi: QSPI,
        _sck: impl AnyPin<Id = PB10>,
        _cs: impl AnyPin<Id = PB11>,
        _io0: impl AnyPin<Id = PA08>,
        _io1: impl AnyPin<Id = PA09>,
        _io2: impl AnyPin<Id = PA10>,
        _io3: impl AnyPin<Id = PA11>,
    ) -> Qspi<OneShot> {
        mclk.apbcmask.modify(|_, w| w.qspi_().set_bit());
        // Enable the clocks for the qspi peripheral in single data rate mode.
        mclk.ahbmask.modify(|_, w| {
            w.qspi_().set_bit();
            w.qspi_2x_().clear_bit()
        });
        let _sck = _sck.into().into_alternate();
        let _cs = _cs.into().into_alternate();
        let _io0 = _io0.into().into_alternate();
        let _io1 = _io1.into().into_alternate();
        let _io2 = _io2.into().into_alternate();
        let _io3 = _io3.into().into_alternate();
        qspi.ctrla.write(|w| w.swrst().set_bit());
        qspi.baud.write(|w| unsafe {
            // TODO get system clock value instead of hardcoding
            //(120_000_000u32 / 4_000_000u32) = 30 = BAUD + 1
            // BAUD = 29
            w.baud().bits(29); // 4Mhz
                               // SPI MODE 0
            w.cpol().clear_bit();
            w.cpha().clear_bit()
        });
        qspi.ctrlb.write(|w| {
            w.mode().memory();
            w.csmode().noreload();
            w.csmode().lastxfer();
            w.datalen()._8bits()
        });
        qspi.ctrla.modify(|_, w| w.enable().set_bit());
        Self {
            qspi,
            _sck,
            _cs,
            _io0,
            _io1,
            _io2,
            _io3,
            _mode: PhantomData,
        }
    }
pub fn new ( mclk : & mut MCLK , qspi : QSPI , _sck : impl AnyPin < Id = PB10 > , _cs : impl AnyPin < Id = PB11 > , _io0 : impl AnyPin < Id = PA08 > , _io1 : impl AnyPin < Id = PA09 > , _io2 : impl AnyPin < Id = PA10 > , _io3 : impl AnyPin < Id = PA11 > , ) -> Qspi < OneShot > { mclk . apbcmask . modify ( | _ , w | w . qspi_ ( ) . set_bit ( ) ) ; // Enable the clocks for the qspi peripheral in single data rate mode. mclk . ahbmask . modify ( | _ , w | { w . qspi_ ( ) . set_bit ( ) ; w . qspi_2x_ ( ) . clear_bit ( ) } ) ; let _sck = _sck . into ( ) . into_alternate ( ) ; let _cs = _cs . into ( ) . into_alternate ( ) ; let _io0 = _io0 . into ( ) . into_alternate ( ) ; let _io1 = _io1 . into ( ) . into_alternate ( ) ; let _io2 = _io2 . into ( ) . into_alternate ( ) ; let _io3 = _io3 . into ( ) . into_alternate ( ) ; qspi . ctrla . write ( | w | w . swrst ( ) . set_bit ( ) ) ; qspi . baud . write ( | w | unsafe { // TODO get system clock value instead of hardcoding //(120_000_000u32 / 4_000_000u32) = 30 = BAUD + 1 // BAUD = 29 w . baud ( ) . bits ( 29 ) ; // 4Mhz // SPI MODE 0 w . cpol ( ) . clear_bit ( ) ; w . cpha ( ) . clear_bit ( ) } ) ; qspi . ctrlb . write ( | w | { w . mode ( ) . memory ( ) ; w . csmode ( ) . noreload ( ) ; w . csmode ( ) . lastxfer ( ) ; w . datalen ( ) . _8bits ( ) } ) ; qspi . ctrla . modify ( | _ , w | w . enable ( ) . set_bit ( ) ) ; Self { qspi , _sck , _cs , _io0 , _io1 , _io2 , _io3 , _mode : PhantomData , } }
Enable the clocks for the qspi peripheral in single data rate mode
assuming 120mhz system clock, for 4mhz spi mode 0 operation.
Enable the clocks for the qspi peripheral in single data rate mode assuming 120mhz system clock for 4mhz spi mode 0 operation .
mclk
&mut MCLK
qspi
QSPI
_sck
impl AnyPin<Id = PB10>
_cs
impl AnyPin<Id = PB11>
_io0
impl AnyPin<Id = PA08>
_io1
impl AnyPin<Id = PA09>
_io2
impl AnyPin<Id = PA10>
_io3
impl AnyPin<Id = PA11>
mclk
&mut MCLK
qspi
QSPI
_sck
impl AnyPin<Id = PB10>
_cs
impl AnyPin<Id = PB11>
_io0
impl AnyPin<Id = PA08>
_io1
impl AnyPin<Id = PA09>
_io2
impl AnyPin<Id = PA10>
_io3
impl AnyPin<Id = PA11>