fn start<T>(&mut self, period: T)
    where
        T: Into<Self::Time>,
    {
        // Write the timeout configuration.
        self.wdt
            .config
            .write(|w| unsafe { w.per().bits(period.into()) });
        // Enable the watchdog timer.
        self.wdt.ctrla.write(|w| w.enable().set_bit());
        // Wait for watchdog timer to be enabled.
        while self.wdt.syncbusy.read().enable().bit_is_set() {}
    }
/// Enables a watchdog timer to reset the processor if software is frozen
/// or stalled.
Enables a watchdog timer to reset the processor if software is frozen
or stalled.
Enables a watchdog timer to reset the processor if software is frozen or stalled .
fn start<T>(&mut self, period: T)
    where
        T: Into<Self::Time>,
    {
        // Write the timeout configuration.
        self.wdt
            .config
            .write(|w| unsafe { w.per().bits(period.into()) });
        // Enable the watchdog timer.
        self.wdt.ctrla.write(|w| w.enable().set_bit());
        // Wait for watchdog timer to be enabled.
        while self.wdt.syncbusy.read().enable().bit_is_set() {}
    }
fn start < T > ( & mut self , period : T ) where T : Into < Self :: Time > , { // Write the timeout configuration. self . wdt . config . write ( | w | unsafe { w . per ( ) . bits ( period . into ( ) ) } ) ; // Enable the watchdog timer. self . wdt . ctrla . write ( | w | w . enable ( ) . set_bit ( ) ) ; // Wait for watchdog timer to be enabled. while self . wdt . syncbusy . read ( ) . enable ( ) . bit_is_set ( ) { } }
Enables a watchdog timer to reset the processor if software is frozen
or stalled.
Enables a watchdog timer to reset the processor if software is frozen or stalled .
&mut self
period
T
&mut self
period
T