fn i2c_frequency() {
        i2c_timing_testcase(|i2c_clk: u32, freq: u32| {
            let (presc_reg, scll, sclh, _, _) = i2c_timing!(i2c_clk, freq);

            // Timing parameters
            let presc = (presc_reg + 1) as f32;
            let t_i2c_clk = 1. / (i2c_clk as f32);
            let freq = freq as f32;

            // Estimate minimum sync times. Analog filter on, 2 i2c_clk cycles
            let t_af_min = 50e-9_f32; // Analog filter 50ns. From H7 Datasheet
            let t_sync1 = t_af_min + 2. * t_i2c_clk;
            let t_sync2 = t_af_min + 2. * t_i2c_clk;

            // See RM0433 Rev 7 Section 47.4.9
            let t_high_low = sclh as f32 + 1. + scll as f32 + 1.;
            let t_scl = t_sync1 + t_sync2 + (t_high_low * presc * t_i2c_clk);
            let f_scl = 1. / t_scl;

            let error = (freq - f_scl) / freq;
            println!(
                "Set SCL = {} Actual = {} Error {:.1}%",
                freq,
                f_scl,
                100. * error
            );

            // We must generate a bus frequency less than or equal to that
            // specified. Tolerate a 2% error
            assert!(f_scl <= 1.02 * freq);

            // But it should not be too much less than specified
            assert!(f_scl > 0.8 * freq);
        });
    }
/// Test the SCL frequency is within the expected range
Test the SCL frequency is within the expected range
Test the SCL frequency is within the expected range
fn i2c_frequency() {
        i2c_timing_testcase(|i2c_clk: u32, freq: u32| {
            let (presc_reg, scll, sclh, _, _) = i2c_timing!(i2c_clk, freq);
            // Timing parameters
            let presc = (presc_reg + 1) as f32;
            let t_i2c_clk = 1. / (i2c_clk as f32);
            let freq = freq as f32;
            // Estimate minimum sync times. Analog filter on, 2 i2c_clk cycles
            let t_af_min = 50e-9_f32; // Analog filter 50ns. From H7 Datasheet
            let t_sync1 = t_af_min + 2. * t_i2c_clk;
            let t_sync2 = t_af_min + 2. * t_i2c_clk;
            // See RM0433 Rev 7 Section 47.4.9
            let t_high_low = sclh as f32 + 1. + scll as f32 + 1.;
            let t_scl = t_sync1 + t_sync2 + (t_high_low * presc * t_i2c_clk);
            let f_scl = 1. / t_scl;
            let error = (freq - f_scl) / freq;
            println!(
                "Set SCL = {} Actual = {} Error {:.1}%",
                freq,
                f_scl,
                100. * error
            );
            // We must generate a bus frequency less than or equal to that
            // specified. Tolerate a 2% error
            assert!(f_scl <= 1.02 * freq);
            // But it should not be too much less than specified
            assert!(f_scl > 0.8 * freq);
        });
    }
fn i2c_frequency ( ) { i2c_timing_testcase ( | i2c_clk : u32 , freq : u32 | { let ( presc_reg , scll , sclh , _ , _ ) = i2c_timing ! ( i2c_clk freq ) ; // Timing parameters let presc = ( presc_reg + 1 ) as f32 ; let t_i2c_clk = 1. / ( i2c_clk as f32 ) ; let freq = freq as f32 ; // Estimate minimum sync times. Analog filter on, 2 i2c_clk cycles let t_af_min = 50e-9_f32 ; // Analog filter 50ns. From H7 Datasheet let t_sync1 = t_af_min + 2. * t_i2c_clk ; let t_sync2 = t_af_min + 2. * t_i2c_clk ; // See RM0433 Rev 7 Section 47.4.9 let t_high_low = sclh as f32 + 1. + scll as f32 + 1. ; let t_scl = t_sync1 + t_sync2 + ( t_high_low * presc * t_i2c_clk ) ; let f_scl = 1. / t_scl ; let error = ( freq - f_scl ) / freq ; println ! ( " " freq f_scl 100. error ) ; // We must generate a bus frequency less than or equal to that // specified. Tolerate a 2% error assert ! ( f_scl 1.02 freq ) ; // But it should not be too much less than specified assert ! ( f_scl 0.8 freq ) ; } ) ; }
Test the SCL frequency is within the expected range
Test the SCL frequency is within the expected range