pub(crate) fn is_valid(
        sysclk: u32,
        hse: Option<u32>,
        pclk1: u32,
        pll_config: &Option<PllConfig>,
    ) -> (cfgr::USBPRE_A, bool) {
        // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
        // PLL output frequency is a supported one.
        // usbpre == false: divide clock by 1.5, otherwise no division
        let usb_ok = hse.is_some() && pll_config.is_some();
        // The APB1 clock must have a minimum frequency of 10 MHz to avoid data overrun/underrun
        // problems. [RM0316 32.5.2]
        if pclk1 >= 10_000_000 {
            match (usb_ok, sysclk) {
                (true, 72_000_000) => (cfgr::USBPRE_A::DIV1_5, true),
                (true, 48_000_000) => (cfgr::USBPRE_A::DIV1, true),
                _ => (cfgr::USBPRE_A::DIV1, false),
            }
        } else {
            (cfgr::USBPRE_A::DIV1, false)
        }
    }
/// Check for all clock options to be
Check for all clock options to be
Check for all clock options to be
pub(crate) fn is_valid(
        sysclk: u32,
        hse: Option<u32>,
        pclk1: u32,
        pll_config: &Option<PllConfig>,
    ) -> (cfgr::USBPRE_A, bool) {
        // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
        // PLL output frequency is a supported one.
        // usbpre == false: divide clock by 1.5, otherwise no division
        let usb_ok = hse.is_some() && pll_config.is_some();
        // The APB1 clock must have a minimum frequency of 10 MHz to avoid data overrun/underrun
        // problems. [RM0316 32.5.2]
        if pclk1 >= 10_000_000 {
            match (usb_ok, sysclk) {
                (true, 72_000_000) => (cfgr::USBPRE_A::DIV1_5, true),
                (true, 48_000_000) => (cfgr::USBPRE_A::DIV1, true),
                _ => (cfgr::USBPRE_A::DIV1, false),
            }
        } else {
            (cfgr::USBPRE_A::DIV1, false)
        }
    }
pub ( crate ) fn is_valid ( sysclk : u32 , hse : Option < u32 > , pclk1 : u32 , pll_config : & Option < PllConfig > , ) -> ( cfgr :: USBPRE_A , bool ) { // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the // PLL output frequency is a supported one. // usbpre == false: divide clock by 1.5, otherwise no division let usb_ok = hse . is_some ( ) && pll_config . is_some ( ) ; // The APB1 clock must have a minimum frequency of 10 MHz to avoid data overrun/underrun // problems. [RM0316 32.5.2] if pclk1 >= 10_000_000 { match ( usb_ok , sysclk ) { ( true , 72_000_000 ) => ( cfgr :: USBPRE_A :: DIV1_5 , true ) , ( true , 48_000_000 ) => ( cfgr :: USBPRE_A :: DIV1 , true ) , _ => ( cfgr :: USBPRE_A :: DIV1 , false ) , } } else { ( cfgr :: USBPRE_A :: DIV1 , false ) } }
Check for all clock options to be
Check for all clock options to be
sysclk
u32
hse
Option<u32>
pclk1
u32
pll_config
&Option<PllConfig>
sysclk
u32
hse
Option<u32>
pclk1
u32
pll_config
&Option<PllConfig>