pub fn into_clock_mode(mut self) -> Rtc<ClockMode> {
        // The max divisor is 1024, so to get 1 Hz, we need a 1024 Hz source.
        assert_eq!(self.rtc_clock_freq.0, 1024_u32, "RTC clk not 1024 Hz!");

        self.sync();
        self.enable(false);
        self.sync();
        self.mode2_ctrla().modify(|_, w| {
            w.mode().clock() // enable mode2 (clock)
            .clkrep().clear_bit()
            .matchclr().clear_bit()
            .prescaler().div1024() // 1.024 kHz / 1024 = 1Hz
        });

        // enable clock sync on SAMx5x
        #[cfg(feature = "min-samd51g")]
        {
            self.mode2_ctrla().modify(|_, w| {
                w.clocksync().set_bit() // synchronize the CLOCK register
            });

            self.sync();
        }

        self.sync();
        self.enable(true);
        self.into_mode()
    }
/// Reconfigures the peripheral for clock/calendar mode. Requires the source
/// clock to be running at 1024 Hz.
Reconfigures the peripheral for clock/calendar mode. Requires the source
clock to be running at 1024 Hz.
Reconfigures the peripheral for clock / calendar mode . Requires the source clock to be running at 1024 Hz .
pub fn into_clock_mode(mut self) -> Rtc<ClockMode> {
        // The max divisor is 1024, so to get 1 Hz, we need a 1024 Hz source.
        assert_eq!(self.rtc_clock_freq.0, 1024_u32, "RTC clk not 1024 Hz!");
        self.sync();
        self.enable(false);
        self.sync();
        self.mode2_ctrla().modify(|_, w| {
            w.mode().clock() // enable mode2 (clock)
            .clkrep().clear_bit()
            .matchclr().clear_bit()
            .prescaler().div1024() // 1.024 kHz / 1024 = 1Hz
        });
        // enable clock sync on SAMx5x
        #[cfg(feature = "min-samd51g")]
        {
            self.mode2_ctrla().modify(|_, w| {
                w.clocksync().set_bit() // synchronize the CLOCK register
            });
            self.sync();
        }
        self.sync();
        self.enable(true);
        self.into_mode()
    }
pub fn into_clock_mode ( mut self ) -> Rtc < ClockMode > { // The max divisor is 1024, so to get 1 Hz, we need a 1024 Hz source. assert_eq ! ( self rtc_clock_freq 0 1024_u32 " " ) ; self . sync ( ) ; self . enable ( false ) ; self . sync ( ) ; self . mode2_ctrla ( ) . modify ( | _ , w | { w . mode ( ) . clock ( ) // enable mode2 (clock) . clkrep ( ) . clear_bit ( ) . matchclr ( ) . clear_bit ( ) . prescaler ( ) . div1024 ( ) // 1.024 kHz / 1024 = 1Hz } ) ; // enable clock sync on SAMx5x # [ cfg ( feature " " ) ] { self . mode2_ctrla ( ) . modify ( | _ , w | { w . clocksync ( ) . set_bit ( ) // synchronize the CLOCK register } ) ; self . sync ( ) ; } self . sync ( ) ; self . enable ( true ) ; self . into_mode ( ) }
Reconfigures the peripheral for clock/calendar mode.
Reconfigures the peripheral for clock / calendar mode .
mut self
mut self