pub fn configure_gclk_divider_and_source(
        &mut self,
        gclk: ClockGenId,
        divider: u16,
        src: ClockSource,
        improve_duty_cycle: bool,
    ) -> Option<GClock> {
        let idx = u8::from(gclk) as usize;
        if self.gclks[idx].0 != 0 {
            return None;
        }
        self.state
            .set_gclk_divider_and_source(gclk, divider, src, improve_duty_cycle);
        let freq: Hertz = match src {
            XOSC32K | OSC32K | OSCULP32K => OSC32K_FREQ,
            GCLKGEN1 => self.gclks[1],
            OSC8M => OSC8M_FREQ,
            DFLL48M => OSC48M_FREQ,
            DPLL96M => 96.mhz().into(),
            GCLKIN | XOSC => unimplemented!(),
        };
        self.gclks[idx] = Hertz(freq.0 / divider as u32);
        Some(GClock { gclk, freq })
    }
/// Configures a clock generator with the specified divider and
/// source.
/// `divider` is a linear divider to be applied to the clock
/// source.  While the hardware also supports an exponential divider,
/// this function doesn't expose that functionality at this time.
/// `improve_duty_cycle` is a boolean that, when set to true, enables
/// a 5o/50 duty cycle for odd divider values.
/// Returns a `GClock` for the configured clock generator.
/// Returns `None` if the clock generator has already been configured.
Configures a clock generator with the specified divider and
source.
`divider` is a linear divider to be applied to the clock
source.  While the hardware also supports an exponential divider,
this function doesn't expose that functionality at this time.
`improve_duty_cycle` is a boolean that, when set to true, enables
a 5o/50 duty cycle for odd divider values.
Returns a `GClock` for the configured clock generator.
Returns `None` if the clock generator has already been configured.
Configures a clock generator with the specified divider and source . ` divider ` is a linear divider to be applied to the clock source . While the hardware also supports an exponential divider this function doesn ' t expose that functionality at this time . ` improve_duty_cycle ` is a boolean that when set to true enables a 5o / 50 duty cycle for odd divider values . Returns a ` GClock ` for the configured clock generator . Returns ` None ` if the clock generator has already been configured .
pub fn configure_gclk_divider_and_source(
        &mut self,
        gclk: ClockGenId,
        divider: u16,
        src: ClockSource,
        improve_duty_cycle: bool,
    ) -> Option<GClock> {
        let idx = u8::from(gclk) as usize;
        if self.gclks[idx].0 != 0 {
            return None;
        }
        self.state
            .set_gclk_divider_and_source(gclk, divider, src, improve_duty_cycle);
        let freq: Hertz = match src {
            XOSC32K | OSC32K | OSCULP32K => OSC32K_FREQ,
            GCLKGEN1 => self.gclks[1],
            OSC8M => OSC8M_FREQ,
            DFLL48M => OSC48M_FREQ,
            DPLL96M => 96.mhz().into(),
            GCLKIN | XOSC => unimplemented!(),
        };
        self.gclks[idx] = Hertz(freq.0 / divider as u32);
        Some(GClock { gclk, freq })
    }
pub fn configure_gclk_divider_and_source ( & mut self , gclk : ClockGenId , divider : u16 , src : ClockSource , improve_duty_cycle : bool , ) -> Option < GClock > { let idx = u8 :: from ( gclk ) as usize ; if self . gclks [ idx ] . 0 != 0 { return None ; } self . state . set_gclk_divider_and_source ( gclk , divider , src , improve_duty_cycle ) ; let freq : Hertz = match src { XOSC32K | OSC32K | OSCULP32K => OSC32K_FREQ , GCLKGEN1 => self . gclks [ 1 ] , OSC8M => OSC8M_FREQ , DFLL48M => OSC48M_FREQ , DPLL96M => 96 . mhz ( ) . into ( ) , GCLKIN | XOSC => unimplemented ! ( ) , } ; self . gclks [ idx ] = Hertz ( freq . 0 / divider as u32 ) ; Some ( GClock { gclk , freq } ) }
Configures a clock generator with the specified divider and
source.
Configures a clock generator with the specified divider and source .
&mut self
gclk
ClockGenId
divider
u16
src
ClockSource
improve_duty_cycle
bool
&mut self
gclk
ClockGenId
divider
u16
src
ClockSource
improve_duty_cycle
bool