fn emit_vcs_sh(
    sess: &Session,
    matches: &ArgMatches,
    targets: TargetSet,
    srcs: Vec<SourceGroup>,
) -> Result<()> {
    println!("{}", header_sh(sess));
    for src in srcs {
        separate_files_in_group(
            src,
            |f| match f {
                SourceFile::File(p) => match p.extension().and_then(std::ffi::OsStr::to_str) {
                    Some("sv") | Some("v") | Some("vp") => Some(SourceType::Verilog),
                    Some("vhd") | Some("vhdl") => Some(SourceType::Vhdl),
                    _ => None,
                },
                _ => None,
            },
            |src, ty, files| {
                let mut lines = vec![];
                match ty {
                    SourceType::Verilog => {
                        lines.push(format!(
                            "{} -sverilog",
                            matches.value_of("vlogan-bin").unwrap()
                        ));
                        // Default flags
                        lines.push("-full64".to_owned());
                        if let Some(args) = matches.values_of("vlog-arg") {
                            lines.extend(args.map(Into::into));
                        }
                        let mut defines: Vec<(String, Option<String>)> = vec![];
                        defines.extend(
                            src.defines
                                .iter()
                                .map(|(k, &v)| (k.to_string(), v.map(String::from))),
                        );
                        defines.extend(
                            targets
                                .iter()
                                .map(|t| (format!("TARGET_{}", t.to_uppercase()), None)),
                        );
                        add_defines_from_matches(&mut defines, matches);
                        defines.sort();
                        for (k, v) in defines {
                            let mut s = format!("+define+{}", k.to_uppercase());
                            if let Some(v) = v {
                                s.push('=');
                                s.push('"');
                                s.push_str(&v);
                                s.push('"');
                            }
                            lines.push(s);
                        }
                        for i in src.clone().get_incdirs() {
                            lines
                                .push(quote(&format!("+incdir+{}", relativize_path(i, sess.root))));
                        }
                    }
                    SourceType::Vhdl => {
                        lines.push("vhdlan".to_owned());
                        if let Some(args) = matches.values_of("vcom-arg") {
                            lines.extend(args.map(Into::into));
                        }
                    }
                }
                for file in files {
                    let p = match file {
                        SourceFile::File(p) => p,
                        _ => continue,
                    };
                    lines.push(quote(&relativize_path(p, sess.root)));
                }
                println!("");
                println!("{}", lines.join(" \\\n    "));
            },
        );
    }
    Ok(())
}
/// Emit a vcs compilation script.
Emit a vcs compilation script.
Emit a vcs compilation script .
fn emit_vcs_sh(
    sess: &Session,
    matches: &ArgMatches,
    targets: TargetSet,
    srcs: Vec<SourceGroup>,
) -> Result<()> {
    println!("{}", header_sh(sess));
    for src in srcs {
        separate_files_in_group(
            src,
            |f| match f {
                SourceFile::File(p) => match p.extension().and_then(std::ffi::OsStr::to_str) {
                    Some("sv") | Some("v") | Some("vp") => Some(SourceType::Verilog),
                    Some("vhd") | Some("vhdl") => Some(SourceType::Vhdl),
                    _ => None,
                },
                _ => None,
            },
            |src, ty, files| {
                let mut lines = vec![];
                match ty {
                    SourceType::Verilog => {
                        lines.push(format!(
                            "{} -sverilog",
                            matches.value_of("vlogan-bin").unwrap()
                        ));
                        // Default flags
                        lines.push("-full64".to_owned());
                        if let Some(args) = matches.values_of("vlog-arg") {
                            lines.extend(args.map(Into::into));
                        }
                        let mut defines: Vec<(String, Option<String>)> = vec![];
                        defines.extend(
                            src.defines
                                .iter()
                                .map(|(k, &v)| (k.to_string(), v.map(String::from))),
                        );
                        defines.extend(
                            targets
                                .iter()
                                .map(|t| (format!("TARGET_{}", t.to_uppercase()), None)),
                        );
                        add_defines_from_matches(&mut defines, matches);
                        defines.sort();
                        for (k, v) in defines {
                            let mut s = format!("+define+{}", k.to_uppercase());
                            if let Some(v) = v {
                                s.push('=');
                                s.push('"');
                                s.push_str(&v);
                                s.push('"');
                            }
                            lines.push(s);
                        }
                        for i in src.clone().get_incdirs() {
                            lines
                                .push(quote(&format!("+incdir+{}", relativize_path(i, sess.root))));
                        }
                    }
                    SourceType::Vhdl => {
                        lines.push("vhdlan".to_owned());
                        if let Some(args) = matches.values_of("vcom-arg") {
                            lines.extend(args.map(Into::into));
                        }
                    }
                }
                for file in files {
                    let p = match file {
                        SourceFile::File(p) => p,
                        _ => continue,
                    };
                    lines.push(quote(&relativize_path(p, sess.root)));
                }
                println!("");
                println!("{}", lines.join(" \\\n    "));
            },
        );
    }
    Ok(())
}
fn emit_vcs_sh ( sess : & Session , matches : & ArgMatches , targets : TargetSet , srcs : Vec < SourceGroup > , ) -> Result < ( ) > { println ! ( " " header_sh ( sess ) ) ; for src in srcs { separate_files_in_group ( src , | f | match f { SourceFile :: File ( p ) => match p . extension ( ) . and_then ( std :: ffi :: OsStr :: to_str ) { Some ( " " ) | Some ( " " ) | Some ( " " ) => Some ( SourceType :: Verilog ) , Some ( " " ) | Some ( " " ) => Some ( SourceType :: Vhdl ) , _ => None , } , _ => None , } , | src , ty , files | { let mut lines = vec ! [ ] ; match ty { SourceType :: Verilog => { lines . push ( format ! ( " " matches value_of ( " " ) unwrap ( ) ) ) ; // Default flags lines . push ( " " . to_owned ( ) ) ; if let Some ( args ) = matches . values_of ( " " ) { lines . extend ( args . map ( Into :: into ) ) ; } let mut defines : Vec < ( String , Option < String > ) > = vec ! [ ] ; defines . extend ( src . defines . iter ( ) . map ( | ( k , & v ) | ( k . to_string ( ) , v . map ( String :: from ) ) ) , ) ; defines . extend ( targets . iter ( ) . map ( | t | ( format ! ( " " t to_uppercase ( ) ) , None ) ) , ) ; add_defines_from_matches ( & mut defines , matches ) ; defines . sort ( ) ; for ( k , v ) in defines { let mut s = format ! ( " " k to_uppercase ( ) ) ; if let Some ( v ) = v { s . push ( '=' ) ; s . push ( '"' ) ; s . push_str ( & v ) ; s . push ( '"' ) ; } lines . push ( s ) ; } for i in src . clone ( ) . get_incdirs ( ) { lines . push ( quote ( & format ! ( " " relativize_path ( i sess root ) ) ) ) ; } } SourceType :: Vhdl => { lines . push ( " " . to_owned ( ) ) ; if let Some ( args ) = matches . values_of ( " " ) { lines . extend ( args . map ( Into :: into ) ) ; } } } for file in files { let p = match file { SourceFile :: File ( p ) => p , _ => continue , } ; lines . push ( quote ( & relativize_path ( p , sess . root ) ) ) ; } println ! ( " " ) ; println ! ( " " lines join ( " \\ \n " ) ) ; } , ) ; } Ok ( ( ) ) }
Emit a vcs compilation script.
Emit a vcs compilation script .
sess
&Session
matches
&ArgMatches
targets
TargetSet
srcs
Vec<SourceGroup>
sess
&Session
matches
&ArgMatches
targets
TargetSet
srcs
Vec<SourceGroup>