fn unpend(&self, ev: Event) {
        let line = ev as u8;

        unsafe {
            match line {
                0..=19 | 20 | 21 => {
                    reg_for_cpu!(self, pr1).write(|w| w.bits(1 << line));
                    let _ = reg_for_cpu!(self, pr1).read();
                    let _ = reg_for_cpu!(self, pr1).read(); // Delay 2 peripheral clocks
                }
                49 | 51 => {
                    reg_for_cpu!(self, pr2).write(|w| w.bits(1 << (line - 32)));
                    let _ = reg_for_cpu!(self, pr2).read();
                    let _ = reg_for_cpu!(self, pr2).read(); // Delay 2 peripheral clocks
                }
                82 | 84 | 85 | 86 => {
                    reg_for_cpu!(self, pr3).write(|w| w.bits(1 << (line - 64)));
                    let _ = reg_for_cpu!(self, pr3).read();
                    let _ = reg_for_cpu!(self, pr3).read(); // Delay 2 peripheral clocks
                }
                _ => {}
            }
        }
    }
/// Clear interrupt and pending flag
///
/// Configurable events only
Clear interrupt and pending flag
Configurable events only
Clear interrupt and pending flag Configurable events only
fn unpend(&self, ev: Event) {
        let line = ev as u8;
        unsafe {
            match line {
                0..=19 | 20 | 21 => {
                    reg_for_cpu!(self, pr1).write(|w| w.bits(1 << line));
                    let _ = reg_for_cpu!(self, pr1).read();
                    let _ = reg_for_cpu!(self, pr1).read(); // Delay 2 peripheral clocks
                }
                49 | 51 => {
                    reg_for_cpu!(self, pr2).write(|w| w.bits(1 << (line - 32)));
                    let _ = reg_for_cpu!(self, pr2).read();
                    let _ = reg_for_cpu!(self, pr2).read(); // Delay 2 peripheral clocks
                }
                82 | 84 | 85 | 86 => {
                    reg_for_cpu!(self, pr3).write(|w| w.bits(1 << (line - 64)));
                    let _ = reg_for_cpu!(self, pr3).read();
                    let _ = reg_for_cpu!(self, pr3).read(); // Delay 2 peripheral clocks
                }
                _ => {}
            }
        }
    }
fn unpend ( & self , ev : Event ) { let line = ev as u8 ; unsafe { match line { 0 ..= 19 | 20 | 21 => { reg_for_cpu ! ( self pr1 ) . write ( | w | w . bits ( 1 << line ) ) ; let _ = reg_for_cpu ! ( self pr1 ) . read ( ) ; let _ = reg_for_cpu ! ( self pr1 ) . read ( ) ; // Delay 2 peripheral clocks } 49 | 51 => { reg_for_cpu ! ( self pr2 ) . write ( | w | w . bits ( 1 << ( line - 32 ) ) ) ; let _ = reg_for_cpu ! ( self pr2 ) . read ( ) ; let _ = reg_for_cpu ! ( self pr2 ) . read ( ) ; // Delay 2 peripheral clocks } 82 | 84 | 85 | 86 => { reg_for_cpu ! ( self pr3 ) . write ( | w | w . bits ( 1 << ( line - 64 ) ) ) ; let _ = reg_for_cpu ! ( self pr3 ) . read ( ) ; let _ = reg_for_cpu ! ( self pr3 ) . read ( ) ; // Delay 2 peripheral clocks } _ => { } } } }
Clear interrupt and pending flag
Configurable events only
Clear interrupt and pending flag Configurable events only
&self
ev
Event
&self
ev
Event