fn configure_and_enable_dpll0(oscctrl: &mut OSCCTRL, gclk: &mut GCLK) {
    gclk.pchctrl[ClockId::FDPLL0 as usize].write(|w| {
        w.chen().set_bit();
        w.gen().gclk5()
    });
    unsafe {
        oscctrl.dpll[0].dpllratio.write(|w| {
            w.ldr().bits(59);
            w.ldrfrac().bits(0)
        });
    }
    oscctrl.dpll[0].dpllctrlb.write(|w| w.refclk().gclk());
    oscctrl.dpll[0].dpllctrla.write(|w| {
        w.enable().set_bit();
        w.ondemand().clear_bit()
    });
}
/// Configure the dpll0 to run at 120MHz
Configure the dpll0 to run at 120MHz
Configure the dpll0 to run at 120MHz
fn configure_and_enable_dpll0(oscctrl: &mut OSCCTRL, gclk: &mut GCLK) {
    gclk.pchctrl[ClockId::FDPLL0 as usize].write(|w| {
        w.chen().set_bit();
        w.gen().gclk5()
    });
    unsafe {
        oscctrl.dpll[0].dpllratio.write(|w| {
            w.ldr().bits(59);
            w.ldrfrac().bits(0)
        });
    }
    oscctrl.dpll[0].dpllctrlb.write(|w| w.refclk().gclk());
    oscctrl.dpll[0].dpllctrla.write(|w| {
        w.enable().set_bit();
        w.ondemand().clear_bit()
    });
}
fn configure_and_enable_dpll0 ( oscctrl : & mut OSCCTRL , gclk : & mut GCLK ) { gclk . pchctrl [ ClockId :: FDPLL0 as usize ] . write ( | w | { w . chen ( ) . set_bit ( ) ; w . gen ( ) . gclk5 ( ) } ) ; unsafe { oscctrl . dpll [ 0 ] . dpllratio . write ( | w | { w . ldr ( ) . bits ( 59 ) ; w . ldrfrac ( ) . bits ( 0 ) } ) ; } oscctrl . dpll [ 0 ] . dpllctrlb . write ( | w | w . refclk ( ) . gclk ( ) ) ; oscctrl . dpll [ 0 ] . dpllctrla . write ( | w | { w . enable ( ) . set_bit ( ) ; w . ondemand ( ) . clear_bit ( ) } ) ; }
Configure the dpll0 to run at 120MHz
Configure the dpll0 to run at 120MHz
oscctrl
&mut OSCCTRL
gclk
&mut GCLK
oscctrl
&mut OSCCTRL
gclk
&mut GCLK