fn init(&mut self, config: DisplayConfiguration) {
        // Check bus access
        assert!(self.ltdc.gcr.read().bits() == 0x2220); // Reset value

        // Configure the HS, VS, DE and PC polarity
        self.ltdc.gcr.modify(|_, w| {
            w.hspol()
                .bit(config.h_sync_pol)
                .vspol()
                .bit(config.v_sync_pol)
                .depol()
                .bit(config.not_data_enable_pol)
                .pcpol()
                .bit(config.pixel_clock_pol)
        });

        // Set synchronization pulse width
        self.ltdc.sscr.modify(|_, w| {
            w.vsh()
                .bits(config.v_sync - 1)
                .hsw()
                .bits(config.h_sync - 1)
        });

        // Set accumulated back porch
        self.ltdc.bpcr.modify(|_, w| {
            w.avbp()
                .bits(config.v_sync + config.v_back_porch - 1)
                .ahbp()
                .bits(config.h_sync + config.h_back_porch - 1)
        });

        // Set accumulated active width
        let aa_height =
            config.v_sync + config.v_back_porch + config.active_height - 1;
        let aa_width =
            config.h_sync + config.h_back_porch + config.active_width - 1;
        self.ltdc
            .awcr
            .modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));

        // Set total width and height
        let total_height: u16 = config.v_sync
            + config.v_back_porch
            + config.active_height
            + config.v_front_porch
            - 1;
        let total_width: u16 = config.h_sync
            + config.h_back_porch
            + config.active_width
            + config.h_front_porch
            - 1;
        self.ltdc.twcr.modify(|_, w| {
            w.totalh().bits(total_height).totalw().bits(total_width)
        });

        // Set the background color value
        self.ltdc.bccr.reset();

        // Enable the Transfer Error and FIFO underrun interrupts
        self.ltdc
            .ier
            .modify(|_, w| w.terrie().set_bit().fuie().set_bit());

        // Enable LTDC by setting LTDCEN bit
        self.ltdc.gcr.modify(|_, w| w.ltdcen().set_bit());

        // Save config
        self.config = Some(config);
    }
/// Initialize the LTDC with a given configuration
///
/// # Panics
///
/// Panics if the LTDC GCR register is not in a reset state. Accesses
/// LTDC registers, so if the pclk | aclk | ker_ck are not running this
/// function will stall the bus.
Initialize the LTDC with a given configuration
Initialize the LTDC with a given configuration
fn init(&mut self, config: DisplayConfiguration) {
        // Check bus access
        assert!(self.ltdc.gcr.read().bits() == 0x2220); // Reset value
        // Configure the HS, VS, DE and PC polarity
        self.ltdc.gcr.modify(|_, w| {
            w.hspol()
                .bit(config.h_sync_pol)
                .vspol()
                .bit(config.v_sync_pol)
                .depol()
                .bit(config.not_data_enable_pol)
                .pcpol()
                .bit(config.pixel_clock_pol)
        });
        // Set synchronization pulse width
        self.ltdc.sscr.modify(|_, w| {
            w.vsh()
                .bits(config.v_sync - 1)
                .hsw()
                .bits(config.h_sync - 1)
        });
        // Set accumulated back porch
        self.ltdc.bpcr.modify(|_, w| {
            w.avbp()
                .bits(config.v_sync + config.v_back_porch - 1)
                .ahbp()
                .bits(config.h_sync + config.h_back_porch - 1)
        });
        // Set accumulated active width
        let aa_height =
            config.v_sync + config.v_back_porch + config.active_height - 1;
        let aa_width =
            config.h_sync + config.h_back_porch + config.active_width - 1;
        self.ltdc
            .awcr
            .modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
        // Set total width and height
        let total_height: u16 = config.v_sync
            + config.v_back_porch
            + config.active_height
            + config.v_front_porch
            - 1;
        let total_width: u16 = config.h_sync
            + config.h_back_porch
            + config.active_width
            + config.h_front_porch
            - 1;
        self.ltdc.twcr.modify(|_, w| {
            w.totalh().bits(total_height).totalw().bits(total_width)
        });
        // Set the background color value
        self.ltdc.bccr.reset();
        // Enable the Transfer Error and FIFO underrun interrupts
        self.ltdc
            .ier
            .modify(|_, w| w.terrie().set_bit().fuie().set_bit());
        // Enable LTDC by setting LTDCEN bit
        self.ltdc.gcr.modify(|_, w| w.ltdcen().set_bit());
        // Save config
        self.config = Some(config);
    }
fn init ( & mut self , config : DisplayConfiguration ) { // Check bus access assert ! ( self ltdc gcr read ( ) bits ( ) 0x2220 ) ; // Reset value // Configure the HS, VS, DE and PC polarity self . ltdc . gcr . modify ( | _ , w | { w . hspol ( ) . bit ( config . h_sync_pol ) . vspol ( ) . bit ( config . v_sync_pol ) . depol ( ) . bit ( config . not_data_enable_pol ) . pcpol ( ) . bit ( config . pixel_clock_pol ) } ) ; // Set synchronization pulse width self . ltdc . sscr . modify ( | _ , w | { w . vsh ( ) . bits ( config . v_sync - 1 ) . hsw ( ) . bits ( config . h_sync - 1 ) } ) ; // Set accumulated back porch self . ltdc . bpcr . modify ( | _ , w | { w . avbp ( ) . bits ( config . v_sync + config . v_back_porch - 1 ) . ahbp ( ) . bits ( config . h_sync + config . h_back_porch - 1 ) } ) ; // Set accumulated active width let aa_height = config . v_sync + config . v_back_porch + config . active_height - 1 ; let aa_width = config . h_sync + config . h_back_porch + config . active_width - 1 ; self . ltdc . awcr . modify ( | _ , w | w . aah ( ) . bits ( aa_height ) . aaw ( ) . bits ( aa_width ) ) ; // Set total width and height let total_height : u16 = config . v_sync + config . v_back_porch + config . active_height + config . v_front_porch - 1 ; let total_width : u16 = config . h_sync + config . h_back_porch + config . active_width + config . h_front_porch - 1 ; self . ltdc . twcr . modify ( | _ , w | { w . totalh ( ) . bits ( total_height ) . totalw ( ) . bits ( total_width ) } ) ; // Set the background color value self . ltdc . bccr . reset ( ) ; // Enable the Transfer Error and FIFO underrun interrupts self . ltdc . ier . modify ( | _ , w | w . terrie ( ) . set_bit ( ) . fuie ( ) . set_bit ( ) ) ; // Enable LTDC by setting LTDCEN bit self . ltdc . gcr . modify ( | _ , w | w . ltdcen ( ) . set_bit ( ) ) ; // Save config self . config = Some ( config ) ; }
Initialize the LTDC with a given configuration
Initialize the LTDC with a given configuration
&mut self
config
DisplayConfiguration
&mut self
config
DisplayConfiguration
panics
Panics if the LTDC GCR register is not in a reset state. Accesses
LTDC registers, so if the pclk | aclk | ker_ck are not running this
function will stall the bus.
Panics if the LTDC GCR register is not in a reset state . Accesses LTDC registers so if the pclk | aclk | ker_ck are not running this function will stall the bus .