fn halt(ctx: &mut impl CpuContext) {
    if ctx.cpustate().interrupt_master_enable.enabled() {
        // No need to special-case interrupts here, since the next `tick` call will un-halt anyway.
        ctx.cpustate_mut().halted = true;
    } else {
        let enabled_interrupts = InterruptFlags::get_interrupt_enable(ctx.mem());
        let pending_interrupts = ctx.cpustate().interrupt_vector;
        if enabled_interrupts.intersects(pending_interrupts) {
            panic!("Halt-Bug encountered (see method description).");
        } else {
            // `tick` will un-halt next time ([IE] & [IF] != 0), but will not service the interrupt.
            ctx.cpustate_mut().halted = true;
        }
    }
}
/// If `IME` is set, just halts the CPU until there is an interrupt available to be serviced. If
/// there's already an interrupt to be serviced, `HALT` is effectively a `NOP` and excution moved
/// directly to the interrupt handler then to the next instruction.
///
/// If `IME` is not set, there's a possibility of triggering a CPU bug:
/// *   If no interrupt is pending, the CPU still halts and resumes the next time an interrupt
///     becomes pending, but the interrupt just isn't handled because IME is off.
/// *   If there are enabled interrupts pending (`[IE] & [IF] != 0`), the bug is triggered:
///     *   In the normal case, the bug just prevents the program counter from incrementing
///         properly, so the byte after `HALT` will be read twice. (This presumably means that any
///         1-byte instruction will execute twice, and any two-byte instruction will read itself as
///         the following value, but that's somewhat unclear. Its also not clear what happens if an
///         `RST` is executed, since that's a 1 byte jump. Does overwritting the `PC` avert the bug?
///         Note that with any normal `CALL`, `JP`, or `JR`, the repeat byte would be used as the
///         jump target or offset instead.)
///     *   If `EI` executed just before `HALT` such that `IME` would become true after the `HALT`,
///         the bug is even weirder: the interrupt is serviced as normal, but then the interrupt
///         returns to `halt` which is executed again.
///
/// Implementing the behavior of preventing PC increment would require a bunch of complex extra
/// state which would have to be checked in a bunch of places, so for now this just panics if the
/// bug would be encountered.
If `IME` is set, just halts the CPU until there is an interrupt available to be serviced. If
there's already an interrupt to be serviced, `HALT` is effectively a `NOP` and excution moved
directly to the interrupt handler then to the next instruction.

If `IME` is not set, there's a possibility of triggering a CPU bug:
If no interrupt is pending, the CPU still halts and resumes the next time an interrupt
becomes pending, but the interrupt just isn't handled because IME is off.
If there are enabled interrupts pending (`[IE] & [IF] != 0`), the bug is triggered:
In the normal case, the bug just prevents the program counter from incrementing
properly, so the byte after `HALT` will be read twice. (This presumably means that any
1-byte instruction will execute twice, and any two-byte instruction will read itself as
the following value, but that's somewhat unclear. Its also not clear what happens if an
`RST` is executed, since that's a 1 byte jump. Does overwritting the `PC` avert the bug.

Implementing the behavior of preventing PC increment would require a bunch of complex extra
state which would have to be checked in a bunch of places, so for now this just panics if the
bug would be encountered.
If ` IME ` is set just halts the CPU until there is an interrupt available to be serviced . If there ' s already an interrupt to be serviced ` HALT ` is effectively a ` NOP ` and excution moved directly to the interrupt handler then to the next instruction . If ` IME ` is not set there ' s a possibility of triggering a CPU bug : If no interrupt is pending the CPU still halts and resumes the next time an interrupt becomes pending but the interrupt just isn ' t handled because IME is off . If there are enabled interrupts pending ( ` [ IE ] & [ IF ] ! = 0 ` ) the bug is triggered : In the normal case the bug just prevents the program counter from incrementing properly so the byte after ` HALT ` will be read twice . ( This presumably means that any 1 - byte instruction will execute twice and any two - byte instruction will read itself as the following value but that ' s somewhat unclear . Its also not clear what happens if an ` RST ` is executed since that ' s a 1 byte jump . Does overwritting the ` PC ` avert the bug . Implementing the behavior of preventing PC increment would require a bunch of complex extra state which would have to be checked in a bunch of places so for now this just panics if the bug would be encountered .
fn halt(ctx: &mut impl CpuContext) {
    if ctx.cpustate().interrupt_master_enable.enabled() {
        // No need to special-case interrupts here, since the next `tick` call will un-halt anyway.
        ctx.cpustate_mut().halted = true;
    } else {
        let enabled_interrupts = InterruptFlags::get_interrupt_enable(ctx.mem());
        let pending_interrupts = ctx.cpustate().interrupt_vector;
        if enabled_interrupts.intersects(pending_interrupts) {
            panic!("Halt-Bug encountered (see method description).");
        } else {
            // `tick` will un-halt next time ([IE] & [IF] != 0), but will not service the interrupt.
            ctx.cpustate_mut().halted = true;
        }
    }
}
fn halt ( ctx : & mut impl CpuContext ) { if ctx . cpustate ( ) . interrupt_master_enable . enabled ( ) { // No need to special-case interrupts here, since the next `tick` call will un-halt anyway. ctx . cpustate_mut ( ) . halted = true ; } else { let enabled_interrupts = InterruptFlags :: get_interrupt_enable ( ctx . mem ( ) ) ; let pending_interrupts = ctx . cpustate ( ) . interrupt_vector ; if enabled_interrupts . intersects ( pending_interrupts ) { panic ! ( " " ) ; } else { // `tick` will un-halt next time ([IE] & [IF] != 0), but will not service the interrupt. ctx . cpustate_mut ( ) . halted = true ; } } }
If `IME` is set, just halts the CPU until there is an interrupt available to be serviced.
If ` IME ` is set just halts the CPU until there is an interrupt available to be serviced .
ctx
&mut impl CpuContext
ctx
&mut impl CpuContext