pub fn freeze(self, acr: &mut ACR) -> Clocks {
        let (sysclk, sysclk_source, pll_config) = self.get_sysclk();

        let (hpre_bits, hpre) = self
            .hclk
            .map(|hclk| match sysclk / hclk {
                0 => unreachable!(),
                1 => (cfgr::HPRE_A::DIV1, 1),
                2 => (cfgr::HPRE_A::DIV2, 2),
                3..=5 => (cfgr::HPRE_A::DIV4, 4),
                6..=11 => (cfgr::HPRE_A::DIV8, 8),
                12..=39 => (cfgr::HPRE_A::DIV16, 16),
                40..=95 => (cfgr::HPRE_A::DIV64, 64),
                96..=191 => (cfgr::HPRE_A::DIV128, 128),
                192..=383 => (cfgr::HPRE_A::DIV256, 256),
                _ => (cfgr::HPRE_A::DIV512, 512),
            })
            .unwrap_or((cfgr::HPRE_A::DIV1, 1));

        let hclk: u32 = sysclk / hpre;

        assert!(hclk <= 72_000_000);

        let (ppre1_bits, ppre1) = self
            .pclk1
            .map(|pclk1| match hclk / pclk1 {
                0 => unreachable!(),
                1 => (cfgr::PPRE1_A::DIV1, 1),
                2 => (cfgr::PPRE1_A::DIV2, 2),
                3..=5 => (cfgr::PPRE1_A::DIV4, 4),
                6..=11 => (cfgr::PPRE1_A::DIV8, 8),
                _ => (cfgr::PPRE1_A::DIV16, 16),
            })
            .unwrap_or((cfgr::PPRE1_A::DIV1, 1));

        let pclk1 = hclk / u32::from(ppre1);

        assert!(pclk1 <= 36_000_000);

        let (ppre2_bits, ppre2) = self
            .pclk2
            .map(|pclk2| match hclk / pclk2 {
                0 => unreachable!(),
                1 => (cfgr::PPRE2_A::DIV1, 1),
                2 => (cfgr::PPRE2_A::DIV2, 2),
                3..=5 => (cfgr::PPRE2_A::DIV4, 4),
                6..=11 => (cfgr::PPRE2_A::DIV8, 8),
                _ => (cfgr::PPRE2_A::DIV16, 16),
            })
            .unwrap_or((cfgr::PPRE2_A::DIV1, 1));

        let pclk2 = hclk / u32::from(ppre2);

        assert!(pclk2 <= 72_000_000);

        // Adjust flash wait states according to the
        // HCLK frequency (cpu core clock)
        acr.acr().modify(|_, w| {
            if hclk <= 24_000_000 {
                w.latency().ws0()
            } else if hclk <= 48_000_000 {
                w.latency().ws1()
            } else {
                w.latency().ws2()
            }
        });

        let (usbpre, usbclk_valid) = usb_clocking::is_valid(sysclk, self.hse, pclk1, &pll_config);

        let rcc = unsafe { &*RCC::ptr() };

        if self.hse.is_some() {
            // enable HSE and wait for it to be ready
            rcc.cr.modify(|_, w| w.hseon().on());

            while rcc.cr.read().hserdy().is_not_ready() {}
        }

        // enable PLL and wait for it to be ready
        if let Some(pll_config) = pll_config {
            rcc.cfgr.modify(|_, w| {
                w.pllmul()
                    .variant(pll_config.mul)
                    .pllsrc()
                    .variant(pll_config.src)
            });

            if let Some(pll_div) = pll_config.div {
                rcc.cfgr2.modify(|_, w| w.prediv().variant(pll_div));
            };

            rcc.cr.modify(|_, w| w.pllon().on());

            while rcc.cr.read().pllrdy().is_not_ready() {}
        };

        // set prescalers and clock source
        rcc.cfgr.modify(|_, w| {
            usb_clocking::set_usbpre(w, usbpre);

            w.ppre2()
                .variant(ppre2_bits)
                .ppre1()
                .variant(ppre1_bits)
                .hpre()
                .variant(hpre_bits)
                .sw()
                .variant(sysclk_source)
        });

        Clocks {
            hclk: Hertz(hclk),
            pclk1: Hertz(pclk1),
            pclk2: Hertz(pclk2),
            ppre1,
            ppre2,
            sysclk: Hertz(sysclk),
            usbclk_valid,
        }
    }
/// Freezes the clock configuration, making it effective
Freezes the clock configuration, making it effective
Freezes the clock configuration making it effective
pub fn freeze(self, acr: &mut ACR) -> Clocks {
        let (sysclk, sysclk_source, pll_config) = self.get_sysclk();
        let (hpre_bits, hpre) = self
            .hclk
            .map(|hclk| match sysclk / hclk {
                0 => unreachable!(),
                1 => (cfgr::HPRE_A::DIV1, 1),
                2 => (cfgr::HPRE_A::DIV2, 2),
                3..=5 => (cfgr::HPRE_A::DIV4, 4),
                6..=11 => (cfgr::HPRE_A::DIV8, 8),
                12..=39 => (cfgr::HPRE_A::DIV16, 16),
                40..=95 => (cfgr::HPRE_A::DIV64, 64),
                96..=191 => (cfgr::HPRE_A::DIV128, 128),
                192..=383 => (cfgr::HPRE_A::DIV256, 256),
                _ => (cfgr::HPRE_A::DIV512, 512),
            })
            .unwrap_or((cfgr::HPRE_A::DIV1, 1));
        let hclk: u32 = sysclk / hpre;
        assert!(hclk <= 72_000_000);
        let (ppre1_bits, ppre1) = self
            .pclk1
            .map(|pclk1| match hclk / pclk1 {
                0 => unreachable!(),
                1 => (cfgr::PPRE1_A::DIV1, 1),
                2 => (cfgr::PPRE1_A::DIV2, 2),
                3..=5 => (cfgr::PPRE1_A::DIV4, 4),
                6..=11 => (cfgr::PPRE1_A::DIV8, 8),
                _ => (cfgr::PPRE1_A::DIV16, 16),
            })
            .unwrap_or((cfgr::PPRE1_A::DIV1, 1));
        let pclk1 = hclk / u32::from(ppre1);
        assert!(pclk1 <= 36_000_000);
        let (ppre2_bits, ppre2) = self
            .pclk2
            .map(|pclk2| match hclk / pclk2 {
                0 => unreachable!(),
                1 => (cfgr::PPRE2_A::DIV1, 1),
                2 => (cfgr::PPRE2_A::DIV2, 2),
                3..=5 => (cfgr::PPRE2_A::DIV4, 4),
                6..=11 => (cfgr::PPRE2_A::DIV8, 8),
                _ => (cfgr::PPRE2_A::DIV16, 16),
            })
            .unwrap_or((cfgr::PPRE2_A::DIV1, 1));
        let pclk2 = hclk / u32::from(ppre2);
        assert!(pclk2 <= 72_000_000);
        // Adjust flash wait states according to the
        // HCLK frequency (cpu core clock)
        acr.acr().modify(|_, w| {
            if hclk <= 24_000_000 {
                w.latency().ws0()
            } else if hclk <= 48_000_000 {
                w.latency().ws1()
            } else {
                w.latency().ws2()
            }
        });
        let (usbpre, usbclk_valid) = usb_clocking::is_valid(sysclk, self.hse, pclk1, &pll_config);
        let rcc = unsafe { &*RCC::ptr() };
        if self.hse.is_some() {
            // enable HSE and wait for it to be ready
            rcc.cr.modify(|_, w| w.hseon().on());
            while rcc.cr.read().hserdy().is_not_ready() {}
        }
        // enable PLL and wait for it to be ready
        if let Some(pll_config) = pll_config {
            rcc.cfgr.modify(|_, w| {
                w.pllmul()
                    .variant(pll_config.mul)
                    .pllsrc()
                    .variant(pll_config.src)
            });
            if let Some(pll_div) = pll_config.div {
                rcc.cfgr2.modify(|_, w| w.prediv().variant(pll_div));
            };
            rcc.cr.modify(|_, w| w.pllon().on());
            while rcc.cr.read().pllrdy().is_not_ready() {}
        };
        // set prescalers and clock source
        rcc.cfgr.modify(|_, w| {
            usb_clocking::set_usbpre(w, usbpre);
            w.ppre2()
                .variant(ppre2_bits)
                .ppre1()
                .variant(ppre1_bits)
                .hpre()
                .variant(hpre_bits)
                .sw()
                .variant(sysclk_source)
        });
        Clocks {
            hclk: Hertz(hclk),
            pclk1: Hertz(pclk1),
            pclk2: Hertz(pclk2),
            ppre1,
            ppre2,
            sysclk: Hertz(sysclk),
            usbclk_valid,
        }
    }
pub fn freeze ( self , acr : & mut ACR ) -> Clocks { let ( sysclk , sysclk_source , pll_config ) = self . get_sysclk ( ) ; let ( hpre_bits , hpre ) = self . hclk . map ( | hclk | match sysclk / hclk { 0 => unreachable ! ( ) , 1 => ( cfgr :: HPRE_A :: DIV1 , 1 ) , 2 => ( cfgr :: HPRE_A :: DIV2 , 2 ) , 3 ..= 5 => ( cfgr :: HPRE_A :: DIV4 , 4 ) , 6 ..= 11 => ( cfgr :: HPRE_A :: DIV8 , 8 ) , 12 ..= 39 => ( cfgr :: HPRE_A :: DIV16 , 16 ) , 40 ..= 95 => ( cfgr :: HPRE_A :: DIV64 , 64 ) , 96 ..= 191 => ( cfgr :: HPRE_A :: DIV128 , 128 ) , 192 ..= 383 => ( cfgr :: HPRE_A :: DIV256 , 256 ) , _ => ( cfgr :: HPRE_A :: DIV512 , 512 ) , } ) . unwrap_or ( ( cfgr :: HPRE_A :: DIV1 , 1 ) ) ; let hclk : u32 = sysclk / hpre ; assert ! ( hclk 72_000_000 ) ; let ( ppre1_bits , ppre1 ) = self . pclk1 . map ( | pclk1 | match hclk / pclk1 { 0 => unreachable ! ( ) , 1 => ( cfgr :: PPRE1_A :: DIV1 , 1 ) , 2 => ( cfgr :: PPRE1_A :: DIV2 , 2 ) , 3 ..= 5 => ( cfgr :: PPRE1_A :: DIV4 , 4 ) , 6 ..= 11 => ( cfgr :: PPRE1_A :: DIV8 , 8 ) , _ => ( cfgr :: PPRE1_A :: DIV16 , 16 ) , } ) . unwrap_or ( ( cfgr :: PPRE1_A :: DIV1 , 1 ) ) ; let pclk1 = hclk / u32 :: from ( ppre1 ) ; assert ! ( pclk1 36_000_000 ) ; let ( ppre2_bits , ppre2 ) = self . pclk2 . map ( | pclk2 | match hclk / pclk2 { 0 => unreachable ! ( ) , 1 => ( cfgr :: PPRE2_A :: DIV1 , 1 ) , 2 => ( cfgr :: PPRE2_A :: DIV2 , 2 ) , 3 ..= 5 => ( cfgr :: PPRE2_A :: DIV4 , 4 ) , 6 ..= 11 => ( cfgr :: PPRE2_A :: DIV8 , 8 ) , _ => ( cfgr :: PPRE2_A :: DIV16 , 16 ) , } ) . unwrap_or ( ( cfgr :: PPRE2_A :: DIV1 , 1 ) ) ; let pclk2 = hclk / u32 :: from ( ppre2 ) ; assert ! ( pclk2 72_000_000 ) ; // Adjust flash wait states according to the // HCLK frequency (cpu core clock) acr . acr ( ) . modify ( | _ , w | { if hclk <= 24_000_000 { w . latency ( ) . ws0 ( ) } else if hclk <= 48_000_000 { w . latency ( ) . ws1 ( ) } else { w . latency ( ) . ws2 ( ) } } ) ; let ( usbpre , usbclk_valid ) = usb_clocking :: is_valid ( sysclk , self . hse , pclk1 , & pll_config ) ; let rcc = unsafe { & * RCC :: ptr ( ) } ; if self . hse . is_some ( ) { // enable HSE and wait for it to be ready rcc . cr . modify ( | _ , w | w . hseon ( ) . on ( ) ) ; while rcc . cr . read ( ) . hserdy ( ) . is_not_ready ( ) { } } // enable PLL and wait for it to be ready if let Some ( pll_config ) = pll_config { rcc . cfgr . modify ( | _ , w | { w . pllmul ( ) . variant ( pll_config . mul ) . pllsrc ( ) . variant ( pll_config . src ) } ) ; if let Some ( pll_div ) = pll_config . div { rcc . cfgr2 . modify ( | _ , w | w . prediv ( ) . variant ( pll_div ) ) ; } ; rcc . cr . modify ( | _ , w | w . pllon ( ) . on ( ) ) ; while rcc . cr . read ( ) . pllrdy ( ) . is_not_ready ( ) { } } ; // set prescalers and clock source rcc . cfgr . modify ( | _ , w | { usb_clocking :: set_usbpre ( w , usbpre ) ; w . ppre2 ( ) . variant ( ppre2_bits ) . ppre1 ( ) . variant ( ppre1_bits ) . hpre ( ) . variant ( hpre_bits ) . sw ( ) . variant ( sysclk_source ) } ) ; Clocks { hclk : Hertz ( hclk ) , pclk1 : Hertz ( pclk1 ) , pclk2 : Hertz ( pclk2 ) , ppre1 , ppre2 , sysclk : Hertz ( sysclk ) , usbclk_valid , } }
Freezes the clock configuration, making it effective
Freezes the clock configuration making it effective
self
acr
&mut ACR
self
acr
&mut ACR