pub fn listen(&mut self, exti: &mut EXTI, event: Event) {
        // RTC interrupts aren't connected directly to the NVIC but are routed through the EXTI,
        // I suppose so that they can use the EXTI's ability to wakeup the CPU or other things.
        // We need to also enable the interrupt in the EXTI.
        //
        // Input Mapping (RM0433 Rev 7 Section 20.4):
        // EXTI 17 = RTC Alarms
        // EXTI 18 = RTC Tamper, RTC Timestamp, RTC LSECSS
        // EXTI 19 = RTC Wakeup Timer

        // unsafe: Only we can use these bits for anything
        let rcc = unsafe { &*RCC::ptr() };

        match event {
            Event::LseCss => {
                exti.listen(ExtiEvent::RTC_OTHER);
                exti.rtsr1.modify(|_, w| w.tr18().enabled());
                rcc.cier.modify(|_, w| w.lsecssie().enabled());
            }
            Event::AlarmA => {
                exti.listen(ExtiEvent::RTC_ALARM);
                exti.rtsr1.modify(|_, w| w.tr17().enabled());
                self.reg.cr.modify(|_, w| w.alraie().set_bit());
            }
            Event::AlarmB => {
                exti.listen(ExtiEvent::RTC_ALARM);
                exti.rtsr1.modify(|_, w| w.tr17().enabled());
                self.reg.cr.modify(|_, w| w.alrbie().set_bit());
            }
            Event::Wakeup => {
                exti.listen(ExtiEvent::RTC_WAKEUP);
                exti.rtsr1.modify(|_, w| w.tr19().enabled());
                self.reg.cr.modify(|_, w| w.wutie().set_bit());
            }
            Event::Timestamp => {
                exti.listen(ExtiEvent::RTC_OTHER);
                exti.rtsr1.modify(|_, w| w.tr18().enabled());
                self.reg.cr.modify(|_, w| w.tsie().set_bit());
            }
        }
    }
/// Start listening for `event`
Start listening for `event`
Start listening for ` event `
pub fn listen(&mut self, exti: &mut EXTI, event: Event) {
        // RTC interrupts aren't connected directly to the NVIC but are routed through the EXTI,
        // I suppose so that they can use the EXTI's ability to wakeup the CPU or other things.
        // We need to also enable the interrupt in the EXTI.
        //
        // Input Mapping (RM0433 Rev 7 Section 20.4):
        // EXTI 17 = RTC Alarms
        // EXTI 18 = RTC Tamper, RTC Timestamp, RTC LSECSS
        // EXTI 19 = RTC Wakeup Timer
        // unsafe: Only we can use these bits for anything
        let rcc = unsafe { &*RCC::ptr() };
        match event {
            Event::LseCss => {
                exti.listen(ExtiEvent::RTC_OTHER);
                exti.rtsr1.modify(|_, w| w.tr18().enabled());
                rcc.cier.modify(|_, w| w.lsecssie().enabled());
            }
            Event::AlarmA => {
                exti.listen(ExtiEvent::RTC_ALARM);
                exti.rtsr1.modify(|_, w| w.tr17().enabled());
                self.reg.cr.modify(|_, w| w.alraie().set_bit());
            }
            Event::AlarmB => {
                exti.listen(ExtiEvent::RTC_ALARM);
                exti.rtsr1.modify(|_, w| w.tr17().enabled());
                self.reg.cr.modify(|_, w| w.alrbie().set_bit());
            }
            Event::Wakeup => {
                exti.listen(ExtiEvent::RTC_WAKEUP);
                exti.rtsr1.modify(|_, w| w.tr19().enabled());
                self.reg.cr.modify(|_, w| w.wutie().set_bit());
            }
            Event::Timestamp => {
                exti.listen(ExtiEvent::RTC_OTHER);
                exti.rtsr1.modify(|_, w| w.tr18().enabled());
                self.reg.cr.modify(|_, w| w.tsie().set_bit());
            }
        }
    }
pub fn listen ( & mut self , exti : & mut EXTI , event : Event ) { // RTC interrupts aren't connected directly to the NVIC but are routed through the EXTI, // I suppose so that they can use the EXTI's ability to wakeup the CPU or other things. // We need to also enable the interrupt in the EXTI. // // Input Mapping (RM0433 Rev 7 Section 20.4): // EXTI 17 = RTC Alarms // EXTI 18 = RTC Tamper, RTC Timestamp, RTC LSECSS // EXTI 19 = RTC Wakeup Timer // unsafe: Only we can use these bits for anything let rcc = unsafe { & * RCC :: ptr ( ) } ; match event { Event :: LseCss => { exti . listen ( ExtiEvent :: RTC_OTHER ) ; exti . rtsr1 . modify ( | _ , w | w . tr18 ( ) . enabled ( ) ) ; rcc . cier . modify ( | _ , w | w . lsecssie ( ) . enabled ( ) ) ; } Event :: AlarmA => { exti . listen ( ExtiEvent :: RTC_ALARM ) ; exti . rtsr1 . modify ( | _ , w | w . tr17 ( ) . enabled ( ) ) ; self . reg . cr . modify ( | _ , w | w . alraie ( ) . set_bit ( ) ) ; } Event :: AlarmB => { exti . listen ( ExtiEvent :: RTC_ALARM ) ; exti . rtsr1 . modify ( | _ , w | w . tr17 ( ) . enabled ( ) ) ; self . reg . cr . modify ( | _ , w | w . alrbie ( ) . set_bit ( ) ) ; } Event :: Wakeup => { exti . listen ( ExtiEvent :: RTC_WAKEUP ) ; exti . rtsr1 . modify ( | _ , w | w . tr19 ( ) . enabled ( ) ) ; self . reg . cr . modify ( | _ , w | w . wutie ( ) . set_bit ( ) ) ; } Event :: Timestamp => { exti . listen ( ExtiEvent :: RTC_OTHER ) ; exti . rtsr1 . modify ( | _ , w | w . tr18 ( ) . enabled ( ) ) ; self . reg . cr . modify ( | _ , w | w . tsie ( ) . set_bit ( ) ) ; } } }
Start listening for `event`
Start listening for ` event `
&mut self
exti
&mut EXTI
event
Event
&mut self
exti
&mut EXTI
event
Event