pub(super) fn read(self, ctx: &mut impl CpuContext) -> u8 {
        trace!("Operand8::read {}", self);
        match self {
            Self::A => ctx.cpustate().regs.acc,
            Self::B => ctx.cpustate().regs.b,
            Self::C => ctx.cpustate().regs.c,
            Self::D => ctx.cpustate().regs.d,
            Self::E => ctx.cpustate().regs.e,
            Self::H => ctx.cpustate().regs.h,
            Self::L => ctx.cpustate().regs.l,
            Self::AddrHL => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrBC => {
                let addr = ctx.cpustate().regs.bc();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrDE => {
                let addr = ctx.cpustate().regs.de();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrHLInc => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_add(1));
                ctx.mem().read(addr.into())
            }
            Self::AddrHLDec => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_sub(1));
                ctx.mem().read(addr.into())
            }
            Self::Immediate => {
                let addr = ctx.cpustate_mut().regs.inc_pc();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrImmediate => {
                let addr = Operand16::Immediate.read(ctx);
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrRelC => {
                let addr = 0xFF00 + ctx.cpustate().regs.c as u16;
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrRelImmediate => {
                let addr = 0xFF00 + Self::Immediate.read(ctx) as u16;
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
        }
    }
/// Read this operand from the CPU context, yielding for memory access if needed.
Read this operand from the CPU context, yielding for memory access if needed.
Read this operand from the CPU context yielding for memory access if needed .
pub(super) fn read(self, ctx: &mut impl CpuContext) -> u8 {
        trace!("Operand8::read {}", self);
        match self {
            Self::A => ctx.cpustate().regs.acc,
            Self::B => ctx.cpustate().regs.b,
            Self::C => ctx.cpustate().regs.c,
            Self::D => ctx.cpustate().regs.d,
            Self::E => ctx.cpustate().regs.e,
            Self::H => ctx.cpustate().regs.h,
            Self::L => ctx.cpustate().regs.l,
            Self::AddrHL => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrBC => {
                let addr = ctx.cpustate().regs.bc();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrDE => {
                let addr = ctx.cpustate().regs.de();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrHLInc => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_add(1));
                ctx.mem().read(addr.into())
            }
            Self::AddrHLDec => {
                let addr = ctx.cpustate().regs.hl();
                ctx.yield1m();
                ctx.cpustate_mut().regs.set_hl(addr.wrapping_sub(1));
                ctx.mem().read(addr.into())
            }
            Self::Immediate => {
                let addr = ctx.cpustate_mut().regs.inc_pc();
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrImmediate => {
                let addr = Operand16::Immediate.read(ctx);
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrRelC => {
                let addr = 0xFF00 + ctx.cpustate().regs.c as u16;
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
            Self::AddrRelImmediate => {
                let addr = 0xFF00 + Self::Immediate.read(ctx) as u16;
                ctx.yield1m();
                ctx.mem().read(addr.into())
            }
        }
    }
pub ( super ) fn read ( self , ctx : & mut impl CpuContext ) -> u8 { trace ! ( " " self ) ; match self { Self :: A => ctx . cpustate ( ) . regs . acc , Self :: B => ctx . cpustate ( ) . regs . b , Self :: C => ctx . cpustate ( ) . regs . c , Self :: D => ctx . cpustate ( ) . regs . d , Self :: E => ctx . cpustate ( ) . regs . e , Self :: H => ctx . cpustate ( ) . regs . h , Self :: L => ctx . cpustate ( ) . regs . l , Self :: AddrHL => { let addr = ctx . cpustate ( ) . regs . hl ( ) ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrBC => { let addr = ctx . cpustate ( ) . regs . bc ( ) ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrDE => { let addr = ctx . cpustate ( ) . regs . de ( ) ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrHLInc => { let addr = ctx . cpustate ( ) . regs . hl ( ) ; ctx . yield1m ( ) ; ctx . cpustate_mut ( ) . regs . set_hl ( addr . wrapping_add ( 1 ) ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrHLDec => { let addr = ctx . cpustate ( ) . regs . hl ( ) ; ctx . yield1m ( ) ; ctx . cpustate_mut ( ) . regs . set_hl ( addr . wrapping_sub ( 1 ) ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: Immediate => { let addr = ctx . cpustate_mut ( ) . regs . inc_pc ( ) ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrImmediate => { let addr = Operand16 :: Immediate . read ( ctx ) ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrRelC => { let addr = 0xFF00 + ctx . cpustate ( ) . regs . c as u16 ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } Self :: AddrRelImmediate => { let addr = 0xFF00 + Self :: Immediate . read ( ctx ) as u16 ; ctx . yield1m ( ) ; ctx . mem ( ) . read ( addr . into ( ) ) } } }
Read this operand from the CPU context, yielding for memory access if needed.
Read this operand from the CPU context yielding for memory access if needed .
self
ctx
&mut impl CpuContext
self
ctx
&mut impl CpuContext