ip_xact/h_addr_generator.py
def write_reg_group_union(self, regGroup):
		"""
		Write group of IP-XACT register objects as a single union to generator
		output. Group of registers should reside within the same memory word.

		Example of union with 32 bit wrdWidth:
			union <joined_name> {
				uint32 u32;
				struct <joined_name>_s {
					uint32  bitfield_first : <width_of_bitfield>)
					  ...
					uint32  bitfield_last  : <width_of_bitfield>  
				}

		Name of union <joined_name> is concatenated from all register names
		within input group of registers.
		Arguments:
			regGroup 	List of IP-XACT register objects.
		"""
		fielDecls = []
		enumDecl = []
		unName = self.prefix + "_"

		for (j,reg) in enumerate(regGroup):

			# Create declaration objects for each field of IP-XACT register.
			for (i,field) in enumerate(sorted(reg.field, key=lambda a: a.bitOffset)):
				fieldDecl = self.create_reg_field_decl(reg, field)
				fieldDecl.comment = None
				if (i == 0):
					fieldDecl.comment = reg.name.upper()

				fielDecls.append(fieldDecl)

			# Append register name to the union name
			unName += reg.name.lower()
			if (j != len(regGroup) - 1):
				unName += "_"

		enumDecl = []

		# Create declaration of u<wrd_width> union member
		unsigned_decl = LanDeclaration("u{}".format(self.wrdWidthBit), value=0)
		unsigned_decl.type = "uint{}_t".format(self.wrdWidthBit)
		unsigned_decl.gap = 1

		# Append declarations to the list of declarations within an enum
		enumDecl.append(unsigned_decl)
		enumDecl.append(fielDecls)

		self.headerGen.create_union(unName, enumDecl)
		self.headerGen.wr_nl()

		Write group of IP-XACT register objects as a single union to generator
		output. Group of registers should reside within the same memory word.

		Example of union with 32 bit wrdWidth:
			union <joined_name> {
				uint32 u32;
				struct <joined_name>_s {
					uint32  bitfield_first : <width_of_bitfield>)
					  ...
					uint32  bitfield_last  : <width_of_bitfield>  
				}

		Name of union <joined_name> is concatenated from all register names
		within input group of registers.
		Arguments:
			regGroup 	List of IP-XACT register objects.
		
Write group of IP-XACT register objects as a single union to generator
output. Group of registers should reside within the same memory word.

Example of union with 32 bit wrdWidth:
union  {
uint32 u32;
struct _s {
uint32  bitfield_first : )

uint32  bitfield_last  : 
}

Name of union  is concatenated from all register names
within input group of registers.
Arguments:
regGroup        List of IP-XACT register objects.
Write group of IP - XACT register objects as a single union to generator output . Group of registers should reside within the same memory word . Example of union with 32 bit wrdWidth : union { uint32 u32 ; struct _s { uint32 bitfield_first : ) uint32 bitfield_last : } Name of union is concatenated from all register names within input group of registers . Arguments : regGroup List of IP - XACT register objects .
def write_reg_group_union(self, regGroup):
		fielDecls = []
		enumDecl = []
		unName = self.prefix + "_"
		for (j,reg) in enumerate(regGroup):
			for (i,field) in enumerate(sorted(reg.field, key=lambda a: a.bitOffset)):
				fieldDecl = self.create_reg_field_decl(reg, field)
				fieldDecl.comment = None
				if (i == 0):
					fieldDecl.comment = reg.name.upper()
				fielDecls.append(fieldDecl)
			unName += reg.name.lower()
			if (j != len(regGroup) - 1):
				unName += "_"
		enumDecl = []
		unsigned_decl = LanDeclaration("u{}".format(self.wrdWidthBit), value=0)
		unsigned_decl.type = "uint{}_t".format(self.wrdWidthBit)
		unsigned_decl.gap = 1
		enumDecl.append(unsigned_decl)
		enumDecl.append(fielDecls)
		self.headerGen.create_union(unName, enumDecl)
		self.headerGen.wr_nl()
def write_reg_group_union ( self , regGroup ) : fielDecls = [ ] enumDecl = [ ] unName = self . prefix + "_" for ( j , reg ) in enumerate ( regGroup ) : for ( i , field ) in enumerate ( sorted ( reg . field , key = lambda a : a . bitOffset ) ) : fieldDecl = self . create_reg_field_decl ( reg , field ) fieldDecl . comment = None if ( i == 0 ) : fieldDecl . comment = reg . name . upper ( ) fielDecls . append ( fieldDecl ) unName += reg . name . lower ( ) if ( j != len ( regGroup ) - 1 ) : unName += "_" enumDecl = [ ] unsigned_decl = LanDeclaration ( "u{}" . format ( self . wrdWidthBit ) , value = 0 ) unsigned_decl . type = "uint{}_t" . format ( self . wrdWidthBit ) unsigned_decl . gap = 1 enumDecl . append ( unsigned_decl ) enumDecl . append ( fielDecls ) self . headerGen . create_union ( unName , enumDecl ) self . headerGen . wr_nl ( )
Write group of IP-XACT register objects as a single union to generator
output.
Write group of IP - XACT register objects as a single union to generator output .
"""
		Write group of IP-XACT register objects as a single union to generator
		output. Group of registers should reside within the same memory word.

		Example of union with 32 bit wrdWidth:
			union <joined_name> {
				uint32 u32;
				struct <joined_name>_s {
					uint32  bitfield_first : <width_of_bitfield>)
					  ...
					uint32  bitfield_last  : <width_of_bitfield>  
				}

		Name of union <joined_name> is concatenated from all register names
		within input group of registers.
		Arguments:
			regGroup 	List of IP-XACT register objects.
		""" # Create declaration objects for each field of IP-XACT register. # Append register name to the union name # Create declaration of u<wrd_width> union member # Append declarations to the list of declarations within an enum
self
regGroup