ip_xact/vhdl_reg_map_generator.py
def create_reg_ports(self, block, signDict):
		"""
		Creates declarations for Output/Input ports of an entity which
		correspond to values Written / Read  to / from registers. 
		Declarations have following format:
			signal <block_name>_in   : in <block_name>_in_t
			signal <block_name>_out  : in <block_name>_out_t
		Declarations are appended to signDict dictionary.
		"""
		if (not checkIsDict(signDict)):
			return
			
		reg_ports = ["out", "in"]

		for reg_port in reg_ports:
			port = LanDeclaration(block.name + "_" + reg_port, value=None)
			port.direction = reg_port
			port.type = block.name + "_" + reg_port + "_t"
			port.bitWidth = 0
			port.specifier = "signal"
			signDict[port.name] = port

		Creates declarations for Output/Input ports of an entity which
		correspond to values Written / Read  to / from registers. 
		Declarations have following format:
			signal <block_name>_in   : in <block_name>_in_t
			signal <block_name>_out  : in <block_name>_out_t
		Declarations are appended to signDict dictionary.
		
Creates declarations for Output/Input ports of an entity which
correspond to values Written / Read  to / from registers.
Declarations have following format:
signal _in   : in _in_t
signal _out  : in _out_t
Declarations are appended to signDict dictionary.
Creates declarations for Output / Input ports of an entity which correspond to values Written / Read to / from registers . Declarations have following format : signal _in : in _in_t signal _out : in _out_t Declarations are appended to signDict dictionary .
def create_reg_ports(self, block, signDict):
		if (not checkIsDict(signDict)):
			return
		reg_ports = ["out", "in"]
		for reg_port in reg_ports:
			port = LanDeclaration(block.name + "_" + reg_port, value=None)
			port.direction = reg_port
			port.type = block.name + "_" + reg_port + "_t"
			port.bitWidth = 0
			port.specifier = "signal"
			signDict[port.name] = port
def create_reg_ports ( self , block , signDict ) : if ( not checkIsDict ( signDict ) ) : return reg_ports = [ "out" , "in" ] for reg_port in reg_ports : port = LanDeclaration ( block . name + "_" + reg_port , value = None ) port . direction = reg_port port . type = block . name + "_" + reg_port + "_t" port . bitWidth = 0 port . specifier = "signal" signDict [ port . name ] = port
Creates declarations for Output/Input ports of an entity which
correspond to values Written / Read  to / from registers.
Creates declarations for Output / Input ports of an entity which correspond to values Written / Read to / from registers .
"""
		Creates declarations for Output/Input ports of an entity which
		correspond to values Written / Read  to / from registers. 
		Declarations have following format:
			signal <block_name>_in   : in <block_name>_in_t
			signal <block_name>_out  : in <block_name>_out_t
		Declarations are appended to signDict dictionary.
		"""
self
block
signDict