ip_xact/vhdl_tb_addr_generator.py
def write_cmn_types(self):
		"""
		Write common types used for generation of register list.
		"""
		self.vhdlGen.write_comment("Common types", gap = 2)

		# Write register type enum
		reg_type_enum = []
		reg_type_enum.append(LanDeclaration("reg_none", ""))
		reg_type_enum.append(LanDeclaration("reg_write_only", ""))
		reg_type_enum.append(LanDeclaration("reg_read_only", ""))
		reg_type_enum.append(LanDeclaration("reg_read_write", ""))
		reg_type_enum.append(LanDeclaration("reg_read_write_once", ""))
		for enum_elem in reg_type_enum:
			enum_elem.gap = 4

		self.vhdlGen.create_enum("t_reg_type", reg_type_enum, gap = 2)
		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_nl()

		# Write register record
		reg_addr = LanDeclaration("address", "")
		reg_addr.type = "std_logic_vector"
		reg_addr.bitWidth = 12
		reg_addr.gap = 4

		reg_size = LanDeclaration("size", "")
		reg_size.type = "integer"
		reg_size.gap = 4

		reg_type = LanDeclaration("reg_type", "")
		reg_type.type = "t_reg_type"
		reg_type.gap = 4

		reset_val = LanDeclaration("reset_val", "")
		reset_val.type = "std_logic_vector"
		reset_val.gap = 4
		reset_val.bitWidth = self.wrdWidthBit

		implemented = LanDeclaration("is_implem","")
		implemented.type = "std_logic_vector"
		implemented.gap = 4
		implemented.bitWidth = self.wrdWidthBit

		self.vhdlGen.create_structure("t_memory_reg", \
			[reg_addr, reg_size, reg_type, reset_val, implemented], gap = 2)

		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_nl()

		Write common types used for generation of register list.
		
Write common types used for generation of register list.
Write common types used for generation of register list .
def write_cmn_types(self):
		self.vhdlGen.write_comment("Common types", gap = 2)
		reg_type_enum = []
		reg_type_enum.append(LanDeclaration("reg_none", ""))
		reg_type_enum.append(LanDeclaration("reg_write_only", ""))
		reg_type_enum.append(LanDeclaration("reg_read_only", ""))
		reg_type_enum.append(LanDeclaration("reg_read_write", ""))
		reg_type_enum.append(LanDeclaration("reg_read_write_once", ""))
		for enum_elem in reg_type_enum:
			enum_elem.gap = 4
		self.vhdlGen.create_enum("t_reg_type", reg_type_enum, gap = 2)
		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_nl()
		reg_addr = LanDeclaration("address", "")
		reg_addr.type = "std_logic_vector"
		reg_addr.bitWidth = 12
		reg_addr.gap = 4
		reg_size = LanDeclaration("size", "")
		reg_size.type = "integer"
		reg_size.gap = 4
		reg_type = LanDeclaration("reg_type", "")
		reg_type.type = "t_reg_type"
		reg_type.gap = 4
		reset_val = LanDeclaration("reset_val", "")
		reset_val.type = "std_logic_vector"
		reset_val.gap = 4
		reset_val.bitWidth = self.wrdWidthBit
		implemented = LanDeclaration("is_implem","")
		implemented.type = "std_logic_vector"
		implemented.gap = 4
		implemented.bitWidth = self.wrdWidthBit
		self.vhdlGen.create_structure("t_memory_reg", \
			[reg_addr, reg_size, reg_type, reset_val, implemented], gap = 2)
		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_nl()
def write_cmn_types ( self ) : self . vhdlGen . write_comment ( "Common types" , gap = 2 ) reg_type_enum = [ ] reg_type_enum . append ( LanDeclaration ( "reg_none" , "" ) ) reg_type_enum . append ( LanDeclaration ( "reg_write_only" , "" ) ) reg_type_enum . append ( LanDeclaration ( "reg_read_only" , "" ) ) reg_type_enum . append ( LanDeclaration ( "reg_read_write" , "" ) ) reg_type_enum . append ( LanDeclaration ( "reg_read_write_once" , "" ) ) for enum_elem in reg_type_enum : enum_elem . gap = 4 self . vhdlGen . create_enum ( "t_reg_type" , reg_type_enum , gap = 2 ) self . vhdlGen . wr_nl ( ) self . vhdlGen . wr_nl ( ) reg_addr = LanDeclaration ( "address" , "" ) reg_addr . type = "std_logic_vector" reg_addr . bitWidth = 12 reg_addr . gap = 4 reg_size = LanDeclaration ( "size" , "" ) reg_size . type = "integer" reg_size . gap = 4 reg_type = LanDeclaration ( "reg_type" , "" ) reg_type . type = "t_reg_type" reg_type . gap = 4 reset_val = LanDeclaration ( "reset_val" , "" ) reset_val . type = "std_logic_vector" reset_val . gap = 4 reset_val . bitWidth = self . wrdWidthBit implemented = LanDeclaration ( "is_implem" , "" ) implemented . type = "std_logic_vector" implemented . gap = 4 implemented . bitWidth = self . wrdWidthBit self . vhdlGen . create_structure ( "t_memory_reg" , [ reg_addr , reg_size , reg_type , reset_val , implemented ] , gap = 2 ) self . vhdlGen . wr_nl ( ) self . vhdlGen . wr_nl ( )
Write common types used for generation of register list.
Write common types used for generation of register list .
"""
		Write common types used for generation of register list.
		""" # Write register type enum # Write register record
self