ip_xact/vhdl_reg_map_generator.py
def create_read_data_mux_ena(self):
		"""
		Create driver for read data multiplexor enable signal. If read data
		should be cleared after transaction, enable is constantly at logic 1,
		thus next cycle will data will be cleared, read mux  output flop is
		permanently enabled. If read data should not be cleared, flop is
		enabled only by new transaction.
		"""

		self.hdlGen.write_comment("Read data multiplexor enable ", gap = 4)
		
		# Read data should be kept, enable is driven by read signal which is
		# active for each read transaction
		self.hdlGen.create_if_generate(name="read_data_keep_gen",
				condition="clear_read_data".upper(), value="false", gap = 4)

		self.hdlGen.create_signal_connection(result="read_mux_ena", 
												driver="read and cs", gap=8)

		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")

		# Read data should be cleared, enable is constant 1, thus at next cycle
		# all byte enables will be zero and all zeroes will propagate on
		# outputs.
		self.hdlGen.create_if_generate(name="read_data_clear_gen",
				condition="clear_read_data".upper(), value="true", gap = 4)

		# Note that this approach will clock register value to the data mux
		# output also when write is executed to this register. We don't
		# mind this, since register reads has no side effects! Side effects
		# are implemented via access_signallers and thus choosing the
		# register value by read data mux even when it is not needed is
		# sth we don't mind.
		self.hdlGen.create_signal_connection(result="read_mux_ena",
												driver="'1'", gap=8)

		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")

		Create driver for read data multiplexor enable signal. If read data
		should be cleared after transaction, enable is constantly at logic 1,
		thus next cycle will data will be cleared, read mux  output flop is
		permanently enabled. If read data should not be cleared, flop is
		enabled only by new transaction.
		
Create driver for read data multiplexor enable signal. If read data
should be cleared after transaction, enable is constantly at logic 1,
thus next cycle will data will be cleared, read mux  output flop is
permanently enabled. If read data should not be cleared, flop is
enabled only by new transaction.
Create driver for read data multiplexor enable signal . If read data should be cleared after transaction enable is constantly at logic 1 thus next cycle will data will be cleared read mux output flop is permanently enabled . If read data should not be cleared flop is enabled only by new transaction .
def create_read_data_mux_ena(self):
		self.hdlGen.write_comment("Read data multiplexor enable ", gap = 4)
		self.hdlGen.create_if_generate(name="read_data_keep_gen",
				condition="clear_read_data".upper(), value="false", gap = 4)
		self.hdlGen.create_signal_connection(result="read_mux_ena", 
												driver="read and cs", gap=8)
		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")
		self.hdlGen.create_if_generate(name="read_data_clear_gen",
				condition="clear_read_data".upper(), value="true", gap = 4)
		self.hdlGen.create_signal_connection(result="read_mux_ena",
												driver="'1'", gap=8)
		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")
def create_read_data_mux_ena ( self ) : self . hdlGen . write_comment ( "Read data multiplexor enable " , gap = 4 ) self . hdlGen . create_if_generate ( name = "read_data_keep_gen" , condition = "clear_read_data" . upper ( ) , value = "false" , gap = 4 ) self . hdlGen . create_signal_connection ( result = "read_mux_ena" , driver = "read and cs" , gap = 8 ) self . hdlGen . commit_append_line ( 1 ) self . hdlGen . wr_line ( "\n" ) self . hdlGen . create_if_generate ( name = "read_data_clear_gen" , condition = "clear_read_data" . upper ( ) , value = "true" , gap = 4 ) self . hdlGen . create_signal_connection ( result = "read_mux_ena" , driver = "'1'" , gap = 8 ) self . hdlGen . commit_append_line ( 1 ) self . hdlGen . wr_line ( "\n" )
Create driver for read data multiplexor enable signal.
Create driver for read data multiplexor enable signal .
"""
		Create driver for read data multiplexor enable signal. If read data
		should be cleared after transaction, enable is constantly at logic 1,
		thus next cycle will data will be cleared, read mux  output flop is
		permanently enabled. If read data should not be cleared, flop is
		enabled only by new transaction.
		""" # Read data should be kept, enable is driven by read signal which is # active for each read transaction # Read data should be cleared, enable is constant 1, thus at next cycle # all byte enables will be zero and all zeroes will propagate on # outputs. # Note that this approach will clock register value to the data mux # output also when write is executed to this register. We don't # mind this, since register reads has no side effects! Side effects # are implemented via access_signallers and thus choosing the # register value by read data mux even when it is not needed is # sth we don't mind.
self