ip_xact/vhdl_reg_map_generator.py
def fill_reg_ports(self, block, reg, reg_inst):
		"""
		Fill ports for register instance from IP-XACT register object
		"""
		reg_inst.ports["clk_sys"].value = "clk_sys"
		reg_inst.ports["res_n"].value = "res_n"

		reg_value = (block.name + "_out_i." + reg.name).lower()
		reg_inst.ports["reg_value"].value = reg_value

		# Calculate data input indices within a memory word
		l_ind = (reg.addressOffset * 8) % self.wrdWidthBit
		h_ind = l_ind + reg.size - 1
		reg_inst.ports["data_in"].value = self.hdlGen.format_vector_range("w_data", h_ind, l_ind);
		reg_inst.ports["write"].value = "write"

		reg_sel_index = self.get_wrd_index(block, reg) - 1
		reg_inst.ports["cs"].value = self.hdlGen.format_vector_index("reg_sel", reg_sel_index)

		# Calculate byte enable index / indices from position of register within a
		# memory word.
		reg_inst.ports["w_be"].value = self.calc_reg_byte_enable_vector(reg)

		# Connect lock signal
		reg_inst.ports["lock"].value = self.get_reg_lock(reg)[2]

		Fill ports for register instance from IP-XACT register object
		
Fill ports for register instance from IP-XACT register object
Fill ports for register instance from IP - XACT register object
def fill_reg_ports(self, block, reg, reg_inst):
		reg_inst.ports["clk_sys"].value = "clk_sys"
		reg_inst.ports["res_n"].value = "res_n"
		reg_value = (block.name + "_out_i." + reg.name).lower()
		reg_inst.ports["reg_value"].value = reg_value
		l_ind = (reg.addressOffset * 8) % self.wrdWidthBit
		h_ind = l_ind + reg.size - 1
		reg_inst.ports["data_in"].value = self.hdlGen.format_vector_range("w_data", h_ind, l_ind);
		reg_inst.ports["write"].value = "write"
		reg_sel_index = self.get_wrd_index(block, reg) - 1
		reg_inst.ports["cs"].value = self.hdlGen.format_vector_index("reg_sel", reg_sel_index)
		reg_inst.ports["w_be"].value = self.calc_reg_byte_enable_vector(reg)
		reg_inst.ports["lock"].value = self.get_reg_lock(reg)[2]
def fill_reg_ports ( self , block , reg , reg_inst ) : reg_inst . ports [ "clk_sys" ] . value = "clk_sys" reg_inst . ports [ "res_n" ] . value = "res_n" reg_value = ( block . name + "_out_i." + reg . name ) . lower ( ) reg_inst . ports [ "reg_value" ] . value = reg_value l_ind = ( reg . addressOffset * 8 ) % self . wrdWidthBit h_ind = l_ind + reg . size - 1 reg_inst . ports [ "data_in" ] . value = self . hdlGen . format_vector_range ( "w_data" , h_ind , l_ind ) ; reg_inst . ports [ "write" ] . value = "write" reg_sel_index = self . get_wrd_index ( block , reg ) - 1 reg_inst . ports [ "cs" ] . value = self . hdlGen . format_vector_index ( "reg_sel" , reg_sel_index ) reg_inst . ports [ "w_be" ] . value = self . calc_reg_byte_enable_vector ( reg ) reg_inst . ports [ "lock" ] . value = self . get_reg_lock ( reg ) [ 2 ]
Fill ports for register instance from IP-XACT register object
Fill ports for register instance from IP - XACT register object
"""
		Fill ports for register instance from IP-XACT register object
		""" # Calculate data input indices within a memory word # Calculate byte enable index / indices from position of register within a # memory word. # Connect lock signal
self
block
reg
reg_inst