ip_xact/vhdl_reg_map_generator.py
def create_reg_access_cover_points(self, block):
		"""
		Create cover points to monitor functional coverage within the
		generated block. Following points are created:
			1. Write cover point for each writable register.
			2. Read cover point for each readable register.
		"""
		# Add comments for readabiliy
		self.hdlGen.write_comment("<RELEASE_OFF>", gap = 4, small=True)
		self.hdlGen.write_comment("Functional coverage", gap = 4)

		# Specify clock for PSL
		if (type(self.hdlGen) == VhdlGenerator):
			self.hdlGen.write_comment(" psl default clock is " \
				"rising_edge(clk_sys);", gap = 4, small=True)

		# Go through the registers
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):

			# Create write psl coverage for every writable register
			if (self.reg_has_access_type(reg, ["write"])):
				self.create_reg_access_cover_point(block, reg, "write");

			# Create read psl coverage for every readable register
			if (self.reg_has_access_type(reg, ["read"])):
				self.create_reg_access_cover_point(block, reg, "read");

		# Add release ON
		self.hdlGen.write_comment("<RELEASE_ON>", gap = 4, small=True)

		Create cover points to monitor functional coverage within the
		generated block. Following points are created:
			1. Write cover point for each writable register.
			2. Read cover point for each readable register.
		
Create cover points to monitor functional coverage within the
generated block. Following points are created:
1. Write cover point for each writable register.
2. Read cover point for each readable register.
Create cover points to monitor functional coverage within the generated block . Following points are created : 1 . Write cover point for each writable register . 2 . Read cover point for each readable register .
def create_reg_access_cover_points(self, block):
		self.hdlGen.write_comment("<RELEASE_OFF>", gap = 4, small=True)
		self.hdlGen.write_comment("Functional coverage", gap = 4)
		if (type(self.hdlGen) == VhdlGenerator):
			self.hdlGen.write_comment(" psl default clock is " \
				"rising_edge(clk_sys);", gap = 4, small=True)
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
			if (self.reg_has_access_type(reg, ["write"])):
				self.create_reg_access_cover_point(block, reg, "write");
			if (self.reg_has_access_type(reg, ["read"])):
				self.create_reg_access_cover_point(block, reg, "read");
		self.hdlGen.write_comment("<RELEASE_ON>", gap = 4, small=True)
def create_reg_access_cover_points ( self , block ) : self . hdlGen . write_comment ( "<RELEASE_OFF>" , gap = 4 , small = True ) self . hdlGen . write_comment ( "Functional coverage" , gap = 4 ) if ( type ( self . hdlGen ) == VhdlGenerator ) : self . hdlGen . write_comment ( " psl default clock is " "rising_edge(clk_sys);" , gap = 4 , small = True ) for i , reg in enumerate ( sorted ( block . register , key = lambda a : a . addressOffset ) ) : if ( self . reg_has_access_type ( reg , [ "write" ] ) ) : self . create_reg_access_cover_point ( block , reg , "write" ) ; if ( self . reg_has_access_type ( reg , [ "read" ] ) ) : self . create_reg_access_cover_point ( block , reg , "read" ) ; self . hdlGen . write_comment ( "<RELEASE_ON>" , gap = 4 , small = True )
Create cover points to monitor functional coverage within the
generated block.
Create cover points to monitor functional coverage within the generated block .
"""
		Create cover points to monitor functional coverage within the
		generated block. Following points are created:
			1. Write cover point for each writable register.
			2. Read cover point for each readable register.
		""" # Add comments for readabiliy # Specify clock for PSL # Go through the registers # Create write psl coverage for every writable register # Create read psl coverage for every readable register # Add release ON
self
block