ip_xact/vhdl_reg_map_generator.py
def create_access_signaller(self, block, reg):
		"""
		Create access signaller components for registers which have this feature
		enabled.
		"""
		path = os.path.join(ROOT_PATH, self.template_sources["access_signaller_template_path"])
		signaller_inst = self.hdlGen.load_entity_template(path)
		signaller_inst.isInstance = True
		signaller_inst.intType = "entity"
		signaller_inst.value = reg.name.lower() + "_access_signaller_comp"

		# Fill generic values of access signaller
		self.fill_access_signaller_generics(reg, signaller_inst)

		# Fill ports of access signaller
		self.fill_access_signaller_ports(block, reg, signaller_inst)

		self.hdlGen.write_comment(reg.name.upper() + " access signallization", gap = 4)
		
		# Create component of signaller
		self.hdlGen.format_entity_decl(signaller_inst)
		self.hdlGen.create_comp_instance(signaller_inst)

		Create access signaller components for registers which have this feature
		enabled.
		
Create access signaller components for registers which have this feature
enabled.
Create access signaller components for registers which have this feature enabled .
def create_access_signaller(self, block, reg):
		path = os.path.join(ROOT_PATH, self.template_sources["access_signaller_template_path"])
		signaller_inst = self.hdlGen.load_entity_template(path)
		signaller_inst.isInstance = True
		signaller_inst.intType = "entity"
		signaller_inst.value = reg.name.lower() + "_access_signaller_comp"
		self.fill_access_signaller_generics(reg, signaller_inst)
		self.fill_access_signaller_ports(block, reg, signaller_inst)
		self.hdlGen.write_comment(reg.name.upper() + " access signallization", gap = 4)
		self.hdlGen.format_entity_decl(signaller_inst)
		self.hdlGen.create_comp_instance(signaller_inst)
def create_access_signaller ( self , block , reg ) : path = os . path . join ( ROOT_PATH , self . template_sources [ "access_signaller_template_path" ] ) signaller_inst = self . hdlGen . load_entity_template ( path ) signaller_inst . isInstance = True signaller_inst . intType = "entity" signaller_inst . value = reg . name . lower ( ) + "_access_signaller_comp" self . fill_access_signaller_generics ( reg , signaller_inst ) self . fill_access_signaller_ports ( block , reg , signaller_inst ) self . hdlGen . write_comment ( reg . name . upper ( ) + " access signallization" , gap = 4 ) self . hdlGen . format_entity_decl ( signaller_inst ) self . hdlGen . create_comp_instance ( signaller_inst )
Create access signaller components for registers which have this feature
enabled.
Create access signaller components for registers which have this feature enabled .
"""
		Create access signaller components for registers which have this feature
		enabled.
		""" # Fill generic values of access signaller # Fill ports of access signaller # Create component of signaller
self
block
reg