ip_xact/vhdl_reg_map_generator.py
def create_read_data_mux_in(self, block):
		"""
		Create driver for read data multiplexor input signal. Read data
		multiplexor is a long vector with read data concatenated to
		long std_logic vector.
		"""
		self.hdlGen.write_comment("Read data driver", gap = 2)
		self.hdlGen.push_parallel_assignment("read_data_mux_in")
		self.hdlGen.wr_line("\n")

		# Check each word in the memory block, Start from highest address
		# since highest bits in std_logic_vector correspond to highest
		# address!
		[low_addr, high_addr] = self.calc_blk_wrd_span(block, ["read"])
		high_addr += self.wrdWidthByte

		# TODO: This could be written with concatenation!!
		for addr in reversed(range(low_addr, high_addr, self.wrdWidthByte)):

			# Create comment with word address
			self.hdlGen.write_comment("Adress:" + str(addr), gap=4, small=True)

			# Search for all registers which are also "read" in given word
			regs_in_wrd = self.get_regs_from_word(addr, block)
			wrd_value = self.create_read_wrd_from_regs(regs_in_wrd, block)

			self.hdlGen.wr_line(wrd_value)

			if (addr != low_addr):
				self.hdlGen.wr_line(" &\n")
			else:
				break
			self.hdlGen.wr_line("\n")

		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")

		Create driver for read data multiplexor input signal. Read data
		multiplexor is a long vector with read data concatenated to
		long std_logic vector.
		
Create driver for read data multiplexor input signal. Read data
multiplexor is a long vector with read data concatenated to
long std_logic vector.
Create driver for read data multiplexor input signal . Read data multiplexor is a long vector with read data concatenated to long std_logic vector .
def create_read_data_mux_in(self, block):
		self.hdlGen.write_comment("Read data driver", gap = 2)
		self.hdlGen.push_parallel_assignment("read_data_mux_in")
		self.hdlGen.wr_line("\n")
		[low_addr, high_addr] = self.calc_blk_wrd_span(block, ["read"])
		high_addr += self.wrdWidthByte
		for addr in reversed(range(low_addr, high_addr, self.wrdWidthByte)):
			self.hdlGen.write_comment("Adress:" + str(addr), gap=4, small=True)
			regs_in_wrd = self.get_regs_from_word(addr, block)
			wrd_value = self.create_read_wrd_from_regs(regs_in_wrd, block)
			self.hdlGen.wr_line(wrd_value)
			if (addr != low_addr):
				self.hdlGen.wr_line(" &\n")
			else:
				break
			self.hdlGen.wr_line("\n")
		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")
def create_read_data_mux_in ( self , block ) : self . hdlGen . write_comment ( "Read data driver" , gap = 2 ) self . hdlGen . push_parallel_assignment ( "read_data_mux_in" ) self . hdlGen . wr_line ( "\n" ) [ low_addr , high_addr ] = self . calc_blk_wrd_span ( block , [ "read" ] ) high_addr += self . wrdWidthByte for addr in reversed ( range ( low_addr , high_addr , self . wrdWidthByte ) ) : self . hdlGen . write_comment ( "Adress:" + str ( addr ) , gap = 4 , small = True ) regs_in_wrd = self . get_regs_from_word ( addr , block ) wrd_value = self . create_read_wrd_from_regs ( regs_in_wrd , block ) self . hdlGen . wr_line ( wrd_value ) if ( addr != low_addr ) : self . hdlGen . wr_line ( " &\n" ) else : break self . hdlGen . wr_line ( "\n" ) self . hdlGen . commit_append_line ( 1 ) self . hdlGen . wr_line ( "\n" )
Create driver for read data multiplexor input signal.
Create driver for read data multiplexor input signal .
"""
		Create driver for read data multiplexor input signal. Read data
		multiplexor is a long vector with read data concatenated to
		long std_logic vector.
		""" # Check each word in the memory block, Start from highest address # since highest bits in std_logic_vector correspond to highest # address! # TODO: This could be written with concatenation!! # Create comment with word address # Search for all registers which are also "read" in given word
self
block