ip_xact/vhdl_addr_generator.py
def write_addrbl_head(self, addressBlock):
		""" 
		Write IP-XACT address block as VHDL constant to generator output.
		Arguments:
			addressBlock	Address block to write (parsed from pyXact framework)
		"""
		# Write capital comment with name of the address Block
		self.vhdlGen.write_comm_line()
		self.vhdlGen.write_comment("Address block: {}".format(addressBlock.name), 2)
		self.vhdlGen.write_comm_line()
		
		# Write the VHDL constant for Address block offset defined as:
		#	block.baseAddress/block.range
		bitWidth = 4 # TODO: So far not bound to IP-XACT
		decl = LanDeclaration(addressBlock.name+"_BLOCK", 
					addressBlock.baseAddress/addressBlock.range,
					"std_logic", bitWidth, "constant", 80)
		self.vhdlGen.write_decl(decl)
		self.vhdlGen.wr_nl()
 
		Write IP-XACT address block as VHDL constant to generator output.
		Arguments:
			addressBlock	Address block to write (parsed from pyXact framework)
		
Write IP-XACT address block as VHDL constant to generator output.
Arguments:
addressBlock    Address block to write (parsed from pyXact framework)
Write IP - XACT address block as VHDL constant to generator output . Arguments : addressBlock Address block to write ( parsed from pyXact framework )
def write_addrbl_head(self, addressBlock):
		self.vhdlGen.write_comm_line()
		self.vhdlGen.write_comment("Address block: {}".format(addressBlock.name), 2)
		self.vhdlGen.write_comm_line()
		bitWidth = 4 
		decl = LanDeclaration(addressBlock.name+"_BLOCK", 
					addressBlock.baseAddress/addressBlock.range,
					"std_logic", bitWidth, "constant", 80)
		self.vhdlGen.write_decl(decl)
		self.vhdlGen.wr_nl()
def write_addrbl_head ( self , addressBlock ) : self . vhdlGen . write_comm_line ( ) self . vhdlGen . write_comment ( "Address block: {}" . format ( addressBlock . name ) , 2 ) self . vhdlGen . write_comm_line ( ) bitWidth = 4 decl = LanDeclaration ( addressBlock . name + "_BLOCK" , addressBlock . baseAddress / addressBlock . range , "std_logic" , bitWidth , "constant" , 80 ) self . vhdlGen . write_decl ( decl ) self . vhdlGen . wr_nl ( )
Write IP-XACT address block as VHDL constant to generator output.
Write IP - XACT address block as VHDL constant to generator output .
""" 
		Write IP-XACT address block as VHDL constant to generator output.
		Arguments:
			addressBlock	Address block to write (parsed from pyXact framework)
		""" # Write capital comment with name of the address Block # Write the VHDL constant for Address block offset defined as: #	block.baseAddress/block.range # TODO: So far not bound to IP-XACT
self
addressBlock