languages/gen_vhdl.py
def is_valid_dir(self, direction):
		"""
		Checks if specified direction is valid in VHDL.
		Accepts: in, out, inout, buffer 
		"""
		acceptDirs = ["in", "out", "buffer", "inout"]
		for acceptDir in acceptDirs:
			if (direction == acceptDir):
				return True

		return False

		Checks if specified direction is valid in VHDL.
		Accepts: in, out, inout, buffer 
		
Checks if specified direction is valid in VHDL.
Accepts: in, out, inout, buffer
Checks if specified direction is valid in VHDL . Accepts : in out inout buffer
def is_valid_dir(self, direction):
		acceptDirs = ["in", "out", "buffer", "inout"]
		for acceptDir in acceptDirs:
			if (direction == acceptDir):
				return True
		return False
def is_valid_dir ( self , direction ) : acceptDirs = [ "in" , "out" , "buffer" , "inout" ] for acceptDir in acceptDirs : if ( direction == acceptDir ) : return True return False
Checks if specified direction is valid in VHDL.
Checks if specified direction is valid in VHDL .
"""
		Checks if specified direction is valid in VHDL.
		Accepts: in, out, inout, buffer 
		"""
self
direction