ip_xact/vhdl_reg_map_generator.py
def write_reg_block(self, block):
		"""
        Create register block in VHDL from IP-XACT memory block object.
		"""

		# Write file introduction
		self.hdlGen.wr_nl()

		self.hdlGen.write_comment("Register map implementation of: " +
				block.name, gap = 0)
		self.hdlGen.write_gen_note()
		self.hdlGen.wr_nl()

		if (type(self.hdlGen) == VhdlGenerator):
			self.hdlGen.create_includes("ieee", ["std_logic_1164.all"])
			self.hdlGen.wr_nl()

		wrk_pkgs = [self.memMap.name.lower() + "_pkg.all", "cmn_reg_map_pkg.all"]
		self.hdlGen.create_includes("ctu_can_fd_rtl", wrk_pkgs)

		# Create entity definition
		entity = self.create_reg_block_template(block)

		# Create architecture of Register Block
		architecture = LanDeclaration("rtl", entity.name)
		architecture.intType = "architecture"
		intSignals = {}
		architecture.ports = intSignals

		# Write declaration of internal architecture signals
		self.create_internal_decls(block, intSignals)

		# Start architecture
		self.hdlGen.create_comp_instance(architecture)
		
		# Create instance of write address generator
		self.create_addr_decoder(block)

		# Create instance of registers
		self.create_write_reg_instances(block)

		# Create driver for enable signal for read data multiplexor
		self.create_read_data_mux_ena()

		# Create Data multiplexor for data reads
		self.create_read_data_mux_instance(block)

		# Create Driver for read data signal
		self.create_read_data_mux_in(block)
		self.create_read_data_mask_driver()

		# Create connections of internal write register record to output
		self.create_write_reg_record_driver(block)	
		self.hdlGen.wr_line("\n")

		# Create PSL functional coverage entries
		self.create_reg_access_cover_points(block)

		self.hdlGen.wr_line("\n")
		self.hdlGen.commit_append_lines_all()

        Create register block in VHDL from IP-XACT memory block object.
		
Create register block in VHDL from IP-XACT memory block object.
Create register block in VHDL from IP - XACT memory block object .
def write_reg_block(self, block):
		self.hdlGen.wr_nl()
		self.hdlGen.write_comment("Register map implementation of: " +
				block.name, gap = 0)
		self.hdlGen.write_gen_note()
		self.hdlGen.wr_nl()
		if (type(self.hdlGen) == VhdlGenerator):
			self.hdlGen.create_includes("ieee", ["std_logic_1164.all"])
			self.hdlGen.wr_nl()
		wrk_pkgs = [self.memMap.name.lower() + "_pkg.all", "cmn_reg_map_pkg.all"]
		self.hdlGen.create_includes("ctu_can_fd_rtl", wrk_pkgs)
		entity = self.create_reg_block_template(block)
		architecture = LanDeclaration("rtl", entity.name)
		architecture.intType = "architecture"
		intSignals = {}
		architecture.ports = intSignals
		self.create_internal_decls(block, intSignals)
		self.hdlGen.create_comp_instance(architecture)
		self.create_addr_decoder(block)
		self.create_write_reg_instances(block)
		self.create_read_data_mux_ena()
		self.create_read_data_mux_instance(block)
		self.create_read_data_mux_in(block)
		self.create_read_data_mask_driver()
		self.create_write_reg_record_driver(block)	
		self.hdlGen.wr_line("\n")
		self.create_reg_access_cover_points(block)
		self.hdlGen.wr_line("\n")
		self.hdlGen.commit_append_lines_all()
def write_reg_block ( self , block ) : self . hdlGen . wr_nl ( ) self . hdlGen . write_comment ( "Register map implementation of: " + block . name , gap = 0 ) self . hdlGen . write_gen_note ( ) self . hdlGen . wr_nl ( ) if ( type ( self . hdlGen ) == VhdlGenerator ) : self . hdlGen . create_includes ( "ieee" , [ "std_logic_1164.all" ] ) self . hdlGen . wr_nl ( ) wrk_pkgs = [ self . memMap . name . lower ( ) + "_pkg.all" , "cmn_reg_map_pkg.all" ] self . hdlGen . create_includes ( "ctu_can_fd_rtl" , wrk_pkgs ) entity = self . create_reg_block_template ( block ) architecture = LanDeclaration ( "rtl" , entity . name ) architecture . intType = "architecture" intSignals = { } architecture . ports = intSignals self . create_internal_decls ( block , intSignals ) self . hdlGen . create_comp_instance ( architecture ) self . create_addr_decoder ( block ) self . create_write_reg_instances ( block ) self . create_read_data_mux_ena ( ) self . create_read_data_mux_instance ( block ) self . create_read_data_mux_in ( block ) self . create_read_data_mask_driver ( ) self . create_write_reg_record_driver ( block ) self . hdlGen . wr_line ( "\n" ) self . create_reg_access_cover_points ( block ) self . hdlGen . wr_line ( "\n" ) self . hdlGen . commit_append_lines_all ( )
Create register block in VHDL from IP-XACT memory block object.
Create register block in VHDL from IP - XACT memory block object .
"""
        Create register block in VHDL from IP-XACT memory block object.
		""" # Write file introduction # Create entity definition # Create architecture of Register Block # Write declaration of internal architecture signals # Start architecture # Create instance of write address generator # Create instance of registers # Create driver for enable signal for read data multiplexor # Create Data multiplexor for data reads # Create Driver for read data signal # Create connections of internal write register record to output # Create PSL functional coverage entries
self
block