ip_xact/vhdl_reg_map_generator.py
def create_reg_instance(self, block, reg):
		"""
		Create register instance from IP-XACT register object. If "isPresent" property
        is set, parameter name is searched in IP-XACT input and it's name is used
        as generic condition for register presence.
		"""
		# Load register template path and create basic instance
		path = os.path.join(ROOT_PATH, self.template_sources["reg_template_path"])
		reg_inst = self.hdlGen.load_entity_template(path)
		reg_inst.isInstance = True
		reg_inst.intType = "entity"
		reg_inst.value = reg.name.lower() + "_reg_comp"

		self.hdlGen.write_comment(reg.name.upper() + " register", gap = 4)

		# Fill generics of reg map component			
		self.fill_reg_inst_generics(reg, reg_inst)

		# Fill Ports of reg map component
		self.fill_reg_ports(block, reg, reg_inst)

		# Write conditional generic expression if register isPresent property 
		# depends on IP-XACT Parameter
		if (reg.isPresent != ""):
			paramName = self.parameter_lookup(reg.isPresent)
			self.hdlGen.create_if_generate(reg.name + "_present_gen_t",
				paramName.upper(), "true", gap=4)

		# Format register instances and print it
		self.hdlGen.format_entity_decl(reg_inst)
		self.hdlGen.create_comp_instance(reg_inst)

		# Pop end of generate statement determined by isPresent property. Append
		# dummy drivers for case when parameter is false
		if (reg.isPresent != ""):
			self.hdlGen.commit_append_line(1)
			self.hdlGen.wr_line("\n")
			self.hdlGen.create_if_generate(reg.name + "_present_gen_f",
				paramName.upper(), "false", gap=4)

			rst_val = self.calc_reg_rstval_mask(reg)
			self.hdlGen.create_signal_connection(
				(block.name + "_out_i." + reg.name).lower(), rst_val, gap = 8)

			self.hdlGen.commit_append_line(1)
			self.hdlGen.wr_line("\n")

		Create register instance from IP-XACT register object. If "isPresent" property
        is set, parameter name is searched in IP-XACT input and it's name is used
        as generic condition for register presence.
		
Create register instance from IP-XACT register object. If "isPresent" property
is set, parameter name is searched in IP-XACT input and it's name is used
as generic condition for register presence.
Create register instance from IP - XACT register object . If " isPresent " property is set parameter name is searched in IP - XACT input and it ' s name is used as generic condition for register presence .
def create_reg_instance(self, block, reg):
		path = os.path.join(ROOT_PATH, self.template_sources["reg_template_path"])
		reg_inst = self.hdlGen.load_entity_template(path)
		reg_inst.isInstance = True
		reg_inst.intType = "entity"
		reg_inst.value = reg.name.lower() + "_reg_comp"
		self.hdlGen.write_comment(reg.name.upper() + " register", gap = 4)
		self.fill_reg_inst_generics(reg, reg_inst)
		self.fill_reg_ports(block, reg, reg_inst)
		if (reg.isPresent != ""):
			paramName = self.parameter_lookup(reg.isPresent)
			self.hdlGen.create_if_generate(reg.name + "_present_gen_t",
				paramName.upper(), "true", gap=4)
		self.hdlGen.format_entity_decl(reg_inst)
		self.hdlGen.create_comp_instance(reg_inst)
		if (reg.isPresent != ""):
			self.hdlGen.commit_append_line(1)
			self.hdlGen.wr_line("\n")
			self.hdlGen.create_if_generate(reg.name + "_present_gen_f",
				paramName.upper(), "false", gap=4)
			rst_val = self.calc_reg_rstval_mask(reg)
			self.hdlGen.create_signal_connection(
				(block.name + "_out_i." + reg.name).lower(), rst_val, gap = 8)
			self.hdlGen.commit_append_line(1)
			self.hdlGen.wr_line("\n")
def create_reg_instance ( self , block , reg ) : path = os . path . join ( ROOT_PATH , self . template_sources [ "reg_template_path" ] ) reg_inst = self . hdlGen . load_entity_template ( path ) reg_inst . isInstance = True reg_inst . intType = "entity" reg_inst . value = reg . name . lower ( ) + "_reg_comp" self . hdlGen . write_comment ( reg . name . upper ( ) + " register" , gap = 4 ) self . fill_reg_inst_generics ( reg , reg_inst ) self . fill_reg_ports ( block , reg , reg_inst ) if ( reg . isPresent != "" ) : paramName = self . parameter_lookup ( reg . isPresent ) self . hdlGen . create_if_generate ( reg . name + "_present_gen_t" , paramName . upper ( ) , "true" , gap = 4 ) self . hdlGen . format_entity_decl ( reg_inst ) self . hdlGen . create_comp_instance ( reg_inst ) if ( reg . isPresent != "" ) : self . hdlGen . commit_append_line ( 1 ) self . hdlGen . wr_line ( "\n" ) self . hdlGen . create_if_generate ( reg . name + "_present_gen_f" , paramName . upper ( ) , "false" , gap = 4 ) rst_val = self . calc_reg_rstval_mask ( reg ) self . hdlGen . create_signal_connection ( ( block . name + "_out_i." + reg . name ) . lower ( ) , rst_val , gap = 8 ) self . hdlGen . commit_append_line ( 1 ) self . hdlGen . wr_line ( "\n" )
Create register instance from IP-XACT register object.
Create register instance from IP - XACT register object .
"""
		Create register instance from IP-XACT register object. If "isPresent" property
        is set, parameter name is searched in IP-XACT input and it's name is used
        as generic condition for register presence.
		""" # Load register template path and create basic instance # Fill generics of reg map component			 # Fill Ports of reg map component # Write conditional generic expression if register isPresent property  # depends on IP-XACT Parameter # Format register instances and print it # Pop end of generate statement determined by isPresent property. Append # dummy drivers for case when parameter is false
self
block
reg