ip_xact/vhdl_reg_map_generator.py
def create_read_data_mux_instance(self, block):
		"""
        Create instance of Read data multiplexor.
		"""
		path = os.path.join(ROOT_PATH, self.template_sources["data_mux_template_path"])

		# Load data mux template
		data_mux = self.hdlGen.load_entity_template(path)
		data_mux.isInstance = True
		data_mux.value = (data_mux.name + "_"+ block.name + "_comp").lower()
		
		# FIll generic values
		data_mux.generics["data_out_width"].value = self.wrdWidthBit

		[low_addr, high_addr] = self.calc_blk_wrd_span(block, ["read"])
		high_addr += self.wrdWidthByte
		data_mux.generics["data_in_width"].value = (high_addr - low_addr) * 8;

		data_mux_indices = self.calc_addr_indices(block)
		data_mux_sel_width = data_mux_indices[0] - data_mux_indices[1] + 1 
		data_mux.generics["sel_width"].value = data_mux_sel_width

		data_mux.generics["registered_out"].value = "registered_read".upper()
		data_mux.generics["reset_polarity"].value = "reset_polarity".upper()

		# Connect ports
		data_mux.ports["clk_sys"].value = "clk_sys"
		data_mux.ports["res_n"].value = "res_n"

		addr_indices = self.calc_addr_indices(block)
		addr_str = self.hdlGen.format_vector_range("address", addr_indices[0], addr_indices[1])
		data_mux.ports["data_selector"].value = addr_str

		data_mux.ports["data_in"].value = "read_data_mux_in"
		data_mux.ports["data_mask_n"].value = "read_data_mask_n"
		data_mux.ports["data_out"].value = "r_data"

		# Enable data loading
		data_mux.ports["enable"].value = "read_mux_ena";

		self.hdlGen.write_comment("Read data multiplexor", gap=4)
		self.hdlGen.format_entity_decl(data_mux)
		self.hdlGen.create_comp_instance(data_mux)

        Create instance of Read data multiplexor.
		
Create instance of Read data multiplexor.
Create instance of Read data multiplexor .
def create_read_data_mux_instance(self, block):
		path = os.path.join(ROOT_PATH, self.template_sources["data_mux_template_path"])
		data_mux = self.hdlGen.load_entity_template(path)
		data_mux.isInstance = True
		data_mux.value = (data_mux.name + "_"+ block.name + "_comp").lower()
		data_mux.generics["data_out_width"].value = self.wrdWidthBit
		[low_addr, high_addr] = self.calc_blk_wrd_span(block, ["read"])
		high_addr += self.wrdWidthByte
		data_mux.generics["data_in_width"].value = (high_addr - low_addr) * 8;
		data_mux_indices = self.calc_addr_indices(block)
		data_mux_sel_width = data_mux_indices[0] - data_mux_indices[1] + 1 
		data_mux.generics["sel_width"].value = data_mux_sel_width
		data_mux.generics["registered_out"].value = "registered_read".upper()
		data_mux.generics["reset_polarity"].value = "reset_polarity".upper()
		data_mux.ports["clk_sys"].value = "clk_sys"
		data_mux.ports["res_n"].value = "res_n"
		addr_indices = self.calc_addr_indices(block)
		addr_str = self.hdlGen.format_vector_range("address", addr_indices[0], addr_indices[1])
		data_mux.ports["data_selector"].value = addr_str
		data_mux.ports["data_in"].value = "read_data_mux_in"
		data_mux.ports["data_mask_n"].value = "read_data_mask_n"
		data_mux.ports["data_out"].value = "r_data"
		data_mux.ports["enable"].value = "read_mux_ena";
		self.hdlGen.write_comment("Read data multiplexor", gap=4)
		self.hdlGen.format_entity_decl(data_mux)
		self.hdlGen.create_comp_instance(data_mux)
def create_read_data_mux_instance ( self , block ) : path = os . path . join ( ROOT_PATH , self . template_sources [ "data_mux_template_path" ] ) data_mux = self . hdlGen . load_entity_template ( path ) data_mux . isInstance = True data_mux . value = ( data_mux . name + "_" + block . name + "_comp" ) . lower ( ) data_mux . generics [ "data_out_width" ] . value = self . wrdWidthBit [ low_addr , high_addr ] = self . calc_blk_wrd_span ( block , [ "read" ] ) high_addr += self . wrdWidthByte data_mux . generics [ "data_in_width" ] . value = ( high_addr - low_addr ) * 8 ; data_mux_indices = self . calc_addr_indices ( block ) data_mux_sel_width = data_mux_indices [ 0 ] - data_mux_indices [ 1 ] + 1 data_mux . generics [ "sel_width" ] . value = data_mux_sel_width data_mux . generics [ "registered_out" ] . value = "registered_read" . upper ( ) data_mux . generics [ "reset_polarity" ] . value = "reset_polarity" . upper ( ) data_mux . ports [ "clk_sys" ] . value = "clk_sys" data_mux . ports [ "res_n" ] . value = "res_n" addr_indices = self . calc_addr_indices ( block ) addr_str = self . hdlGen . format_vector_range ( "address" , addr_indices [ 0 ] , addr_indices [ 1 ] ) data_mux . ports [ "data_selector" ] . value = addr_str data_mux . ports [ "data_in" ] . value = "read_data_mux_in" data_mux . ports [ "data_mask_n" ] . value = "read_data_mask_n" data_mux . ports [ "data_out" ] . value = "r_data" data_mux . ports [ "enable" ] . value = "read_mux_ena" ; self . hdlGen . write_comment ( "Read data multiplexor" , gap = 4 ) self . hdlGen . format_entity_decl ( data_mux ) self . hdlGen . create_comp_instance ( data_mux )
Create instance of Read data multiplexor.
Create instance of Read data multiplexor .
"""
        Create instance of Read data multiplexor.
		""" # Load data mux template # FIll generic values # Connect ports # Enable data loading
self
block