languages/gen_vhdl.py
def format_int_std_log_decl_val(self, decl):
		"""
		Format value of std_logic or std_logic_vector declaration given as
		integer value.
		"""
		strVal = ""

		# For single bit, this is written as '1', '0'
		if (decl.bitWidth == 1):
			strVal = "'{}'".format(decl.value)
			return strVal

		# If width is multiple of 4 -> use hex format, binary otherwise
		if (decl.bitWidth % 4 == 0):
			fmt = ':0{}x'.format(math.ceil(float(decl.bitWidth/4)))
			hPref = 'x' 
		else:
			fmt = ':0{}b'.format(math.ceil(float(decl.bitWidth)))
			hPref = ''
		fmt = '{'+fmt+'}'

		strVal = strVal + hPref+'"'+fmt.format(int(decl.value)).upper()+'"'

		## For longer logic vectors which have equal value of each
		## bit use (OTHERS => )
		if ((decl.bitWidth > 8 and hPref == '') or decl.bitWidth > 32):
			binStr = str(':0{}b'.format(decl.value))
			isBinaryEq = True
			for binChr in binStr[1:-1]:
				if (binChr != binStr[1]):
					isBinaryEq = False
			
			if (isBinaryEq):
				strVal = "(OTHERS => '{}')".format(binStr[1])

		return strVal

		Format value of std_logic or std_logic_vector declaration given as
		integer value.
		
Format value of std_logic or std_logic_vector declaration given as
integer value.
Format value of std_logic or std_logic_vector declaration given as integer value .
def format_int_std_log_decl_val(self, decl):
		strVal = ""
		if (decl.bitWidth == 1):
			strVal = "'{}'".format(decl.value)
			return strVal
		if (decl.bitWidth % 4 == 0):
			fmt = ':0{}x'.format(math.ceil(float(decl.bitWidth/4)))
			hPref = 'x' 
		else:
			fmt = ':0{}b'.format(math.ceil(float(decl.bitWidth)))
			hPref = ''
		fmt = '{'+fmt+'}'
		strVal = strVal + hPref+'"'+fmt.format(int(decl.value)).upper()+'"'
		if ((decl.bitWidth > 8 and hPref == '') or decl.bitWidth > 32):
			binStr = str(':0{}b'.format(decl.value))
			isBinaryEq = True
			for binChr in binStr[1:-1]:
				if (binChr != binStr[1]):
					isBinaryEq = False
			if (isBinaryEq):
				strVal = "(OTHERS => '{}')".format(binStr[1])
		return strVal
def format_int_std_log_decl_val ( self , decl ) : strVal = "" if ( decl . bitWidth == 1 ) : strVal = "'{}'" . format ( decl . value ) return strVal if ( decl . bitWidth % 4 == 0 ) : fmt = ':0{}x' . format ( math . ceil ( float ( decl . bitWidth / 4 ) ) ) hPref = 'x' else : fmt = ':0{}b' . format ( math . ceil ( float ( decl . bitWidth ) ) ) hPref = '' fmt = '{' + fmt + '}' strVal = strVal + hPref + '"' + fmt . format ( int ( decl . value ) ) . upper ( ) + '"' if ( ( decl . bitWidth > 8 and hPref == '' ) or decl . bitWidth > 32 ) : binStr = str ( ':0{}b' . format ( decl . value ) ) isBinaryEq = True for binChr in binStr [ 1 : - 1 ] : if ( binChr != binStr [ 1 ] ) : isBinaryEq = False if ( isBinaryEq ) : strVal = "(OTHERS => '{}')" . format ( binStr [ 1 ] ) return strVal
Format value of std_logic or std_logic_vector declaration given as
integer value.
Format value of std_logic or std_logic_vector declaration given as integer value .
"""
		Format value of std_logic or std_logic_vector declaration given as
		integer value.
		""" # For single bit, this is written as '1', '0' # If width is multiple of 4 -> use hex format, binary otherwise ## For longer logic vectors which have equal value of each ## bit use (OTHERS => )
self
decl