sonar/testbench.py
def _statement(self, condition, *args):
        """
        Add a line to the thread, which is a complete Systemverilog line that
        that will be inserted verbatim into the TB. Any variables used in the
        statement will be replaced.

        Args:
            condition (str): SV-compatible statement (e.g. wait(); or @();)
            args (int): Conditions can use variables and their values can be
            passed in as args
        """

        self.commands.append({"wait": {"key": condition, "args": args}})
        self._print_timestamp()

        Add a line to the thread, which is a complete Systemverilog line that
        that will be inserted verbatim into the TB. Any variables used in the
        statement will be replaced.

        Args:
            condition (str): SV-compatible statement (e.g. wait(); or @();)
            args (int): Conditions can use variables and their values can be
            passed in as args
        
Add a line to the thread, which is a complete Systemverilog line that
that will be inserted verbatim into the TB. Any variables used in the
statement will be replaced.

condition (str): SV-compatible statement ; or @();)
args (int): Conditions can use variables and their values can be
passed in as args
Add a line to the thread which is a complete Systemverilog line that that will be inserted verbatim into the TB . Any variables used in the statement will be replaced . condition ( str ) : SV - compatible statement ; or @ () ; ) args ( int ) : Conditions can use variables and their values can be passed in as args
def _statement(self, condition, *args):
        self.commands.append({"wait": {"key": condition, "args": args}})
        self._print_timestamp()
def _statement ( self , condition , * args ) : self . commands . append ( { "wait" : { "key" : condition , "args" : args } } ) self . _print_timestamp ( )
Add a line to the thread, which is a complete Systemverilog line that
that will be inserted verbatim into the TB.
Add a line to the thread which is a complete Systemverilog line that that will be inserted verbatim into the TB .
"""
        Add a line to the thread, which is a complete Systemverilog line that
        that will be inserted verbatim into the TB. Any variables used in the
        statement will be replaced.

        Args:
            condition (str): SV-compatible statement (e.g. wait(); or @();)
            args (int): Conditions can use variables and their values can be
            passed in as args
        """
self
condition