pgtt/mmu.py
def _sctlr() -> str:
    """
    Generate required value for SCTLR_ELn.
    """
    reg = Register(f"sctlr_el{args.el}")

    """
    Configurable bitfields present at all exception levels.
    """
    reg.field( 0,  0, "m", 1)    # MMU enabled
    reg.field( 2,  2, "c", 1)    # D-side access cacheability controlled by pgtables
    reg.field(12, 12, "i", 1),   # I-side access cacheability controlled by pgtables


    return hex(reg.value()[0])

    Generate required value for SCTLR_ELn.
    
Generate required value for SCTLR_ELn.
Generate required value for SCTLR_ELn .
def _sctlr() -> str:
    reg = Register(f"sctlr_el{args.el}")
    reg.field( 0,  0, "m", 1)    
    reg.field( 2,  2, "c", 1)    
    reg.field(12, 12, "i", 1),   
    return hex(reg.value()[0])
def _sctlr ( ) -> str : reg = Register ( f"sctlr_el{args.el}" ) """
    Configurable bitfields present at all exception levels.
    """ reg . field ( 0 , 0 , "m" , 1 ) reg . field ( 2 , 2 , "c" , 1 ) reg . field ( 12 , 12 , "i" , 1 ) , return hex ( reg . value ( ) [ 0 ] )
Generate required value for SCTLR_ELn.
Generate required value for SCTLR_ELn .
"""
    Generate required value for SCTLR_ELn.
    """ """
    Configurable bitfields present at all exception levels.
    """ # MMU enabled # D-side access cacheability controlled by pgtables # I-side access cacheability controlled by pgtables