languages/gen_vhdl.py
def write_connection(self, decl, specDir = False):
		"""
		Create component port or generic connection on VHDL entity.
		Arguments:
			decl     Declaration object
			specDir  If Direction should be specified in the connection
				     in VHDL comment   
		"""
		portDelim = ""
		if (decl.addSemicoln):
			portDelim = ","

		pref = " {} {} ".format(" " * decl.gap, decl.name)
		pref = pref + " " * (40 - len(pref)) + "=>"
		post = " {} {}".format(decl.value, portDelim)

		if (specDir and (decl.direction != None and decl.direction != "")):
			post = post + "-- {}".format(decl.direction)

		post = post + "\n"
		self.__wr_line(pref + post)

		Create component port or generic connection on VHDL entity.
		Arguments:
			decl     Declaration object
			specDir  If Direction should be specified in the connection
				     in VHDL comment   
		
Create component port or generic connection on VHDL entity.
Arguments:
decl     Declaration object
specDir  If Direction should be specified in the connection
in VHDL comment
Create component port or generic connection on VHDL entity . Arguments : decl Declaration object specDir If Direction should be specified in the connection in VHDL comment
def write_connection(self, decl, specDir = False):
		portDelim = ""
		if (decl.addSemicoln):
			portDelim = ","
		pref = " {} {} ".format(" " * decl.gap, decl.name)
		pref = pref + " " * (40 - len(pref)) + "=>"
		post = " {} {}".format(decl.value, portDelim)
		if (specDir and (decl.direction != None and decl.direction != "")):
			post = post + "-- {}".format(decl.direction)
		post = post + "\n"
		self.__wr_line(pref + post)
def write_connection ( self , decl , specDir = False ) : portDelim = "" if ( decl . addSemicoln ) : portDelim = "," pref = " {} {} " . format ( " " * decl . gap , decl . name ) pref = pref + " " * ( 40 - len ( pref ) ) + "=>" post = " {} {}" . format ( decl . value , portDelim ) if ( specDir and ( decl . direction != None and decl . direction != "" ) ) : post = post + "-- {}" . format ( decl . direction ) post = post + "\n" self . __wr_line ( pref + post )
Create component port or generic connection on VHDL entity.
Create component port or generic connection on VHDL entity .
"""
		Create component port or generic connection on VHDL entity.
		Arguments:
			decl     Declaration object
			specDir  If Direction should be specified in the connection
				     in VHDL comment   
		"""
self
decl
specDir