languages/gen_vhdl.py
def parse_gen_or_port(self, line):
		"""
		Parses input line which is a port or generic declaration into a
 		declaration object.
		On ports, direction must be specified. On generics, it must NOT be
		speciffied.
		If line could not be parsed, None is returned. Otherwise declaration
		object is returned.
		Each line must start with 'signal' for port declarations, or 'constant'
		for generic declarations.
		
		"""
		decl = LanDeclaration("new", value="")
		#decl.alignRight = False
		#decl.alignLength = 80
		#decl.doIndent = True

		# Find all separated words and numbers
		cmn_re = re.compile("[\w]+")
		wrds = cmn_re.findall(line)

		# Allow only signal and constant prefixes
		if (len(wrds) > 2 and 
			(wrds[0] == "signal" or wrds[0] == "constant")):
			decl.specifier = wrds[0]
		else:
			return None

		# For Ports, Direction must be valid VHDL port direction
		if (wrds[0] == "signal" and (not self.is_valid_dir(wrds[2]))):
			return None

		# Name is common for generics and ports
		decl.name = wrds[1]

		if (wrds[0] == "signal"):
			decl.direction = wrds[2]
			decl.type = wrds[3]

		if (wrds[0] == "constant"):
			# Initialized default value (for generics only)
			if (":=" in line):
				decl.value = wrds[-1]
			decl.type = wrds[2]

		# Process std_logic_vector specially to determine range. Support
		# only downto, we don't need to be too generic
		#print("DEEEECL")				
		#print(decl.name)
		#print(decl.type)
		#print("\n")
		if (decl.type == "std_logic_vector"):
			stdv_re = re.compile("\([ ]*.+ downto .*[ ]*\)")
			rng_spec = stdv_re.findall(line)
			
			# Skip vectors without range (e.g. generics)
			if (len(rng_spec) == 0):
				return decl

			# Strip brackets and take vector boundaries
			ths = rng_spec[0][1:-1].split("downto")
			decl.upBound = ths[0].strip()
			decl.lowBound = ths[1].strip()

			# Calculate bitWidth, but only for integers, for strings
			# leave only boundaries, we don't need complicated parsing logic
			if (decl.upBound.isdigit() and decl.lowBound.isdigit()):
				decl.bitWidth = eval(decl.upBound + " - " + decl.lowBound + "+ 1")

		elif (decl.type == "std_logic"):
			decl.bitWidth = 1

		return decl

		Parses input line which is a port or generic declaration into a
 		declaration object.
		On ports, direction must be specified. On generics, it must NOT be
		speciffied.
		If line could not be parsed, None is returned. Otherwise declaration
		object is returned.
		Each line must start with 'signal' for port declarations, or 'constant'
		for generic declarations.
		
		
Parses input line which is a port or generic declaration into a
declaration object.
On ports, direction must be specified. On generics, it must NOT be
speciffied.
If line could not be parsed, None is returned. Otherwise declaration
object is returned.
Each line must start with 'signal' for port declarations, or 'constant'
for generic declarations.
Parses input line which is a port or generic declaration into a declaration object . On ports direction must be specified . On generics it must NOT be speciffied . If line could not be parsed None is returned . Otherwise declaration object is returned . Each line must start with ' signal ' for port declarations or ' constant ' for generic declarations .
def parse_gen_or_port(self, line):
		decl = LanDeclaration("new", value="")
		cmn_re = re.compile("[\w]+")
		wrds = cmn_re.findall(line)
		if (len(wrds) > 2 and 
			(wrds[0] == "signal" or wrds[0] == "constant")):
			decl.specifier = wrds[0]
		else:
			return None
		if (wrds[0] == "signal" and (not self.is_valid_dir(wrds[2]))):
			return None
		decl.name = wrds[1]
		if (wrds[0] == "signal"):
			decl.direction = wrds[2]
			decl.type = wrds[3]
		if (wrds[0] == "constant"):
			if (":=" in line):
				decl.value = wrds[-1]
			decl.type = wrds[2]
		if (decl.type == "std_logic_vector"):
			stdv_re = re.compile("\([ ]*.+ downto .*[ ]*\)")
			rng_spec = stdv_re.findall(line)
			if (len(rng_spec) == 0):
				return decl
			ths = rng_spec[0][1:-1].split("downto")
			decl.upBound = ths[0].strip()
			decl.lowBound = ths[1].strip()
			if (decl.upBound.isdigit() and decl.lowBound.isdigit()):
				decl.bitWidth = eval(decl.upBound + " - " + decl.lowBound + "+ 1")
		elif (decl.type == "std_logic"):
			decl.bitWidth = 1
		return decl
def parse_gen_or_port ( self , line ) : decl = LanDeclaration ( "new" , value = "" ) cmn_re = re . compile ( "[\w]+" ) wrds = cmn_re . findall ( line ) if ( len ( wrds ) > 2 and ( wrds [ 0 ] == "signal" or wrds [ 0 ] == "constant" ) ) : decl . specifier = wrds [ 0 ] else : return None if ( wrds [ 0 ] == "signal" and ( not self . is_valid_dir ( wrds [ 2 ] ) ) ) : return None decl . name = wrds [ 1 ] if ( wrds [ 0 ] == "signal" ) : decl . direction = wrds [ 2 ] decl . type = wrds [ 3 ] if ( wrds [ 0 ] == "constant" ) : if ( ":=" in line ) : decl . value = wrds [ - 1 ] decl . type = wrds [ 2 ] if ( decl . type == "std_logic_vector" ) : stdv_re = re . compile ( "\([ ]*.+ downto .*[ ]*\)" ) rng_spec = stdv_re . findall ( line ) if ( len ( rng_spec ) == 0 ) : return decl ths = rng_spec [ 0 ] [ 1 : - 1 ] . split ( "downto" ) decl . upBound = ths [ 0 ] . strip ( ) decl . lowBound = ths [ 1 ] . strip ( ) if ( decl . upBound . isdigit ( ) and decl . lowBound . isdigit ( ) ) : decl . bitWidth = eval ( decl . upBound + " - " + decl . lowBound + "+ 1" ) elif ( decl . type == "std_logic" ) : decl . bitWidth = 1 return decl
Parses input line which is a port or generic declaration into a
declaration object.
Parses input line which is a port or generic declaration into a declaration object .
"""
		Parses input line which is a port or generic declaration into a
 		declaration object.
		On ports, direction must be specified. On generics, it must NOT be
		speciffied.
		If line could not be parsed, None is returned. Otherwise declaration
		object is returned.
		Each line must start with 'signal' for port declarations, or 'constant'
		for generic declarations.
		
		""" #decl.alignRight = False #decl.alignLength = 80 #decl.doIndent = True # Find all separated words and numbers # Allow only signal and constant prefixes # For Ports, Direction must be valid VHDL port direction # Name is common for generics and ports # Initialized default value (for generics only) # Process std_logic_vector specially to determine range. Support # only downto, we don't need to be too generic #print("DEEEECL")				 #print(decl.name) #print(decl.type) #print("\n") # Skip vectors without range (e.g. generics) # Strip brackets and take vector boundaries # Calculate bitWidth, but only for integers, for strings # leave only boundaries, we don't need complicated parsing logic
self
line