ip_xact/vhdl_reg_map_generator.py
def create_addr_decoder(self, block):
		"""
        Create instance of address decoder for writable registers.
		"""
		path = os.path.join(ROOT_PATH, self.template_sources["addr_dec_template_path"])

		addr_dec = self.hdlGen.load_entity_template(path)
		addr_dec.isInstance = True
		addr_dec.value = addr_dec.name.lower() + "_" + block.name.lower() + "_comp"
		addr_dec.gap = 2

		# Connect generics
		addr_dec.generics["address_width"].value = self.calc_wrd_address_width(block)
		addr_dec.generics["address_entries"].value = self.calc_blk_wrd_count(block)
		addr_dec.generics["addr_vect"].value = "ADDR_VECT"
		addr_dec.generics["registered_out"].value = "false"
		addr_dec.generics["reset_polarity"].value = "reset_polarity".upper()

		# Connect ports
		addr_dec.ports["clk_sys"].value = "clk_sys"
		addr_dec.ports["res_n"].value = "res_n"
		
		addr_indices = self.calc_addr_indices(block)
		addr_str =  "address(" + str(addr_indices[0])
		addr_str += " downto " + str(addr_indices[1]) + ")"
		addr_dec.ports["address"].value = addr_str

		addr_dec.ports["addr_dec"].value = "reg_sel"

		addr_dec.ports["enable"].value = "cs"

        # Create instance of a component
		self.hdlGen.write_comment("Write address to One-hot decoder", gap = 4)
		self.hdlGen.format_entity_decl(addr_dec)

		self.hdlGen.create_comp_instance(addr_dec)

        Create instance of address decoder for writable registers.
		
Create instance of address decoder for writable registers.
Create instance of address decoder for writable registers .
def create_addr_decoder(self, block):
		path = os.path.join(ROOT_PATH, self.template_sources["addr_dec_template_path"])
		addr_dec = self.hdlGen.load_entity_template(path)
		addr_dec.isInstance = True
		addr_dec.value = addr_dec.name.lower() + "_" + block.name.lower() + "_comp"
		addr_dec.gap = 2
		addr_dec.generics["address_width"].value = self.calc_wrd_address_width(block)
		addr_dec.generics["address_entries"].value = self.calc_blk_wrd_count(block)
		addr_dec.generics["addr_vect"].value = "ADDR_VECT"
		addr_dec.generics["registered_out"].value = "false"
		addr_dec.generics["reset_polarity"].value = "reset_polarity".upper()
		addr_dec.ports["clk_sys"].value = "clk_sys"
		addr_dec.ports["res_n"].value = "res_n"
		addr_indices = self.calc_addr_indices(block)
		addr_str =  "address(" + str(addr_indices[0])
		addr_str += " downto " + str(addr_indices[1]) + ")"
		addr_dec.ports["address"].value = addr_str
		addr_dec.ports["addr_dec"].value = "reg_sel"
		addr_dec.ports["enable"].value = "cs"
		self.hdlGen.write_comment("Write address to One-hot decoder", gap = 4)
		self.hdlGen.format_entity_decl(addr_dec)
		self.hdlGen.create_comp_instance(addr_dec)
def create_addr_decoder ( self , block ) : path = os . path . join ( ROOT_PATH , self . template_sources [ "addr_dec_template_path" ] ) addr_dec = self . hdlGen . load_entity_template ( path ) addr_dec . isInstance = True addr_dec . value = addr_dec . name . lower ( ) + "_" + block . name . lower ( ) + "_comp" addr_dec . gap = 2 addr_dec . generics [ "address_width" ] . value = self . calc_wrd_address_width ( block ) addr_dec . generics [ "address_entries" ] . value = self . calc_blk_wrd_count ( block ) addr_dec . generics [ "addr_vect" ] . value = "ADDR_VECT" addr_dec . generics [ "registered_out" ] . value = "false" addr_dec . generics [ "reset_polarity" ] . value = "reset_polarity" . upper ( ) addr_dec . ports [ "clk_sys" ] . value = "clk_sys" addr_dec . ports [ "res_n" ] . value = "res_n" addr_indices = self . calc_addr_indices ( block ) addr_str = "address(" + str ( addr_indices [ 0 ] ) addr_str += " downto " + str ( addr_indices [ 1 ] ) + ")" addr_dec . ports [ "address" ] . value = addr_str addr_dec . ports [ "addr_dec" ] . value = "reg_sel" addr_dec . ports [ "enable" ] . value = "cs" self . hdlGen . write_comment ( "Write address to One-hot decoder" , gap = 4 ) self . hdlGen . format_entity_decl ( addr_dec ) self . hdlGen . create_comp_instance ( addr_dec )
Create instance of address decoder for writable registers.
Create instance of address decoder for writable registers .
"""
        Create instance of address decoder for writable registers.
		""" # Connect generics # Connect ports # Create instance of a component
self
block