ip_xact/vhdl_reg_map_generator.py
def create_reg_access_cover_point(self, block, reg, acc_type):
		"""
		Create cover point for write/read to/from a register.
		"""
		# Get index of memory word for the register
		reg_sel_index = self.get_wrd_index(block, reg) - 1

		# Calcuate byte enable indices
		l_be_ind = reg.addressOffset % 4
		h_be_ind = l_be_ind + int(reg.size / 8) - 1

		be_lst = []
		for i in range(l_be_ind, h_be_ind + 1):
	
			be_lst.append(self.hdlGen.format_logic_op(
						    [self.hdlGen.format_vector_index("be",i),
							 self.hdlGen.format_bin_const("1")],
							 self.hdlGen.LogicOp.OP_COMPARE))
		
		be_str = self.hdlGen.format_logic_op(be_lst, self.hdlGen.LogicOp.OP_OR)

		op_lst = []
		op_lst.append(self.hdlGen.format_logic_op(
						["cs", self.hdlGen.format_bin_const("1")],
						self.hdlGen.LogicOp.OP_COMPARE))
		op_lst.append(self.hdlGen.format_logic_op(
						[acc_type, self.hdlGen.format_bin_const("1")],
						self.hdlGen.LogicOp.OP_COMPARE))
		op_lst.append(self.hdlGen.format_logic_op(
						[self.hdlGen.format_vector_index("reg_sel", reg_sel_index),
						 self.hdlGen.format_bin_const("1")],
						self.hdlGen.LogicOp.OP_COMPARE))
		op_lst.append(be_str)
		sequence = self.hdlGen.format_logic_op(op_lst, self.hdlGen.LogicOp.OP_AND)
		self.hdlGen.write_assertion("{}_{}_access_cov".format(reg.name.lower(), acc_type),
							   "cover", sequence);

		self.hdlGen.wr_nl()

		Create cover point for write/read to/from a register.
		
Create cover point for write/read to/from a register.
Create cover point for write / read to / from a register .
def create_reg_access_cover_point(self, block, reg, acc_type):
		reg_sel_index = self.get_wrd_index(block, reg) - 1
		l_be_ind = reg.addressOffset % 4
		h_be_ind = l_be_ind + int(reg.size / 8) - 1
		be_lst = []
		for i in range(l_be_ind, h_be_ind + 1):
			be_lst.append(self.hdlGen.format_logic_op(
						    [self.hdlGen.format_vector_index("be",i),
							 self.hdlGen.format_bin_const("1")],
							 self.hdlGen.LogicOp.OP_COMPARE))
		be_str = self.hdlGen.format_logic_op(be_lst, self.hdlGen.LogicOp.OP_OR)
		op_lst = []
		op_lst.append(self.hdlGen.format_logic_op(
						["cs", self.hdlGen.format_bin_const("1")],
						self.hdlGen.LogicOp.OP_COMPARE))
		op_lst.append(self.hdlGen.format_logic_op(
						[acc_type, self.hdlGen.format_bin_const("1")],
						self.hdlGen.LogicOp.OP_COMPARE))
		op_lst.append(self.hdlGen.format_logic_op(
						[self.hdlGen.format_vector_index("reg_sel", reg_sel_index),
						 self.hdlGen.format_bin_const("1")],
						self.hdlGen.LogicOp.OP_COMPARE))
		op_lst.append(be_str)
		sequence = self.hdlGen.format_logic_op(op_lst, self.hdlGen.LogicOp.OP_AND)
		self.hdlGen.write_assertion("{}_{}_access_cov".format(reg.name.lower(), acc_type),
							   "cover", sequence);
		self.hdlGen.wr_nl()
def create_reg_access_cover_point ( self , block , reg , acc_type ) : reg_sel_index = self . get_wrd_index ( block , reg ) - 1 l_be_ind = reg . addressOffset % 4 h_be_ind = l_be_ind + int ( reg . size / 8 ) - 1 be_lst = [ ] for i in range ( l_be_ind , h_be_ind + 1 ) : be_lst . append ( self . hdlGen . format_logic_op ( [ self . hdlGen . format_vector_index ( "be" , i ) , self . hdlGen . format_bin_const ( "1" ) ] , self . hdlGen . LogicOp . OP_COMPARE ) ) be_str = self . hdlGen . format_logic_op ( be_lst , self . hdlGen . LogicOp . OP_OR ) op_lst = [ ] op_lst . append ( self . hdlGen . format_logic_op ( [ "cs" , self . hdlGen . format_bin_const ( "1" ) ] , self . hdlGen . LogicOp . OP_COMPARE ) ) op_lst . append ( self . hdlGen . format_logic_op ( [ acc_type , self . hdlGen . format_bin_const ( "1" ) ] , self . hdlGen . LogicOp . OP_COMPARE ) ) op_lst . append ( self . hdlGen . format_logic_op ( [ self . hdlGen . format_vector_index ( "reg_sel" , reg_sel_index ) , self . hdlGen . format_bin_const ( "1" ) ] , self . hdlGen . LogicOp . OP_COMPARE ) ) op_lst . append ( be_str ) sequence = self . hdlGen . format_logic_op ( op_lst , self . hdlGen . LogicOp . OP_AND ) self . hdlGen . write_assertion ( "{}_{}_access_cov" . format ( reg . name . lower ( ) , acc_type ) , "cover" , sequence ) ; self . hdlGen . wr_nl ( )
Create cover point for write/read to/from a register.
Create cover point for write / read to / from a register .
"""
		Create cover point for write/read to/from a register.
		""" # Get index of memory word for the register # Calcuate byte enable indices
self
block
reg
acc_type