languages/gen_vhdl.py
def write_decl(self, decl):
		"""
		Create VHDL declaration of simple type. CAN be used for either
        component ports (with direction), generics or signal/constant
        declaration without binding to entity/component.
		Arguments:
			decl		    Declaration object
		"""
		[strType, strVal] = self.format_decl_type_and_val(decl)

		dirStr = self.format_decl_dir(decl)
		name_fmt = self.format_decl_name(decl)

		# Declare prefix and postfix, two parts of declaration
		pref_string = ""
		if (decl.specifier != None):
			pref_string = decl.specifier
		pref = '  {} {}'.format(pref_string, name_fmt)

		post = ' :{} {}'.format(dirStr, strType)

		# Distinguish between initialized and non-initialized declarations!
		if (not((decl.value == "") or (decl.value == None))):
			post += " := {}".format(strVal)

		# Append semicoln
		if (decl.addSemicoln):
			post += ";"
		post += "\n";

		# Following aligning section is a little nasty thing and one might
		# wonder how it works... Author does not know either, so this should
		# be reworked in future. Bottom line is: There are no clear rules
		# on how alignement of declaration objects should be done. It should
		# be generic enough to cover maximal line length, left, right alignments
		# inited, non-inited vectors so that each generated code looks NICE!

		# When Aligning left, align prefix
		if (decl.alignLeft):
			pref = '{:<{}}'.format(pref, decl.alignLen)

		# When Aligning left, align postfix
		if (decl.alignRight):
			post = '{:>{}}'.format(post, decl.alignLen - len(pref))


		newLineChar = ""
		if (len(pref) + len(post) > 80 and decl.wrap):
			newLineChar = "\n                "
		
		self.__wr_line(" " * decl.gap + pref + newLineChar + post)
		return True

		Create VHDL declaration of simple type. CAN be used for either
        component ports (with direction), generics or signal/constant
        declaration without binding to entity/component.
		Arguments:
			decl		    Declaration object
		
Create VHDL declaration of simple type. CAN be used for either
component ports (with direction), generics or signal/constant
declaration without binding to entity/component.
Arguments:
decl                Declaration object
Create VHDL declaration of simple type . CAN be used for either component ports ( with direction ) generics or signal / constant declaration without binding to entity / component . Arguments : decl Declaration object
def write_decl(self, decl):
		[strType, strVal] = self.format_decl_type_and_val(decl)
		dirStr = self.format_decl_dir(decl)
		name_fmt = self.format_decl_name(decl)
		pref_string = ""
		if (decl.specifier != None):
			pref_string = decl.specifier
		pref = '  {} {}'.format(pref_string, name_fmt)
		post = ' :{} {}'.format(dirStr, strType)
		if (not((decl.value == "") or (decl.value == None))):
			post += " := {}".format(strVal)
		if (decl.addSemicoln):
			post += ";"
		post += "\n";
		if (decl.alignLeft):
			pref = '{:<{}}'.format(pref, decl.alignLen)
		if (decl.alignRight):
			post = '{:>{}}'.format(post, decl.alignLen - len(pref))
		newLineChar = ""
		if (len(pref) + len(post) > 80 and decl.wrap):
			newLineChar = "\n                "
		self.__wr_line(" " * decl.gap + pref + newLineChar + post)
		return True
def write_decl ( self , decl ) : [ strType , strVal ] = self . format_decl_type_and_val ( decl ) dirStr = self . format_decl_dir ( decl ) name_fmt = self . format_decl_name ( decl ) pref_string = "" if ( decl . specifier != None ) : pref_string = decl . specifier pref = '  {} {}' . format ( pref_string , name_fmt ) post = ' :{} {}' . format ( dirStr , strType ) if ( not ( ( decl . value == "" ) or ( decl . value == None ) ) ) : post += " := {}" . format ( strVal ) if ( decl . addSemicoln ) : post += ";" post += "\n" ; if ( decl . alignLeft ) : pref = '{:<{}}' . format ( pref , decl . alignLen ) if ( decl . alignRight ) : post = '{:>{}}' . format ( post , decl . alignLen - len ( pref ) ) newLineChar = "" if ( len ( pref ) + len ( post ) > 80 and decl . wrap ) : newLineChar = "\n                " self . __wr_line ( " " * decl . gap + pref + newLineChar + post ) return True
Create VHDL declaration of simple type.
Create VHDL declaration of simple type .
"""
		Create VHDL declaration of simple type. CAN be used for either
        component ports (with direction), generics or signal/constant
        declaration without binding to entity/component.
		Arguments:
			decl		    Declaration object
		""" # Declare prefix and postfix, two parts of declaration # Distinguish between initialized and non-initialized declarations! # Append semicoln # Following aligning section is a little nasty thing and one might # wonder how it works... Author does not know either, so this should # be reworked in future. Bottom line is: There are no clear rules # on how alignement of declaration objects should be done. It should # be generic enough to cover maximal line length, left, right alignments # inited, non-inited vectors so that each generated code looks NICE! # When Aligning left, align prefix # When Aligning left, align postfix
self
decl