ip_xact/vhdl_tb_addr_generator.py
def write_addrbl_reg_list(self, addressBlock):
		"""
		Write list of registers within an address block.
		"""
		self.vhdlGen.wr_nl()
		self.vhdlGen.write_comment("Register list", gap = 2)
		
		# Write register type (declaration does not support array, do it directly)
		array_str = "  type t_{}_list is array (0 to {}) of t_memory_reg;\n".format(
						addressBlock.name, len(addressBlock.register) - 1)
		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_line(array_str)
		self.vhdlGen.wr_nl()

		# Write list of registers
		self.vhdlGen.wr_line("  constant {}_list : t_{}_list :=(\n".format(
			addressBlock.name, addressBlock.name))
		self.vhdlGen.wr_nl()

		for i,reg in enumerate(sorted(addressBlock.register, key=lambda a: a.addressOffset)):
			self.vhdlGen.wr_line("    (address   => {}_ADR,\n".format(reg.name.upper()))
			self.vhdlGen.wr_line("     size      => {},\n".format(reg.size))

			reg_t_str = "reg_none"
			if (reg.access == "read-only"):
				reg_t_str = "reg_read_only"

			elif (reg.access == "write-only"):
				reg_t_str = "reg_write_only"

			elif (reg.access == "read-write"):
				reg_t_str = "reg_read_write"

			elif (reg.access == "read-writeOnce"):
				reg_t_str = "reg_read_write_once"

			self.vhdlGen.wr_line("     reg_type  => {},\n".format(reg_t_str))

			# Calculate reset mask and offset to position of reg
			self.vhdlGen.wr_line('     reset_val => "{}",\n'.format(self.get_padded_rst_mask(reg)))

			# Create vector with implemented bits
			self.vhdlGen.wr_line('     is_implem => "{}")'.format(self.get_implemented_mask(reg)))

			if (i == len(addressBlock.register) - 1):
				self.vhdlGen.wr_line("\n  );\n")
			else:
				self.vhdlGen.wr_line(",\n")

		Write list of registers within an address block.
		
Write list of registers within an address block.
Write list of registers within an address block .
def write_addrbl_reg_list(self, addressBlock):
		self.vhdlGen.wr_nl()
		self.vhdlGen.write_comment("Register list", gap = 2)
		array_str = "  type t_{}_list is array (0 to {}) of t_memory_reg;\n".format(
						addressBlock.name, len(addressBlock.register) - 1)
		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_line(array_str)
		self.vhdlGen.wr_nl()
		self.vhdlGen.wr_line("  constant {}_list : t_{}_list :=(\n".format(
			addressBlock.name, addressBlock.name))
		self.vhdlGen.wr_nl()
		for i,reg in enumerate(sorted(addressBlock.register, key=lambda a: a.addressOffset)):
			self.vhdlGen.wr_line("    (address   => {}_ADR,\n".format(reg.name.upper()))
			self.vhdlGen.wr_line("     size      => {},\n".format(reg.size))
			reg_t_str = "reg_none"
			if (reg.access == "read-only"):
				reg_t_str = "reg_read_only"
			elif (reg.access == "write-only"):
				reg_t_str = "reg_write_only"
			elif (reg.access == "read-write"):
				reg_t_str = "reg_read_write"
			elif (reg.access == "read-writeOnce"):
				reg_t_str = "reg_read_write_once"
			self.vhdlGen.wr_line("     reg_type  => {},\n".format(reg_t_str))
			self.vhdlGen.wr_line('     reset_val => "{}",\n'.format(self.get_padded_rst_mask(reg)))
			self.vhdlGen.wr_line('     is_implem => "{}")'.format(self.get_implemented_mask(reg)))
			if (i == len(addressBlock.register) - 1):
				self.vhdlGen.wr_line("\n  );\n")
			else:
				self.vhdlGen.wr_line(",\n")
def write_addrbl_reg_list ( self , addressBlock ) : self . vhdlGen . wr_nl ( ) self . vhdlGen . write_comment ( "Register list" , gap = 2 ) array_str = "  type t_{}_list is array (0 to {}) of t_memory_reg;\n" . format ( addressBlock . name , len ( addressBlock . register ) - 1 ) self . vhdlGen . wr_nl ( ) self . vhdlGen . wr_line ( array_str ) self . vhdlGen . wr_nl ( ) self . vhdlGen . wr_line ( "  constant {}_list : t_{}_list :=(\n" . format ( addressBlock . name , addressBlock . name ) ) self . vhdlGen . wr_nl ( ) for i , reg in enumerate ( sorted ( addressBlock . register , key = lambda a : a . addressOffset ) ) : self . vhdlGen . wr_line ( "    (address   => {}_ADR,\n" . format ( reg . name . upper ( ) ) ) self . vhdlGen . wr_line ( "     size      => {},\n" . format ( reg . size ) ) reg_t_str = "reg_none" if ( reg . access == "read-only" ) : reg_t_str = "reg_read_only" elif ( reg . access == "write-only" ) : reg_t_str = "reg_write_only" elif ( reg . access == "read-write" ) : reg_t_str = "reg_read_write" elif ( reg . access == "read-writeOnce" ) : reg_t_str = "reg_read_write_once" self . vhdlGen . wr_line ( "     reg_type  => {},\n" . format ( reg_t_str ) ) self . vhdlGen . wr_line ( '     reset_val => "{}",\n' . format ( self . get_padded_rst_mask ( reg ) ) ) self . vhdlGen . wr_line ( '     is_implem => "{}")' . format ( self . get_implemented_mask ( reg ) ) ) if ( i == len ( addressBlock . register ) - 1 ) : self . vhdlGen . wr_line ( "\n  );\n" ) else : self . vhdlGen . wr_line ( ",\n" )
Write list of registers within an address block.
Write list of registers within an address block .
"""
		Write list of registers within an address block.
		""" # Write register type (declaration does not support array, do it directly) # Write list of registers # Calculate reset mask and offset to position of reg # Create vector with implemented bits
self
addressBlock