ip_xact/vhdl_reg_map_generator.py
def create_write_reg_record_driver(self, block):
		"""
		Create driver for write registe record. Internal signal is connected
		to output port.
		"""
		dest = block.name + "_out"
		src = dest + "_i"
		self.hdlGen.create_signal_connection(dest, src, gap = 4)

		Create driver for write registe record. Internal signal is connected
		to output port.
		
Create driver for write registe record. Internal signal is connected
to output port.
Create driver for write registe record . Internal signal is connected to output port .
def create_write_reg_record_driver(self, block):
		dest = block.name + "_out"
		src = dest + "_i"
		self.hdlGen.create_signal_connection(dest, src, gap = 4)
def create_write_reg_record_driver ( self , block ) : dest = block . name + "_out" src = dest + "_i" self . hdlGen . create_signal_connection ( dest , src , gap = 4 )
Create driver for write registe record.
Create driver for write registe record .
"""
		Create driver for write registe record. Internal signal is connected
		to output port.
		"""
self
block