languages/gen_vhdl.py
def format_decl_type_and_val(self, decl):
		"""
		Format value of a declaration into string.
		"""
		strType = ""
		strVal = ""

		# For std_logic or std_logic_vector parse it separately
		if (decl.type == "std_logic" or decl.type == "std_logic_vector"):
			if (decl.value != "" and decl.value != None):
				strVal = self.format_std_log_decl_val(decl)

			strType = self.format_std_log_decl_type(decl)

		# All other types
		else:
			strType = decl.type
			strVal = decl.value

		return [strType, strVal]

		Format value of a declaration into string.
		
Format value of a declaration into string.
Format value of a declaration into string .
def format_decl_type_and_val(self, decl):
		strType = ""
		strVal = ""
		if (decl.type == "std_logic" or decl.type == "std_logic_vector"):
			if (decl.value != "" and decl.value != None):
				strVal = self.format_std_log_decl_val(decl)
			strType = self.format_std_log_decl_type(decl)
		else:
			strType = decl.type
			strVal = decl.value
		return [strType, strVal]
def format_decl_type_and_val ( self , decl ) : strType = "" strVal = "" if ( decl . type == "std_logic" or decl . type == "std_logic_vector" ) : if ( decl . value != "" and decl . value != None ) : strVal = self . format_std_log_decl_val ( decl ) strType = self . format_std_log_decl_type ( decl ) else : strType = decl . type strVal = decl . value return [ strType , strVal ]
Format value of a declaration into string.
Format value of a declaration into string .
"""
		Format value of a declaration into string.
		""" # For std_logic or std_logic_vector parse it separately # All other types
self
decl