languages/gen_vhdl.py
def format_std_log_decl_type(self, decl):
		""" 
		Formats "type" specifier for std_logic and std_logic_vector.
		types. Supports Integer and String Bitwidths.
			decl		Declaration object
		"""
		strType = decl.type

		# If Both bounds are given, use the bounds
		if (decl.upBound != None and decl.lowBound != None):
			if (decl.type == "std_logic"):
				strType += "_vector"
			strType += "({} downto {})".format(decl.upBound, decl.lowBound)

		# If only numeric bitWidth is given, use it and go till zero 
		elif (str(decl.bitWidth).isdigit() and decl.bitWidth > 1):
			if (decl.type == "std_logic"):
				strType += "_vector"
			strType += "({} downto 0)".format(decl.bitWidth - 1)

		# If digit is 0 -> nothing is needed we keep std_logic
		elif (decl.bitWidth == 1):			
			return strType

		# If nothing is specified, we don't know how to format the vector ->
		# FUCK IT!
		else:
			print("WARNING: No std_logic_vector range! Assuming without range.")
			
		return strType
 
		Formats "type" specifier for std_logic and std_logic_vector.
		types. Supports Integer and String Bitwidths.
			decl		Declaration object
		
Formats "type" specifier for std_logic and std_logic_vector.
types. Supports Integer and String Bitwidths.
decl            Declaration object
Formats " type " specifier for std_logic and std_logic_vector . types . Supports Integer and String Bitwidths . decl Declaration object
def format_std_log_decl_type(self, decl):
		strType = decl.type
		if (decl.upBound != None and decl.lowBound != None):
			if (decl.type == "std_logic"):
				strType += "_vector"
			strType += "({} downto {})".format(decl.upBound, decl.lowBound)
		elif (str(decl.bitWidth).isdigit() and decl.bitWidth > 1):
			if (decl.type == "std_logic"):
				strType += "_vector"
			strType += "({} downto 0)".format(decl.bitWidth - 1)
		elif (decl.bitWidth == 1):			
			return strType
		else:
			print("WARNING: No std_logic_vector range! Assuming without range.")
		return strType
def format_std_log_decl_type ( self , decl ) : strType = decl . type if ( decl . upBound != None and decl . lowBound != None ) : if ( decl . type == "std_logic" ) : strType += "_vector" strType += "({} downto {})" . format ( decl . upBound , decl . lowBound ) elif ( str ( decl . bitWidth ) . isdigit ( ) and decl . bitWidth > 1 ) : if ( decl . type == "std_logic" ) : strType += "_vector" strType += "({} downto 0)" . format ( decl . bitWidth - 1 ) elif ( decl . bitWidth == 1 ) : return strType else : print ( "WARNING: No std_logic_vector range! Assuming without range." ) return strType
Formats "type" specifier for std_logic and std_logic_vector.
Formats " type " specifier for std_logic and std_logic_vector .
""" 
		Formats "type" specifier for std_logic and std_logic_vector.
		types. Supports Integer and String Bitwidths.
			decl		Declaration object
		""" # If Both bounds are given, use the bounds # If only numeric bitWidth is given, use it and go till zero  # If digit is 0 -> nothing is needed we keep std_logic # If nothing is specified, we don't know how to format the vector -> # FUCK IT!
self
decl