ip_xact/vhdl_reg_map_generator.py
def create_reg_block_template(self, block):
		"""
		Load memory bus entity template, add ports for register inputs, outputs.
		Create declaration of register block entity.
		"""
		# Load memory bus template and create entity definition
		path = os.path.join(ROOT_PATH, self.template_sources["mem_bus_template_path"])
		entity = self.hdlGen.load_entity_template(path)
		entity.intType = "entity"
		entity.isInstance = False		
		entity.name = block.name.lower() + "_reg_map"

		# Add ports for register values
		self.create_reg_ports(block, entity.ports)

		# Add generics for conditionally defined components
		self.create_reg_cond_generics(block, entity)

		# Format entity declarations to look nice
		self.hdlGen.format_decls(entity.ports, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)
		self.hdlGen.format_decls(entity.generics, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)

		self.hdlGen.create_comp_instance(entity)
		self.hdlGen.commit_append_line(1)

		return entity

		Load memory bus entity template, add ports for register inputs, outputs.
		Create declaration of register block entity.
		
Load memory bus entity template, add ports for register inputs, outputs.
Create declaration of register block entity.
Load memory bus entity template add ports for register inputs outputs . Create declaration of register block entity .
def create_reg_block_template(self, block):
		path = os.path.join(ROOT_PATH, self.template_sources["mem_bus_template_path"])
		entity = self.hdlGen.load_entity_template(path)
		entity.intType = "entity"
		entity.isInstance = False		
		entity.name = block.name.lower() + "_reg_map"
		self.create_reg_ports(block, entity.ports)
		self.create_reg_cond_generics(block, entity)
		self.hdlGen.format_decls(entity.ports, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)
		self.hdlGen.format_decls(entity.generics, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)
		self.hdlGen.create_comp_instance(entity)
		self.hdlGen.commit_append_line(1)
		return entity
def create_reg_block_template ( self , block ) : path = os . path . join ( ROOT_PATH , self . template_sources [ "mem_bus_template_path" ] ) entity = self . hdlGen . load_entity_template ( path ) entity . intType = "entity" entity . isInstance = False entity . name = block . name . lower ( ) + "_reg_map" self . create_reg_ports ( block , entity . ports ) self . create_reg_cond_generics ( block , entity ) self . hdlGen . format_decls ( entity . ports , gap = 2 , alignLeft = True , alignRight = False , alignLen = 30 , wrap = False ) self . hdlGen . format_decls ( entity . generics , gap = 2 , alignLeft = True , alignRight = False , alignLen = 30 , wrap = False ) self . hdlGen . create_comp_instance ( entity ) self . hdlGen . commit_append_line ( 1 ) return entity
Load memory bus entity template, add ports for register inputs, outputs.
Load memory bus entity template add ports for register inputs outputs .
"""
		Load memory bus entity template, add ports for register inputs, outputs.
		Create declaration of register block entity.
		""" # Load memory bus template and create entity definition # Add ports for register values # Add generics for conditionally defined components # Format entity declarations to look nice
self
block