ip_xact/vhdl_reg_map_generator.py
def create_mem_block_records(self, block):
		"""
		Create records for register module input/outputs. Each writable
		register is present in "write record". Each readable register is 
		present in a read record.
		"""
		self.hdlGen.wr_nl()

		self.create_output_reg_record(block)

		self.hdlGen.wr_nl()
		self.hdlGen.wr_nl()

		self.create_input_reg_record(block)

		self.hdlGen.wr_nl()

		Create records for register module input/outputs. Each writable
		register is present in "write record". Each readable register is 
		present in a read record.
		
Create records for register module input/outputs. Each writable
register is present in "write record". Each readable register is
present in a read record.
Create records for register module input / outputs . Each writable register is present in " write record " . Each readable register is present in a read record .
def create_mem_block_records(self, block):
		self.hdlGen.wr_nl()
		self.create_output_reg_record(block)
		self.hdlGen.wr_nl()
		self.hdlGen.wr_nl()
		self.create_input_reg_record(block)
		self.hdlGen.wr_nl()
def create_mem_block_records ( self , block ) : self . hdlGen . wr_nl ( ) self . create_output_reg_record ( block ) self . hdlGen . wr_nl ( ) self . hdlGen . wr_nl ( ) self . create_input_reg_record ( block ) self . hdlGen . wr_nl ( )
Create records for register module input/outputs.
Create records for register module input / outputs .
"""
		Create records for register module input/outputs. Each writable
		register is present in "write record". Each readable register is 
		present in a read record.
		"""
self
block