ip_xact/vhdl_reg_map_generator.py
def create_input_reg_record(self, block):
		"""
		Create record for readable registers from IP-XACT memory block object.
		"""
		# Input Declarations record
		inDecls = []
		inName = block.name + "_in_t"

		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):

			# All registers with read, but not read-write, since read-write is register
			# whose value is written and the same value is read back
			if (("read" in reg.access) and (reg.access != "read-write")):
				inDecls.append(LanDeclaration(reg.name, value=""))
				inDecls[-1].type = "std_logic_vector"
				inDecls[-1].bitWidth = reg.size
				inDecls[-1].specifier = ""

		# Format the declaration
		self.hdlGen.format_decls(inDecls, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)

		self.hdlGen.create_structure(inName, inDecls, gap = 2)

		Create record for readable registers from IP-XACT memory block object.
		
Create record for readable registers from IP-XACT memory block object.
Create record for readable registers from IP - XACT memory block object .
def create_input_reg_record(self, block):
		inDecls = []
		inName = block.name + "_in_t"
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
			if (("read" in reg.access) and (reg.access != "read-write")):
				inDecls.append(LanDeclaration(reg.name, value=""))
				inDecls[-1].type = "std_logic_vector"
				inDecls[-1].bitWidth = reg.size
				inDecls[-1].specifier = ""
		self.hdlGen.format_decls(inDecls, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)
		self.hdlGen.create_structure(inName, inDecls, gap = 2)
def create_input_reg_record ( self , block ) : inDecls = [ ] inName = block . name + "_in_t" for i , reg in enumerate ( sorted ( block . register , key = lambda a : a . addressOffset ) ) : if ( ( "read" in reg . access ) and ( reg . access != "read-write" ) ) : inDecls . append ( LanDeclaration ( reg . name , value = "" ) ) inDecls [ - 1 ] . type = "std_logic_vector" inDecls [ - 1 ] . bitWidth = reg . size inDecls [ - 1 ] . specifier = "" self . hdlGen . format_decls ( inDecls , gap = 2 , alignLeft = True , alignRight = False , alignLen = 30 , wrap = False ) self . hdlGen . create_structure ( inName , inDecls , gap = 2 )
Create record for readable registers from IP-XACT memory block object.
Create record for readable registers from IP - XACT memory block object .
"""
		Create record for readable registers from IP-XACT memory block object.
		""" # Input Declarations record # All registers with read, but not read-write, since read-write is register # whose value is written and the same value is read back # Format the declaration
self
block