ip_xact/vhdl_reg_map_generator.py
def calc_reg_byte_enable_vector(self, reg):
		"""
		Create byte enable vector for a register. Position of register within
		a memory word is considered.
		"""
		l_be_ind = reg.addressOffset % 4
		h_be_ind = l_be_ind + int(reg.size / 8) - 1
		return self.hdlGen.format_vector_range("be", h_be_ind, l_be_ind)

		Create byte enable vector for a register. Position of register within
		a memory word is considered.
		
Create byte enable vector for a register. Position of register within
a memory word is considered.
Create byte enable vector for a register . Position of register within a memory word is considered .
def calc_reg_byte_enable_vector(self, reg):
		l_be_ind = reg.addressOffset % 4
		h_be_ind = l_be_ind + int(reg.size / 8) - 1
		return self.hdlGen.format_vector_range("be", h_be_ind, l_be_ind)
def calc_reg_byte_enable_vector ( self , reg ) : l_be_ind = reg . addressOffset % 4 h_be_ind = l_be_ind + int ( reg . size / 8 ) - 1 return self . hdlGen . format_vector_range ( "be" , h_be_ind , l_be_ind )
Create byte enable vector for a register.
Create byte enable vector for a register .
"""
		Create byte enable vector for a register. Position of register within
		a memory word is considered.
		"""
self
reg