ip_xact/vhdl_addr_generator.py
def create_addrMap_package(self, name):
		""" 
		Create a VHDL package to the address generator output. Insert basic
		IEEE include: std_logic_1164.all. Add address definitions, create
		constants for enums and reset values.
		Arguments:
			name	VHDL pacakge name
		"""
		self.vhdlGen.wr_nl()
		self.vhdlGen.write_comm_line(gap=0)
		if (self.memMap != None):
			print ("Writing addresses of '%s' register map" % self.memMap.name)
			self.vhdlGen.write_comment("Memory map for: {}".format(
											self.memMap.name), 0, small=True)
		self.vhdlGen.write_gen_note()

		self.vhdlGen.write_comm_line(gap=0)
		self.vhdlGen.wr_nl()
		
		self.vhdlGen.create_includes("ieee", ["std_logic_1164.all"])
		self.vhdlGen.wr_nl()
		self.vhdlGen.create_package(name)
		self.vhdlGen.wr_nl()

		if (self.memMap):
			self.write_mem_map_addr()
			self.write_mem_map_fields()
			
		self.vhdlGen.commit_append_line(1)
 
		Create a VHDL package to the address generator output. Insert basic
		IEEE include: std_logic_1164.all. Add address definitions, create
		constants for enums and reset values.
		Arguments:
			name	VHDL pacakge name
		
Create a VHDL package to the address generator output. Insert basic
IEEE include: std_logic_1164.all. Add address definitions, create
constants for enums and reset values.
Arguments:
name    VHDL pacakge name
Create a VHDL package to the address generator output . Insert basic IEEE include : std_logic_1164 . all . Add address definitions create constants for enums and reset values . Arguments : name VHDL pacakge name
def create_addrMap_package(self, name):
		self.vhdlGen.wr_nl()
		self.vhdlGen.write_comm_line(gap=0)
		if (self.memMap != None):
			print ("Writing addresses of '%s' register map" % self.memMap.name)
			self.vhdlGen.write_comment("Memory map for: {}".format(
											self.memMap.name), 0, small=True)
		self.vhdlGen.write_gen_note()
		self.vhdlGen.write_comm_line(gap=0)
		self.vhdlGen.wr_nl()
		self.vhdlGen.create_includes("ieee", ["std_logic_1164.all"])
		self.vhdlGen.wr_nl()
		self.vhdlGen.create_package(name)
		self.vhdlGen.wr_nl()
		if (self.memMap):
			self.write_mem_map_addr()
			self.write_mem_map_fields()
		self.vhdlGen.commit_append_line(1)
def create_addrMap_package ( self , name ) : self . vhdlGen . wr_nl ( ) self . vhdlGen . write_comm_line ( gap = 0 ) if ( self . memMap != None ) : print ( "Writing addresses of '%s' register map" % self . memMap . name ) self . vhdlGen . write_comment ( "Memory map for: {}" . format ( self . memMap . name ) , 0 , small = True ) self . vhdlGen . write_gen_note ( ) self . vhdlGen . write_comm_line ( gap = 0 ) self . vhdlGen . wr_nl ( ) self . vhdlGen . create_includes ( "ieee" , [ "std_logic_1164.all" ] ) self . vhdlGen . wr_nl ( ) self . vhdlGen . create_package ( name ) self . vhdlGen . wr_nl ( ) if ( self . memMap ) : self . write_mem_map_addr ( ) self . write_mem_map_fields ( ) self . vhdlGen . commit_append_line ( 1 )
Create a VHDL package to the address generator output.
Create a VHDL package to the address generator output .
""" 
		Create a VHDL package to the address generator output. Insert basic
		IEEE include: std_logic_1164.all. Add address definitions, create
		constants for enums and reset values.
		Arguments:
			name	VHDL pacakge name
		"""
self
name