sonar/core/backends/sv.py
def modify_signal_name(original_name, dut_type):
    """
    For Vivado HLS, some signal names are changed from the source file in the
    generated Verilog. Here, we address that change

    Args:
        original_name (str): The original name of the port from the src file
        dut_type (dict): Information from the testbench config describing the
        type of DUT that is being used.

    Returns:
        str: The modified name of the signal, if changed
    """
    port_name = original_name
    if dut_type["lang"] != "sv":  # TODO temporary workaround
        if dut_type["hls"] == "vivado" and dut_type["hls_version"] == "2018.1":
            port_name = original_name + "_V"
    return port_name

    For Vivado HLS, some signal names are changed from the source file in the
    generated Verilog. Here, we address that change

    Args:
        original_name (str): The original name of the port from the src file
        dut_type (dict): Information from the testbench config describing the
        type of DUT that is being used.

    Returns:
        str: The modified name of the signal, if changed
    
For Vivado HLS, some signal names are changed from the source file in the
generated Verilog. Here, we address that change

original_name (str): The original name of the port from the src file
dut_type (dict): Information from the testbench config describing the
type of DUT that is being used.

The modified name of the signal, if changed
For Vivado HLS some signal names are changed from the source file in the generated Verilog . Here we address that change original_name ( str ) : The original name of the port from the src file dut_type ( dict ) : Information from the testbench config describing the type of DUT that is being used . The modified name of the signal if changed
def modify_signal_name(original_name, dut_type):
    port_name = original_name
    if dut_type["lang"] != "sv":  
        if dut_type["hls"] == "vivado" and dut_type["hls_version"] == "2018.1":
            port_name = original_name + "_V"
    return port_name
def modify_signal_name ( original_name , dut_type ) : port_name = original_name if dut_type [ "lang" ] != "sv" : if dut_type [ "hls" ] == "vivado" and dut_type [ "hls_version" ] == "2018.1" : port_name = original_name + "_V" return port_name
For Vivado HLS, some signal names are changed from the source file in the
generated Verilog.
For Vivado HLS some signal names are changed from the source file in the generated Verilog .
"""
    For Vivado HLS, some signal names are changed from the source file in the
    generated Verilog. Here, we address that change

    Args:
        original_name (str): The original name of the port from the src file
        dut_type (dict): Information from the testbench config describing the
        type of DUT that is being used.

    Returns:
        str: The modified name of the signal, if changed
    """ # TODO temporary workaround
original_name
dut_type