build-tools/newad.py
def make_decoder_inner(inst, mod, p):
    '''
    Constructs a decoder for a port p.
    p: is an instance of Port
    '''
    # print '// make_decoder',inst,mod,a
    if p.direction != 'output':
        # print '// make_decoder instance=%s name=%s'%(inst,a[5])
        clk_prefix = p.clk_domain
        cd_index_str = ''
        if p.cd_indexed and p.cd_index is not None:
            cd_index_str = '[%d]' % p.cd_index
        key = use_ram_key(p.module, p.name)
        # print '// checking use_ram for key '+key
        if inst is None:
            sig_name = re.sub(':', '_', p.name)
        else:
            sig_name = '%s_%s' % (inst, re.sub(':', '_', p.name))
        decode_def = 'wire we_%s = %s_write%s&(`ADDR_HIT_%s);\\\n' %\
                     (sig_name, clk_prefix, cd_index_str, sig_name)
        msb = int(p.downto[0])
        lsb = int(p.downto[1])
        data_width = msb - lsb + 1
        sign = p.sign if p.sign else 'unsigned'
        if key in use_ram:
            addr_range = use_ram[key]
            data_range = '[%d:%d]' % (msb, lsb)
            addr_width = range_width(addr_range)
            # print '// ***** use_ram %s %s'%(key,use_ram[key]), addr_range,
            # addr_width, data_range, data_width
            wire_def = 'wire %s %s_addr;\\\nwire %s %s;\\\n' %\
                       (addr_range, sig_name, data_range, sig_name)
            dpram_a = '.clka(%s_clk), .addra(%s_addr%s%s), .dina(%s_data%s%s),'\
                      ' .wena(we_%s)' % \
                      (clk_prefix, clk_prefix, cd_index_str, addr_range,
                       clk_prefix, cd_index_str, data_range, sig_name)
            dpram_b = '.clkb(%s_clk), .addrb(%s_addr), .doutb(%s)' %\
                      (clk_prefix, sig_name, sig_name)
            dpram_def = 'dpram #(.aw(%d),.dw(%d)) dp_%s(\\\n\t%s,\\\n\t%s);\\\n' %\
                        (addr_width, data_width, sig_name, dpram_a, dpram_b)
            decodes.append(wire_def + decode_def + dpram_def)
            gch[sig_name] = (addr_width, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'single-cycle':
            reg_def = 'reg [%d:%d] %s=0; always @(posedge %s_clk) '\
                      '%s <= we_%s ? %s_data%s[%d:%d] : %d\'b0;\\\n' %\
                      (msb, lsb, sig_name, clk_prefix, sig_name, sig_name,
                       clk_prefix, cd_index_str, msb, lsb, data_width)
            decodes.append(decode_def + reg_def)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'strobe':
            read_strobe = 'wire %s = %s_read & (`ADDR_HIT_%s);\\\n' %\
                          (sig_name, clk_prefix, sig_name)
            decodes.append(read_strobe)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'we-strobe':
            reg_def = 'wire %s = we_%s;\\\n' % (sig_name, sig_name)
            decodes.append(decode_def + reg_def)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'plus-we-VOID':
            pass
        else:
            if p.signal_type == 'plus-we':
                we_def = 'wire %s_we = we_%s;\\\n' % (sig_name, sig_name)
            else:
                we_def = ''
            reg_def = 'reg [%d:%d] %s=0; always @(posedge %s_clk) '\
                      'if (we_%s) %s <= %s_data%s;\\\n' %\
                      (msb, lsb, sig_name, clk_prefix, sig_name, sig_name,
                       clk_prefix, cd_index_str)
            decodes.append(decode_def + we_def + reg_def)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)

    Constructs a decoder for a port p.
    p: is an instance of Port
    
Constructs a decoder for a port p.
p: is an instance of Port
Constructs a decoder for a port p . p : is an instance of Port
def make_decoder_inner(inst, mod, p):
    if p.direction != 'output':
        clk_prefix = p.clk_domain
        cd_index_str = ''
        if p.cd_indexed and p.cd_index is not None:
            cd_index_str = '[%d]' % p.cd_index
        key = use_ram_key(p.module, p.name)
        if inst is None:
            sig_name = re.sub(':', '_', p.name)
        else:
            sig_name = '%s_%s' % (inst, re.sub(':', '_', p.name))
        decode_def = 'wire we_%s = %s_write%s&(`ADDR_HIT_%s);\\\n' %\
                     (sig_name, clk_prefix, cd_index_str, sig_name)
        msb = int(p.downto[0])
        lsb = int(p.downto[1])
        data_width = msb - lsb + 1
        sign = p.sign if p.sign else 'unsigned'
        if key in use_ram:
            addr_range = use_ram[key]
            data_range = '[%d:%d]' % (msb, lsb)
            addr_width = range_width(addr_range)
            wire_def = 'wire %s %s_addr;\\\nwire %s %s;\\\n' %\
                       (addr_range, sig_name, data_range, sig_name)
            dpram_a = '.clka(%s_clk), .addra(%s_addr%s%s), .dina(%s_data%s%s),'\
                      ' .wena(we_%s)' % \
                      (clk_prefix, clk_prefix, cd_index_str, addr_range,
                       clk_prefix, cd_index_str, data_range, sig_name)
            dpram_b = '.clkb(%s_clk), .addrb(%s_addr), .doutb(%s)' %\
                      (clk_prefix, sig_name, sig_name)
            dpram_def = 'dpram #(.aw(%d),.dw(%d)) dp_%s(\\\n\t%s,\\\n\t%s);\\\n' %\
                        (addr_width, data_width, sig_name, dpram_a, dpram_b)
            decodes.append(wire_def + decode_def + dpram_def)
            gch[sig_name] = (addr_width, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'single-cycle':
            reg_def = 'reg [%d:%d] %s=0; always @(posedge %s_clk) '\
                      '%s <= we_%s ? %s_data%s[%d:%d] : %d\'b0;\\\n' %\
                      (msb, lsb, sig_name, clk_prefix, sig_name, sig_name,
                       clk_prefix, cd_index_str, msb, lsb, data_width)
            decodes.append(decode_def + reg_def)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'strobe':
            read_strobe = 'wire %s = %s_read & (`ADDR_HIT_%s);\\\n' %\
                          (sig_name, clk_prefix, sig_name)
            decodes.append(read_strobe)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'we-strobe':
            reg_def = 'wire %s = we_%s;\\\n' % (sig_name, sig_name)
            decodes.append(decode_def + reg_def)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
        elif p.signal_type == 'plus-we-VOID':
            pass
        else:
            if p.signal_type == 'plus-we':
                we_def = 'wire %s_we = we_%s;\\\n' % (sig_name, sig_name)
            else:
                we_def = ''
            reg_def = 'reg [%d:%d] %s=0; always @(posedge %s_clk) '\
                      'if (we_%s) %s <= %s_data%s;\\\n' %\
                      (msb, lsb, sig_name, clk_prefix, sig_name, sig_name,
                       clk_prefix, cd_index_str)
            decodes.append(decode_def + we_def + reg_def)
            gch[sig_name] = (0, mod, sign, data_width, clk_prefix,
                             cd_index_str, p.description)
def make_decoder_inner ( inst , mod , p ) : if p . direction != 'output' : clk_prefix = p . clk_domain cd_index_str = '' if p . cd_indexed and p . cd_index is not None : cd_index_str = '[%d]' % p . cd_index key = use_ram_key ( p . module , p . name ) if inst is None : sig_name = re . sub ( ':' , '_' , p . name ) else : sig_name = '%s_%s' % ( inst , re . sub ( ':' , '_' , p . name ) ) decode_def = 'wire we_%s = %s_write%s&(`ADDR_HIT_%s);\\\n' % ( sig_name , clk_prefix , cd_index_str , sig_name ) msb = int ( p . downto [ 0 ] ) lsb = int ( p . downto [ 1 ] ) data_width = msb - lsb + 1 sign = p . sign if p . sign else 'unsigned' if key in use_ram : addr_range = use_ram [ key ] data_range = '[%d:%d]' % ( msb , lsb ) addr_width = range_width ( addr_range ) wire_def = 'wire %s %s_addr;\\\nwire %s %s;\\\n' % ( addr_range , sig_name , data_range , sig_name ) dpram_a = '.clka(%s_clk), .addra(%s_addr%s%s), .dina(%s_data%s%s),' ' .wena(we_%s)' % ( clk_prefix , clk_prefix , cd_index_str , addr_range , clk_prefix , cd_index_str , data_range , sig_name ) dpram_b = '.clkb(%s_clk), .addrb(%s_addr), .doutb(%s)' % ( clk_prefix , sig_name , sig_name ) dpram_def = 'dpram #(.aw(%d),.dw(%d)) dp_%s(\\\n\t%s,\\\n\t%s);\\\n' % ( addr_width , data_width , sig_name , dpram_a , dpram_b ) decodes . append ( wire_def + decode_def + dpram_def ) gch [ sig_name ] = ( addr_width , mod , sign , data_width , clk_prefix , cd_index_str , p . description ) elif p . signal_type == 'single-cycle' : reg_def = 'reg [%d:%d] %s=0; always @(posedge %s_clk) ' '%s <= we_%s ? %s_data%s[%d:%d] : %d\'b0;\\\n' % ( msb , lsb , sig_name , clk_prefix , sig_name , sig_name , clk_prefix , cd_index_str , msb , lsb , data_width ) decodes . append ( decode_def + reg_def ) gch [ sig_name ] = ( 0 , mod , sign , data_width , clk_prefix , cd_index_str , p . description ) elif p . signal_type == 'strobe' : read_strobe = 'wire %s = %s_read & (`ADDR_HIT_%s);\\\n' % ( sig_name , clk_prefix , sig_name ) decodes . append ( read_strobe ) gch [ sig_name ] = ( 0 , mod , sign , data_width , clk_prefix , cd_index_str , p . description ) elif p . signal_type == 'we-strobe' : reg_def = 'wire %s = we_%s;\\\n' % ( sig_name , sig_name ) decodes . append ( decode_def + reg_def ) gch [ sig_name ] = ( 0 , mod , sign , data_width , clk_prefix , cd_index_str , p . description ) elif p . signal_type == 'plus-we-VOID' : pass else : if p . signal_type == 'plus-we' : we_def = 'wire %s_we = we_%s;\\\n' % ( sig_name , sig_name ) else : we_def = '' reg_def = 'reg [%d:%d] %s=0; always @(posedge %s_clk) ' 'if (we_%s) %s <= %s_data%s;\\\n' % ( msb , lsb , sig_name , clk_prefix , sig_name , sig_name , clk_prefix , cd_index_str ) decodes . append ( decode_def + we_def + reg_def ) gch [ sig_name ] = ( 0 , mod , sign , data_width , clk_prefix , cd_index_str , p . description )
Constructs a decoder for a port p.
p: is an instance of Port
Constructs a decoder for a port p . p : is an instance of Port
'''
    Constructs a decoder for a port p.
    p: is an instance of Port
    ''' # print '// make_decoder',inst,mod,a # print '// make_decoder instance=%s name=%s'%(inst,a[5]) # print '// checking use_ram for key '+key # print '// ***** use_ram %s %s'%(key,use_ram[key]), addr_range, # addr_width, data_range, data_width
inst
mod
p