languages/gen_vhdl.py
def format_str_std_log_decl_val(self, decl):
		"""
		Format value of std_logic or std_logic_vector declaration given as
		string object.
		"""
		strVal = ""
		if (decl.bitWidth == 1):
			strVal = "'" + decl.value + "'"
		else:
			strVal = '"' + decl.value + '"'

		return strVal

		Format value of std_logic or std_logic_vector declaration given as
		string object.
		
Format value of std_logic or std_logic_vector declaration given as
string object.
Format value of std_logic or std_logic_vector declaration given as string object .
def format_str_std_log_decl_val(self, decl):
		strVal = ""
		if (decl.bitWidth == 1):
			strVal = "'" + decl.value + "'"
		else:
			strVal = '"' + decl.value + '"'
		return strVal
def format_str_std_log_decl_val ( self , decl ) : strVal = "" if ( decl . bitWidth == 1 ) : strVal = "'" + decl . value + "'" else : strVal = '"' + decl . value + '"' return strVal
Format value of std_logic or std_logic_vector declaration given as
string object.
Format value of std_logic or std_logic_vector declaration given as string object .
"""
		Format value of std_logic or std_logic_vector declaration given as
		string object.
		"""
self
decl