build-tools/newad.py
def parse_vfile(stack, fin, fd, dlist, clk_domain, cd_indexed, try_sv=True):
    '''
    Given a filename, parse Verilog:
    (a) looking for module instantiations marked automatic,
    for which we need to generate port assignments.
    When such an instantiation is found, recurse.
    (b) looking for input/output ports labeled 'external'.
    Record them in the port_lists dictionary for this module.
    '''
    fin_sv = splitext(fin)[0] + '.sv'
    searchpath = dirname(fin)
    fname = basename(fin)
    fname_sv = basename(fin_sv)
    fsearch = [fname, fname_sv] if try_sv else [fname]
    found = False
    for fn in fsearch:
        if isfile(fn):
            fin = fn
            break
        for d in dlist:
            x = d + '/' + fn
            if isfile(x):
                fin = x
                found = True
                break
        if found:
            break

    if not isfile(fin):
        print("File not found:", fin)
        print("(from hierarchy %s)" % stack)
        global file_not_found
        file_not_found += 1
        return
    fd.write('// parse_vfile %s %s\n' % (stack, fin))
    if searchpath == '':
        searchpath = '.'
    this_mod = fin.split('/')[-1].split('.')[0]
    verilog_file_lines = []
    # Looks like the reason we read the whole file is to avoid opening
    # several files at the same time
    with open(fin, 'r') as f:
        verilog_file_lines = f.readlines()
    this_port_list = []
    attributes = {}
    for line in verilog_file_lines:
        # Search for attributes
        m = re.search(DESCRIPTION_ATTRIBUTE, line)
        if m:
            value = m.group(1)
            attributes['description'] = value
        # (a) instantiations
        m = re.search(INSTANTIATION_SITE, line)
        if m:
            mod = m.group(1)
            inst = m.group(3)
            gspec = m.group(4)
            clk_domain_l = clk_domain
            cd_indexed_l = cd_indexed
            if m.group(6) is not None:
                clk_domain_l = m.group(6)
                if m.group(8) is not None:
                    cd_indexed_l = True
            if gspec is not None:
                mm = re.search(r'\((\w+),(\d+)\)', gspec)
                gvar = mm.group(1)
                gcnt = int(mm.group(2))
            else:
                gvar = None
                gcnt = None
            fd.write('// module=%s instance=%s gvar=%s gcnt=%s\n' %
                     (mod, inst, gvar, str(gcnt)))
            if mod not in port_lists:
                # recurse
                parse_vfile(stack + ':' + fin, searchpath + '/' + mod + '.v',
                            fd, dlist, clk_domain_l, cd_indexed_l)
            if not stack:
                print_instance_ports(inst, mod, gvar, gcnt, fd)
            # add this instance's ports to our own port list
            for p in port_lists[mod] if mod in port_lists else []:
                if gcnt is None:
                    p_p = deepcopy(p)  # p_prime
                    this_port_list.append(p_p.port_prefix_set(inst + ':'))
                else:
                    for ig in range(gcnt):
                        p_p = deepcopy(p)  # p_prime
                        p_p = p_p.port_prefix_set('%s_%d:' % (inst, ig))
                        if cd_indexed_l and m.group(6) is not None:
                            p_p.cd_index = ig
                        this_port_list.append(p_p)
                    if this_mod not in self_map:
                        self_map[this_mod] = []
                    construct_map(inst, p, gcnt, this_mod)
        # (b) ports
        # Search for port with register width defined 'input (signed)? [%d:%d] name // <...>'
        m = re.search(PORT_WIDTH_MULTI, line)
        if m:
            info = [m.group(i) for i in range(7)]
            p = Port(info[5], (info[3], info[4]), info[1], info[2], this_mod,
                     info[6], clk_domain, cd_indexed, **attributes)
            this_port_list.append(p)
            consider_port(p, fd)
            if info[6] == 'plus-we':
                p = Port(info[5] + '_we', (0, 0), info[1], None, this_mod,
                         info[6] + '-VOID', clk_domain, cd_indexed,
                         **attributes)
                this_port_list.append(p)
                consider_port(p, fd)
            attributes = {}
        else:
            m = re.search(PORT_WIDTH_SINGLE, line)
            if m:
                info = [m.group(i) for i in range(5)]
                p = Port(info[3], (0, 0), info[1], info[2], this_mod, info[4],
                         clk_domain, cd_indexed, **attributes)
                this_port_list.append(p)
                consider_port(p, fd)
                attributes = {}

        # (c) registers in the top-level file
        if not stack:
            m = re.search(TOP_LEVEL_REG, line)
            if m:
                info = [m.group(i) for i in range(6)]
                p = Port(info[4], (info[2], info[3]), 'top_level', info[1],
                         this_mod, info[5], clk_domain, cd_indexed,
                         **attributes)
                this_port_list.append(p)
                # Since these are top level registers, decoders can be generated here
                make_decoder(None, this_mod, p, None)
                attributes = {}
    # print '// debug',this_mod,this_port_list
    port_lists[this_mod] = this_port_list

    Given a filename, parse Verilog:
    (a) looking for module instantiations marked automatic,
    for which we need to generate port assignments.
    When such an instantiation is found, recurse.
    (b) looking for input/output ports labeled 'external'.
    Record them in the port_lists dictionary for this module.
    
Given a filename, parse Verilog:
(a) looking for module instantiations marked automatic,
for which we need to generate port assignments.
When such an instantiation is found, recurse.
(b) looking for input/output ports labeled 'external'.
Record them in the port_lists dictionary for this module.
Given a filename parse Verilog : ( a ) looking for module instantiations marked automatic for which we need to generate port assignments . When such an instantiation is found recurse . ( b ) looking for input / output ports labeled ' external ' . Record them in the port_lists dictionary for this module .
def parse_vfile(stack, fin, fd, dlist, clk_domain, cd_indexed, try_sv=True):
    fin_sv = splitext(fin)[0] + '.sv'
    searchpath = dirname(fin)
    fname = basename(fin)
    fname_sv = basename(fin_sv)
    fsearch = [fname, fname_sv] if try_sv else [fname]
    found = False
    for fn in fsearch:
        if isfile(fn):
            fin = fn
            break
        for d in dlist:
            x = d + '/' + fn
            if isfile(x):
                fin = x
                found = True
                break
        if found:
            break
    if not isfile(fin):
        print("File not found:", fin)
        print("(from hierarchy %s)" % stack)
        global file_not_found
        file_not_found += 1
        return
    fd.write('// parse_vfile %s %s\n' % (stack, fin))
    if searchpath == '':
        searchpath = '.'
    this_mod = fin.split('/')[-1].split('.')[0]
    verilog_file_lines = []
    with open(fin, 'r') as f:
        verilog_file_lines = f.readlines()
    this_port_list = []
    attributes = {}
    for line in verilog_file_lines:
        m = re.search(DESCRIPTION_ATTRIBUTE, line)
        if m:
            value = m.group(1)
            attributes['description'] = value
        m = re.search(INSTANTIATION_SITE, line)
        if m:
            mod = m.group(1)
            inst = m.group(3)
            gspec = m.group(4)
            clk_domain_l = clk_domain
            cd_indexed_l = cd_indexed
            if m.group(6) is not None:
                clk_domain_l = m.group(6)
                if m.group(8) is not None:
                    cd_indexed_l = True
            if gspec is not None:
                mm = re.search(r'\((\w+),(\d+)\)', gspec)
                gvar = mm.group(1)
                gcnt = int(mm.group(2))
            else:
                gvar = None
                gcnt = None
            fd.write('// module=%s instance=%s gvar=%s gcnt=%s\n' %
                     (mod, inst, gvar, str(gcnt)))
            if mod not in port_lists:
                parse_vfile(stack + ':' + fin, searchpath + '/' + mod + '.v',
                            fd, dlist, clk_domain_l, cd_indexed_l)
            if not stack:
                print_instance_ports(inst, mod, gvar, gcnt, fd)
            for p in port_lists[mod] if mod in port_lists else []:
                if gcnt is None:
                    p_p = deepcopy(p)  
                    this_port_list.append(p_p.port_prefix_set(inst + ':'))
                else:
                    for ig in range(gcnt):
                        p_p = deepcopy(p)  
                        p_p = p_p.port_prefix_set('%s_%d:' % (inst, ig))
                        if cd_indexed_l and m.group(6) is not None:
                            p_p.cd_index = ig
                        this_port_list.append(p_p)
                    if this_mod not in self_map:
                        self_map[this_mod] = []
                    construct_map(inst, p, gcnt, this_mod)
        m = re.search(PORT_WIDTH_MULTI, line)
        if m:
            info = [m.group(i) for i in range(7)]
            p = Port(info[5], (info[3], info[4]), info[1], info[2], this_mod,
                     info[6], clk_domain, cd_indexed, **attributes)
            this_port_list.append(p)
            consider_port(p, fd)
            if info[6] == 'plus-we':
                p = Port(info[5] + '_we', (0, 0), info[1], None, this_mod,
                         info[6] + '-VOID', clk_domain, cd_indexed,
                         **attributes)
                this_port_list.append(p)
                consider_port(p, fd)
            attributes = {}
        else:
            m = re.search(PORT_WIDTH_SINGLE, line)
            if m:
                info = [m.group(i) for i in range(5)]
                p = Port(info[3], (0, 0), info[1], info[2], this_mod, info[4],
                         clk_domain, cd_indexed, **attributes)
                this_port_list.append(p)
                consider_port(p, fd)
                attributes = {}
        if not stack:
            m = re.search(TOP_LEVEL_REG, line)
            if m:
                info = [m.group(i) for i in range(6)]
                p = Port(info[4], (info[2], info[3]), 'top_level', info[1],
                         this_mod, info[5], clk_domain, cd_indexed,
                         **attributes)
                this_port_list.append(p)
                make_decoder(None, this_mod, p, None)
                attributes = {}
    port_lists[this_mod] = this_port_list
def parse_vfile ( stack , fin , fd , dlist , clk_domain , cd_indexed , try_sv = True ) : fin_sv = splitext ( fin ) [ 0 ] + '.sv' searchpath = dirname ( fin ) fname = basename ( fin ) fname_sv = basename ( fin_sv ) fsearch = [ fname , fname_sv ] if try_sv else [ fname ] found = False for fn in fsearch : if isfile ( fn ) : fin = fn break for d in dlist : x = d + '/' + fn if isfile ( x ) : fin = x found = True break if found : break if not isfile ( fin ) : print ( "File not found:" , fin ) print ( "(from hierarchy %s)" % stack ) global file_not_found file_not_found += 1 return fd . write ( '// parse_vfile %s %s\n' % ( stack , fin ) ) if searchpath == '' : searchpath = '.' this_mod = fin . split ( '/' ) [ - 1 ] . split ( '.' ) [ 0 ] verilog_file_lines = [ ] with open ( fin , 'r' ) as f : verilog_file_lines = f . readlines ( ) this_port_list = [ ] attributes = { } for line in verilog_file_lines : m = re . search ( DESCRIPTION_ATTRIBUTE , line ) if m : value = m . group ( 1 ) attributes [ 'description' ] = value m = re . search ( INSTANTIATION_SITE , line ) if m : mod = m . group ( 1 ) inst = m . group ( 3 ) gspec = m . group ( 4 ) clk_domain_l = clk_domain cd_indexed_l = cd_indexed if m . group ( 6 ) is not None : clk_domain_l = m . group ( 6 ) if m . group ( 8 ) is not None : cd_indexed_l = True if gspec is not None : mm = re . search ( r'\((\w+),(\d+)\)' , gspec ) gvar = mm . group ( 1 ) gcnt = int ( mm . group ( 2 ) ) else : gvar = None gcnt = None fd . write ( '// module=%s instance=%s gvar=%s gcnt=%s\n' % ( mod , inst , gvar , str ( gcnt ) ) ) if mod not in port_lists : parse_vfile ( stack + ':' + fin , searchpath + '/' + mod + '.v' , fd , dlist , clk_domain_l , cd_indexed_l ) if not stack : print_instance_ports ( inst , mod , gvar , gcnt , fd ) for p in port_lists [ mod ] if mod in port_lists else [ ] : if gcnt is None : p_p = deepcopy ( p ) this_port_list . append ( p_p . port_prefix_set ( inst + ':' ) ) else : for ig in range ( gcnt ) : p_p = deepcopy ( p ) p_p = p_p . port_prefix_set ( '%s_%d:' % ( inst , ig ) ) if cd_indexed_l and m . group ( 6 ) is not None : p_p . cd_index = ig this_port_list . append ( p_p ) if this_mod not in self_map : self_map [ this_mod ] = [ ] construct_map ( inst , p , gcnt , this_mod ) m = re . search ( PORT_WIDTH_MULTI , line ) if m : info = [ m . group ( i ) for i in range ( 7 ) ] p = Port ( info [ 5 ] , ( info [ 3 ] , info [ 4 ] ) , info [ 1 ] , info [ 2 ] , this_mod , info [ 6 ] , clk_domain , cd_indexed , ** attributes ) this_port_list . append ( p ) consider_port ( p , fd ) if info [ 6 ] == 'plus-we' : p = Port ( info [ 5 ] + '_we' , ( 0 , 0 ) , info [ 1 ] , None , this_mod , info [ 6 ] + '-VOID' , clk_domain , cd_indexed , ** attributes ) this_port_list . append ( p ) consider_port ( p , fd ) attributes = { } else : m = re . search ( PORT_WIDTH_SINGLE , line ) if m : info = [ m . group ( i ) for i in range ( 5 ) ] p = Port ( info [ 3 ] , ( 0 , 0 ) , info [ 1 ] , info [ 2 ] , this_mod , info [ 4 ] , clk_domain , cd_indexed , ** attributes ) this_port_list . append ( p ) consider_port ( p , fd ) attributes = { } if not stack : m = re . search ( TOP_LEVEL_REG , line ) if m : info = [ m . group ( i ) for i in range ( 6 ) ] p = Port ( info [ 4 ] , ( info [ 2 ] , info [ 3 ] ) , 'top_level' , info [ 1 ] , this_mod , info [ 5 ] , clk_domain , cd_indexed , ** attributes ) this_port_list . append ( p ) make_decoder ( None , this_mod , p , None ) attributes = { } port_lists [ this_mod ] = this_port_list
Given a filename, parse Verilog:
(a) looking for module instantiations marked automatic,
for which we need to generate port assignments.
Given a filename parse Verilog : ( a ) looking for module instantiations marked automatic for which we need to generate port assignments .
'''
    Given a filename, parse Verilog:
    (a) looking for module instantiations marked automatic,
    for which we need to generate port assignments.
    When such an instantiation is found, recurse.
    (b) looking for input/output ports labeled 'external'.
    Record them in the port_lists dictionary for this module.
    ''' # Looks like the reason we read the whole file is to avoid opening # several files at the same time # Search for attributes # (a) instantiations # recurse # add this instance's ports to our own port list # p_prime # p_prime # (b) ports # Search for port with register width defined 'input (signed)? [%d:%d] name // <...>' # (c) registers in the top-level file # Since these are top level registers, decoders can be generated here # print '// debug',this_mod,this_port_list
stack
fin
fd
dlist
clk_domain
cd_indexed
try_sv