ip_xact/vhdl_reg_map_generator.py
def create_output_reg_record(self, block):
		"""
		Create record for writable registers from IP-XACT memory block object.
		If register write should be indicated, additional <reg_name>_write signal
		is added.
		If register read should be indicated, additional <reg_name>_read signal is
		added.
		"""
		outDecls = []
		outName = block.name + "_out_t"

		# Create the declarations
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):

			if ("write" in reg.access):
				outDecls.append(LanDeclaration(reg.name, value=""))
				outDecls[-1].type = "std_logic_vector"
				outDecls[-1].bitWidth = reg.size
				outDecls[-1].specifier = ""

			if (self.is_reg_write_indicate(reg)):
				outDecls.append(LanDeclaration(reg.name + "_update", value=""))
				outDecls[-1].type = "std_logic"
				outDecls[-1].bitWidth = 1
				outDecls[-1].specifier = ""

			if (self.is_reg_read_indicate(reg)):
				outDecls.append(LanDeclaration(reg.name + "_read", value=""))
				outDecls[-1].type = "std_logic"
				outDecls[-1].bitWidth = 1
				outDecls[-1].specifier = ""

		# Format the declaration
		self.hdlGen.format_decls(outDecls, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)

		self.hdlGen.create_structure(outName, outDecls, gap = 2)

		Create record for writable registers from IP-XACT memory block object.
		If register write should be indicated, additional <reg_name>_write signal
		is added.
		If register read should be indicated, additional <reg_name>_read signal is
		added.
		
Create record for writable registers from IP-XACT memory block object.
If register write should be indicated, additional _write signal
is added.
If register read should be indicated, additional _read signal is
added.
Create record for writable registers from IP - XACT memory block object . If register write should be indicated additional _write signal is added . If register read should be indicated additional _read signal is added .
def create_output_reg_record(self, block):
		outDecls = []
		outName = block.name + "_out_t"
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
			if ("write" in reg.access):
				outDecls.append(LanDeclaration(reg.name, value=""))
				outDecls[-1].type = "std_logic_vector"
				outDecls[-1].bitWidth = reg.size
				outDecls[-1].specifier = ""
			if (self.is_reg_write_indicate(reg)):
				outDecls.append(LanDeclaration(reg.name + "_update", value=""))
				outDecls[-1].type = "std_logic"
				outDecls[-1].bitWidth = 1
				outDecls[-1].specifier = ""
			if (self.is_reg_read_indicate(reg)):
				outDecls.append(LanDeclaration(reg.name + "_read", value=""))
				outDecls[-1].type = "std_logic"
				outDecls[-1].bitWidth = 1
				outDecls[-1].specifier = ""
		self.hdlGen.format_decls(outDecls, gap=2, alignLeft=True,
					alignRight=False, alignLen=30, wrap=False)
		self.hdlGen.create_structure(outName, outDecls, gap = 2)
def create_output_reg_record ( self , block ) : outDecls = [ ] outName = block . name + "_out_t" for i , reg in enumerate ( sorted ( block . register , key = lambda a : a . addressOffset ) ) : if ( "write" in reg . access ) : outDecls . append ( LanDeclaration ( reg . name , value = "" ) ) outDecls [ - 1 ] . type = "std_logic_vector" outDecls [ - 1 ] . bitWidth = reg . size outDecls [ - 1 ] . specifier = "" if ( self . is_reg_write_indicate ( reg ) ) : outDecls . append ( LanDeclaration ( reg . name + "_update" , value = "" ) ) outDecls [ - 1 ] . type = "std_logic" outDecls [ - 1 ] . bitWidth = 1 outDecls [ - 1 ] . specifier = "" if ( self . is_reg_read_indicate ( reg ) ) : outDecls . append ( LanDeclaration ( reg . name + "_read" , value = "" ) ) outDecls [ - 1 ] . type = "std_logic" outDecls [ - 1 ] . bitWidth = 1 outDecls [ - 1 ] . specifier = "" self . hdlGen . format_decls ( outDecls , gap = 2 , alignLeft = True , alignRight = False , alignLen = 30 , wrap = False ) self . hdlGen . create_structure ( outName , outDecls , gap = 2 )
Create record for writable registers from IP-XACT memory block object.
Create record for writable registers from IP - XACT memory block object .
"""
		Create record for writable registers from IP-XACT memory block object.
		If register write should be indicated, additional <reg_name>_write signal
		is added.
		If register read should be indicated, additional <reg_name>_read signal is
		added.
		""" # Create the declarations # Format the declaration
self
block