ip_xact/vhdl_addr_generator.py
def write_reg_field(self, field, reg):
		""" 
		Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
		property to concatenate register indices into word aligned sizes.
		E.g. register with 0x1 offset will start at index 8, 0x2 at index 16 etc...
		Write to the generator output.
		Arguments:
			field		Register field object (parsed from pyXact) whose 
						field indices to write.
			reg			Register object (parsed from pyXact) to which belongs
						the field in previous argument.
		"""
		bitIndexL = field.bitOffset
		bitIndexH = field.bitOffset + field.bitWidth-1

		bitIndexL = bitIndexL + ((reg.addressOffset*8) % self.wrdWidthBit)
		bitIndexH = bitIndexH + ((reg.addressOffset*8) % self.wrdWidthBit)

        # Distinguish between single bit and multiple bit fields		
		if (bitIndexH == bitIndexL):
			iterator = [["_IND", bitIndexL]]
		else:
			iterator = [["_L", bitIndexL], ["_H", bitIndexH]]

		for item in iterator:
			decl = LanDeclaration(field.name+item[0], item[1], "natural",
									field.bitWidth, "constant", 50)
			self.vhdlGen.write_decl(decl)
 
		Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
		property to concatenate register indices into word aligned sizes.
		E.g. register with 0x1 offset will start at index 8, 0x2 at index 16 etc...
		Write to the generator output.
		Arguments:
			field		Register field object (parsed from pyXact) whose 
						field indices to write.
			reg			Register object (parsed from pyXact) to which belongs
						the field in previous argument.
		
Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
property to concatenate register indices into word aligned sizes.
Write IP - XACT register field indices as VHDL constants . Use " wrdWidthBit " property to concatenate register indices into word aligned sizes .
def write_reg_field(self, field, reg):
		bitIndexL = field.bitOffset
		bitIndexH = field.bitOffset + field.bitWidth-1
		bitIndexL = bitIndexL + ((reg.addressOffset*8) % self.wrdWidthBit)
		bitIndexH = bitIndexH + ((reg.addressOffset*8) % self.wrdWidthBit)
		if (bitIndexH == bitIndexL):
			iterator = [["_IND", bitIndexL]]
		else:
			iterator = [["_L", bitIndexL], ["_H", bitIndexH]]
		for item in iterator:
			decl = LanDeclaration(field.name+item[0], item[1], "natural",
									field.bitWidth, "constant", 50)
			self.vhdlGen.write_decl(decl)
def write_reg_field ( self , field , reg ) : bitIndexL = field . bitOffset bitIndexH = field . bitOffset + field . bitWidth - 1 bitIndexL = bitIndexL + ( ( reg . addressOffset * 8 ) % self . wrdWidthBit ) bitIndexH = bitIndexH + ( ( reg . addressOffset * 8 ) % self . wrdWidthBit ) if ( bitIndexH == bitIndexL ) : iterator = [ [ "_IND" , bitIndexL ] ] else : iterator = [ [ "_L" , bitIndexL ] , [ "_H" , bitIndexH ] ] for item in iterator : decl = LanDeclaration ( field . name + item [ 0 ] , item [ 1 ] , "natural" , field . bitWidth , "constant" , 50 ) self . vhdlGen . write_decl ( decl )
Write IP-XACT register field indices as VHDL constants.
Write IP - XACT register field indices as VHDL constants .
""" 
		Write IP-XACT register field indices as VHDL constants. Use "wrdWidthBit"
		property to concatenate register indices into word aligned sizes.
		E.g. register with 0x1 offset will start at index 8, 0x2 at index 16 etc...
		Write to the generator output.
		Arguments:
			field		Register field object (parsed from pyXact) whose 
						field indices to write.
			reg			Register object (parsed from pyXact) to which belongs
						the field in previous argument.
		""" # Distinguish between single bit and multiple bit fields		
self
field
reg