ip_xact/vhdl_reg_map_generator.py
def create_write_reg_instances(self, block):
		"""
		Create VHDL instance for each writable register in a memory block.
		"""
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):

			# Create register instances for writable registers
			if (self.reg_has_access_type(reg, ["write"])):
				self.create_reg_instance(block, reg)

			# Create access signalling for registers which have signalling enabled
			if (self.is_reg_write_indicate(reg) or self.is_reg_read_indicate(reg)):
				self.create_access_signaller(block, reg)

		Create VHDL instance for each writable register in a memory block.
		
Create VHDL instance for each writable register in a memory block.
Create VHDL instance for each writable register in a memory block .
def create_write_reg_instances(self, block):
		for i,reg in enumerate(sorted(block.register, key=lambda a: a.addressOffset)):
			if (self.reg_has_access_type(reg, ["write"])):
				self.create_reg_instance(block, reg)
			if (self.is_reg_write_indicate(reg) or self.is_reg_read_indicate(reg)):
				self.create_access_signaller(block, reg)
def create_write_reg_instances ( self , block ) : for i , reg in enumerate ( sorted ( block . register , key = lambda a : a . addressOffset ) ) : if ( self . reg_has_access_type ( reg , [ "write" ] ) ) : self . create_reg_instance ( block , reg ) if ( self . is_reg_write_indicate ( reg ) or self . is_reg_read_indicate ( reg ) ) : self . create_access_signaller ( block , reg )
Create VHDL instance for each writable register in a memory block.
Create VHDL instance for each writable register in a memory block .
"""
		Create VHDL instance for each writable register in a memory block.
		""" # Create register instances for writable registers # Create access signalling for registers which have signalling enabled
self
block