ip_xact/vhdl_reg_map_generator.py
def create_read_wrd_from_regs(self, regs_in_wrd, block):
		"""
		Create single read word input to read data multiplexor input. Readable
		registers are implemented. 
		"""
		read_wrd = "    "
		for byte_ind in range(self.wrdWidthByte - 1, -1, -1):

			pad_zeroes = True
			for reg in regs_in_wrd:

				# Skip registers which are not readable
				if (not (self.reg_has_access_type(reg, ["read"]))):
					continue;

				[pad_zeroes, read_wrd] = self.append_reg_byte_val(block, reg, 
											byte_ind, read_wrd)
				if (pad_zeroes == False):
					break

			# If there is no register on this byte append zeroes as read data
			if (pad_zeroes):
				read_wrd += '"' + '0' * 8 + '"'
				if (byte_ind != 0):
					read_wrd += " & "

		return read_wrd

		Create single read word input to read data multiplexor input. Readable
		registers are implemented. 
		
Create single read word input to read data multiplexor input. Readable
registers are implemented.
Create single read word input to read data multiplexor input . Readable registers are implemented .
def create_read_wrd_from_regs(self, regs_in_wrd, block):
		read_wrd = "    "
		for byte_ind in range(self.wrdWidthByte - 1, -1, -1):
			pad_zeroes = True
			for reg in regs_in_wrd:
				if (not (self.reg_has_access_type(reg, ["read"]))):
					continue;
				[pad_zeroes, read_wrd] = self.append_reg_byte_val(block, reg, 
											byte_ind, read_wrd)
				if (pad_zeroes == False):
					break
			if (pad_zeroes):
				read_wrd += '"' + '0' * 8 + '"'
				if (byte_ind != 0):
					read_wrd += " & "
		return read_wrd
def create_read_wrd_from_regs ( self , regs_in_wrd , block ) : read_wrd = "    " for byte_ind in range ( self . wrdWidthByte - 1 , - 1 , - 1 ) : pad_zeroes = True for reg in regs_in_wrd : if ( not ( self . reg_has_access_type ( reg , [ "read" ] ) ) ) : continue ; [ pad_zeroes , read_wrd ] = self . append_reg_byte_val ( block , reg , byte_ind , read_wrd ) if ( pad_zeroes == False ) : break if ( pad_zeroes ) : read_wrd += '"' + '0' * 8 + '"' if ( byte_ind != 0 ) : read_wrd += " & " return read_wrd
Create single read word input to read data multiplexor input.
Create single read word input to read data multiplexor input .
"""
		Create single read word input to read data multiplexor input. Readable
		registers are implemented. 
		""" # Skip registers which are not readable # If there is no register on this byte append zeroes as read data
self
regs_in_wrd
block