sonar/core/backends/sv.py
def add_exerciser_ports(testbench_config, testbench, used_interfaces):
    """
    Add the ports of the Exerciser

    Args:
        testbench_config (Testbench): The testbench configuration
        testbench (str): The testbench being generated
        used_interfaces (dict): Each used interface appears once

    Returns:
        str: Updated testbench
    """

    def add_interfaces(exerciser_ports):
        interfaces = testbench_config.get_from_dut("interfaces_dict")
        for direction in ["slave", "master", "mixed"]:
            for interface in interfaces[direction]:
                curr_interface = used_interfaces[interface.interface_type]
                for signal_type, signal in interface.signals.items():
                    exerciser_ports += leading_spaces
                    if direction in ["slave", "mixed"]:
                        if signal_type in curr_interface.signals["input"]:
                            exerciser_ports += "input "
                        else:
                            exerciser_ports += "output "
                            init_signals.append(
                                interface.name + "_" + signal_type
                            )
                    else:
                        if signal_type in curr_interface.signals["output"]:
                            exerciser_ports += "input "
                        else:
                            exerciser_ports += "output "
                            init_signals.append(
                                interface.name + "_" + signal_type
                            )
                    exerciser_ports += "logic "
                    if int(signal.size) != 1:
                        exerciser_ports += (
                            "[" + str(int(signal.size) - 1) + ":0] "
                        )
                    exerciser_ports += (
                        interface.name + "_" + signal_type + ",\n"
                    )
        return exerciser_ports

    def resolve_init_signals():
        init_commands = []
        for init_signal in init_signals:
            init_commands.append({"signal": {"name": init_signal, "value": 0}})

        for i, vector in enumerate(testbench_config.vectors):
            for j, thread in enumerate(vector.threads):
                for k, command in enumerate(thread.commands):
                    if (
                        "macro" in command
                        and command["macro"] == "INIT_SIGNALS"
                    ):
                        testbench_config.vectors[i].threads[j].commands[k][
                            "commands"
                        ] = init_commands

    dut = testbench_config.modules["DUT"]
    clocks_in = dut.ports.get_clocks("input")
    signals_in = dut.ports.get_signals("input")
    resets_in = dut.ports.get_resets("input")
    signals_out = dut.ports.get_signals("output")

    init_signals = []

    exerciser_ports = ""
    leading_spaces = include.get_indentation(
        "SONAR_EXERCISER_PORTS", testbench
    )
    for clock in clocks_in:
        if exerciser_ports != "":
            exerciser_ports += leading_spaces
        exerciser_ports += "output logic " + clock.name + ",\n"

    exerciser_ports = add_interfaces(exerciser_ports)

    for signal in itertools.chain(signals_in, resets_in):
        exerciser_ports += leading_spaces + "output logic "
        if int(signal.size) != 1:
            exerciser_ports += "[" + str(int(signal.size) - 1) + ":0] "
        exerciser_ports += signal.name + ",\n"
        init_signals.append(signal.name)
    for signal in signals_out:
        exerciser_ports += leading_spaces + "input logic "
        if int(signal.size) != 1:
            exerciser_ports += "[" + str(int(signal.size) - 1) + ":0] "
        exerciser_ports += signal.name + ",\n"
    testbench = include.replace_in_testbenches(
        testbench, "SONAR_EXERCISER_PORTS", exerciser_ports[:-2]
    )

    resolve_init_signals()

    return testbench, testbench_config

    Add the ports of the Exerciser

    Args:
        testbench_config (Testbench): The testbench configuration
        testbench (str): The testbench being generated
        used_interfaces (dict): Each used interface appears once

    Returns:
        str: Updated testbench
    
Add the ports of the Exerciser
Add the ports of the Exerciser
def add_exerciser_ports(testbench_config, testbench, used_interfaces):
    def add_interfaces(exerciser_ports):
        interfaces = testbench_config.get_from_dut("interfaces_dict")
        for direction in ["slave", "master", "mixed"]:
            for interface in interfaces[direction]:
                curr_interface = used_interfaces[interface.interface_type]
                for signal_type, signal in interface.signals.items():
                    exerciser_ports += leading_spaces
                    if direction in ["slave", "mixed"]:
                        if signal_type in curr_interface.signals["input"]:
                            exerciser_ports += "input "
                        else:
                            exerciser_ports += "output "
                            init_signals.append(
                                interface.name + "_" + signal_type
                            )
                    else:
                        if signal_type in curr_interface.signals["output"]:
                            exerciser_ports += "input "
                        else:
                            exerciser_ports += "output "
                            init_signals.append(
                                interface.name + "_" + signal_type
                            )
                    exerciser_ports += "logic "
                    if int(signal.size) != 1:
                        exerciser_ports += (
                            "[" + str(int(signal.size) - 1) + ":0] "
                        )
                    exerciser_ports += (
                        interface.name + "_" + signal_type + ",\n"
                    )
        return exerciser_ports
    def resolve_init_signals():
        init_commands = []
        for init_signal in init_signals:
            init_commands.append({"signal": {"name": init_signal, "value": 0}})
        for i, vector in enumerate(testbench_config.vectors):
            for j, thread in enumerate(vector.threads):
                for k, command in enumerate(thread.commands):
                    if (
                        "macro" in command
                        and command["macro"] == "INIT_SIGNALS"
                    ):
                        testbench_config.vectors[i].threads[j].commands[k][
                            "commands"
                        ] = init_commands
    dut = testbench_config.modules["DUT"]
    clocks_in = dut.ports.get_clocks("input")
    signals_in = dut.ports.get_signals("input")
    resets_in = dut.ports.get_resets("input")
    signals_out = dut.ports.get_signals("output")
    init_signals = []
    exerciser_ports = ""
    leading_spaces = include.get_indentation(
        "SONAR_EXERCISER_PORTS", testbench
    )
    for clock in clocks_in:
        if exerciser_ports != "":
            exerciser_ports += leading_spaces
        exerciser_ports += "output logic " + clock.name + ",\n"
    exerciser_ports = add_interfaces(exerciser_ports)
    for signal in itertools.chain(signals_in, resets_in):
        exerciser_ports += leading_spaces + "output logic "
        if int(signal.size) != 1:
            exerciser_ports += "[" + str(int(signal.size) - 1) + ":0] "
        exerciser_ports += signal.name + ",\n"
        init_signals.append(signal.name)
    for signal in signals_out:
        exerciser_ports += leading_spaces + "input logic "
        if int(signal.size) != 1:
            exerciser_ports += "[" + str(int(signal.size) - 1) + ":0] "
        exerciser_ports += signal.name + ",\n"
    testbench = include.replace_in_testbenches(
        testbench, "SONAR_EXERCISER_PORTS", exerciser_ports[:-2]
    )
    resolve_init_signals()
    return testbench, testbench_config
def add_exerciser_ports ( testbench_config , testbench , used_interfaces ) : def add_interfaces ( exerciser_ports ) : interfaces = testbench_config . get_from_dut ( "interfaces_dict" ) for direction in [ "slave" , "master" , "mixed" ] : for interface in interfaces [ direction ] : curr_interface = used_interfaces [ interface . interface_type ] for signal_type , signal in interface . signals . items ( ) : exerciser_ports += leading_spaces if direction in [ "slave" , "mixed" ] : if signal_type in curr_interface . signals [ "input" ] : exerciser_ports += "input " else : exerciser_ports += "output " init_signals . append ( interface . name + "_" + signal_type ) else : if signal_type in curr_interface . signals [ "output" ] : exerciser_ports += "input " else : exerciser_ports += "output " init_signals . append ( interface . name + "_" + signal_type ) exerciser_ports += "logic " if int ( signal . size ) != 1 : exerciser_ports += ( "[" + str ( int ( signal . size ) - 1 ) + ":0] " ) exerciser_ports += ( interface . name + "_" + signal_type + ",\n" ) return exerciser_ports def resolve_init_signals ( ) : init_commands = [ ] for init_signal in init_signals : init_commands . append ( { "signal" : { "name" : init_signal , "value" : 0 } } ) for i , vector in enumerate ( testbench_config . vectors ) : for j , thread in enumerate ( vector . threads ) : for k , command in enumerate ( thread . commands ) : if ( "macro" in command and command [ "macro" ] == "INIT_SIGNALS" ) : testbench_config . vectors [ i ] . threads [ j ] . commands [ k ] [ "commands" ] = init_commands dut = testbench_config . modules [ "DUT" ] clocks_in = dut . ports . get_clocks ( "input" ) signals_in = dut . ports . get_signals ( "input" ) resets_in = dut . ports . get_resets ( "input" ) signals_out = dut . ports . get_signals ( "output" ) init_signals = [ ] exerciser_ports = "" leading_spaces = include . get_indentation ( "SONAR_EXERCISER_PORTS" , testbench ) for clock in clocks_in : if exerciser_ports != "" : exerciser_ports += leading_spaces exerciser_ports += "output logic " + clock . name + ",\n" exerciser_ports = add_interfaces ( exerciser_ports ) for signal in itertools . chain ( signals_in , resets_in ) : exerciser_ports += leading_spaces + "output logic " if int ( signal . size ) != 1 : exerciser_ports += "[" + str ( int ( signal . size ) - 1 ) + ":0] " exerciser_ports += signal . name + ",\n" init_signals . append ( signal . name ) for signal in signals_out : exerciser_ports += leading_spaces + "input logic " if int ( signal . size ) != 1 : exerciser_ports += "[" + str ( int ( signal . size ) - 1 ) + ":0] " exerciser_ports += signal . name + ",\n" testbench = include . replace_in_testbenches ( testbench , "SONAR_EXERCISER_PORTS" , exerciser_ports [ : - 2 ] ) resolve_init_signals ( ) return testbench , testbench_config
Add the ports of the Exerciser
Add the ports of the Exerciser
"""
    Add the ports of the Exerciser

    Args:
        testbench_config (Testbench): The testbench configuration
        testbench (str): The testbench being generated
        used_interfaces (dict): Each used interface appears once

    Returns:
        str: Updated testbench
    """
None
str
testbench_config
The testbench configuration
The testbench configuration
testbench
The testbench being generated
The testbench being generated
used_interfaces
Each used interface appears once
Each used interface appears once