languages/gen_vhdl.py
def load_entity_template(self, path):
		"""
		Load entity template from VHDL file. Recognizes: entity name,
		Entity ports, generics. Note that on each generic "constant"
		must be explicitly specified. On each port "signal" must be
		explicitly specified. Direction must be specified on each signal!
        Parsing stops upon "architecture" definition start.
		Return declaration object of parsed entity. 
		Arguments:
			TODO
		"""
		if (not(path.endswith(".vhd"))):
			print("Only VHDL files are supported for parsing!")
			return

		fd = open(path)

		# Entity name parser
		ent_re = re.compile("^[ ]*entity[ ]*[\w]+[ ]*is$")
		
		# Architecture parser
		# Upon start of architecture parsing is finished, otherwise internal
		# signals would be parsed too!
		architecture_re = re.compile("^[ ]*architecture[ ]+[\w]+[ ]+of[ ]+[\w]+[ ]+is[ ]*$")
 	
		entity = LanDeclaration("name", value="")
		entity.intType = "entity"

		for line in fd:
			line = line.lower()

			# Finish when architecture starts
			arch_res = architecture_re.match(line)
			if (arch_res):
				break

			# Get name of entity
			ent_res = ent_re.match(line)
			if (ent_res):
				mtch = re.compile("[\w]+").findall(line)
				entity.name = mtch[1]
			
			# Parse ports or generics
			port_or_gen = self.parse_gen_or_port(line)			
			if (port_or_gen == None):	
				continue

			if (port_or_gen.specifier == "signal"):
				entity.ports[port_or_gen.name] = port_or_gen

			elif (port_or_gen.specifier == "constant"):
				entity.generics[port_or_gen.name] = port_or_gen

		fd.close()
		return entity

		Load entity template from VHDL file. Recognizes: entity name,
		Entity ports, generics. Note that on each generic "constant"
		must be explicitly specified. On each port "signal" must be
		explicitly specified. Direction must be specified on each signal!
        Parsing stops upon "architecture" definition start.
		Return declaration object of parsed entity. 
		Arguments:
			TODO
		
Load entity template from VHDL file. Recognizes: entity name,
Entity ports, generics. Note that on each generic "constant"
must be explicitly specified. On each port "signal" must be
explicitly specified. Direction must be specified on each signal.
Parsing stops upon "architecture" definition start.
Return declaration object of parsed entity.
Arguments:
TODO
Load entity template from VHDL file . Recognizes : entity name Entity ports generics . Note that on each generic " constant " must be explicitly specified . On each port " signal " must be explicitly specified . Direction must be specified on each signal . Parsing stops upon " architecture " definition start . Return declaration object of parsed entity . Arguments : TODO
def load_entity_template(self, path):
		if (not(path.endswith(".vhd"))):
			print("Only VHDL files are supported for parsing!")
			return
		fd = open(path)
		ent_re = re.compile("^[ ]*entity[ ]*[\w]+[ ]*is$")
		architecture_re = re.compile("^[ ]*architecture[ ]+[\w]+[ ]+of[ ]+[\w]+[ ]+is[ ]*$")
		entity = LanDeclaration("name", value="")
		entity.intType = "entity"
		for line in fd:
			line = line.lower()
			arch_res = architecture_re.match(line)
			if (arch_res):
				break
			ent_res = ent_re.match(line)
			if (ent_res):
				mtch = re.compile("[\w]+").findall(line)
				entity.name = mtch[1]
			port_or_gen = self.parse_gen_or_port(line)			
			if (port_or_gen == None):	
				continue
			if (port_or_gen.specifier == "signal"):
				entity.ports[port_or_gen.name] = port_or_gen
			elif (port_or_gen.specifier == "constant"):
				entity.generics[port_or_gen.name] = port_or_gen
		fd.close()
		return entity
def load_entity_template ( self , path ) : if ( not ( path . endswith ( ".vhd" ) ) ) : print ( "Only VHDL files are supported for parsing!" ) return fd = open ( path ) ent_re = re . compile ( "^[ ]*entity[ ]*[\w]+[ ]*is$" ) architecture_re = re . compile ( "^[ ]*architecture[ ]+[\w]+[ ]+of[ ]+[\w]+[ ]+is[ ]*$" ) entity = LanDeclaration ( "name" , value = "" ) entity . intType = "entity" for line in fd : line = line . lower ( ) arch_res = architecture_re . match ( line ) if ( arch_res ) : break ent_res = ent_re . match ( line ) if ( ent_res ) : mtch = re . compile ( "[\w]+" ) . findall ( line ) entity . name = mtch [ 1 ] port_or_gen = self . parse_gen_or_port ( line ) if ( port_or_gen == None ) : continue if ( port_or_gen . specifier == "signal" ) : entity . ports [ port_or_gen . name ] = port_or_gen elif ( port_or_gen . specifier == "constant" ) : entity . generics [ port_or_gen . name ] = port_or_gen fd . close ( ) return entity
Load entity template from VHDL file.
Load entity template from VHDL file .
"""
		Load entity template from VHDL file. Recognizes: entity name,
		Entity ports, generics. Note that on each generic "constant"
		must be explicitly specified. On each port "signal" must be
		explicitly specified. Direction must be specified on each signal!
        Parsing stops upon "architecture" definition start.
		Return declaration object of parsed entity. 
		Arguments:
			TODO
		""" # Entity name parser # Architecture parser # Upon start of architecture parsing is finished, otherwise internal # signals would be parsed too! # Finish when architecture starts # Get name of entity # Parse ports or generics
self
path