ip_xact/vhdl_reg_map_generator.py
def create_internal_decls(self, block, signDict):
		"""
		Create declarations of internal signals of architecture of register
		memory block. Following declarations are created:
			- Write selector signal for all writable registers
			- Address vector input to address decoder
			- Read data multiplexor input vector.
			- Read data mask signal from byte enable signals
            - Internal signal for output register structure
		"""
		if (not checkIsDict(signDict)):
			return;

		# Create output of address decoder
		self.create_wr_reg_sel_decl(block, signDict) 

		# Create address vector input to address decoder
		self.create_addr_vect_decl(block, signDict)

		# Create data mux input signal (long logic vector)
		self.create_read_data_mux_in_decl(block, signDict)
		
		# Create data mask signal for read multiplextor
		self.create_read_data_mask_n_decl(block, signDict)

		# Create internal signal for output register structure (output values
		# of writable registers)
		self.create_write_data_int_decl(block, signDict)

		# Create declaration of read data clear signal
		self.create_read_mux_ena_int_decl(signDict)

		Create declarations of internal signals of architecture of register
		memory block. Following declarations are created:
			- Write selector signal for all writable registers
			- Address vector input to address decoder
			- Read data multiplexor input vector.
			- Read data mask signal from byte enable signals
            - Internal signal for output register structure
		
Create declarations of internal signals of architecture of register
memory block. Following declarations are created:
Write selector signal for all writable registers
Address vector input to address decoder
Read data multiplexor input vector.
Read data mask signal from byte enable signals
Internal signal for output register structure
Create declarations of internal signals of architecture of register memory block . Following declarations are created : Write selector signal for all writable registers Address vector input to address decoder Read data multiplexor input vector . Read data mask signal from byte enable signals Internal signal for output register structure
def create_internal_decls(self, block, signDict):
		if (not checkIsDict(signDict)):
			return;
		self.create_wr_reg_sel_decl(block, signDict) 
		self.create_addr_vect_decl(block, signDict)
		self.create_read_data_mux_in_decl(block, signDict)
		self.create_read_data_mask_n_decl(block, signDict)
		self.create_write_data_int_decl(block, signDict)
		self.create_read_mux_ena_int_decl(signDict)
def create_internal_decls ( self , block , signDict ) : if ( not checkIsDict ( signDict ) ) : return ; self . create_wr_reg_sel_decl ( block , signDict ) self . create_addr_vect_decl ( block , signDict ) self . create_read_data_mux_in_decl ( block , signDict ) self . create_read_data_mask_n_decl ( block , signDict ) self . create_write_data_int_decl ( block , signDict ) self . create_read_mux_ena_int_decl ( signDict )
Create declarations of internal signals of architecture of register
memory block.
Create declarations of internal signals of architecture of register memory block .
"""
		Create declarations of internal signals of architecture of register
		memory block. Following declarations are created:
			- Write selector signal for all writable registers
			- Address vector input to address decoder
			- Read data multiplexor input vector.
			- Read data mask signal from byte enable signals
            - Internal signal for output register structure
		""" # Create output of address decoder # Create address vector input to address decoder # Create data mux input signal (long logic vector) # Create data mask signal for read multiplextor # Create internal signal for output register structure (output values # of writable registers) # Create declaration of read data clear signal
self
block
signDict