pgtt/mmu.py
def _tcr() -> str:
    """
    Generate required value for TCR_ELn.
    """
    reg = Register(f"tcr_el{args.el}")

    """
    Configurable bitfields present at all exception levels.
    """
    reg.field( 5,  0, "t0sz", 64-args.tsz)
    reg.field( 9,  8, "irgn0", 1)  # Normal WB RAWA
    reg.field(11, 10, "orgn0", 1)  # Normal WB RAWA
    reg.field(13, 12, "sh0", 3)    # Inner Shareable
    reg.field(15, 14, "tg0", {"4K":0, "16K":2, "64K":1}[args.tg_str])

    """
    Bits that are RES1 at all exception levels.
    """
    reg.res1(23) # technically epd1 at EL1 but we'll want =1 then anyway

    """
    Exception level specific differences.
    """
    ps_val = {32:0, 36:1, 40:2, 48:5}[args.tsz]
    if args.el == 1:
        reg.field(34, 32, "ps", ps_val)
    else:
        reg.field(18, 16, "ps", ps_val)
        reg.res1(31)

    return hex(reg.value()[0])

    Generate required value for TCR_ELn.
    
Generate required value for TCR_ELn.
Generate required value for TCR_ELn .
def _tcr() -> str:
    reg = Register(f"tcr_el{args.el}")
    reg.field( 5,  0, "t0sz", 64-args.tsz)
    reg.field( 9,  8, "irgn0", 1)  
    reg.field(11, 10, "orgn0", 1)  
    reg.field(13, 12, "sh0", 3)    
    reg.field(15, 14, "tg0", {"4K":0, "16K":2, "64K":1}[args.tg_str])
    reg.res1(23) 
    ps_val = {32:0, 36:1, 40:2, 48:5}[args.tsz]
    if args.el == 1:
        reg.field(34, 32, "ps", ps_val)
    else:
        reg.field(18, 16, "ps", ps_val)
        reg.res1(31)
    return hex(reg.value()[0])
def _tcr ( ) -> str : reg = Register ( f"tcr_el{args.el}" ) """
    Configurable bitfields present at all exception levels.
    """ reg . field ( 5 , 0 , "t0sz" , 64 - args . tsz ) reg . field ( 9 , 8 , "irgn0" , 1 ) reg . field ( 11 , 10 , "orgn0" , 1 ) reg . field ( 13 , 12 , "sh0" , 3 ) reg . field ( 15 , 14 , "tg0" , { "4K" : 0 , "16K" : 2 , "64K" : 1 } [ args . tg_str ] ) """
    Bits that are RES1 at all exception levels.
    """ reg . res1 ( 23 ) """
    Exception level specific differences.
    """ ps_val = { 32 : 0 , 36 : 1 , 40 : 2 , 48 : 5 } [ args . tsz ] if args . el == 1 : reg . field ( 34 , 32 , "ps" , ps_val ) else : reg . field ( 18 , 16 , "ps" , ps_val ) reg . res1 ( 31 ) return hex ( reg . value ( ) [ 0 ] )
Generate required value for TCR_ELn.
Generate required value for TCR_ELn .
"""
    Generate required value for TCR_ELn.
    """ """
    Configurable bitfields present at all exception levels.
    """ # Normal WB RAWA # Normal WB RAWA # Inner Shareable """
    Bits that are RES1 at all exception levels.
    """ # technically epd1 at EL1 but we'll want =1 then anyway """
    Exception level specific differences.
    """