ip_xact/vhdl_reg_map_generator.py
def append_reg_byte_val(self, block, reg, byte_ind, read_wrd):
		"""
		Append name of a register if it is located on a given byte within a
		memory word.
		Returns:
			[pad_zeroes, read_wrd]
			pad_zeroes - If zeores should be padded instead of this register
			read_wrd   - Appended value of word value
		"""
		reg_offset = reg.addressOffset % self.wrdWidthByte
		reg_bytes = reg.size / 8

		# Register starts on given byte -> Append it
		if (reg_offset == byte_ind):
			
			# Read-write registers are fed from its own values! All other
			# register types are fed from outside of the module.
			if (self.reg_is_access_type(reg, ["read-write"])):
				appendix = "_out_i."
			else:
				appendix = "_in."

			read_wrd += (block.name + appendix + reg.name).lower()
			if (byte_ind != 0):
				read_wrd += " & "
			return [False, read_wrd]

		# Register contains this byte
		elif (reg_offset <= byte_ind <= reg_offset + reg_bytes - 1):
			return [False, read_wrd]

		return [True, read_wrd]

		Append name of a register if it is located on a given byte within a
		memory word.
		Returns:
			[pad_zeroes, read_wrd]
			pad_zeroes - If zeores should be padded instead of this register
			read_wrd   - Appended value of word value
		
Append name of a register if it is located on a given byte within a
memory word.
Append name of a register if it is located on a given byte within a memory word .
def append_reg_byte_val(self, block, reg, byte_ind, read_wrd):
		reg_offset = reg.addressOffset % self.wrdWidthByte
		reg_bytes = reg.size / 8
		if (reg_offset == byte_ind):
			if (self.reg_is_access_type(reg, ["read-write"])):
				appendix = "_out_i."
			else:
				appendix = "_in."
			read_wrd += (block.name + appendix + reg.name).lower()
			if (byte_ind != 0):
				read_wrd += " & "
			return [False, read_wrd]
		elif (reg_offset <= byte_ind <= reg_offset + reg_bytes - 1):
			return [False, read_wrd]
		return [True, read_wrd]
def append_reg_byte_val ( self , block , reg , byte_ind , read_wrd ) : reg_offset = reg . addressOffset % self . wrdWidthByte reg_bytes = reg . size / 8 if ( reg_offset == byte_ind ) : if ( self . reg_is_access_type ( reg , [ "read-write" ] ) ) : appendix = "_out_i." else : appendix = "_in." read_wrd += ( block . name + appendix + reg . name ) . lower ( ) if ( byte_ind != 0 ) : read_wrd += " & " return [ False , read_wrd ] elif ( reg_offset <= byte_ind <= reg_offset + reg_bytes - 1 ) : return [ False , read_wrd ] return [ True , read_wrd ]
Append name of a register if it is located on a given byte within a
memory word.
Append name of a register if it is located on a given byte within a memory word .
"""
		Append name of a register if it is located on a given byte within a
		memory word.
		Returns:
			[pad_zeroes, read_wrd]
			pad_zeroes - If zeores should be padded instead of this register
			read_wrd   - Appended value of word value
		""" # Register starts on given byte -> Append it # Read-write registers are fed from its own values! All other # register types are fed from outside of the module. # Register contains this byte
[pad_zeroes, read_wrd]
pad_zeroes - If zeores should be padded instead of this register
read_wrd   - Appended value of word value
[ pad_zeroes read_wrd ] pad_zeroes - If zeores should be padded instead of this register read_wrd - Appended value of word value
self
block
reg
byte_ind
read_wrd