ip_xact/vhdl_reg_map_generator.py
def create_write_data_int_decl(self, block, signDict):
		"""
		Create declaration for internal record with data written to writable
		registers.
		"""
		name = block.name + "_out"
		signDict[name + "_i"] = LanDeclaration(name + "_i", value = None)
		signDict[name + "_i"].type = name + "_t"
		signDict[name + "_i"].specifier = "signal"

		Create declaration for internal record with data written to writable
		registers.
		
Create declaration for internal record with data written to writable
registers.
Create declaration for internal record with data written to writable registers .
def create_write_data_int_decl(self, block, signDict):
		name = block.name + "_out"
		signDict[name + "_i"] = LanDeclaration(name + "_i", value = None)
		signDict[name + "_i"].type = name + "_t"
		signDict[name + "_i"].specifier = "signal"
def create_write_data_int_decl ( self , block , signDict ) : name = block . name + "_out" signDict [ name + "_i" ] = LanDeclaration ( name + "_i" , value = None ) signDict [ name + "_i" ] . type = name + "_t" signDict [ name + "_i" ] . specifier = "signal"
Create declaration for internal record with data written to writable
registers.
Create declaration for internal record with data written to writable registers .
"""
		Create declaration for internal record with data written to writable
		registers.
		"""
self
block
signDict