ip_xact/vhdl_reg_map_generator.py
def write_reg_map_pkg(self):
		"""
		Create package with declarations of register map input / output
		records.
		"""
		self.hdlGen.wr_nl()

		self.hdlGen.write_comment("Register map package for: " +
				self.memMap.name, gap = 0)
		self.hdlGen.write_gen_note()
		self.hdlGen.wr_nl()

		if (type(self.hdlGen) == VhdlGenerator):
			self.hdlGen.create_includes("ieee", ["std_logic_1164.all"])
			self.hdlGen.wr_nl()

		self.hdlGen.create_package(self.memMap.name.lower() + "_pkg")

		for block in self.memMap.addressBlock:

			# Skip blocks marked as memory
			if (block.usage == "memory"):
				continue

			self.create_mem_block_records(block)

		self.hdlGen.commit_append_line(1)

		Create package with declarations of register map input / output
		records.
		
Create package with declarations of register map input / output
records.
Create package with declarations of register map input / output records .
def write_reg_map_pkg(self):
		self.hdlGen.wr_nl()
		self.hdlGen.write_comment("Register map package for: " +
				self.memMap.name, gap = 0)
		self.hdlGen.write_gen_note()
		self.hdlGen.wr_nl()
		if (type(self.hdlGen) == VhdlGenerator):
			self.hdlGen.create_includes("ieee", ["std_logic_1164.all"])
			self.hdlGen.wr_nl()
		self.hdlGen.create_package(self.memMap.name.lower() + "_pkg")
		for block in self.memMap.addressBlock:
			if (block.usage == "memory"):
				continue
			self.create_mem_block_records(block)
		self.hdlGen.commit_append_line(1)
def write_reg_map_pkg ( self ) : self . hdlGen . wr_nl ( ) self . hdlGen . write_comment ( "Register map package for: " + self . memMap . name , gap = 0 ) self . hdlGen . write_gen_note ( ) self . hdlGen . wr_nl ( ) if ( type ( self . hdlGen ) == VhdlGenerator ) : self . hdlGen . create_includes ( "ieee" , [ "std_logic_1164.all" ] ) self . hdlGen . wr_nl ( ) self . hdlGen . create_package ( self . memMap . name . lower ( ) + "_pkg" ) for block in self . memMap . addressBlock : if ( block . usage == "memory" ) : continue self . create_mem_block_records ( block ) self . hdlGen . commit_append_line ( 1 )
Create package with declarations of register map input / output
records.
Create package with declarations of register map input / output records .
"""
		Create package with declarations of register map input / output
		records.
		""" # Skip blocks marked as memory
self