languages/gen_vhdl.py
def create_comp_instance(self, decl):
		"""
		Create component instance of VHDL entity, entity declaration, component
		declaration or architecture declaration.
		Arguments:
			decl        Declaration object (VhdlCompDeclaration)
			specDir     If Direction should be specified in the connection
					    in VHDL comment   
		"""
		titleStr = ["generic {}(\n", "port {}(\n"]
		mapSuf = ""
		semicoln = ""
		gstr = " " * decl.gap

		self.__wr_line("\n")

		# Write instance title and name, entity name or component name
		if (decl.intType == "entity"):
			if (decl.isInstance):
				title = decl.value + " : " + decl.name + "\n"
				mapSuf = "map"
			else:
				title = decl.intType + " " + decl.name + " is" + "\n"

		# For architecture, there is no disnitguishing between instance
		# or declaration. "value" now contains entity name!
		elif (decl.intType == "architecture"):
			title = decl.intType + " " + decl.name + " of " + decl.value
			title = title + " is\n"
		else:
			print("Unsupported component type!")
			return

		self.__wr_line(gstr + title)

        # Go through Generics and Ports
		for (i, title) in enumerate(titleStr):
			items = decl.generics if (i == 0) else decl.ports

			# If no generics are defined -> skip them.
			if (len(items) == 0):
				#print("Skipping: " + title)
				continue;

			# Add semicoln for ports in instance, or generic and port of decl.
			if ((i == 1) or (decl.isInstance == False)):
				semicoln = ";"

			# Write "generic/port" and "map". Skip for architecture (no generic
			# nor ports)
			if (decl.intType != "architecture"):
				title = title.format(mapSuf)
				self.__wr_line(gstr + title)
				self.append_line(gstr + ")" + semicoln + "\n")

			# Write ports or generics
			self.write_ports_or_declarations(decl, items, decl.isInstance)

			# Appending final bracket for entities always, for components
			# only with ports!
			if (decl.intType != "architecture"):
				self.commit_append_line(1)

		# After printing declarations of architecture, print "BEGIN"
		if (decl.intType == "architecture"):
			self.__wr_line("begin\n")
			self.append_line("end architecture "+decl.name+";\n")

		# Finalize component / entity. skip for architecture!
		if (decl.isInstance == False and decl.intType != "architecture"):
			endStr = "end {} {};\n".format(decl.intType, decl.name)
			self.__wr_line(endStr)

		self.__wr_line("\n")

		Create component instance of VHDL entity, entity declaration, component
		declaration or architecture declaration.
		Arguments:
			decl        Declaration object (VhdlCompDeclaration)
			specDir     If Direction should be specified in the connection
					    in VHDL comment   
		
Create component instance of VHDL entity, entity declaration, component
declaration or architecture declaration.
Arguments:
decl        Declaration object (VhdlCompDeclaration)
specDir     If Direction should be specified in the connection
in VHDL comment
Create component instance of VHDL entity entity declaration component declaration or architecture declaration . Arguments : decl Declaration object ( VhdlCompDeclaration ) specDir If Direction should be specified in the connection in VHDL comment
def create_comp_instance(self, decl):
		titleStr = ["generic {}(\n", "port {}(\n"]
		mapSuf = ""
		semicoln = ""
		gstr = " " * decl.gap
		self.__wr_line("\n")
		if (decl.intType == "entity"):
			if (decl.isInstance):
				title = decl.value + " : " + decl.name + "\n"
				mapSuf = "map"
			else:
				title = decl.intType + " " + decl.name + " is" + "\n"
		elif (decl.intType == "architecture"):
			title = decl.intType + " " + decl.name + " of " + decl.value
			title = title + " is\n"
		else:
			print("Unsupported component type!")
			return
		self.__wr_line(gstr + title)
		for (i, title) in enumerate(titleStr):
			items = decl.generics if (i == 0) else decl.ports
			if (len(items) == 0):
				continue;
			if ((i == 1) or (decl.isInstance == False)):
				semicoln = ";"
			if (decl.intType != "architecture"):
				title = title.format(mapSuf)
				self.__wr_line(gstr + title)
				self.append_line(gstr + ")" + semicoln + "\n")
			self.write_ports_or_declarations(decl, items, decl.isInstance)
			if (decl.intType != "architecture"):
				self.commit_append_line(1)
		if (decl.intType == "architecture"):
			self.__wr_line("begin\n")
			self.append_line("end architecture "+decl.name+";\n")
		if (decl.isInstance == False and decl.intType != "architecture"):
			endStr = "end {} {};\n".format(decl.intType, decl.name)
			self.__wr_line(endStr)
		self.__wr_line("\n")
def create_comp_instance ( self , decl ) : titleStr = [ "generic {}(\n" , "port {}(\n" ] mapSuf = "" semicoln = "" gstr = " " * decl . gap self . __wr_line ( "\n" ) if ( decl . intType == "entity" ) : if ( decl . isInstance ) : title = decl . value + " : " + decl . name + "\n" mapSuf = "map" else : title = decl . intType + " " + decl . name + " is" + "\n" elif ( decl . intType == "architecture" ) : title = decl . intType + " " + decl . name + " of " + decl . value title = title + " is\n" else : print ( "Unsupported component type!" ) return self . __wr_line ( gstr + title ) for ( i , title ) in enumerate ( titleStr ) : items = decl . generics if ( i == 0 ) else decl . ports if ( len ( items ) == 0 ) : continue ; if ( ( i == 1 ) or ( decl . isInstance == False ) ) : semicoln = ";" if ( decl . intType != "architecture" ) : title = title . format ( mapSuf ) self . __wr_line ( gstr + title ) self . append_line ( gstr + ")" + semicoln + "\n" ) self . write_ports_or_declarations ( decl , items , decl . isInstance ) if ( decl . intType != "architecture" ) : self . commit_append_line ( 1 ) if ( decl . intType == "architecture" ) : self . __wr_line ( "begin\n" ) self . append_line ( "end architecture " + decl . name + ";\n" ) if ( decl . isInstance == False and decl . intType != "architecture" ) : endStr = "end {} {};\n" . format ( decl . intType , decl . name ) self . __wr_line ( endStr ) self . __wr_line ( "\n" )
Create component instance of VHDL entity, entity declaration, component
declaration or architecture declaration.
Create component instance of VHDL entity entity declaration component declaration or architecture declaration .
"""
		Create component instance of VHDL entity, entity declaration, component
		declaration or architecture declaration.
		Arguments:
			decl        Declaration object (VhdlCompDeclaration)
			specDir     If Direction should be specified in the connection
					    in VHDL comment   
		""" # Write instance title and name, entity name or component name # For architecture, there is no disnitguishing between instance # or declaration. "value" now contains entity name! # Go through Generics and Ports # If no generics are defined -> skip them. #print("Skipping: " + title) # Add semicoln for ports in instance, or generic and port of decl. # Write "generic/port" and "map". Skip for architecture (no generic # nor ports) # Write ports or generics # Appending final bracket for entities always, for components # only with ports! # After printing declarations of architecture, print "BEGIN" # Finalize component / entity. skip for architecture!
self
decl