ip_xact/vhdl_reg_map_generator.py
def fill_access_signaller_ports(self, block, reg, signaller_inst):
		"""
		Fill ports for VHDL access signaller instance from IP-XACT register
		object.
		"""
		signaller_inst.ports["clk_sys"].value = "clk_sys"
		signaller_inst.ports["res_n"].value = "res_n"

		# Get word index from address decoder
		reg_sel_index = self.get_wrd_index(block, reg) - 1
		signaller_inst.ports["cs"].value = \
			self.hdlGen.format_vector_index("reg_sel", reg_sel_index)

		# Connect memory bus signals
		signaller_inst.ports["read"].value = "read"
		signaller_inst.ports["write"].value = "write"
		signaller_inst.ports["be"].value = self.calc_reg_byte_enable_vector(reg)

		# Connect write access signalling
		wr_signal = "open"
		if (self.is_reg_write_indicate(reg)):
			wr_signal = (block.name + "_out_i." + reg.name + "_write").lower()			
		signaller_inst.ports["write_signal"].value = wr_signal

		# Connect read access signalling
		rd_signal = "open"
		if (self.is_reg_read_indicate(reg)):
			rd_signal = (block.name + "_out_i." + reg.name + "_read").lower()			
		signaller_inst.ports["read_signal"].value = rd_signal

		Fill ports for VHDL access signaller instance from IP-XACT register
		object.
		
Fill ports for VHDL access signaller instance from IP-XACT register
object.
Fill ports for VHDL access signaller instance from IP - XACT register object .
def fill_access_signaller_ports(self, block, reg, signaller_inst):
		signaller_inst.ports["clk_sys"].value = "clk_sys"
		signaller_inst.ports["res_n"].value = "res_n"
		reg_sel_index = self.get_wrd_index(block, reg) - 1
		signaller_inst.ports["cs"].value = \
			self.hdlGen.format_vector_index("reg_sel", reg_sel_index)
		signaller_inst.ports["read"].value = "read"
		signaller_inst.ports["write"].value = "write"
		signaller_inst.ports["be"].value = self.calc_reg_byte_enable_vector(reg)
		wr_signal = "open"
		if (self.is_reg_write_indicate(reg)):
			wr_signal = (block.name + "_out_i." + reg.name + "_write").lower()			
		signaller_inst.ports["write_signal"].value = wr_signal
		rd_signal = "open"
		if (self.is_reg_read_indicate(reg)):
			rd_signal = (block.name + "_out_i." + reg.name + "_read").lower()			
		signaller_inst.ports["read_signal"].value = rd_signal
def fill_access_signaller_ports ( self , block , reg , signaller_inst ) : signaller_inst . ports [ "clk_sys" ] . value = "clk_sys" signaller_inst . ports [ "res_n" ] . value = "res_n" reg_sel_index = self . get_wrd_index ( block , reg ) - 1 signaller_inst . ports [ "cs" ] . value = self . hdlGen . format_vector_index ( "reg_sel" , reg_sel_index ) signaller_inst . ports [ "read" ] . value = "read" signaller_inst . ports [ "write" ] . value = "write" signaller_inst . ports [ "be" ] . value = self . calc_reg_byte_enable_vector ( reg ) wr_signal = "open" if ( self . is_reg_write_indicate ( reg ) ) : wr_signal = ( block . name + "_out_i." + reg . name + "_write" ) . lower ( ) signaller_inst . ports [ "write_signal" ] . value = wr_signal rd_signal = "open" if ( self . is_reg_read_indicate ( reg ) ) : rd_signal = ( block . name + "_out_i." + reg . name + "_read" ) . lower ( ) signaller_inst . ports [ "read_signal" ] . value = rd_signal
Fill ports for VHDL access signaller instance from IP-XACT register
object.
Fill ports for VHDL access signaller instance from IP - XACT register object .
"""
		Fill ports for VHDL access signaller instance from IP-XACT register
		object.
		""" # Get word index from address decoder # Connect memory bus signals # Connect write access signalling # Connect read access signalling
self
block
reg
signaller_inst