languages/gen_vhdl.py
def create_gate(self, result, signals, gate, gap=2):
		"""
        Create basic logic function two two signals.
        Arguments:
            result		Name of resulting signal
            signals		List with original signal names
			gate		String with gate function     
        """
		gStr = " " * gap
		line = gStr+result+" <= "+signals[0]+" "+ gate+" "+signals[1]+";\n"
		self.__wr_line(line)

        Create basic logic function two two signals.
        Arguments:
            result		Name of resulting signal
            signals		List with original signal names
			gate		String with gate function     
        
Create basic logic function two two signals.
Arguments:
result              Name of resulting signal
signals             List with original signal names
gate            String with gate function
Create basic logic function two two signals . Arguments : result Name of resulting signal signals List with original signal names gate String with gate function
def create_gate(self, result, signals, gate, gap=2):
		gStr = " " * gap
		line = gStr+result+" <= "+signals[0]+" "+ gate+" "+signals[1]+";\n"
		self.__wr_line(line)
def create_gate ( self , result , signals , gate , gap = 2 ) : gStr = " " * gap line = gStr + result + " <= " + signals [ 0 ] + " " + gate + " " + signals [ 1 ] + ";\n" self . __wr_line ( line )
Create basic logic function two two signals.
Create basic logic function two two signals .
"""
        Create basic logic function two two signals.
        Arguments:
            result		Name of resulting signal
            signals		List with original signal names
			gate		String with gate function     
        """
self
result
signals
gate
gap