ip_xact/vhdl_reg_map_generator.py
def create_read_data_mask_driver(self):
		"""
		Create driver for read data mask signal from byte enable inputs of memory
		bus.
		"""
		self.hdlGen.write_comment("Read data mask - Byte enables", gap = 4)
		self.hdlGen.push_parallel_assignment(signalName = "read_data_mask_n", gap = 4)

		wrd_line = ""
		byte_lst = []
		for byte in range(self.wrdWidthByte - 1, -1, -1):
			be_ind = self.hdlGen.format_vector_index("be", byte)			
			for x in range(0,8):
				byte_lst.append(be_ind)
				byte_lst[-1] += " "
				if (x == 0):
					byte_lst[-1] = "\n      " + byte_lst[-1]

		self.hdlGen.wr_line(self.hdlGen.format_concatenation(byte_lst))
		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")

		Create driver for read data mask signal from byte enable inputs of memory
		bus.
		
Create driver for read data mask signal from byte enable inputs of memory
bus.
Create driver for read data mask signal from byte enable inputs of memory bus .
def create_read_data_mask_driver(self):
		self.hdlGen.write_comment("Read data mask - Byte enables", gap = 4)
		self.hdlGen.push_parallel_assignment(signalName = "read_data_mask_n", gap = 4)
		wrd_line = ""
		byte_lst = []
		for byte in range(self.wrdWidthByte - 1, -1, -1):
			be_ind = self.hdlGen.format_vector_index("be", byte)			
			for x in range(0,8):
				byte_lst.append(be_ind)
				byte_lst[-1] += " "
				if (x == 0):
					byte_lst[-1] = "\n      " + byte_lst[-1]
		self.hdlGen.wr_line(self.hdlGen.format_concatenation(byte_lst))
		self.hdlGen.commit_append_line(1)
		self.hdlGen.wr_line("\n")
def create_read_data_mask_driver ( self ) : self . hdlGen . write_comment ( "Read data mask - Byte enables" , gap = 4 ) self . hdlGen . push_parallel_assignment ( signalName = "read_data_mask_n" , gap = 4 ) wrd_line = "" byte_lst = [ ] for byte in range ( self . wrdWidthByte - 1 , - 1 , - 1 ) : be_ind = self . hdlGen . format_vector_index ( "be" , byte ) for x in range ( 0 , 8 ) : byte_lst . append ( be_ind ) byte_lst [ - 1 ] += " " if ( x == 0 ) : byte_lst [ - 1 ] = "\n      " + byte_lst [ - 1 ] self . hdlGen . wr_line ( self . hdlGen . format_concatenation ( byte_lst ) ) self . hdlGen . commit_append_line ( 1 ) self . hdlGen . wr_line ( "\n" )
Create driver for read data mask signal from byte enable inputs of memory
bus.
Create driver for read data mask signal from byte enable inputs of memory bus .
"""
		Create driver for read data mask signal from byte enable inputs of memory
		bus.
		"""
self