ip_xact/vhdl_reg_map_generator.py
def fill_access_signaller_generics(self, reg, signaller_inst):
		"""
		Fill generics for VHDL access signaller instance from IP-XACT register
		object.
		"""
		signaller_inst.generics["reset_polarity"].value = "reset_polarity".upper()
		signaller_inst.generics["data_width"].value = reg.size

		# Read signalling capability
		if (self.is_reg_read_indicate(reg)):
			signaller_inst.generics["read_signalling"].value = True
		else:
			signaller_inst.generics["read_signalling"].value = False

		# Mark read signalling as combinational value!
		signaller_inst.generics["read_signalling_reg"].value = False

		# Write signalling capability, set signalling as registered to have
		# the signal in the same clock cycle as new data are written to the
		# register!
		if (self.is_reg_write_indicate(reg)):
			signaller_inst.generics["write_signalling"].value = True
			signaller_inst.generics["write_signalling_reg"].value = True
		else:
			signaller_inst.generics["write_signalling"].value = False
			signaller_inst.generics["write_signalling_reg"].value = False

		Fill generics for VHDL access signaller instance from IP-XACT register
		object.
		
Fill generics for VHDL access signaller instance from IP-XACT register
object.
Fill generics for VHDL access signaller instance from IP - XACT register object .
def fill_access_signaller_generics(self, reg, signaller_inst):
		signaller_inst.generics["reset_polarity"].value = "reset_polarity".upper()
		signaller_inst.generics["data_width"].value = reg.size
		if (self.is_reg_read_indicate(reg)):
			signaller_inst.generics["read_signalling"].value = True
		else:
			signaller_inst.generics["read_signalling"].value = False
		signaller_inst.generics["read_signalling_reg"].value = False
		if (self.is_reg_write_indicate(reg)):
			signaller_inst.generics["write_signalling"].value = True
			signaller_inst.generics["write_signalling_reg"].value = True
		else:
			signaller_inst.generics["write_signalling"].value = False
			signaller_inst.generics["write_signalling_reg"].value = False
def fill_access_signaller_generics ( self , reg , signaller_inst ) : signaller_inst . generics [ "reset_polarity" ] . value = "reset_polarity" . upper ( ) signaller_inst . generics [ "data_width" ] . value = reg . size if ( self . is_reg_read_indicate ( reg ) ) : signaller_inst . generics [ "read_signalling" ] . value = True else : signaller_inst . generics [ "read_signalling" ] . value = False signaller_inst . generics [ "read_signalling_reg" ] . value = False if ( self . is_reg_write_indicate ( reg ) ) : signaller_inst . generics [ "write_signalling" ] . value = True signaller_inst . generics [ "write_signalling_reg" ] . value = True else : signaller_inst . generics [ "write_signalling" ] . value = False signaller_inst . generics [ "write_signalling_reg" ] . value = False
Fill generics for VHDL access signaller instance from IP-XACT register
object.
Fill generics for VHDL access signaller instance from IP - XACT register object .
"""
		Fill generics for VHDL access signaller instance from IP-XACT register
		object.
		""" # Read signalling capability # Mark read signalling as combinational value! # Write signalling capability, set signalling as registered to have # the signal in the same clock cycle as new data are written to the # register!
self
reg
signaller_inst