build-tools/newad.py
def generate_mirror(dw, mirror_n):
    '''
    Generates a dpram which mirrors the register values being written into the
    automatically generated addresses.
    dw, aw: data/address width of the ram
    mirror_base:
    mirror_n: A unique identifier for the mirror dpram
    '''
    # HACK: HARD coding clk_prefix to be 'lb'
    cp = 'lb'
    mirror_strobe = 'wire [%d:0] mirror_out_%d;'\
                    'wire mirror_write_%d = %s_write &(`ADDR_HIT_MIRROR);\\\n' %\
                    (dw-1, mirror_n, mirror_n, cp)
    dpram_a = '.clka(%s_clk), .addra(%s_addr[`MIRROR_WIDTH-1:0]), '\
              '.dina(%s_data[%d:0]), .wena(mirror_write_%d)' %\
              (cp, cp, cp, dw-1, mirror_n)
    dpram_b = '.clkb(%s_clk), .addrb(%s_addr[`MIRROR_WIDTH-1:0]), .doutb(mirror_out_%d)' %\
              (cp, cp, mirror_n)
    dpram_def = 'dpram #(.aw(`MIRROR_WIDTH),.dw(%d)) mirror_%d(\\\n\t%s,\\\n\t%s);\\\n' %\
                (dw, mirror_n, dpram_a, dpram_b)
    return mirror_strobe + dpram_def

    Generates a dpram which mirrors the register values being written into the
    automatically generated addresses.
    dw, aw: data/address width of the ram
    mirror_base:
    mirror_n: A unique identifier for the mirror dpram
    
Generates a dpram which mirrors the register values being written into the
automatically generated addresses.
dw, aw: data/address width of the ram
mirror_base:
mirror_n: A unique identifier for the mirror dpram
Generates a dpram which mirrors the register values being written into the automatically generated addresses . dw aw : data / address width of the ram mirror_base : mirror_n : A unique identifier for the mirror dpram
def generate_mirror(dw, mirror_n):
    cp = 'lb'
    mirror_strobe = 'wire [%d:0] mirror_out_%d;'\
                    'wire mirror_write_%d = %s_write &(`ADDR_HIT_MIRROR);\\\n' %\
                    (dw-1, mirror_n, mirror_n, cp)
    dpram_a = '.clka(%s_clk), .addra(%s_addr[`MIRROR_WIDTH-1:0]), '\
              '.dina(%s_data[%d:0]), .wena(mirror_write_%d)' %\
              (cp, cp, cp, dw-1, mirror_n)
    dpram_b = '.clkb(%s_clk), .addrb(%s_addr[`MIRROR_WIDTH-1:0]), .doutb(mirror_out_%d)' %\
              (cp, cp, mirror_n)
    dpram_def = 'dpram #(.aw(`MIRROR_WIDTH),.dw(%d)) mirror_%d(\\\n\t%s,\\\n\t%s);\\\n' %\
                (dw, mirror_n, dpram_a, dpram_b)
    return mirror_strobe + dpram_def
def generate_mirror ( dw , mirror_n ) : cp = 'lb' mirror_strobe = 'wire [%d:0] mirror_out_%d;' 'wire mirror_write_%d = %s_write &(`ADDR_HIT_MIRROR);\\\n' % ( dw - 1 , mirror_n , mirror_n , cp ) dpram_a = '.clka(%s_clk), .addra(%s_addr[`MIRROR_WIDTH-1:0]), ' '.dina(%s_data[%d:0]), .wena(mirror_write_%d)' % ( cp , cp , cp , dw - 1 , mirror_n ) dpram_b = '.clkb(%s_clk), .addrb(%s_addr[`MIRROR_WIDTH-1:0]), .doutb(mirror_out_%d)' % ( cp , cp , mirror_n ) dpram_def = 'dpram #(.aw(`MIRROR_WIDTH),.dw(%d)) mirror_%d(\\\n\t%s,\\\n\t%s);\\\n' % ( dw , mirror_n , dpram_a , dpram_b ) return mirror_strobe + dpram_def
Generates a dpram which mirrors the register values being written into the
automatically generated addresses.
Generates a dpram which mirrors the register values being written into the automatically generated addresses .
'''
    Generates a dpram which mirrors the register values being written into the
    automatically generated addresses.
    dw, aw: data/address width of the ram
    mirror_base:
    mirror_n: A unique identifier for the mirror dpram
    ''' # HACK: HARD coding clk_prefix to be 'lb'
dw
mirror_n