rtl/execute.py
def ExecuteStage():
    """The execute stage for Geode.

    This stage contains the primary ALU for Geode. It takes in register values
    produced in the previous stage (or forwarded values when necessary) to
    perform operations on.

    Additionally, it produces the branch target for branch instructions.
    """

    io = Io({
        'id_ex': Input(id_ex_bundle),
        'fwd1_select': Input(Bits(forward.fwd.bitwidth)),
        'fwd2_select': Input(Bits(forward.fwd.bitwidth)),
        'fwd_mem_data': Input(Bits(C['core-width'])),
        'fwd_wb_data': Input(Bits(C['core-width'])),
        'ex_mem': Output(ex_mem_bundle)
    })

    io.ex_mem.mem_ctrl <<= io.id_ex.mem_ctrl
    io.ex_mem.wb_ctrl <<= io.id_ex.wb_ctrl
    io.ex_mem.inst_data <<= io.id_ex.inst_data

    alu = Instance(ArithmeticLogicUnit())

    #
    # Branch Target Generation
    #

    io.ex_mem.branch_target <<= io.id_ex.inst_data.pc + io.id_ex.imm

    #
    # Forwarding Logic
    #

    rs1_fwd = Wire(Bits(C['core-width']))
    rs2_fwd = Wire(Bits(C['core-width']))

    rs1_fwd <<= io.id_ex.rs1_data

    with io.fwd1_select == forward.fwd.mem:
        rs1_fwd <<= io.fwd_mem_data

    with io.fwd1_select == forward.fwd.wb:
        rs1_fwd <<= io.fwd_wb_data

    rs2_fwd <<= io.id_ex.rs1_data

    with io.fwd2_select == forward.fwd.mem:
        rs2_fwd <<= io.fwd_mem_data

    with io.fwd2_select == forward.fwd.wb:
        rs2_fwd <<= io.fwd_wb_data

    #
    # ALU Source Selection
    #

    alu.op0 <<= rs1_fwd

    with io.id_ex.ex_ctrl.alu_src == AluSrc.RS2:
        alu.op1 <<= rs2_fwd
    with otherwise:
        alu.op1 <<= io.id_ex.imm

    #
    # ALU Instruction Selection
    #

    AluControl(
        alu.alu_inst,
        io.id_ex.ex_ctrl.alu_op,
        io.id_ex.ex_ctrl.funct7,
        io.id_ex.ex_ctrl.funct3)

    #
    # Data Output Connections
    #

    io.ex_mem.rs2_data <<= io.id_ex.rs2_data
    io.ex_mem.alu_result <<= alu.result
    io.ex_mem.alu_flags <<= alu.flags

    NameSignals(locals())
The execute stage for Geode.

    This stage contains the primary ALU for Geode. It takes in register values
    produced in the previous stage (or forwarded values when necessary) to
    perform operations on.

    Additionally, it produces the branch target for branch instructions.
    
The execute stage for Geode.
This stage contains the primary ALU for Geode. It takes in register values
produced in the previous stage (or forwarded values when necessary) to
perform operations on.

Additionally, it produces the branch target for branch instructions.
The execute stage for Geode . This stage contains the primary ALU for Geode . It takes in register values produced in the previous stage ( or forwarded values when necessary ) to perform operations on . Additionally it produces the branch target for branch instructions .
def ExecuteStage():
    io = Io({
        'id_ex': Input(id_ex_bundle),
        'fwd1_select': Input(Bits(forward.fwd.bitwidth)),
        'fwd2_select': Input(Bits(forward.fwd.bitwidth)),
        'fwd_mem_data': Input(Bits(C['core-width'])),
        'fwd_wb_data': Input(Bits(C['core-width'])),
        'ex_mem': Output(ex_mem_bundle)
    })
    io.ex_mem.mem_ctrl <<= io.id_ex.mem_ctrl
    io.ex_mem.wb_ctrl <<= io.id_ex.wb_ctrl
    io.ex_mem.inst_data <<= io.id_ex.inst_data
    alu = Instance(ArithmeticLogicUnit())
     Branch Target Generation
    io.ex_mem.branch_target <<= io.id_ex.inst_data.pc + io.id_ex.imm
     Forwarding Logic
    rs1_fwd = Wire(Bits(C['core-width']))
    rs2_fwd = Wire(Bits(C['core-width']))
    rs1_fwd <<= io.id_ex.rs1_data
    with io.fwd1_select == forward.fwd.mem:
        rs1_fwd <<= io.fwd_mem_data
    with io.fwd1_select == forward.fwd.wb:
        rs1_fwd <<= io.fwd_wb_data
    rs2_fwd <<= io.id_ex.rs1_data
    with io.fwd2_select == forward.fwd.mem:
        rs2_fwd <<= io.fwd_mem_data
    with io.fwd2_select == forward.fwd.wb:
        rs2_fwd <<= io.fwd_wb_data
     ALU Source Selection
    alu.op0 <<= rs1_fwd
    with io.id_ex.ex_ctrl.alu_src == AluSrc.RS2:
        alu.op1 <<= rs2_fwd
    with otherwise:
        alu.op1 <<= io.id_ex.imm
     ALU Instruction Selection
    AluControl(
        alu.alu_inst,
        io.id_ex.ex_ctrl.alu_op,
        io.id_ex.ex_ctrl.funct7,
        io.id_ex.ex_ctrl.funct3)
     Data Output Connections
    io.ex_mem.rs2_data <<= io.id_ex.rs2_data
    io.ex_mem.alu_result <<= alu.result
    io.ex_mem.alu_flags <<= alu.flags
    NameSignals(locals())
def ExecuteStage ( ) : io = Io ( { 'id_ex' : Input ( id_ex_bundle ) , 'fwd1_select' : Input ( Bits ( forward . fwd . bitwidth ) ) , 'fwd2_select' : Input ( Bits ( forward . fwd . bitwidth ) ) , 'fwd_mem_data' : Input ( Bits ( C [ 'core-width' ] ) ) , 'fwd_wb_data' : Input ( Bits ( C [ 'core-width' ] ) ) , 'ex_mem' : Output ( ex_mem_bundle ) } ) io . ex_mem . mem_ctrl <<= io . id_ex . mem_ctrl io . ex_mem . wb_ctrl <<= io . id_ex . wb_ctrl io . ex_mem . inst_data <<= io . id_ex . inst_data alu = Instance ( ArithmeticLogicUnit ( ) ) io . ex_mem . branch_target <<= io . id_ex . inst_data . pc + io . id_ex . imm rs1_fwd = Wire ( Bits ( C [ 'core-width' ] ) ) rs2_fwd = Wire ( Bits ( C [ 'core-width' ] ) ) rs1_fwd <<= io . id_ex . rs1_data with io . fwd1_select == forward . fwd . mem : rs1_fwd <<= io . fwd_mem_data with io . fwd1_select == forward . fwd . wb : rs1_fwd <<= io . fwd_wb_data rs2_fwd <<= io . id_ex . rs1_data with io . fwd2_select == forward . fwd . mem : rs2_fwd <<= io . fwd_mem_data with io . fwd2_select == forward . fwd . wb : rs2_fwd <<= io . fwd_wb_data alu . op0 <<= rs1_fwd with io . id_ex . ex_ctrl . alu_src == AluSrc . RS2 : alu . op1 <<= rs2_fwd with otherwise : alu . op1 <<= io . id_ex . imm AluControl ( alu . alu_inst , io . id_ex . ex_ctrl . alu_op , io . id_ex . ex_ctrl . funct7 , io . id_ex . ex_ctrl . funct3 ) io . ex_mem . rs2_data <<= io . id_ex . rs2_data io . ex_mem . alu_result <<= alu . result io . ex_mem . alu_flags <<= alu . flags NameSignals ( locals ( ) )
The execute stage for Geode.
The execute stage for Geode .
"""The execute stage for Geode.

    This stage contains the primary ALU for Geode. It takes in register values
    produced in the previous stage (or forwarded values when necessary) to
    perform operations on.

    Additionally, it produces the branch target for branch instructions.
    """ # # Branch Target Generation # # # Forwarding Logic # # # ALU Source Selection # # # ALU Instruction Selection # # # Data Output Connections #