rtl/forward.py
def ForwardReg(rs, mem_reg_write, mem_rd, wb_reg_write, wb_rd, fwd_select):
    """Forward logic for a source register."""

    fwd_select <<= fwd.none

    #
    # Detect whether the mem or wb stages are producing a new value for the
    # source register specified by "rs".
    #

    mem_match = mem_reg_write & (mem_rd != 0) & (mem_rd == rs)
    wb_match = wb_reg_write & (wb_rd != 0) & (wb_rd == rs)

    #
    # The logic here is carefully crafted. A match with mem_stage needs to take
    # precedence over a match with the writeback stage to ensure the most
    # recent version of the register's value.
    #

    with mem_match:
        fwd_select <<= fwd.mem

    with otherwise:
        with wb_match:
            fwd_select <<= fwd.wb
Forward logic for a source register.
Forward logic for a source register.
Forward logic for a source register .
def ForwardReg(rs, mem_reg_write, mem_rd, wb_reg_write, wb_rd, fwd_select):
    fwd_select <<= fwd.none
     Detect whether the mem or wb stages are producing a new value for the
     source register specified by "rs".
    mem_match = mem_reg_write & (mem_rd != 0) & (mem_rd == rs)
    wb_match = wb_reg_write & (wb_rd != 0) & (wb_rd == rs)
     The logic here is carefully crafted. A match with mem_stage needs to take
     precedence over a match with the writeback stage to ensure the most
     recent version of the register's value.
    with mem_match:
        fwd_select <<= fwd.mem
    with otherwise:
        with wb_match:
            fwd_select <<= fwd.wb
def ForwardReg ( rs , mem_reg_write , mem_rd , wb_reg_write , wb_rd , fwd_select ) : fwd_select <<= fwd . none mem_match = mem_reg_write & ( mem_rd != 0 ) & ( mem_rd == rs ) wb_match = wb_reg_write & ( wb_rd != 0 ) & ( wb_rd == rs ) with mem_match : fwd_select <<= fwd . mem with otherwise : with wb_match : fwd_select <<= fwd . wb
Forward logic for a source register.
Forward logic for a source register .
"""Forward logic for a source register.""" # # Detect whether the mem or wb stages are producing a new value for the # source register specified by "rs". # # # The logic here is carefully crafted. A match with mem_stage needs to take # precedence over a match with the writeback stage to ensure the most # recent version of the register's value. #
rs
mem_reg_write
mem_rd
wb_reg_write
wb_rd
fwd_select