pyOCD/coresight/cortex_m.py
def writeCoreRegistersRaw(self, reg_list, data_list):
        """
        Write one or more core registers

        Write core registers in reg_list with the associated value in
        data_list.  If any register in reg_list is a string, find the number
        associated to this register in the lookup table CORE_REGISTER.
        """
        assert len(reg_list) == len(data_list)
        # convert to index only
        reg_list = [register_name_to_index(reg) for reg in reg_list]

        # Sanity check register values
        for reg in reg_list:
            if reg not in CORE_REGISTER.values():
                raise ValueError("unknown reg: %d" % reg)
            elif ((reg >= 0x40) or (reg == 33)) and (not self.has_fpu):
                raise ValueError("attempt to write FPU register without FPU")

        # Read special register if it is present in the list
        for reg in reg_list:
            if (reg < 0) and (reg >= -4):
                specialRegValue = self.readCoreRegister(CORE_REGISTER['cfbp'])
                break

        # Write out registers
        dhcsr_cb_list = []
        for reg, data in zip(reg_list, data_list):
            if (reg < 0) and (reg >= -4):
                # Mask in the new special register value so we don't modify the other register
                # values that share the same DCRSR number.
                shift = (-reg - 1) * 8
                mask = 0xffffffff ^ (0xff << shift)
                data = (specialRegValue & mask) | ((data & 0xff) << shift)
                specialRegValue = data # update special register for other writes that might be in the list
                reg = CORE_REGISTER['cfbp']

            # write DCRDR
            self.writeMemory(CortexM.DCRDR, data)

            # write id in DCRSR and flag to start write transfer
            self.writeMemory(CortexM.DCRSR, reg | CortexM.DCRSR_REGWnR)

            # Technically, we need to poll S_REGRDY in DHCSR here to ensure the
            # register write has completed.
            # Read it and assert that S_REGRDY is set
            dhcsr_cb = self.readMemory(CortexM.DHCSR, now=False)
            dhcsr_cb_list.append(dhcsr_cb)

        # Make sure S_REGRDY was set for all register
        # writes
        for dhcsr_cb in dhcsr_cb_list:
            dhcsr_val = dhcsr_cb()
            assert dhcsr_val & CortexM.S_REGRDY

        Write one or more core registers

        Write core registers in reg_list with the associated value in
        data_list.  If any register in reg_list is a string, find the number
        associated to this register in the lookup table CORE_REGISTER.
        
Write one or more core registers
Write core registers in reg_list with the associated value in
data_list.  If any register in reg_list is a string, find the number
associated to this register in the lookup table CORE_REGISTER.
Write one or more core registers Write core registers in reg_list with the associated value in data_list . If any register in reg_list is a string find the number associated to this register in the lookup table CORE_REGISTER .
def writeCoreRegistersRaw(self, reg_list, data_list):
        assert len(reg_list) == len(data_list)
        reg_list = [register_name_to_index(reg) for reg in reg_list]
        for reg in reg_list:
            if reg not in CORE_REGISTER.values():
                raise ValueError("unknown reg: %d" % reg)
            elif ((reg >= 0x40) or (reg == 33)) and (not self.has_fpu):
                raise ValueError("attempt to write FPU register without FPU")
        for reg in reg_list:
            if (reg < 0) and (reg >= -4):
                specialRegValue = self.readCoreRegister(CORE_REGISTER['cfbp'])
                break
        dhcsr_cb_list = []
        for reg, data in zip(reg_list, data_list):
            if (reg < 0) and (reg >= -4):
                shift = (-reg - 1) * 8
                mask = 0xffffffff ^ (0xff << shift)
                data = (specialRegValue & mask) | ((data & 0xff) << shift)
                specialRegValue = data 
                reg = CORE_REGISTER['cfbp']
            self.writeMemory(CortexM.DCRDR, data)
            self.writeMemory(CortexM.DCRSR, reg | CortexM.DCRSR_REGWnR)
            dhcsr_cb = self.readMemory(CortexM.DHCSR, now=False)
            dhcsr_cb_list.append(dhcsr_cb)
        for dhcsr_cb in dhcsr_cb_list:
            dhcsr_val = dhcsr_cb()
            assert dhcsr_val & CortexM.S_REGRDY
def writeCoreRegistersRaw ( self , reg_list , data_list ) : assert len ( reg_list ) == len ( data_list ) reg_list = [ register_name_to_index ( reg ) for reg in reg_list ] for reg in reg_list : if reg not in CORE_REGISTER . values ( ) : raise ValueError ( "unknown reg: %d" % reg ) elif ( ( reg >= 0x40 ) or ( reg == 33 ) ) and ( not self . has_fpu ) : raise ValueError ( "attempt to write FPU register without FPU" ) for reg in reg_list : if ( reg < 0 ) and ( reg >= - 4 ) : specialRegValue = self . readCoreRegister ( CORE_REGISTER [ 'cfbp' ] ) break dhcsr_cb_list = [ ] for reg , data in zip ( reg_list , data_list ) : if ( reg < 0 ) and ( reg >= - 4 ) : shift = ( - reg - 1 ) * 8 mask = 0xffffffff ^ ( 0xff << shift ) data = ( specialRegValue & mask ) | ( ( data & 0xff ) << shift ) specialRegValue = data reg = CORE_REGISTER [ 'cfbp' ] self . writeMemory ( CortexM . DCRDR , data ) self . writeMemory ( CortexM . DCRSR , reg | CortexM . DCRSR_REGWnR ) dhcsr_cb = self . readMemory ( CortexM . DHCSR , now = False ) dhcsr_cb_list . append ( dhcsr_cb ) for dhcsr_cb in dhcsr_cb_list : dhcsr_val = dhcsr_cb ( ) assert dhcsr_val & CortexM . S_REGRDY
Write one or more core registers
Write core registers in reg_list with the associated value in
data_list.
Write one or more core registers Write core registers in reg_list with the associated value in data_list .
"""
        Write one or more core registers

        Write core registers in reg_list with the associated value in
        data_list.  If any register in reg_list is a string, find the number
        associated to this register in the lookup table CORE_REGISTER.
        """ # convert to index only # Sanity check register values # Read special register if it is present in the list # Write out registers # Mask in the new special register value so we don't modify the other register # values that share the same DCRSR number. # update special register for other writes that might be in the list # write DCRDR # write id in DCRSR and flag to start write transfer # Technically, we need to poll S_REGRDY in DHCSR here to ensure the # register write has completed. # Read it and assert that S_REGRDY is set # Make sure S_REGRDY was set for all register # writes
self
reg_list
data_list