pyOCD/coresight/cortex_m.py
def step(self, disable_interrupts=True):
        """
        perform an instruction level step.  This function preserves the previous
        interrupt mask state
        """
        # Was 'if self.getState() != TARGET_HALTED:'
        # but now value of dhcsr is saved
        dhcsr = self.readMemory(CortexM.DHCSR)
        if not (dhcsr & (CortexM.C_STEP | CortexM.C_HALT)):
            logging.error('cannot step: target not halted')
            return

        self.notify(Notification(event=Target.EVENT_PRE_RUN, source=self, data=Target.RUN_TYPE_STEP))

        self.clearDebugCauseBits()

        # Save previous interrupt mask state
        interrupts_masked = (CortexM.C_MASKINTS & dhcsr) != 0

        # Mask interrupts - C_HALT must be set when changing to C_MASKINTS
        if not interrupts_masked and disable_interrupts:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_HALT | CortexM.C_MASKINTS)

        # Single step using current C_MASKINTS setting
        if disable_interrupts or interrupts_masked:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_MASKINTS | CortexM.C_STEP)
        else:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_STEP)

        # Wait for halt to auto set (This should be done before the first read)
        while not self.readMemory(CortexM.DHCSR) & CortexM.C_HALT:
            pass

        # Restore interrupt mask state
        if not interrupts_masked and disable_interrupts:
            # Unmask interrupts - C_HALT must be set when changing to C_MASKINTS
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_HALT)

        self.dp.flush()

        self._run_token += 1

        self.notify(Notification(event=Target.EVENT_POST_RUN, source=self, data=Target.RUN_TYPE_STEP))

        perform an instruction level step.  This function preserves the previous
        interrupt mask state
        
perform an instruction level step.  This function preserves the previous
interrupt mask state
perform an instruction level step . This function preserves the previous interrupt mask state
def step(self, disable_interrupts=True):
        dhcsr = self.readMemory(CortexM.DHCSR)
        if not (dhcsr & (CortexM.C_STEP | CortexM.C_HALT)):
            logging.error('cannot step: target not halted')
            return
        self.notify(Notification(event=Target.EVENT_PRE_RUN, source=self, data=Target.RUN_TYPE_STEP))
        self.clearDebugCauseBits()
        interrupts_masked = (CortexM.C_MASKINTS & dhcsr) != 0
        if not interrupts_masked and disable_interrupts:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_HALT | CortexM.C_MASKINTS)
        if disable_interrupts or interrupts_masked:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_MASKINTS | CortexM.C_STEP)
        else:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_STEP)
        while not self.readMemory(CortexM.DHCSR) & CortexM.C_HALT:
            pass
        if not interrupts_masked and disable_interrupts:
            self.writeMemory(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN | CortexM.C_HALT)
        self.dp.flush()
        self._run_token += 1
        self.notify(Notification(event=Target.EVENT_POST_RUN, source=self, data=Target.RUN_TYPE_STEP))
def step ( self , disable_interrupts = True ) : dhcsr = self . readMemory ( CortexM . DHCSR ) if not ( dhcsr & ( CortexM . C_STEP | CortexM . C_HALT ) ) : logging . error ( 'cannot step: target not halted' ) return self . notify ( Notification ( event = Target . EVENT_PRE_RUN , source = self , data = Target . RUN_TYPE_STEP ) ) self . clearDebugCauseBits ( ) interrupts_masked = ( CortexM . C_MASKINTS & dhcsr ) != 0 if not interrupts_masked and disable_interrupts : self . writeMemory ( CortexM . DHCSR , CortexM . DBGKEY | CortexM . C_DEBUGEN | CortexM . C_HALT | CortexM . C_MASKINTS ) if disable_interrupts or interrupts_masked : self . writeMemory ( CortexM . DHCSR , CortexM . DBGKEY | CortexM . C_DEBUGEN | CortexM . C_MASKINTS | CortexM . C_STEP ) else : self . writeMemory ( CortexM . DHCSR , CortexM . DBGKEY | CortexM . C_DEBUGEN | CortexM . C_STEP ) while not self . readMemory ( CortexM . DHCSR ) & CortexM . C_HALT : pass if not interrupts_masked and disable_interrupts : self . writeMemory ( CortexM . DHCSR , CortexM . DBGKEY | CortexM . C_DEBUGEN | CortexM . C_HALT ) self . dp . flush ( ) self . _run_token += 1 self . notify ( Notification ( event = Target . EVENT_POST_RUN , source = self , data = Target . RUN_TYPE_STEP ) )
perform an instruction level step.
perform an instruction level step .
"""
        perform an instruction level step.  This function preserves the previous
        interrupt mask state
        """ # Was 'if self.getState() != TARGET_HALTED:' # but now value of dhcsr is saved # Save previous interrupt mask state # Mask interrupts - C_HALT must be set when changing to C_MASKINTS # Single step using current C_MASKINTS setting # Wait for halt to auto set (This should be done before the first read) # Restore interrupt mask state # Unmask interrupts - C_HALT must be set when changing to C_MASKINTS
self
disable_interrupts