rtl/idecode.py
def Control(inst, itype, ex_ctrl, mem_ctrl, wb_ctrl):
    """Primary control logic for Geode."""

    #
    # opcode, funct3 and func7 are computed once here so that duplicate verilog
    # code isn't produced for every loop iteration below.
    #

    opcode = Opcode(inst)
    funct3 = Funct3(inst)
    funct7 = Funct7(inst)

    #
    # Atlas requires all wire signals to be fully initialized or it fails in the
    # emitter. An easy solution is to do a first assignment to a default value,
    # and later assignments will take precedence.
    #

    itype <<= 0

    ex_ctrl.alu_src <<= 0
    ex_ctrl.alu_op <<= 0
    ex_ctrl.funct3 <<= funct3
    ex_ctrl.funct7 <<= funct7

    mem_ctrl.branch <<= 0
    mem_ctrl.mem_write <<= 0
    mem_ctrl.mem_read <<= 0

    wb_ctrl.mem_to_reg <<= 0

    #
    # This part here really shows the power / advantage of Atlas's meta-
    # programming abilities. Each instruction declared above is considered, and
    # a "match" signal is produced. Upon a match, the control signals for that
    # function are assigned to the output of the idecode stage.
    #

    for name in instructions:
        inst_spec = instructions[name]

        #
        # For some instructions, funct3 and funct7 don't need to be matched
        # (and so are marked as Python "None"). For these cases, funct3_match
        # and/or funct7_match are just set to 1 (always true).
        #

        opcode_match = opcode == inst_spec.pattern.opcode

        if inst_spec.pattern.funct3 is None:
            funct3_match = 1
        else:
            funct3_match = funct3 == inst_spec.pattern.funct3

        if inst_spec.pattern.funct7 is None:
            funct7_match = 1
        else:
            funct7_match = funct7 == inst_spec.pattern.funct7

        with opcode_match & funct3_match & funct7_match:
            SetControlSignals(inst_spec, itype, ex_ctrl, mem_ctrl, wb_ctrl)
Primary control logic for Geode.
Primary control logic for Geode.
Primary control logic for Geode .
def Control(inst, itype, ex_ctrl, mem_ctrl, wb_ctrl):
     opcode, funct3 and func7 are computed once here so that duplicate verilog
     code isn't produced for every loop iteration below.
    opcode = Opcode(inst)
    funct3 = Funct3(inst)
    funct7 = Funct7(inst)
     Atlas requires all wire signals to be fully initialized or it fails in the
     emitter. An easy solution is to do a first assignment to a default value,
     and later assignments will take precedence.
    itype <<= 0
    ex_ctrl.alu_src <<= 0
    ex_ctrl.alu_op <<= 0
    ex_ctrl.funct3 <<= funct3
    ex_ctrl.funct7 <<= funct7
    mem_ctrl.branch <<= 0
    mem_ctrl.mem_write <<= 0
    mem_ctrl.mem_read <<= 0
    wb_ctrl.mem_to_reg <<= 0
     This part here really shows the power / advantage of Atlas's meta-
     programming abilities. Each instruction declared above is considered, and
     a "match" signal is produced. Upon a match, the control signals for that
     function are assigned to the output of the idecode stage.
    for name in instructions:
        inst_spec = instructions[name]
         For some instructions, funct3 and funct7 don't need to be matched
         (and so are marked as Python "None"). For these cases, funct3_match
         and/or funct7_match are just set to 1 (always true).
        opcode_match = opcode == inst_spec.pattern.opcode
        if inst_spec.pattern.funct3 is None:
            funct3_match = 1
        else:
            funct3_match = funct3 == inst_spec.pattern.funct3
        if inst_spec.pattern.funct7 is None:
            funct7_match = 1
        else:
            funct7_match = funct7 == inst_spec.pattern.funct7
        with opcode_match & funct3_match & funct7_match:
            SetControlSignals(inst_spec, itype, ex_ctrl, mem_ctrl, wb_ctrl)
def Control ( inst , itype , ex_ctrl , mem_ctrl , wb_ctrl ) : opcode = Opcode ( inst ) funct3 = Funct3 ( inst ) funct7 = Funct7 ( inst ) itype <<= 0 ex_ctrl . alu_src <<= 0 ex_ctrl . alu_op <<= 0 ex_ctrl . funct3 <<= funct3 ex_ctrl . funct7 <<= funct7 mem_ctrl . branch <<= 0 mem_ctrl . mem_write <<= 0 mem_ctrl . mem_read <<= 0 wb_ctrl . mem_to_reg <<= 0 for name in instructions : inst_spec = instructions [ name ] opcode_match = opcode == inst_spec . pattern . opcode if inst_spec . pattern . funct3 is None : funct3_match = 1 else : funct3_match = funct3 == inst_spec . pattern . funct3 if inst_spec . pattern . funct7 is None : funct7_match = 1 else : funct7_match = funct7 == inst_spec . pattern . funct7 with opcode_match & funct3_match & funct7_match : SetControlSignals ( inst_spec , itype , ex_ctrl , mem_ctrl , wb_ctrl )
Primary control logic for Geode.
Primary control logic for Geode .
"""Primary control logic for Geode.""" # # opcode, funct3 and func7 are computed once here so that duplicate verilog # code isn't produced for every loop iteration below. # # # Atlas requires all wire signals to be fully initialized or it fails in the # emitter. An easy solution is to do a first assignment to a default value, # and later assignments will take precedence. # # # This part here really shows the power / advantage of Atlas's meta- # programming abilities. Each instruction declared above is considered, and # a "match" signal is produced. Upon a match, the control signals for that # function are assigned to the output of the idecode stage. # # # For some instructions, funct3 and funct7 don't need to be matched # (and so are marked as Python "None"). For these cases, funct3_match # and/or funct7_match are just set to 1 (always true). #
inst
itype
ex_ctrl
mem_ctrl
wb_ctrl