hardware/espressif/esp32/tools/esptool.py
def _connect_attempt(self, mode='default_reset', esp32r0_delay=False):
        """ A single connection attempt, with esp32r0 workaround options """
        # esp32r0_delay is a workaround for bugs with the most common auto reset
        # circuit and Windows, if the EN pin on the dev board does not have
        # enough capacitance.
        #
        # Newer dev boards shouldn't have this problem (higher value capacitor
        # on the EN pin), and ESP32 revision 1 can't use this workaround as it
        # relies on a silicon bug.
        #
        # Details: https://github.com/espressif/esptool/issues/136
        last_error = None

        # issue reset-to-bootloader:
        # RTS = either CH_PD/EN or nRESET (both active low = chip in reset
        # DTR = GPIO0 (active low = boot to flasher)
        #
        # DTR & RTS are active low signals,
        # ie True = pin @ 0V, False = pin @ VCC.
        if mode != 'no_reset':
            self._port.setDTR(False)  # IO0=HIGH
            self._port.setRTS(True)   # EN=LOW, chip in reset
            time.sleep(0.1)
            if esp32r0_delay:
                # Some chips are more likely to trigger the esp32r0
                # watchdog reset silicon bug if they're held with EN=LOW
                # for a longer period
                time.sleep(1.2)
            self._port.setDTR(True)   # IO0=LOW
            self._port.setRTS(False)  # EN=HIGH, chip out of reset
            if esp32r0_delay:
                # Sleep longer after reset.
                # This workaround only works on revision 0 ESP32 chips,
                # it exploits a silicon bug spurious watchdog reset.
                time.sleep(0.4)  # allow watchdog reset to occur
            time.sleep(0.05)
            self._port.setDTR(False)  # IO0=HIGH, done

        self._port.timeout = 0.1
        for _ in range(5):
            try:
                self.flush_input()
                self._port.flushOutput()
                self.sync()
                self._port.timeout = 5
                return None
            except FatalError as e:
                if esp32r0_delay:
                    print('_', end='')
                else:
                    print('.', end='')
                sys.stdout.flush()
                time.sleep(0.05)
                last_error = e
        return last_error
 A single connection attempt, with esp32r0 workaround options 
A single connection attempt, with esp32r0 workaround options
A single connection attempt with esp32r0 workaround options
def _connect_attempt(self, mode='default_reset', esp32r0_delay=False):
         Newer dev boards shouldn't have this problem (higher value capacitor
         on the EN pin), and ESP32 revision 1 can't use this workaround as it
         relies on a silicon bug.
         Details: https://github.com/espressif/esptool/issues/136
        last_error = None
         issue reset-to-bootloader:
         RTS = either CH_PD/EN or nRESET (both active low = chip in reset
         DTR = GPIO0 (active low = boot to flasher)
         DTR & RTS are active low signals,
         ie True = pin @ 0V, False = pin @ VCC.
        if mode != 'no_reset':
            self._port.setDTR(False)   IO0=HIGH
            self._port.setRTS(True)    EN=LOW, chip in reset
            time.sleep(0.1)
            if esp32r0_delay:
                 Some chips are more likely to trigger the esp32r0
                 watchdog reset silicon bug if they're held with EN=LOW
                 for a longer period
                time.sleep(1.2)
            self._port.setDTR(True)    IO0=LOW
            self._port.setRTS(False)   EN=HIGH, chip out of reset
            if esp32r0_delay:
                 Sleep longer after reset.
                 This workaround only works on revision 0 ESP32 chips,
                 it exploits a silicon bug spurious watchdog reset.
                time.sleep(0.4)   allow watchdog reset to occur
            time.sleep(0.05)
            self._port.setDTR(False)   IO0=HIGH, done
        self._port.timeout = 0.1
        for _ in range(5):
            try:
                self.flush_input()
                self._port.flushOutput()
                self.sync()
                self._port.timeout = 5
                return None
            except FatalError as e:
                if esp32r0_delay:
                    print('_', end='')
                else:
                    print('.', end='')
                sys.stdout.flush()
                time.sleep(0.05)
                last_error = e
        return last_error
def _connect_attempt ( self , mode = 'default_reset' , esp32r0_delay = False ) : last_error = None if mode != 'no_reset' : self . _port . setDTR ( False ) self . _port . setRTS ( True ) time . sleep ( 0.1 ) if esp32r0_delay : time . sleep ( 1.2 ) self . _port . setDTR ( True ) self . _port . setRTS ( False ) if esp32r0_delay : time . sleep ( 0.4 ) time . sleep ( 0.05 ) self . _port . setDTR ( False ) self . _port . timeout = 0.1 for _ in range ( 5 ) : try : self . flush_input ( ) self . _port . flushOutput ( ) self . sync ( ) self . _port . timeout = 5 return None except FatalError as e : if esp32r0_delay : print ( '_' , end = '' ) else : print ( '.' , end = '' ) sys . stdout . flush ( ) time . sleep ( 0.05 ) last_error = e return last_error
A single connection attempt, with esp32r0 workaround options
A single connection attempt with esp32r0 workaround options
""" A single connection attempt, with esp32r0 workaround options """ # esp32r0_delay is a workaround for bugs with the most common auto reset # circuit and Windows, if the EN pin on the dev board does not have # enough capacitance. # # Newer dev boards shouldn't have this problem (higher value capacitor # on the EN pin), and ESP32 revision 1 can't use this workaround as it # relies on a silicon bug. # # Details: https://github.com/espressif/esptool/issues/136 # issue reset-to-bootloader: # RTS = either CH_PD/EN or nRESET (both active low = chip in reset # DTR = GPIO0 (active low = boot to flasher) # # DTR & RTS are active low signals, # ie True = pin @ 0V, False = pin @ VCC. # IO0=HIGH # EN=LOW, chip in reset # Some chips are more likely to trigger the esp32r0 # watchdog reset silicon bug if they're held with EN=LOW # for a longer period # IO0=LOW # EN=HIGH, chip out of reset # Sleep longer after reset. # This workaround only works on revision 0 ESP32 chips, # it exploits a silicon bug spurious watchdog reset. # allow watchdog reset to occur # IO0=HIGH, done
self
mode
esp32r0_delay